diff --git a/.codecheckignore b/.codecheckignore index 5232c65a58..62e12b56f4 100644 --- a/.codecheckignore +++ b/.codecheckignore @@ -6,6 +6,7 @@ ^connectivity/libraries/ppp ^connectivity/drivers/emac ^connectivity/drivers/mbedtls +^connectivity/drivers/wifi/COMPONENT_WHD ^connectivity/mbedtls ^features/frameworks ^connectivity/lwipstack/lwip diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml new file mode 100644 index 0000000000..f0ac02241e --- /dev/null +++ b/.github/workflows/main.yml @@ -0,0 +1,29 @@ +on: + issues: + types: [ opened, reopened ] + +jobs: + build: + runs-on: ubuntu-latest + + steps: + - name: Checkout repo + uses: actions/checkout@v2 + + - name: Install Python environment + uses: actions/setup-python@v2 + with: + python-version: 3.8 + + - name: Checkout mbed-os-scripts repo (This repo is currently private) + uses: actions/checkout@v2 + with: + repository: ARMmbed/mbed-os-ci-scripts + token: ${{ secrets.ISSUE_TRIAGING_PERMS }} + path: scripts + ref: master + + - name: Run the script + run: | + python -m pip install pygithub + python ./scripts/issue_triaging/__init__.py -i ${{github.event.issue.number}} -r ${{ github.event.repository.name }} -t ${{ secrets.ISSUE_TRIAGING_PERMS }} diff --git a/.gitignore b/.gitignore index deb1de7433..3e907cf52c 100644 --- a/.gitignore +++ b/.gitignore @@ -102,3 +102,5 @@ DELIVERY/ CMakeCache.txt cmake_install.cmake CMakeFiles/ +cmake_build/ +Testing/ diff --git a/.lgtm.yml b/.lgtm.yml new file mode 100644 index 0000000000..b3a7b64d4b --- /dev/null +++ b/.lgtm.yml @@ -0,0 +1,27 @@ +path_classifiers: + docs: + - docs + test: + - "**/TESTS" + - "**/UNITTESTS" + tools: + - tools + +extraction: + cpp: + prepare: + packages: + - ninja-build + - python-pip + after_prepare: + - pip install --user cmake + - ls ~/.local/bin + - export PATH=~/.local/bin:$PATH + - cmake --version + configure: + command: + - cmake -S . -B __build -GNinja -DBUILD_TESTING=ON -DCOVERAGE=OFF -DCMAKE_BUILD_TYPE=Debug + index: + build_command: + - cmake --build __build + - cmake --build __build --target test diff --git a/.travis.yml b/.travis.yml index 5b325995d5..7d9c28e3fa 100644 --- a/.travis.yml +++ b/.travis.yml @@ -39,9 +39,11 @@ addons: - sourceline: 'deb https://apt.kitware.com/ubuntu/ focal main' key_url: 'https://apt.kitware.com/keys/kitware-archive-latest.asc' packages: - - cmake - - ninja-build - - libncursesw5 + - cmake + - ninja-build + - gcovr + - libncursesw5 + - g++-7 matrix: include: @@ -66,9 +68,8 @@ matrix: before_script: - mkdir -p SCANCODE - mkdir -p SCANCODE_NEW_FILES - # Fetch remaining information needed for branch comparison - - git fetch --all --unshallow --tags - - git fetch origin "${TRAVIS_BRANCH}" + # Fetch the base branch to compare against + - git fetch origin "${TRAVIS_BRANCH}" --depth=1 script: # scancode does not support list of files, only one file or directory # we use SCANCODE directory for all changed files (their copies with full tree) @@ -104,6 +105,12 @@ matrix: false; fi + - <<: *basic-vm + name: "UTF-8 Check" + script: + # Make sure we're not introducing any text which is not UTF-8 encoded + - git diff $TRAVIS_BRANCH...HEAD -U0 | ( grep -a '^+' || true ) | ( ! grep -axv '.*' ) + - <<: *basic-vm name: "include check" env: NAME=include_check @@ -128,9 +135,8 @@ matrix: export PATH="${PWD}/bin:${PATH}"; cd - - astyle --version - # Fetch remaining information needed for branch comparison - - git fetch --all --unshallow --tags - - git fetch origin "${TRAVIS_BRANCH}" + # Fetch the base branch to compare against + - git fetch origin "${TRAVIS_BRANCH}" --depth=1 script: - >- git diff --name-only --diff-filter=d FETCH_HEAD..HEAD \ @@ -189,35 +195,6 @@ matrix: find -name "*.s" | tee BUILD/badasm | sed -e "s/^/Bad Assembler file name found: /" && [ ! -s BUILD/badasm ] - - <<: *docs-vm - name: "Frozen tools check" - env: NAME=frozen_tools_check - script: - # Reject any changes to tools that would require a re-release of the - # tools for the online compiler. - - >- - frozen_files=`\ - git diff --name-only --diff-filter=d FETCH_HEAD..HEAD \ - | egrep \ - -e "^tools/build_api*" \ - -e "^tools/config*" \ - -e "^tools/export*" \ - -e "^tools/notifier*" \ - -e "^tools/paths*" \ - -e "^tools/resources*" \ - -e "^tools/targets*" \ - -e "^tools/toolchains*" \ - -e "^tools/utils*" \ - -e "^$"` - if [ -z "$frozen_files" ]; then - echo "Success!"; - else - echo -e "Failure: Frozen files were modified\n$frozen_files"; - echo -e "Please see https://os.mbed.com/blog/entry/Introducing-the-new-Mbed-Tools/" \ - "\nfor why we've frozen the legacy tools."; - false; - fi - ### Python Tests ### - &pytools-vm stage: "Pytest" @@ -273,9 +250,8 @@ matrix: - python -m pip install --upgrade setuptools==40.4.3 - pip install tabulate argparse - pip list --verbose - # Fetch remaining information needed for branch comparison - - git fetch --all --unshallow --tags - - git fetch origin "${TRAVIS_BRANCH}" + # Fetch the base branch to compare against + - git fetch origin "${TRAVIS_BRANCH}" --depth=1 script: - >- git diff --name-only --diff-filter=d FETCH_HEAD..HEAD \ @@ -321,3 +297,57 @@ matrix: - mbedtools configure -p ${ROOT} -t ${TOOLCHAIN} -m ${TARGET_NAME} --mbed-os-path . - cmake -S ${ROOT} -B ${ROOT}/cmake_build/${TARGET_NAME}/${PROFILE}/${TOOLCHAIN}/ -GNinja -DCMAKE_BUILD_TYPE=${PROFILE} - cmake --build ${ROOT}/cmake_build/${TARGET_NAME}/${PROFILE}/${TOOLCHAIN}/ + + ### Mbed OS unittest ### + - &cmake-build-run-unittest + stage: "CMake" + name: "CMake unittest build" + env: NAME=cmake_unittest + install: + # Hide Travis-preinstalled CMake + # The Travis-preinstalled CMake is unfortunately not installed via apt, so we + # can't replace it with an apt-supplied version very easily. Additionally, we + # can't permit the Travis-preinstalled copy to survive, as the Travis default + # path lists the Travis CMake install location ahead of any place where apt + # would install CMake to. Instead of apt removing or upgrading to a new CMake + # version, we must instead delete the Travis copy of CMake. + - sudo rm -rf /usr/local/cmake* + script: + - echo ctest --build-and-test . build --build-generator Ninja --build-options -DBUILD_TESTING=ON -DCMAKE_BUILD_TYPE=Debug -DCOVERAGE=ON -DCMAKE_CXX_COMPILER=g++-7 -DCMAKE_C_COMPILER=gcc-7 --test-command ctest + - ctest --build-and-test . build --build-generator Ninja --build-options -DBUILD_TESTING=ON -DCMAKE_BUILD_TYPE=Debug -DCOVERAGE=ON -DCMAKE_CXX_COMPILER=g++-7 -DCMAKE_C_COMPILER=gcc-7 --test-command ctest + - gcovr --gcov-executable gcov-7 -r . ./build -s -e ".*\.h" --exclude-directories=$TRAVIS_BUILD_DIR/build/UNITTESTS --exclude-directories=$TRAVIS_BUILD_DIR/build/_deps + - ccache -s + + ### Frozen tools check ### + - &frozen-tools-vm + stage: "Frozen tools check" + name: "Frozen tools check" + env: NAME=frozen_tools_check + before_script: + # Fetch the base branch to compare against + - git fetch origin "${TRAVIS_BRANCH}" --depth=1 + script: + # Reject any changes to tools that would require a re-release of the + # tools for the online compiler. + - >- + frozen_files=`\ + git diff --name-only FETCH_HEAD..HEAD \ + | egrep \ + -e "^tools/build_api*" \ + -e "^tools/config*" \ + -e "^tools/export*" \ + -e "^tools/notifier*" \ + -e "^tools/paths*" \ + -e "^tools/resources*" \ + -e "^tools/targets*" \ + -e "^tools/toolchains*" \ + -e "^tools/utils*" \ + -e "^$"` + if [ -z "$frozen_files" ]; then + echo "Success!"; + else + echo -e "Failure: Frozen files were modified\n$frozen_files"; + echo -e "Please see https://os.mbed.com/blog/entry/Introducing-the-new-Mbed-Tools/" \ + "\nfor why we've frozen the legacy tools."; + false; + fi diff --git a/CMakeLists.txt b/CMakeLists.txt index 68c48add1c..f85615fc9c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -5,16 +5,25 @@ cmake_minimum_required(VERSION 3.19.0 FATAL_ERROR) -include(${MBED_CONFIG_PATH}/mbed_config.cmake) -include(mbed_set_linker_script) +if(${CMAKE_CROSSCOMPILING}) + include(${MBED_CONFIG_PATH}/mbed_config.cmake) + include(mbed_set_linker_script) +endif() project(mbed-os) # Add all paths to the list files within Mbed OS -list(APPEND CMAKE_MODULE_PATH +list(APPEND CMAKE_MODULE_PATH "${mbed-os_SOURCE_DIR}/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_LATEST/scripts;${mbed-os_SOURCE_DIR}/targets/TARGET_Cypress/scripts;${mbed-os_SOURCE_DIR}/targets/TARGET_NXP/scripts" ) +option(BUILD_TESTING "Run unit tests only." OFF) + +if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) + include(CTest) + add_subdirectory(UNITTESTS) +endif() + add_library(mbed-core INTERFACE) add_library(mbed-os INTERFACE) @@ -33,88 +42,90 @@ target_link_libraries(mbed-baremetal ) # Validate selected C library type # The C library type selected has to match the library that the target can support -if(${MBED_C_LIB} STREQUAL "small") - if(NOT "small" IN_LIST MBED_TARGET_SUPPORTED_C_LIBS) - if("std" IN_LIST MBED_TARGET_SUPPORTED_C_LIBS) - message(WARNING - "We noticed that target.c_lib is set to `${MBED_C_LIB}`." - " As the ${MBED_TARGET} target does not support a small C library for the ${MBED_TOOLCHAIN} toolchain," - " we are using the standard C library instead." - ) - set(MBED_C_LIB "std" CACHE STRING "") +if(${CMAKE_CROSSCOMPILING}) + if(${MBED_C_LIB} STREQUAL "small") + if(NOT "small" IN_LIST MBED_TARGET_SUPPORTED_C_LIBS) + if("std" IN_LIST MBED_TARGET_SUPPORTED_C_LIBS) + message(WARNING + "We noticed that target.c_lib is set to `${MBED_C_LIB}`." + " As the ${MBED_TARGET} target does not support a small C library for the ${MBED_TOOLCHAIN} toolchain," + " we are using the standard C library instead." + ) + set(MBED_C_LIB "std" CACHE STRING "") + endif() endif() + elseif(NOT ${MBED_C_LIB} IN_LIST MBED_TARGET_SUPPORTED_C_LIBS) + message(FATAL_ERROR + "Invalid `target.c_lib` ('${MBED_C_LIB}') for '${MBED_TARGET}' target." + "\nPossible value(s): ${MBED_TARGET_SUPPORTED_C_LIBS}" + ) endif() -elseif(NOT ${MBED_C_LIB} IN_LIST MBED_TARGET_SUPPORTED_C_LIBS) - message(FATAL_ERROR - "Invalid `target.c_lib` ('${MBED_C_LIB}') for '${MBED_TARGET}' target." - "\nPossible value(s): ${MBED_TARGET_SUPPORTED_C_LIBS}" - ) -endif() -# Validate selected printf library -set(MBED_PRINTF_LIB_TYPES std minimal-printf) -if(NOT ${MBED_PRINTF_LIB} IN_LIST MBED_PRINTF_LIB_TYPES) - message(FATAL_ERROR - "Invalid printf library type '${MBED_PRINTF_LIB}'. Possible values:\n ${MBED_PRINTF_LIB_TYPES}" - ) -endif() + # Validate selected printf library + set(MBED_PRINTF_LIB_TYPES std minimal-printf) + if(NOT ${MBED_PRINTF_LIB} IN_LIST MBED_PRINTF_LIB_TYPES) + message(FATAL_ERROR + "Invalid printf library type '${MBED_PRINTF_LIB}'. Possible values:\n ${MBED_PRINTF_LIB_TYPES}" + ) + endif() -mbed_set_cpu_core_definitions(mbed-core) -if(${MBED_TOOLCHAIN_FILE_USED}) - mbed_set_profile_options(mbed-core ${MBED_TOOLCHAIN}) - mbed_set_c_lib(mbed-core ${MBED_C_LIB}) - mbed_set_printf_lib(mbed-core ${MBED_PRINTF_LIB}) + mbed_set_cpu_core_definitions(mbed-core) + if(${MBED_TOOLCHAIN_FILE_USED}) + mbed_set_profile_options(mbed-core ${MBED_TOOLCHAIN}) + mbed_set_c_lib(mbed-core ${MBED_C_LIB}) + mbed_set_printf_lib(mbed-core ${MBED_PRINTF_LIB}) - target_compile_features(mbed-core - INTERFACE - c_std_11 - cxx_std_14 - ) + target_compile_features(mbed-core + INTERFACE + c_std_11 + cxx_std_14 + ) -endif() + endif() -target_compile_definitions(mbed-core - INTERFACE - ${MBED_TARGET_DEFINITIONS} - ${MBED_CONFIG_DEFINITIONS} -) - -# Add MBED_TEST_MODE for backward compatibility with Greentea tests written for use with Mbed CLI 1 -if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) - target_compile_definitions(${PROJECT_NAME} - PUBLIC - MBED_TEST_MODE - ) -endif() - -# We need to generate a "response file" to pass to the C preprocessor when we preprocess the linker -# script, because of path length limitations on Windows. We set the response file and bind the path -# to a global property here. The MBED_TARGET being built queries this global property when it sets -# the linker script. -# -# We must set this global property before the targets subdirectory is added to the project. This is -# required because the MBED_TARGET depends on the response file. If the path to the response file -# is not defined when the target requests it the config definitions will not be passed to CPP. -# -# TODO: Remove this and find a more idiomatic way of passing compile definitions to CPP without -# using response files or global properties. -mbed_generate_options_for_linker(mbed-core RESPONSE_FILE_PATH) -set_property(GLOBAL PROPERTY COMPILE_DEFS_RESPONSE_FILE ${RESPONSE_FILE_PATH}) - -# Add compile definitions for backward compatibility with the toolchain -# supported. New source files should instead check for __GNUC__ and __clang__ -# for the GCC_ARM and ARM toolchains respectively. -if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") target_compile_definitions(mbed-core INTERFACE - TOOLCHAIN_GCC_ARM - TOOLCHAIN_GCC - ) -elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") - target_compile_definitions(mbed-core - INTERFACE - TOOLCHAIN_ARM + ${MBED_TARGET_DEFINITIONS} + ${MBED_CONFIG_DEFINITIONS} ) + + # Add MBED_TEST_MODE for backward compatibility with Greentea tests written for use with Mbed CLI 1 + if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) + target_compile_definitions(${PROJECT_NAME} + PUBLIC + MBED_TEST_MODE + ) + endif() + + # We need to generate a "response file" to pass to the C preprocessor when we preprocess the linker + # script, because of path length limitations on Windows. We set the response file and bind the path + # to a global property here. The MBED_TARGET being built queries this global property when it sets + # the linker script. + # + # We must set this global property before the targets subdirectory is added to the project. This is + # required because the MBED_TARGET depends on the response file. If the path to the response file + # is not defined when the target requests it the config definitions will not be passed to CPP. + # + # TODO: Remove this and find a more idiomatic way of passing compile definitions to CPP without + # using response files or global properties. + mbed_generate_options_for_linker(mbed-core RESPONSE_FILE_PATH) + set_property(GLOBAL PROPERTY COMPILE_DEFS_RESPONSE_FILE ${RESPONSE_FILE_PATH}) + + # Add compile definitions for backward compatibility with the toolchain + # supported. New source files should instead check for __GNUC__ and __clang__ + # for the GCC_ARM and ARM toolchains respectively. + if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + target_compile_definitions(mbed-core + INTERFACE + TOOLCHAIN_GCC_ARM + TOOLCHAIN_GCC + ) + elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + target_compile_definitions(mbed-core + INTERFACE + TOOLCHAIN_ARM + ) + endif() endif() # Include mbed.h and config from generate folder @@ -136,23 +147,26 @@ add_subdirectory(hal) add_subdirectory(platform) add_subdirectory(rtos) add_subdirectory(targets) +add_subdirectory(storage) +add_subdirectory(events) +add_subdirectory(connectivity) # The directories below contain optional target libraries -add_subdirectory(events EXCLUDE_FROM_ALL) -add_subdirectory(connectivity EXCLUDE_FROM_ALL) -add_subdirectory(storage EXCLUDE_FROM_ALL) add_subdirectory(drivers/device_key EXCLUDE_FROM_ALL) add_subdirectory(drivers/usb EXCLUDE_FROM_ALL) add_subdirectory(features EXCLUDE_FROM_ALL) add_subdirectory(cmsis/CMSIS_5/CMSIS/RTOS2 EXCLUDE_FROM_ALL) add_subdirectory(cmsis/device/rtos EXCLUDE_FROM_ALL) -# Ensure the words that make up the Mbed target name are separated with a hyphen, lowercase, and with the `mbed-` prefix. -string(TOLOWER ${MBED_TARGET} MBED_TARGET_CONVERTED) -string(REPLACE "_" "-" MBED_TARGET_CONVERTED ${MBED_TARGET_CONVERTED}) -string(PREPEND MBED_TARGET_CONVERTED "mbed-") -target_link_libraries(mbed-core INTERFACE ${MBED_TARGET_CONVERTED}) +if(${CMAKE_CROSSCOMPILING}) + # Ensure the words that make up the Mbed target name are separated with a hyphen, lowercase, and with the `mbed-` prefix. + string(TOLOWER ${MBED_TARGET} MBED_TARGET_CONVERTED) + string(REPLACE "_" "-" MBED_TARGET_CONVERTED ${MBED_TARGET_CONVERTED}) + string(PREPEND MBED_TARGET_CONVERTED "mbed-") + + target_link_libraries(mbed-core INTERFACE ${MBED_TARGET_CONVERTED}) +endif() # # Converts output file of `target` to binary file and to Intel HEX file. diff --git a/TESTS/configs/baremetal.json b/TESTS/configs/baremetal.json index 6f02501676..feb06a5cc4 100644 --- a/TESTS/configs/baremetal.json +++ b/TESTS/configs/baremetal.json @@ -18,6 +18,7 @@ "storage_filesystem", "storage_tdb_external", "fat_chan", + "cordio-stm32wb", "lora", "sx1276-lora-driver", "stm32wl-lora-driver", diff --git a/TESTS/configs/mbedtls.json b/TESTS/configs/mbedtls.json new file mode 100644 index 0000000000..46be8a650c --- /dev/null +++ b/TESTS/configs/mbedtls.json @@ -0,0 +1,7 @@ +{ + "macros": [ + "MBEDTLS_SELF_TEST", + "MBEDTLS_TIMING_C", + "MBEDTLS_TIMING_ALT" + ] +} diff --git a/TESTS/integration/net-single/main.cpp b/TESTS/integration/net-single/main.cpp index b0bfc7e645..e636eeb0c4 100644 --- a/TESTS/integration/net-single/main.cpp +++ b/TESTS/integration/net-single/main.cpp @@ -56,15 +56,15 @@ void led_thread() #endif #define MAX_RETRIES 3 -NetworkInterface *interface = NULL; +NetworkInterface *netif = NULL; static control_t setup_network(const size_t call_count) { - interface = NetworkInterface::get_default_instance(); - TEST_ASSERT_NOT_NULL_MESSAGE(interface, "failed to initialize network"); + netif = NetworkInterface::get_default_instance(); + TEST_ASSERT_NOT_NULL_MESSAGE(netif, "failed to initialize network"); nsapi_error_t err = -1; for (int tries = 0; tries < MAX_RETRIES; tries++) { - err = interface->connect(); + err = netif->connect(); if (err == NSAPI_ERROR_OK) { break; } else { @@ -78,34 +78,34 @@ static control_t setup_network(const size_t call_count) static control_t download_128(const size_t call_count) { - download_test(interface, story, sizeof(story), 128); + download_test(netif, story, sizeof(story), 128); return CaseNext; } static control_t download_256(const size_t call_count) { - download_test(interface, story, sizeof(story), 256); + download_test(netif, story, sizeof(story), 256); return CaseNext; } static control_t download_1k(const size_t call_count) { - download_test(interface, story, sizeof(story), 1024); + download_test(netif, story, sizeof(story), 1024); return CaseNext; } static control_t download_2k(const size_t call_count) { - download_test(interface, story, sizeof(story), 2 * 1024); + download_test(netif, story, sizeof(story), 2 * 1024); return CaseNext; } static control_t download_4k(const size_t call_count) { - download_test(interface, story, sizeof(story), 4 * 1024); + download_test(netif, story, sizeof(story), 4 * 1024); return CaseNext; } diff --git a/TESTS/integration/stress-net-fs/main.cpp b/TESTS/integration/stress-net-fs/main.cpp index d017553ec5..148e696c7d 100644 --- a/TESTS/integration/stress-net-fs/main.cpp +++ b/TESTS/integration/stress-net-fs/main.cpp @@ -61,16 +61,16 @@ void led_thread() #endif #define MAX_RETRIES 3 -NetworkInterface *interface = NULL; +NetworkInterface *netif = NULL; static control_t setup_network(const size_t call_count) { - interface = NetworkInterface::get_default_instance(); - TEST_ASSERT_NOT_NULL_MESSAGE(interface, "failed to initialize network"); + netif = NetworkInterface::get_default_instance(); + TEST_ASSERT_NOT_NULL_MESSAGE(netif, "failed to initialize network"); nsapi_error_t err = -1; for (int tries = 0; tries < MAX_RETRIES; tries++) { - err = interface->connect(); + err = netif->connect(); if (err == NSAPI_ERROR_OK) { break; } else { @@ -106,7 +106,7 @@ static uint32_t thread_counter = 0; void download_fn() { uint32_t thread_id = core_util_atomic_incr_u32(&thread_counter, 1); - download_test(interface, story, sizeof(story), 256, thread_id); + download_test(netif, story, sizeof(story), 256, thread_id); } void file_fn(size_t buffer) { diff --git a/UNITTESTS/CMakeLists.txt b/UNITTESTS/CMakeLists.txt index 6aba4ba07f..35e26dbe44 100644 --- a/UNITTESTS/CMakeLists.txt +++ b/UNITTESTS/CMakeLists.txt @@ -1,75 +1,39 @@ -cmake_minimum_required(VERSION 3.0.2) - -set(PROJECT_NAME unittests) -set(LIB_NAME MbedOS) - -project(${PROJECT_NAME}) +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 # Setup c++ standard -macro(use_cxx14) - if (CMAKE_VERSION VERSION_LESS 3.1) - if (CMAKE_CXX_COMPILER_ID STREQUAL "GNU") - set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=gnu++14") - endif() - else() - set(CMAKE_CXX_STANDARD 14) - set(CMAKE_CXX_STANDARD_REQUIRED ON) - endif() -endmacro() - -use_cxx14() +set(CMAKE_CXX_STANDARD 14 CACHE STRING "") +set(CMAKE_CXX_STANDARD_REQUIRED ON CACHE BOOL "") +add_definitions(-DUNITTEST) if (MINGW) - # enable PRIx formatting globally - set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -D__STDC_FORMAT_MACROS") - set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -D__STDC_FORMAT_MACROS") + # enable PRIx formatting globally + add_definitions(-D__STDC_FORMAT_MACROS) endif (MINGW) #################### # GTEST #################### - -# Download and unpack googletest at configure time -configure_file(googletest-CMakeLists.txt.in googletest-download/CMakeLists.txt) -execute_process(COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" . - RESULT_VARIABLE result - WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/googletest-download) -if (result) - message(FATAL_ERROR "CMake failed for google test: ${result}") -endif() -execute_process(COMMAND ${CMAKE_COMMAND} --build . - RESULT_VARIABLE result - WORKING_DIRECTORY ${CMAKE_BINARY_DIR}/googletest-download) -if (result) - message(FATAL_ERROR "Build failed for google test: ${result}") -endif() +include(FetchContent) +# Download and unpack googletest +FetchContent_Declare(googletest + GIT_REPOSITORY https://github.com/google/googletest.git + GIT_TAG master +) +FetchContent_MakeAvailable(googletest) # Prevent overriding the parent project's compiler/linker # settings on Windows set(gtest_force_shared_crt ON CACHE BOOL "" FORCE) -# Add googletest directly to our build. This defines -# the gtest and gtest_main targets. -add_subdirectory(${CMAKE_BINARY_DIR}/googletest-src - ${CMAKE_BINARY_DIR}/googletest-build - EXCLUDE_FROM_ALL) - -# The gtest/gtest_main/gmock/gmock_main targets carry header search path -# dependencies automatically when using CMake 2.8.11 or -# later. -target_include_directories(gmock_main SYSTEM BEFORE INTERFACE - "$" - "$") #################### # TESTING #################### -include(CTest) - set_property(DIRECTORY APPEND PROPERTY ADDITIONAL_MAKE_CLEAN_FILES - "${CMAKE_BINARY_DIR}/Testing" + "${CMAKE_BINARY_DIR}/Testing" ) #################### @@ -78,163 +42,21 @@ set_property(DIRECTORY APPEND PROPERTY ADDITIONAL_MAKE_CLEAN_FILES if (COVERAGE) - if (NOT CMAKE_BUILD_TYPE STREQUAL "Debug") - message(WARNING "Non-debug build may result misleading code coverage results.") - endif() + if (NOT CMAKE_BUILD_TYPE STREQUAL "Debug") + message(WARNING "Non-debug build may result misleading code coverage results.") + endif() - # Append coverage compiler flags - set(COVERAGE_COMPILER_FLAGS "-g -O0 --coverage") - set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${COVERAGE_COMPILER_FLAGS}") - set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${COVERAGE_COMPILER_FLAGS}") + # Append coverage compiler flags + set(COVERAGE_COMPILER_FLAGS "-g -O0 --coverage") + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${COVERAGE_COMPILER_FLAGS}" CACHE STRING "" FORCE) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${COVERAGE_COMPILER_FLAGS}" CACHE STRING "" FORCE) endif(COVERAGE) if (VALGRIND) - find_program(MEMORYCHECK_COMMAND valgrind) + find_program(MEMORYCHECK_COMMAND valgrind) endif(VALGRIND) -#################### -# UNIT TESTS -#################### - -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DUNITTEST") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DUNITTEST") - -# Set include dirs. -set(unittest-includes-base - "${PROJECT_SOURCE_DIR}/target_h" - "${PROJECT_SOURCE_DIR}/../events/tests/UNITTESTS/target_h" - "${PROJECT_SOURCE_DIR}/../events/tests/UNITTESTS/target_h/equeue" - "${PROJECT_SOURCE_DIR}/target_h/platform" - "${PROJECT_SOURCE_DIR}/target_h/platform/cxxsupport" - "${PROJECT_SOURCE_DIR}/target_h/drivers" - "${PROJECT_SOURCE_DIR}/target_h/rtos/include" - "${PROJECT_SOURCE_DIR}/stubs" - "${PROJECT_SOURCE_DIR}/.." - "${PROJECT_SOURCE_DIR}/../features" - "${PROJECT_SOURCE_DIR}/../platform/include" - "${PROJECT_SOURCE_DIR}/../platform/include/platform" - "${PROJECT_SOURCE_DIR}/../platform/mbed-trace/include" - "${PROJECT_SOURCE_DIR}/../storage/filesystem/littlefs/include" - "${PROJECT_SOURCE_DIR}/../storage/filesystem/fat/include" - "${PROJECT_SOURCE_DIR}/../storage/blockdevice/include" - "${PROJECT_SOURCE_DIR}/../storage/filesystem/include" - "${PROJECT_SOURCE_DIR}/../storage/kvstore/include" - "${PROJECT_SOURCE_DIR}/../storage/kvstore/kv_config" - "${PROJECT_SOURCE_DIR}/../storage/kvstore/kv_config/include" - "${PROJECT_SOURCE_DIR}/../storage/kvstore/tdbstore/include" - "${PROJECT_SOURCE_DIR}/../storage/kvstore/filesystemstore/include" - "${PROJECT_SOURCE_DIR}/../storage/kvstore/kvstore_global_api/include" - "${PROJECT_SOURCE_DIR}/../drivers" - "${PROJECT_SOURCE_DIR}/../drivers/include" - "${PROJECT_SOURCE_DIR}/../drivers/include/drivers" - "${PROJECT_SOURCE_DIR}/../drivers/include/drivers/internal" - "${PROJECT_SOURCE_DIR}/../hal" - "${PROJECT_SOURCE_DIR}/../hal/include" - "${PROJECT_SOURCE_DIR}/../events/include" - "${PROJECT_SOURCE_DIR}/../events/include/events/internal" - "${PROJECT_SOURCE_DIR}/../events/source" - "${PROJECT_SOURCE_DIR}/../rtos/include" - "${PROJECT_SOURCE_DIR}/../features/frameworks" - "${PROJECT_SOURCE_DIR}/../connectivity/libraries/nanostack-libservice" - "${PROJECT_SOURCE_DIR}/../connectivity/libraries/nanostack-libservice/mbed-client-libservice" - "${PROJECT_SOURCE_DIR}/../connectivity/netsocket/include" - "${PROJECT_SOURCE_DIR}/../features/filesystem/fat" - "${PROJECT_SOURCE_DIR}/../features/filesystem/fat/ChaN" - "${PROJECT_SOURCE_DIR}/../features/filesystem/bd" - "${PROJECT_SOURCE_DIR}/../features/filesystem/" - "${PROJECT_SOURCE_DIR}/../features/filesystem/littlefs" - "${PROJECT_SOURCE_DIR}/../features/filesystem/littlefs/littlefs" - "${PROJECT_SOURCE_DIR}/../connectivity/cellular/include/cellular/framework/API" - "${PROJECT_SOURCE_DIR}/../connectivity/cellular/include/cellular/framework/AT" - "${PROJECT_SOURCE_DIR}/../connectivity/cellular/include/cellular/framework/device" - "${PROJECT_SOURCE_DIR}/../connectivity/cellular/include/cellular/framework" - "${PROJECT_SOURCE_DIR}/../connectivity/cellular/include/cellular/framework/common" - "${PROJECT_SOURCE_DIR}/../connectivity" - "${PROJECT_SOURCE_DIR}/../connectivity/lorawan/include/lorawan" - "${PROJECT_SOURCE_DIR}/../connectivity/lorawan/lorastack" - "${PROJECT_SOURCE_DIR}/../connectivity/lorawan/lorastack/mac" - "${PROJECT_SOURCE_DIR}/../connectivity/lorawan/lorastack/phy" - "${PROJECT_SOURCE_DIR}/../connectivity/lorawan" - "${PROJECT_SOURCE_DIR}/../connectivity/mbedtls" - "${PROJECT_SOURCE_DIR}/../connectivity/mbedtls/include" -) - -# Create a list for test suites. -set(TEST_SUITES) - -# Get all matched tests. -file(GLOB_RECURSE unittest-file-list - "../unittest.cmake" # matches any ../**/unittest.cmake -) - -if ("${unittest-file-list}" STREQUAL "") - message(FATAL_ERROR "No tests found. Exiting...") -endif() - -# Create unit test targets -foreach(testfile ${unittest-file-list}) - #################### - # DEFINE TARGETS - #################### - - # Init file lists. - set(unittest-includes ${unittest-includes-base}) - set(unittest-sources) - set(unittest-test-sources) - set(unittest-test-flags) - - # Get source files - include("${testfile}") - - get_filename_component(TEST_SUITE_DIR ${testfile} DIRECTORY) - - file(RELATIVE_PATH - TEST_SUITE_NAME # output - "${PROJECT_SOURCE_DIR}/.." # root - ${TEST_SUITE_DIR} #abs dirpath - ) - - string(REGEX REPLACE "/|\\\\" "-" TEST_SUITE_NAME ${TEST_SUITE_NAME}) - - set(TEST_SUITES ${TEST_SUITES} ${TEST_SUITE_NAME}) - - set(LIBS_TO_BE_LINKED gmock_main) - - # Build directories list - set(BUILD_DIRECTORIES) - - if (unittest-sources) - # Create the testable static library. - add_library("${TEST_SUITE_NAME}.${LIB_NAME}" STATIC ${unittest-sources}) - target_include_directories("${TEST_SUITE_NAME}.${LIB_NAME}" PRIVATE - ${unittest-includes}) - target_compile_options("${TEST_SUITE_NAME}.${LIB_NAME}" PRIVATE - ${unittest-test-flags}) - set(LIBS_TO_BE_LINKED ${LIBS_TO_BE_LINKED} "${TEST_SUITE_NAME}.${LIB_NAME}") - - # Append lib build directory to list - list(APPEND BUILD_DIRECTORIES "./CMakeFiles/${TEST_SUITE_NAME}.${LIB_NAME}.dir") - endif(unittest-sources) - - if (unittest-test-sources) - # Create the executable. - add_executable(${TEST_SUITE_NAME} ${unittest-test-sources}) - - target_include_directories(${TEST_SUITE_NAME} PRIVATE - ${unittest-includes}) - target_compile_options(${TEST_SUITE_NAME} PRIVATE - ${unittest-test-flags}) - - # Link the executable with the libraries. - target_link_libraries(${TEST_SUITE_NAME} ${LIBS_TO_BE_LINKED}) - - add_test(NAME "${TEST_SUITE_NAME}" COMMAND ${TEST_SUITE_NAME}) - - # Append test build directory to list - list(APPEND BUILD_DIRECTORIES "./CMakeFiles/${TEST_SUITE_NAME}.dir") - else() - message(WARNING "No test source files found for ${TEST_SUITE_NAME}.\n") - endif(unittest-test-sources) -endforeach(testfile) +add_subdirectory(stubs) +add_subdirectory(fakes) diff --git a/UNITTESTS/README.md b/UNITTESTS/README.md deleted file mode 100644 index 5dd3f04511..0000000000 --- a/UNITTESTS/README.md +++ /dev/null @@ -1,306 +0,0 @@ -## Unit testing - -This document describes how to write and use unit tests for Arm Mbed OS. - -### Introduction - -Unit tests test code in small sections on a host machine. Unlike other testing tools, unit testing doesn't require embedded hardware or need to build a full operating system. Because of this, unit testing can result in faster tests than other tools. Unit testing happens in a build environment where you test each C or C++ class or module in isolation. Build test suites into separate test binaries and stub all access outside to remove dependencies on any specific embedded hardware or software combination. This allows you to complete tests using native compilers on the build machine. - -### Prerequisites - -Please install the following dependencies to use Mbed OS unit testing: - -* GNU toolchains. - * GCC 6 or later. We recommend you use MinGW-W64 on Windows, but any Windows port of the above GCC versions works. Default compilers can be used on Mac OS instead of GCC to shorten build times, but code coverage results can differ. -* CMake 3.0 or newer. -* Python 2.7.x, 3.5 or newer. -* Pip 10.0 or newer. -* Gcovr 4.1 or newer. -* Arm Mbed CLI 1.8.0 or newer. - -Detailed instructions for supported operating systems are below. - -#### Installing dependencies on Debian or Ubuntu - -In a terminal window: - -1. `sudo apt-get -y install build-essential cmake` -1. Install Python and Pip with: - - ``` - sudo apt-get -y install python python-setuptools - sudo easy_install pip - ``` - -1. Install Gcovr and [Mbed CLI](https://os.mbed.com/docs/mbed-os/latest/tools/developing-mbed-cli.html) with `pip install "gcovr>=4.1" mbed-cli`. - -#### Installing dependencies on macOS - -In a terminal window: - -1. Install [Homebrew](https://brew.sh/). -1. Install Xcode Command Line Tools with `xcode-select --install`. -1. Install CMake with: `brew install cmake`. -1. Install Python and Pip: - - ``` - brew install python - sudo easy_install pip - ``` - -1. Install Gcovr and [Mbed CLI](https://os.mbed.com/docs/mbed-os/latest/tools/developing-mbed-cli.html) with `pip install "gcovr>=4.1" mbed-cli`. -1. (Optional) Install GCC with `brew install gcc`. - -#### Installing dependencies on Windows - -In a terminal window: - -1. Download and install MinGW-W64 from [SourceForge](https://sourceforge.net/projects/mingw-w64/files/Toolchains%20targetting%20Win64/Personal%20Builds/mingw-builds/). -1. Download CMake binaries from https://cmake.org/download/, and run the installer. -1. Download Python 2.7 or Python 3 from https://www.python.org/getit/, and run the installer. -1. Add MinGW, CMake and Python into system PATH. -1. Install Gcovr and [Mbed CLI](https://os.mbed.com/docs/mbed-os/latest/tools/developing-mbed-cli.html) with `pip install "gcovr>=4.1" mbed-cli`. - -### Test code structure - -Find unit tests in the Mbed OS repository under the `UNITTESTS` folder. We recommend unit test files use an identical directory path as the file under test. This makes it easier to find unit tests for a particular class or a module. For example, if the file you're testing is `some/example/path/ClassName.cpp`, then all the test files are in the `UNITTESTS/some/example/path/ClassName` directory. Each test suite needs to have its own `unittest.cmake` file for test configuration. - -All the class stubs should be located in the `UNITTESTS/stubs` directory. A single stub class can be used by multiple test suites and should follow the naming convention `ClassName_stub.cpp` for the source file, and `ClassName_stub.h` for the header file. Use the actual header files for the unit tests, and don't stub headers if possible. The stubbed headers reside in the `UNITTESTS/target_h` directory. - -#### Test discovery - -Registering unit tests to run happens automatically, and the test runner handles registration. However, test files do not automatically build. Build unit tests with a separate system that searches for unit tests under the `UNITTESTS` directory. - -For the build system to find and build any test suite automatically, include a unit test configuration file named `unittest.cmake` for each unit test suite. This configuration file lists all the source files required for the test build. - -#### Test names - -The build system automatically generates names of test suites. The name is constructed by taking a relative file path from the UNITTESTS directory to the test directory and replacing path separators with dashes. For example, the test suite name for `some/example/path/ClassName.cpp` is `some-example-path-ClassName`. Suite names are used when deciding which test suites to run. - -### Unit testing with Mbed CLI - -Mbed CLI supports unit tests through the `mbed test --unittests` command. For information on using Mbed CLI, please see the [CLI documentation](https://os.mbed.com/docs/mbed-os/latest/tools/developing-mbed-cli.html). - -### Writing unit tests - -A unit tests suite consists of one or more test cases. The test cases should cover all the functions in a class under test. All the external dependencies are stubbed including the other classes in the same module. Avoid stubbing header files. Finally, analyze code coverage to ensure all code is tested, and no dead code is found. - -Unit tests are written using [Google Test v1.10.0](https://github.com/google/googletest/releases/tag/release-1.10.0). - -Please see the [documentation for Google Test](https://github.com/google/googletest/blob/master/googletest/docs/primer.md) to learn how to write unit tests using its framework. See the [documentation for Google Mock](https://github.com/google/googletest/blob/master/googlemock/docs/Documentation.md) if you want to write and use C++ mock classes instead of stubs. - -#### Test suite configuration - -Create two files in the test directory for each test suite: - -* Unit test source file (`test_ClassName.cpp`). -* Unit test configuration file (`unittest.cmake`). - -List all the required files for the build in the `unittest.cmake` file with paths relative to the `UNITTESTS` folder. Use the following variables to list the source files and include paths: - -* **unittest-includes**: List of header include paths. You can use this to extend or overwrite default paths listed in `UNITTESTS/CMakeLists.txt`. -* **unittest-sources**: List of files under test. -* **unittest-test-sources**: List of test sources and stubs. - -You can also set custom compiler flags and other configurations supported by CMake in `unittest.cmake`. - -#### Example - -With the following steps, you can write a simple unit test. This example creates dummy classes to be tested, creates and configures unit tests for a class and stubs all external dependencies. - -1. Create the following dummy classes in `mbed-os/example`: - - **MyClass.h** - - ``` - #ifndef MYCLASS_H_ - #define MYCLASS_H_ - - namespace example { - - class MyClass { - public: - int myFunction(); - }; - - } - - #endif - ``` - - **MyClass.cpp** - - ``` - #include "MyClass.h" - #include "OtherClass.h" - - namespace example { - - int MyClass::myFunction() { - OtherClass o = OtherClass(); - return o.otherFunction(); - } - - } - ``` - - **OtherClass.h** - - ``` - #ifndef OTHERCLASS_H_ - #define OTHERCLASS_H_ - - namespace example { - - class OtherClass { - public: - int otherFunction(); - }; - - } - - #endif - ``` - - **OtherClass.cpp** - - ``` - #include "OtherClass.h" - - namespace example { - - int OtherClass::otherFunction() { - return 1; - } - - } - ``` - -1. Create a directory for MyClass unit tests in `UNITTESTS/example/MyClass`. -1. Create a configuration file and a source file for MyClass unit tests in `UNITTESTS/example/MyClass`: - - **unittest.cmake** - - ``` - # Add here additional test specific include paths - set(unittest-includes ${unittest-includes} - ../example - ) - - # Add here classes under test - set(unittest-sources - ../example/MyClass.cpp - ) - - # Add here test classes and stubs - set(unittest-test-sources - example/MyClass/test_MyClass.cpp - stubs/OtherClass_stub.cpp - ) - ``` - - **test_MyClass.cpp** - - ``` - #include "gtest/gtest.h" - #include "example/MyClass.h" - - class TestMyClass : public testing::Test { - protected: - example::MyClass *obj; - - virtual void SetUp() - { - obj = new example::MyClass(); - } - - virtual void TearDown() - { - delete obj; - } - }; - - TEST_F(TestMyClass, constructor) - { - EXPECT_TRUE(obj); - } - - TEST_F(TestMyClass, myfunction) - { - EXPECT_EQ(obj->myFunction(), 0); - } - ``` - -1. Stub all external dependencies. Create the following stub in `UNITTESTS/stubs`: - - **OtherClass_stub.cpp** - - ``` - #include "example/OtherClass.h" - - namespace example { - - int OtherClass::otherFunction() { - return 0; - } - - } - ``` - -This example does not use any Mbed OS code, but if your unit tests do, then remember to update header stubs in `UNITTESTS/target_h` and source stubs in `UNITTESTS/stubs` with any missing type or function declarations. - -### Building and running unit tests - -Use Mbed CLI to build and run unit tests. For advanced use, you can run CMake and a Make program directly. - -#### Build tests directly with CMake - -1. Create a build directory `mkdir UNITTESTS/build`. -1. Move to the build directory `cd UNITTESTS/build`. -1. Run CMake using a relative path to `UNITTESTS` folder as the argument. So from `UNITTESTS/build` use `cmake ..`: - * Add `-g [generator]` if generating other than Unix Makefiles such in case of MinGW use `-g "MinGW Makefiles"`. - * Add `-DCMAKE_MAKE_PROGRAM=`, `-DCMAKE_CXX_COMPILER=` and `-DCMAKE_C_COMPILER=` to use a specific Make program and compilers. - * Add `-DCMAKE_BUILD_TYPE=Debug` for a debug build. - * Add `-DCOVERAGE=True` to add coverage compiler flags. - * Add `-Dgtest_disable_pthreads=ON` to run in a single thread. - * See the [CMake manual](https://cmake.org/cmake/help/v3.0/manual/cmake.1.html) for more information. -1. Run a Make program to build tests. - -#### Run tests directly with CTest - -Run a test binary in the build directory to run a unit test suite. To run multiple test suites at once, use the CTest test runner. Run CTest with `ctest`. Add `-v` to get results for each test case. See the [CTest manual](https://cmake.org/cmake/help/v3.0/manual/ctest.1.html) for more information. - -#### Run tests with GUI test runner - -1. Install `gtest-runner` according to the [documentation](https://github.com/nholthaus/gtest-runner). -1. Run `gtest-runner`. -1. Add test executables into the list and run. - -### Debugging - -1. Use Mbed CLI to build a debug build. For advanced use, run CMake directly with `-DCMAKE_BUILD_TYPE=Debug`, and then run a Make program. -1. Run GDB with a test executable as an argument to debug unit tests. -1. Run tests with Valgrind to analyze the test memory profile. - -### Get code coverage - -Use Mbed CLI to generate code coverage reports. For advanced use, follow these steps: - -1. Run CMake with both `-DCMAKE_BUILD_TYPE=Debug` and `-DCOVERAGE=True`. -1. Run a Make program to build the tests. -1. Run the tests. -1. Run Gcovr or any other code coverage tool directly in the build directory. - -### Troubleshooting - -**Problem:** Generic problems with CMake or with the build process. -* **Solution**: Delete the build directory. Make sure that CMake, g++, GCC and a Make program can be found in the path and are correct versions. - -**Problem:** (Windows) Virus protection identifies files generated by CMake as malicious and quarantines the files. -* **Solution**: Restore false-positive files from the quarantine. - -**Problem:** (Windows) Git with shell installation adds sh.exe to the path and then CMake throws an error: sh.exe was found in your PATH. For MinGW make to work correctly, sh.exe must NOT be in your path. -* **Solution**: Remove sh.exe from the system path. - -**Problem:** (Mac OS) CMake compiler check fails on Mac OS Mojave when using GCC-8. -* **Solution**: Make sure gnm (binutils) is not installed. Uninstall binutils with `brew uninstall binutils`. diff --git a/UNITTESTS/empty_baseline/unittest.cmake b/UNITTESTS/empty_baseline/unittest.cmake deleted file mode 100644 index 34aae47f63..0000000000 --- a/UNITTESTS/empty_baseline/unittest.cmake +++ /dev/null @@ -1,57 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-includes ${unittest-includes} - . - .. - ../connectivity/mbedtls/include/mbedtls/ - ../connectivity/mbedtls/platform/inc/ - ../platform/mbed-trace/include/mbed-trace/ -) - -set(unittest-test-sources - empty_baseline/empty_baseline.cpp -) - -set(unittest-test-flags - -DDEVICE_ANALOGIN - -DDEVICE_ANALOGOUT - -DDEVICE_CAN - -DDEVICE_ETHERNET - -DDEVICE_FLASH - -DDEVICE_I2C - -DDEVICE_I2CSLAVE - -DDEVICE_I2C_ASYNCH - -DDEVICE_INTERRUPTIN - -DDEVICE_LPTICKER - -DDEVICE_PORTIN - -DDEVICE_PORTINOUT - -DDEVICE_PORTOUT - -DDEVICE_PWMOUT - -DDEVICE_QSPI - -DDEVICE_SERIAL - -DDEVICE_SERIAL_ASYNCH - -DDEVICE_SERIAL_FC - -DDEVICE_SPI - -DDEVICE_SPISLAVE - -DDEVICE_SPI_ASYNCH - -DCOMPONENT_FLASHIAP - -DMBED_CONF_PLATFORM_CTHUNK_COUNT_MAX=10 - -DMBED_CONF_DATAFLASH_SPI_FREQ=1 - -DMBED_CONF_FLASHIAP_BLOCK_DEVICE_BASE_ADDRESS=0 - -DMBED_CONF_FLASHIAP_BLOCK_DEVICE_SIZE=0 - -DMBED_CONF_QSPIF_QSPI_FREQ=1 - -DMBED_CONF_QSPIF_QSPI_MIN_READ_SIZE=1 - -DMBED_CONF_QSPIF_QSPI_MIN_PROG_SIZE=1 - -DMBED_LFS_READ_SIZE=64 - -DMBED_LFS_PROG_SIZE=64 - -DMBED_LFS_BLOCK_SIZE=512 - -DMBED_LFS_LOOKAHEAD=512 - -DFLASHIAP_APP_ROM_END_ADDR=0x80000 - -DMBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_SIZE=1024 - -DMBED_CONF_STORAGE_TDB_INTERNAL_INTERNAL_BASE_ADDRESS=0x80000 - -DMBED_CONF_STORAGE_STORAGE_TYPE=default - -DMBED_CONF_FAT_CHAN_FF_MAX_SS=4096 -) diff --git a/UNITTESTS/fakes/CMakeLists.txt b/UNITTESTS/fakes/CMakeLists.txt new file mode 100644 index 0000000000..538093dd78 --- /dev/null +++ b/UNITTESTS/fakes/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(events) +add_subdirectory(ble) diff --git a/UNITTESTS/fakes/ble/BLE.cpp b/UNITTESTS/fakes/ble/BLE.cpp new file mode 100644 index 0000000000..57eb53d52b --- /dev/null +++ b/UNITTESTS/fakes/ble/BLE.cpp @@ -0,0 +1,163 @@ +/* mbed Microcontroller Library + * Copyright (c) 2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "ble/BLE.h" +#include "GattServerImpl_mock.h" +#include "GattClientImpl_mock.h" +#include "GapImpl_mock.h" +#include "SecurityManagerImpl_mock.h" +#include "ble/GattClient.h" +#include "ble/GattServer.h" +#include "ble/SecurityManager.h" +#include "ble/Gap.h" +#include "ble_mocks.h" + +namespace ble { + +static GapMock *gap_impl = nullptr; +static GattServerMock *gatt_server_impl = nullptr; +static GattClientMock *gatt_client_impl = nullptr; +static SecurityManagerMock *security_manager_impl = nullptr; + +static Gap *gap = nullptr; +static GattServer *gatt_server = nullptr; +static GattClient *gatt_client = nullptr; +static SecurityManager *security_manager = nullptr; + +GapMock& gap_mock() { + return *ble::gap_impl; +} + +GattServerMock& gatt_server_mock() { + return *ble::gatt_server_impl; +} + +GattClientMock& gatt_client_mock() { + return *ble::gatt_client_impl; +} + +SecurityManagerMock& security_manager_mock() { + return *ble::security_manager_impl; +} + +void init_mocks() { + if (gap_impl) { + /* we are already initialised */ + return; + } + + /* mocks */ + gap_impl = new GapMock(); + gatt_server_impl = new GattServerMock(); + gatt_client_impl = new GattClientMock(); + security_manager_impl = new SecurityManagerMock(); + /* user APIS */ + gap = new Gap(gap_impl); + gatt_server = new GattServer(gatt_server_impl); + gatt_client = new GattClient(gatt_client_impl); + security_manager = new SecurityManager(security_manager_impl); +} + +void delete_mocks() { + delete gap; + delete gap_impl; + delete gatt_server; + delete gatt_server_impl; + delete gatt_client; + delete gatt_client_impl; + delete security_manager; + delete security_manager_impl; + + gap = nullptr; + gap_impl = nullptr; + gatt_server = nullptr; + gatt_server_impl = nullptr; + gatt_client = nullptr; + gatt_client_impl = nullptr; + security_manager = nullptr; + security_manager_impl = nullptr; +} + +class BLEInstanceBase { +}; + +BLE::BLE(ble::BLEInstanceBase &transport) : transport(transport) +{ +} + +BLE& BLE::Instance() +{ + static ble::BLEInstanceBase transport; + static BLE instance(transport); + init_mocks(); + return instance; +} + +ble::Gap &BLE::gap() +{ + init_mocks(); + return *ble::gap; +} + +ble::GattServer &BLE::gattServer() +{ + init_mocks(); + return *ble::gatt_server; +} + +ble::GattClient &BLE::gattClient() +{ + init_mocks(); + return *ble::gatt_client; +} + +ble::SecurityManager &BLE::securityManager() +{ + init_mocks(); + return *ble::security_manager; +} + +const ble::Gap &BLE::gap() const +{ + auto &self = const_cast(*this); + return const_cast(self.gap()); +} + +const ble::GattServer &BLE::gattServer() const +{ + auto &self = const_cast(*this); + return const_cast(self.gattServer()); +} + +const ble::GattClient &BLE::gattClient() const +{ + auto &self = const_cast(*this); + return const_cast(self.gattClient()); +} + +const ble::SecurityManager &BLE::securityManager() const +{ + auto &self = const_cast(*this); + return const_cast(self.securityManager()); +} + +void BLE::processEvents() +{ + +} + +} diff --git a/UNITTESTS/fakes/ble/CMakeLists.txt b/UNITTESTS/fakes/ble/CMakeLists.txt new file mode 100644 index 0000000000..c8fb84935d --- /dev/null +++ b/UNITTESTS/fakes/ble/CMakeLists.txt @@ -0,0 +1,41 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-fakes-ble) + +target_include_directories(mbed-fakes-ble + PUBLIC + ${mbed-os_SOURCE_DIR}/UNITTESTS/fakes/ble/ + ${mbed-os_SOURCE_DIR}/connectivity/FEATURE_BLE/include + ${mbed-os_SOURCE_DIR}/connectivity/FEATURE_BLE/include/ble + ${mbed-os_SOURCE_DIR}/connectivity/FEATURE_BLE/source + PRIVATE + ${gtest_SOURCE_DIR}/include + ${gmock_SOURCE_DIR}/include +) + +target_sources(mbed-fakes-ble + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/FEATURE_BLE/source/gap/AdvertisingDataBuilder.cpp + ${mbed-os_SOURCE_DIR}/connectivity/FEATURE_BLE/source/gap/AdvertisingParameters.cpp + ${mbed-os_SOURCE_DIR}/connectivity/FEATURE_BLE/source/gap/ConnectionParameters.cpp + ${mbed-os_SOURCE_DIR}/connectivity/FEATURE_BLE/source/gatt/DiscoveredCharacteristic.cpp + ${mbed-os_SOURCE_DIR}/connectivity/FEATURE_BLE/source/Gap.cpp + ${mbed-os_SOURCE_DIR}/connectivity/FEATURE_BLE/source/GattClient.cpp + ${mbed-os_SOURCE_DIR}/connectivity/FEATURE_BLE/source/GattServer.cpp + ${mbed-os_SOURCE_DIR}/connectivity/FEATURE_BLE/source/SecurityManager.cpp + ${mbed-os_SOURCE_DIR}/UNITTESTS/fakes/ble/BLE.cpp + ${mbed-os_SOURCE_DIR}/UNITTESTS/fakes/ble/source/GattServerImpl_mock.cpp + ${mbed-os_SOURCE_DIR}/UNITTESTS/fakes/ble/ble_mocks.h + ${mbed-os_SOURCE_DIR}/UNITTESTS/fakes/ble/GapImpl_mock.h + ${mbed-os_SOURCE_DIR}/UNITTESTS/fakes/ble/GattClientImpl_mock.h + ${mbed-os_SOURCE_DIR}/UNITTESTS/fakes/ble/GattServerImpl_mock.h + ${mbed-os_SOURCE_DIR}/UNITTESTS/fakes/ble/SecurityManagerImpl_mock.h +) + +target_link_libraries(mbed-fakes-ble + PRIVATE + mbed-headers + mbed-stubs-headers + gcov +) diff --git a/UNITTESTS/fakes/ble/GapImpl_mock.h b/UNITTESTS/fakes/ble/GapImpl_mock.h new file mode 100644 index 0000000000..b59461da14 --- /dev/null +++ b/UNITTESTS/fakes/ble/GapImpl_mock.h @@ -0,0 +1,91 @@ +/* mbed Microcontroller Library + * Copyright (c) 2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_GAPMOCK_H +#define BLE_GAPMOCK_H + +#include "gmock/gmock.h" +#include "source/generic/GapImpl.h" + +namespace ble { + +class GapMock : public ble::impl::Gap { +public: + GapMock() {}; + GapMock(const GapMock&) = delete; + GapMock& operator=(const GapMock&) = delete; + virtual ~GapMock() {}; + + MOCK_METHOD((ble_error_t), reset, (), (override)); + MOCK_METHOD(void, setEventHandler, (EventHandler *handler), (override)); + MOCK_METHOD(bool, isFeatureSupported, (controller_supported_features_t feature), (override)); + MOCK_METHOD(uint8_t, getMaxAdvertisingSetNumber, (), (override)); + MOCK_METHOD(uint16_t, getMaxAdvertisingDataLength, (), (override)); + MOCK_METHOD(uint16_t, getMaxConnectableAdvertisingDataLength, (), (override)); + MOCK_METHOD(uint16_t, getMaxActiveSetAdvertisingDataLength, (), (override)); + MOCK_METHOD(ble_error_t, createAdvertisingSet, (advertising_handle_t *handle, const AdvertisingParameters ¶meters), (override)); + MOCK_METHOD(ble_error_t, destroyAdvertisingSet, (advertising_handle_t handle), (override)); + MOCK_METHOD(ble_error_t, setAdvertisingParameters, (advertising_handle_t handle, const AdvertisingParameters ¶ms), (override)); + MOCK_METHOD(ble_error_t, setAdvertisingPayload, (advertising_handle_t handle, mbed::Span payload), (override)); + MOCK_METHOD(ble_error_t, setAdvertisingScanResponse, (advertising_handle_t handle, mbed::Span response), (override)); + MOCK_METHOD(ble_error_t, startAdvertising, (advertising_handle_t handle, adv_duration_t maxDuration, uint8_t maxEvents), (override)); + MOCK_METHOD(ble_error_t, stopAdvertising, (advertising_handle_t handle), (override)); + MOCK_METHOD(bool, isAdvertisingActive, (advertising_handle_t handle), (override)); + MOCK_METHOD(ble_error_t, setPeriodicAdvertisingParameters, (advertising_handle_t handle, periodic_interval_t periodicAdvertisingIntervalMin, periodic_interval_t periodicAdvertisingIntervalMax, bool advertiseTxPower), (override)); + MOCK_METHOD(ble_error_t, setPeriodicAdvertisingPayload, (advertising_handle_t handle, mbed::Span payload), (override)); + MOCK_METHOD(ble_error_t, startPeriodicAdvertising, (advertising_handle_t handle), (override)); + MOCK_METHOD(ble_error_t, stopPeriodicAdvertising, (advertising_handle_t handle), (override)); + MOCK_METHOD(bool, isPeriodicAdvertisingActive, (advertising_handle_t handle), (override)); + MOCK_METHOD(ble_error_t, setScanParameters, (const ScanParameters ¶ms), (override)); + MOCK_METHOD(ble_error_t, startScan, (scan_duration_t duration, duplicates_filter_t filtering, scan_period_t period), (override)); + MOCK_METHOD(ble_error_t, initiate_scan, (), (override)); + MOCK_METHOD(ble_error_t, stopScan, (), (override)); + MOCK_METHOD(ble_error_t, createSync, (peer_address_type_t peerAddressType, const address_t &peerAddress, uint8_t sid, slave_latency_t maxPacketSkip, sync_timeout_t timeout), (override)); + MOCK_METHOD(ble_error_t, createSync, (slave_latency_t maxPacketSkip, sync_timeout_t timeout), (override)); + MOCK_METHOD(ble_error_t, cancelCreateSync, (), (override)); + MOCK_METHOD(ble_error_t, terminateSync, (periodic_sync_handle_t handle), (override)); + MOCK_METHOD(ble_error_t, addDeviceToPeriodicAdvertiserList, (peer_address_type_t peerAddressType, const address_t &peerAddress, advertising_sid_t sid), (override)); + MOCK_METHOD(ble_error_t, removeDeviceFromPeriodicAdvertiserList, (peer_address_type_t peerAddressType, const address_t &peerAddress, advertising_sid_t sid), (override)); + MOCK_METHOD(ble_error_t, clearPeriodicAdvertiserList, (), (override)); + MOCK_METHOD(ble_error_t, connect, (peer_address_type_t peerAddressType, const address_t &peerAddress, const ConnectionParameters &connectionParams), (override)); + MOCK_METHOD(ble_error_t, cancelConnect, (), (override)); + MOCK_METHOD(ble_error_t, updateConnectionParameters, (connection_handle_t connectionHandle, conn_interval_t minConnectionInterval, conn_interval_t maxConnectionInterval, slave_latency_t slaveLatency, supervision_timeout_t supervision_timeout, conn_event_length_t minConnectionEventLength, conn_event_length_t maxConnectionEventLength), (override)); + MOCK_METHOD(ble_error_t, manageConnectionParametersUpdateRequest, (bool userManageConnectionUpdateRequest), (override)); + MOCK_METHOD(ble_error_t, acceptConnectionParametersUpdate, (connection_handle_t connectionHandle, conn_interval_t minConnectionInterval, conn_interval_t maxConnectionInterval, slave_latency_t slaveLatency, supervision_timeout_t supervision_timeout, conn_event_length_t minConnectionEventLength, conn_event_length_t maxConnectionEventLength), (override)); + MOCK_METHOD(ble_error_t, rejectConnectionParametersUpdate, (connection_handle_t connectionHandle), (override)); + MOCK_METHOD(ble_error_t, disconnect, (connection_handle_t connectionHandle, local_disconnection_reason_t reason), (override)); + MOCK_METHOD(ble_error_t, readPhy, (connection_handle_t connection), (override)); + MOCK_METHOD(ble_error_t, setPreferredPhys, (const phy_set_t *txPhys, const phy_set_t *rxPhys), (override)); + MOCK_METHOD(ble_error_t, setPhy, (connection_handle_t connection, const phy_set_t *txPhys, const phy_set_t *rxPhys, coded_symbol_per_bit_t codedSymbol), (override)); + MOCK_METHOD(ble_error_t, enablePrivacy, (bool enable), (override)); + MOCK_METHOD(ble_error_t, setPeripheralPrivacyConfiguration, (const peripheral_privacy_configuration_t *configuration), (override)); + MOCK_METHOD(ble_error_t, getPeripheralPrivacyConfiguration, (peripheral_privacy_configuration_t *configuration), (override)); + MOCK_METHOD(ble_error_t, setCentralPrivacyConfiguration, (const central_privacy_configuration_t *configuration), (override)); + MOCK_METHOD(ble_error_t, getCentralPrivacyConfiguration, (central_privacy_configuration_t *configuration), (override)); + MOCK_METHOD(uint8_t, getMaxWhitelistSize, (), (const, override)); + MOCK_METHOD(ble_error_t, getWhitelist, (whitelist_t &whitelist), (const, override)); + MOCK_METHOD(ble_error_t, setWhitelist, (const whitelist_t &whitelist), (override)); + MOCK_METHOD(ble_error_t, getAddress, (own_address_type_t &typeP, address_t &address), (override)); + MOCK_METHOD(void, onShutdown, (const GapShutdownCallback_t &callback), (override)); + MOCK_METHOD(GapShutdownCallbackChain_t&, onShutdown, (), (override)); + MOCK_METHOD(ble_error_t, setRandomStaticAddress, (const ble::address_t &address), (override)); + MOCK_METHOD(ble::address_t, getRandomStaticAddress, (), (override)); +}; + +} + +#endif //BLE_GAPMOCK_H diff --git a/UNITTESTS/fakes/ble/GattClientImpl_mock.h b/UNITTESTS/fakes/ble/GattClientImpl_mock.h new file mode 100644 index 0000000000..6150ad1697 --- /dev/null +++ b/UNITTESTS/fakes/ble/GattClientImpl_mock.h @@ -0,0 +1,62 @@ +/* mbed Microcontroller Library + * Copyright (c) 2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_GATTCLIENTMOCK_H +#define BLE_GATTCLIENTMOCK_H + +#include "gmock/gmock.h" +#include "source/generic/GattClientImpl.h" + +namespace ble { + +class GattClientMock : public ble::impl::GattClient { +public: + GattClientMock() {}; + GattClientMock(const GattClientMock&) = delete; + GattClientMock& operator=(const GattClientMock&) = delete; + virtual ~GattClientMock() {}; + + MOCK_METHOD(ble_error_t, reset, (), (override)); + MOCK_METHOD(void, setEventHandler, (EventHandler *handler), (override)); + MOCK_METHOD(ble_error_t, launchServiceDiscovery, (ble::connection_handle_t connectionHandle, ServiceDiscovery::ServiceCallback_t sc, ServiceDiscovery::CharacteristicCallback_t cc, const UUID &matchingServiceUUID, const UUID &matchingCharacteristicUUIDIn), (override)); + MOCK_METHOD(ble_error_t, discoverServices, (ble::connection_handle_t connectionHandle, ServiceDiscovery::ServiceCallback_t callback, const UUID &matchingServiceUUID), (override)); + MOCK_METHOD(ble_error_t, discoverServices, (ble::connection_handle_t connectionHandle, ServiceDiscovery::ServiceCallback_t callback, GattAttribute::Handle_t startHandle, GattAttribute::Handle_t endHandle), (override)); + MOCK_METHOD(bool, isServiceDiscoveryActive, (), (const, override)); + MOCK_METHOD(void, terminateServiceDiscovery, (), (override)); + MOCK_METHOD(ble_error_t, read, (ble::connection_handle_t connHandle, GattAttribute::Handle_t attributeHandle, uint16_t offset), (const, override)); + MOCK_METHOD(ble_error_t, write, (GattClient::WriteOp_t cmd, ble::connection_handle_t connHandle, GattAttribute::Handle_t attributeHandle, size_t length, const uint8_t *value), (const, override)); + MOCK_METHOD(void, onDataRead, (ReadCallback_t callback), (override)); + MOCK_METHOD(ReadCallbackChain_t&, onDataRead, (), (override)); + MOCK_METHOD(void, onDataWritten, (WriteCallback_t callback), (override)); + MOCK_METHOD(WriteCallbackChain_t&, onDataWritten, (), (override)); + MOCK_METHOD(void, onServiceDiscoveryTermination, (ServiceDiscovery::TerminationCallback_t callback), (override)); + MOCK_METHOD(ble_error_t, discoverCharacteristicDescriptors, (const DiscoveredCharacteristic &characteristic, const CharacteristicDescriptorDiscovery::DiscoveryCallback_t &discoveryCallback, const CharacteristicDescriptorDiscovery::TerminationCallback_t &terminationCallback), (override)); + MOCK_METHOD(bool, isCharacteristicDescriptorDiscoveryActive, (const DiscoveredCharacteristic &characteristic), (const, override)); + MOCK_METHOD(void, terminateCharacteristicDescriptorDiscovery, (const DiscoveredCharacteristic &characteristic), (override)); + MOCK_METHOD(ble_error_t, negotiateAttMtu, (ble::connection_handle_t connection), (override)); + MOCK_METHOD(void, onHVX, (HVXCallback_t callback), (override)); + MOCK_METHOD(void, onShutdown, (const GattClientShutdownCallback_t &callback), (override)); + MOCK_METHOD(GattClientShutdownCallbackChain_t&, onShutdown, (), (override)); + MOCK_METHOD(HVXCallbackChain_t&, onHVX, (), (override)); + MOCK_METHOD(void, processReadResponse, (const GattReadCallbackParams *params), (override)); + MOCK_METHOD(void, processWriteResponse, (const GattWriteCallbackParams *params), (override)); + MOCK_METHOD(void, processHVXEvent, (const GattHVXCallbackParams *params), (override)); +}; + +} + +#endif //BLE_GATTCLIENTMOCK_H diff --git a/UNITTESTS/fakes/ble/GattServerImpl_mock.h b/UNITTESTS/fakes/ble/GattServerImpl_mock.h new file mode 100644 index 0000000000..bfafb52400 --- /dev/null +++ b/UNITTESTS/fakes/ble/GattServerImpl_mock.h @@ -0,0 +1,105 @@ +/* mbed Microcontroller Library + * Copyright (c) 2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_GATTSERVERMOCK_H +#define BLE_GATTSERVERMOCK_H + +#include "gmock/gmock.h" +#include "source/GattServerImpl.h" + +namespace ble { + +class GattServerMock : public ble::impl::GattServer { +public: + GattServerMock(); + GattServerMock(const GattServerMock&) = delete; + GattServerMock& operator=(const GattServerMock&) = delete; + virtual ~GattServerMock(); + + MOCK_METHOD(ble_error_t, reset, (ble::GattServer* server), (override)); + MOCK_METHOD(void, setEventHandler, (EventHandler *handler), (override)); + MOCK_METHOD(ble_error_t, addService, (GattService &service), (override)); + MOCK_METHOD(ble_error_t, read, (GattAttribute::Handle_t attributeHandle, uint8_t buffer[], uint16_t *lengthP), (override)); + MOCK_METHOD(ble_error_t, read, (ble::connection_handle_t connectionHandle, GattAttribute::Handle_t attributeHandle, uint8_t *buffer, uint16_t *lengthP), (override)); + MOCK_METHOD(ble_error_t, write, (GattAttribute::Handle_t attributeHandle, const uint8_t *value, uint16_t size, bool localOnly), (override)); + MOCK_METHOD(ble_error_t, write, (ble::connection_handle_t connectionHandle, GattAttribute::Handle_t attributeHandle, const uint8_t *value, uint16_t size, bool localOnly), (override)); + MOCK_METHOD(ble_error_t, areUpdatesEnabled, (const GattCharacteristic &characteristic, bool *enabledP), (override)); + MOCK_METHOD(ble_error_t, areUpdatesEnabled, (ble::connection_handle_t connectionHandle, const GattCharacteristic &characteristic, bool *enabledP), (override)); + MOCK_METHOD(ble::Gap::PreferredConnectionParams_t, getPreferredConnectionParams, (), (override)); + MOCK_METHOD(void, setPreferredConnectionParams, (const ble::Gap::PreferredConnectionParams_t ¶ms), (override)); + MOCK_METHOD(bool, isOnDataReadAvailable, (), (const, override)); + MOCK_METHOD(void, onDataSent, (const DataSentCallback_t &callback), (override)); + MOCK_METHOD(DataSentCallbackChain_t&, onDataSent, (), (override)); + MOCK_METHOD(void, onDataWritten, (const DataWrittenCallback_t &callback), (override)); + MOCK_METHOD(DataWrittenCallbackChain_t&, onDataWritten, (), (override)); + MOCK_METHOD(ble_error_t, onDataRead, (const DataReadCallback_t &callback), (override)); + MOCK_METHOD(DataReadCallbackChain_t&, onDataRead, (), (override)); + MOCK_METHOD(void, onShutdown, (const GattServerShutdownCallback_t &callback), (override)); + MOCK_METHOD(GattServerShutdownCallbackChain_t&, onShutdown, (), (override)); + MOCK_METHOD(void, onUpdatesEnabled, (EventCallback_t callback), (override)); + MOCK_METHOD(void, onUpdatesDisabled, (EventCallback_t callback), (override)); + MOCK_METHOD(void, onConfirmationReceived, (EventCallback_t callback), (override)); + MOCK_METHOD(void, handleDataWrittenEvent, (const GattWriteCallbackParams *params), (override)); + MOCK_METHOD(void, handleDataReadEvent, (const GattReadCallbackParams *params), (override)); + MOCK_METHOD(void, handleEvent, (GattServerEvents::gattEvent_e type, ble::connection_handle_t connHandle, GattAttribute::Handle_t attributeHandle), (override)); + MOCK_METHOD(void, handleDataSentEvent, (unsigned count), (override)); + + // Fake part + // Descriptor representation of a descriptor registered with ble::test::register_services + struct descriptor_t { + UUID uuid; + ble::attribute_handle_t handle; + ble::att_security_requirement_t read_security = ble::att_security_requirement_t::NONE; + ble::att_security_requirement_t write_security = ble::att_security_requirement_t::NONE; + bool is_readable; + bool is_writable; + std::vector value; // Use capacity to determine the max size. + }; + + // Characteristic representation of a characteristic registered with ble::test::register_services + struct characteristic_t { + UUID uuid; + ble::attribute_handle_t value_handle; + uint8_t properties; + ble::att_security_requirement_t read_security = ble::att_security_requirement_t::NONE; + ble::att_security_requirement_t write_security = ble::att_security_requirement_t::NONE; + ble::att_security_requirement_t update_security = ble::att_security_requirement_t::NONE; + FunctionPointerWithContext + read_cb; + FunctionPointerWithContext + write_cb; + bool has_variable_len; + std::vector value; // Use capacity to determine the max size. + std::vector descriptors; + }; + + // Service representation of a service registered with ble::test::register_services + struct service_t { + UUID uuid; + ble::attribute_handle_t handle; + std::vector characteristics; + }; + + void fake_register_services(GattService& gattService); + + std::vector services; + ble::attribute_handle_t current_handle = 1; +}; + +} + +#endif //BLE_GATTSERVERMOCK_H diff --git a/UNITTESTS/fakes/ble/SecurityManagerImpl_mock.h b/UNITTESTS/fakes/ble/SecurityManagerImpl_mock.h new file mode 100644 index 0000000000..3f1007e4fa --- /dev/null +++ b/UNITTESTS/fakes/ble/SecurityManagerImpl_mock.h @@ -0,0 +1,73 @@ +/* mbed Microcontroller Library + * Copyright (c) 2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SECURITYMANAGERMOCK_H +#define SECURITYMANAGERMOCK_H + +#include "gmock/gmock.h" +#include "source/generic/SecurityManagerImpl.h" + +namespace ble { + +class SecurityManagerMock : public ble::impl::SecurityManager { +public: + SecurityManagerMock() {}; + SecurityManagerMock(const GattServerMock&) = delete; + SecurityManagerMock& operator=(const GattServerMock&) = delete; + virtual ~SecurityManagerMock() {}; + + MOCK_METHOD(ble_error_t, reset, (), (override)); + MOCK_METHOD(ble_error_t, init, (bool enableBonding, bool requireMITM, SecurityIOCapabilities_t iocaps, const Passkey_t passkey, bool signing, const char *dbFilepath), (override)); + MOCK_METHOD(ble_error_t, setDatabaseFilepath, (const char *dbFilepath), (override)); + MOCK_METHOD(ble_error_t, preserveBondingStateOnReset, (bool enable), (override)); + MOCK_METHOD(ble_error_t, purgeAllBondingState, (), (override)); + MOCK_METHOD(ble_error_t, generateWhitelistFromBondTable, (::ble::whitelist_t *whitelist), (const, override)); + MOCK_METHOD(ble_error_t, requestPairing, (ble::connection_handle_t connectionHandle), (override)); + MOCK_METHOD(ble_error_t, acceptPairingRequest, (ble::connection_handle_t connectionHandle), (override)); + MOCK_METHOD(ble_error_t, cancelPairingRequest, (ble::connection_handle_t connectionHandle), (override)); + MOCK_METHOD(ble_error_t, setPairingRequestAuthorisation, (bool required), (override)); + MOCK_METHOD(ble_error_t, getPeerIdentity, (ble::connection_handle_t connectionHandle), (override)); + MOCK_METHOD(ble_error_t, allowLegacyPairing, (bool allow), (override)); + MOCK_METHOD(ble_error_t, getSecureConnectionsSupport, (bool *enabled), (override)); + MOCK_METHOD(ble_error_t, setIoCapability, (SecurityIOCapabilities_t iocaps), (override)); + MOCK_METHOD(ble_error_t, setDisplayPasskey, (const Passkey_t passkey), (override)); + MOCK_METHOD(ble_error_t, setLinkSecurity, (ble::connection_handle_t connectionHandle, SecurityMode_t securityMode), (override)); + MOCK_METHOD(ble_error_t, setKeypressNotification, (bool enabled), (override)); + MOCK_METHOD(ble_error_t, enableSigning, (ble::connection_handle_t connectionHandle, bool enabled), (override)); + MOCK_METHOD(ble_error_t, setHintFutureRoleReversal, (bool enable), (override)); + MOCK_METHOD(ble_error_t, getLinkEncryption, (ble::connection_handle_t connectionHandle, ble::link_encryption_t *encryption), (override)); + MOCK_METHOD(ble_error_t, setLinkEncryption, (ble::connection_handle_t connectionHandle, ble::link_encryption_t encryption), (override)); + MOCK_METHOD(ble_error_t, setEncryptionKeyRequirements, (uint8_t minimumByteSize, uint8_t maximumByteSize), (override)); + MOCK_METHOD(ble_error_t, getEncryptionKeySize, (connection_handle_t connectionHandle, uint8_t *size), (override)); + MOCK_METHOD(ble_error_t, requestAuthentication, (ble::connection_handle_t connectionHandle), (override)); + MOCK_METHOD(ble_error_t, generateOOB, (const ble::address_t *address), (override)); + MOCK_METHOD(ble_error_t, setOOBDataUsage, (ble::connection_handle_t connectionHandle, bool useOOB, bool OOBProvidesMITM), (override)); + MOCK_METHOD(ble_error_t, passkeyEntered, (ble::connection_handle_t connectionHandle, Passkey_t passkey), (override)); + MOCK_METHOD(ble_error_t, legacyPairingOobReceived, (const ble::address_t *address, const ble::oob_tk_t *tk), (override)); + MOCK_METHOD(ble_error_t, confirmationEntered, (ble::connection_handle_t connectionHandle, bool confirmation), (override)); + MOCK_METHOD(ble_error_t, sendKeypressNotification, (ble::connection_handle_t connectionHandle, ble::Keypress_t keypress), (override)); + MOCK_METHOD(ble_error_t, oobReceived, (const ble::address_t *address, const ble::oob_lesc_value_t *random, const ble::oob_confirm_t *confirm), (override)); + MOCK_METHOD(ble_error_t, getSigningKey, (ble::connection_handle_t connectionHandle, bool authenticated), (override)); + MOCK_METHOD(ble_error_t, setPrivateAddressTimeout, (uint16_t timeout_in_seconds), (override)); + MOCK_METHOD(void, onShutdown, (const SecurityManagerShutdownCallback_t &callback), (override)); + MOCK_METHOD(SecurityManagerShutdownCallbackChain_t&, onShutdown, (), (override)); + MOCK_METHOD(void, setSecurityManagerEventHandler, (EventHandler *handler), (override)); +}; + +} + +#endif //SECURITYMANAGERMOCK_H diff --git a/UNITTESTS/fakes/ble/ble_mocks.h b/UNITTESTS/fakes/ble/ble_mocks.h new file mode 100644 index 0000000000..d92904e173 --- /dev/null +++ b/UNITTESTS/fakes/ble/ble_mocks.h @@ -0,0 +1,45 @@ +/* mbed Microcontroller Library + * Copyright (c) 2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_MOCKS_H +#define BLE_MOCKS_H + +#include "GattServerImpl_mock.h" +#include "GattClientImpl_mock.h" +#include "GapImpl_mock.h" +#include "SecurityManagerImpl_mock.h" + +/*** + * You must use delete_mocks() at the end of the test. BLE::Instance(), ble::gap() etc. inits the mocks. Do not cache + * pointers between tests. Call BLE::Instance() at the start of the tests, otherwise call init_mocks() yourself. + * To access mocks use: + * gap_mock(), gatt_server_mock(), gatt_client_mock(), security_manager_mock(). + * All functions are in namespace ble. + */ +namespace ble { + +void init_mocks(); +void delete_mocks(); + +GapMock& gap_mock(); +GattServerMock& gatt_server_mock(); +GattClientMock& gatt_client_mock(); +SecurityManagerMock& security_manager_mock(); + +} + +#endif // BLE_MOCKS_H diff --git a/UNITTESTS/fakes/ble/source/GattServerImpl.h b/UNITTESTS/fakes/ble/source/GattServerImpl.h new file mode 100644 index 0000000000..d4b43490d3 --- /dev/null +++ b/UNITTESTS/fakes/ble/source/GattServerImpl.h @@ -0,0 +1,137 @@ +/* mbed Microcontroller Library + * Copyright (c) 2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_GATTSERVERSTUB_H +#define BLE_GATTSERVERSTUB_H + +#include "ble/GattServer.h" +#include "generic/GattServerEvents.h" +#include "ble/Gap.h" + +namespace ble { +namespace impl { + +class GattServer { +public: + GattServer() {}; + GattServer(const GattServer&) = delete; + GattServer& operator=(const GattServer&) = delete; + virtual ~GattServer() {}; + + using EventHandler = ble::GattServer::EventHandler; + using DataSentCallback_t = ble::GattServer::DataSentCallback_t ; + using DataSentCallbackChain_t = ble::GattServer::DataSentCallbackChain_t ; + using DataWrittenCallback_t = ble::GattServer::DataWrittenCallback_t ; + using DataWrittenCallbackChain_t = ble::GattServer::DataWrittenCallbackChain_t ; + using DataReadCallback_t = ble::GattServer::DataReadCallback_t; + using DataReadCallbackChain_t = ble::GattServer::DataReadCallbackChain_t; + using GattServerShutdownCallback_t = ble::GattServer::GattServerShutdownCallback_t; + using GattServerShutdownCallbackChain_t = ble::GattServer::GattServerShutdownCallbackChain_t; + using EventCallback_t = ble::GattServer::EventCallback_t; + + virtual void setEventHandler(EventHandler *handler) { }; + + virtual ble_error_t reset(ble::GattServer* server) { return BLE_ERROR_NONE; }; + + virtual ble_error_t addService(GattService &service) { return BLE_ERROR_NONE; }; + + virtual ble_error_t read( + GattAttribute::Handle_t attributeHandle, + uint8_t buffer[], + uint16_t *lengthP + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t read( + ble::connection_handle_t connectionHandle, + GattAttribute::Handle_t attributeHandle, + uint8_t *buffer, + uint16_t *lengthP + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t write( + GattAttribute::Handle_t attributeHandle, + const uint8_t *value, + uint16_t size, + bool localOnly = false + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t write( + ble::connection_handle_t connectionHandle, + GattAttribute::Handle_t attributeHandle, + const uint8_t *value, + uint16_t size, + bool localOnly = false + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t areUpdatesEnabled( + const GattCharacteristic &characteristic, + bool *enabledP + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t areUpdatesEnabled( + ble::connection_handle_t connectionHandle, + const GattCharacteristic &characteristic, + bool *enabledP + ) { return BLE_ERROR_NONE; }; + + virtual ble::Gap::PreferredConnectionParams_t getPreferredConnectionParams() { + ble::Gap::PreferredConnectionParams_t params = {0}; return params; + }; + + virtual void setPreferredConnectionParams(const ble::Gap::PreferredConnectionParams_t ¶ms) { }; + + virtual bool isOnDataReadAvailable() const { return true; }; + + virtual void onDataSent(const DataSentCallback_t &callback) { }; + + virtual DataSentCallbackChain_t &onDataSent() { static DataSentCallbackChain_t chain; return chain; }; + + virtual void onDataWritten(const DataWrittenCallback_t &callback) { }; + + virtual DataWrittenCallbackChain_t &onDataWritten() { static DataWrittenCallbackChain_t chain; return chain; }; + + virtual ble_error_t onDataRead(const DataReadCallback_t &callback) { return BLE_ERROR_NONE; }; + + virtual DataReadCallbackChain_t &onDataRead() { static DataReadCallbackChain_t chain; return chain; }; + + virtual void onShutdown(const GattServerShutdownCallback_t &callback) { }; + + virtual GattServerShutdownCallbackChain_t &onShutdown() { static GattServerShutdownCallbackChain_t chain; return chain; }; + + virtual void onUpdatesEnabled(EventCallback_t callback) { }; + + virtual void onUpdatesDisabled(EventCallback_t callback) { }; + + virtual void onConfirmationReceived(EventCallback_t callback) { }; + + virtual void handleDataWrittenEvent(const GattWriteCallbackParams *params) { }; + + virtual void handleDataReadEvent(const GattReadCallbackParams *params) { }; + + virtual void handleEvent( + GattServerEvents::gattEvent_e type, + ble::connection_handle_t connHandle, + GattAttribute::Handle_t attributeHandle + ) { }; + + virtual void handleDataSentEvent(unsigned count) { }; +}; + +} +} + +#endif //BLE_GATTSERVERSTUB_H diff --git a/UNITTESTS/fakes/ble/source/GattServerImpl_mock.cpp b/UNITTESTS/fakes/ble/source/GattServerImpl_mock.cpp new file mode 100644 index 0000000000..baf6d0c8a6 --- /dev/null +++ b/UNITTESTS/fakes/ble/source/GattServerImpl_mock.cpp @@ -0,0 +1,96 @@ +/* mbed Microcontroller Library + * Copyright (c) 2021 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "GattServerImpl_mock.h" + +namespace ble { + +GattServerMock::GattServerMock() +{ + ON_CALL(*this, addService).WillByDefault([this](GattService &service) { + // Fake registration, it populates the handles of the input and store its + // representation in the services field. + fake_register_services(service); + return BLE_ERROR_NONE; + }); +} + +GattServerMock::~GattServerMock() {}; + +void GattServerMock::fake_register_services(GattService& gattService) +{ + gattService.setHandle(current_handle++); + service_t result { + gattService.getUUID(), + gattService.getHandle() + }; + + for (size_t i = 0; i < gattService.getCharacteristicCount(); ++i) { + current_handle++; // Increment for the characteristic declaration handle + auto& ref = *gattService.getCharacteristic(i); + ref.getValueAttribute().setHandle(current_handle++); + + characteristic_t c; + c.uuid = ref.getValueAttribute().getUUID(); + c.value_handle = ref.getValueHandle(); + c.properties = ref.getProperties(); + c.read_security = ref.getReadSecurityRequirement(); + c.write_security = ref.getWriteSecurityRequirement(); + c.update_security = ref.getUpdateSecurityRequirement(); + c.read_cb = ref.getReadAuthorizationCallback(); + c.write_cb = ref.getWriteAuthorizationCallback(); + c.value.reserve(ref.getValueAttribute().getMaxLength()); + c.value.resize(ref.getValueAttribute().getLength()); + { + auto value_ptr = ref.getValueAttribute().getValuePtr(); + if (value_ptr) { + std::copy(value_ptr, value_ptr + c.value.size(), c.value.begin()); + } + } + c.has_variable_len = ref.getValueAttribute().hasVariableLength(); + + for (size_t j = 0; j < ref.getDescriptorCount(); ++j) { + auto& ref_desc = *ref.getDescriptor(j); + ref_desc.setHandle(current_handle++); + + descriptor_t d; + d.uuid = ref_desc.getUUID(); + d.handle = ref_desc.getHandle(); + d.read_security = ref_desc.getReadSecurityRequirement(); + d.write_security = ref_desc.getWriteSecurityRequirement(); + d.is_readable = ref_desc.isReadAllowed(); + d.is_writable = ref_desc.isWriteAllowed(); + d.value.reserve(ref_desc.getMaxLength()); + d.value.resize(ref_desc.getLength()); + { + auto value_ptr = ref_desc.getValuePtr(); + if (value_ptr) { + std::copy(value_ptr, value_ptr + d.value.size(), d.value.begin()); + } + } + + c.descriptors.push_back(d); + } + + result.characteristics.push_back(c); + } + + services.push_back(result); +} + + +} diff --git a/UNITTESTS/fakes/ble/source/generic/GapImpl.h b/UNITTESTS/fakes/ble/source/generic/GapImpl.h new file mode 100644 index 0000000000..6cd3bbf41f --- /dev/null +++ b/UNITTESTS/fakes/ble/source/generic/GapImpl.h @@ -0,0 +1,317 @@ +/* mbed Microcontroller Library + * Copyright (c) 2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_GAPSTUB_H +#define BLE_GAPSTUB_H + +namespace ble { +namespace impl { + +class Gap { +public: + Gap() {}; + Gap(const Gap&) = delete; + Gap& operator=(const Gap&) = delete; + virtual ~Gap() {}; + + using EventHandler = ::ble::Gap::EventHandler; + using GapShutdownCallback_t = ::ble::Gap::GapShutdownCallback_t; + using GapShutdownCallbackChain_t = ::ble::Gap::GapShutdownCallbackChain_t ; + using PreferredConnectionParams_t = ::ble::Gap::PreferredConnectionParams_t ; + +#if BLE_FEATURE_PRIVACY +#if BLE_ROLE_BROADCASTER + static const peripheral_privacy_configuration_t default_peripheral_privacy_configuration; +#endif // BLE_ROLE_BROADCASTER + +#if BLE_ROLE_OBSERVER + /** + * Default peripheral privacy configuration. + */ + static const central_privacy_configuration_t default_central_privacy_configuration; +#endif // BLE_ROLE_OBSERVER +#endif // BLE_FEATURE_PRIVACY + +public: + virtual void setEventHandler(EventHandler *handler) { }; + + virtual bool isFeatureSupported(controller_supported_features_t feature) { return true; }; + + /* advertising */ +#if BLE_ROLE_BROADCASTER + + virtual uint8_t getMaxAdvertisingSetNumber() { return 1; }; + + virtual uint16_t getMaxAdvertisingDataLength() { return 23; }; + + virtual uint16_t getMaxConnectableAdvertisingDataLength() { return 21; }; + + virtual uint16_t getMaxActiveSetAdvertisingDataLength() { return 21; }; + +#if BLE_FEATURE_EXTENDED_ADVERTISING + + virtual ble_error_t createAdvertisingSet( + advertising_handle_t *handle, + const AdvertisingParameters ¶meters + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t destroyAdvertisingSet(advertising_handle_t handle) { return BLE_ERROR_NONE; }; + +#endif // BLE_FEATURE_EXTENDED_ADVERTISING + + virtual ble_error_t setAdvertisingParameters( + advertising_handle_t handle, + const AdvertisingParameters ¶ms + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t setAdvertisingPayload( + advertising_handle_t handle, + mbed::Span payload + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t setAdvertisingScanResponse( + advertising_handle_t handle, + mbed::Span response + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t startAdvertising( + advertising_handle_t handle, + adv_duration_t maxDuration = adv_duration_t::forever(), + uint8_t maxEvents = 0 + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t stopAdvertising(advertising_handle_t handle) { return BLE_ERROR_NONE; }; + + virtual bool isAdvertisingActive(advertising_handle_t handle) { return true; }; + +#endif // BLE_ROLE_BROADCASTER + +#if BLE_ROLE_BROADCASTER +#if BLE_FEATURE_PERIODIC_ADVERTISING + + virtual ble_error_t setPeriodicAdvertisingParameters( + advertising_handle_t handle, + periodic_interval_t periodicAdvertisingIntervalMin, + periodic_interval_t periodicAdvertisingIntervalMax, + bool advertiseTxPower = true + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t setPeriodicAdvertisingPayload( + advertising_handle_t handle, + mbed::Span payload + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t startPeriodicAdvertising(advertising_handle_t handle) { return BLE_ERROR_NONE; }; + + virtual ble_error_t stopPeriodicAdvertising(advertising_handle_t handle) { return BLE_ERROR_NONE; }; + + virtual bool isPeriodicAdvertisingActive(advertising_handle_t handle) { return true; }; + +#endif // BLE_ROLE_BROADCASTER +#endif // BLE_FEATURE_PERIODIC_ADVERTISING + + /* scanning */ +#if BLE_ROLE_OBSERVER + + virtual ble_error_t setScanParameters(const ScanParameters ¶ms) { return BLE_ERROR_NONE; }; + + virtual ble_error_t startScan( + scan_duration_t duration = scan_duration_t::forever(), + duplicates_filter_t filtering = duplicates_filter_t::DISABLE, + scan_period_t period = scan_period_t(0) + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t initiate_scan() { return BLE_ERROR_NONE; }; + + virtual ble_error_t stopScan() { return BLE_ERROR_NONE; }; + +#endif // BLE_ROLE_OBSERVER + +#if BLE_ROLE_OBSERVER +#if BLE_FEATURE_PERIODIC_ADVERTISING + + virtual ble_error_t createSync( + peer_address_type_t peerAddressType, + const address_t &peerAddress, + uint8_t sid, + slave_latency_t maxPacketSkip, + sync_timeout_t timeout + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t createSync( + slave_latency_t maxPacketSkip, + sync_timeout_t timeout + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t cancelCreateSync() { return BLE_ERROR_NONE; }; + + virtual ble_error_t terminateSync(periodic_sync_handle_t handle) { return BLE_ERROR_NONE; }; + + virtual ble_error_t addDeviceToPeriodicAdvertiserList( + peer_address_type_t peerAddressType, + const address_t &peerAddress, + advertising_sid_t sid + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t removeDeviceFromPeriodicAdvertiserList( + peer_address_type_t peerAddressType, + const address_t &peerAddress, + advertising_sid_t sid + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t clearPeriodicAdvertiserList() { return BLE_ERROR_NONE; }; + + uint8_t getMaxPeriodicAdvertiserListSize() { return 1; }; + +#endif // BLE_ROLE_OBSERVER +#endif // BLE_FEATURE_PERIODIC_ADVERTISING + +#if BLE_ROLE_CENTRAL + + virtual ble_error_t connect( + peer_address_type_t peerAddressType, + const address_t &peerAddress, + const ConnectionParameters &connectionParams + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t cancelConnect() { return BLE_ERROR_NONE; }; + +#endif // BLE_ROLE_CENTRAL + +#if BLE_FEATURE_CONNECTABLE + + virtual ble_error_t updateConnectionParameters( + connection_handle_t connectionHandle, + conn_interval_t minConnectionInterval, + conn_interval_t maxConnectionInterval, + slave_latency_t slaveLatency, + supervision_timeout_t supervision_timeout, + conn_event_length_t minConnectionEventLength = conn_event_length_t(0), + conn_event_length_t maxConnectionEventLength = conn_event_length_t(0) + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t manageConnectionParametersUpdateRequest( + bool userManageConnectionUpdateRequest + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t acceptConnectionParametersUpdate( + connection_handle_t connectionHandle, + conn_interval_t minConnectionInterval, + conn_interval_t maxConnectionInterval, + slave_latency_t slaveLatency, + supervision_timeout_t supervision_timeout, + conn_event_length_t minConnectionEventLength = conn_event_length_t(0), + conn_event_length_t maxConnectionEventLength = conn_event_length_t(0) + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t rejectConnectionParametersUpdate( + connection_handle_t connectionHandle + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t disconnect( + connection_handle_t connectionHandle, + local_disconnection_reason_t reason + ) { return BLE_ERROR_NONE; }; + +#endif // BLE_FEATURE_CONNECTABLE +#if BLE_FEATURE_PHY_MANAGEMENT + + virtual ble_error_t readPhy(connection_handle_t connection) { return BLE_ERROR_NONE; }; + + virtual ble_error_t setPreferredPhys( + const phy_set_t *txPhys, + const phy_set_t *rxPhys + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t setPhy( + connection_handle_t connection, + const phy_set_t *txPhys, + const phy_set_t *rxPhys, + coded_symbol_per_bit_t codedSymbol + ) { return BLE_ERROR_NONE; }; + +#endif // BLE_FEATURE_PHY_MANAGEMENT + +#if BLE_FEATURE_PRIVACY + + virtual ble_error_t enablePrivacy(bool enable) { return BLE_ERROR_NONE; }; + +#if BLE_ROLE_BROADCASTER + + virtual ble_error_t setPeripheralPrivacyConfiguration( + const peripheral_privacy_configuration_t *configuration + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t getPeripheralPrivacyConfiguration( + peripheral_privacy_configuration_t *configuration + ) { return BLE_ERROR_NONE; }; + +#endif // BLE_ROLE_BROADCASTER + +#if BLE_ROLE_OBSERVER + + virtual ble_error_t setCentralPrivacyConfiguration( + const central_privacy_configuration_t *configuration + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t getCentralPrivacyConfiguration( + central_privacy_configuration_t *configuration + ) { return BLE_ERROR_NONE; }; + +#endif // BLE_ROLE_OBSERVER +#endif // BLE_FEATURE_PRIVACY + +#if BLE_FEATURE_WHITELIST + + virtual uint8_t getMaxWhitelistSize() const { return 1; }; + + virtual ble_error_t getWhitelist(whitelist_t &whitelist) const { return BLE_ERROR_NONE; }; + + virtual ble_error_t setWhitelist(const whitelist_t &whitelist) { return BLE_ERROR_NONE; }; + +#endif // BLE_FEATURE_WHITELIST + + virtual ble_error_t getAddress( + own_address_type_t &typeP, + address_t &address + ) { return BLE_ERROR_NONE; }; + + static ble_error_t getRandomAddressType( + ble::address_t address, + ble::random_address_type_t *addressType + ) { return BLE_ERROR_NONE;}; + + virtual ble_error_t reset() { return BLE_ERROR_NONE; }; + + virtual void onShutdown(const GapShutdownCallback_t &callback) { }; + + virtual GapShutdownCallbackChain_t &onShutdown() { static GapShutdownCallbackChain_t chain; return chain; }; + + /* + * API reserved for the controller driver to set the random static address. + * Setting a new random static address while the controller is operating is + * forbidden by the Bluetooth specification. + */ + virtual ble_error_t setRandomStaticAddress(const ble::address_t &address) { return BLE_ERROR_NONE; }; + + virtual ble::address_t getRandomStaticAddress() { return ble::address_t(); }; +}; + +} +} + +#endif //BLE_GAPSTUB_H diff --git a/UNITTESTS/fakes/ble/source/generic/GattClientImpl.h b/UNITTESTS/fakes/ble/source/generic/GattClientImpl.h new file mode 100644 index 0000000000..2795ffeec9 --- /dev/null +++ b/UNITTESTS/fakes/ble/source/generic/GattClientImpl.h @@ -0,0 +1,133 @@ +/* mbed Microcontroller Library + * Copyright (c) 2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef BLE_GATTCLIENTSTUB_H +#define BLE_GATTCLIENTSTUB_H + +#include "events/EventQueue.h" + +namespace ble { +namespace impl { + +class GattClient { +public: + using EventHandler = ble::GattClient::EventHandler; + using WriteOp_t = ble::GattClient::WriteOp_t; + using HVXCallback_t = ble::GattClient::HVXCallback_t ; + using GattClientShutdownCallback_t = ble::GattClient::GattClientShutdownCallback_t ; + using GattClientShutdownCallbackChain_t = ble::GattClient::GattClientShutdownCallbackChain_t ; + using HVXCallbackChain_t = ble::GattClient::HVXCallbackChain_t ; + using ReadCallbackChain_t = ble::GattClient::ReadCallbackChain_t ; + using WriteCallbackChain_t = ble::GattClient::WriteCallbackChain_t ; + + GattClient() {}; + GattClient(const GattClient&) = delete; + GattClient& operator=(const GattClient&) = delete; + virtual ~GattClient() {}; + + virtual void setEventHandler(EventHandler *handler) { }; + + virtual ble_error_t launchServiceDiscovery( + ble::connection_handle_t connectionHandle, + ServiceDiscovery::ServiceCallback_t sc = nullptr, + ServiceDiscovery::CharacteristicCallback_t cc = nullptr, + const UUID &matchingServiceUUID = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN), + const UUID &matchingCharacteristicUUIDIn = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN) + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t discoverServices( + ble::connection_handle_t connectionHandle, + ServiceDiscovery::ServiceCallback_t callback, + const UUID &matchingServiceUUID = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN) + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t discoverServices( + ble::connection_handle_t connectionHandle, + ServiceDiscovery::ServiceCallback_t callback, + GattAttribute::Handle_t startHandle, + GattAttribute::Handle_t endHandle + ) { return BLE_ERROR_NONE; }; + + virtual bool isServiceDiscoveryActive(void) const { return true; }; + + virtual void terminateServiceDiscovery(void) { }; + + virtual ble_error_t read( + ble::connection_handle_t connHandle, + GattAttribute::Handle_t attributeHandle, + uint16_t offset + ) const { return BLE_ERROR_NONE; }; + + virtual ble_error_t write( + GattClient::WriteOp_t cmd, + ble::connection_handle_t connHandle, + GattAttribute::Handle_t attributeHandle, + size_t length, + const uint8_t *value + ) const { return BLE_ERROR_NONE; }; + + /* Event callback handlers. */ + + virtual void onDataRead(ReadCallback_t callback) { }; + + virtual ReadCallbackChain_t &onDataRead() { static ReadCallbackChain_t chain; return chain; }; + + virtual void onDataWritten(WriteCallback_t callback) { }; + + virtual WriteCallbackChain_t &onDataWritten() { static WriteCallbackChain_t chain; return chain; }; + + virtual void onServiceDiscoveryTermination( + ServiceDiscovery::TerminationCallback_t callback + ) { }; + + virtual ble_error_t discoverCharacteristicDescriptors( + const DiscoveredCharacteristic &characteristic, + const CharacteristicDescriptorDiscovery::DiscoveryCallback_t &discoveryCallback, + const CharacteristicDescriptorDiscovery::TerminationCallback_t &terminationCallback + ) { return BLE_ERROR_NONE; }; + + virtual bool isCharacteristicDescriptorDiscoveryActive( + const DiscoveredCharacteristic &characteristic + ) const { return true; }; + + virtual void terminateCharacteristicDescriptorDiscovery( + const DiscoveredCharacteristic &characteristic + ) { }; + + virtual ble_error_t negotiateAttMtu(ble::connection_handle_t connection) { return BLE_ERROR_NONE; }; + + virtual void onHVX(HVXCallback_t callback) { }; + + virtual void onShutdown(const GattClientShutdownCallback_t &callback) { }; + + virtual GattClientShutdownCallbackChain_t &onShutdown() { static GattClientShutdownCallbackChain_t chain; return chain; }; + + virtual HVXCallbackChain_t &onHVX() { static HVXCallbackChain_t chain; return chain; }; + + virtual ble_error_t reset(void) { return BLE_ERROR_NONE; }; + + virtual void processReadResponse(const GattReadCallbackParams *params) { }; + + virtual void processWriteResponse(const GattWriteCallbackParams *params) { }; + + virtual void processHVXEvent(const GattHVXCallbackParams *params) { }; +}; + +} +} + +#endif //BLE_GATTCLIENTSTUB_H diff --git a/UNITTESTS/fakes/ble/source/generic/SecurityManagerImpl.h b/UNITTESTS/fakes/ble/source/generic/SecurityManagerImpl.h new file mode 100644 index 0000000000..35e4de5117 --- /dev/null +++ b/UNITTESTS/fakes/ble/source/generic/SecurityManagerImpl.h @@ -0,0 +1,186 @@ +/* mbed Microcontroller Library + * Copyright (c) 2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SECURITYMANAGERSTUB_H +#define SECURITYMANAGERSTUB_H + +namespace ble { +namespace impl { + +class SecurityManager { +public: + SecurityManager() {}; + SecurityManager(const SecurityManager&) = delete; + SecurityManager& operator=(const SecurityManager&) = delete; + virtual ~SecurityManager() {}; + + using SecurityIOCapabilities_t = ble::SecurityManager::SecurityIOCapabilities_t; + using SecurityMode_t = ble::SecurityManager::SecurityMode_t; + using SecurityManagerShutdownCallback_t = ble::SecurityManager::SecurityManagerShutdownCallback_t; + using SecurityManagerShutdownCallbackChain_t = ble::SecurityManager::SecurityManagerShutdownCallbackChain_t; + using EventHandler = ble::SecurityManager::EventHandler; + using Passkey_t = ble::SecurityManager::Passkey_t ; + + static auto constexpr IO_CAPS_NONE = ble::SecurityManager::IO_CAPS_NONE; + + virtual ble_error_t init( + bool enableBonding = true, + bool requireMITM = true, + SecurityIOCapabilities_t iocaps = IO_CAPS_NONE, + const Passkey_t passkey = nullptr, + bool signing = true, + const char *dbFilepath = nullptr + ) { return BLE_ERROR_NONE; }; + + virtual ble_error_t setDatabaseFilepath(const char *dbFilepath = nullptr) { return BLE_ERROR_NONE; }; + + virtual ble_error_t reset() { return BLE_ERROR_NONE; }; + + virtual ble_error_t preserveBondingStateOnReset(bool enable) { return BLE_ERROR_NONE; }; + + //////////////////////////////////////////////////////////////////////////// + // List management + // + + virtual ble_error_t purgeAllBondingState() { return BLE_ERROR_NONE; }; + + virtual ble_error_t generateWhitelistFromBondTable(::ble::whitelist_t *whitelist) const { return BLE_ERROR_NONE; }; + + //////////////////////////////////////////////////////////////////////////// + // Pairing + // + +#if BLE_ROLE_CENTRAL + virtual ble_error_t requestPairing(ble::connection_handle_t connectionHandle) { return BLE_ERROR_NONE; }; +#endif // BLE_ROLE_CENTRAL + +#if BLE_ROLE_PERIPHERAL + virtual ble_error_t acceptPairingRequest(ble::connection_handle_t connectionHandle) { return BLE_ERROR_NONE; }; +#endif // BLE_ROLE_PERIPHERAL + + virtual ble_error_t cancelPairingRequest(ble::connection_handle_t connectionHandle) { return BLE_ERROR_NONE; }; + + virtual ble_error_t setPairingRequestAuthorisation(bool required = true) { return BLE_ERROR_NONE; }; + + virtual ble_error_t getPeerIdentity(ble::connection_handle_t connectionHandle) { return BLE_ERROR_NONE; }; + + //////////////////////////////////////////////////////////////////////////// + // Feature support + // +#if BLE_FEATURE_SECURE_CONNECTIONS + virtual ble_error_t allowLegacyPairing(bool allow = true) { return BLE_ERROR_NONE; }; + + virtual ble_error_t getSecureConnectionsSupport(bool *enabled) { return BLE_ERROR_NONE; }; +#endif // BLE_FEATURE_SECURE_CONNECTIONS + + //////////////////////////////////////////////////////////////////////////// + // Security settings + // + + virtual ble_error_t setIoCapability(SecurityIOCapabilities_t iocaps) { return BLE_ERROR_NONE; }; + + virtual ble_error_t setDisplayPasskey(const Passkey_t passkey) { return BLE_ERROR_NONE; }; + + virtual ble_error_t setLinkSecurity(ble::connection_handle_t connectionHandle, SecurityMode_t securityMode) { return BLE_ERROR_NONE; }; + + virtual ble_error_t setKeypressNotification(bool enabled = true) { return BLE_ERROR_NONE; }; + +#if BLE_FEATURE_SIGNING + + virtual ble_error_t enableSigning(ble::connection_handle_t connectionHandle, bool enabled = true) { return BLE_ERROR_NONE; }; + +#endif // BLE_FEATURE_SIGNING + + virtual ble_error_t setHintFutureRoleReversal(bool enable = true) { return BLE_ERROR_NONE; }; + + //////////////////////////////////////////////////////////////////////////// + // Encryption + // + + virtual ble_error_t getLinkEncryption(ble::connection_handle_t connectionHandle, ble::link_encryption_t *encryption) { return BLE_ERROR_NONE; }; + + virtual ble_error_t setLinkEncryption(ble::connection_handle_t connectionHandle, ble::link_encryption_t encryption) { return BLE_ERROR_NONE; }; + + virtual ble_error_t setEncryptionKeyRequirements(uint8_t minimumByteSize, uint8_t maximumByteSize) { return BLE_ERROR_NONE; }; + + virtual ble_error_t getEncryptionKeySize( + connection_handle_t connectionHandle, + uint8_t *size + ) { return BLE_ERROR_NONE; }; + + //////////////////////////////////////////////////////////////////////////// + // Authentication + // + + virtual ble_error_t requestAuthentication(ble::connection_handle_t connectionHandle) { return BLE_ERROR_NONE; }; + + //////////////////////////////////////////////////////////////////////////// + // MITM + // + + virtual ble_error_t generateOOB(const ble::address_t *address) { return BLE_ERROR_NONE; }; + + virtual ble_error_t setOOBDataUsage(ble::connection_handle_t connectionHandle, bool useOOB, bool OOBProvidesMITM = true) { return BLE_ERROR_NONE; }; + + virtual ble_error_t passkeyEntered(ble::connection_handle_t connectionHandle, Passkey_t passkey) { return BLE_ERROR_NONE; }; + + virtual ble_error_t legacyPairingOobReceived(const ble::address_t *address, const ble::oob_tk_t *tk) { return BLE_ERROR_NONE; }; +#if BLE_FEATURE_SECURE_CONNECTIONS + virtual ble_error_t confirmationEntered(ble::connection_handle_t connectionHandle, bool confirmation) { return BLE_ERROR_NONE; }; + + virtual ble_error_t sendKeypressNotification(ble::connection_handle_t connectionHandle, ble::Keypress_t keypress) { return BLE_ERROR_NONE; }; + + virtual ble_error_t oobReceived( + const ble::address_t *address, + const ble::oob_lesc_value_t *random, + const ble::oob_confirm_t *confirm + ) { return BLE_ERROR_NONE; }; +#endif // BLE_FEATURE_SECURE_CONNECTIONS + + //////////////////////////////////////////////////////////////////////////// + // Keys + // +#if BLE_FEATURE_SIGNING + virtual ble_error_t getSigningKey(ble::connection_handle_t connectionHandle, bool authenticated) { return BLE_ERROR_NONE; }; +#endif // BLE_FEATURE_SIGNING + //////////////////////////////////////////////////////////////////////////// + // Privacy + // + +#if BLE_FEATURE_PRIVACY + virtual ble_error_t setPrivateAddressTimeout( + uint16_t timeout_in_seconds + ) { return BLE_ERROR_NONE; }; +#endif // BLE_FEATURE_PRIVACY + + /* Event callback handlers. */ +public: + + virtual void onShutdown(const SecurityManagerShutdownCallback_t &callback) { }; + + template + void onShutdown(T *objPtr, void (T::*memberPtr)(const SecurityManager *)) { }; + + virtual SecurityManagerShutdownCallbackChain_t &onShutdown() { static SecurityManagerShutdownCallbackChain_t chain; return chain; }; + + virtual void setSecurityManagerEventHandler(EventHandler *handler) { }; +}; + +} +} + +#endif //SECURITYMANAGERSTUB_H diff --git a/UNITTESTS/fakes/events/CMakeLists.txt b/UNITTESTS/fakes/events/CMakeLists.txt new file mode 100644 index 0000000000..e50f30ac10 --- /dev/null +++ b/UNITTESTS/fakes/events/CMakeLists.txt @@ -0,0 +1,20 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-fakes-event-queue) + +target_sources(mbed-fakes-event-queue + PRIVATE + events/EventQueue.cpp +) + +target_include_directories(mbed-fakes-event-queue + PUBLIC + . +) + +target_link_libraries(mbed-fakes-event-queue + PRIVATE + mbed-headers + gcov +) diff --git a/UNITTESTS/fakes/events/events/EventQueue.cpp b/UNITTESTS/fakes/events/events/EventQueue.cpp new file mode 100644 index 0000000000..4f937c240c --- /dev/null +++ b/UNITTESTS/fakes/events/events/EventQueue.cpp @@ -0,0 +1,120 @@ +/* mbed Microcontroller Library + * Copyright (c) 2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "EventQueue.h" + +namespace events { + +handle_t EventQueue::call_handler(function_t handler) +{ + return call_handler_in(0, handler); +} + +handle_t EventQueue::call_handler_in(tick_t ms, function_t handler) +{ + _handler_id++; + + _handlers.push_back( + internal_event{ + std::unique_ptr(new function_t(handler)), + _now + ms, + _handler_id + } + ); + + return _handler_id; +} + +bool EventQueue::cancel_handler(handle_t handle) +{ + if (!handle) { + return false; + } + + auto found = std::remove_if( + _handlers.begin(), + _handlers.end(), + [handle](internal_event& element) -> bool { + return (handle == element.handle); + } + ); + + if (found != _handlers.end()) { + _handlers.erase( + found, + _handlers.end() + ); + return true; + } + + return false; +} + +void EventQueue::process_events(tick_t duration_ms) +{ + // execute all events during the duration + for (uint64_t i = 0; i < duration_ms; ++i) { + process_events(); + _now++; + } + + // last round to execute immediate events + process_events(); +} + +void EventQueue::process_events() { + while (true) { + if (_handlers.empty()) { + return; + } + + /* to guarantee order we only dispatch one tick at a time*/ + auto smallest = std::min_element( + _handlers.begin(), + _handlers.end(), + [](internal_event& element, internal_event& smallest){ + return (element.tick < smallest.tick); + } + ); + tick_t earliest_tick = smallest->tick; + + /* stop if all elements happen later */ + if (earliest_tick > _now) { + return; + } + + /* dispatch all handlers that happen at this time */ + auto found = std::remove_if( + _handlers.begin(), + _handlers.end(), + [earliest_tick](internal_event& element) -> bool { + if (earliest_tick >= element.tick) { + (*(element.handler))(); + return true; + } else { + return false; + } + } + ); + + if (found != _handlers.end()) { + _handlers.erase(found, _handlers.end()); + } + } +} + +} diff --git a/UNITTESTS/fakes/events/events/EventQueue.h b/UNITTESTS/fakes/events/events/EventQueue.h new file mode 100644 index 0000000000..0e09cfe434 --- /dev/null +++ b/UNITTESTS/fakes/events/events/EventQueue.h @@ -0,0 +1,137 @@ +/* mbed Microcontroller Library + * Copyright (c) 2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef EVENTQUEUE_FAKE_H +#define EVENTQUEUE_FAKE_H + +#include +#include +#include +#include +#include +#include "events/EventQueue.h" +#include +#include + +namespace events { + +typedef int handle_t; +typedef std::function function_t; +typedef unsigned tick_t; + +class EventQueue { + using duration = std::chrono::duration; + +public: + EventQueue(unsigned size = 0, unsigned char *buffer = NULL) { delete buffer; }; + + ~EventQueue() { }; + + /** This will advance time by given amount of milliseconds and then dispatch all events that were set to happen in that time. + * + * @param ms number of miliseconds to advance time + */ + void dispatch(int milliseconds = -1) { + if (milliseconds > 0) { + process_events(milliseconds); + } else { + _now = (tick_t)-1; + process_events(); + _now = 0; + } + }; + + tick_t tick() { + return _now; + }; + + bool cancel(handle_t id) { + return cancel_handler(id); + }; + + /** Get number of events in queue. + * + * @return Number of events waiting in the queue. + */ + size_t size() const { + return _handlers.size(); + } + + template + handle_t call(F f, ArgTs... args) { + return call_handler( + [f, args = mstd::make_tuple(args...)]() { + mstd::apply(f, args); + } + ); + } + + template + handle_t call_in(duration ms, F f, ArgTs... args) { + return call_handler_in( + ms.count(), + [f, args = mstd::make_tuple(args...)]() { + mstd::apply(f, args); + } + ); + } + + template + int call(T *obj, R(T::*method)(ArgTs...), ArgTs... args) { + return call_handler( + [obj, method, args = mstd::make_tuple(args...)]() { + mstd::apply(method, obj, args); + } + ); + } + + template + int call_in(duration ms, T *obj, R(T::*method)(ArgTs...), ArgTs... args) { + return call_handler_in( + ms.count(), + [obj, method, args = mstd::make_tuple(args...)]() { + mstd::apply(method, obj, args); + } + ); + } + +private: + handle_t call_handler(function_t handler); + + handle_t call_handler_in(tick_t ms, function_t handler); + + bool cancel_handler(handle_t handle); + + void process_events(tick_t duration_ms); + + void process_events(); + +private: + struct internal_event { + std::unique_ptr handler; + tick_t tick; + handle_t handle; + }; + + std::vector _handlers; + tick_t _now = 0; + handle_t _handler_id = 0; +}; + +} + +#endif //EVENTQUEUE_FAKE_H diff --git a/UNITTESTS/mbed_unittest.py b/UNITTESTS/mbed_unittest.py index 41039b0354..9312c38bfe 100755 --- a/UNITTESTS/mbed_unittest.py +++ b/UNITTESTS/mbed_unittest.py @@ -1,7 +1,7 @@ #!/usr/bin/env python """ -Copyright (c) 2018, Arm Limited +Copyright (c) 2018-2021, Arm Limited SPDX-License-Identifier: Apache-2.0 Licensed under the Apache License, Version 2.0 (the "License"); @@ -71,9 +71,8 @@ def _mbed_unittest_test(options, cwd, pwd): clean=options.clean) if options.compile_only: - # Create makefiles - src_path = os.path.relpath(pwd, options.build) - tool.create_makefiles(path_to_src=src_path, + # Create makefiles + tool.create_makefiles(path_to_src=cwd, generator=options.cmake_generator, coverage_output_type=options.coverage, debug=options.debug_build, diff --git a/UNITTESTS/stubs/CMakeLists.txt b/UNITTESTS/stubs/CMakeLists.txt new file mode 100644 index 0000000000..69195ef31e --- /dev/null +++ b/UNITTESTS/stubs/CMakeLists.txt @@ -0,0 +1,140 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-stubs-headers INTERFACE) +add_library(mbed-headers INTERFACE) +add_library(mbed-headers-base INTERFACE) +add_library(mbed-headers-platform INTERFACE) +add_library(mbed-headers-connectivity INTERFACE) +add_library(mbed-headers-storage INTERFACE) +add_library(mbed-headers-hal INTERFACE) +add_library(mbed-headers-events INTERFACE) +add_library(mbed-headers-rtos INTERFACE) + +target_link_libraries(mbed-headers + INTERFACE + mbed-headers-base + mbed-headers-platform + mbed-headers-connectivity + mbed-headers-storage + mbed-headers-drivers + mbed-headers-hal + mbed-headers-events + mbed-headers-rtos +) + +target_include_directories(mbed-headers-platform + INTERFACE + ${mbed-os_SOURCE_DIR}/platform/include + ${mbed-os_SOURCE_DIR}/platform/include/platform + ${mbed-os_SOURCE_DIR}/platform/randlib/include/mbed-client-randlib/ + ${mbed-os_SOURCE_DIR}/platform/randlib/include/ + ${mbed-os_SOURCE_DIR}/platform/mbed-trace/include +) + +target_include_directories(mbed-headers-base + INTERFACE + ${mbed-os_SOURCE_DIR}/UNITTESTS/target_h + ${mbed-os_SOURCE_DIR}/UNITTESTS/target_h/platform + ${mbed-os_SOURCE_DIR}/UNITTESTS/target_h/platform/cxxsupport + ${mbed-os_SOURCE_DIR}/UNITTESTS/target_h/drivers + ${mbed-os_SOURCE_DIR}/UNITTESTS/target_h/rtos/include + ${mbed-os_SOURCE_DIR}/UNITTESTS/target_h/rtos + ${mbed-os_SOURCE_DIR}/UNITTESTS/target_h/sys +) + +target_include_directories(mbed-headers-storage + INTERFACE + ${mbed-os_SOURCE_DIR}/storage/filesystem/fat/include + ${mbed-os_SOURCE_DIR}/storage/filesystem/fat/ChaN + ${mbed-os_SOURCE_DIR}/storage/filesystem/littlefs + ${mbed-os_SOURCE_DIR}/storage/filesystem/littlefs/include + ${mbed-os_SOURCE_DIR}/storage/filesystem/littlefsv2/littlefs + ${mbed-os_SOURCE_DIR}/storage/filesystem/littlefsv2/littlefs/bd + ${mbed-os_SOURCE_DIR}/storage/filesystem/littlefs/littlefs + ${mbed-os_SOURCE_DIR}/storage/blockdevice/include + ${mbed-os_SOURCE_DIR}/storage/filesystem/include + ${mbed-os_SOURCE_DIR}/storage/kvstore/include + ${mbed-os_SOURCE_DIR}/storage/kvstore/kv_config + ${mbed-os_SOURCE_DIR}/storage/kvstore/kv_config/include + ${mbed-os_SOURCE_DIR}/storage/kvstore/tdbstore/include + ${mbed-os_SOURCE_DIR}/storage/kvstore/filesystemstore/include + ${mbed-os_SOURCE_DIR}/storage/kvstore/kvstore_global_api/include + ${mbed-os_SOURCE_DIR}/storage/blockdevice/include/blockdevice +) + +target_include_directories(mbed-headers-connectivity + INTERFACE + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/mbed-client-libservice + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/include + ${mbed-os_SOURCE_DIR}/connectivity/cellular/include/cellular/framework/API + ${mbed-os_SOURCE_DIR}/connectivity/cellular/include/cellular/framework/AT + ${mbed-os_SOURCE_DIR}/connectivity/cellular/include/cellular/framework/device + ${mbed-os_SOURCE_DIR}/connectivity/cellular/include/cellular/framework + ${mbed-os_SOURCE_DIR}/connectivity/cellular/include/cellular/framework/common + ${mbed-os_SOURCE_DIR}/connectivity + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/include/lorawan + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/mac + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/phy + ${mbed-os_SOURCE_DIR}/connectivity/lorawan + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/system + ${mbed-os_SOURCE_DIR}/connectivity/mbedtls + ${mbed-os_SOURCE_DIR}/connectivity/mbedtls/include + ${mbed-os_SOURCE_DIR}/connectivity/FEATURE_BLE/include + ${mbed-os_SOURCE_DIR}/connectivity/FEATURE_BLE/include/ble +) + +target_include_directories(mbed-headers-events + INTERFACE + ${mbed-os_SOURCE_DIR}/events/tests/UNITTESTS/target_h + ${mbed-os_SOURCE_DIR}/events/tests/UNITTESTS/target_h/equeue + ${mbed-os_SOURCE_DIR}/events/include + ${mbed-os_SOURCE_DIR}/events/include/events + ${mbed-os_SOURCE_DIR}/events/include/events/internal +) + +target_include_directories(mbed-headers-hal + INTERFACE + ${mbed-os_SOURCE_DIR}/hal + ${mbed-os_SOURCE_DIR}/hal/include +) + +target_include_directories(mbed-headers-rtos + INTERFACE + ${mbed-os_SOURCE_DIR}/rtos/include + ${mbed-os_SOURCE_DIR}/rtos/include/rtos +) + +target_include_directories(mbed-headers + INTERFACE + ${mbed-os_SOURCE_DIR}/features + ${mbed-os_SOURCE_DIR}/features/frameworks +) + +target_include_directories(mbed-stubs-headers + INTERFACE + . + ${mbed-os_SOURCE_DIR}/connectivity/nanostack/coap-service/test/coap-service/unittest/stub +) + +add_subdirectory(connectivity) +add_subdirectory(events) +add_subdirectory(hal) +add_subdirectory(platform) +add_subdirectory(rtos) +add_subdirectory(storage) + +add_library(mbed-stubs INTERFACE) + +target_link_libraries(mbed-stubs + INTERFACE + mbed-stubs-connectivity + mbed-stubs-drivers + mbed-stubs-events + mbed-stubs-hal + mbed-stubs-platform + mbed-stubs-rtos + mbed-stubs-storage +) diff --git a/UNITTESTS/stubs/FileHandle_stub.h b/UNITTESTS/stubs/FileHandle_stub.h index af8c6cc2b1..5dacb0b459 100644 --- a/UNITTESTS/stubs/FileHandle_stub.h +++ b/UNITTESTS/stubs/FileHandle_stub.h @@ -67,6 +67,7 @@ public: virtual int close() { + return 0; } virtual short poll(short events) const diff --git a/UNITTESTS/stubs/ATHandler_stub.cpp b/UNITTESTS/stubs/connectivity/ATHandler_stub.cpp similarity index 100% rename from UNITTESTS/stubs/ATHandler_stub.cpp rename to UNITTESTS/stubs/connectivity/ATHandler_stub.cpp diff --git a/UNITTESTS/stubs/AT_CellularContext_stub.cpp b/UNITTESTS/stubs/connectivity/AT_CellularContext_stub.cpp similarity index 100% rename from UNITTESTS/stubs/AT_CellularContext_stub.cpp rename to UNITTESTS/stubs/connectivity/AT_CellularContext_stub.cpp diff --git a/UNITTESTS/stubs/AT_CellularDevice_stub.cpp b/UNITTESTS/stubs/connectivity/AT_CellularDevice_stub.cpp similarity index 99% rename from UNITTESTS/stubs/AT_CellularDevice_stub.cpp rename to UNITTESTS/stubs/connectivity/AT_CellularDevice_stub.cpp index f8fd1b699d..f65362bcde 100644 --- a/UNITTESTS/stubs/AT_CellularDevice_stub.cpp +++ b/UNITTESTS/stubs/connectivity/AT_CellularDevice_stub.cpp @@ -56,6 +56,7 @@ ATHandler *AT_CellularDevice::get_at_handler() CellularContext *create_context(const char *apn) { + return nullptr; } void delete_context(CellularContext *context) diff --git a/UNITTESTS/stubs/AT_CellularInformation_stub.cpp b/UNITTESTS/stubs/connectivity/AT_CellularInformation_stub.cpp similarity index 100% rename from UNITTESTS/stubs/AT_CellularInformation_stub.cpp rename to UNITTESTS/stubs/connectivity/AT_CellularInformation_stub.cpp diff --git a/UNITTESTS/stubs/AT_CellularNetwork_stub.cpp b/UNITTESTS/stubs/connectivity/AT_CellularNetwork_stub.cpp similarity index 100% rename from UNITTESTS/stubs/AT_CellularNetwork_stub.cpp rename to UNITTESTS/stubs/connectivity/AT_CellularNetwork_stub.cpp diff --git a/UNITTESTS/stubs/AT_CellularSMS_stub.cpp b/UNITTESTS/stubs/connectivity/AT_CellularSMS_stub.cpp similarity index 100% rename from UNITTESTS/stubs/AT_CellularSMS_stub.cpp rename to UNITTESTS/stubs/connectivity/AT_CellularSMS_stub.cpp diff --git a/UNITTESTS/stubs/AT_CellularStack_stub.cpp b/UNITTESTS/stubs/connectivity/AT_CellularStack_stub.cpp similarity index 100% rename from UNITTESTS/stubs/AT_CellularStack_stub.cpp rename to UNITTESTS/stubs/connectivity/AT_CellularStack_stub.cpp diff --git a/UNITTESTS/stubs/AT_ControlPlane_netif_stub.cpp b/UNITTESTS/stubs/connectivity/AT_ControlPlane_netif_stub.cpp similarity index 100% rename from UNITTESTS/stubs/AT_ControlPlane_netif_stub.cpp rename to UNITTESTS/stubs/connectivity/AT_ControlPlane_netif_stub.cpp diff --git a/UNITTESTS/stubs/connectivity/CMakeLists.txt b/UNITTESTS/stubs/connectivity/CMakeLists.txt new file mode 100644 index 0000000000..4f207f24e0 --- /dev/null +++ b/UNITTESTS/stubs/connectivity/CMakeLists.txt @@ -0,0 +1,64 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-stubs-connectivity) + +target_compile_definitions(mbed-stubs-connectivity + PRIVATE + DEVICE_SERIAL=1 + DEVICE_INTERRUPTIN=1 + MBED_CONF_CELLULAR_USE_SMS=1 + MBED_CONF_NSAPI_DEFAULT_CELLULAR_APN=NULL + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 + MBED_CONF_LORA_OVER_THE_AIR_ACTIVATION=true + MBED_CONF_LORA_AUTOMATIC_UPLINK_MESSAGE=true + MBED_CONF_LORA_TX_MAX_SIZE=255 + MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 + MDMTXD=NC + MDMRXD=NC +) + +target_sources(mbed-stubs-connectivity + PRIVATE + aes_stub.c + AT_CellularContext_stub.cpp + AT_CellularDevice_stub.cpp + AT_CellularInformation_stub.cpp + AT_CellularNetwork_stub.cpp + AT_CellularSMS_stub.cpp + AT_CellularStack_stub.cpp + AT_ControlPlane_netif_stub.cpp + ATHandler_stub.cpp + CellularContext_stub.cpp + CellularDevice_stub.cpp + CellularInterface_stub.cpp + CellularStateMachine_stub.cpp + CellularUtil_stub.cpp + cipher_stub.c + cmac_stub.c + ip4tos_stub.c + LoRaMacChannelPlan_stub.cpp + LoRaMacCommand_stub.cpp + LoRaMacCrypto_stub.cpp + LoRaMac_stub.cpp + LoRaPHYEU868_stub.cpp + LoRaPHY_stub.cpp + LoRaWANStack_stub.cpp + LoRaWANTimer_stub.cpp + MeshInterface_stub.cpp + NetworkInterfaceDefaults_stub.cpp + NetworkInterface_stub.cpp + NetworkStack_stub.cpp + nsapi_dns_stub.cpp + SocketAddress_stub.cpp + SocketStats_Stub.cpp + stoip4_stub.c + ${mbed-os_SOURCE_DIR}/connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c +) + +target_link_libraries(mbed-stubs-connectivity + PRIVATE + mbed-headers + mbed-stubs-headers + gtest +) diff --git a/UNITTESTS/stubs/CellularContext_stub.cpp b/UNITTESTS/stubs/connectivity/CellularContext_stub.cpp similarity index 100% rename from UNITTESTS/stubs/CellularContext_stub.cpp rename to UNITTESTS/stubs/connectivity/CellularContext_stub.cpp diff --git a/UNITTESTS/stubs/CellularDevice_stub.cpp b/UNITTESTS/stubs/connectivity/CellularDevice_stub.cpp similarity index 100% rename from UNITTESTS/stubs/CellularDevice_stub.cpp rename to UNITTESTS/stubs/connectivity/CellularDevice_stub.cpp diff --git a/UNITTESTS/stubs/CellularInterface_stub.cpp b/UNITTESTS/stubs/connectivity/CellularInterface_stub.cpp similarity index 100% rename from UNITTESTS/stubs/CellularInterface_stub.cpp rename to UNITTESTS/stubs/connectivity/CellularInterface_stub.cpp diff --git a/UNITTESTS/stubs/CellularStateMachine_stub.cpp b/UNITTESTS/stubs/connectivity/CellularStateMachine_stub.cpp similarity index 100% rename from UNITTESTS/stubs/CellularStateMachine_stub.cpp rename to UNITTESTS/stubs/connectivity/CellularStateMachine_stub.cpp diff --git a/UNITTESTS/stubs/CellularUtil_stub.cpp b/UNITTESTS/stubs/connectivity/CellularUtil_stub.cpp similarity index 100% rename from UNITTESTS/stubs/CellularUtil_stub.cpp rename to UNITTESTS/stubs/connectivity/CellularUtil_stub.cpp diff --git a/UNITTESTS/stubs/LoRaMacChannelPlan_stub.cpp b/UNITTESTS/stubs/connectivity/LoRaMacChannelPlan_stub.cpp similarity index 100% rename from UNITTESTS/stubs/LoRaMacChannelPlan_stub.cpp rename to UNITTESTS/stubs/connectivity/LoRaMacChannelPlan_stub.cpp diff --git a/UNITTESTS/stubs/LoRaMacCommand_stub.cpp b/UNITTESTS/stubs/connectivity/LoRaMacCommand_stub.cpp similarity index 100% rename from UNITTESTS/stubs/LoRaMacCommand_stub.cpp rename to UNITTESTS/stubs/connectivity/LoRaMacCommand_stub.cpp diff --git a/UNITTESTS/stubs/LoRaMacCrypto_stub.cpp b/UNITTESTS/stubs/connectivity/LoRaMacCrypto_stub.cpp similarity index 100% rename from UNITTESTS/stubs/LoRaMacCrypto_stub.cpp rename to UNITTESTS/stubs/connectivity/LoRaMacCrypto_stub.cpp diff --git a/UNITTESTS/stubs/LoRaMac_stub.cpp b/UNITTESTS/stubs/connectivity/LoRaMac_stub.cpp similarity index 99% rename from UNITTESTS/stubs/LoRaMac_stub.cpp rename to UNITTESTS/stubs/connectivity/LoRaMac_stub.cpp index 083115d38a..22895fe246 100644 --- a/UNITTESTS/stubs/LoRaMac_stub.cpp +++ b/UNITTESTS/stubs/connectivity/LoRaMac_stub.cpp @@ -94,6 +94,7 @@ void LoRaMac::post_process_mlme_ind() lorawan_time_t LoRaMac::get_current_time(void) { + return 0; } rx_slot_t LoRaMac::get_current_slot(void) diff --git a/UNITTESTS/stubs/LoRaPHYEU868_stub.cpp b/UNITTESTS/stubs/connectivity/LoRaPHYEU868_stub.cpp similarity index 100% rename from UNITTESTS/stubs/LoRaPHYEU868_stub.cpp rename to UNITTESTS/stubs/connectivity/LoRaPHYEU868_stub.cpp diff --git a/UNITTESTS/stubs/LoRaPHY_stub.cpp b/UNITTESTS/stubs/connectivity/LoRaPHY_stub.cpp similarity index 100% rename from UNITTESTS/stubs/LoRaPHY_stub.cpp rename to UNITTESTS/stubs/connectivity/LoRaPHY_stub.cpp diff --git a/UNITTESTS/stubs/LoRaWANStack_stub.cpp b/UNITTESTS/stubs/connectivity/LoRaWANStack_stub.cpp similarity index 100% rename from UNITTESTS/stubs/LoRaWANStack_stub.cpp rename to UNITTESTS/stubs/connectivity/LoRaWANStack_stub.cpp diff --git a/UNITTESTS/stubs/LoRaWANTimer_stub.cpp b/UNITTESTS/stubs/connectivity/LoRaWANTimer_stub.cpp similarity index 100% rename from UNITTESTS/stubs/LoRaWANTimer_stub.cpp rename to UNITTESTS/stubs/connectivity/LoRaWANTimer_stub.cpp diff --git a/UNITTESTS/stubs/MeshInterface_stub.cpp b/UNITTESTS/stubs/connectivity/MeshInterface_stub.cpp similarity index 100% rename from UNITTESTS/stubs/MeshInterface_stub.cpp rename to UNITTESTS/stubs/connectivity/MeshInterface_stub.cpp diff --git a/UNITTESTS/stubs/NetworkInterfaceDefaults_stub.cpp b/UNITTESTS/stubs/connectivity/NetworkInterfaceDefaults_stub.cpp similarity index 100% rename from UNITTESTS/stubs/NetworkInterfaceDefaults_stub.cpp rename to UNITTESTS/stubs/connectivity/NetworkInterfaceDefaults_stub.cpp diff --git a/UNITTESTS/stubs/NetworkInterface_stub.cpp b/UNITTESTS/stubs/connectivity/NetworkInterface_stub.cpp similarity index 100% rename from UNITTESTS/stubs/NetworkInterface_stub.cpp rename to UNITTESTS/stubs/connectivity/NetworkInterface_stub.cpp diff --git a/UNITTESTS/stubs/NetworkStack_stub.cpp b/UNITTESTS/stubs/connectivity/NetworkStack_stub.cpp similarity index 100% rename from UNITTESTS/stubs/NetworkStack_stub.cpp rename to UNITTESTS/stubs/connectivity/NetworkStack_stub.cpp diff --git a/UNITTESTS/stubs/SocketAddress_stub.cpp b/UNITTESTS/stubs/connectivity/SocketAddress_stub.cpp similarity index 100% rename from UNITTESTS/stubs/SocketAddress_stub.cpp rename to UNITTESTS/stubs/connectivity/SocketAddress_stub.cpp diff --git a/UNITTESTS/stubs/SocketStats_Stub.cpp b/UNITTESTS/stubs/connectivity/SocketStats_Stub.cpp similarity index 100% rename from UNITTESTS/stubs/SocketStats_Stub.cpp rename to UNITTESTS/stubs/connectivity/SocketStats_Stub.cpp diff --git a/UNITTESTS/stubs/aes_stub.c b/UNITTESTS/stubs/connectivity/aes_stub.c similarity index 100% rename from UNITTESTS/stubs/aes_stub.c rename to UNITTESTS/stubs/connectivity/aes_stub.c diff --git a/UNITTESTS/stubs/cipher_stub.c b/UNITTESTS/stubs/connectivity/cipher_stub.c similarity index 100% rename from UNITTESTS/stubs/cipher_stub.c rename to UNITTESTS/stubs/connectivity/cipher_stub.c diff --git a/UNITTESTS/stubs/cmac_stub.c b/UNITTESTS/stubs/connectivity/cmac_stub.c similarity index 100% rename from UNITTESTS/stubs/cmac_stub.c rename to UNITTESTS/stubs/connectivity/cmac_stub.c diff --git a/UNITTESTS/stubs/ip4tos_stub.c b/UNITTESTS/stubs/connectivity/ip4tos_stub.c similarity index 100% rename from UNITTESTS/stubs/ip4tos_stub.c rename to UNITTESTS/stubs/connectivity/ip4tos_stub.c diff --git a/UNITTESTS/stubs/nsapi_dns_stub.cpp b/UNITTESTS/stubs/connectivity/nsapi_dns_stub.cpp similarity index 100% rename from UNITTESTS/stubs/nsapi_dns_stub.cpp rename to UNITTESTS/stubs/connectivity/nsapi_dns_stub.cpp diff --git a/UNITTESTS/stubs/stoip4_stub.c b/UNITTESTS/stubs/connectivity/stoip4_stub.c similarity index 100% rename from UNITTESTS/stubs/stoip4_stub.c rename to UNITTESTS/stubs/connectivity/stoip4_stub.c diff --git a/UNITTESTS/stubs/events/CMakeLists.txt b/UNITTESTS/stubs/events/CMakeLists.txt new file mode 100644 index 0000000000..c0127aab56 --- /dev/null +++ b/UNITTESTS/stubs/events/CMakeLists.txt @@ -0,0 +1,19 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-stubs-events) + +target_sources(mbed-stubs-events + PRIVATE + equeue_stub.c + ${mbed-os_SOURCE_DIR}/events/tests/UNITTESTS/stubs/EqueuePosix_stub.c + EventFlags_stub.cpp + EventQueue_stub.cpp + mbed_shared_queues_stub.cpp +) + +target_link_libraries(mbed-stubs-events + PRIVATE + mbed-headers + mbed-stubs-headers +) diff --git a/UNITTESTS/stubs/EventFlags_stub.cpp b/UNITTESTS/stubs/events/EventFlags_stub.cpp similarity index 100% rename from UNITTESTS/stubs/EventFlags_stub.cpp rename to UNITTESTS/stubs/events/EventFlags_stub.cpp diff --git a/UNITTESTS/stubs/EventQueue_stub.cpp b/UNITTESTS/stubs/events/EventQueue_stub.cpp similarity index 100% rename from UNITTESTS/stubs/EventQueue_stub.cpp rename to UNITTESTS/stubs/events/EventQueue_stub.cpp diff --git a/UNITTESTS/stubs/equeue_stub.c b/UNITTESTS/stubs/events/equeue_stub.c similarity index 99% rename from UNITTESTS/stubs/equeue_stub.c rename to UNITTESTS/stubs/events/equeue_stub.c index 125e57ce1e..5b6a068c4a 100644 --- a/UNITTESTS/stubs/equeue_stub.c +++ b/UNITTESTS/stubs/events/equeue_stub.c @@ -105,7 +105,7 @@ void equeue_background(equeue_t *queue, int equeue_chain(equeue_t *queue, equeue_t *target) { - + return 0; } int equeue_call_in(equeue_t *q, int ms, void (*cb)(void *), void *data) diff --git a/UNITTESTS/stubs/mbed_shared_queues_stub.cpp b/UNITTESTS/stubs/events/mbed_shared_queues_stub.cpp similarity index 100% rename from UNITTESTS/stubs/mbed_shared_queues_stub.cpp rename to UNITTESTS/stubs/events/mbed_shared_queues_stub.cpp diff --git a/UNITTESTS/stubs/hal/CMakeLists.txt b/UNITTESTS/stubs/hal/CMakeLists.txt new file mode 100644 index 0000000000..a327d31efc --- /dev/null +++ b/UNITTESTS/stubs/hal/CMakeLists.txt @@ -0,0 +1,29 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-stubs-hal) + +target_compile_definitions(mbed-stubs-hal + PRIVATE + DEVICE_PWMOUT + DEVICE_WATCHDOG + MBED_WDOG_ASSERT=1 +) + +target_sources(mbed-stubs-hal + PRIVATE + pwmout_api_stub.c + us_ticker_stub.cpp + watchdog_api_stub.c +) + +target_link_options(mbed-stubs-hal + PRIVATE + --coverage +) + +target_link_libraries(mbed-stubs-hal + PRIVATE + mbed-headers + mbed-stubs-headers +) diff --git a/UNITTESTS/stubs/pwmout_api_stub.c b/UNITTESTS/stubs/hal/pwmout_api_stub.c similarity index 100% rename from UNITTESTS/stubs/pwmout_api_stub.c rename to UNITTESTS/stubs/hal/pwmout_api_stub.c diff --git a/UNITTESTS/stubs/us_ticker_stub.cpp b/UNITTESTS/stubs/hal/us_ticker_stub.cpp similarity index 100% rename from UNITTESTS/stubs/us_ticker_stub.cpp rename to UNITTESTS/stubs/hal/us_ticker_stub.cpp diff --git a/UNITTESTS/stubs/watchdog_api_stub.c b/UNITTESTS/stubs/hal/watchdog_api_stub.c similarity index 100% rename from UNITTESTS/stubs/watchdog_api_stub.c rename to UNITTESTS/stubs/hal/watchdog_api_stub.c diff --git a/UNITTESTS/stubs/platform/CMakeLists.txt b/UNITTESTS/stubs/platform/CMakeLists.txt new file mode 100644 index 0000000000..051bc67877 --- /dev/null +++ b/UNITTESTS/stubs/platform/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-stubs-platform) + +target_sources(mbed-stubs-platform + PRIVATE + mbed_critical_stub.c + mbed_atomic_stub.c + mbed_error.c + mbed_poll_stub.cpp + mbed_assert_stub.cpp + mbed_wait_api_stub.cpp + mbed_retarget_stub.cpp + FileHandle_stub.cpp + nvic_wrapper_stub.c + randLIB_stub.c + randLIB_stub.cpp +) + +target_link_options(mbed-stubs-platform + PRIVATE + --coverage +) + +target_link_libraries(mbed-stubs-platform + PRIVATE + mbed-headers + mbed-stubs-headers +) diff --git a/UNITTESTS/stubs/FileHandle_stub.cpp b/UNITTESTS/stubs/platform/FileHandle_stub.cpp similarity index 100% rename from UNITTESTS/stubs/FileHandle_stub.cpp rename to UNITTESTS/stubs/platform/FileHandle_stub.cpp diff --git a/UNITTESTS/stubs/mbed_assert_stub.cpp b/UNITTESTS/stubs/platform/mbed_assert_stub.cpp similarity index 100% rename from UNITTESTS/stubs/mbed_assert_stub.cpp rename to UNITTESTS/stubs/platform/mbed_assert_stub.cpp diff --git a/UNITTESTS/stubs/mbed_atomic_stub.c b/UNITTESTS/stubs/platform/mbed_atomic_stub.c similarity index 100% rename from UNITTESTS/stubs/mbed_atomic_stub.c rename to UNITTESTS/stubs/platform/mbed_atomic_stub.c diff --git a/UNITTESTS/stubs/mbed_critical_stub.c b/UNITTESTS/stubs/platform/mbed_critical_stub.c similarity index 100% rename from UNITTESTS/stubs/mbed_critical_stub.c rename to UNITTESTS/stubs/platform/mbed_critical_stub.c diff --git a/UNITTESTS/stubs/mbed_error.c b/UNITTESTS/stubs/platform/mbed_error.c similarity index 100% rename from UNITTESTS/stubs/mbed_error.c rename to UNITTESTS/stubs/platform/mbed_error.c diff --git a/UNITTESTS/stubs/mbed_poll_stub.cpp b/UNITTESTS/stubs/platform/mbed_poll_stub.cpp similarity index 100% rename from UNITTESTS/stubs/mbed_poll_stub.cpp rename to UNITTESTS/stubs/platform/mbed_poll_stub.cpp diff --git a/UNITTESTS/stubs/mbed_retarget_stub.cpp b/UNITTESTS/stubs/platform/mbed_retarget_stub.cpp similarity index 100% rename from UNITTESTS/stubs/mbed_retarget_stub.cpp rename to UNITTESTS/stubs/platform/mbed_retarget_stub.cpp diff --git a/UNITTESTS/stubs/mbed_wait_api_stub.cpp b/UNITTESTS/stubs/platform/mbed_wait_api_stub.cpp similarity index 100% rename from UNITTESTS/stubs/mbed_wait_api_stub.cpp rename to UNITTESTS/stubs/platform/mbed_wait_api_stub.cpp diff --git a/UNITTESTS/stubs/nvic_wrapper_stub.c b/UNITTESTS/stubs/platform/nvic_wrapper_stub.c similarity index 100% rename from UNITTESTS/stubs/nvic_wrapper_stub.c rename to UNITTESTS/stubs/platform/nvic_wrapper_stub.c diff --git a/UNITTESTS/stubs/randLIB_stub.c b/UNITTESTS/stubs/platform/randLIB_stub.c similarity index 100% rename from UNITTESTS/stubs/randLIB_stub.c rename to UNITTESTS/stubs/platform/randLIB_stub.c diff --git a/UNITTESTS/stubs/randLIB_stub.cpp b/UNITTESTS/stubs/platform/randLIB_stub.cpp similarity index 100% rename from UNITTESTS/stubs/randLIB_stub.cpp rename to UNITTESTS/stubs/platform/randLIB_stub.cpp diff --git a/UNITTESTS/stubs/rtos/CMakeLists.txt b/UNITTESTS/stubs/rtos/CMakeLists.txt new file mode 100644 index 0000000000..fc9a759b8d --- /dev/null +++ b/UNITTESTS/stubs/rtos/CMakeLists.txt @@ -0,0 +1,22 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-stubs-rtos) + +target_sources(mbed-stubs-rtos + PRIVATE + ConditionVariable_stub.cpp + Kernel_stub.cpp + mbed_rtos_rtx_stub.c + Mutex_stub.cpp + rtx_mutex_stub.c + Semaphore_stub.cpp + ThisThread_stub.cpp + Thread_stub.cpp +) + +target_link_libraries(mbed-stubs-rtos + PRIVATE + mbed-headers + mbed-stubs-headers +) diff --git a/UNITTESTS/stubs/ConditionVariable_stub.cpp b/UNITTESTS/stubs/rtos/ConditionVariable_stub.cpp similarity index 100% rename from UNITTESTS/stubs/ConditionVariable_stub.cpp rename to UNITTESTS/stubs/rtos/ConditionVariable_stub.cpp diff --git a/UNITTESTS/stubs/Kernel_stub.cpp b/UNITTESTS/stubs/rtos/Kernel_stub.cpp similarity index 100% rename from UNITTESTS/stubs/Kernel_stub.cpp rename to UNITTESTS/stubs/rtos/Kernel_stub.cpp diff --git a/UNITTESTS/stubs/Mutex_stub.cpp b/UNITTESTS/stubs/rtos/Mutex_stub.cpp similarity index 100% rename from UNITTESTS/stubs/Mutex_stub.cpp rename to UNITTESTS/stubs/rtos/Mutex_stub.cpp diff --git a/UNITTESTS/stubs/Semaphore_stub.cpp b/UNITTESTS/stubs/rtos/Semaphore_stub.cpp similarity index 100% rename from UNITTESTS/stubs/Semaphore_stub.cpp rename to UNITTESTS/stubs/rtos/Semaphore_stub.cpp diff --git a/UNITTESTS/stubs/ThisThread_stub.cpp b/UNITTESTS/stubs/rtos/ThisThread_stub.cpp similarity index 100% rename from UNITTESTS/stubs/ThisThread_stub.cpp rename to UNITTESTS/stubs/rtos/ThisThread_stub.cpp diff --git a/UNITTESTS/stubs/Thread_stub.cpp b/UNITTESTS/stubs/rtos/Thread_stub.cpp similarity index 100% rename from UNITTESTS/stubs/Thread_stub.cpp rename to UNITTESTS/stubs/rtos/Thread_stub.cpp diff --git a/UNITTESTS/stubs/mbed_rtos_rtx_stub.c b/UNITTESTS/stubs/rtos/mbed_rtos_rtx_stub.c similarity index 96% rename from UNITTESTS/stubs/mbed_rtos_rtx_stub.c rename to UNITTESTS/stubs/rtos/mbed_rtos_rtx_stub.c index aa45009fa5..889065cbcb 100644 --- a/UNITTESTS/stubs/mbed_rtos_rtx_stub.c +++ b/UNITTESTS/stubs/rtos/mbed_rtos_rtx_stub.c @@ -15,6 +15,6 @@ * limitations under the License. */ -#include "cmsis_os2.h" +#include "mbed_rtos_types.h" osMutexId_t singleton_mutex_id; diff --git a/UNITTESTS/stubs/rtx_mutex_stub.c b/UNITTESTS/stubs/rtos/rtx_mutex_stub.c similarity index 96% rename from UNITTESTS/stubs/rtx_mutex_stub.c rename to UNITTESTS/stubs/rtos/rtx_mutex_stub.c index de5aed92bd..916be3ee95 100644 --- a/UNITTESTS/stubs/rtx_mutex_stub.c +++ b/UNITTESTS/stubs/rtos/rtx_mutex_stub.c @@ -15,7 +15,7 @@ * limitations under the License. */ -#include "cmsis_os2.h" +#include "mbed_rtos_types.h" osStatus_t osMutexAcquire(osMutexId_t mutex_id, uint32_t timeout) { diff --git a/UNITTESTS/stubs/BufferedBlockDevice_stub.cpp b/UNITTESTS/stubs/storage/BufferedBlockDevice_stub.cpp similarity index 100% rename from UNITTESTS/stubs/BufferedBlockDevice_stub.cpp rename to UNITTESTS/stubs/storage/BufferedBlockDevice_stub.cpp diff --git a/UNITTESTS/stubs/storage/CMakeLists.txt b/UNITTESTS/stubs/storage/CMakeLists.txt new file mode 100644 index 0000000000..721f0f1d92 --- /dev/null +++ b/UNITTESTS/stubs/storage/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-stubs-storage) + +target_sources(mbed-stubs-storage + PRIVATE + BufferedBlockDevice_stub.cpp + ChainingBlockDevice_stub.cpp + EmulatedSD.cpp + ExhaustibleBlockDevice_stub.cpp + FlashSimBlockDevice_stub.cpp + HeapBlockDevice_stub.cpp + MBRBlockDevice_stub.cpp + ObservingBlockDevice_stub.cpp + ProfilingBlockDevice_stub.cpp + ReadOnlyBlockDevice_stub.cpp + SlicingBlockDevice_stub.cpp + kv_config_stub.cpp +) + +target_link_libraries(mbed-stubs-storage + PRIVATE + mbed-headers + mbed-stubs-headers +) diff --git a/UNITTESTS/stubs/ChainingBlockDevice_stub.cpp b/UNITTESTS/stubs/storage/ChainingBlockDevice_stub.cpp similarity index 100% rename from UNITTESTS/stubs/ChainingBlockDevice_stub.cpp rename to UNITTESTS/stubs/storage/ChainingBlockDevice_stub.cpp diff --git a/UNITTESTS/stubs/EmulatedSD.cpp b/UNITTESTS/stubs/storage/EmulatedSD.cpp similarity index 99% rename from UNITTESTS/stubs/EmulatedSD.cpp rename to UNITTESTS/stubs/storage/EmulatedSD.cpp index ff2192e729..9b9fe83477 100644 --- a/UNITTESTS/stubs/EmulatedSD.cpp +++ b/UNITTESTS/stubs/storage/EmulatedSD.cpp @@ -62,6 +62,7 @@ int EmulatedSD::deinit() { fclose(_p->fs); _p->fs = nullptr; + return 0; } int EmulatedSD::read(void *buffer, bd_addr_t addr, bd_size_t size) diff --git a/UNITTESTS/stubs/ExhaustibleBlockDevice_stub.cpp b/UNITTESTS/stubs/storage/ExhaustibleBlockDevice_stub.cpp similarity index 100% rename from UNITTESTS/stubs/ExhaustibleBlockDevice_stub.cpp rename to UNITTESTS/stubs/storage/ExhaustibleBlockDevice_stub.cpp diff --git a/UNITTESTS/stubs/FlashSimBlockDevice_stub.cpp b/UNITTESTS/stubs/storage/FlashSimBlockDevice_stub.cpp similarity index 100% rename from UNITTESTS/stubs/FlashSimBlockDevice_stub.cpp rename to UNITTESTS/stubs/storage/FlashSimBlockDevice_stub.cpp diff --git a/UNITTESTS/stubs/HeapBlockDevice_stub.cpp b/UNITTESTS/stubs/storage/HeapBlockDevice_stub.cpp similarity index 100% rename from UNITTESTS/stubs/HeapBlockDevice_stub.cpp rename to UNITTESTS/stubs/storage/HeapBlockDevice_stub.cpp diff --git a/UNITTESTS/stubs/MBRBlockDevice_stub.cpp b/UNITTESTS/stubs/storage/MBRBlockDevice_stub.cpp similarity index 99% rename from UNITTESTS/stubs/MBRBlockDevice_stub.cpp rename to UNITTESTS/stubs/storage/MBRBlockDevice_stub.cpp index 449236be6e..64fe7d181b 100644 --- a/UNITTESTS/stubs/MBRBlockDevice_stub.cpp +++ b/UNITTESTS/stubs/storage/MBRBlockDevice_stub.cpp @@ -18,6 +18,7 @@ #include "MBRBlockDevice.h" #include "mbed_critical.h" #include +#include "mbed_toolchain.h" // On disk structures, all entries are little endian diff --git a/UNITTESTS/stubs/ObservingBlockDevice_stub.cpp b/UNITTESTS/stubs/storage/ObservingBlockDevice_stub.cpp similarity index 100% rename from UNITTESTS/stubs/ObservingBlockDevice_stub.cpp rename to UNITTESTS/stubs/storage/ObservingBlockDevice_stub.cpp diff --git a/UNITTESTS/stubs/ProfilingBlockDevice_stub.cpp b/UNITTESTS/stubs/storage/ProfilingBlockDevice_stub.cpp similarity index 100% rename from UNITTESTS/stubs/ProfilingBlockDevice_stub.cpp rename to UNITTESTS/stubs/storage/ProfilingBlockDevice_stub.cpp diff --git a/UNITTESTS/stubs/ReadOnlyBlockDevice_stub.cpp b/UNITTESTS/stubs/storage/ReadOnlyBlockDevice_stub.cpp similarity index 100% rename from UNITTESTS/stubs/ReadOnlyBlockDevice_stub.cpp rename to UNITTESTS/stubs/storage/ReadOnlyBlockDevice_stub.cpp diff --git a/UNITTESTS/stubs/SlicingBlockDevice_stub.cpp b/UNITTESTS/stubs/storage/SlicingBlockDevice_stub.cpp similarity index 100% rename from UNITTESTS/stubs/SlicingBlockDevice_stub.cpp rename to UNITTESTS/stubs/storage/SlicingBlockDevice_stub.cpp diff --git a/UNITTESTS/stubs/kv_config_stub.cpp b/UNITTESTS/stubs/storage/kv_config_stub.cpp similarity index 100% rename from UNITTESTS/stubs/kv_config_stub.cpp rename to UNITTESTS/stubs/storage/kv_config_stub.cpp diff --git a/UNITTESTS/target_h/cmsis_os.h b/UNITTESTS/target_h/cmsis_os.h index a40ab9e73b..4e8b5570aa 100644 --- a/UNITTESTS/target_h/cmsis_os.h +++ b/UNITTESTS/target_h/cmsis_os.h @@ -18,7 +18,7 @@ #ifndef CMSIS_OS_H_ #define CMSIS_OS_H_ -#include "cmsis_os2.h" +#include "mbed_rtos_types.h" #define osPriority osPriority_t @@ -27,4 +27,5 @@ typedef struct { } osEvent; +typedef int32_t osStatus; #endif diff --git a/UNITTESTS/target_h/platform/cxxsupport/mstd_tuple b/UNITTESTS/target_h/platform/cxxsupport/mstd_tuple new file mode 100644 index 0000000000..d9e926aa57 --- /dev/null +++ b/UNITTESTS/target_h/platform/cxxsupport/mstd_tuple @@ -0,0 +1,93 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES LEOR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MSTD_TUPLE_ +#define MSTD_TUPLE_ + +/* + * + * - includes toolchain's + * - For all toolchains, C++17 backports: + * - mstd::apply + * - mstd::make_from_tuple + */ + +#include + +#if __cpp_lib_apply < 201603 || __cpp_lib_make_from_tuple < 201606 +#include // integer_sequence +#endif +#if __cpp_lib_apply < 201603 +#include // invoke +#endif + +namespace mstd { +using std::tuple; +using std::ignore; +using std::make_tuple; +using std::forward_as_tuple; +using std::tie; +using std::tuple_cat; +using std::tuple_size; +using std::tuple_element; +using std::tuple_element_t; +using std::get; + +// [tuple.apply] +#if __cpp_lib_apply >= 201603 +using std::apply; +#else +namespace impl { +template +invoke_result_t...> apply(F&& f, Tuple&& t, std::index_sequence) +{ + return mstd::invoke(std::forward(f), std::get(std::forward(t))...); +} +} + +// apply - works also for tuple-like objects such as array or pair +// user-defined types can specialize std::get and std::tuple_size to make this work +template +auto apply(F&& f, Tuple&& t) -> +decltype(impl::apply(std::forward(f), std::forward(t), std::make_index_sequence>::value>{})) +{ + return impl::apply(std::forward(f), std::forward(t), + std::make_index_sequence>::value>{}); +} +#endif + +#if __cpp_lib_make_from_tuple >= 201606 +using std::make_from_tuple; +#else +namespace impl { +template +T make_from_tuple(Tuple&& t, std::index_sequence) +{ + return T(std::get(std::forward(t))...); +} +} + +template +T make_from_tuple(Tuple&& t) +{ + return impl::make_from_tuple(std::forward(t), + std::make_index_sequence>::value>{}); +} +#endif + +} // namespace mstd + +#endif // MSTD_TUPLE_ diff --git a/UNITTESTS/target_h/rtos/Semaphore.h b/UNITTESTS/target_h/rtos/Semaphore.h index ecbdee511d..aecea8f6a3 100644 --- a/UNITTESTS/target_h/rtos/Semaphore.h +++ b/UNITTESTS/target_h/rtos/Semaphore.h @@ -18,7 +18,7 @@ #define SEMAPHORE_H #include -#include "cmsis_os2.h" +#include "internal/mbed_rtos1_types.h" #include "rtos/Kernel.h" namespace rtos { diff --git a/UNITTESTS/target_h/rtos/include/rtos/internal/mbed_rtos_storage.h b/UNITTESTS/target_h/rtos/include/rtos/internal/mbed_rtos_storage.h index e1b1276138..c160374e65 100644 --- a/UNITTESTS/target_h/rtos/include/rtos/internal/mbed_rtos_storage.h +++ b/UNITTESTS/target_h/rtos/include/rtos/internal/mbed_rtos_storage.h @@ -22,7 +22,7 @@ extern "C" { #endif -#include "cmsis_os2.h" +#include "mbed_rtos_types.h" #include "rtx_os.h" #include "rtx_lib.h" #include "mbed_rtx_conf.h" diff --git a/UNITTESTS/unit_test/test.py b/UNITTESTS/unit_test/test.py index a2f8b89480..dd0a71642e 100644 --- a/UNITTESTS/unit_test/test.py +++ b/UNITTESTS/unit_test/test.py @@ -86,6 +86,7 @@ class UnitTestTool(object): args = [cmake, "-G", generator, + "-DBUILD_TESTING=ON" "-DCMAKE_MAKE_PROGRAM=%s" % self.make_program, "-DCMAKE_CXX_COMPILER=%s" % get_cxx_tool(), "-DCMAKE_C_COMPILER=%s" % get_c_tool()] diff --git a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/CMakeLists.txt b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/CMakeLists.txt index e742f1483d..e25cbf8067 100644 --- a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/CMakeLists.txt +++ b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/CMakeLists.txt @@ -1,47 +1,45 @@ # Copyright (c) 2020-2021 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 -function(_mbed_get_cortex_m_exception_handlers toolchain_dir) - foreach(key ${MBED_TARGET_LABELS}) - if(${key} STREQUAL CORTEX_A) - set(STARTUP_RTX_FILE TARGET_CORTEX_A/irq_ca.S) - elseif(${key} STREQUAL M0) - set(STARTUP_RTX_FILE TARGET_M0/irq_cm0.S) - elseif(${key} STREQUAL M0P) - set(STARTUP_RTX_FILE TARGET_M0P/irq_cm0.S) - elseif(${key} STREQUAL M23) - set(STARTUP_RTX_FILE TARGET_M23/irq_armv8mbl.S) - elseif(${key} STREQUAL M3) - set(STARTUP_RTX_FILE TARGET_M3/irq_cm3.S) - elseif(${key} STREQUAL M33) - set(STARTUP_RTX_FILE TARGET_M33/irq_armv8mml.S) - elseif(${key} STREQUAL M55) - set(STARTUP_RTX_FILE TARGET_M33/irq_armv8mml.S) - elseif(${key} STREQUAL RTOS_M4_M7) - set(STARTUP_RTX_FILE TARGET_RTOS_M4_M7/irq_cm4f.S) - endif() +if(${CMAKE_CROSSCOMPILING}) + function(_mbed_get_cortex_m_exception_handlers toolchain_dir) + foreach(key ${MBED_TARGET_LABELS}) + if(${key} STREQUAL CORTEX_A) + set(STARTUP_RTX_FILE TARGET_CORTEX_A/irq_ca.S) + elseif(${key} STREQUAL M0) + set(STARTUP_RTX_FILE TARGET_M0/irq_cm0.S) + elseif(${key} STREQUAL M0P) + set(STARTUP_RTX_FILE TARGET_M0P/irq_cm0.S) + elseif(${key} STREQUAL M23) + set(STARTUP_RTX_FILE TARGET_M23/irq_armv8mbl.S) + elseif(${key} STREQUAL M3) + set(STARTUP_RTX_FILE TARGET_M3/irq_cm3.S) + elseif(${key} STREQUAL M33) + set(STARTUP_RTX_FILE TARGET_M33/irq_armv8mml.S) + elseif(${key} STREQUAL M55) + set(STARTUP_RTX_FILE TARGET_M33/irq_armv8mml.S) + elseif(${key} STREQUAL RTOS_M4_M7) + set(STARTUP_RTX_FILE TARGET_RTOS_M4_M7/irq_cm4f.S) + endif() - target_sources(mbed-rtos - INTERFACE - Source/${toolchain_dir}/${STARTUP_RTX_FILE} - ) - endforeach() -endfunction() - -function(_mbed_get_cortex_a_exception_handlers) - foreach(key ${MBED_TARGET_LABELS}) - if(${key} STREQUAL CORTEX_A) - target_sources(mbed-rtos INTERFACE Config/TARGET_CORTEX_A/handlers.c) - endif() - endforeach() -endfunction() - -_mbed_get_cortex_a_exception_handlers() - -if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + target_sources(mbed-rtos + INTERFACE + Source/${toolchain_dir}/${STARTUP_RTX_FILE} + ) + endforeach() + endfunction() + + function(_mbed_get_cortex_a_exception_handlers) + foreach(key ${MBED_TARGET_LABELS}) + if(${key} STREQUAL CORTEX_A) + target_sources(mbed-rtos INTERFACE Config/TARGET_CORTEX_A/handlers.c) + endif() + endforeach() + endfunction() + + _mbed_get_cortex_a_exception_handlers() + _mbed_get_cortex_m_exception_handlers(TOOLCHAIN_GCC) -elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") - _mbed_get_cortex_m_exception_handlers(TOOLCHAIN_ARM) endif() target_include_directories(mbed-rtos diff --git a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_GCC/TARGET_M0/irq_cm0.S b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_GCC/TARGET_M0/irq_cm0.S index e261cd066f..4d1359116e 100644 --- a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_GCC/TARGET_M0/irq_cm0.S +++ b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_GCC/TARGET_M0/irq_cm0.S @@ -102,7 +102,7 @@ SVC_ContextRestore: SUBS R0,R0,#32 // Adjust address LDMIA R0!,{R4-R7} // Restore R4..R7 - MOVS R0,#~0xFFFFFFFD + MOVS R0,#2 // Binary complement of 0xFFFFFFFD MVNS R0,R0 // Set EXC_RETURN value BX R0 // Exit from handler diff --git a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_GCC/TARGET_M0P/irq_cm0.S b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_GCC/TARGET_M0P/irq_cm0.S index e261cd066f..4d1359116e 100644 --- a/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_GCC/TARGET_M0P/irq_cm0.S +++ b/cmsis/CMSIS_5/CMSIS/RTOS2/RTX/Source/TOOLCHAIN_GCC/TARGET_M0P/irq_cm0.S @@ -102,7 +102,7 @@ SVC_ContextRestore: SUBS R0,R0,#32 // Adjust address LDMIA R0!,{R4-R7} // Restore R4..R7 - MOVS R0,#~0xFFFFFFFD + MOVS R0,#2 // Binary complement of 0xFFFFFFFD MVNS R0,R0 // Set EXC_RETURN value BX R0 // Exit from handler diff --git a/cmsis/device/rtos/CMakeLists.txt b/cmsis/device/rtos/CMakeLists.txt index 024cf56218..34cd1623e4 100644 --- a/cmsis/device/rtos/CMakeLists.txt +++ b/cmsis/device/rtos/CMakeLists.txt @@ -1,16 +1,18 @@ # Copyright (c) 2020-2021 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 -if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") - target_sources(mbed-rtos - INTERFACE - TOOLCHAIN_GCC_ARM/mbed_boot_gcc_arm.c - ) -elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") - target_sources(mbed-rtos - INTERFACE - TOOLCHAIN_ARM_STD/mbed_boot_arm_std.c - ) +if(${CMAKE_CROSSCOMPILING}) + if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + target_sources(mbed-rtos + INTERFACE + TOOLCHAIN_GCC_ARM/mbed_boot_gcc_arm.c + ) + elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + target_sources(mbed-rtos + INTERFACE + TOOLCHAIN_ARM_STD/mbed_boot_arm_std.c + ) + endif() endif() target_include_directories(mbed-rtos diff --git a/connectivity/CMakeLists.txt b/connectivity/CMakeLists.txt index 985cdb8c40..e011ad27dd 100644 --- a/connectivity/CMakeLists.txt +++ b/connectivity/CMakeLists.txt @@ -24,14 +24,21 @@ add_library(mbed-nfc INTERFACE) add_library(mbed-ppp INTERFACE) add_library(mbed-wifi INTERFACE) - -add_subdirectory(FEATURE_BLE) -add_subdirectory(cellular) -add_subdirectory(drivers) -add_subdirectory(libraries) -add_subdirectory(lorawan) -add_subdirectory(lwipstack) -add_subdirectory(mbedtls) -add_subdirectory(nanostack) -add_subdirectory(netsocket) -add_subdirectory(nfc) +if(${CMAKE_CROSSCOMPILING}) + # The directories below contain optional target libraries + add_subdirectory(FEATURE_BLE EXCLUDE_FROM_ALL) + add_subdirectory(cellular EXCLUDE_FROM_ALL) + add_subdirectory(drivers EXCLUDE_FROM_ALL) + add_subdirectory(libraries EXCLUDE_FROM_ALL) + add_subdirectory(lorawan EXCLUDE_FROM_ALL) + add_subdirectory(lwipstack EXCLUDE_FROM_ALL) + add_subdirectory(mbedtls EXCLUDE_FROM_ALL) + add_subdirectory(nanostack EXCLUDE_FROM_ALL) + add_subdirectory(netsocket EXCLUDE_FROM_ALL) + add_subdirectory(nfc EXCLUDE_FROM_ALL) +else() + # Add these subdirectories for the Unit test + add_subdirectory(cellular) + add_subdirectory(lorawan) + add_subdirectory(netsocket) +endif() diff --git a/connectivity/FEATURE_BLE/include/ble/Gap.h b/connectivity/FEATURE_BLE/include/ble/Gap.h index 067895d628..a5477aa5a6 100644 --- a/connectivity/FEATURE_BLE/include/ble/Gap.h +++ b/connectivity/FEATURE_BLE/include/ble/Gap.h @@ -747,7 +747,9 @@ public: * @param handle Advertising set handle. * @param maxDuration Max duration for advertising (in units of 10ms) - 0 means no limit. * @param maxEvents Max number of events produced during advertising - 0 means no limit. - * @return BLE_ERROR_NONE on success. + * @return BLE_ERROR_NONE on success. This does not guarantee the set has started if + * extended advertising is enabled. Register an event handler and wait for onAdvertisingStart + * event. An (unlikely) failed start the status of the event will contain an error. * * @see EventHandler::onAdvertisingStart when the advertising starts. * @see EventHandler::onScanRequestReceived when a scan request is received. @@ -765,7 +767,9 @@ public: * which will not be affected. * * @param handle Advertising set handle. - * @return BLE_ERROR_NONE on success. + * @return BLE_ERROR_NONE on success. For extented advertising this does not guarantee + * the set is stopped if. Register an event handler and wait for onAdvertisingEnd event. + * An (unlikely) failed stop the event status will contain the error code. */ ble_error_t stopAdvertising(advertising_handle_t handle); diff --git a/connectivity/FEATURE_BLE/include/ble/common/BLERoles.h b/connectivity/FEATURE_BLE/include/ble/common/BLERoles.h index 2c28eadbd5..7ef8d63b82 100644 --- a/connectivity/FEATURE_BLE/include/ble/common/BLERoles.h +++ b/connectivity/FEATURE_BLE/include/ble/common/BLERoles.h @@ -19,6 +19,50 @@ #ifndef MBED_BLE_ROLES_H__ #define MBED_BLE_ROLES_H__ +/* we provide default values if no configuration is present (e.g. in unittests) */ +#if !defined(BLE_ROLE_OBSERVER) +#define BLE_ROLE_OBSERVER 1 +#endif +#if !defined(BLE_ROLE_BROADCASTER) +#define BLE_ROLE_BROADCASTER 1 +#endif +#if !defined(BLE_ROLE_CENTRAL) +#define BLE_ROLE_CENTRAL 1 +#endif +#if !defined(BLE_ROLE_PERIPHERAL) +#define BLE_ROLE_PERIPHERAL 1 +#endif +#if !defined(BLE_FEATURE_GATT_CLIENT) +#define BLE_FEATURE_GATT_CLIENT 1 +#endif +#if !defined(BLE_FEATURE_GATT_SERVER) +#define BLE_FEATURE_GATT_SERVER 1 +#endif +#if !defined(BLE_FEATURE_SECURITY) +#define BLE_FEATURE_SECURITY 1 +#endif +#if !defined(BLE_FEATURE_SECURE_CONNECTIONS) +#define BLE_FEATURE_SECURE_CONNECTIONS 1 +#endif +#if !defined(BLE_FEATURE_SIGNING) +#define BLE_FEATURE_SIGNING 1 +#endif +#if !defined(BLE_FEATURE_WHITELIST) +#define BLE_FEATURE_WHITELIST 1 +#endif +#if !defined(BLE_FEATURE_PRIVACY) +#define BLE_FEATURE_PRIVACY 1 +#endif +#if !defined(BLE_FEATURE_PHY_MANAGEMENT) +#define BLE_FEATURE_PHY_MANAGEMENT 1 +#endif +#if !defined(BLE_FEATURE_EXTENDED_ADVERTISING) +#define BLE_FEATURE_EXTENDED_ADVERTISING 1 +#endif +#if !defined(BLE_FEATURE_PERIODIC_ADVERTISING) +#define BLE_FEATURE_PERIODIC_ADVERTISING 1 +#endif + #if !(BLE_ROLE_OBSERVER) && !(BLE_ROLE_BROADCASTER) #error "BLE requires at least one role 'BROADCASTER' or 'OBSERVER' to be enabled" #endif diff --git a/connectivity/FEATURE_BLE/include/ble/common/blecommon.h b/connectivity/FEATURE_BLE/include/ble/common/blecommon.h index ee74592205..fcd99fd734 100644 --- a/connectivity/FEATURE_BLE/include/ble/common/blecommon.h +++ b/connectivity/FEATURE_BLE/include/ble/common/blecommon.h @@ -216,7 +216,17 @@ enum ble_error_t { /** * Data not found or there is nothing to return. */ - BLE_ERROR_NOT_FOUND = 13 + BLE_ERROR_NOT_FOUND = 13, + + /** + * Specified timeout expired. + */ + BLE_ERROR_TIMEOUT = 14, + + /** + * Specified limit expired. + */ + BLE_ERROR_LIMIT_REACHED = 15 }; /** diff --git a/connectivity/FEATURE_BLE/include/ble/gap/Events.h b/connectivity/FEATURE_BLE/include/ble/gap/Events.h index a181f7b762..7d269af836 100644 --- a/connectivity/FEATURE_BLE/include/ble/gap/Events.h +++ b/connectivity/FEATURE_BLE/include/ble/gap/Events.h @@ -586,9 +586,10 @@ struct AdvertisingStartEvent { /** Create an advertising start event. * * @param advHandle Advertising set handle. + * @param status Advertising set start command status. */ - AdvertisingStartEvent(advertising_handle_t advHandle) : - advHandle(advHandle) + AdvertisingStartEvent(advertising_handle_t advHandle, ble_error_t status = BLE_ERROR_NONE) : + advHandle(advHandle), status(status) { } @@ -600,8 +601,15 @@ struct AdvertisingStartEvent { return advHandle; } + /** Get status of operation. */ + ble_error_t getStatus() const + { + return status; + } + private: advertising_handle_t advHandle; + ble_error_t status; }; /** @@ -610,7 +618,8 @@ private: * @see ble::Gap::EventHandler::onAdvertisingEnd(). * * @note The connection handle, connected flag and completed_event fields are - * valid if the flag legacy is not set to true. + * valid if the flag legacy is not set to true. If status is different from BLE_ERROR_NONE + * the completed_events field is not valid and the set may still be active. */ struct AdvertisingEndEvent { #if !defined(DOXYGEN_ONLY) @@ -618,21 +627,29 @@ struct AdvertisingEndEvent { /** Create an extended advertising end event. * * @param advHandle Advertising set handle. - * @param connection Connection handle. - * @param completed_events Number of events created during before advertising end. + * @param connection Connection handle - only valid if connected is True. + * @param completed_events Number of events created during before advertising end - only valid + * if advertising end has been caused by BLE_ERROR_LIMIT_REACHED, not the local user. + * Check getStatus(). * @param connected True if connection has been established. + * @param status Error code showing the reason for event. BLE_ERROR_LIMIT_REACHED if set number + * of events have been reached. BLE_ERROR_TIMEOUT if set time has elapsed. + * BLE_ERROR_SUCCESS if connection occurred or user ended the set. Check isConnected() + * to determine which. */ AdvertisingEndEvent( advertising_handle_t advHandle, connection_handle_t connection, uint8_t completed_events, - bool connected + bool connected, + ble_error_t status = BLE_ERROR_NONE ) : advHandle(advHandle), connection(connection), completed_events(completed_events), connected(connected), - legacy(false) + legacy(false), + status(status) { } @@ -643,7 +660,8 @@ struct AdvertisingEndEvent { connection(), completed_events(0), connected(false), - legacy(true) + legacy(true), + status(BLE_ERROR_NONE) { } @@ -683,12 +701,20 @@ struct AdvertisingEndEvent { return legacy; } + /** Get the result of the stop advertising event. If the status is not BLE_ERROR_NONE the set + * may still be active. */ + ble_error_t getStatus() const + { + return status; + } + private: advertising_handle_t advHandle; connection_handle_t connection; uint8_t completed_events; bool connected; bool legacy; + ble_error_t status; }; /** diff --git a/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/dm/dm_adv_ae.c b/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/dm/dm_adv_ae.c index 9f7c956740..ea32b7118d 100644 --- a/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/dm/dm_adv_ae.c +++ b/connectivity/FEATURE_BLE/libraries/cordio_stack/ble-host/sources/stack/dm/dm_adv_ae.c @@ -31,6 +31,7 @@ #include "dm_adv.h" #include "dm_dev.h" #include "dm_main.h" +#include "dm_conn.h" /************************************************************************************************** Macros @@ -1215,7 +1216,8 @@ void dmExtAdvActHciEnableCmpl(hciEvt_t *pEvent) dmEvt_t dmMsg; memcpy(&dmMsg, &pEvent->hdr, sizeof(wsfMsgHdr_t)); - dmMsg.advSetStart.numSets = 0; + + /* we have to handle stopping and starting separately as it uses the same message memory */ for ( i= 0; i < DM_NUM_ADV_SETS; i++) { @@ -1223,7 +1225,11 @@ void dmExtAdvActHciEnableCmpl(hciEvt_t *pEvent) { case DM_ADV_STATE_STOPPING: case DM_ADV_STATE_STOPPING_DIRECTED: + /* prepare the message for callback */ + dmMsg.advSetStop.handle = DM_ADV_HCI_HANDLE_NONE; + dmMsg.advSetStop.status = dmMsg.hdr.status; dmMsg.advSetStop.advHandle = i; + advType = dmAdvCb.advType[i]; if (dmMsg.hdr.status == HCI_SUCCESS) @@ -1243,10 +1249,24 @@ void dmExtAdvActHciEnableCmpl(hciEvt_t *pEvent) /* if not connectable directed advertising */ if ((advType != DM_ADV_NONE) && !DM_ADV_CONN_DIRECTED(advType)) { - cbackEvent = DM_ADV_SET_STOP_IND; + /* we have to dispatch callbacks one by one as msg only has space for one set of parameters */ + dmMsg.hdr.event = DM_ADV_SET_STOP_IND; + (*dmCb.cback)((dmEvt_t *) &dmMsg); } break; + default: + break; + } + } + + /* safe to write as message is only used by starting, removing and clearing does not send a message */ + dmMsg.advSetStart.numSets = 0; + + for ( i= 0; i < DM_NUM_ADV_SETS; i++) + { + switch(dmAdvCb.advState[i]) + { case DM_ADV_STATE_STARTING: case DM_ADV_STATE_STARTING_DIRECTED: dmMsg.advSetStart.advHandle[dmMsg.advSetStart.numSets++] = i; @@ -1355,6 +1375,13 @@ void dmExtAdvHciHandler(hciEvt_t *pEvent) if (!DM_ADV_CONN_DIRECTED(advType)) { pEvent->hdr.event = DM_ADV_SET_STOP_IND; + if (pEvent->leAdvSetTerm.status == HCI_SUCCESS) { + /* translate the handle to conn id */ + dmConnCcb_t* ccb = dmConnCcbByHandle(pEvent->leAdvSetTerm.handle); + if (ccb) { + pEvent->hdr.param = ccb->connId; + } + } (*dmCb.cback)((dmEvt_t *) pEvent); } /* else if low duty cycle directed advertising failed to create connection */ diff --git a/connectivity/FEATURE_BLE/mbed_lib.json b/connectivity/FEATURE_BLE/mbed_lib.json index 8cb752c076..2d1b11ef40 100644 --- a/connectivity/FEATURE_BLE/mbed_lib.json +++ b/connectivity/FEATURE_BLE/mbed_lib.json @@ -108,6 +108,11 @@ "value": 16, "macro_name": "BLE_GAP_HOST_PRIVACY_RESOLVED_CACHE_SIZE" }, + "ble-gap-host-max-advertising-start-commands": { + "help": "There can only be one outstanding advertising set command sent to the controller. This determines how many advertising set start commands can be queued on the host. Must be between 1 and BLE_GAP_MAX_ADVERTISING_SETS. If privacy is used, this must be at equal or higher than then number of simultaneously active sets with a private address.", + "value": 4, + "macro_name": "BLE_GAP_HOST_MAX_OUTSTANDING_ADVERTISING_START_COMMANDS" + }, "ble-passkey-display-reversed-digits-deprecation": { "help": "This option is part of the deprecation process. Set this to false to remove the deprecation notice. When set to true, the digits in the SecurityManager passkeyDiplay event are reversed. When set to false the digits are in the correct order.", diff --git a/connectivity/FEATURE_BLE/source/common/ble_trace_helpers.cpp b/connectivity/FEATURE_BLE/source/common/ble_trace_helpers.cpp index fcf11d3791..1864bbed32 100644 --- a/connectivity/FEATURE_BLE/source/common/ble_trace_helpers.cpp +++ b/connectivity/FEATURE_BLE/source/common/ble_trace_helpers.cpp @@ -522,7 +522,12 @@ const char *to_string(const UUID& uuid) static constexpr const char *HEX = "0123456789ABCDEF"; static constexpr const size_t HYPHENS_DELIMITER_COUNT = 4; - static char string_buffer[ROW_COUNT][UUID::LENGTH_OF_LONG_UUID + HYPHENS_DELIMITER_COUNT]; + /* + * For each hex digit, we require 2 bytes. So, we need at most 2 * 16 = 32 bytes for the hex digits. + * In the case of 128-bit UUIDs, we also need space for 4 hyphen delimiters. + * An additional byte is required at the end of each array to store the null terminator. + */ + static char string_buffer[ROW_COUNT][2 * UUID::LENGTH_OF_LONG_UUID + HYPHENS_DELIMITER_COUNT + 1]; static uint8_t idx = 0; ++idx; diff --git a/connectivity/FEATURE_BLE/source/cordio/source/BLEInstanceBaseImpl.cpp b/connectivity/FEATURE_BLE/source/cordio/source/BLEInstanceBaseImpl.cpp index 195ba9612f..4a93bc41ee 100644 --- a/connectivity/FEATURE_BLE/source/cordio/source/BLEInstanceBaseImpl.cpp +++ b/connectivity/FEATURE_BLE/source/cordio/source/BLEInstanceBaseImpl.cpp @@ -745,7 +745,7 @@ void BLEInstanceBase::callDispatcher() wsfOsDispatcher(); - static mbed::LowPowerTimeout nextTimeout; + static Timeout nextTimeout; mbed::CriticalSectionLock critical_section; if (wsfOsReadyToSleep()) { diff --git a/connectivity/FEATURE_BLE/source/cordio/source/BLEInstanceBaseImpl.h b/connectivity/FEATURE_BLE/source/cordio/source/BLEInstanceBaseImpl.h index ceb727a416..9d2289ae6d 100644 --- a/connectivity/FEATURE_BLE/source/cordio/source/BLEInstanceBaseImpl.h +++ b/connectivity/FEATURE_BLE/source/cordio/source/BLEInstanceBaseImpl.h @@ -45,7 +45,13 @@ #include "source/PalPrivateAddressControllerImpl.h" #include "source/generic/PrivateAddressController.h" +#include "drivers/Timeout.h" +#ifdef DEVICE_LPTICKER +#include "drivers/LowPowerTimeout.h" #include "drivers/LowPowerTimer.h" +#else +#include "drivers/Timer.h" +#endif namespace ble { @@ -57,6 +63,14 @@ namespace impl { * @see BLEInstanceBase */ class BLEInstanceBase final : public ble::BLEInstanceBase { +#ifdef DEVICE_LPTICKER + using Timeout = mbed::LowPowerTimeout; + using Timer = mbed::LowPowerTimer; +#else + using Timeout = mbed::Timeout; + using Timer = mbed::Timer; +#endif + friend PalSigningMonitor; /** @@ -200,7 +214,7 @@ private: } initialization_status; mutable ble::impl::PalEventQueue _event_queue; - mbed::LowPowerTimer _timer; + Timer _timer; uint64_t _last_update_us; }; diff --git a/connectivity/FEATURE_BLE/source/cordio/source/PalGapImpl.cpp b/connectivity/FEATURE_BLE/source/cordio/source/PalGapImpl.cpp index b7586bd52b..0ecee16e93 100644 --- a/connectivity/FEATURE_BLE/source/cordio/source/PalGapImpl.cpp +++ b/connectivity/FEATURE_BLE/source/cordio/source/PalGapImpl.cpp @@ -869,10 +869,17 @@ void PalGap::gap_handler(const wsfMsgHdr_t *msg) break; } + connection_handle_t connection_handle = DM_CONN_ID_NONE; + /* the way we distinguish between local close and connection is the invalid HCI conn handle */ + if (evt->status == HCI_SUCCESS && evt->handle != DM_CONN_HCI_HANDLE_NONE) { + /* use the translated conn handle */ + connection_handle = evt->hdr.param; + } + handler->on_advertising_set_terminated( hci_error_code_t(evt->status), evt->advHandle, - evt->handle, + connection_handle, evt->numComplEvts ); } break; diff --git a/connectivity/FEATURE_BLE/source/generic/CMakeLists.txt b/connectivity/FEATURE_BLE/source/generic/CMakeLists.txt index 30fecfba2a..085a834380 100644 --- a/connectivity/FEATURE_BLE/source/generic/CMakeLists.txt +++ b/connectivity/FEATURE_BLE/source/generic/CMakeLists.txt @@ -17,3 +17,10 @@ target_sources(mbed-ble SecurityDb.cpp SecurityManagerImpl.cpp ) + +target_link_libraries(mbed-ble + INTERFACE + mbed-storage-kvstore + mbed-storage-tdbstore + mbed-storage-kv-global-api +) diff --git a/connectivity/FEATURE_BLE/source/generic/GapImpl.cpp b/connectivity/FEATURE_BLE/source/generic/GapImpl.cpp index 5296ae690f..9eb8edccf2 100644 --- a/connectivity/FEATURE_BLE/source/generic/GapImpl.cpp +++ b/connectivity/FEATURE_BLE/source/generic/GapImpl.cpp @@ -373,6 +373,9 @@ Gap::Gap( , _scan_parameters_set(false) #endif // BLE_ROLE_OBSERVER { +#if BLE_FEATURE_EXTENDED_ADVERTISING + _advertising_enable_command_params.number_of_handles = 0; +#endif //BLE_FEATURE_EXTENDED_ADVERTISING _pal_gap.initialize(); _pal_gap.when_gap_event_received( @@ -1212,8 +1215,7 @@ ble_error_t Gap::reset() _event_handler = nullptr; _initiating = false; - set_scan_state(ScanState::idle); - _scan_requested = false; + #if BLE_FEATURE_PRIVACY _privacy_initialization_pending = false; #if BLE_GAP_HOST_BASED_PRIVATE_ADDRESS_RESOLUTION @@ -1224,49 +1226,26 @@ ble_error_t Gap::reset() #endif // BLE_FEATURE_PRIVACY #if BLE_ROLE_OBSERVER + set_scan_state(ScanState::idle); + _scan_requested = false; _scan_parameters_set = false; _scan_timeout.detach(); #endif #if BLE_ROLE_BROADCASTER #if BLE_FEATURE_EXTENDED_ADVERTISING - if (is_extended_advertising_available()) { - /* stop all advertising sets */ - for (size_t i = 0; i < BLE_GAP_MAX_ADVERTISING_SETS; ++i) { - if (_active_sets.get(i)) { - _pal_gap.extended_advertising_enable( - /* enable */ false, - /* number of advertising sets */ 1, - (advertising_handle_t *) &i, - nullptr, - nullptr - ); - } + /* clear advertising set data on the controller */ + _pal_gap.clear_advertising_sets(); + /* reset pending advertising sets */ + _advertising_enable_command_params.number_of_handles = 0; + _process_enable_queue_pending = false; + _process_disable_queue_pending = false; + _existing_sets.clear(); + _pending_stop_sets.clear(); #if BLE_FEATURE_PERIODIC_ADVERTISING - if (_active_periodic_sets.get(i)) { - _pal_gap.periodic_advertising_enable( - /* enable */ false, - (advertising_handle_t) i - ); - } - _active_periodic_sets.clear(); + _active_periodic_sets.clear(); #endif // BLE_FEATURE_PERIODIC_ADVERTISING - } - - /* clear state of all advertising sets */ - _existing_sets.clear(); - - /* clear advertising set data on the controller */ - _pal_gap.clear_advertising_sets(); - } else -#else // BLE_FEATURE_EXTENDED_ADVERTISING - { - if (_active_sets.get(LEGACY_ADVERTISING_HANDLE)) { - _pal_gap.advertising_enable(false); - } - } #endif // BLE_FEATURE_EXTENDED_ADVERTISING - _active_sets.clear(); _pending_sets.clear(); _address_refresh_sets.clear(); @@ -2413,22 +2392,30 @@ ble_error_t Gap::startAdvertising( _pal_gap.set_advertising_set_random_address(handle, *random_address); } - error = _pal_gap.extended_advertising_enable( - /* enable */ true, - /* number of advertising sets */ 1, - &handle, - maxDuration.storage(), - &maxEvents - ); - - if (error) { - return error; + /* check we haven't run out of space to remember parameters */ + if (_advertising_enable_command_params.number_of_handles == BLE_GAP_HOST_MAX_OUTSTANDING_ADVERTISING_START_COMMANDS) { + /* try to process early */ + tr_debug("Processing enable queue early as run out of queue space"); + process_enable_queue(); + /* if the processing didn't clear the handles we cannot continue */ + if (_advertising_enable_command_params.number_of_handles) { + tr_warn("Cannot enable set as no memory to record the parameters"); + return BLE_ERROR_NO_MEM; + } } - if (maxDuration.value() || maxEvents) { - _interruptible_sets.clear(handle); - } else { - _interruptible_sets.set(handle); + /* remember the parameters that will be enabled in the delayed processing */ + const uint8_t i = _advertising_enable_command_params.number_of_handles; + _advertising_enable_command_params.handles[i] = handle; + _advertising_enable_command_params.max_durations[i] = maxDuration; + _advertising_enable_command_params.max_events[i] = maxEvents; + _advertising_enable_command_params.number_of_handles++; + + /* we delay the processing to gather as many calls as we can in one go */ + if (!_process_enable_queue_pending) { + _process_enable_queue_pending = _event_queue.post([this] { + process_enable_queue(); + }); } } else @@ -2439,12 +2426,14 @@ ble_error_t Gap::startAdvertising( return BLE_ERROR_INVALID_PARAM; } +#if BLE_ROLE_OBSERVER // Address can be updated if the device is not scanning or advertising if ((_scan_state == ScanState::idle) && !_active_sets.get(LEGACY_ADVERTISING_HANDLE)) { _pal_gap.set_random_address(*random_address); } else { tr_error("could not update address, device scanning/advertising"); } +#endif // BLE_ROLE_OBSERVER error = _pal_gap.advertising_enable(true); if (error) { @@ -2461,14 +2450,66 @@ ble_error_t Gap::startAdvertising( } _interruptible_sets.set(LEGACY_ADVERTISING_HANDLE); - } - _pending_sets.set(handle); + _pending_sets.set(handle); + } return error; } #endif +#if BLE_FEATURE_EXTENDED_ADVERTISING +void Gap::process_enable_queue() +{ + _process_enable_queue_pending = false; + + tr_info("Evaluating pending advertising sets to be started"); + if (!_advertising_enable_command_params.number_of_handles) { + /* no set pending to be enabled */ + tr_debug("No sets to be enabled"); + return; + } + + for (size_t i = 0; i < BLE_GAP_MAX_ADVERTISING_SETS; ++i) { + if (_pending_sets.get(i)) { + /* we have to wait until nothing is pending */ + tr_info("Cannot enable sets as pending sets present, will retry later"); + return; + } + } + + ble_error_t error = _pal_gap.extended_advertising_enable( + /* enable */ true, + _advertising_enable_command_params.number_of_handles, + _advertising_enable_command_params.handles, + (uint16_t*)&_advertising_enable_command_params.max_durations, + _advertising_enable_command_params.max_events + ); + + if (error) { + tr_error("Failed to start advertising set with error: %s", to_string(error)); + if (_event_handler) { + for (size_t i = 0; i < _advertising_enable_command_params.number_of_handles; ++i) { + _pending_sets.clear(_advertising_enable_command_params.handles[i]); + _event_handler->onAdvertisingStart( + AdvertisingStartEvent(_advertising_enable_command_params.handles[i], error) + ); + } + } + } else { + for (size_t i = 0; i < _advertising_enable_command_params.number_of_handles; ++i) { + if (_advertising_enable_command_params.max_durations[i].value() || _advertising_enable_command_params.max_events[i]) { + _interruptible_sets.clear(_advertising_enable_command_params.handles[i]); + } else { + _interruptible_sets.set(_advertising_enable_command_params.handles[i]); + } + _pending_sets.set(_advertising_enable_command_params.handles[i]); + } + } + + _advertising_enable_command_params.number_of_handles = 0; +} +#endif //BLE_FEATURE_EXTENDED_ADVERTISING #if BLE_ROLE_BROADCASTER ble_error_t Gap::stopAdvertising(advertising_handle_t handle) @@ -2499,17 +2540,16 @@ ble_error_t Gap::stopAdvertising(advertising_handle_t handle) #if BLE_FEATURE_EXTENDED_ADVERTISING if (is_extended_advertising_available()) { - status = _pal_gap.extended_advertising_enable( - /*enable ? */ false, - /* number of advertising sets */ 1, - &handle, - nullptr, - nullptr - ); - - if (status) { - return status; + _pending_stop_sets.set(handle); + /* delay execution of command to accumulate multiple sets */ + if (!_process_disable_queue_pending) { + _process_disable_queue_pending = _event_queue.post([this] { + process_disable_queue(); + }); } + + status = BLE_ERROR_NONE; + } else #endif // BLE_FEATURE_EXTENDED_ADVERTISING { @@ -2525,12 +2565,60 @@ ble_error_t Gap::stopAdvertising(advertising_handle_t handle) } _advertising_timeout.detach(); - } - _pending_sets.set(handle); + _pending_sets.set(handle); + } return status; } + +#if BLE_FEATURE_EXTENDED_ADVERTISING +void Gap::process_disable_queue() +{ + advertising_handle_t sets[BLE_GAP_MAX_ADVERTISING_SETS]; + uint8_t number_of_handles = 0; + // refresh for address for all connectable advertising sets + for (size_t i = 0; i < BLE_GAP_MAX_ADVERTISING_SETS; ++i) { + if (_pending_stop_sets.get(i)) { + sets[number_of_handles] = i; + number_of_handles++; + _pending_stop_sets.clear(i); + } + } + + if (number_of_handles) { + ble_error_t error = _pal_gap.extended_advertising_enable( + /* enable */ false, + number_of_handles, + (advertising_handle_t*)&sets, + nullptr, + nullptr + ); + + if (error) { + for (size_t i = 0; i < number_of_handles; ++i) { + _event_handler->onAdvertisingEnd( + AdvertisingEndEvent( + (advertising_handle_t)sets[i], + 0/*connection*/, + 0/*completed_events*/, + false/*connected*/, + error + ) + ); + tr_error("Could not stop advertising set %u, error: %s", i, to_string(error)); + } + } else { + for (size_t i = 0; i < number_of_handles; ++i) { + _pending_sets.set(sets[i]); + } + } + } + + _process_disable_queue_pending = false; +} +#endif // BLE_FEATURE_EXTENDED_ADVERTISING + #endif @@ -3334,7 +3422,11 @@ void Gap::on_legacy_advertising_stopped() _pending_sets.clear(LEGACY_ADVERTISING_HANDLE); // restart advertising if it was stopped to refresh the address - if (_address_refresh_sets.get(LEGACY_ADVERTISING_HANDLE) && (_scan_state == ScanState::idle)) { + if (_address_refresh_sets.get(LEGACY_ADVERTISING_HANDLE) +#if BLE_ROLE_OBSERVER + && (_scan_state == ScanState::idle) +#endif //BLE_ROLE_OBSERVER + ) { _address_refresh_sets.clear(LEGACY_ADVERTISING_HANDLE); startAdvertising(LEGACY_ADVERTISING_HANDLE); _adv_started_from_refresh.set(LEGACY_ADVERTISING_HANDLE); @@ -3365,6 +3457,13 @@ void Gap::on_advertising_set_started(const mbed::Span& handles) ); } } + + /* delay processing to minimise churn (if multiple events are pending that would trigger it) */ + if (!_process_enable_queue_pending) { + _process_enable_queue_pending = _event_queue.post([this] { + process_enable_queue(); + }); + } } void Gap::on_advertising_set_terminated( @@ -3382,16 +3481,41 @@ void Gap::on_advertising_set_terminated( to_string(status), number_of_completed_extended_advertising_events); - _active_sets.clear(advertising_handle); - _pending_sets.clear(advertising_handle); + ble_error_t error_code = BLE_ERROR_UNSPECIFIED; + bool connected = false; - // If this is part of the address refresh start advertising again. - if (_address_refresh_sets.get(advertising_handle) && !connection_handle) { - _address_refresh_sets.clear(advertising_handle); - tr_info("Part of the address refresh, restarting advertising"); - startAdvertising(advertising_handle); - _adv_started_from_refresh.set(advertising_handle); - return; + /* translate HCI error into BLE API error code */ + if (status == hci_error_code_t::SUCCESS) { + error_code = BLE_ERROR_NONE; + /* self cancelled set will have the handle set to invalid value */ + if (connection_handle != DM_CONN_ID_NONE) { + connected = true; + } + } else if (status == hci_error_code_t::ADVERTISING_TIMEOUT) { + error_code = BLE_ERROR_TIMEOUT; + } else if (status == hci_error_code_t::LIMIT_REACHED) { + error_code = BLE_ERROR_LIMIT_REACHED; + } + + if (error_code != BLE_ERROR_UNSPECIFIED) { + _active_sets.clear(advertising_handle); + _pending_sets.clear(advertising_handle); + + // If this is part of the address refresh start advertising again. + if (_address_refresh_sets.get(advertising_handle) && !connection_handle) { + _address_refresh_sets.clear(advertising_handle); + tr_info("Part of the address refresh, restarting advertising"); + startAdvertising(advertising_handle); + _adv_started_from_refresh.set(advertising_handle); + return; + } + } + + /* postpone as other events may still be pending */ + if (!_process_disable_queue_pending) { + _process_disable_queue_pending = _event_queue.post([this] { + process_disable_queue(); + }); } if (!_event_handler) { @@ -3403,7 +3527,8 @@ void Gap::on_advertising_set_terminated( advertising_handle, connection_handle, number_of_completed_extended_advertising_events, - status == hci_error_code_t::SUCCESS + connected, + error_code ) ); } @@ -4129,7 +4254,11 @@ bool Gap::is_advertising() const } bool Gap::is_radio_active() const { - return _initiating || (_scan_state != ScanState::idle) || is_advertising(); + return _initiating || +#if BLE_ROLE_OBSERVER + (_scan_state != ScanState::idle) || +#endif // BLE_ROLE_OBSERVER + is_advertising(); } void Gap::update_advertising_set_connectable_attribute( @@ -4194,12 +4323,14 @@ const address_t *Gap::get_random_address(controller_operation_t operation, size_ // it to the address to use to determine if the address is correct or not. if (_initiating) { address_in_use = &resolvable_address; +#if BLE_ROLE_OBSERVER } else if (_scan_state != ScanState::idle) { if (central_non_resolvable) { address_in_use = &non_resolvable_address; } else { address_in_use = &resolvable_address; } +#endif //BLE_ROLE_OBSERVER } else if (advertising_use_main_address && (_active_sets.get(set_id) || _pending_sets.get(set_id))) { if (!_set_is_connectable.get(set_id) && peripheral_non_resolvable) { address_in_use = &non_resolvable_address; diff --git a/connectivity/FEATURE_BLE/source/generic/GapImpl.h b/connectivity/FEATURE_BLE/source/generic/GapImpl.h index d006738975..f85dfb9b56 100644 --- a/connectivity/FEATURE_BLE/source/generic/GapImpl.h +++ b/connectivity/FEATURE_BLE/source/generic/GapImpl.h @@ -23,8 +23,6 @@ #include -#include "drivers/LowPowerTimeout.h" -#include "drivers/LowPowerTicker.h" #include "platform/mbed_error.h" #include "ble/common/BLERoles.h" @@ -43,6 +41,14 @@ #include "ble/Gap.h" +#ifdef DEVICE_LPTICKER +#include "drivers/LowPowerTimeout.h" +#include "drivers/LowPowerTicker.h" +#else +#include "drivers/Timeout.h" +#include "drivers/Ticker.h" +#endif + namespace ble { class PalGenericAccessService; @@ -75,6 +81,14 @@ class Gap : public: using PreferredConnectionParams_t = ::ble::Gap::PreferredConnectionParams_t ; +#ifdef DEVICE_LPTICKER + using Timeout = mbed::LowPowerTimeout; + using Ticker = mbed::LowPowerTicker; +#else + using Timeout = mbed::Timeout; + using Ticker = mbed::Ticker; +#endif + #if BLE_FEATURE_PRIVACY #if BLE_ROLE_BROADCASTER /** @@ -562,6 +576,11 @@ private: ~Gap(); #if BLE_ROLE_BROADCASTER +#if BLE_FEATURE_EXTENDED_ADVERTISING + void process_enable_queue(); + void process_disable_queue(); +#endif // BLE_FEATURE_EXTENDED_ADVERTISING + ble_error_t setAdvertisingData( advertising_handle_t handle, Span payload, @@ -898,6 +917,7 @@ private: #endif // BLE_FEATURE_PRIVACY ble::address_t _random_static_identity_address; +#if BLE_ROLE_OBSERVER enum class ScanState : uint8_t { idle, scan, @@ -914,6 +934,7 @@ private: scan_period_t _scan_requested_period = scan_period_t(0); bool _scan_requested = false; +#endif // BLE_ROLE_OBSERVER #if BLE_GAP_HOST_BASED_PRIVATE_ADDRESS_RESOLUTION enum class ConnectionToHostResolvedAddressState : uint8_t { @@ -927,9 +948,9 @@ private: ConnectionParameters *_connect_to_host_resolved_address_parameters = nullptr; #endif // BLE_GAP_HOST_BASED_PRIVATE_ADDRESS_RESOLUTION - mbed::LowPowerTimeout _advertising_timeout; - mbed::LowPowerTimeout _scan_timeout; - mbed::LowPowerTicker _address_rotation_ticker; + Timeout _advertising_timeout; + Timeout _scan_timeout; + Ticker _address_rotation_ticker; bool _initiating = false; @@ -980,6 +1001,9 @@ private: }; BitArray _existing_sets; +#if BLE_FEATURE_EXTENDED_ADVERTISING + BitArray _pending_stop_sets; +#endif // BLE_FEATURE_EXTENDED_ADVERTISING BitArray _active_sets; BitArray _active_periodic_sets; BitArray _connectable_payload_size_exceeded; @@ -989,6 +1013,21 @@ private: BitArray _interruptible_sets; BitArray _adv_started_from_refresh; +#if BLE_FEATURE_EXTENDED_ADVERTISING +#if BLE_GAP_HOST_MAX_OUTSTANDING_ADVERTISING_START_COMMANDS < 1 || BLE_GAP_HOST_MAX_OUTSTANDING_ADVERTISING_START_COMMANDS > BLE_GAP_MAX_ADVERTISING_SETS +#error "BLE_GAP_HOST_MAX_OUTSTANDING_ADVERTISING_START_COMMANDS must be at least 1 and not bigger than BLE_GAP_MAX_ADVERTISING_SETS" +#endif + struct AdvertisingEnableCommandParams_t { + adv_duration_t max_durations[BLE_GAP_HOST_MAX_OUTSTANDING_ADVERTISING_START_COMMANDS]; + advertising_handle_t handles[BLE_GAP_HOST_MAX_OUTSTANDING_ADVERTISING_START_COMMANDS]; + uint8_t max_events[BLE_GAP_HOST_MAX_OUTSTANDING_ADVERTISING_START_COMMANDS]; + uint8_t number_of_handles; + }; + + AdvertisingEnableCommandParams_t _advertising_enable_command_params; + bool _process_enable_queue_pending = false; + bool _process_disable_queue_pending = false; +#endif // BLE_FEATURE_EXTENDED_ADVERTISING bool _user_manage_connection_parameter_requests; #if BLE_ROLE_OBSERVER diff --git a/connectivity/FEATURE_BLE/source/generic/KVStoreSecurityDb.cpp b/connectivity/FEATURE_BLE/source/generic/KVStoreSecurityDb.cpp index 68c5a16ff0..7a18620342 100644 --- a/connectivity/FEATURE_BLE/source/generic/KVStoreSecurityDb.cpp +++ b/connectivity/FEATURE_BLE/source/generic/KVStoreSecurityDb.cpp @@ -158,7 +158,7 @@ void KVStoreSecurityDb::set_entry_local_ltk( SecurityEntryKeys_t* current_entry = read_in_entry_local_keys(db_handle); current_entry->ltk = ltk; - tr_info("Write DB entry %d: local ltk %s", get_index(db_handle), to_string(ltk)); + tr_info("Write DB entry %d: local ltk %s", get_index(entry), to_string(ltk)); db_write_entry(current_entry, DB_ENTRY_LOCAL_KEYS, get_index(entry)); } @@ -177,7 +177,7 @@ void KVStoreSecurityDb::set_entry_local_ediv_rand( current_entry->ediv = ediv; current_entry->rand = rand; - tr_info("Write DB entry %d: local ediv %s rand %s", get_index(db_handle), to_string(ediv), to_string(rand)); + tr_info("Write DB entry %d: local ediv %s rand %s", get_index(entry), to_string(ediv), to_string(rand)); db_write_entry(current_entry, DB_ENTRY_LOCAL_KEYS, get_index(entry)); } @@ -200,7 +200,7 @@ void KVStoreSecurityDb::set_entry_peer_ltk( SecurityEntryKeys_t* current_entry = read_in_entry_peer_keys(db_handle); current_entry->ltk = ltk; - tr_info("Write DB entry %d: peer ltk %s", get_index(db_handle), to_string(ltk)); + tr_info("Write DB entry %d: peer ltk %s", get_index(entry), to_string(ltk)); db_write_entry(current_entry, DB_ENTRY_PEER_KEYS, get_index(entry)); } @@ -219,7 +219,7 @@ void KVStoreSecurityDb::set_entry_peer_ediv_rand( current_entry->ediv = ediv; current_entry->rand = rand; - tr_info("Write DB entry %d: peer ediv %s rand %s", get_index(db_handle), to_string(ediv), to_string(rand)); + tr_info("Write DB entry %d: peer ediv %s rand %s", get_index(entry), to_string(ediv), to_string(rand)); db_write_entry(current_entry, DB_ENTRY_PEER_KEYS, get_index(entry)); } @@ -238,7 +238,7 @@ void KVStoreSecurityDb::set_entry_peer_irk( SecurityEntryIdentity_t* current_entry = read_in_entry_peer_identity(db_handle); current_entry->irk = irk; - tr_info("Write DB entry %d: peer irk %s", get_index(db_handle), to_string(irk)); + tr_info("Write DB entry %d: peer irk %s", get_index(entry), to_string(irk)); db_write_entry(current_entry, DB_ENTRY_PEER_IDENTITY, get_index(entry)); } @@ -257,7 +257,7 @@ void KVStoreSecurityDb::set_entry_peer_bdaddr( current_entry->identity_address = peer_address; current_entry->identity_address_is_public = address_is_public; - tr_info("Write DB entry %d: %s peer address %s", get_index(db_handle), address_is_public? "public" : "private", to_string(peer_address)); + tr_info("Write DB entry %d: %s peer address %s", get_index(entry), address_is_public? "public" : "private", to_string(peer_address)); db_write_entry(current_entry, DB_ENTRY_PEER_IDENTITY, get_index(entry)); } @@ -276,7 +276,7 @@ void KVStoreSecurityDb::set_entry_peer_csrk( SecurityEntrySigning_t* current_entry = read_in_entry_peer_signing(db_handle); current_entry->csrk = csrk; - tr_info("Write DB entry %d: peer csrk %s", get_index(db_handle), to_string(csrk)); + tr_info("Write DB entry %d: peer csrk %s", get_index(entry), to_string(csrk)); db_write_entry(current_entry, DB_ENTRY_PEER_SIGNING, get_index(entry)); } diff --git a/connectivity/FEATURE_BLE/source/generic/KVStoreSecurityDb.h b/connectivity/FEATURE_BLE/source/generic/KVStoreSecurityDb.h index 49b6ed77cc..8ce9ac5788 100644 --- a/connectivity/FEATURE_BLE/source/generic/KVStoreSecurityDb.h +++ b/connectivity/FEATURE_BLE/source/generic/KVStoreSecurityDb.h @@ -40,6 +40,8 @@ private: sign_count_t peer_sign_counter; }; + static entry_t *as_entry(entry_handle_t db_handle); + static constexpr uint8_t KVSTORESECURITYDB_VERSION = 1; static constexpr size_t DB_PREFIX_SIZE = 7 + sizeof (STR(MBED_CONF_STORAGE_DEFAULT_KV)) - 1; diff --git a/connectivity/FEATURE_BLE/source/generic/PrivateAddressController.h b/connectivity/FEATURE_BLE/source/generic/PrivateAddressController.h index e24de9d6c4..decf6f4d74 100644 --- a/connectivity/FEATURE_BLE/source/generic/PrivateAddressController.h +++ b/connectivity/FEATURE_BLE/source/generic/PrivateAddressController.h @@ -22,12 +22,17 @@ #include -#include "drivers/LowPowerTicker.h" #include "ble/common/BLETypes.h" #include "ble/common/blecommon.h" #include "source/pal/PalEventQueue.h" #include "source/pal/PalPrivateAddressController.h" +#ifdef DEVICE_LPTICKER +#include "drivers/LowPowerTicker.h" +#else +#include "drivers/Ticker.h" +#endif + namespace ble { /** @@ -38,6 +43,12 @@ namespace ble { */ class PrivateAddressController : private PalPrivateAddressController::EventHandler { public: +#ifdef DEVICE_LPTICKER + using Ticker = mbed::LowPowerTicker; +#else + using Ticker = mbed::Ticker; +#endif + struct EventHandler { /** * Called when a new resolvable private address has been generated. @@ -313,7 +324,7 @@ private: bool _generation_started; irk_t _local_irk = {}; EventHandler *_event_handler = nullptr; - mbed::LowPowerTicker _address_rotation_ticker; + Ticker _address_rotation_ticker; address_t _resolvable_address = {}; address_t _non_resolvable_address = {}; diff --git a/connectivity/FEATURE_BLE/source/pal/PalEventQueue.h b/connectivity/FEATURE_BLE/source/pal/PalEventQueue.h index e5fbb4cd6d..727859c97e 100644 --- a/connectivity/FEATURE_BLE/source/pal/PalEventQueue.h +++ b/connectivity/FEATURE_BLE/source/pal/PalEventQueue.h @@ -52,6 +52,10 @@ public: * BLEInstanceBase::process */ virtual bool post(const mbed::Callback& event) = 0; + + /** Remove all pending events. + */ + virtual void clear() = 0; }; } // namespace ble diff --git a/connectivity/FEATURE_BLE/source/pal/PalGap.h b/connectivity/FEATURE_BLE/source/pal/PalGap.h index f3dacc496d..41f3da1fcb 100644 --- a/connectivity/FEATURE_BLE/source/pal/PalGap.h +++ b/connectivity/FEATURE_BLE/source/pal/PalGap.h @@ -193,9 +193,9 @@ public: /** Called when advertising set stops advertising. * - * @param status SUCCESS if connection has been established. + * @param status SUCCESS if connection has been established or if stopped by user. * @param advertising_handle Advertising set handle. - * @param advertising_handle Connection handle. + * @param advertising_handle Connection handle. Set to invalid handle if no connection made. * @param number_of_completed_extended_advertising_events Number of events created during before advertising end. */ virtual void on_advertising_set_terminated( diff --git a/connectivity/cellular/CMakeLists.txt b/connectivity/cellular/CMakeLists.txt index 00b5d7a84a..d7ce11f90d 100644 --- a/connectivity/cellular/CMakeLists.txt +++ b/connectivity/cellular/CMakeLists.txt @@ -1,6 +1,10 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) + add_subdirectory(tests/UNITTESTS) +endif() + add_subdirectory(source/framework) target_include_directories(mbed-cellular diff --git a/connectivity/cellular/include/cellular/framework/API/ATHandler.h b/connectivity/cellular/include/cellular/framework/API/ATHandler.h index 5010b9a0e1..6ba6562fbe 100644 --- a/connectivity/cellular/include/cellular/framework/API/ATHandler.h +++ b/connectivity/cellular/include/cellular/framework/API/ATHandler.h @@ -50,8 +50,6 @@ class FileHandle; extern const char *OK; extern const char *CRLF; -#define BUFF_SIZE 32 - /* AT Error types enumeration */ enum DeviceErrorType { DeviceErrorTypeNoError = 0, @@ -114,7 +112,7 @@ public: /** Set callback function for URC * - * @param prefix URC text to look for, e.g. "+CMTI:". Maximum length is BUFF_SIZE. + * @param prefix URC text to look for, e.g. "+CMTI:". Maximum length is MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE. * @param callback function to call on prefix, or 0 to remove callback */ void set_urc_handler(const char *prefix, Callback callback); @@ -601,7 +599,7 @@ private: //Member variables bool _is_fh_usable; // should fit any prefix and int - char _recv_buff[BUFF_SIZE]; + char _recv_buff[MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE]; // reading position size_t _recv_len; // reading length @@ -630,7 +628,7 @@ private: //Member variables size_t _max_resp_length; // prefix set during resp_start and used to try matching possible information responses - char _info_resp_prefix[BUFF_SIZE]; + char _info_resp_prefix[MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE]; bool _debug_on; bool _cmd_start; bool _use_delimiter; @@ -640,7 +638,7 @@ private: //Member variables // eventqueue event id int _event_id; - char _cmd_buffer[BUFF_SIZE]; + char _cmd_buffer[MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE]; }; } // namespace mbed diff --git a/connectivity/cellular/mbed_lib.json b/connectivity/cellular/mbed_lib.json index 616a052f20..c8a24fc2cd 100644 --- a/connectivity/cellular/mbed_lib.json +++ b/connectivity/cellular/mbed_lib.json @@ -44,6 +44,10 @@ "plmn-fallback-auto" : { "help": "If manual PLMN is selected, use mode 4 manual/automatic in AT+COPS to try automatic mode if manual selection fails. Set to null to disable", "value": null + }, + "at-handler-buffer-size" : { + "help": "Size of the AT handler buffer", + "value": 32 } } } diff --git a/connectivity/cellular/source/framework/device/ATHandler.cpp b/connectivity/cellular/source/framework/device/ATHandler.cpp index c504b1f038..a3009e70fc 100644 --- a/connectivity/cellular/source/framework/device/ATHandler.cpp +++ b/connectivity/cellular/source/framework/device/ATHandler.cpp @@ -683,7 +683,7 @@ int32_t ATHandler::read_int() return -1; } - char buff[BUFF_SIZE]; + char buff[MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE]; if (read_string(buff, sizeof(buff)) == 0) { return -1; } @@ -960,7 +960,7 @@ void ATHandler::resp_start(const char *prefix, bool stop) (void)fill_buffer(false); if (prefix) { - MBED_ASSERT(strlen(prefix) < BUFF_SIZE); + MBED_ASSERT(strlen(prefix) < MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE); strcpy(_info_resp_prefix, prefix); // copy prefix so we can later use it without having to provide again for info_resp } @@ -1225,7 +1225,7 @@ void ATHandler::handle_start(const char *cmd, const char *cmd_chr) if (cmd_chr) { cmd_char_len = strlen(cmd_chr); } - MBED_ASSERT((3 + strlen(cmd) + cmd_char_len) < BUFF_SIZE); + MBED_ASSERT((3 + strlen(cmd) + cmd_char_len) < MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE); memcpy(_cmd_buffer + len, cmd, strlen(cmd)); len += strlen(cmd); @@ -1258,7 +1258,7 @@ void ATHandler::cmd_start_stop(const char *cmd, const char *cmd_chr, const char nsapi_error_t ATHandler::at_cmd_str(const char *cmd, const char *cmd_chr, char *resp_buf, size_t buf_size, const char *format, ...) { - MBED_ASSERT(strlen(cmd) < BUFF_SIZE); + MBED_ASSERT(strlen(cmd) < MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE); lock(); handle_start(cmd, cmd_chr); diff --git a/connectivity/cellular/tests/UNITTESTS/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/CMakeLists.txt new file mode 100644 index 0000000000..7fa72fe29e --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(framework) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/AT/CMakeLists.txt new file mode 100644 index 0000000000..fcc649fa52 --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/AT/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(at_cellularcontext) +add_subdirectory(at_cellulardevice) +add_subdirectory(at_cellularinformation) +add_subdirectory(at_cellularnetwork) +add_subdirectory(at_cellularsms) +add_subdirectory(at_cellularstack) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularcontext/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularcontext/CMakeLists.txt new file mode 100644 index 0000000000..0daa233d6c --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularcontext/CMakeLists.txt @@ -0,0 +1,34 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME at_cellularcontext-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_SERIAL=1 + DEVICE_INTERRUPTIN=1 + MBED_CONF_CELLULAR_USE_SMS=1 + MBED_CONF_NSAPI_DEFAULT_CELLULAR_APN=NULL + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 + MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/cellular/source/framework/AT/AT_CellularContext.cpp + at_cellularcontexttest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "cellular") diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularcontext/at_cellularcontexttest.cpp b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularcontext/at_cellularcontexttest.cpp index 304e342d3f..eb0a2a0459 100644 --- a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularcontext/at_cellularcontexttest.cpp +++ b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularcontext/at_cellularcontexttest.cpp @@ -58,10 +58,8 @@ protected: ATHandler_stub::call_immediately = false; ATHandler_stub::resp_info_true_counter = false; ATHandler_stub::info_elem_true_counter = false; - ATHandler_stub::int_valid_count_table[kRead_int_table_size]; ATHandler_stub::int_count = kRead_int_table_size; ATHandler_stub::read_string_index = kRead_string_table_size; - ATHandler_stub::read_string_table[kRead_string_table_size]; ATHandler_stub::resp_stop_success_count = kResp_stop_count_default; CellularDevice_stub::connect_counter = 2; @@ -153,6 +151,8 @@ public: if (!_stack) { _stack = new my_stack(_at, *get_device()); } + + return _stack; } virtual uint32_t get_timeout_for_operation(ContextOperation op) const { diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularcontext/unittest.cmake b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularcontext/unittest.cmake deleted file mode 100644 index 4c90919afe..0000000000 --- a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularcontext/unittest.cmake +++ /dev/null @@ -1,54 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - ../connectivity/cellular/tests/UNITTESTS/framework/common/util - ../connectivity/cellular/include/cellular/framework/common - ../connectivity/cellular/include/cellular/framework/AT - ../connectivity/cellular/include/cellular/framework/device -) - -# Source files -set(unittest-sources - ../connectivity/cellular/source/framework/AT/AT_CellularContext.cpp -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/at_cellularcontexttest.cpp - stubs/ATHandler_stub.cpp - stubs/AT_CellularDevice_stub.cpp - stubs/AT_CellularStack_stub.cpp - stubs/AT_CellularNetwork_stub.cpp - stubs/AT_ControlPlane_netif_stub.cpp - stubs/CellularDevice_stub.cpp - stubs/CellularStateMachine_stub.cpp - stubs/equeue_stub.c - stubs/EventQueue_stub.cpp - stubs/FileHandle_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/NetworkInterface_stub.cpp - stubs/NetworkInterfaceDefaults_stub.cpp - stubs/NetworkStack_stub.cpp - stubs/randLIB_stub.cpp - stubs/Semaphore_stub.cpp - stubs/us_ticker_stub.cpp - stubs/BufferedSerial_stub.cpp - stubs/SerialBase_stub.cpp - stubs/CellularContext_stub.cpp - stubs/CellularUtil_stub.cpp - stubs/SocketAddress_stub.cpp - stubs/ConditionVariable_stub.cpp - stubs/Mutex_stub.cpp -) - -set(unittest-test-flags - -DDEVICE_SERIAL=1 - -DDEVICE_INTERRUPTIN=1 - -DMBED_CONF_CELLULAR_USE_SMS=1 - -DMBED_CONF_NSAPI_DEFAULT_CELLULAR_APN=NULL - -DMBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 -) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellulardevice/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellulardevice/CMakeLists.txt new file mode 100644 index 0000000000..e065e68a14 --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellulardevice/CMakeLists.txt @@ -0,0 +1,40 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME at_cellulardevice-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_SERIAL=1 + DEVICE_INTERRUPTIN=1 + MBED_CONF_NSAPI_DEFAULT_CELLULAR_APN=NULL + MBED_CONF_NSAPI_DEFAULT_CELLULAR_USERNAME=NULL + MBED_CONF_NSAPI_DEFAULT_CELLULAR_PASSWORD=NULL + MBED_CONF_NSAPI_DEFAULT_CELLULAR_PLMN=NULL + MBED_CONF_NSAPI_DEFAULT_CELLULAR_SIM_PIN=NULL + MDMTXD=NC + MDMRXD=NC + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 + MBED_CONF_CELLULAR_USE_SMS=1 + MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp + at_cellulardevicetest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "cellular") diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellulardevice/unittest.cmake b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellulardevice/unittest.cmake deleted file mode 100644 index 20bc316880..0000000000 --- a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellulardevice/unittest.cmake +++ /dev/null @@ -1,61 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - ../connectivity/cellular/tests/UNITTESTS/framework/common/util - ../connectivity/cellular/include/cellular/framework/common - ../connectivity/cellular/include/cellular/framework/AT - ../connectivity/cellular/include/cellular/framework/device - ../platform/randlib/include/mbed-client-randlib - ../drivers - ../hal -) - -# Source files -set(unittest-sources - stubs/randLIB_stub.c - ../connectivity/cellular/source/framework/AT/AT_CellularDevice.cpp -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/at_cellulardevicetest.cpp - stubs/AT_CellularNetwork_stub.cpp - stubs/ATHandler_stub.cpp - stubs/AT_CellularSMS_stub.cpp - stubs/AT_CellularInformation_stub.cpp - stubs/CellularUtil_stub.cpp - stubs/NetworkInterface_stub.cpp - stubs/NetworkInterfaceDefaults_stub.cpp - stubs/EventQueue_stub.cpp - stubs/FileHandle_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/CellularDevice_stub.cpp - stubs/NetworkStack_stub.cpp - stubs/AT_CellularContext_stub.cpp - stubs/Semaphore_stub.cpp - stubs/BufferedSerial_stub.cpp - stubs/SerialBase_stub.cpp - stubs/CellularStateMachine_stub.cpp - stubs/CellularContext_stub.cpp - stubs/ThisThread_stub.cpp - stubs/ConditionVariable_stub.cpp - stubs/Mutex_stub.cpp -) - -set(unittest-test-flags - -DDEVICE_SERIAL=1 - -DDEVICE_INTERRUPTIN=1 - -DMBED_CONF_NSAPI_DEFAULT_CELLULAR_APN=NULL - -DMBED_CONF_NSAPI_DEFAULT_CELLULAR_USERNAME=NULL - -DMBED_CONF_NSAPI_DEFAULT_CELLULAR_PASSWORD=NULL - -DMBED_CONF_NSAPI_DEFAULT_CELLULAR_PLMN=NULL - -DMBED_CONF_NSAPI_DEFAULT_CELLULAR_SIM_PIN=NULL - -DMDMTXD=NC - -DMDMRXD=NC - -DMBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 - -DMBED_CONF_CELLULAR_USE_SMS=1 -) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularinformation/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularinformation/CMakeLists.txt new file mode 100644 index 0000000000..b7a6ec83f7 --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularinformation/CMakeLists.txt @@ -0,0 +1,32 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME at_cellularinformation-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_SERIAL=1 + DEVICE_INTERRUPTIN=1 + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 + MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/cellular/source/framework/AT/AT_CellularInformation.cpp + at_cellularinformationtest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "cellular") diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularinformation/unittest.cmake b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularinformation/unittest.cmake deleted file mode 100644 index fad602356c..0000000000 --- a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularinformation/unittest.cmake +++ /dev/null @@ -1,43 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - ../connectivity/cellular/tests/UNITTESTS/framework/common/util - ../connectivity/cellular/include/cellular/framework/common - ../connectivity/cellular/include/cellular/framework/AT - ../platform/randlib/include/mbed-client-randlib -) - -# Source files -set(unittest-sources - stubs/randLIB_stub.c - ../connectivity/cellular/source/framework/AT/AT_CellularInformation.cpp -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/at_cellularinformationtest.cpp - stubs/ATHandler_stub.cpp - stubs/EventQueue_stub.cpp - stubs/FileHandle_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/ConditionVariable_stub.cpp - stubs/CellularDevice_stub.cpp - stubs/AT_CellularDevice_stub.cpp - stubs/CellularContext_stub.cpp - stubs/AT_CellularContext_stub.cpp - stubs/AT_CellularNetwork_stub.cpp - stubs/NetworkInterface_stub.cpp - stubs/NetworkInterfaceDefaults_stub.cpp - stubs/Mutex_stub.cpp - stubs/Semaphore_stub.cpp -) - -set(unittest-test-flags - -DDEVICE_SERIAL=1 - -DDEVICE_INTERRUPTIN=1 - -DMBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 -) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularnetwork/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularnetwork/CMakeLists.txt new file mode 100644 index 0000000000..70d33ecdc0 --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularnetwork/CMakeLists.txt @@ -0,0 +1,33 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME at_cellularnetwork-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_SERIAL=1 + DEVICE_INTERRUPTIN=1 + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 + MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/cellular/source/framework/AT/AT_CellularNetwork.cpp + ${mbed-os_SOURCE_DIR}/connectivity/cellular/source/framework/common/CellularUtil.cpp + at_cellularnetworktest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "cellular") diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularnetwork/unittest.cmake b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularnetwork/unittest.cmake deleted file mode 100644 index 07c7b9c438..0000000000 --- a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularnetwork/unittest.cmake +++ /dev/null @@ -1,45 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - ../connectivity/cellular/tests/UNITTESTS/framework/common/util - ../connectivity/cellular/include/cellular/framework/common - ../connectivity/cellular/include/cellular/framework/AT - ../platform/randlib/include/mbed-client-randlib -) - -# Source files -set(unittest-sources - ../connectivity/cellular/source/framework/AT/AT_CellularNetwork.cpp - ../connectivity/cellular/source/framework/common/CellularUtil.cpp -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/at_cellularnetworktest.cpp - stubs/ATHandler_stub.cpp - stubs/EventQueue_stub.cpp - stubs/FileHandle_stub.cpp - stubs/us_ticker_stub.cpp - stubs/CellularDevice_stub.cpp - stubs/AT_CellularDevice_stub.cpp - stubs/CellularContext_stub.cpp - stubs/AT_CellularContext_stub.cpp - stubs/NetworkInterface_stub.cpp - stubs/NetworkInterfaceDefaults_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/SocketAddress_stub.cpp - stubs/randLIB_stub.cpp - stubs/ConditionVariable_stub.cpp - stubs/Mutex_stub.cpp - stubs/Semaphore_stub.cpp -) - -set(unittest-test-flags - -DDEVICE_SERIAL=1 - -DDEVICE_INTERRUPTIN=1 - -DMBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 -) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularsms/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularsms/CMakeLists.txt new file mode 100644 index 0000000000..2f62b64f8d --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularsms/CMakeLists.txt @@ -0,0 +1,33 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME at_cellularsms-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_SERIAL=1 + DEVICE_INTERRUPTIN=1 + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 + MBED_CONF_CELLULAR_USE_SMS=1 + MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/cellular/source/framework/AT/AT_CellularSMS.cpp + at_cellularsmstest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "cellular") diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularsms/unittest.cmake b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularsms/unittest.cmake deleted file mode 100644 index dc344876f9..0000000000 --- a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularsms/unittest.cmake +++ /dev/null @@ -1,47 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - ../connectivity/cellular/tests/UNITTESTS/framework/common/util - ../connectivity/cellular/include/cellular/framework/common - ../connectivity/cellular/include/cellular/framework/AT - ../platform/randlib/include/mbed-client-randlib -) - -# Source files -set(unittest-sources - ../connectivity/cellular/source/framework/AT/AT_CellularSMS.cpp -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/at_cellularsmstest.cpp - stubs/ATHandler_stub.cpp - stubs/EventQueue_stub.cpp - stubs/FileHandle_stub.cpp - stubs/CellularUtil_stub.cpp - stubs/us_ticker_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/ThisThread_stub.cpp - stubs/mbed_wait_api_stub.cpp - stubs/ConditionVariable_stub.cpp - stubs/CellularDevice_stub.cpp - stubs/AT_CellularDevice_stub.cpp - stubs/CellularContext_stub.cpp - stubs/AT_CellularContext_stub.cpp - stubs/AT_CellularNetwork_stub.cpp - stubs/NetworkInterface_stub.cpp - stubs/NetworkInterfaceDefaults_stub.cpp - stubs/Mutex_stub.cpp - stubs/Semaphore_stub.cpp -) - -set(unittest-test-flags - -DMBED_CONF_CELLULAR_USE_SMS=1 - -DDEVICE_SERIAL=1 - -DDEVICE_INTERRUPTIN=1 - -DMBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 -) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularstack/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularstack/CMakeLists.txt new file mode 100644 index 0000000000..79c69ea85a --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularstack/CMakeLists.txt @@ -0,0 +1,38 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME at_cellularstack-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_SERIAL=1 + DEVICE_INTERRUPTIN=1 + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 + MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/cellular/source/framework/AT/AT_CellularStack.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + at_cellularstacktest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "cellular") diff --git a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularstack/unittest.cmake b/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularstack/unittest.cmake deleted file mode 100644 index 97fe9a230b..0000000000 --- a/connectivity/cellular/tests/UNITTESTS/framework/AT/at_cellularstack/unittest.cmake +++ /dev/null @@ -1,52 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - ../connectivity/cellular/tests/UNITTESTS/framework/common/util - ../connectivity/cellular/include/cellular/framework/common - ../connectivity/cellular/include/cellular/framework/AT - ../platform/randlib/include/mbed-client-randlib -) - -# Source files -set(unittest-sources - ../connectivity/cellular/source/framework/AT/AT_CellularStack.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c - ../connectivity/netsocket/source/SocketAddress.cpp -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/at_cellularstacktest.cpp - stubs/ATHandler_stub.cpp - stubs/EventQueue_stub.cpp - stubs/FileHandle_stub.cpp - stubs/CellularUtil_stub.cpp - stubs/CellularContext_stub.cpp - stubs/AT_CellularContext_stub.cpp - stubs/AT_CellularNetwork_stub.cpp - stubs/NetworkInterfaceDefaults_stub.cpp - stubs/NetworkInterface_stub.cpp - stubs/CellularDevice_stub.cpp - stubs/AT_CellularDevice_stub.cpp - stubs/us_ticker_stub.cpp - stubs/NetworkStack_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/ThisThread_stub.cpp - stubs/ConditionVariable_stub.cpp - stubs/Mutex_stub.cpp - stubs/Semaphore_stub.cpp -) - -set(unittest-test-flags - -DDEVICE_SERIAL=1 - -DDEVICE_INTERRUPTIN=1 - -DMBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 -) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/CMakeLists.txt new file mode 100644 index 0000000000..e9e308a23a --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(AT) +add_subdirectory(common) +add_subdirectory(device) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/common/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/common/CMakeLists.txt new file mode 100644 index 0000000000..f61ce37797 --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/common/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(list) +add_subdirectory(util) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/common/list/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/common/list/CMakeLists.txt new file mode 100644 index 0000000000..fea658b740 --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/common/list/CMakeLists.txt @@ -0,0 +1,21 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME cellular-framework-common-list-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + listtest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "cellular") diff --git a/connectivity/cellular/tests/UNITTESTS/framework/common/list/unittest.cmake b/connectivity/cellular/tests/UNITTESTS/framework/common/list/unittest.cmake deleted file mode 100644 index 2325fb0e89..0000000000 --- a/connectivity/cellular/tests/UNITTESTS/framework/common/list/unittest.cmake +++ /dev/null @@ -1,19 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - ../connectivity/cellular/tests/UNITTESTS/framework/common/util - ../connectivity/cellular/include/cellular/framework/common -) - -# Source files -set(unittest-sources -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/listtest.cpp -) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/common/util/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/common/util/CMakeLists.txt new file mode 100644 index 0000000000..5731fb5aff --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/common/util/CMakeLists.txt @@ -0,0 +1,23 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME cellular-framework-common-util-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/cellular/source/framework/common/CellularUtil.cpp + utiltest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "cellular") diff --git a/connectivity/cellular/tests/UNITTESTS/framework/common/util/unittest.cmake b/connectivity/cellular/tests/UNITTESTS/framework/common/util/unittest.cmake deleted file mode 100644 index 556c12a261..0000000000 --- a/connectivity/cellular/tests/UNITTESTS/framework/common/util/unittest.cmake +++ /dev/null @@ -1,22 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - ../connectivity/cellular/tests/UNITTESTS/framework/common/util - ../connectivity/cellular/include/cellular/framework/common - ../platform/randlib/include/mbed-client-randlib -) - -# Source files -set(unittest-sources - ../connectivity/cellular/source/framework/common/CellularUtil.cpp -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/utiltest.cpp - stubs/randLIB_stub.cpp -) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/device/CMakeLists.txt new file mode 100644 index 0000000000..50b30e3767 --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/device/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(athandler) +add_subdirectory(cellularcontext) +add_subdirectory(cellulardevice) +add_subdirectory(cellularstatemachine) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/athandler/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/device/athandler/CMakeLists.txt new file mode 100644 index 0000000000..9ea7f08523 --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/device/athandler/CMakeLists.txt @@ -0,0 +1,34 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME cellular-framework-device-athandler-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_CELLULAR_DEBUG_AT=true + OS_STACK_SIZE=2048 + DEVICE_SERIAL=1 + DEVICE_INTERRUPTIN=1 + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 + MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/cellular/source/framework/device/ATHandler.cpp + athandlertest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "cellular") diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/athandler/unittest.cmake b/connectivity/cellular/tests/UNITTESTS/framework/device/athandler/unittest.cmake deleted file mode 100644 index 8a787df9c7..0000000000 --- a/connectivity/cellular/tests/UNITTESTS/framework/device/athandler/unittest.cmake +++ /dev/null @@ -1,48 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - ../platform - ../connectivity/cellular/tests/UNITTESTS/framework/common/util - ../connectivity/cellular/include/cellular/framework/common - ../connectivity/cellular/include/cellular/framework/AT - ../platform/randlib/include/mbed-client-randlib - -) - -# Source files -set(unittest-sources - ../connectivity/cellular/source/framework/device/ATHandler.cpp -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/athandlertest.cpp - stubs/EventQueue_stub.cpp - stubs/FileHandle_stub.cpp - stubs/us_ticker_stub.cpp - stubs/BufferedSerial_stub.cpp - stubs/SerialBase_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/mbed_poll_stub.cpp - stubs/equeue_stub.c - stubs/Kernel_stub.cpp - stubs/ThisThread_stub.cpp - stubs/randLIB_stub.cpp - stubs/CellularUtil_stub.cpp - stubs/ConditionVariable_stub.cpp - stubs/Mutex_stub.cpp - stubs/mbed_rtos_rtx_stub.c - stubs/rtx_mutex_stub.c -) - -set(unittest-test-flags - -DMBED_CONF_CELLULAR_DEBUG_AT=true - -DOS_STACK_SIZE=2048 - -DDEVICE_SERIAL=1 - -DDEVICE_INTERRUPTIN=1 - -DMBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 -) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/cellularcontext/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/device/cellularcontext/CMakeLists.txt new file mode 100644 index 0000000000..c774d6ce2e --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/device/cellularcontext/CMakeLists.txt @@ -0,0 +1,46 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME cellular-framework-device-cellular-context-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MDMRTS=PTC0 + MDMCTS=PTC1 + MDMTXD=NC + MDMRXD=NC + CELLULAR_DEVICE=myCellularDevice + DEVICE_SERIAL_FC=1 + MBED_CONF_CELLULAR_CONTROL_PLANE_OPT=0 + MBED_CONF_CELLULAR_USE_SMS=1 + DEVICE_SERIAL=1 + DEVICE_INTERRUPTIN=1 + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 + MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/cellular/source/framework/device/CellularContext.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + cellularcontexttest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "cellular") diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/cellularcontext/unittest.cmake b/connectivity/cellular/tests/UNITTESTS/framework/device/cellularcontext/unittest.cmake deleted file mode 100644 index 8bbb4c4a8a..0000000000 --- a/connectivity/cellular/tests/UNITTESTS/framework/device/cellularcontext/unittest.cmake +++ /dev/null @@ -1,59 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - ../connectivity/cellular/include/cellular/framework/device/cellulardevice - ../connectivity/cellular/include/cellular/framework/device - ../connectivity/cellular/include/cellular/framework/common -) - -# Source files -set(unittest-sources - ../connectivity/cellular/source/framework/device/CellularContext.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c - ../connectivity/netsocket/source/SocketAddress.cpp -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/cellularcontexttest.cpp - stubs/FileHandle_stub.cpp - stubs/CellularStateMachine_stub.cpp - stubs/EventQueue_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/BufferedSerial_stub.cpp - stubs/SerialBase_stub.cpp - stubs/ATHandler_stub.cpp - stubs/AT_CellularNetwork_stub.cpp - stubs/AT_CellularContext_stub.cpp - stubs/AT_CellularDevice_stub.cpp - stubs/Semaphore_stub.cpp - stubs/NetworkInterface_stub.cpp - stubs/NetworkInterfaceDefaults_stub.cpp - stubs/CellularDevice_stub.cpp - stubs/equeue_stub.c - stubs/ThisThread_stub.cpp - stubs/ConditionVariable_stub.cpp - stubs/Mutex_stub.cpp -) - -set(unittest-test-flags - -DMDMRTS=PTC0 - -DMDMCTS=PTC1 - -DMDMTXD=NC - -DMDMRXD=NC - -DMBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 - -DCELLULAR_DEVICE=myCellularDevice - -DDEVICE_SERIAL_FC=1 - -DMBED_CONF_CELLULAR_CONTROL_PLANE_OPT=0 - -DDEVICE_SERIAL=1 - -DDEVICE_INTERRUPTIN=1 - -DMBED_CONF_CELLULAR_USE_SMS=1 -) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/cellulardevice/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/device/cellulardevice/CMakeLists.txt new file mode 100644 index 0000000000..b903eb0868 --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/device/cellulardevice/CMakeLists.txt @@ -0,0 +1,38 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME cellular-framework-device-cellular-device-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MDMRTS=PTC0 + MDMCTS=PTC1 + MDMTXD=NC + MDMRXD=NC + CELLULAR_DEVICE=myCellularDevice + DEVICE_SERIAL_FC=1 + DEVICE_SERIAL=1 + DEVICE_INTERRUPTIN=1 + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 + MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/cellular/source/framework/device/CellularDevice.cpp + cellulardevicetest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "cellular") diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/cellulardevice/unittest.cmake b/connectivity/cellular/tests/UNITTESTS/framework/device/cellulardevice/unittest.cmake deleted file mode 100644 index b0052a7ec8..0000000000 --- a/connectivity/cellular/tests/UNITTESTS/framework/device/cellulardevice/unittest.cmake +++ /dev/null @@ -1,50 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - ../connectivity/cellular/include/cellular/framework/device/cellulardevice - ../connectivity/cellular/include/cellular/framework/device - ../connectivity/cellular/include/cellular/framework/common -) - -# Source files -set(unittest-sources - ../connectivity/cellular/source/framework/device/CellularDevice.cpp -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/cellulardevicetest.cpp - stubs/FileHandle_stub.cpp - stubs/CellularStateMachine_stub.cpp - stubs/EventQueue_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/BufferedSerial_stub.cpp - stubs/SerialBase_stub.cpp - stubs/ATHandler_stub.cpp - stubs/AT_CellularNetwork_stub.cpp - stubs/AT_CellularContext_stub.cpp - stubs/AT_CellularDevice_stub.cpp - stubs/Semaphore_stub.cpp - stubs/NetworkInterface_stub.cpp - stubs/NetworkInterfaceDefaults_stub.cpp - stubs/CellularContext_stub.cpp - stubs/ConditionVariable_stub.cpp - stubs/Mutex_stub.cpp - stubs/mbed_shared_queues_stub.cpp -) - -set(unittest-test-flags - -DMDMRTS=PTC0 - -DMDMCTS=PTC1 - -DMDMTXD=NC - -DMDMRXD=NC - -DMBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 - -DCELLULAR_DEVICE=myCellularDevice - -DDEVICE_SERIAL_FC=1 - -DDEVICE_SERIAL=1 - -DDEVICE_INTERRUPTIN=1 -) diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/CMakeLists.txt b/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/CMakeLists.txt new file mode 100644 index 0000000000..00d3b3bd42 --- /dev/null +++ b/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/CMakeLists.txt @@ -0,0 +1,39 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME cellular-framework-device-cellular-state-machine-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MDMRTS=PTC0 + MDMCTS=PTC1 + MDMTXD=NC + MDMRXD=NC + CELLULAR_DEVICE=myCellularDevice + DEVICE_SERIAL_FC=1 + MBED_CONF_RTOS_PRESENT=1 + DEVICE_SERIAL=1 + DEVICE_INTERRUPTIN=1 + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 + MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/cellular/source/framework/device/CellularStateMachine.cpp + cellularstatemachinetest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "cellular") diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/cellularstatemachinetest.cpp b/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/cellularstatemachinetest.cpp index 8f4ad47e62..96c9b89d0c 100644 --- a/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/cellularstatemachinetest.cpp +++ b/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/cellularstatemachinetest.cpp @@ -23,7 +23,7 @@ #include "AT_CellularNetwork_stub.h" #include "myCellularDevice.h" #include "Thread_stub.h" -#include "cmsis_os2.h" +#include "mbed_rtos_types.h" #include "equeue_stub.h" using namespace mbed; diff --git a/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/unittest.cmake b/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/unittest.cmake deleted file mode 100644 index 1d628e13d0..0000000000 --- a/connectivity/cellular/tests/UNITTESTS/framework/device/cellularstatemachine/unittest.cmake +++ /dev/null @@ -1,55 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - ../connectivity/cellular/include/cellular/framework/device/cellularstatemachine - ../connectivity/cellular/include/cellular/framework/device - ../connectivity/cellular/include/cellular/framework/common -) - -# Source files -set(unittest-sources - ../connectivity/cellular/source/framework/device/CellularStateMachine.cpp -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/cellularstatemachinetest.cpp - stubs/FileHandle_stub.cpp - stubs/CellularDevice_stub.cpp - stubs/EventQueue_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/BufferedSerial_stub.cpp - stubs/SerialBase_stub.cpp - stubs/ATHandler_stub.cpp - stubs/AT_CellularNetwork_stub.cpp - stubs/AT_CellularContext_stub.cpp - stubs/AT_CellularDevice_stub.cpp - stubs/Semaphore_stub.cpp - stubs/NetworkInterface_stub.cpp - stubs/NetworkInterfaceDefaults_stub.cpp - stubs/Thread_stub.cpp - stubs/Mutex_stub.cpp - stubs/EventQueue_stub.cpp - stubs/equeue_stub.c - stubs/CellularContext_stub.cpp - stubs/ConditionVariable_stub.cpp - stubs/Mutex_stub.cpp -) - -set(unittest-test-flags - -DMDMRTS=PTC0 - -DMDMCTS=PTC1 - -DMDMTXD=NC - -DMDMRXD=NC - -DMBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 - -DCELLULAR_DEVICE=myCellularDevice - -DDEVICE_SERIAL_FC=1 - -DMBED_CONF_RTOS_PRESENT=1 - -DDEVICE_SERIAL=1 - -DDEVICE_INTERRUPTIN=1 - -DMBED_CONF_CELLULAR_USE_SMS=1 -) diff --git a/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_BlueNRG_2/BlueNrg2HCIDriver.cpp b/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_BlueNRG_2/BlueNrg2HCIDriver.cpp index acc9346734..1800de7e1c 100644 --- a/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_BlueNRG_2/BlueNrg2HCIDriver.cpp +++ b/connectivity/drivers/ble/FEATURE_BLE/COMPONENT_BlueNRG_2/BlueNrg2HCIDriver.cpp @@ -60,7 +60,11 @@ #define RANDOM_STATIC_ADDRESS_OFFSET 0x80 #define LL_WITHOUT_HOST_OFFSET 0x2C +#ifdef NDEBUG #define SPI_STACK_SIZE 1024 +#else +#define SPI_STACK_SIZE 2048 +#endif #define IRQ_TIMEOUT_DURATION 100 //ms diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/HCIDriver.cpp b/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/HCIDriver.cpp index 7d9ab4852c..03339e7402 100644 --- a/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/HCIDriver.cpp +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/HCIDriver.cpp @@ -28,6 +28,7 @@ #include "bstream.h" #include "hci_mbed_os_adaptation.h" #include "mbed_trace.h" +#include "platform/mbed_error.h" /* STM32WB include files */ #include "stm32wbxx_ll_ipcc.h" @@ -83,7 +84,9 @@ static bool get_bd_address(uint8_t *bd_addr); static bool sysevt_wait(void); static bool sysevt_check(void); +#if DEVICE_FLASH extern int BLE_inited; +#endif namespace ble { namespace vendor { @@ -130,7 +133,8 @@ public: HciResetCmd(); } - static uint8_t convert_db_to_tx_power_index(int8_t level_db) { + static uint8_t convert_db_to_tx_power_index(int8_t level_db) + { const int8_t conversion[] = { -40, -21, -20, -19, -18, -16, -15, -14, @@ -151,7 +155,8 @@ public: return index; } - virtual ble_error_t set_tx_power(int8_t level_db) { + virtual ble_error_t set_tx_power(int8_t level_db) + { uint8_t buf[2]; @@ -480,10 +485,43 @@ public: WirelessFwInfo_t wireless_info_instance; WirelessFwInfo_t *p_wireless_info = &wireless_info_instance; if (SHCI_GetWirelessFwInfo(p_wireless_info) != SHCI_Success) { - tr_info("SHCI_GetWirelessFwInfo error"); + tr_error("SHCI_GetWirelessFwInfo error"); } else { + // https://github.com/STMicroelectronics/STM32CubeWB/tree/master/Projects/STM32WB_Copro_Wireless_Binaries + // Be sure that you are using the latest BLE FW version tr_info("WIRELESS COPROCESSOR FW VERSION ID = %d.%d.%d", p_wireless_info->VersionMajor, p_wireless_info->VersionMinor, p_wireless_info->VersionSub); - tr_info("WIRELESS COPROCESSOR FW STACK TYPE = %d", p_wireless_info->StackType); + tr_info("WIRELESS COPROCESSOR FW STACK TYPE = %d (ROM size 0x%x)", p_wireless_info->StackType, MBED_ROM_SIZE); + +#if STM32WB15xx + switch (p_wireless_info->StackType) { + case INFO_STACK_TYPE_BLE_FULL: + error("Wrong BLE FW\n"); + break; + case INFO_STACK_TYPE_BLE_HCI: + if (MBED_ROM_SIZE > 0x32800) { + error("Wrong MBED_ROM_SIZE with HCI FW\n"); + } + break; + default: + tr_error("StackType %u not expected\n", p_wireless_info->StackType); + } +#endif +#if STM32WB55xx + switch (p_wireless_info->StackType) { + case INFO_STACK_TYPE_BLE_FULL: + if (MBED_ROM_SIZE > 0xCA000) { + error("Wrong MBED_ROM_SIZE with BLE FW\n"); + } + break; + case INFO_STACK_TYPE_BLE_HCI: + if (MBED_ROM_SIZE > 0xE0000) { + error("Wrong MBED_ROM_SIZE with HCI FW\n"); + } + break; + default: + tr_error("StackType %u not expected\n", p_wireless_info->StackType); + } +#endif } } } @@ -532,7 +570,7 @@ private: /* At this stage, we'll need to wait for ready event, * passed thru TL_SYS_EvtReceived */ if (!sysevt_wait()) { - tr_info("ERROR booting WB controler"); + error("ERROR booting WB controler\n"); return; } @@ -659,8 +697,10 @@ private: */ SHCI_C2_BLE_Init(&ble_init_cmd_packet); +#if DEVICE_FLASH /* Used in flash_api.c */ BLE_inited = 1; +#endif } TL_CmdPacket_t *bleCmdBuf; diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/STM32Cube_FW/shci.h b/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/STM32Cube_FW/shci.h index 435a4e17a5..fc27b571dd 100644 --- a/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/STM32Cube_FW/shci.h +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/STM32Cube_FW/shci.h @@ -435,7 +435,7 @@ extern "C" { * PrWriteListSize * NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure ) * - * Maximum number of supported “prepare write request” + * Maximum number of supported “prepare write request” * - Min value: given by the macro DEFAULT_PREP_WRITE_LIST_SIZE * - Max value: a value higher than the minimum required can be specified, but it is not recommended */ @@ -502,7 +502,7 @@ extern "C" { * MaxConnEventLength * This parameter determines the maximum duration of a slave connection event. When this duration is reached the slave closes * the current connections event (whatever is the CE_length parameter specified by the master in HCI_CREATE_CONNECTION HCI command), - * expressed in units of 625/256 µs (~2.44 µs) + * expressed in units of 625/256 µs (~2.44 µs) * - Min value: 0 (if 0 is specified, the master and slave perform only a single TX-RX exchange per connection event) * - Max value: 1638400 (4000 ms). A higher value can be specified (max 0xFFFFFFFF) but results in a maximum connection time * of 4000 ms as specified. In this case the parameter is not applied, and the predicted CE length calculated on slave is not shortened @@ -511,7 +511,7 @@ extern "C" { /** * HsStartupTime - * Startup time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 µs (~2.44 µs). + * Startup time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 µs (~2.44 µs). * - Min value: 0 * - Max value: 820 (~2 ms). A higher value can be specified, but the value that implemented in stack is forced to ~2 ms */ diff --git a/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/mbed_lib.json b/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/mbed_lib.json index b0c80f5002..13d17bcf08 100644 --- a/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/mbed_lib.json +++ b/connectivity/drivers/ble/FEATURE_BLE/TARGET_STM32WB/mbed_lib.json @@ -1,3 +1,4 @@ { - "name": "cordio-stm32wb" + "name": "cordio-stm32wb", + "requires": ["cordio", "ble"] } diff --git a/connectivity/drivers/cellular/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp b/connectivity/drivers/cellular/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp index e0ce8bffdf..bc71cb26a2 100644 --- a/connectivity/drivers/cellular/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp +++ b/connectivity/drivers/cellular/QUECTEL/BG96/QUECTEL_BG96_CellularStack.cpp @@ -20,6 +20,7 @@ #include "QUECTEL/BG96/QUECTEL_BG96_CellularStack.h" #include "CellularLog.h" #include "netsocket/TLSSocket.h" +#include "CellularUtil.h" // Ref: Quectel_BG96_SSL_AT_Commands_Manual, ch 2.1.1 AT+QSSLCFG static const int BG96_SUPPORTED_SSL_VERSION = 4; // All @@ -157,6 +158,40 @@ nsapi_error_t QUECTEL_BG96_CellularStack::socket_connect(nsapi_socket_t handle, return err; } +nsapi_error_t QUECTEL_BG96_CellularStack::get_ip_address(SocketAddress *address) +{ + if (!address) { + return NSAPI_ERROR_PARAMETER; + } + _at.lock(); + + _at.cmd_start_stop("+QIACT", "?"); + _at.resp_start("+QIACT:"); + + int32_t context_type = 0; + + if (_at.info_resp()) { + _at.skip_param(); // ID + _at.skip_param(); // State + + context_type = _at.read_int(); + if (context_type == 1) { + _stack_type = IPV4_STACK; + } else if (context_type == 2) { + _stack_type = IPV6_STACK; + } + + if (_at.read_string(_ip, PDP_IPV6_SIZE) != -1) { + mbed_cellular_util::convert_ipv6(_ip); + address->set_ip_address(_ip); + } + } + _at.resp_stop(); + _at.unlock(); + + return (context_type > 0) ? NSAPI_ERROR_OK : NSAPI_ERROR_NO_ADDRESS; +} + void QUECTEL_BG96_CellularStack::urc_qiurc_recv() { urc_qiurc(URC_RECV); diff --git a/connectivity/drivers/cellular/QUECTEL/BG96/QUECTEL_BG96_CellularStack.h b/connectivity/drivers/cellular/QUECTEL/BG96/QUECTEL_BG96_CellularStack.h index 77fa70970a..015ab93348 100644 --- a/connectivity/drivers/cellular/QUECTEL/BG96/QUECTEL_BG96_CellularStack.h +++ b/connectivity/drivers/cellular/QUECTEL/BG96/QUECTEL_BG96_CellularStack.h @@ -47,6 +47,8 @@ protected: // NetworkStack virtual nsapi_error_t socket_connect(nsapi_socket_t handle, const SocketAddress &address); + virtual nsapi_error_t get_ip_address(SocketAddress *address); + #ifdef MBED_CONF_CELLULAR_OFFLOAD_DNS_QUERIES virtual nsapi_error_t gethostbyname(const char *host, SocketAddress *address, nsapi_version_t version, const char *interface_name); virtual nsapi_value_or_error_t gethostbyname_async(const char *host, hostbyname_cb_t callback, nsapi_version_t version = NSAPI_UNSPEC, diff --git a/connectivity/drivers/emac/CMakeLists.txt b/connectivity/drivers/emac/CMakeLists.txt index 21f104947c..56e7f474ea 100644 --- a/connectivity/drivers/emac/CMakeLists.txt +++ b/connectivity/drivers/emac/CMakeLists.txt @@ -25,6 +25,10 @@ elseif("Silicon_Labs" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_Silicon_Labs) endif() +if("WHD" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(COMPONENT_WHD) +endif() + target_link_libraries(mbed-emac INTERFACE mbed-netsocket diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/CMakeLists.txt b/connectivity/drivers/emac/COMPONENT_WHD/CMakeLists.txt similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/CMakeLists.txt rename to connectivity/drivers/emac/COMPONENT_WHD/CMakeLists.txt diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/CyDhcpServer.cpp b/connectivity/drivers/emac/COMPONENT_WHD/interface/CyDhcpServer.cpp similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/CyDhcpServer.cpp rename to connectivity/drivers/emac/COMPONENT_WHD/interface/CyDhcpServer.cpp diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/CyDhcpServer.h b/connectivity/drivers/emac/COMPONENT_WHD/interface/CyDhcpServer.h similarity index 99% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/CyDhcpServer.h rename to connectivity/drivers/emac/COMPONENT_WHD/interface/CyDhcpServer.h index b11d0317cd..fd22eaec47 100644 --- a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/CyDhcpServer.h +++ b/connectivity/drivers/emac/COMPONENT_WHD/interface/CyDhcpServer.h @@ -100,7 +100,7 @@ private: NetworkStack *_nstack = NULL; NetworkInterface *_niface = NULL; UDPSocket _socket; - Thread _thread; + rtos::Thread _thread; bool _running = false; cy_ip_addr_t _available_addr; diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/WhdAccessPoint.cpp b/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdAccessPoint.cpp similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/WhdAccessPoint.cpp rename to connectivity/drivers/emac/COMPONENT_WHD/interface/WhdAccessPoint.cpp diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/WhdAccessPoint.h b/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdAccessPoint.h similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/WhdAccessPoint.h rename to connectivity/drivers/emac/COMPONENT_WHD/interface/WhdAccessPoint.h diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp b/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.cpp similarity index 99% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp rename to connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.cpp index af14a7e2c4..6fec15adb0 100644 --- a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp +++ b/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.cpp @@ -27,6 +27,7 @@ #include "whd_emac.h" #include "whd_wifi_api.h" #include "whd_wlioctl.h" +#include "cy_utils.h" #define CMP_MAC( a, b ) (((((unsigned char*)a)[0])==(((unsigned char*)b)[0]))&& \ ((((unsigned char*)a)[1])==(((unsigned char*)b)[1]))&& \ diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.h b/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.h similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.h rename to connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSTAInterface.h diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/WhdSoftAPInterface.cpp b/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSoftAPInterface.cpp similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/WhdSoftAPInterface.cpp rename to connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSoftAPInterface.cpp diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/WhdSoftAPInterface.h b/connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSoftAPInterface.h similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/WhdSoftAPInterface.h rename to connectivity/drivers/emac/COMPONENT_WHD/interface/WhdSoftAPInterface.h diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/emac_eapol.h b/connectivity/drivers/emac/COMPONENT_WHD/interface/emac_eapol.h similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/emac_eapol.h rename to connectivity/drivers/emac/COMPONENT_WHD/interface/emac_eapol.h diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/whd_emac.cpp b/connectivity/drivers/emac/COMPONENT_WHD/interface/whd_emac.cpp similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/whd_emac.cpp rename to connectivity/drivers/emac/COMPONENT_WHD/interface/whd_emac.cpp diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/whd_emac.h b/connectivity/drivers/emac/COMPONENT_WHD/interface/whd_emac.h similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/whd_emac.h rename to connectivity/drivers/emac/COMPONENT_WHD/interface/whd_emac.h diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/whd_interface.cpp b/connectivity/drivers/emac/COMPONENT_WHD/interface/whd_interface.cpp similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/whd_interface.cpp rename to connectivity/drivers/emac/COMPONENT_WHD/interface/whd_interface.cpp diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/whd_interface.h b/connectivity/drivers/emac/COMPONENT_WHD/interface/whd_interface.h similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/interface/whd_interface.h rename to connectivity/drivers/emac/COMPONENT_WHD/interface/whd_interface.h diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/network/whd_network.h b/connectivity/drivers/emac/COMPONENT_WHD/network/whd_network.h similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/network/whd_network.h rename to connectivity/drivers/emac/COMPONENT_WHD/network/whd_network.h diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/utils/cydhcp_server_debug.cpp b/connectivity/drivers/emac/COMPONENT_WHD/utils/cydhcp_server_debug.cpp similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/utils/cydhcp_server_debug.cpp rename to connectivity/drivers/emac/COMPONENT_WHD/utils/cydhcp_server_debug.cpp diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/utils/cynetwork_utils.c b/connectivity/drivers/emac/COMPONENT_WHD/utils/cynetwork_utils.c similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/utils/cynetwork_utils.c rename to connectivity/drivers/emac/COMPONENT_WHD/utils/cynetwork_utils.c diff --git a/connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/utils/cynetwork_utils.h b/connectivity/drivers/emac/COMPONENT_WHD/utils/cynetwork_utils.h similarity index 100% rename from connectivity/drivers/emac/TARGET_Cypress/COMPONENT_WHD/utils/cynetwork_utils.h rename to connectivity/drivers/emac/COMPONENT_WHD/utils/cynetwork_utils.h diff --git a/connectivity/drivers/emac/TARGET_Cypress/CMakeLists.txt b/connectivity/drivers/emac/TARGET_Cypress/CMakeLists.txt index 9c4697181d..748188c205 100644 --- a/connectivity/drivers/emac/TARGET_Cypress/CMakeLists.txt +++ b/connectivity/drivers/emac/TARGET_Cypress/CMakeLists.txt @@ -4,7 +4,3 @@ if("SCL" IN_LIST MBED_TARGET_LABELS) add_subdirectory(COMPONENT_SCL) endif() - -if("WHD" IN_LIST MBED_TARGET_LABELS) - add_subdirectory(COMPONENT_WHD) -endif() diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c index 4f674d0aef..2adb1a9b99 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c @@ -61,14 +61,13 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) { GPIO_InitTypeDef GPIO_InitStruct; - if(heth->Instance == ETH) - { + if (heth->Instance == ETH) { enableEthPowerSupply(); - - #if !(defined(DUAL_CORE) && defined(CORE_CM4)) + +#if !(defined(DUAL_CORE) && defined(CORE_CM4)) /* Disable DCache for STM32H7 family */ SCB_DisableDCache(); - #endif +#endif /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); @@ -118,21 +117,21 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) PC4 ------> ETH_RXD0 PC5 ------> ETH_RXD1 */ - GPIO_InitStruct.Pin = ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin; + GPIO_InitStruct.Pin = ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF11_ETH; HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin; + GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF11_ETH; HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - GPIO_InitStruct.Pin = ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin; + GPIO_InitStruct.Pin = ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; @@ -146,8 +145,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) */ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) { - if(heth->Instance == ETH) - { + if (heth->Instance == ETH) { /* Peripheral clock disable */ __HAL_RCC_ETH1MAC_CLK_DISABLE(); __HAL_RCC_ETH1TX_CLK_DISABLE(); @@ -164,11 +162,11 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) PC4 ------> ETH_RXD0 PC5 ------> ETH_RXD1 */ - HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin); + HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin); - HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin); + HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin); - HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin); + HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin); HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0); } diff --git a/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_LoRaRadio.cpp b/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_LoRaRadio.cpp index 79c7043b02..6a7df14b8d 100644 --- a/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_LoRaRadio.cpp +++ b/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_LoRaRadio.cpp @@ -123,16 +123,10 @@ static DigitalOut _rf_dbg_tx(MBED_CONF_STM32WL_LORA_DRIVER_DEBUG_TX, 0); #endif -STM32WL_LoRaRadio::STM32WL_LoRaRadio(PinName rf_switch_ctrl1, - PinName rf_switch_ctrl2, - PinName rf_switch_ctrl3 - ) - : - _rf_switch_ctrl1(rf_switch_ctrl1, 0), - _rf_switch_ctrl2(rf_switch_ctrl2, 0), - _rf_switch_ctrl3(rf_switch_ctrl3, 0) - +STM32WL_LoRaRadio::STM32WL_LoRaRadio() { + set_antenna_switch(RBI_SWITCH_OFF); + _radio_events = NULL; _image_calibrated = false; _force_image_calibration = false; @@ -481,49 +475,6 @@ void STM32WL_LoRaRadio::Radio_SMPS_Set(uint8_t level) } } -/** - * Sets up radio switch position according to the - * radio mode - */ -void STM32WL_LoRaRadio::set_antenna_switch(RBI_Switch_TypeDef state) -{ - // here we got to do ifdef for changing controls - // as some pins might be NC - switch (state) { - case RBI_SWITCH_OFF: { - /* Turn off switch */ - _rf_switch_ctrl3 = 0; - _rf_switch_ctrl1 = 0; - _rf_switch_ctrl2 = 0; - break; - } - case RBI_SWITCH_RX: { - /*Turns On in Rx Mode the RF Switch */ - _rf_switch_ctrl3 = 1; - _rf_switch_ctrl1 = 1; - _rf_switch_ctrl2 = 0; - break; - } - case RBI_SWITCH_RFO_LP: { - /*Turns On in Tx Low Power the RF Switch */ - _rf_switch_ctrl3 = 1; - _rf_switch_ctrl1 = 1; - _rf_switch_ctrl2 = 1; - break; - } - case RBI_SWITCH_RFO_HP: { - /*Turns On in Tx High Power the RF Switch */ - _rf_switch_ctrl3 = 1; - _rf_switch_ctrl1 = 0; - _rf_switch_ctrl2 = 1; - break; - } - default: - break; - } -} -/* End STM32WL specific HW defs */ - void STM32WL_LoRaRadio::calibrate_image(uint32_t freq) { uint8_t cal_freq[2]; diff --git a/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_LoRaRadio.h b/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_LoRaRadio.h index 81c0a598c4..a2835cecc5 100644 --- a/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_LoRaRadio.h +++ b/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_LoRaRadio.h @@ -51,16 +51,14 @@ SPDX-License-Identifier: BSD-3-Clause #define MAX_DATA_BUFFER_SIZE_STM32WL 255 #endif - +extern void set_antenna_switch(RBI_Switch_TypeDef state); class STM32WL_LoRaRadio : public LoRaRadio { public: - STM32WL_LoRaRadio(PinName rf_switch_ctrl1 = MBED_CONF_STM32WL_LORA_DRIVER_RF_SWITCH_CTL1, - PinName rf_switch_ctrl2 = MBED_CONF_STM32WL_LORA_DRIVER_RF_SWITCH_CTL2, - PinName rf_switch_ctrl3 = MBED_CONF_STM32WL_LORA_DRIVER_RF_SWITCH_CTL3); + STM32WL_LoRaRadio(); - virtual ~STM32WL_LoRaRadio(); + ~STM32WL_LoRaRadio(); /** * Registers radio events with the Mbed LoRaWAN stack and @@ -315,11 +313,6 @@ public: private: - // Radio specific controls (TX/RX duplexer switch control) - mbed::DigitalOut _rf_switch_ctrl1; - mbed::DigitalOut _rf_switch_ctrl2; - mbed::DigitalOut _rf_switch_ctrl3; - // Access protection PlatformMutex mutex; @@ -369,7 +362,6 @@ private: uint8_t SUBGRF_SetRfTxPower(int8_t power); void SUBGRF_SetTxParams(uint8_t paSelect, int8_t power, radio_ramp_time_t rampTime); void Radio_SMPS_Set(uint8_t level); - void set_antenna_switch(RBI_Switch_TypeDef state); uint32_t RadioGetWakeupTime(void); diff --git a/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_radio_driver.cpp b/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_radio_driver.cpp new file mode 100644 index 0000000000..2640b3a95d --- /dev/null +++ b/connectivity/drivers/lora/TARGET_STM32WL/STM32WL_radio_driver.cpp @@ -0,0 +1,64 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "STM32WL_radio_driver.h" +#include "drivers/DigitalOut.h" + + +/* Sets up radio switch position according to the radio mode */ +/* This configuration is for NUCLEO_WL55JC */ +/* But provided as __weak so it has to be overwritten to match each specicific HW board */ +MBED_WEAK void set_antenna_switch(RBI_Switch_TypeDef state) +{ + + // Radio specific controls (TX/RX duplexer switch control) + mbed::DigitalOut _rf_switch_ctrl1(MBED_CONF_STM32WL_LORA_DRIVER_RF_SWITCH_CTL1); + mbed::DigitalOut _rf_switch_ctrl2(MBED_CONF_STM32WL_LORA_DRIVER_RF_SWITCH_CTL2); + mbed::DigitalOut _rf_switch_ctrl3(MBED_CONF_STM32WL_LORA_DRIVER_RF_SWITCH_CTL3); + + switch (state) { + case RBI_SWITCH_OFF: { + /* Turn off switch */ + _rf_switch_ctrl3 = 0; + _rf_switch_ctrl1 = 0; + _rf_switch_ctrl2 = 0; + break; + } + case RBI_SWITCH_RX: { + /*Turns On in Rx Mode the RF Switch */ + _rf_switch_ctrl3 = 1; + _rf_switch_ctrl1 = 1; + _rf_switch_ctrl2 = 0; + break; + } + case RBI_SWITCH_RFO_LP: { + /*Turns On in Tx Low Power the RF Switch */ + _rf_switch_ctrl3 = 1; + _rf_switch_ctrl1 = 1; + _rf_switch_ctrl2 = 1; + break; + } + case RBI_SWITCH_RFO_HP: { + /*Turns On in Tx High Power the RF Switch */ + _rf_switch_ctrl3 = 1; + _rf_switch_ctrl1 = 0; + _rf_switch_ctrl2 = 1; + break; + } + default: + break; + } +} + diff --git a/connectivity/drivers/wifi/CMakeLists.txt b/connectivity/drivers/wifi/CMakeLists.txt index 5a7bd97647..6ca3b2f092 100644 --- a/connectivity/drivers/wifi/CMakeLists.txt +++ b/connectivity/drivers/wifi/CMakeLists.txt @@ -3,6 +3,8 @@ add_subdirectory(TARGET_WICED EXCLUDE_FROM_ALL) +add_subdirectory(COMPONENT_WHD EXCLUDE_FROM_ALL) + add_subdirectory(esp8266-driver) target_link_libraries(mbed-wifi diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/CMakeLists.txt b/connectivity/drivers/wifi/COMPONENT_WHD/CMakeLists.txt similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/CMakeLists.txt rename to connectivity/drivers/wifi/COMPONENT_WHD/CMakeLists.txt index 5127c51734..a273a0a69c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/CMakeLists.txt +++ b/connectivity/drivers/wifi/COMPONENT_WHD/CMakeLists.txt @@ -1,6 +1,8 @@ # Copyright (c) 2020-2021 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +add_subdirectory(network EXCLUDE_FROM_ALL) + add_library(mbed-cy-psoc6-whd-43012 INTERFACE) target_include_directories(mbed-cy-psoc6-whd-43012 INTERFACE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/generated_mac_address.txt b/connectivity/drivers/wifi/COMPONENT_WHD/generated_mac_address.txt similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/generated_mac_address.txt rename to connectivity/drivers/wifi/COMPONENT_WHD/generated_mac_address.txt diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd.h b/connectivity/drivers/wifi/COMPONENT_WHD/inc/whd.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd.h rename to connectivity/drivers/wifi/COMPONENT_WHD/inc/whd.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd_events.h b/connectivity/drivers/wifi/COMPONENT_WHD/inc/whd_events.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd_events.h rename to connectivity/drivers/wifi/COMPONENT_WHD/inc/whd_events.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd_network_types.h b/connectivity/drivers/wifi/COMPONENT_WHD/inc/whd_network_types.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd_network_types.h rename to connectivity/drivers/wifi/COMPONENT_WHD/inc/whd_network_types.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd_resource_api.h b/connectivity/drivers/wifi/COMPONENT_WHD/inc/whd_resource_api.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd_resource_api.h rename to connectivity/drivers/wifi/COMPONENT_WHD/inc/whd_resource_api.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd_types.h b/connectivity/drivers/wifi/COMPONENT_WHD/inc/whd_types.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd_types.h rename to connectivity/drivers/wifi/COMPONENT_WHD/inc/whd_types.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd_version.h b/connectivity/drivers/wifi/COMPONENT_WHD/inc/whd_version.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd_version.h rename to connectivity/drivers/wifi/COMPONENT_WHD/inc/whd_version.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd_wifi_api.h b/connectivity/drivers/wifi/COMPONENT_WHD/inc/whd_wifi_api.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/inc/whd_wifi_api.h rename to connectivity/drivers/wifi/COMPONENT_WHD/inc/whd_wifi_api.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/mbed_lib.json b/connectivity/drivers/wifi/COMPONENT_WHD/mbed_lib.json similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/mbed_lib.json rename to connectivity/drivers/wifi/COMPONENT_WHD/mbed_lib.json diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/CMakeLists.txt b/connectivity/drivers/wifi/COMPONENT_WHD/network/CMakeLists.txt similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/CMakeLists.txt rename to connectivity/drivers/wifi/COMPONENT_WHD/network/CMakeLists.txt diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/cy_network_buffer.c b/connectivity/drivers/wifi/COMPONENT_WHD/network/cy_network_buffer.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/cy_network_buffer.c rename to connectivity/drivers/wifi/COMPONENT_WHD/network/cy_network_buffer.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/cy_network_buffer.h b/connectivity/drivers/wifi/COMPONENT_WHD/network/cy_network_buffer.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/cy_network_buffer.h rename to connectivity/drivers/wifi/COMPONENT_WHD/network/cy_network_buffer.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/cy_wifi_fw_section.h b/connectivity/drivers/wifi/COMPONENT_WHD/network/cy_wifi_fw_section.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/cy_wifi_fw_section.h rename to connectivity/drivers/wifi/COMPONENT_WHD/network/cy_wifi_fw_section.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/cybsp_wifi.c b/connectivity/drivers/wifi/COMPONENT_WHD/network/cybsp_wifi.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/cybsp_wifi.c rename to connectivity/drivers/wifi/COMPONENT_WHD/network/cybsp_wifi.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/cybsp_wifi.h b/connectivity/drivers/wifi/COMPONENT_WHD/network/cybsp_wifi.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/cybsp_wifi.h rename to connectivity/drivers/wifi/COMPONENT_WHD/network/cybsp_wifi.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/mbed_lib.json b/connectivity/drivers/wifi/COMPONENT_WHD/network/mbed_lib.json similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/common/COMPONENT_WHD/mbed_lib.json rename to connectivity/drivers/wifi/COMPONENT_WHD/network/mbed_lib.json diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt b/connectivity/drivers/wifi/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/LICENSE-permissive-binary-license-1.0.txt diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest.bin b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest.bin similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest.bin rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest.bin diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest.clm_blob b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest.clm_blob similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest.clm_blob rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest.clm_blob diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest_bin.c b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest_bin.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest_bin.c rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest_bin.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest_clm_blob.c b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest_clm_blob.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest_clm_blob.c rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43012/43012C0-mfgtest_clm_blob.c diff --git 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rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43012/resources.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43012/resources.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1-mfgtest.bin b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1-mfgtest.bin similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1-mfgtest.bin rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1-mfgtest.bin diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1-mfgtest.clm_blob b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1-mfgtest.clm_blob similarity index 100% rename from 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rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1.clm_blob diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1_bin.c b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1_bin.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1_bin.c rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1_bin.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1_clm_blob.c b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1_clm_blob.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1_clm_blob.c rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43438/43438A1_clm_blob.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43438/resources.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43438/resources.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_43438/resources.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_43438/resources.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest.bin b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest.bin similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest.bin rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest.bin diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest.clm_blob b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest.clm_blob similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest.clm_blob rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest.clm_blob diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest_bin.c b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest_bin.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest_bin.c rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest_bin.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest_clm_blob.c b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest_clm_blob.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest_clm_blob.c rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1-mfgtest_clm_blob.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1.bin b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1.bin similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1.bin rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1.bin diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1.clm_blob b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1.clm_blob similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1.clm_blob rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1.clm_blob diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1_bin.c b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1_bin.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1_bin.c rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1_bin.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1_clm_blob.c b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1_clm_blob.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1_clm_blob.c rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/4343WA1_clm_blob.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/resources.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/resources.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/resources.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4343W/resources.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest.bin b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest.bin similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest.bin rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest.bin diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest.clm_blob b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest.clm_blob similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest.clm_blob rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest.clm_blob diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest_bin.c b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest_bin.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest_bin.c rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest_bin.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest_clm_blob.c b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest_clm_blob.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest_clm_blob.c rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0-mfgtest_clm_blob.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0.bin b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0.bin similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0.bin rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0.bin diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0.clm_blob b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0.clm_blob similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0.clm_blob rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0.clm_blob diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0_bin.c b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0_bin.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0_bin.c rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0_bin.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0_clm_blob.c b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0_clm_blob.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0_clm_blob.c rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/4373A0_clm_blob.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/resources.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/resources.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/firmware/COMPONENT_4373/resources.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/firmware/COMPONENT_4373/resources.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062S2_43012/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062S2_43012/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062S2_43012/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062S2_43012/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062S2_4343W/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062S2_4343W/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062S2_4343W/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062S2_4343W/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062_4343W/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062_4343W/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062_4343W/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062_4343W/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062_WIFI_BT/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062_WIFI_BT/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062_WIFI_BT/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_062_WIFI_BT/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064B0S2_4343W/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064B0S2_4343W/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064B0S2_4343W/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064B0S2_4343W/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064S0S2_4343W/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064S0S2_4343W/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064S0S2_4343W/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064S0S2_4343W/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064S1_4343W/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064S1_4343W/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064S1_4343W/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064S1_4343W/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064S2_4343W/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064S2_4343W/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064S2_4343W/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CKIT_064S2_4343W/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CMOD_062S2_43012/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CMOD_062S2_43012/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CMOD_062S2_43012/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CMOD_062S2_43012/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CMOD_062S3_4343W/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CMOD_062S3_4343W/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CMOD_062S3_4343W/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CMOD_062S3_4343W/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CMOD_062_4343W/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CMOD_062_4343W/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CMOD_062_4343W/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CMOD_062_4343W/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CPROTO_062S3_4343W/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CPROTO_062S3_4343W/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CPROTO_062S3_4343W/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CPROTO_062S3_4343W/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CPROTO_062_4343W/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CPROTO_062_4343W/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CY8CPROTO_062_4343W/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CY8CPROTO_062_4343W/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYTFM_064B0S2_4343W/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYTFM_064B0S2_4343W/wifi_nvram_image.h old mode 100755 new mode 100644 similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYTFM_064B0S2_4343W/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYTFM_064B0S2_4343W/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYW943012P6EVB_01/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYW943012P6EVB_01/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYW943012P6EVB_01/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYW943012P6EVB_01/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYW943012WCD2/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYW943012WCD2/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYW943012WCD2/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYW943012WCD2/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S1_43012CAR_01/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S1_43012CAR_01/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S1_43012CAR_01/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S1_43012CAR_01/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S1_43012EVB_01/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S1_43012EVB_01/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S1_43012EVB_01/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S1_43012EVB_01/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S1_43438EVB_01/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S1_43438EVB_01/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S1_43438EVB_01/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S1_43438EVB_01/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S2_M2BASE_4373/wifi_nvram_image.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S2_M2BASE_4373/wifi_nvram_image.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S2_M2BASE_4373/wifi_nvram_image.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/nvram/TARGET_CYW9P62S2_M2BASE_4373/wifi_nvram_image.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/resource_imp/whd_resources.c b/connectivity/drivers/wifi/COMPONENT_WHD/resources/resource_imp/whd_resources.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/resource_imp/whd_resources.c rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/resource_imp/whd_resources.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/resource_imp/wiced_resource.h b/connectivity/drivers/wifi/COMPONENT_WHD/resources/resource_imp/wiced_resource.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/resources/resource_imp/wiced_resource.h rename to connectivity/drivers/wifi/COMPONENT_WHD/resources/resource_imp/wiced_resource.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_common.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_common.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_common.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_common.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_common.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_common.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_common.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_common.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_protocol_interface.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_protocol_interface.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_protocol_interface.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_protocol_interface.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_sdio_protocol.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_sdio_protocol.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_sdio_protocol.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_sdio_protocol.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_sdio_protocol.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_sdio_protocol.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_sdio_protocol.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_sdio_protocol.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_spi_protocol.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_spi_protocol.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_spi_protocol.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_spi_protocol.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_spi_protocol.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_spi_protocol.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_bus_spi_protocol.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_bus_spi_protocol.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_chip_reg.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_chip_reg.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_chip_reg.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_chip_reg.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_sdio.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_sdio.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_sdio.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_sdio.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_spi.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_spi.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/bus_protocols/whd_spi.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/bus_protocols/whd_spi.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_ap.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_ap.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_ap.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_ap.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_buffer_api.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_buffer_api.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_buffer_api.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_buffer_api.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_cdc_bdc.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_cdc_bdc.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_cdc_bdc.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_cdc_bdc.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_chip.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_chip.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_chip.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_chip.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_chip_constants.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_chip_constants.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_chip_constants.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_chip_constants.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_clm.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_clm.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_clm.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_clm.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_debug.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_debug.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_debug.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_debug.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_endian.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_endian.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_endian.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_endian.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_events_int.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_events_int.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_events_int.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_events_int.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_int.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_int.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_int.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_int.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_network_if.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_network_if.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_network_if.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_network_if.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_poll.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_poll.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_poll.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_poll.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_resource_if.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_resource_if.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_resource_if.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_resource_if.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_sdpcm.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_sdpcm.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_sdpcm.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_sdpcm.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_thread.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_thread.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_thread.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_thread.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_thread_internal.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_thread_internal.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_thread_internal.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_thread_internal.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_types_int.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_types_int.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_types_int.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_types_int.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_utils.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_utils.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_utils.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_utils.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_wifi_p2p.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_wifi_p2p.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_wifi_p2p.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_wifi_p2p.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_wlioctl.h b/connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_wlioctl.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/include/whd_wlioctl.h rename to connectivity/drivers/wifi/COMPONENT_WHD/src/include/whd_wlioctl.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_ap.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_ap.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_ap.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_ap.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_buffer_api.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_buffer_api.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_buffer_api.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_buffer_api.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_cdc_bdc.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_cdc_bdc.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_cdc_bdc.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_cdc_bdc.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_chip.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_chip.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_chip.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_chip.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_chip_constants.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_chip_constants.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_chip_constants.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_chip_constants.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_clm.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_clm.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_clm.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_clm.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_debug.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_debug.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_debug.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_debug.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_events.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_events.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_events.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_events.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_logging.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_logging.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_logging.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_logging.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_management.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_management.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_management.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_management.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_network_if.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_network_if.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_network_if.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_network_if.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_resource_if.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_resource_if.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_resource_if.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_resource_if.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_sdpcm.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_sdpcm.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_sdpcm.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_sdpcm.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_thread.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_thread.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_thread.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_thread.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_utils.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_utils.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_utils.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_utils.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_wifi.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_wifi.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_wifi.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_wifi.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_wifi_api.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_wifi_api.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_wifi_api.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_wifi_api.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_wifi_p2p.c b/connectivity/drivers/wifi/COMPONENT_WHD/src/whd_wifi_p2p.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_WHD/src/whd_wifi_p2p.c rename to connectivity/drivers/wifi/COMPONENT_WHD/src/whd_wifi_p2p.c diff --git a/connectivity/drivers/wifi/TARGET_WICED/CMakeLists.txt b/connectivity/drivers/wifi/TARGET_WICED/CMakeLists.txt index c6f83e6b9c..8bcf3677e3 100644 --- a/connectivity/drivers/wifi/TARGET_WICED/CMakeLists.txt +++ b/connectivity/drivers/wifi/TARGET_WICED/CMakeLists.txt @@ -3,13 +3,15 @@ add_library(mbed-wiced INTERFACE) -if(${MBED_TOOLCHAIN} STREQUAL "ARM") - set(LIB_WICED_DRIVERS TOOLCHAIN_ARMC6/TARGET_WIO_EMW3166/libwiced_drivers.ar) -elseif(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") - set(LIB_WICED_DRIVERS TOOLCHAIN_GCC_ARM/TARGET_WIO_EMW3166/libwiced_drivers.a) -endif() +if(${CMAKE_CROSSCOMPILING}) + if(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(LIB_WICED_DRIVERS TOOLCHAIN_ARMC6/TARGET_WIO_EMW3166/libwiced_drivers.ar) + elseif(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(LIB_WICED_DRIVERS TOOLCHAIN_GCC_ARM/TARGET_WIO_EMW3166/libwiced_drivers.a) + endif() target_link_libraries(mbed-wiced INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/${LIB_WICED_DRIVERS}) +endif() target_include_directories(mbed-wiced INTERFACE diff --git a/connectivity/libraries/mbed-coap/CHANGELOG.md b/connectivity/libraries/mbed-coap/CHANGELOG.md index 256dbcf5c8..ca463f75b0 100644 --- a/connectivity/libraries/mbed-coap/CHANGELOG.md +++ b/connectivity/libraries/mbed-coap/CHANGELOG.md @@ -1,4 +1,18 @@ # Change Log +## [v5.1.11](https://github.com/ARMmbed/mbed-coap/releases/tag/v5.1.11) + +Block-Wise request (block1) error handling improvements: + * Removed SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED usage. Block-Wise requests will now follow normal retranmission rules. + * Process block1 responses only once. If response is coming in wrong order just ignore it wait next response to happen. + +## [v5.1.10](https://github.com/ARMmbed/mbed-coap/releases/tag/v5.1.10) + +- Fix regression from previous release concerning 1024 byte blocksize operations. +- Do not store ACK's into duplicate list. + +## [v5.1.9](https://github.com/ARMmbed/mbed-coap/releases/tag/v5.1.9) + +- Code size optimizations. ## [v5.1.8](https://github.com/ARMmbed/mbed-coap/releases/tag/v5.1.8) diff --git a/connectivity/libraries/mbed-coap/Makefile.test b/connectivity/libraries/mbed-coap/Makefile.test index 37f8b5fbf3..bd27559310 100644 --- a/connectivity/libraries/mbed-coap/Makefile.test +++ b/connectivity/libraries/mbed-coap/Makefile.test @@ -15,6 +15,9 @@ TEST_MODULES = ./test_modules TEST_MODULE_MBED_TRACE = $(TEST_MODULES)/mbed-trace TEST_MODULE_NANOSTACK = $(TEST_MODULES)/nanostack-libservice TEST_MODULE_RANDLIB = $(TEST_MODULES)/mbed-client-randlib +TEST_MODULE_CCPUTEST_VERSION = "v3.8" +TEST_MODULE_CPPUTEST = $(TEST_MODULES)/cpputest +TEST_MODULE_CPPUTEST_LIB = $(TEST_MODULE_CPPUTEST)/lib/libCppUTest.a .PHONY: clone clone: @@ -33,13 +36,20 @@ clone: if [ ! -d $(TEST_MODULE_RANDLIB) ]; \ then git clone --depth 1 git@github.com:ARMmbed/mbed-client-randlib.git $(TEST_MODULE_RANDLIB); \ fi; + + if [ ! -d $(TEST_MODULE_CPPUTEST) ]; \ + then git clone --single-branch -b $(TEST_MODULE_CCPUTEST_VERSION) https://github.com/cpputest/cpputest.git $(TEST_MODULE_CPPUTEST); \ + fi; + .PHONY: test -test: $(TESTDIRS) +test: $(TEST_MODULE_CPPUTEST_LIB) $(TESTDIRS) @rm -rf ./lcov @rm -rf ./coverage + @rm -rf ./valgrind_logs @mkdir -p lcov @mkdir -p lcov/results @mkdir coverage + @mkdir valgrind_logs @find ./test -name '*.xml' | xargs cp -t ./lcov/results/ @rm -f lcov/index.xml @./xsl_script.sh @@ -47,16 +57,22 @@ test: $(TESTDIRS) @xsltproc -o lcov/testresults.html lcov/junit_xsl.xslt lcov/index.xml @rm -f lcov/junit_xsl.xslt @rm -f lcov/index.xml - @find ./ -name '*.gcno' | xargs cp --backup=numbered -t ./coverage/ - @find ./ -name '*.gcda' | xargs cp --backup=numbered -t ./coverage/ - @gcovr --object-directory ./coverage --exclude-unreachable-branches -e '.*/builds/.*' -e '.*/CppUTest/.*' -e '.*/mbed-client-libservice/.*' -e '.*/test/.*' -e '.*/stubs/.*' -e '.*/mbed-coap/.*' -x -o ./lcov/gcovr.xml - @lcov -d test/. -c -o $(COVERAGEFILE) + @gcovr -r . --filter='.*/sn_coap_builder.c' --filter='.*/sn_coap_protocol.c' --filter='.*/sn_coap_parser.c' --filter='.*/sn_coap_header_check.c' -x -o ./lcov/gcovr.xml + @lcov -q -d test/. -c -o $(COVERAGEFILE) @lcov -q -r $(COVERAGEFILE) "/usr*" -o $(COVERAGEFILE) - @lcov -q -r $(COVERAGEFILE) "/test*" -o $(COVERAGEFILE) - @lcov -q -r $(COVERAGEFILE) "/mbed-client-libservice*" -o $(COVERAGEFILE) + @lcov -q -r $(COVERAGEFILE) "*unittest*" -o $(COVERAGEFILE) + @lcov -q -r $(COVERAGEFILE) "*test_modules*" -o $(COVERAGEFILE) @genhtml -q $(COVERAGEFILE) --show-details --output-directory lcov/html + @find ./test -name \valgrind*.xml -print0 | xargs -0 cp --target-directory=./valgrind_logs/ @echo mbed-coap module unit tests built +$(TEST_MODULE_CPPUTEST_LIB): + cd $(TEST_MODULE_CPPUTEST) && \ + ./autogen.sh && \ + ./configure --disable-memory-leak-detection && \ + make && \ + cd $(CUR_DIR); \ + $(TESTDIRS): @make -C $(@:build-%=%) diff --git a/connectivity/libraries/mbed-coap/mbed-coap/sn_coap_header.h b/connectivity/libraries/mbed-coap/mbed-coap/sn_coap_header.h index 881770d849..d6964e2288 100644 --- a/connectivity/libraries/mbed-coap/mbed-coap/sn_coap_header.h +++ b/connectivity/libraries/mbed-coap/mbed-coap/sn_coap_header.h @@ -23,6 +23,9 @@ #ifndef SN_COAP_HEADER_H_ #define SN_COAP_HEADER_H_ +#include "sn_config.h" +#include "ns_types.h" + #ifdef __cplusplus extern "C" { #endif @@ -180,8 +183,8 @@ typedef enum sn_coap_status_ { */ typedef struct sn_coap_options_list_ { uint8_t etag_len; /**< 1-8 bytes. Repeatable */ - unsigned int use_size1:1; - unsigned int use_size2:1; + bool use_size1; + bool use_size2; uint16_t proxy_uri_len; /**< 1-1034 bytes. */ uint16_t uri_host_len; /**< 1-255 bytes. */ @@ -351,7 +354,10 @@ extern int16_t sn_coap_builder(uint8_t *dst_packet_data_ptr, const sn_coap_hdr_s * \return Return value is count of needed memory as bytes for build Packet data * Null if failed */ -extern uint16_t sn_coap_builder_calc_needed_packet_data_size(const sn_coap_hdr_s *src_coap_msg_ptr); +extern uint16_t (sn_coap_builder_calc_needed_packet_data_size)(const sn_coap_hdr_s *src_coap_msg_ptr); +#ifdef SN_COAP_CONSTANT_NEEDED_SIZE +#define sn_coap_builder_calc_needed_packet_data_size(m) (SN_COAP_CONSTANT_NEEDED_SIZE) +#endif /** * \fn int16_t sn_coap_builder_2(uint8_t *dst_packet_data_ptr, sn_coap_hdr_s *src_coap_msg_ptr, uint16_t blockwise_size) @@ -382,7 +388,10 @@ extern int16_t sn_coap_builder_2(uint8_t *dst_packet_data_ptr, const sn_coap_hdr * \return Return value is count of needed memory as bytes for build Packet data * Null if failed */ -extern uint16_t sn_coap_builder_calc_needed_packet_data_size_2(const sn_coap_hdr_s *src_coap_msg_ptr, uint16_t blockwise_payload_size); +extern uint16_t (sn_coap_builder_calc_needed_packet_data_size_2)(const sn_coap_hdr_s *src_coap_msg_ptr, uint16_t blockwise_payload_size); +#ifdef SN_COAP_CONSTANT_NEEDED_SIZE +#define sn_coap_builder_calc_needed_packet_data_size_2(m, p) (SN_COAP_CONSTANT_NEEDED_SIZE) +#endif /** * \fn sn_coap_hdr_s *sn_coap_build_response(struct coap_s *handle, sn_coap_hdr_s *coap_packet_ptr, uint8_t msg_code) diff --git a/connectivity/libraries/mbed-coap/mbed-coap/sn_config.h b/connectivity/libraries/mbed-coap/mbed-coap/sn_config.h index 4ad6b14edf..e46da064b9 100644 --- a/connectivity/libraries/mbed-coap/mbed-coap/sn_config.h +++ b/connectivity/libraries/mbed-coap/mbed-coap/sn_config.h @@ -68,6 +68,23 @@ #define SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE 0 /**< Must be 2^x and x is at least 4. Suitable values: 0, 16, 32, 64, 128, 256, 512 and 1024 */ #endif +/** + * \def SN_COAP_CONSTANT_NEEDED_SIZE + * \brief Avoid needed size calculations + * If this is defined, sn_coap_builder_calc_needed_packet_data_size always returns that value, + * saving a lot of calculation code, at the cost of outgoing TX buffers being oversized, and + * with danger of them being undersized. + * + * sn_coap_builder_payload_build does not have any size input to limit its output, so it is + * always wise for users to assert that it has not output more than the size returned by + * sn_coap_builder_calc_needed_packet_size, whether this option is defined or not. + */ +#ifdef MBED_CONF_MBED_CLIENT_SN_COAP_CONSTANT_NEEDED_SIZE +#define SN_COAP_CONSTANT_NEEDED_SIZE MBED_CONF_MBED_CLIENT_SN_COAP_CONSTANT_NEEDED_SIZE +#endif + +//#define SN_COAP_CONSTANT_NEEDED_SIZE 1024 + /** * \def SN_COAP_DISABLE_RESENDINGS * \brief Disables resending feature. Resending feature should not be needed diff --git a/connectivity/libraries/mbed-coap/run_unit_tests.sh b/connectivity/libraries/mbed-coap/run_unit_tests.sh deleted file mode 100755 index de190fe139..0000000000 --- a/connectivity/libraries/mbed-coap/run_unit_tests.sh +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/bash -# Copyright (c) 2015 ARM Limited. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 -# Licensed under the Apache License, Version 2.0 (the License); you may -# not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# * http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an AS IS BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. - -echo -echo "Build mbed-coap C unit tests" -echo - -make -f Makefile.test clone -make -f Makefile.test test -#make -f Makefile.test test clean diff --git a/connectivity/libraries/mbed-coap/run_unit_tests_with_valgrind.sh b/connectivity/libraries/mbed-coap/run_unit_tests_with_valgrind.sh deleted file mode 100755 index f02fd71470..0000000000 --- a/connectivity/libraries/mbed-coap/run_unit_tests_with_valgrind.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash -# Execute script with root path where to find binaries. -# For example ./run_unit_tests_with_valgrind.sh ./build/x86-linux-native-coverage/test/mbedclient/ - -input="binaries.txt" -valgrind_logs="valgrind_logs" -rm -rf $valgrind_logs -mkdir $valgrind_logs -find $1 -type f -executable -exec sh -c "file -i '{}' | grep -q 'x-executable; charset=binary'" \; -print > $input -while file= read -r binary -do - valgrind --track-origins=yes --xml=yes --xml-file="${valgrind_logs}/valgrind_$(basename $binary).xml" "$binary" - -done < "$input" diff --git a/connectivity/libraries/mbed-coap/source/include/sn_coap_header_internal.h b/connectivity/libraries/mbed-coap/source/include/sn_coap_header_internal.h index ef62e1742e..13197899ea 100644 --- a/connectivity/libraries/mbed-coap/source/include/sn_coap_header_internal.h +++ b/connectivity/libraries/mbed-coap/source/include/sn_coap_header_internal.h @@ -58,12 +58,12 @@ extern "C" { * \brief This structure is returned by sn_coap_exec() for sending */ typedef struct sn_nsdl_transmit_ { + uint8_t *packet_ptr; + uint16_t packet_len; sn_nsdl_addr_s dst_addr_ptr; sn_nsdl_capab_e protocol; - uint16_t packet_len; - uint8_t *packet_ptr; } sn_nsdl_transmit_s; /* * * * * * * * * * * * * * * * * * * * * * */ diff --git a/connectivity/libraries/mbed-coap/source/include/sn_coap_protocol_internal.h b/connectivity/libraries/mbed-coap/source/include/sn_coap_protocol_internal.h index f0cfffa5a8..c846abedb1 100644 --- a/connectivity/libraries/mbed-coap/source/include/sn_coap_protocol_internal.h +++ b/connectivity/libraries/mbed-coap/source/include/sn_coap_protocol_internal.h @@ -45,7 +45,7 @@ int8_t prepare_blockwise_message(struct coap_s *handle, struct sn_coap_hdr_ *coa /* Structure which is stored to Linked list for message sending purposes */ typedef struct coap_send_msg_ { - uint8_t resending_counter; /* Tells how many times message is still tried to resend */ + uint_fast8_t resending_counter; /* Tells how many times message is still tried to resend */ uint32_t resending_time; /* Tells next resending time */ sn_nsdl_transmit_s send_msg_ptr; @@ -86,25 +86,35 @@ typedef NS_LIST_HEAD(coap_blockwise_msg_s, link) coap_blockwise_msg_list_t; /* Structure which is stored to Linked list for blockwise messages receiving purposes */ typedef struct coap_blockwise_payload_ { - uint32_t timestamp; /* Tells when Payload is stored to Linked list */ - uint8_t addr_len; - uint8_t *addr_ptr; + uint8_t token_len; + bool use_size1; uint16_t port; + uint16_t payload_len; + uint8_t *addr_ptr; uint32_t block_number; uint8_t *token_ptr; - uint8_t token_len; - - uint16_t payload_len; uint8_t *payload_ptr; - unsigned int use_size1:1; - + uint32_t timestamp; /* Tells when Payload is stored to Linked list */ ns_list_link_t link; } coap_blockwise_payload_s; typedef NS_LIST_HEAD(coap_blockwise_payload_s, link) coap_blockwise_payload_list_t; struct coap_s { + uint8_t sn_coap_resending_queue_msgs; + uint8_t sn_coap_resending_count; + uint8_t sn_coap_resending_intervall; + uint8_t sn_coap_duplication_buffer_size; + uint8_t sn_coap_internal_block2_resp_handling; /* If this is set then coap itself sends a next GET request automatically */ + uint16_t sn_coap_block_data_size; + #if ENABLE_RESENDINGS + uint16_t count_resent_msgs; + #endif +#if SN_COAP_DUPLICATION_MAX_MSGS_COUNT + uint16_t count_duplication_msgs; +#endif + void *(*sn_coap_protocol_malloc)(uint16_t); void (*sn_coap_protocol_free)(void *); @@ -113,12 +123,10 @@ struct coap_s { #if ENABLE_RESENDINGS /* If Message resending is not used at all, this part of code will not be compiled */ coap_send_msg_list_t linked_list_resent_msgs; /* Active resending messages are stored to this Linked list */ - uint16_t count_resent_msgs; #endif #if SN_COAP_DUPLICATION_MAX_MSGS_COUNT /* If Message duplication detection is not used at all, this part of code will not be compiled */ coap_duplication_info_list_t linked_list_duplication_msgs; /* Messages for duplicated messages detection is stored to this Linked list */ - uint16_t count_duplication_msgs; #endif #if SN_COAP_BLOCKWISE_ENABLED || SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE /* If Message blockwise is not enabled, this part of code will not be compiled */ @@ -127,20 +135,14 @@ struct coap_s { #endif uint32_t system_time; /* System time seconds */ - uint16_t sn_coap_block_data_size; - uint8_t sn_coap_resending_queue_msgs; uint32_t sn_coap_resending_queue_bytes; - uint8_t sn_coap_resending_count; - uint8_t sn_coap_resending_intervall; - uint8_t sn_coap_duplication_buffer_size; - uint8_t sn_coap_internal_block2_resp_handling; /* If this is set then coap itself sends a next GET request automatically */ }; /* Utility function which performs a call to sn_coap_protocol_malloc() and memset's the result to zero. */ -void *sn_coap_protocol_calloc(struct coap_s *handle, uint16_t length); +void *sn_coap_protocol_calloc(struct coap_s *handle, uint_fast16_t length); /* Utility function which performs a call to sn_coap_protocol_malloc() and memcopy's the source to result buffer. */ -void *sn_coap_protocol_malloc_copy(struct coap_s *handle, const void *source, uint16_t length); +void *sn_coap_protocol_malloc_copy(struct coap_s *handle, const void *source, uint_fast16_t length); #ifdef __cplusplus } diff --git a/connectivity/libraries/mbed-coap/source/sn_coap_builder.c b/connectivity/libraries/mbed-coap/source/sn_coap_builder.c index 9282743643..e7aae6d7a2 100644 --- a/connectivity/libraries/mbed-coap/source/sn_coap_builder.c +++ b/connectivity/libraries/mbed-coap/source/sn_coap_builder.c @@ -37,17 +37,18 @@ #define TRACE_GROUP "coap" /* * * * LOCAL FUNCTION PROTOTYPES * * * */ -static int8_t sn_coap_builder_header_build(uint8_t **dst_packet_data_pptr, const sn_coap_hdr_s *src_coap_msg_ptr); -static int8_t sn_coap_builder_options_build(uint8_t **dst_packet_data_pptr, const sn_coap_hdr_s *src_coap_msg_ptr); -static uint16_t sn_coap_builder_options_calc_option_size(uint16_t query_len, const uint8_t *query_ptr, sn_coap_option_numbers_e option); -static int16_t sn_coap_builder_options_build_add_one_option(uint8_t **dst_packet_data_pptr, uint16_t option_len, const uint8_t *option_ptr, sn_coap_option_numbers_e option_number, uint16_t *previous_option_number); -static void sn_coap_builder_options_build_add_multiple_option(uint8_t **dst_packet_data_pptr, const uint8_t *src_pptr, uint16_t src_len_ptr, sn_coap_option_numbers_e option, uint16_t *previous_option_number); -static uint8_t sn_coap_builder_options_build_add_uint_option(uint8_t **dst_packet_data_pptr, uint32_t value, sn_coap_option_numbers_e option_number, uint16_t *previous_option_number); -static uint8_t sn_coap_builder_options_get_option_part_count(uint16_t query_len, const uint8_t *query_ptr, sn_coap_option_numbers_e option); -static uint16_t sn_coap_builder_options_get_option_part_length_from_whole_option_string(uint16_t query_len, const uint8_t *query_ptr, uint8_t query_index, sn_coap_option_numbers_e option); -static int16_t sn_coap_builder_options_get_option_part_position(uint16_t query_len, const uint8_t *query_ptr, uint8_t query_index, sn_coap_option_numbers_e option); -static void sn_coap_builder_payload_build(uint8_t **dst_packet_data_pptr, const sn_coap_hdr_s *src_coap_msg_ptr); -static uint8_t sn_coap_builder_options_calculate_jump_need(const sn_coap_hdr_s *src_coap_msg_ptr); +static uint8_t *sn_coap_builder_header_build(uint8_t *dst_packet_data_pptr, const sn_coap_hdr_s *src_coap_msg_ptr); +static uint8_t *sn_coap_builder_options_build(uint8_t *dst_packet_data_ptr, const sn_coap_hdr_s *src_coap_msg_ptr); +static uint_fast16_t sn_coap_builder_options_calc_option_size(uint16_t query_len, const uint8_t *query_ptr, sn_coap_option_numbers_e option); +static uint8_t *sn_coap_builder_options_build_add_one_option(uint8_t *dst_packet_data_ptr, uint_fast16_t option_len, const uint8_t *option_ptr, sn_coap_option_numbers_e option_number, uint16_t *previous_option_number); +static uint8_t *sn_coap_builder_options_build_add_multiple_option(uint8_t *dst_packet_data_pptr, const uint8_t *src_pptr, uint_fast16_t src_len, sn_coap_option_numbers_e option, uint16_t *previous_option_number); +static uint_fast8_t sn_coap_builder_options_calc_uint_option_size(uint32_t option_value); +static uint8_t *sn_coap_builder_options_build_add_uint_option(uint8_t *dst_packet_data_ptr, uint32_t value, sn_coap_option_numbers_e option_number, uint16_t *previous_option_number); +static uint_fast8_t sn_coap_builder_options_get_option_part_count(uint_fast16_t query_len, const uint8_t *query_ptr, sn_coap_option_numbers_e option); +static uint_fast16_t sn_coap_builder_options_get_option_part_length_from_whole_option_string(uint_fast16_t query_len, const uint8_t *query_ptr, uint_fast8_t query_index, sn_coap_option_numbers_e option); +static int_fast16_t sn_coap_builder_options_get_option_part_position(uint_fast16_t query_len, const uint8_t *query_ptr, uint_fast8_t query_index, sn_coap_option_numbers_e option); +static uint8_t *sn_coap_builder_payload_build(uint8_t *dst_packet_data_ptr, const sn_coap_hdr_s *src_coap_msg_ptr); +static uint_fast8_t sn_coap_builder_options_calculate_jump_need(const sn_coap_hdr_s *src_coap_msg_ptr); sn_coap_hdr_s *sn_coap_build_response(struct coap_s *handle, const sn_coap_hdr_s *coap_packet_ptr, uint8_t msg_code) { @@ -101,7 +102,7 @@ int16_t sn_coap_builder(uint8_t *dst_packet_data_ptr, const sn_coap_hdr_s *src_c return sn_coap_builder_2(dst_packet_data_ptr, src_coap_msg_ptr, SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE); } -int16_t sn_coap_builder_2(uint8_t *dst_packet_data_ptr, const sn_coap_hdr_s *src_coap_msg_ptr, uint16_t blockwise_payload_size) +int16_t sn_coap_builder_2(uint8_t * restrict dst_packet_data_ptr, const sn_coap_hdr_s * restrict src_coap_msg_ptr, uint16_t blockwise_payload_size) { uint8_t *base_packet_data_ptr; @@ -110,23 +111,22 @@ int16_t sn_coap_builder_2(uint8_t *dst_packet_data_ptr, const sn_coap_hdr_s *src return -2; } - /* Initialize given Packet data memory area with zero values */ + /* This serves as a pre-validity check for various src_coap_msg_ptr fields */ + /* (as long as SN_COAP_CONSTANT_NEEDED_SIZE is not set) */ uint16_t dst_byte_count_to_be_built = sn_coap_builder_calc_needed_packet_data_size_2(src_coap_msg_ptr, blockwise_payload_size); if (!dst_byte_count_to_be_built) { tr_error("sn_coap_builder_2 - failed to allocate message!"); return -1; } - // XXX: this should not be needed anymore but I have no courage to remove it yet. - memset(dst_packet_data_ptr, 0, dst_byte_count_to_be_built); - /* * * * Store base (= original) destination Packet data pointer for later usage * * * */ base_packet_data_ptr = dst_packet_data_ptr; /* * * * * * * * * * * * * * * * * * */ /* * * * Header part building * * * */ /* * * * * * * * * * * * * * * * * * */ - if (sn_coap_builder_header_build(&dst_packet_data_ptr, src_coap_msg_ptr) != 0) { + dst_packet_data_ptr = sn_coap_builder_header_build(dst_packet_data_ptr, src_coap_msg_ptr); + if (!dst_packet_data_ptr) { /* Header building failed */ tr_error("sn_coap_builder_2 - header building failed!"); return -1; @@ -137,23 +137,34 @@ int16_t sn_coap_builder_2(uint8_t *dst_packet_data_ptr, const sn_coap_hdr_s *src /* * * * * * * * * * * * * * * * * * */ /* * * * Options part building * * * */ /* * * * * * * * * * * * * * * * * * */ - sn_coap_builder_options_build(&dst_packet_data_ptr, src_coap_msg_ptr); + dst_packet_data_ptr = sn_coap_builder_options_build(dst_packet_data_ptr, src_coap_msg_ptr); /* * * * * * * * * * * * * * * * * * */ /* * * * Payload part building * * * */ /* * * * * * * * * * * * * * * * * * */ - sn_coap_builder_payload_build(&dst_packet_data_ptr, src_coap_msg_ptr); + dst_packet_data_ptr = sn_coap_builder_payload_build(dst_packet_data_ptr, src_coap_msg_ptr); } + + /* Shout as much as we can about overflow - if we exceed this, may have overrun user's buffer */ + if (dst_packet_data_ptr - base_packet_data_ptr > dst_byte_count_to_be_built) { + tr_error("sn_coap_builder_2 - overflowed expected size!"); + return -1; + } + /* * * * Return built Packet data length * * * */ return (dst_packet_data_ptr - base_packet_data_ptr); } -uint16_t sn_coap_builder_calc_needed_packet_data_size(const sn_coap_hdr_s *src_coap_msg_ptr) + +uint16_t (sn_coap_builder_calc_needed_packet_data_size)(const sn_coap_hdr_s *src_coap_msg_ptr) { return sn_coap_builder_calc_needed_packet_data_size_2(src_coap_msg_ptr, SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE); } -uint16_t sn_coap_builder_calc_needed_packet_data_size_2(const sn_coap_hdr_s *src_coap_msg_ptr, uint16_t blockwise_payload_size) +uint16_t (sn_coap_builder_calc_needed_packet_data_size_2)(const sn_coap_hdr_s *src_coap_msg_ptr, uint16_t blockwise_payload_size) { +#ifdef SN_COAP_CONSTANT_NEEDED_SIZE + return SN_COAP_CONSTANT_NEEDED_SIZE; +#else (void)blockwise_payload_size; uint_fast32_t returned_byte_count = 0; @@ -169,7 +180,7 @@ uint16_t sn_coap_builder_calc_needed_packet_data_size_2(const sn_coap_hdr_s *src /* If else than Reset message because Reset message must be empty */ if (src_coap_msg_ptr->msg_type != COAP_MSG_TYPE_RESET) { - uint16_t repeatable_option_size = 0; + uint_fast16_t repeatable_option_size = 0; /* TOKEN - Length is 1-8 bytes */ if (src_coap_msg_ptr->token_ptr != NULL) { if (src_coap_msg_ptr->token_len > 8 || src_coap_msg_ptr->token_len < 1) { /* Check that option is not longer than defined */ @@ -190,19 +201,18 @@ uint16_t sn_coap_builder_calc_needed_packet_data_size_2(const sn_coap_hdr_s *src } } - uint16_t tempInt = 0; /* CONTENT FORMAT - An integer option, up to 2 bytes */ if (src_coap_msg_ptr->content_format != COAP_CT_NONE) { if ((uint32_t) src_coap_msg_ptr->content_format > 0xffff) { tr_error("sn_coap_builder_calc_needed_packet_data_size_2 - content format too large!"); return 0; } - returned_byte_count += sn_coap_builder_options_build_add_uint_option(NULL, src_coap_msg_ptr->content_format, COAP_OPTION_CONTENT_FORMAT, &tempInt); + returned_byte_count += sn_coap_builder_options_calc_uint_option_size(src_coap_msg_ptr->content_format); } /* If options list pointer exists */ if (src_coap_msg_ptr->options_list_ptr != NULL) { - const sn_coap_options_list_s *src_options_list_ptr = src_coap_msg_ptr->options_list_ptr; + const sn_coap_options_list_s * restrict src_options_list_ptr = src_coap_msg_ptr->options_list_ptr; /* ACCEPT - An integer option, up to 2 bytes */ if (src_options_list_ptr->accept != COAP_CT_NONE) { @@ -210,11 +220,11 @@ uint16_t sn_coap_builder_calc_needed_packet_data_size_2(const sn_coap_hdr_s *src tr_error("sn_coap_builder_calc_needed_packet_data_size_2 - accept too large!"); return 0; } - returned_byte_count += sn_coap_builder_options_build_add_uint_option(NULL, src_options_list_ptr->accept, COAP_OPTION_ACCEPT, &tempInt); + returned_byte_count += sn_coap_builder_options_calc_uint_option_size(src_options_list_ptr->accept); } /* MAX AGE - An integer option, omitted for default. Up to 4 bytes */ if (src_options_list_ptr->max_age != COAP_OPTION_MAX_AGE_DEFAULT) { - returned_byte_count += sn_coap_builder_options_build_add_uint_option(NULL, src_options_list_ptr->max_age, COAP_OPTION_MAX_AGE, &tempInt); + returned_byte_count += sn_coap_builder_options_calc_uint_option_size(src_options_list_ptr->max_age); } /* PROXY URI - Length of this option is 1-1034 bytes */ if (src_options_list_ptr->proxy_uri_ptr != NULL) { @@ -282,7 +292,7 @@ uint16_t sn_coap_builder_calc_needed_packet_data_size_2(const sn_coap_hdr_s *src tr_error("sn_coap_builder_calc_needed_packet_data_size_2 - uri port too large!"); return 0; } - returned_byte_count += sn_coap_builder_options_build_add_uint_option(NULL, src_options_list_ptr->uri_port, COAP_OPTION_URI_PORT, &tempInt); + returned_byte_count += sn_coap_builder_options_calc_uint_option_size(src_options_list_ptr->uri_port); } /* lOCATION QUERY - Repeatable option. Length of this option is 0-255 bytes */ if (src_options_list_ptr->location_query_ptr != NULL) { @@ -300,7 +310,7 @@ uint16_t sn_coap_builder_calc_needed_packet_data_size_2(const sn_coap_hdr_s *src if ((uint32_t) src_options_list_ptr->observe > 0xffffff) { return 0; } - returned_byte_count += sn_coap_builder_options_build_add_uint_option(NULL, src_options_list_ptr->observe, COAP_OPTION_OBSERVE, &tempInt); + returned_byte_count += sn_coap_builder_options_calc_uint_option_size(src_options_list_ptr->observe); } /* URI QUERY - Repeatable option. Length of this option is 1-255 */ if (src_options_list_ptr->uri_query_ptr != NULL) { @@ -320,11 +330,11 @@ uint16_t sn_coap_builder_calc_needed_packet_data_size_2(const sn_coap_hdr_s *src tr_error("sn_coap_builder_calc_needed_packet_data_size_2 - block1 too large!"); return 0; } - returned_byte_count += sn_coap_builder_options_build_add_uint_option(NULL, src_options_list_ptr->block1, COAP_OPTION_BLOCK1, &tempInt); + returned_byte_count += sn_coap_builder_options_calc_uint_option_size(src_options_list_ptr->block1); } /* SIZE1 - Length of this option is 0-4 bytes */ if (src_options_list_ptr->use_size1) { - returned_byte_count += sn_coap_builder_options_build_add_uint_option(NULL, src_options_list_ptr->size1, COAP_OPTION_SIZE1, &tempInt); + returned_byte_count += sn_coap_builder_options_calc_uint_option_size(src_options_list_ptr->size1); } /* BLOCK 2 - An integer option, up to 3 bytes */ if (src_options_list_ptr->block2 != COAP_OPTION_BLOCK_NONE) { @@ -332,11 +342,11 @@ uint16_t sn_coap_builder_calc_needed_packet_data_size_2(const sn_coap_hdr_s *src tr_error("sn_coap_builder_calc_needed_packet_data_size_2 - block2 too large!"); return 0; } - returned_byte_count += sn_coap_builder_options_build_add_uint_option(NULL, src_options_list_ptr->block2, COAP_OPTION_BLOCK2, &tempInt); + returned_byte_count += sn_coap_builder_options_calc_uint_option_size(src_options_list_ptr->block2); } /* SIZE2 - Length of this option is 0-4 bytes */ if (src_coap_msg_ptr->options_list_ptr->use_size2) { - returned_byte_count += sn_coap_builder_options_build_add_uint_option(NULL, src_options_list_ptr->size2, COAP_OPTION_SIZE2, &tempInt); + returned_byte_count += sn_coap_builder_options_calc_uint_option_size(src_options_list_ptr->size2); } } #if SN_COAP_BLOCKWISE_ENABLED || SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE @@ -360,6 +370,7 @@ uint16_t sn_coap_builder_calc_needed_packet_data_size_2(const sn_coap_hdr_s *src return 0; } return (uint16_t)returned_byte_count; +#endif } /** @@ -374,10 +385,10 @@ uint16_t sn_coap_builder_calc_needed_packet_data_size_2(const sn_coap_hdr_s *src * \return Returns bytes needed for jumping */ -static uint8_t sn_coap_builder_options_calculate_jump_need(const sn_coap_hdr_s *src_coap_msg_ptr) +static uint_fast8_t sn_coap_builder_options_calculate_jump_need(const sn_coap_hdr_s *src_coap_msg_ptr) { uint8_t previous_option_number = 0; - uint8_t needed_space = 0; + uint_fast8_t needed_space = 0; const sn_coap_options_list_s* options_list_ptr = src_coap_msg_ptr->options_list_ptr; @@ -489,54 +500,52 @@ static uint8_t sn_coap_builder_options_calculate_jump_need(const sn_coap_hdr_s * } /** - * \fn static int8_t sn_coap_builder_header_build(uint8_t **dst_packet_data_pptr, sn_coap_hdr_s *src_coap_msg_ptr) + * \fn static int8_t sn_coap_builder_header_build(uint8_t *dst_packet_data_ptr, sn_coap_hdr_s *src_coap_msg_ptr) * * \brief Builds Header part of Packet data * - * \param **dst_packet_data_pptr is destination for built Packet data + * \param *dst_packet_data_ptr is destination for built Packet data * * \param *src_coap_msg_ptr is source for building Packet data * * \return Return value is 0 in ok case and -1 in failure case **************************************************************************** */ -static int8_t sn_coap_builder_header_build(uint8_t **dst_packet_data_pptr, const sn_coap_hdr_s *src_coap_msg_ptr) +static uint8_t *sn_coap_builder_header_build(uint8_t * restrict dst_packet_data_ptr, const sn_coap_hdr_s * restrict src_coap_msg_ptr) { /* * * * Check validity of Header values * * * */ if (sn_coap_header_validity_check(src_coap_msg_ptr, COAP_VERSION) != 0) { tr_error("sn_coap_builder_header_build - header build failed!"); - return -1; + return NULL; } - uint8_t* dest_packet = *dst_packet_data_pptr; - /* Set CoAP Version, Message type and Token length */ - dest_packet[0] = COAP_VERSION | src_coap_msg_ptr->msg_type | src_coap_msg_ptr->token_len; + dst_packet_data_ptr[0] = COAP_VERSION | src_coap_msg_ptr->msg_type | src_coap_msg_ptr->token_len; /* * * Add Message code * * */ - dest_packet[1] = src_coap_msg_ptr->msg_code; + dst_packet_data_ptr[1] = src_coap_msg_ptr->msg_code; /* * * Add Message ID * * */ - dest_packet[2] = (uint8_t)(src_coap_msg_ptr->msg_id >> COAP_HEADER_MSG_ID_MSB_SHIFT); /* MSB part */ - dest_packet[3] = (uint8_t)src_coap_msg_ptr->msg_id; /* LSB part */ + dst_packet_data_ptr[2] = (uint8_t)(src_coap_msg_ptr->msg_id >> COAP_HEADER_MSG_ID_MSB_SHIFT); /* MSB part */ + dst_packet_data_ptr[3] = (uint8_t)src_coap_msg_ptr->msg_id; /* LSB part */ - *dst_packet_data_pptr = dest_packet + 4; + dst_packet_data_ptr += 4; /* Success */ - return 0; + return dst_packet_data_ptr; } /** - * \fn static int8_t sn_coap_builder_options_build(uint8_t **dst_packet_data_pptr, sn_coap_hdr_s *src_coap_msg_ptr) + * \fn static int8_t sn_coap_builder_options_build(uint8_t *dst_packet_data_ptr, sn_coap_hdr_s *src_coap_msg_ptr) * * \brief Builds Options part of Packet data * - * \param **dst_packet_data_pptr is destination for built Packet data + * \param *dst_packet_data_ptr is destination for built Packet data * * \param *src_coap_msg_ptr is source for building Packet data * - * \return Return value is 0 in every case + * \return Returns updated output pointer */ -static int8_t sn_coap_builder_options_build(uint8_t **dst_packet_data_pptr, const sn_coap_hdr_s *src_coap_msg_ptr) +static uint8_t *sn_coap_builder_options_build(uint8_t * restrict dst_packet_data_ptr, const sn_coap_hdr_s * restrict src_coap_msg_ptr) { /* * * * Check if Options are used at all * * * */ if (src_coap_msg_ptr->uri_path_ptr == NULL && src_coap_msg_ptr->token_ptr == NULL && @@ -545,14 +554,14 @@ static int8_t sn_coap_builder_options_build(uint8_t **dst_packet_data_pptr, cons if (src_coap_msg_ptr->msg_type != COAP_MSG_TYPE_CONFIRMABLE) { tr_error("sn_coap_builder_options_build - options not used!"); } - return 0; + return dst_packet_data_ptr; } /* * * * First add Token option * * * */ if (src_coap_msg_ptr->token_len && src_coap_msg_ptr->token_ptr) { - memcpy(*dst_packet_data_pptr, src_coap_msg_ptr->token_ptr, src_coap_msg_ptr->token_len); + memcpy(dst_packet_data_ptr, src_coap_msg_ptr->token_ptr, src_coap_msg_ptr->token_len); } - (*dst_packet_data_pptr) += src_coap_msg_ptr->token_len; + dst_packet_data_ptr += src_coap_msg_ptr->token_len; /* Then build rest of the options */ @@ -561,105 +570,105 @@ static int8_t sn_coap_builder_options_build(uint8_t **dst_packet_data_pptr, cons //missing: COAP_OPTION_IF_MATCH, COAP_OPTION_IF_NONE_MATCH, COAP_OPTION_SIZE - const sn_coap_options_list_s *src_options_list_ptr = src_coap_msg_ptr->options_list_ptr; + const sn_coap_options_list_s * restrict src_options_list_ptr = src_coap_msg_ptr->options_list_ptr; /* Check if less used options are used at all */ if (src_options_list_ptr != NULL) { /* * * * Build Uri-Host option * * * */ - sn_coap_builder_options_build_add_one_option(dst_packet_data_pptr, src_options_list_ptr->uri_host_len, + dst_packet_data_ptr = sn_coap_builder_options_build_add_one_option(dst_packet_data_ptr, src_options_list_ptr->uri_host_len, src_options_list_ptr->uri_host_ptr, COAP_OPTION_URI_HOST, &previous_option_number); /* * * * Build ETag option * * * */ - sn_coap_builder_options_build_add_multiple_option(dst_packet_data_pptr, src_options_list_ptr->etag_ptr, + dst_packet_data_ptr = sn_coap_builder_options_build_add_multiple_option(dst_packet_data_ptr, src_options_list_ptr->etag_ptr, src_options_list_ptr->etag_len, COAP_OPTION_ETAG, &previous_option_number); /* * * * Build Observe option * * * * */ if (src_options_list_ptr->observe != COAP_OBSERVE_NONE) { - sn_coap_builder_options_build_add_uint_option(dst_packet_data_pptr, src_options_list_ptr->observe, + dst_packet_data_ptr = sn_coap_builder_options_build_add_uint_option(dst_packet_data_ptr, src_options_list_ptr->observe, COAP_OPTION_OBSERVE, &previous_option_number); } /* * * * Build Uri-Port option * * * */ if (src_options_list_ptr->uri_port != COAP_OPTION_URI_PORT_NONE) { - sn_coap_builder_options_build_add_uint_option(dst_packet_data_pptr, src_options_list_ptr->uri_port, + dst_packet_data_ptr = sn_coap_builder_options_build_add_uint_option(dst_packet_data_ptr, src_options_list_ptr->uri_port, COAP_OPTION_URI_PORT, &previous_option_number); } /* * * * Build Location-Path option * * * */ - sn_coap_builder_options_build_add_multiple_option(dst_packet_data_pptr, src_options_list_ptr->location_path_ptr, + dst_packet_data_ptr = sn_coap_builder_options_build_add_multiple_option(dst_packet_data_ptr, src_options_list_ptr->location_path_ptr, src_options_list_ptr->location_path_len, COAP_OPTION_LOCATION_PATH, &previous_option_number); } /* * * * Build Uri-Path option * * * */ - sn_coap_builder_options_build_add_multiple_option(dst_packet_data_pptr, src_coap_msg_ptr->uri_path_ptr, + dst_packet_data_ptr = sn_coap_builder_options_build_add_multiple_option(dst_packet_data_ptr, src_coap_msg_ptr->uri_path_ptr, src_coap_msg_ptr->uri_path_len, COAP_OPTION_URI_PATH, &previous_option_number); /* * * * Build Content-Type option * * * */ if (src_coap_msg_ptr->content_format != COAP_CT_NONE) { - sn_coap_builder_options_build_add_uint_option(dst_packet_data_pptr, src_coap_msg_ptr->content_format, + dst_packet_data_ptr = sn_coap_builder_options_build_add_uint_option(dst_packet_data_ptr, src_coap_msg_ptr->content_format, COAP_OPTION_CONTENT_FORMAT, &previous_option_number); } if (src_options_list_ptr != NULL) { /* * * * Build Max-Age option * * * */ if (src_options_list_ptr->max_age != COAP_OPTION_MAX_AGE_DEFAULT) { - sn_coap_builder_options_build_add_uint_option(dst_packet_data_pptr, src_options_list_ptr->max_age, + dst_packet_data_ptr = sn_coap_builder_options_build_add_uint_option(dst_packet_data_ptr, src_options_list_ptr->max_age, COAP_OPTION_MAX_AGE, &previous_option_number); } /* * * * Build Uri-Query option * * * * */ - sn_coap_builder_options_build_add_multiple_option(dst_packet_data_pptr, src_options_list_ptr->uri_query_ptr, + dst_packet_data_ptr = sn_coap_builder_options_build_add_multiple_option(dst_packet_data_ptr, src_options_list_ptr->uri_query_ptr, src_options_list_ptr->uri_query_len, COAP_OPTION_URI_QUERY, &previous_option_number); /* * * * Build Accept option * * * * */ if (src_coap_msg_ptr->options_list_ptr->accept != COAP_CT_NONE) { - sn_coap_builder_options_build_add_uint_option(dst_packet_data_pptr, src_options_list_ptr->accept, + dst_packet_data_ptr = sn_coap_builder_options_build_add_uint_option(dst_packet_data_ptr, src_options_list_ptr->accept, COAP_OPTION_ACCEPT, &previous_option_number); } /* * * * Build Location-Query option * * * */ - sn_coap_builder_options_build_add_multiple_option(dst_packet_data_pptr, src_options_list_ptr->location_query_ptr, + dst_packet_data_ptr = sn_coap_builder_options_build_add_multiple_option(dst_packet_data_ptr, src_options_list_ptr->location_query_ptr, src_options_list_ptr->location_query_len, COAP_OPTION_LOCATION_QUERY, &previous_option_number); /* * * * Build Block2 option * * * * */ if (src_coap_msg_ptr->options_list_ptr->block2 != COAP_OPTION_BLOCK_NONE) { - sn_coap_builder_options_build_add_uint_option(dst_packet_data_pptr, src_options_list_ptr->block2, + dst_packet_data_ptr = sn_coap_builder_options_build_add_uint_option(dst_packet_data_ptr, src_options_list_ptr->block2, COAP_OPTION_BLOCK2, &previous_option_number); } /* * * * Build Block1 option * * * * */ if (src_coap_msg_ptr->options_list_ptr->block1 != COAP_OPTION_BLOCK_NONE) { - sn_coap_builder_options_build_add_uint_option(dst_packet_data_pptr, src_options_list_ptr->block1, + dst_packet_data_ptr = sn_coap_builder_options_build_add_uint_option(dst_packet_data_ptr, src_options_list_ptr->block1, COAP_OPTION_BLOCK1, &previous_option_number); } /* * * * Build Size2 option * * * */ if (src_coap_msg_ptr->options_list_ptr->use_size2) { - sn_coap_builder_options_build_add_uint_option(dst_packet_data_pptr, src_options_list_ptr->size2, + dst_packet_data_ptr = sn_coap_builder_options_build_add_uint_option(dst_packet_data_ptr, src_options_list_ptr->size2, COAP_OPTION_SIZE2, &previous_option_number); } /* * * * Build Proxy-Uri option * * * */ - sn_coap_builder_options_build_add_one_option(dst_packet_data_pptr, src_options_list_ptr->proxy_uri_len, + dst_packet_data_ptr = sn_coap_builder_options_build_add_one_option(dst_packet_data_ptr, src_options_list_ptr->proxy_uri_len, src_options_list_ptr->proxy_uri_ptr, COAP_OPTION_PROXY_URI, &previous_option_number); /* * * * Build Size1 option * * * */ if (src_options_list_ptr->use_size1) { - sn_coap_builder_options_build_add_uint_option(dst_packet_data_pptr, src_options_list_ptr->size1, + dst_packet_data_ptr = sn_coap_builder_options_build_add_uint_option(dst_packet_data_ptr, src_options_list_ptr->size1, COAP_OPTION_SIZE1, &previous_option_number); } } /* Success */ - return 0; + return dst_packet_data_ptr; } /** - * \fn static int16_t sn_coap_builder_options_build_add_one_option(uint8_t **dst_packet_data_pptr, uint16_t option_value_len, uint8_t *option_value_ptr, sn_coap_option_numbers_e option_number) + * \fn static uint8_t *sn_coap_builder_options_build_add_one_option(uint8_t *dst_packet_data_ptr, uint16_t option_value_len, uint8_t *option_value_ptr, sn_coap_option_numbers_e option_number) * * \brief Adds Options part of Packet data * - * \param **dst_packet_data_pptr is destination for built Packet data + * \param *dst_packet_data_ptr is destination for built Packet data * * \param option_value_len is Option value length to be added * @@ -667,20 +676,20 @@ static int8_t sn_coap_builder_options_build(uint8_t **dst_packet_data_pptr, cons * * \param option_number is Option number to be added * - * \return Return value is 0 if option was not added, 1 if added + * \return Advanced destination */ -static int16_t sn_coap_builder_options_build_add_one_option(uint8_t **dst_packet_data_pptr, uint16_t option_len, - const uint8_t *option_ptr, sn_coap_option_numbers_e option_number, uint16_t *previous_option_number) +static uint8_t *sn_coap_builder_options_build_add_one_option(uint8_t * restrict dst_packet_data_ptr, uint_fast16_t option_len, + const uint8_t * restrict option_ptr, sn_coap_option_numbers_e option_number, uint16_t * restrict previous_option_number) { /* Check if there is option at all */ if (option_ptr != NULL) { - uint16_t option_delta; + uint_fast16_t option_delta; option_delta = (option_number - *previous_option_number); /* * * Build option header * * */ - uint8_t first_byte; + uint_fast8_t first_byte; /* First option length without extended part */ if (option_len <= 12) { @@ -695,101 +704,97 @@ static int16_t sn_coap_builder_options_build_add_one_option(uint8_t **dst_packet first_byte = 0x0E; } - uint8_t *dest_packet = *dst_packet_data_pptr; - /* Then option delta with extensions, and move pointer */ if (option_delta <= 12) { - dest_packet[0] = first_byte + (option_delta << 4); - dest_packet += 1; + *dst_packet_data_ptr++ = first_byte + (option_delta << 4); } else if (option_delta > 12 && option_delta < 269) { - dest_packet[0] = first_byte + 0xD0; + *dst_packet_data_ptr++ = first_byte + 0xD0; option_delta -= 13; - dest_packet[1] = (uint8_t)option_delta; - dest_packet += 2; + *dst_packet_data_ptr++ = (uint8_t)option_delta; } //This is currently dead code (but possibly needed in future) else /*if (option_delta >= 269)*/ { - dest_packet[0] = first_byte + 0xE0; + *dst_packet_data_ptr++ = first_byte + 0xE0; option_delta -= 269; - dest_packet[1] = (option_delta >> 8); - dest_packet[2] = (uint8_t)option_delta; - dest_packet += 3; + *dst_packet_data_ptr++ = (option_delta >> 8); + *dst_packet_data_ptr++ = (uint8_t)option_delta; } /* Now option length extensions, if needed */ if (option_len > 12 && option_len < 269) { - dest_packet[0] = (uint8_t)(option_len - 13); - dest_packet += 1; + *dst_packet_data_ptr++ = (uint8_t)(option_len - 13); } else if (option_len >= 269) { - dest_packet[0] = ((option_len - 269) >> 8); - dest_packet[1] = (uint8_t)(option_len - 269); - dest_packet += 2; + *dst_packet_data_ptr++ = ((option_len - 269) >> 8); + *dst_packet_data_ptr++ = (uint8_t)(option_len - 269); } *previous_option_number = option_number; /* Write Option value */ - memcpy(dest_packet, option_ptr, option_len); + memcpy(dst_packet_data_ptr, option_ptr, option_len); /* Increase destination Packet data pointer */ - dest_packet += option_len; - - *dst_packet_data_pptr = dest_packet; - - return 1; + dst_packet_data_ptr += option_len; } /* Success */ - return 0; + return dst_packet_data_ptr; +} + +static uint_fast8_t sn_coap_builder_options_calc_uint_option_size(uint32_t option_value) +{ + // Calculation assumes option type/len is always 1 byte. + // Length certainly fits, and any extra for option type is accounted for + // separately by sn_coap_builder_options_calculate_jump_need. + uint_fast8_t len = 1; + + while (option_value != 0) { + len++; + option_value >>= 8; + } + + return len; } /** * \brief Constructs a uint Options part of Packet data * - * \param **dst_packet_data_pptr is destination for built Packet data; NULL + * \param *dst_packet_data_pptr is destination for built Packet data; NULL * to compute size only. * * \param option_value is Option value to be added * * \param option_number is Option number to be added * - * \return Return value is total option size, or -1 in write failure case + * \return Updated destination pointer */ -static uint8_t sn_coap_builder_options_build_add_uint_option(uint8_t **dst_packet_data_pptr, uint32_t option_value, sn_coap_option_numbers_e option_number, uint16_t *previous_option_number) +static uint8_t *sn_coap_builder_options_build_add_uint_option(uint8_t * restrict dst_packet_data_ptr, uint32_t option_value, sn_coap_option_numbers_e option_number, uint16_t * restrict previous_option_number) { uint8_t payload[4]; - uint8_t len = 0; + uint_fast8_t len = 0; /* Construct the variable-length payload representing the value */ - for (uint8_t i = 0; i < 4; i++) { + for (uint_fast8_t i = 0; i < 4; i++) { if (len > 0 || (option_value & 0xff000000)) { payload[len++] = option_value >> 24; } option_value <<= 8; } - /* If output pointer isn't NULL, write it out */ - if (dst_packet_data_pptr) { - // No need to check & handle return value, as the function returns failure only if the option pointer is zero - // and it is pointing to a local variable here. - sn_coap_builder_options_build_add_one_option(dst_packet_data_pptr, len, payload, option_number, previous_option_number); - } - - /* Return the total option size */ - return 1 + len; + return sn_coap_builder_options_build_add_one_option(dst_packet_data_ptr, len, payload, option_number, previous_option_number); } /** - * \fn static int16_t sn_coap_builder_options_build_add_multiple_option(uint8_t **dst_packet_data_pptr, uint8_t **src_pptr, uint16_t *src_len_ptr, sn_coap_option_numbers_e option) + * \fn static int16_t sn_coap_builder_options_build_add_multiple_option(uint8_t *dst_packet_data_pptr, uint8_t **src_pptr, uint16_t *src_len_ptr, sn_coap_option_numbers_e option) * * \brief Builds Option Uri-Query from given CoAP Header structure to Packet data * - * \param **dst_packet_data_pptr is destination for built Packet data + * \param *dst_packet_data_ptr is destination for built Packet data * * \param uint8_t **src_ptr * @@ -797,17 +802,17 @@ static uint8_t sn_coap_builder_options_build_add_uint_option(uint8_t **dst_packe * * \paramsn_coap_option_numbers_e option option to be added * - * \return Return value is 0 always + * \return Returns updated output pointer */ -static void sn_coap_builder_options_build_add_multiple_option(uint8_t **dst_packet_data_pptr, const uint8_t *src_pptr, uint16_t src_len, sn_coap_option_numbers_e option, uint16_t *previous_option_number) +static uint8_t *sn_coap_builder_options_build_add_multiple_option(uint8_t * restrict dst_packet_data_ptr, const uint8_t * restrict src_pptr, uint_fast16_t src_len, sn_coap_option_numbers_e option, uint16_t * restrict previous_option_number) { /* Check if there is option at all */ if (src_pptr != NULL) { - const uint8_t *query_ptr = src_pptr; - uint8_t query_part_count = 0; - uint16_t query_len = src_len; - uint8_t i = 0; - uint16_t query_part_offset = 0; + const uint8_t * restrict query_ptr = src_pptr; + uint_fast8_t query_part_count = 0; + uint_fast16_t query_len = src_len; + uint_fast8_t i = 0; + uint_fast16_t query_part_offset = 0; /* Get query part count */ query_part_count = sn_coap_builder_options_get_option_part_count(query_len, query_ptr, option); @@ -815,16 +820,17 @@ static void sn_coap_builder_options_build_add_multiple_option(uint8_t **dst_pack /* * * * Options by adding all parts to option * * * */ for (i = 0; i < query_part_count; i++) { /* Get length of query part */ - uint16_t one_query_part_len = sn_coap_builder_options_get_option_part_length_from_whole_option_string(query_len, query_ptr, i, option); + uint_fast16_t one_query_part_len = sn_coap_builder_options_get_option_part_length_from_whole_option_string(query_len, query_ptr, i, option); /* Get position of query part */ query_part_offset = sn_coap_builder_options_get_option_part_position(query_len, query_ptr, i, option); /* Add Uri-query's one part to Options */ - sn_coap_builder_options_build_add_one_option(dst_packet_data_pptr, one_query_part_len, src_pptr + query_part_offset, option, previous_option_number); + dst_packet_data_ptr = sn_coap_builder_options_build_add_one_option(dst_packet_data_ptr, one_query_part_len, src_pptr + query_part_offset, option, previous_option_number); } } /* Success */ + return dst_packet_data_ptr; } @@ -839,11 +845,11 @@ static void sn_coap_builder_options_build_add_multiple_option(uint8_t **dst_pack * * \return Return value is count of needed memory as bytes for Uri-query option */ -static uint16_t sn_coap_builder_options_calc_option_size(uint16_t query_len, const uint8_t *query_ptr, sn_coap_option_numbers_e option) +static uint_fast16_t sn_coap_builder_options_calc_option_size(uint16_t query_len, const uint8_t *query_ptr, sn_coap_option_numbers_e option) { - uint8_t query_part_count = sn_coap_builder_options_get_option_part_count(query_len, query_ptr, option); - uint8_t i = 0; - uint16_t ret_value = 0; + uint_fast8_t query_part_count = sn_coap_builder_options_get_option_part_count(query_len, query_ptr, option); + uint_fast8_t i = 0; + uint_fast16_t ret_value = 0; /* * * * * * * * * * * * * * * * * * * * * * * * */ /* * * * Calculate Uri-query options length * * */ @@ -852,7 +858,7 @@ static uint16_t sn_coap_builder_options_calc_option_size(uint16_t query_len, con /* * * Length of Option number and Option value length * * */ /* Get length of Query part */ - uint16_t one_query_part_len = sn_coap_builder_options_get_option_part_length_from_whole_option_string(query_len, query_ptr, i, option); + uint_fast16_t one_query_part_len = sn_coap_builder_options_get_option_part_length_from_whole_option_string(query_len, query_ptr, i, option); /* Check option length */ switch (option) { @@ -920,25 +926,27 @@ static uint16_t sn_coap_builder_options_calc_option_size(uint16_t query_len, con * * \return Return value is count of query parts */ -static uint8_t sn_coap_builder_options_get_option_part_count(uint16_t query_len, const uint8_t *query_ptr, sn_coap_option_numbers_e option) +static uint_fast8_t sn_coap_builder_options_get_option_part_count(uint_fast16_t query_len, const uint8_t *query_ptr, sn_coap_option_numbers_e option) { - uint8_t returned_query_count = 0; - uint16_t query_len_index = 0; - uint8_t char_to_search = '&'; + if (query_len <= 2) { + return 1; + } + + const uint8_t *query_end = query_ptr + query_len - 1; + uint8_t char_to_search = '&'; if (option == COAP_OPTION_URI_PATH || option == COAP_OPTION_LOCATION_PATH) { char_to_search = '/'; } /* Loop whole query and search '\0' characters (not first and last char) */ - for (query_len_index = 1; query_len_index < query_len - 1; query_len_index++) { - /* If new query part starts */ - if (*(query_ptr + query_len_index) == char_to_search) { /* If match */ + uint_fast8_t returned_query_count = 1; + query_ptr++; + do { + if (*query_ptr++ == char_to_search) { /* If match */ returned_query_count++; } - } - - returned_query_count++; + } while (query_ptr < query_end); return returned_query_count; } @@ -960,13 +968,13 @@ static uint8_t sn_coap_builder_options_get_option_part_count(uint16_t query_len, * * \return Return value is length of query part */ -static uint16_t sn_coap_builder_options_get_option_part_length_from_whole_option_string(uint16_t query_len, const uint8_t *query_ptr, - uint8_t query_index, sn_coap_option_numbers_e option) +static uint_fast16_t sn_coap_builder_options_get_option_part_length_from_whole_option_string(uint_fast16_t query_len, const uint8_t *query_ptr, + uint_fast8_t query_index, sn_coap_option_numbers_e option) { - uint16_t returned_query_part_len = 0; - uint8_t temp_query_index = 0; - uint16_t query_len_index = 0; - uint8_t char_to_search = '&'; + uint_fast16_t returned_query_part_len = 0; + uint_fast8_t temp_query_index = 0; + uint_fast16_t query_len_index = 0; + uint_fast8_t char_to_search = '&'; if (option == COAP_OPTION_URI_PATH || option == COAP_OPTION_LOCATION_PATH) { char_to_search = '/'; @@ -975,7 +983,7 @@ static uint16_t sn_coap_builder_options_get_option_part_length_from_whole_option /* Loop whole query and search '\0' characters */ for (query_len_index = 0; query_len_index < query_len; query_len_index++) { /* Store character to temp_char for helping debugging */ - uint8_t temp_char = *query_ptr; + uint_fast8_t temp_char = *query_ptr; /* If new query part starts */ if (temp_char == char_to_search && returned_query_part_len > 0) { /* returned_query_part_len > 0 is for querys which start with "\0" */ @@ -1018,13 +1026,13 @@ static uint16_t sn_coap_builder_options_get_option_part_length_from_whole_option * \return Return value is position (= offset) of query part in whole query. In * fail cases -1 is returned. */ -static int16_t sn_coap_builder_options_get_option_part_position(uint16_t query_len, const uint8_t *query_ptr, - uint8_t query_index, sn_coap_option_numbers_e option) +static int_fast16_t sn_coap_builder_options_get_option_part_position(uint_fast16_t query_len, const uint8_t *query_ptr, + uint_fast8_t query_index, sn_coap_option_numbers_e option) { - uint16_t returned_query_part_offset = 0; - uint8_t temp_query_index = 0; - uint16_t query_len_index = 0; - uint8_t char_to_search = '&'; + uint_fast16_t returned_query_part_offset = 0; + uint_fast8_t temp_query_index = 0; + uint_fast16_t query_len_index = 0; + uint_fast8_t char_to_search = '&'; if (option == COAP_OPTION_URI_PATH || option == COAP_OPTION_LOCATION_PATH) { char_to_search = '/'; @@ -1041,7 +1049,7 @@ static int16_t sn_coap_builder_options_get_option_part_position(uint16_t query_l /* Loop whole query and search separator characters */ for (query_len_index = 0; query_len_index < query_len; query_len_index++) { /* Store character to temp_char for helping debugging */ - uint8_t temp_char = *query_ptr; + uint_fast8_t temp_char = *query_ptr; /* If new query part starts */ if (temp_char == char_to_search && returned_query_part_offset > 0) { /* returned_query_part_offset > 0 is for querys which start with searched char */ @@ -1065,27 +1073,28 @@ static int16_t sn_coap_builder_options_get_option_part_position(uint16_t query_l /** - * \fn static void sn_coap_builder_payload_build(uint8_t **dst_packet_data_pptr, sn_coap_hdr_s *src_coap_msg_ptr) + * \fn static void sn_coap_builder_payload_build(uint8_t *dst_packet_data_pptr, sn_coap_hdr_s *src_coap_msg_ptr) * * \brief Builds Options part of Packet data * - * \param **dst_packet_data_pptr is destination for built Packet data + * \param *dst_packet_data_ptr is destination for built Packet data * * \param *src_coap_msg_ptr is source for building Packet data */ -static void sn_coap_builder_payload_build(uint8_t **dst_packet_data_pptr, const sn_coap_hdr_s *src_coap_msg_ptr) +static uint8_t *sn_coap_builder_payload_build(uint8_t * restrict dst_packet_data_ptr, const sn_coap_hdr_s * restrict src_coap_msg_ptr) { /* Check if Payload is used at all */ if (src_coap_msg_ptr->payload_len && src_coap_msg_ptr->payload_ptr != NULL) { /* Write Payload marker */ - **dst_packet_data_pptr = 0xff; - (*dst_packet_data_pptr)++; + *dst_packet_data_ptr++ = 0xff; /* Write Payload */ - memcpy(*dst_packet_data_pptr, src_coap_msg_ptr->payload_ptr, src_coap_msg_ptr->payload_len); + memcpy(dst_packet_data_ptr, src_coap_msg_ptr->payload_ptr, src_coap_msg_ptr->payload_len); /* Increase destination Packet data pointer */ - (*dst_packet_data_pptr) += src_coap_msg_ptr->payload_len; + dst_packet_data_ptr += src_coap_msg_ptr->payload_len; } + + return dst_packet_data_ptr; } diff --git a/connectivity/libraries/mbed-coap/source/sn_coap_parser.c b/connectivity/libraries/mbed-coap/source/sn_coap_parser.c index 8145a0856a..7764afd36c 100644 --- a/connectivity/libraries/mbed-coap/source/sn_coap_parser.c +++ b/connectivity/libraries/mbed-coap/source/sn_coap_parser.c @@ -42,11 +42,11 @@ /* * * * LOCAL FUNCTION PROTOTYPES * * * */ /* * * * * * * * * * * * * * * * * * * * */ -static void sn_coap_parser_header_parse(uint8_t **packet_data_pptr, sn_coap_hdr_s *dst_coap_msg_ptr, coap_version_e *coap_version_ptr); -static int8_t sn_coap_parser_options_parse(struct coap_s *handle, uint8_t **packet_data_pptr, sn_coap_hdr_s *dst_coap_msg_ptr, uint8_t *packet_data_start_ptr, uint16_t packet_len); -static int8_t sn_coap_parser_options_parse_multiple_options(struct coap_s *handle, uint8_t **packet_data_pptr, uint16_t packet_left_len, uint8_t **dst_pptr, uint16_t *dst_len_ptr, sn_coap_option_numbers_e option, uint16_t option_number_len); -static int16_t sn_coap_parser_options_count_needed_memory_multiple_option(uint8_t *packet_data_ptr, uint16_t packet_left_len, sn_coap_option_numbers_e option, uint16_t option_number_len); -static int8_t sn_coap_parser_payload_parse(uint16_t packet_data_len, uint8_t *packet_data_start_ptr, uint8_t **packet_data_pptr, sn_coap_hdr_s *dst_coap_msg_ptr); +static const uint8_t *sn_coap_parser_header_parse(const uint8_t *packet_data_ptr, sn_coap_hdr_s *dst_coap_msg_ptr, coap_version_e *coap_version_ptr); +static const uint8_t *sn_coap_parser_options_parse(const uint8_t *packet_data_ptr, struct coap_s *handle, sn_coap_hdr_s *dst_coap_msg_ptr, const uint8_t *packet_data_start_ptr, uint_fast16_t packet_len); +static const uint8_t *sn_coap_parser_options_parse_multiple_options(const uint8_t *packet_data_ptr, struct coap_s *handle, uint_fast16_t packet_left_len, uint8_t **dst_pptr, uint16_t *dst_len_ptr, sn_coap_option_numbers_e option, uint_fast16_t option_number_len); +static int sn_coap_parser_options_count_needed_memory_multiple_option(const uint8_t *packet_data_ptr, uint_fast16_t packet_left_len, sn_coap_option_numbers_e option, uint_fast16_t option_number_len); +static const uint8_t *sn_coap_parser_payload_parse(const uint8_t *packet_data_ptr, uint16_t packet_data_len, uint8_t *packet_data_start_ptr, sn_coap_hdr_s *dst_coap_msg_ptr); sn_coap_hdr_s *sn_coap_parser_init_message(sn_coap_hdr_s *coap_msg_ptr) { @@ -138,7 +138,7 @@ sn_coap_options_list_s *sn_coap_parser_alloc_options(struct coap_s *handle, sn_c sn_coap_hdr_s *sn_coap_parser(struct coap_s *handle, uint16_t packet_data_len, uint8_t *packet_data_ptr, coap_version_e *coap_version_ptr) { - uint8_t *data_temp_ptr = packet_data_ptr; + const uint8_t *data_temp_ptr = packet_data_ptr; sn_coap_hdr_s *parsed_and_returned_coap_msg_ptr = NULL; /* * * * Check given pointer * * * */ @@ -155,15 +155,18 @@ sn_coap_hdr_s *sn_coap_parser(struct coap_s *handle, uint16_t packet_data_len, u } /* * * * Header parsing, move pointer over the header... * * * */ - sn_coap_parser_header_parse(&data_temp_ptr, parsed_and_returned_coap_msg_ptr, coap_version_ptr); + data_temp_ptr = sn_coap_parser_header_parse(data_temp_ptr, parsed_and_returned_coap_msg_ptr, coap_version_ptr); + /* * * * Options parsing, move pointer over the options... * * * */ - if (sn_coap_parser_options_parse(handle, &data_temp_ptr, parsed_and_returned_coap_msg_ptr, packet_data_ptr, packet_data_len) != 0) { + data_temp_ptr = sn_coap_parser_options_parse(data_temp_ptr, handle, parsed_and_returned_coap_msg_ptr, packet_data_ptr, packet_data_len); + if (!data_temp_ptr) { parsed_and_returned_coap_msg_ptr->coap_status = COAP_STATUS_PARSER_ERROR_IN_HEADER; return parsed_and_returned_coap_msg_ptr; } /* * * * Payload parsing * * * */ - if (sn_coap_parser_payload_parse(packet_data_len, packet_data_ptr, &data_temp_ptr, parsed_and_returned_coap_msg_ptr) == -1) { + data_temp_ptr = sn_coap_parser_payload_parse(data_temp_ptr, packet_data_len, packet_data_ptr, parsed_and_returned_coap_msg_ptr); + if (!data_temp_ptr) { parsed_and_returned_coap_msg_ptr->coap_status = COAP_STATUS_PARSER_ERROR_IN_HEADER; return parsed_and_returned_coap_msg_ptr; } @@ -224,22 +227,20 @@ void sn_coap_parser_release_allocated_coap_msg_mem(struct coap_s *handle, sn_coa * * \param *coap_version_ptr is destination for parsed CoAP specification version */ -static void sn_coap_parser_header_parse(uint8_t **packet_data_pptr, sn_coap_hdr_s *dst_coap_msg_ptr, coap_version_e *coap_version_ptr) +static const uint8_t *sn_coap_parser_header_parse(const uint8_t * restrict packet_data_ptr, sn_coap_hdr_s * restrict dst_coap_msg_ptr, coap_version_e * restrict coap_version_ptr) { /* Parse CoAP Version and message type*/ - *coap_version_ptr = (coap_version_e)(**packet_data_pptr & COAP_HEADER_VERSION_MASK); - dst_coap_msg_ptr->msg_type = (sn_coap_msg_type_e)(**packet_data_pptr & COAP_HEADER_MSG_TYPE_MASK); - (*packet_data_pptr) += 1; + *coap_version_ptr = (coap_version_e)(*packet_data_ptr & COAP_HEADER_VERSION_MASK); + dst_coap_msg_ptr->msg_type = (sn_coap_msg_type_e)(*packet_data_ptr++ & COAP_HEADER_MSG_TYPE_MASK); /* Parse Message code */ - dst_coap_msg_ptr->msg_code = (sn_coap_msg_code_e) **packet_data_pptr; - (*packet_data_pptr) += 1; + dst_coap_msg_ptr->msg_code = (sn_coap_msg_code_e) *packet_data_ptr++; /* Parse Message ID */ - dst_coap_msg_ptr->msg_id = *(*packet_data_pptr + 1); - dst_coap_msg_ptr->msg_id += **packet_data_pptr << COAP_HEADER_MSG_ID_MSB_SHIFT; - (*packet_data_pptr) += 2; + dst_coap_msg_ptr->msg_id = *packet_data_ptr++ << COAP_HEADER_MSG_ID_MSB_SHIFT; + dst_coap_msg_ptr->msg_id |= *packet_data_ptr++; + return packet_data_ptr; } /** @@ -250,13 +251,15 @@ static void sn_coap_parser_header_parse(uint8_t **packet_data_pptr, sn_coap_hdr_ * * \return Return value is value of uint */ -static uint32_t sn_coap_parser_options_parse_uint(uint8_t **packet_data_pptr, uint8_t option_len) +static uint32_t sn_coap_parser_options_parse_uint(const uint8_t * restrict * restrict packet_data_pptr, uint_fast8_t option_len) { uint32_t value = 0; + const uint8_t *packet_data_ptr = *packet_data_pptr; while (option_len--) { value <<= 8; - value |= *(*packet_data_pptr)++; + value |= *packet_data_ptr++; } + *packet_data_pptr = packet_data_ptr; return value; } @@ -267,15 +270,15 @@ static uint32_t sn_coap_parser_options_parse_uint(uint8_t **packet_data_pptr, ui * \param b second term of addion * \param result pointer to the result variable * - * \return Return 0 if there was no overflow, -1 otherwise + * \return Return 0 if there was no overflow, non-zero otherwise */ -static int8_t sn_coap_parser_add_u16_limit(uint16_t a, uint16_t b, uint16_t *result) +static int_fast8_t sn_coap_parser_add_u16_limit(uint_fast16_t a, uint_fast16_t b, uint_fast16_t *result) { uint16_t c; c = a + b; if (c < a || c < b) { - return -1; + return 1; } *result = c; @@ -291,19 +294,19 @@ static int8_t sn_coap_parser_add_u16_limit(uint16_t a, uint16_t b, uint16_t *res * \param packet_len total packet length * \param delta the number of bytes forward to check * - * \return Return 0 if the data is within the bounds, -1 otherwise + * \return Return 0 if the data is within the bounds, non-zero otherwise */ -static int8_t sn_coap_parser_check_packet_ptr(uint8_t *packet_data_ptr, uint8_t *packet_data_start_ptr, uint16_t packet_len, uint16_t delta) +static int_fast8_t sn_coap_parser_check_packet_ptr(const uint8_t *packet_data_ptr, const uint8_t *packet_data_start_ptr, uint_fast16_t packet_len, uint_fast16_t delta) { - uint8_t *packet_end = packet_data_start_ptr + packet_len; - uint8_t *new_data_ptr = packet_data_ptr + delta; + const uint8_t *packet_end = packet_data_start_ptr + packet_len; + const uint8_t *new_data_ptr = packet_data_ptr + delta; if (delta > packet_len) { - return -1; + return 1; } if (new_data_ptr < packet_data_start_ptr || new_data_ptr > packet_end) { - return -1; + return 1; } return 0; @@ -319,10 +322,10 @@ static int8_t sn_coap_parser_check_packet_ptr(uint8_t *packet_data_ptr, uint8_t * * \return Return The remaining packet data length */ -static uint16_t sn_coap_parser_move_packet_ptr(uint8_t **packet_data_pptr, uint8_t *packet_data_start_ptr, uint16_t packet_len, uint16_t delta) +static uint_fast16_t sn_coap_parser_move_packet_ptr(const uint8_t * restrict *packet_data_pptr, const uint8_t *packet_data_start_ptr, uint_fast16_t packet_len, uint_fast16_t delta) { - uint8_t *packet_end = packet_data_start_ptr + packet_len; - uint8_t *new_data_ptr = *packet_data_pptr + delta; + const uint8_t *packet_end = packet_data_start_ptr + packet_len; + const uint8_t *new_data_ptr = *packet_data_pptr + delta; if (new_data_ptr < packet_data_start_ptr) { return 0; @@ -333,7 +336,7 @@ static uint16_t sn_coap_parser_move_packet_ptr(uint8_t **packet_data_pptr, uint8 *packet_data_pptr = new_data_ptr; - return (uint16_t)(packet_end - new_data_ptr); + return (uint_fast16_t)(packet_end - new_data_ptr); } /** @@ -344,11 +347,11 @@ static uint16_t sn_coap_parser_move_packet_ptr(uint8_t **packet_data_pptr, uint8 * \param packet_data_start_ptr pointer to data packet start * \param packet_len total packet length * - * \return Return 0 if the data is within the bounds, -1 otherwise + * \return Return 0 if the data is within the bounds, non-zero otherwise */ -static int8_t sn_coap_parser_read_packet_u8(uint8_t *dst, uint8_t *packet_data_ptr, uint8_t *packet_data_start_ptr, uint16_t packet_len) +static int8_t sn_coap_parser_read_packet_u8(uint8_t *dst, const uint8_t *packet_data_ptr, const uint8_t *packet_data_start_ptr, uint_fast16_t packet_len) { - int8_t ptr_check_result; + int_fast8_t ptr_check_result; ptr_check_result = sn_coap_parser_check_packet_ptr(packet_data_ptr, packet_data_start_ptr, packet_len, 1); @@ -371,12 +374,12 @@ static int8_t sn_coap_parser_read_packet_u8(uint8_t *dst, uint8_t *packet_data_p * \param packet_data_start_ptr pointer to data packet start * \param packet_len total packet length * - * \return Return 0 if the data is within the bounds, -1 otherwise + * \return Return 0 if the data is within the bounds, non-zero otherwise */ -static int8_t sn_coap_parser_read_packet_u16(uint16_t *dst, uint8_t *packet_data_ptr, uint8_t *packet_data_start_ptr, uint16_t packet_len) +static int_fast8_t sn_coap_parser_read_packet_u16(uint_fast16_t *dst, const uint8_t *packet_data_ptr, const uint8_t *packet_data_start_ptr, uint16_t packet_len) { - int8_t ptr_check_result; - uint16_t value; + int_fast8_t ptr_check_result; + uint_fast16_t value; ptr_check_result = sn_coap_parser_check_packet_ptr(packet_data_ptr, packet_data_start_ptr, packet_len, 2); @@ -402,9 +405,9 @@ static int8_t sn_coap_parser_read_packet_u16(uint16_t *dst, uint8_t *packet_data * * \return Return 0 if the read was successful, -1 otherwise */ -static int8_t parse_ext_option(uint16_t *dst, uint8_t **packet_data_pptr, uint8_t *packet_data_start_ptr, uint16_t packet_len, uint16_t *message_left) +static int_fast8_t parse_ext_option(uint_fast16_t *dst, const uint8_t * restrict *packet_data_pptr, const uint8_t *packet_data_start_ptr, uint_fast16_t packet_len, uint_fast16_t *message_left) { - uint16_t option_number = *dst; + uint_fast16_t option_number = *dst; if (option_number == 13) { uint8_t option_ext; @@ -421,7 +424,7 @@ static int8_t parse_ext_option(uint16_t *dst, uint8_t **packet_data_pptr, uint8_ *message_left = sn_coap_parser_move_packet_ptr(packet_data_pptr, packet_data_start_ptr, packet_len, 1); } } else if (option_number == 14) { - int8_t read_result = sn_coap_parser_read_packet_u16(&option_number, *packet_data_pptr, packet_data_start_ptr, packet_len); + int_fast8_t read_result = sn_coap_parser_read_packet_u16(&option_number, *packet_data_pptr, packet_data_start_ptr, packet_len); if (read_result != 0) { /* packet_data_pptr would overflow! */ tr_error("sn_coap_parser_options_parse - **packet_data_pptr overflow !"); @@ -449,67 +452,68 @@ static int8_t parse_ext_option(uint16_t *dst, uint8_t **packet_data_pptr, uint8_ * * \brief Parses CoAP message's Options part from given Packet data * - * \param **packet_data_pptr is source of Packet data to be parsed to CoAP message + * \param *packet_data_ptr is source of Packet data to be parsed to CoAP message * \param *dst_coap_msg_ptr is destination for parsed CoAP message * - * \return Return value is 0 in ok case and -1 in failure case + * \return Return value is advanced input pointer in ok case and NULL in failure case */ -static int8_t sn_coap_parser_options_parse(struct coap_s *handle, uint8_t **packet_data_pptr, sn_coap_hdr_s *dst_coap_msg_ptr, uint8_t *packet_data_start_ptr, uint16_t packet_len) +static const uint8_t * sn_coap_parser_options_parse(const uint8_t * restrict packet_data_ptr, struct coap_s * restrict handle, sn_coap_hdr_s * restrict dst_coap_msg_ptr, const uint8_t *packet_data_start_ptr, uint_fast16_t packet_len) { - uint8_t previous_option_number = 0; - int8_t ret_status = 0; - uint16_t message_left = sn_coap_parser_move_packet_ptr(packet_data_pptr, packet_data_start_ptr, packet_len, 0); + uint_fast16_t previous_option_number = 0; + uint_fast16_t message_left = sn_coap_parser_move_packet_ptr(&packet_data_ptr, packet_data_start_ptr, packet_len, 0); /* Parse token, if exists */ dst_coap_msg_ptr->token_len = *packet_data_start_ptr & COAP_HEADER_TOKEN_LENGTH_MASK; if (dst_coap_msg_ptr->token_len) { - int8_t ptr_check_result; + int_fast8_t ptr_check_result; if ((dst_coap_msg_ptr->token_len > 8) || dst_coap_msg_ptr->token_ptr) { tr_error("sn_coap_parser_options_parse - token not valid!"); - return -1; + return NULL; } - ptr_check_result = sn_coap_parser_check_packet_ptr(*packet_data_pptr, packet_data_start_ptr, packet_len, dst_coap_msg_ptr->token_len); + ptr_check_result = sn_coap_parser_check_packet_ptr(packet_data_ptr, packet_data_start_ptr, packet_len, dst_coap_msg_ptr->token_len); if (0 != ptr_check_result) { - tr_error("sn_coap_parser_options_parse - **packet_data_pptr overflow !"); - return -1; + tr_error("sn_coap_parser_options_parse - *packet_data_ptr overflow !"); + return NULL; } - dst_coap_msg_ptr->token_ptr = sn_coap_protocol_malloc_copy(handle, *packet_data_pptr, dst_coap_msg_ptr->token_len); + dst_coap_msg_ptr->token_ptr = sn_coap_protocol_malloc_copy(handle, packet_data_ptr, dst_coap_msg_ptr->token_len); if (dst_coap_msg_ptr->token_ptr == NULL) { tr_error("sn_coap_parser_options_parse - failed to allocate token!"); - return -1; + return NULL; } - message_left = sn_coap_parser_move_packet_ptr(packet_data_pptr, packet_data_start_ptr, packet_len, dst_coap_msg_ptr->token_len); + message_left = sn_coap_parser_move_packet_ptr(&packet_data_ptr, packet_data_start_ptr, packet_len, dst_coap_msg_ptr->token_len); } + message_left = packet_len - (packet_data_ptr - packet_data_start_ptr); + /* Loop all Options */ - while (message_left && (**packet_data_pptr != 0xff)) { + uint_fast8_t option_byte; + while (message_left && ((option_byte = *packet_data_ptr) != 0xff)) { /* Get option length WITHOUT extensions */ - uint16_t option_len = (**packet_data_pptr & 0x0F); + uint_fast16_t option_len = (option_byte & 0x0F); /* Get option number WITHOUT extensions */ - uint16_t option_number = (**packet_data_pptr >> COAP_OPTIONS_OPTION_NUMBER_SHIFT); + uint_fast16_t option_number = (option_byte >> COAP_OPTIONS_OPTION_NUMBER_SHIFT); - message_left = sn_coap_parser_move_packet_ptr(packet_data_pptr, packet_data_start_ptr, packet_len, 1); - - int8_t option_parse_result; + message_left = sn_coap_parser_move_packet_ptr(&packet_data_ptr, packet_data_start_ptr, packet_len, 1); + int_fast8_t option_parse_result; /* Add possible option delta extension */ - option_parse_result = parse_ext_option(&option_number, packet_data_pptr, packet_data_start_ptr, packet_len, &message_left); + option_parse_result = parse_ext_option(&option_number, &packet_data_ptr, packet_data_start_ptr, packet_len, &message_left); if (option_parse_result != 0) { - return -1; + return NULL; } /* Add previous option to option delta and get option number */ if (sn_coap_parser_add_u16_limit(option_number, previous_option_number, &option_number) != 0) { - return -1; + return NULL; } /* Add possible option length extension to resolve full length of the option */ - option_parse_result = parse_ext_option(&option_len, packet_data_pptr, packet_data_start_ptr, packet_len, &message_left); + option_parse_result = parse_ext_option(&option_len, &packet_data_ptr, packet_data_start_ptr, packet_len, &message_left); if (option_parse_result != 0) { - return -1; + return NULL; } /* * * Parse option itself * * */ @@ -533,15 +537,15 @@ static int8_t sn_coap_parser_options_parse(struct coap_s *handle, uint8_t **pack case COAP_OPTION_SIZE2: if (sn_coap_parser_alloc_options(handle, dst_coap_msg_ptr) == NULL) { tr_error("sn_coap_parser_options_parse - failed to allocate options!"); - return -1; + return NULL; } break; } if (message_left < option_len){ - /* packet_data_pptr would overflow! */ - tr_error("sn_coap_parser_options_parse - **packet_data_pptr would overflow when parsing options!"); - return -1; + /* packet_data_ptr would overflow! */ + tr_error("sn_coap_parser_options_parse - *packet_data_ptr would overflow when parsing options!"); + return NULL; } /* Parse option */ @@ -549,100 +553,102 @@ static int8_t sn_coap_parser_options_parse(struct coap_s *handle, uint8_t **pack case COAP_OPTION_CONTENT_FORMAT: if ((option_len > 2) || (dst_coap_msg_ptr->content_format != COAP_CT_NONE)) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_CONTENT_FORMAT not valid!"); - return -1; + return NULL; } - dst_coap_msg_ptr->content_format = (sn_coap_content_format_e) sn_coap_parser_options_parse_uint(packet_data_pptr, option_len); + dst_coap_msg_ptr->content_format = (sn_coap_content_format_e) sn_coap_parser_options_parse_uint(&packet_data_ptr, option_len); break; case COAP_OPTION_MAX_AGE: if (option_len > 4) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_MAX_AGE not valid!"); - return -1; + return NULL; } - dst_coap_msg_ptr->options_list_ptr->max_age = sn_coap_parser_options_parse_uint(packet_data_pptr, option_len); + dst_coap_msg_ptr->options_list_ptr->max_age = sn_coap_parser_options_parse_uint(&packet_data_ptr, option_len); break; case COAP_OPTION_PROXY_URI: if ((option_len > 1034) || (option_len < 1) || dst_coap_msg_ptr->options_list_ptr->proxy_uri_ptr) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_PROXY_URI not valid!"); - return -1; + return NULL; } dst_coap_msg_ptr->options_list_ptr->proxy_uri_len = option_len; - dst_coap_msg_ptr->options_list_ptr->proxy_uri_ptr = sn_coap_protocol_malloc_copy(handle, *packet_data_pptr, option_len); + dst_coap_msg_ptr->options_list_ptr->proxy_uri_ptr = sn_coap_protocol_malloc_copy(handle, packet_data_ptr, option_len); if (dst_coap_msg_ptr->options_list_ptr->proxy_uri_ptr == NULL) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_PROXY_URI allocation failed!"); - return -1; + return NULL; } - message_left = sn_coap_parser_move_packet_ptr(packet_data_pptr, packet_data_start_ptr, packet_len, option_len); + message_left = sn_coap_parser_move_packet_ptr(&packet_data_ptr, packet_data_start_ptr, packet_len, option_len); break; case COAP_OPTION_ETAG: if (dst_coap_msg_ptr->options_list_ptr->etag_ptr) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_ETAG exists!"); - return -1; + return NULL; } /* This is managed independently because User gives this option in one character table */ - ret_status = sn_coap_parser_options_parse_multiple_options(handle, packet_data_pptr, + uint16_t len; + packet_data_ptr = sn_coap_parser_options_parse_multiple_options(packet_data_ptr, handle, message_left, &dst_coap_msg_ptr->options_list_ptr->etag_ptr, - (uint16_t *)&dst_coap_msg_ptr->options_list_ptr->etag_len, + &len, COAP_OPTION_ETAG, option_len); - if (ret_status < 0) { + if (!packet_data_ptr) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_ETAG not valid!"); - return -1; + return NULL; } + dst_coap_msg_ptr->options_list_ptr->etag_len = (uint8_t) len; break; case COAP_OPTION_URI_HOST: if ((option_len > 255) || (option_len < 1) || dst_coap_msg_ptr->options_list_ptr->uri_host_ptr) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_URI_HOST not valid!"); - return -1; + return NULL; } dst_coap_msg_ptr->options_list_ptr->uri_host_len = option_len; - dst_coap_msg_ptr->options_list_ptr->uri_host_ptr = sn_coap_protocol_malloc_copy(handle, *packet_data_pptr, option_len); + dst_coap_msg_ptr->options_list_ptr->uri_host_ptr = sn_coap_protocol_malloc_copy(handle, packet_data_ptr, option_len); if (dst_coap_msg_ptr->options_list_ptr->uri_host_ptr == NULL) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_URI_HOST allocation failed!"); - return -1; + return NULL; } - message_left = sn_coap_parser_move_packet_ptr(packet_data_pptr, packet_data_start_ptr, packet_len, option_len); + message_left = sn_coap_parser_move_packet_ptr(&packet_data_ptr, packet_data_start_ptr, packet_len, option_len); break; case COAP_OPTION_LOCATION_PATH: if (dst_coap_msg_ptr->options_list_ptr->location_path_ptr) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_LOCATION_PATH exists!"); - return -1; + return NULL; } /* This is managed independently because User gives this option in one character table */ - ret_status = sn_coap_parser_options_parse_multiple_options(handle, packet_data_pptr, message_left, + packet_data_ptr = sn_coap_parser_options_parse_multiple_options(packet_data_ptr, handle, message_left, &dst_coap_msg_ptr->options_list_ptr->location_path_ptr, &dst_coap_msg_ptr->options_list_ptr->location_path_len, COAP_OPTION_LOCATION_PATH, option_len); - if (ret_status < 0) { + if (!packet_data_ptr) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_LOCATION_PATH not valid!"); - return -1; + return NULL; } break; case COAP_OPTION_URI_PORT: if ((option_len > 2) || dst_coap_msg_ptr->options_list_ptr->uri_port != COAP_OPTION_URI_PORT_NONE) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_URI_PORT not valid!"); - return -1; + return NULL; } - dst_coap_msg_ptr->options_list_ptr->uri_port = sn_coap_parser_options_parse_uint(packet_data_pptr, option_len); + dst_coap_msg_ptr->options_list_ptr->uri_port = sn_coap_parser_options_parse_uint(&packet_data_ptr, option_len); break; case COAP_OPTION_LOCATION_QUERY: if (dst_coap_msg_ptr->options_list_ptr->location_query_ptr) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_LOCATION_QUERY exists!"); - return -1; + return NULL; } - ret_status = sn_coap_parser_options_parse_multiple_options(handle, packet_data_pptr, message_left, + packet_data_ptr = sn_coap_parser_options_parse_multiple_options(packet_data_ptr, handle, message_left, &dst_coap_msg_ptr->options_list_ptr->location_query_ptr, &dst_coap_msg_ptr->options_list_ptr->location_query_len, COAP_OPTION_LOCATION_QUERY, option_len); - if (ret_status < 0) { + if (!packet_data_ptr) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_LOCATION_QUERY not valid!"); - return -1; + return NULL; } break; @@ -650,99 +656,99 @@ static int8_t sn_coap_parser_options_parse(struct coap_s *handle, uint8_t **pack case COAP_OPTION_URI_PATH: if (dst_coap_msg_ptr->uri_path_ptr) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_URI_PATH exists!"); - return -1; + return NULL; } - ret_status = sn_coap_parser_options_parse_multiple_options(handle, packet_data_pptr, message_left, + packet_data_ptr = sn_coap_parser_options_parse_multiple_options(packet_data_ptr, handle, message_left, &dst_coap_msg_ptr->uri_path_ptr, &dst_coap_msg_ptr->uri_path_len, COAP_OPTION_URI_PATH, option_len); - if (ret_status < 0) { + if (!packet_data_ptr) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_URI_PATH not valid!"); - return -1; + return NULL; } break; case COAP_OPTION_OBSERVE: if ((option_len > 2) || dst_coap_msg_ptr->options_list_ptr->observe != COAP_OBSERVE_NONE) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_OBSERVE not valid!"); - return -1; + return NULL; } - dst_coap_msg_ptr->options_list_ptr->observe = sn_coap_parser_options_parse_uint(packet_data_pptr, option_len); + dst_coap_msg_ptr->options_list_ptr->observe = sn_coap_parser_options_parse_uint(&packet_data_ptr, option_len); break; case COAP_OPTION_URI_QUERY: - ret_status = sn_coap_parser_options_parse_multiple_options(handle, packet_data_pptr, message_left, + packet_data_ptr = sn_coap_parser_options_parse_multiple_options(packet_data_ptr, handle, message_left, &dst_coap_msg_ptr->options_list_ptr->uri_query_ptr, &dst_coap_msg_ptr->options_list_ptr->uri_query_len, COAP_OPTION_URI_QUERY, option_len); - if (ret_status < 0) { + if (!packet_data_ptr) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_URI_QUERY not valid!"); - return -1; + return NULL; } break; case COAP_OPTION_BLOCK2: if ((option_len > 3) || dst_coap_msg_ptr->options_list_ptr->block2 != COAP_OPTION_BLOCK_NONE) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_BLOCK2 not valid!"); - return -1; + return NULL; } - dst_coap_msg_ptr->options_list_ptr->block2 = sn_coap_parser_options_parse_uint(packet_data_pptr, option_len); + dst_coap_msg_ptr->options_list_ptr->block2 = sn_coap_parser_options_parse_uint(&packet_data_ptr, option_len); break; case COAP_OPTION_BLOCK1: if ((option_len > 3) || dst_coap_msg_ptr->options_list_ptr->block1 != COAP_OPTION_BLOCK_NONE) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_BLOCK1 not valid!"); - return -1; + return NULL; } - dst_coap_msg_ptr->options_list_ptr->block1 = sn_coap_parser_options_parse_uint(packet_data_pptr, option_len); + dst_coap_msg_ptr->options_list_ptr->block1 = sn_coap_parser_options_parse_uint(&packet_data_ptr, option_len); break; case COAP_OPTION_ACCEPT: if ((option_len > 2) || (dst_coap_msg_ptr->options_list_ptr->accept != COAP_CT_NONE)) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_ACCEPT not valid!"); - return -1; + return NULL; } - dst_coap_msg_ptr->options_list_ptr->accept = (sn_coap_content_format_e) sn_coap_parser_options_parse_uint(packet_data_pptr, option_len); + dst_coap_msg_ptr->options_list_ptr->accept = (sn_coap_content_format_e) sn_coap_parser_options_parse_uint(&packet_data_ptr, option_len); break; case COAP_OPTION_SIZE1: if ((option_len > 4) || dst_coap_msg_ptr->options_list_ptr->use_size1) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_SIZE1 not valid!"); - return -1; + return NULL; } dst_coap_msg_ptr->options_list_ptr->use_size1 = true; - dst_coap_msg_ptr->options_list_ptr->size1 = sn_coap_parser_options_parse_uint(packet_data_pptr, option_len); + dst_coap_msg_ptr->options_list_ptr->size1 = sn_coap_parser_options_parse_uint(&packet_data_ptr, option_len); break; case COAP_OPTION_SIZE2: if ((option_len > 4) || dst_coap_msg_ptr->options_list_ptr->use_size2) { tr_error("sn_coap_parser_options_parse - COAP_OPTION_SIZE2 not valid!"); - return -1; + return NULL; } dst_coap_msg_ptr->options_list_ptr->use_size2 = true; - dst_coap_msg_ptr->options_list_ptr->size2 = sn_coap_parser_options_parse_uint(packet_data_pptr, option_len); + dst_coap_msg_ptr->options_list_ptr->size2 = sn_coap_parser_options_parse_uint(&packet_data_ptr, option_len); break; default: tr_error("sn_coap_parser_options_parse - unknown option!"); - return -1; + return NULL; } /* Check for overflow */ - if ((*packet_data_pptr - packet_data_start_ptr) > packet_len) { - return -1; + if ((packet_data_ptr - packet_data_start_ptr) > packet_len) { + return NULL; } - message_left = sn_coap_parser_move_packet_ptr(packet_data_pptr, packet_data_start_ptr, packet_len, 0); + message_left = packet_len - (packet_data_ptr - packet_data_start_ptr); } - return 0; + return packet_data_ptr; } /** - * \fn static int8_t sn_coap_parser_options_parse_multiple_options(uint8_t **packet_data_pptr, uint8_t options_count_left, uint8_t *previous_option_number_ptr, uint8_t **dst_pptr, + * \fn static int8_t sn_coap_parser_options_parse_multiple_options(uint8_t *packet_data_pptr, uint8_t options_count_left, uint8_t *previous_option_number_ptr, uint8_t **dst_pptr, * uint16_t *dst_len_ptr, sn_coap_option_numbers_e option, uint16_t option_number_len) * * \brief Parses CoAP message's Uri-query options * - * \param **packet_data_pptr is source for Packet data to be parsed to CoAP message + * \param *packet_data_ptr is source for Packet data to be parsed to CoAP message * * \param *dst_coap_msg_ptr is destination for parsed CoAP message * @@ -750,26 +756,27 @@ static int8_t sn_coap_parser_options_parse(struct coap_s *handle, uint8_t **pack * * \param *previous_option_number_ptr is pointer to used and returned previous Option number * - * \return Return value is count of Uri-query optios parsed. In failure case -1 is returned. + * \return Return value is advanced input pointer. In failure case NULL is returned. */ -static int8_t sn_coap_parser_options_parse_multiple_options(struct coap_s *handle, uint8_t **packet_data_pptr, uint16_t packet_left_len, uint8_t **dst_pptr, uint16_t *dst_len_ptr, sn_coap_option_numbers_e option, uint16_t option_number_len) +static const uint8_t *sn_coap_parser_options_parse_multiple_options(const uint8_t * restrict packet_data_ptr, struct coap_s * restrict handle, uint_fast16_t packet_left_len, uint8_t ** restrict dst_pptr, uint16_t * restrict dst_len_ptr, sn_coap_option_numbers_e option, uint_fast16_t option_number_len) { - int16_t uri_query_needed_heap = sn_coap_parser_options_count_needed_memory_multiple_option(*packet_data_pptr, packet_left_len, option, option_number_len); - uint8_t *temp_parsed_uri_query_ptr = NULL; - uint8_t returned_option_counter = 0; - uint8_t *start_ptr = *packet_data_pptr; - uint16_t message_left = packet_left_len; + + int uri_query_needed_heap = sn_coap_parser_options_count_needed_memory_multiple_option(packet_data_ptr, packet_left_len, option, option_number_len); + uint8_t * restrict temp_parsed_uri_query_ptr = NULL; + const uint8_t *start_ptr = packet_data_ptr; + uint_fast16_t message_left = packet_left_len; + bool first_option = true; if (uri_query_needed_heap == -1) { - return -1; + return NULL; } if (uri_query_needed_heap) { - *dst_pptr = (uint8_t *) handle->sn_coap_protocol_malloc(uri_query_needed_heap); + *dst_pptr = handle->sn_coap_protocol_malloc(uri_query_needed_heap); if (*dst_pptr == NULL) { tr_error("sn_coap_parser_options_parse_multiple_options - failed to allocate options!"); - return -1; + return NULL; } } @@ -779,7 +786,7 @@ static int8_t sn_coap_parser_options_parse_multiple_options(struct coap_s *handl /* Loop all Uri-Query options */ while ((temp_parsed_uri_query_ptr - *dst_pptr) < uri_query_needed_heap && message_left) { /* Check if this is first Uri-Query option */ - if (returned_option_counter > 0) { + if (!first_option) { /* Uri-Query is modified to following format: temp1'\0'temp2'\0'temp3 i.e. */ /* Uri-Path is modified to following format: temp1\temp2\temp3 i.e. */ if (option == COAP_OPTION_URI_QUERY || option == COAP_OPTION_LOCATION_QUERY || option == COAP_OPTION_ETAG || option == COAP_OPTION_ACCEPT) { @@ -789,43 +796,42 @@ static int8_t sn_coap_parser_options_parse_multiple_options(struct coap_s *handl } temp_parsed_uri_query_ptr++; + } else { + first_option = false; } - returned_option_counter++; - if (((temp_parsed_uri_query_ptr - *dst_pptr) + option_number_len) > uri_query_needed_heap) { - return -1; + return NULL; } - - if (0 != sn_coap_parser_check_packet_ptr(*packet_data_pptr, start_ptr, packet_left_len, option_number_len)) { + if (0 != sn_coap_parser_check_packet_ptr(packet_data_ptr, start_ptr, packet_left_len, option_number_len)) { /* Buffer read overflow. */ - return -1; + return NULL; } /* Copy the option value to URI query buffer */ - memcpy(temp_parsed_uri_query_ptr, *packet_data_pptr, option_number_len); + memcpy(temp_parsed_uri_query_ptr, packet_data_ptr, option_number_len); - message_left = sn_coap_parser_move_packet_ptr(packet_data_pptr, start_ptr, packet_left_len, option_number_len); + message_left = sn_coap_parser_move_packet_ptr(&packet_data_ptr, start_ptr, packet_left_len, option_number_len); temp_parsed_uri_query_ptr += option_number_len; /* Check if there is more input to process */ - if (message_left == 0 || ((**packet_data_pptr >> COAP_OPTIONS_OPTION_NUMBER_SHIFT) != 0)) { - return returned_option_counter; + if (message_left == 0 || ((*packet_data_ptr >> COAP_OPTIONS_OPTION_NUMBER_SHIFT) != 0)) { + return packet_data_ptr; } /* Process next option */ - option_number_len = (**packet_data_pptr & 0x0F); - message_left = sn_coap_parser_move_packet_ptr(packet_data_pptr, start_ptr, packet_left_len, 1); + option_number_len = (*packet_data_ptr & 0x0F); + message_left = sn_coap_parser_move_packet_ptr(&packet_data_ptr, start_ptr, packet_left_len, 1); /* Add possible option length extension to resolve full length of the option */ - int8_t option_parse_result = parse_ext_option(&option_number_len, packet_data_pptr, start_ptr, packet_left_len, &message_left); + int_fast8_t option_parse_result = parse_ext_option(&option_number_len, &packet_data_ptr, start_ptr, packet_left_len, &message_left); if (option_parse_result != 0) { /* Extended option parsing failed. */ - return -1; + return NULL; } } - return returned_option_counter; + return packet_data_ptr; } /** @@ -843,11 +849,11 @@ static int8_t sn_coap_parser_options_parse_multiple_options(struct coap_s *handl * * \param uint16_t option_number_len length of the first option part */ -static int16_t sn_coap_parser_options_count_needed_memory_multiple_option(uint8_t *packet_data_ptr, uint16_t packet_left_len, sn_coap_option_numbers_e option, uint16_t option_number_len) +static int sn_coap_parser_options_count_needed_memory_multiple_option(const uint8_t * restrict packet_data_ptr, uint_fast16_t packet_left_len, sn_coap_option_numbers_e option, uint_fast16_t option_number_len) { - uint16_t ret_value = 0; - uint16_t message_left = packet_left_len; - uint8_t *start_ptr = packet_data_ptr; + int ret_value = 0; + uint_fast16_t message_left = packet_left_len; + const uint8_t *start_ptr = packet_data_ptr; /* Loop all Uri-Query options */ while (message_left > 0) { @@ -871,7 +877,7 @@ static int16_t sn_coap_parser_options_count_needed_memory_multiple_option(uint8_ } /* Check if the value length is within buffer limits */ - int8_t ptr_check_result = sn_coap_parser_check_packet_ptr(packet_data_ptr, start_ptr, packet_left_len, option_number_len); + int_fast8_t ptr_check_result = sn_coap_parser_check_packet_ptr(packet_data_ptr, start_ptr, packet_left_len, option_number_len); if (ptr_check_result != 0) { return -1; } @@ -896,7 +902,7 @@ static int16_t sn_coap_parser_options_count_needed_memory_multiple_option(uint8_ message_left = sn_coap_parser_move_packet_ptr(&packet_data_ptr, start_ptr, packet_left_len, 1); /* Add possible option length extension to resolve full length of the option */ - int8_t option_parse_result = parse_ext_option(&option_number_len, &packet_data_ptr, start_ptr, packet_left_len, &message_left); + int_fast8_t option_parse_result = parse_ext_option(&option_number_len, &packet_data_ptr, start_ptr, packet_left_len, &message_left); if (option_parse_result != 0) { return -1; } @@ -922,29 +928,29 @@ static int16_t sn_coap_parser_options_count_needed_memory_multiple_option(uint8_ * * \param *dst_coap_msg_ptr is destination for parsed CoAP message *****************************************************************************/ -static int8_t sn_coap_parser_payload_parse(uint16_t packet_data_len, uint8_t *packet_data_start_ptr, uint8_t **packet_data_pptr, sn_coap_hdr_s *dst_coap_msg_ptr) +static const uint8_t *sn_coap_parser_payload_parse(const uint8_t * restrict packet_data_ptr, uint16_t packet_data_len, uint8_t *packet_data_start_ptr, sn_coap_hdr_s * restrict dst_coap_msg_ptr) { /* If there is payload */ - if ((*packet_data_pptr - packet_data_start_ptr) < packet_data_len) { - if (**packet_data_pptr == 0xff) { - (*packet_data_pptr)++; + if ((packet_data_ptr - packet_data_start_ptr) < packet_data_len) { + if (*packet_data_ptr == 0xff) { + packet_data_ptr++; /* Parse Payload length */ - dst_coap_msg_ptr->payload_len = packet_data_len - (*packet_data_pptr - packet_data_start_ptr); + dst_coap_msg_ptr->payload_len = packet_data_len - (packet_data_ptr - packet_data_start_ptr); /* The presence of a marker followed by a zero-length payload MUST be processed as a message format error */ if (dst_coap_msg_ptr->payload_len == 0) { - return -1; + return NULL; } /* Parse Payload by setting CoAP message's payload_ptr to point Payload in Packet data */ - dst_coap_msg_ptr->payload_ptr = *packet_data_pptr; + dst_coap_msg_ptr->payload_ptr = (uint8_t *) packet_data_ptr; } /* No payload marker.. */ else { tr_error("sn_coap_parser_payload_parse - payload marker not found!"); - return -1; + return NULL; } } - return 0; + return packet_data_ptr; } diff --git a/connectivity/libraries/mbed-coap/source/sn_coap_protocol.c b/connectivity/libraries/mbed-coap/source/sn_coap_protocol.c index 855bfb9288..5f6f68c96c 100644 --- a/connectivity/libraries/mbed-coap/source/sn_coap_protocol.c +++ b/connectivity/libraries/mbed-coap/source/sn_coap_protocol.c @@ -52,8 +52,8 @@ static void sn_coap_protocol_linked_list_duplication_info_store static coap_duplication_info_s *sn_coap_protocol_linked_list_duplication_info_search(const struct coap_s *handle, const sn_nsdl_addr_s *scr_addr_ptr, const uint16_t msg_id); static void sn_coap_protocol_linked_list_duplication_info_remove_old_ones(struct coap_s *handle); static void sn_coap_protocol_duplication_info_free(struct coap_s *handle, coap_duplication_info_s *duplication_info_ptr); -static bool sn_coap_protocol_update_duplicate_package_data(const struct coap_s *handle, const sn_nsdl_addr_s *dst_addr_ptr, const sn_coap_hdr_s *coap_msg_ptr, const int16_t data_size, const uint8_t *dst_packet_data_ptr); -static bool sn_coap_protocol_update_duplicate_package_data_all(const struct coap_s *handle, const sn_nsdl_addr_s *dst_addr_ptr, const sn_coap_hdr_s *coap_msg_ptr, const int16_t data_size, const uint8_t *dst_packet_data_ptr); +static bool sn_coap_protocol_update_duplicate_package_data(const struct coap_s *handle, const sn_nsdl_addr_s *dst_addr_ptr, const sn_coap_hdr_s *coap_msg_ptr, const int_fast16_t data_size, const uint8_t *dst_packet_data_ptr); +static bool sn_coap_protocol_update_duplicate_package_data_all(const struct coap_s *handle, const sn_nsdl_addr_s *dst_addr_ptr, const sn_coap_hdr_s *coap_msg_ptr, const int_fast16_t data_size, const uint8_t *dst_packet_data_ptr); #endif @@ -65,8 +65,8 @@ static coap_blockwise_payload_s *sn_coap_protocol_linked_list_blockwise_search(s static bool sn_coap_protocol_linked_list_blockwise_payload_search_compare_block_number(struct coap_s *handle, const sn_nsdl_addr_s *src_addr_ptr, const uint8_t *token_ptr, uint8_t token_len, uint32_t block_number); static void sn_coap_protocol_linked_list_blockwise_payload_remove(struct coap_s *handle, coap_blockwise_payload_s *removed_payload_ptr); static uint32_t sn_coap_protocol_linked_list_blockwise_payloads_get_len(struct coap_s *handle, const sn_nsdl_addr_s *src_addr_ptr, const uint8_t *token_ptr, uint8_t token_len); -static void sn_coap_protocol_handle_blockwise_timout(struct coap_s *handle); -static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn_nsdl_addr_s *src_addr_ptr, sn_coap_hdr_s *received_coap_msg_ptr, void *param); +static void sn_coap_protocol_handle_blockwise_timeout(struct coap_s *handle); +static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn_nsdl_addr_s *src_addr_ptr, sn_coap_hdr_s *received_coap_msg_ptr, void *param, bool *keep_in_resend_queue); static bool sn_coap_handle_last_blockwise(struct coap_s *handle, const sn_nsdl_addr_s *src_addr_ptr, sn_coap_hdr_s *received_coap_msg_ptr); static sn_coap_hdr_s *sn_coap_protocol_copy_header(struct coap_s *handle, const sn_coap_hdr_s *source_header_ptr); static coap_blockwise_msg_s *search_sent_blockwise_message(struct coap_s *handle, uint16_t msg_id); @@ -74,18 +74,18 @@ static int16_t store_blockwise_copy(struct coap_s *handle, cons #endif #if ENABLE_RESENDINGS -static uint8_t sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len, uint8_t *send_packet_data_ptr, uint32_t sending_time, void *param); +static uint8_t sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint_fast16_t send_packet_data_len, uint8_t *send_packet_data_ptr, uint32_t sending_time, void *param); static void sn_coap_protocol_linked_list_send_msg_remove(struct coap_s *handle, const sn_nsdl_addr_s *src_addr_ptr, uint16_t msg_id); -static coap_send_msg_s *sn_coap_protocol_allocate_mem_for_msg(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t packet_data_len); +static coap_send_msg_s *sn_coap_protocol_allocate_mem_for_msg(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint_fast16_t packet_data_len); static void sn_coap_protocol_release_allocated_send_msg_mem(struct coap_s *handle, coap_send_msg_s *freed_send_msg_ptr); -static uint16_t sn_coap_count_linked_list_size(const coap_send_msg_list_t *linked_list_ptr); +static uint_fast16_t sn_coap_count_linked_list_size(const coap_send_msg_list_t *linked_list_ptr); static uint32_t sn_coap_calculate_new_resend_time(const uint32_t current_time, const uint8_t interval, const uint8_t counter); #endif static uint16_t read_packet_msg_id(const coap_send_msg_s *stored_msg); static uint16_t get_new_message_id(void); -static bool compare_port(const sn_nsdl_addr_s* left, const sn_nsdl_addr_s* right); +static bool compare_port(const sn_nsdl_addr_s *left, const sn_nsdl_addr_s *right); /* * * * * * * * * * * * * * * * * */ /* * * * GLOBAL DECLARATIONS * * * */ @@ -202,19 +202,9 @@ int8_t sn_coap_protocol_set_block_size(struct coap_s *handle, uint16_t block_siz if (handle == NULL) { return -1; } - switch (block_size) { - case 0: - case 16: - case 32: - case 64: - case 128: - case 256: - case 512: - case 1024: - handle->sn_coap_block_data_size = block_size; - return 0; - default: - break; + if (sn_coap_convert_block_size(block_size) >= 0) { + handle->sn_coap_block_data_size = block_size; + return 0; } #endif return -1; @@ -268,7 +258,7 @@ int8_t sn_coap_protocol_set_duplicate_buffer_size(struct coap_s *handle, uint8_t } int8_t sn_coap_protocol_set_retransmission_parameters(struct coap_s *handle, - uint8_t resending_count, uint8_t resending_intervall) + uint8_t resending_count, uint8_t resending_intervall) { #if ENABLE_RESENDINGS if (handle == NULL) { @@ -290,14 +280,14 @@ int8_t sn_coap_protocol_set_retransmission_parameters(struct coap_s *handle, } int8_t sn_coap_protocol_set_retransmission_buffer(struct coap_s *handle, - uint8_t buffer_size_messages, uint16_t buffer_size_bytes) + uint8_t buffer_size_messages, uint16_t buffer_size_bytes) { #if ENABLE_RESENDINGS if (handle == NULL) { return -1; } if (buffer_size_bytes <= SN_COAP_MAX_ALLOWED_RESENDING_BUFF_SIZE_BYTES && - buffer_size_messages <= SN_COAP_MAX_ALLOWED_RESENDING_BUFF_SIZE_MSGS ) { + buffer_size_messages <= SN_COAP_MAX_ALLOWED_RESENDING_BUFF_SIZE_MSGS) { handle->sn_coap_resending_queue_bytes = buffer_size_bytes; handle->sn_coap_resending_queue_msgs = buffer_size_messages; return 0; @@ -317,8 +307,8 @@ void sn_coap_protocol_clear_retransmission_buffer(struct coap_s *handle) ns_list_foreach_safe(coap_send_msg_s, tmp, &handle->linked_list_resent_msgs) { ns_list_remove(&handle->linked_list_resent_msgs, tmp); sn_coap_protocol_release_allocated_send_msg_mem(handle, tmp); - --handle->count_resent_msgs; } + handle->count_resent_msgs = 0; #endif } @@ -352,7 +342,7 @@ int8_t sn_coap_protocol_delete_retransmission_by_token(struct coap_s *handle, co } ns_list_foreach(coap_send_msg_s, stored_msg, &handle->linked_list_resent_msgs) { - uint8_t stored_token_len = (stored_msg->send_msg_ptr.packet_ptr[0] & 0x0F); + uint8_t stored_token_len = (stored_msg->send_msg_ptr.packet_ptr[0] & 0x0F); if (stored_token_len == token_len) { if (memcmp(&stored_msg->send_msg_ptr.packet_ptr[4], token, stored_token_len) == 0) { @@ -384,8 +374,8 @@ int8_t prepare_blockwise_message(struct coap_s *handle, sn_coap_hdr_s *src_coap_ #if SN_COAP_BLOCKWISE_ENABLED || SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE /* If Message blockwising is not enabled, this part of code will not be compiled */ if ((src_coap_msg_ptr->payload_len > SN_COAP_MAX_NONBLOCKWISE_PAYLOAD_SIZE) && - (src_coap_msg_ptr->payload_len > handle->sn_coap_block_data_size) && - (handle->sn_coap_block_data_size > 0)) { + (src_coap_msg_ptr->payload_len > handle->sn_coap_block_data_size) && + (handle->sn_coap_block_data_size > 0)) { /* * * * Add Blockwise option to send CoAP message * * */ /* Allocate memory for less used options */ @@ -448,8 +438,8 @@ int16_t sn_coap_protocol_build(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_p #if SN_COAP_BLOCKWISE_ENABLED || SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE /* If Message blockwising is not enabled, this part of code will not be compiled */ /* If blockwising needed */ if ((src_coap_msg_ptr->payload_len > SN_COAP_MAX_NONBLOCKWISE_PAYLOAD_SIZE) && - (src_coap_msg_ptr->payload_len > handle->sn_coap_block_data_size) && - (handle->sn_coap_block_data_size > 0)) { + (src_coap_msg_ptr->payload_len > handle->sn_coap_block_data_size) && + (handle->sn_coap_block_data_size > 0)) { /* Store original Payload length */ original_payload_len = src_coap_msg_ptr->payload_len; /* Change Payload length of send message because Payload is blockwised */ @@ -474,8 +464,8 @@ int16_t sn_coap_protocol_build(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_p /* Store message to Linked list for resending purposes */ uint32_t resend_time = sn_coap_calculate_new_resend_time(handle->system_time, handle->sn_coap_resending_intervall, 0); if (sn_coap_protocol_linked_list_send_msg_store(handle, dst_addr_ptr, byte_count_built, dst_packet_data_ptr, - resend_time, - param) == 0) { + resend_time, + param) == 0) { return -4; } } @@ -523,7 +513,7 @@ int16_t sn_coap_protocol_build(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_p #if SN_COAP_BLOCKWISE_ENABLED || SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE static int16_t store_blockwise_copy(struct coap_s *handle, const sn_coap_hdr_s *src_coap_msg_ptr, void *param, uint16_t original_payload_len, bool copy_payload) { - coap_blockwise_msg_s *stored_blockwise_msg_ptr; + coap_blockwise_msg_s *restrict stored_blockwise_msg_ptr; stored_blockwise_msg_ptr = sn_coap_protocol_calloc(handle, sizeof(coap_blockwise_msg_s)); if (!stored_blockwise_msg_ptr) { @@ -535,20 +525,21 @@ static int16_t store_blockwise_copy(struct coap_s *handle, const sn_coap_hdr_s * /* Fill struct */ stored_blockwise_msg_ptr->timestamp = handle->system_time; - stored_blockwise_msg_ptr->coap_msg_ptr = sn_coap_protocol_copy_header(handle, src_coap_msg_ptr); - if( stored_blockwise_msg_ptr->coap_msg_ptr == NULL ){ + sn_coap_hdr_s *restrict copied_msg_ptr = sn_coap_protocol_copy_header(handle, src_coap_msg_ptr); + if (copied_msg_ptr == NULL) { handle->sn_coap_protocol_free(stored_blockwise_msg_ptr); tr_error("sn_coap_protocol_build - block header copy failed!"); return -2; } + stored_blockwise_msg_ptr->coap_msg_ptr = copied_msg_ptr; if (copy_payload) { - stored_blockwise_msg_ptr->coap_msg_ptr->payload_len = original_payload_len; - stored_blockwise_msg_ptr->coap_msg_ptr->payload_ptr = sn_coap_protocol_malloc_copy(handle, src_coap_msg_ptr->payload_ptr, stored_blockwise_msg_ptr->coap_msg_ptr->payload_len); + copied_msg_ptr->payload_len = original_payload_len; + copied_msg_ptr->payload_ptr = sn_coap_protocol_malloc_copy(handle, src_coap_msg_ptr->payload_ptr, stored_blockwise_msg_ptr->coap_msg_ptr->payload_len); - if (!stored_blockwise_msg_ptr->coap_msg_ptr->payload_ptr) { + if (!copied_msg_ptr->payload_ptr) { //block payload save failed, only first block can be build. Perhaps we should return error. - sn_coap_parser_release_allocated_coap_msg_mem(handle, stored_blockwise_msg_ptr->coap_msg_ptr); + sn_coap_parser_release_allocated_coap_msg_mem(handle, copied_msg_ptr); handle->sn_coap_protocol_free(stored_blockwise_msg_ptr); tr_error("sn_coap_protocol_build - block payload allocation failed!"); return -2; @@ -556,7 +547,7 @@ static int16_t store_blockwise_copy(struct coap_s *handle, const sn_coap_hdr_s * } stored_blockwise_msg_ptr->param = param; - stored_blockwise_msg_ptr->msg_id = stored_blockwise_msg_ptr->coap_msg_ptr->msg_id; + stored_blockwise_msg_ptr->msg_id = copied_msg_ptr->msg_id; ns_list_add_to_end(&handle->linked_list_blockwise_sent_msgs, stored_blockwise_msg_ptr); @@ -564,19 +555,18 @@ static int16_t store_blockwise_copy(struct coap_s *handle, const sn_coap_hdr_s * } #endif -sn_coap_hdr_s *sn_coap_protocol_parse(struct coap_s *handle, sn_nsdl_addr_s *src_addr_ptr, uint16_t packet_data_len, uint8_t *packet_data_ptr, void *param) +sn_coap_hdr_s *sn_coap_protocol_parse(struct coap_s *restrict handle, sn_nsdl_addr_s *restrict src_addr_ptr, uint16_t packet_data_len, uint8_t *restrict packet_data_ptr, void *param) { - sn_coap_hdr_s *returned_dst_coap_msg_ptr = NULL; coap_version_e coap_version = COAP_VERSION_UNKNOWN; /* * * * Check given pointer * * * */ if (src_addr_ptr == NULL || src_addr_ptr->addr_ptr == NULL || - packet_data_ptr == NULL || handle == NULL) { + packet_data_ptr == NULL || handle == NULL) { return NULL; } /* * * * Parse Packet data to CoAP message by using CoAP Header parser * * * */ - returned_dst_coap_msg_ptr = sn_coap_parser(handle, packet_data_len, packet_data_ptr, &coap_version); + sn_coap_hdr_s *restrict returned_dst_coap_msg_ptr = sn_coap_parser(handle, packet_data_len, packet_data_ptr, &coap_version); /* Check status of returned pointer */ if (returned_dst_coap_msg_ptr == NULL) { @@ -651,12 +641,10 @@ sn_coap_hdr_s *sn_coap_protocol_parse(struct coap_s *handle, sn_nsdl_addr_s *src // If no message duplication detected if ((returned_dst_coap_msg_ptr->msg_type == COAP_MSG_TYPE_CONFIRMABLE || - returned_dst_coap_msg_ptr->msg_type == COAP_MSG_TYPE_NON_CONFIRMABLE || - (returned_dst_coap_msg_ptr->msg_type == COAP_MSG_TYPE_ACKNOWLEDGEMENT && - returned_dst_coap_msg_ptr->msg_code != COAP_MSG_CODE_EMPTY)) && - handle->sn_coap_duplication_buffer_size != 0) { + returned_dst_coap_msg_ptr->msg_type == COAP_MSG_TYPE_NON_CONFIRMABLE) && + handle->sn_coap_duplication_buffer_size != 0) { - coap_duplication_info_s* response = sn_coap_protocol_linked_list_duplication_info_search(handle, + coap_duplication_info_s *response = sn_coap_protocol_linked_list_duplication_info_search(handle, src_addr_ptr, returned_dst_coap_msg_ptr->msg_id); if (response == NULL) { @@ -686,12 +674,12 @@ sn_coap_hdr_s *sn_coap_protocol_parse(struct coap_s *handle, sn_nsdl_addr_s *src returned_dst_coap_msg_ptr->coap_status = COAP_STATUS_PARSER_DUPLICATED_MSG; // Send ACK response - if (response && returned_dst_coap_msg_ptr->msg_type != COAP_MSG_TYPE_ACKNOWLEDGEMENT) { + if (response) { // Check that response has been created if (response->packet_ptr) { tr_debug("sn_coap_protocol_parse - send ack for duplicate message"); handle->sn_coap_tx_callback(response->packet_ptr, - response->packet_len, response->address, response->param); + response->packet_len, response->address, response->param); } else { tr_error("sn_coap_protocol_parse - response not yet build"); } @@ -705,15 +693,15 @@ sn_coap_hdr_s *sn_coap_protocol_parse(struct coap_s *handle, sn_nsdl_addr_s *src /*** And here we check if message was block message ***/ /*** If so, we call own block handling function and ***/ /*** return to caller. ***/ - + bool keep_in_resend_queue = false; #if SN_COAP_BLOCKWISE_ENABLED || SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE if (returned_dst_coap_msg_ptr->options_list_ptr != NULL && - (returned_dst_coap_msg_ptr->options_list_ptr->block1 != COAP_OPTION_BLOCK_NONE || - returned_dst_coap_msg_ptr->options_list_ptr->block2 != COAP_OPTION_BLOCK_NONE)) { + (returned_dst_coap_msg_ptr->options_list_ptr->block1 != COAP_OPTION_BLOCK_NONE || + returned_dst_coap_msg_ptr->options_list_ptr->block2 != COAP_OPTION_BLOCK_NONE)) { // the sn_coap_handle_blockwise_message() will return the given message on success or NULL on error - if (sn_coap_handle_blockwise_message(handle, src_addr_ptr, returned_dst_coap_msg_ptr, param) == NULL) { + if (sn_coap_handle_blockwise_message(handle, src_addr_ptr, returned_dst_coap_msg_ptr, param, &keep_in_resend_queue) == NULL) { tr_error("sn_coap_protocol_parse - handle blockwise returns null!"); @@ -794,22 +782,22 @@ cleanup: /* Get ... */ coap_blockwise_msg_s *stored_blockwise_msg_temp_ptr = search_sent_blockwise_message(handle, returned_dst_coap_msg_ptr->msg_id); - /* Remove from the list if not an notification message. + /* Remove from the list if not a notification message. * Initial notification message is needed for sending rest of the blocks (GET request). */ - bool remove_from_the_list = false; if (stored_blockwise_msg_temp_ptr) { + bool remove_from_the_list; if (stored_blockwise_msg_temp_ptr->coap_msg_ptr && - stored_blockwise_msg_temp_ptr->coap_msg_ptr->options_list_ptr && - stored_blockwise_msg_temp_ptr->coap_msg_ptr->options_list_ptr->observe != COAP_OBSERVE_NONE) { + stored_blockwise_msg_temp_ptr->coap_msg_ptr->options_list_ptr && + stored_blockwise_msg_temp_ptr->coap_msg_ptr->options_list_ptr->observe != COAP_OBSERVE_NONE) { remove_from_the_list = false; } else { remove_from_the_list = true; } - } - if (remove_from_the_list) { - sn_coap_protocol_linked_list_blockwise_msg_remove(handle, stored_blockwise_msg_temp_ptr); + if (remove_from_the_list) { + sn_coap_protocol_linked_list_blockwise_msg_remove(handle, stored_blockwise_msg_temp_ptr); + } } } @@ -830,7 +818,7 @@ cleanup: /* Get node count i.e. count of active resending messages */ uint16_t stored_resending_msgs_count = handle->count_resent_msgs; /* Check if there is ongoing active message resendings */ - if (stored_resending_msgs_count > 0) { + if (stored_resending_msgs_count > 0 && !keep_in_resend_queue) { /* Remove resending message from active message resending Linked list, if any exists */ sn_coap_protocol_linked_list_send_msg_remove(handle, src_addr_ptr, returned_dst_coap_msg_ptr->msg_id); } @@ -844,8 +832,8 @@ cleanup: int8_t sn_coap_protocol_exec(struct coap_s *handle, uint32_t current_time) { - if( !handle ){ - return -1; + if (!handle) { + return -1; } /* * * * Store current System time * * * */ @@ -853,7 +841,7 @@ int8_t sn_coap_protocol_exec(struct coap_s *handle, uint32_t current_time) #if SN_COAP_BLOCKWISE_ENABLED || SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE /* * * * Handle block transfer timed outs * * * */ - sn_coap_protocol_handle_blockwise_timout(handle); + sn_coap_protocol_handle_blockwise_timeout(handle); #endif #if SN_COAP_DUPLICATION_MAX_MSGS_COUNT @@ -888,6 +876,9 @@ rescan: tmp_coap_hdr_ptr = sn_coap_parser(handle, stored_msg_ptr->send_msg_ptr.packet_len, stored_msg_ptr->send_msg_ptr.packet_ptr, &coap_version); if (tmp_coap_hdr_ptr != 0) { +#if SN_COAP_BLOCKWISE_ENABLED || SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE + sn_coap_protocol_remove_sent_blockwise_message(handle, tmp_coap_hdr_ptr->msg_id); +#endif // SN_COAP_BLOCKWISE_ENABLED || SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE tmp_coap_hdr_ptr->coap_status = COAP_STATUS_BUILDER_MESSAGE_SENDING_FAILED; handle->sn_coap_rx_callback(tmp_coap_hdr_ptr, &stored_msg_ptr->send_msg_ptr.dst_addr_ptr, stored_msg_ptr->param); @@ -900,7 +891,7 @@ rescan: } else { /* Send message */ handle->sn_coap_tx_callback(stored_msg_ptr->send_msg_ptr.packet_ptr, - stored_msg_ptr->send_msg_ptr.packet_len, &stored_msg_ptr->send_msg_ptr.dst_addr_ptr, stored_msg_ptr->param); + stored_msg_ptr->send_msg_ptr.packet_len, &stored_msg_ptr->send_msg_ptr.dst_addr_ptr, stored_msg_ptr->param); /* * * Count new Resending time * * */ stored_msg_ptr->resending_time = sn_coap_calculate_new_resend_time(current_time, @@ -938,11 +929,11 @@ rescan: * \return 1 Msg stored properly *****************************************************************************/ -static uint8_t sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t send_packet_data_len, - uint8_t *send_packet_data_ptr, uint32_t sending_time, void *param) +static uint8_t sn_coap_protocol_linked_list_send_msg_store(struct coap_s *restrict handle, sn_nsdl_addr_s *restrict dst_addr_ptr, uint_fast16_t send_packet_data_len, + uint8_t *restrict send_packet_data_ptr, uint32_t sending_time, void *param) { - coap_send_msg_s *stored_msg_ptr; + coap_send_msg_s *restrict stored_msg_ptr; /* If both queue parameters are "0" or resending count is "0", then re-sending is disabled */ if (((handle->sn_coap_resending_queue_msgs == 0) && (handle->sn_coap_resending_queue_bytes == 0)) || (handle->sn_coap_resending_count == 0)) { @@ -1005,7 +996,7 @@ static uint8_t sn_coap_protocol_linked_list_send_msg_store(struct coap_s *handle * \param msg_id is searching key for removed message *****************************************************************************/ -static void sn_coap_protocol_linked_list_send_msg_remove(struct coap_s *handle, const sn_nsdl_addr_s *src_addr_ptr, uint16_t msg_id) +static void sn_coap_protocol_linked_list_send_msg_remove(struct coap_s *restrict handle, const sn_nsdl_addr_s *restrict src_addr_ptr, uint16_t msg_id) { /* Loop all stored resending messages in Linked list */ ns_list_foreach(coap_send_msg_s, stored_msg_ptr, &handle->linked_list_resent_msgs) { @@ -1075,10 +1066,10 @@ uint16_t sn_coap_protocol_get_configured_blockwise_size(struct coap_s *handle) * \param *addr_ptr is pointer to Address information to be stored *****************************************************************************/ -static void sn_coap_protocol_linked_list_duplication_info_store(struct coap_s *handle, sn_nsdl_addr_s *addr_ptr, - uint16_t msg_id, void *param) +static void sn_coap_protocol_linked_list_duplication_info_store(struct coap_s *restrict handle, sn_nsdl_addr_s *restrict addr_ptr, + uint16_t msg_id, void *param) { - coap_duplication_info_s *stored_duplication_info_ptr = NULL; + coap_duplication_info_s *restrict stored_duplication_info_ptr = NULL; /* * * * Allocating memory for stored Duplication info * * * */ @@ -1131,8 +1122,8 @@ static void sn_coap_protocol_linked_list_duplication_info_store(struct coap_s *h * \return Return value is 0 when message found and -1 if not found *****************************************************************************/ -static coap_duplication_info_s* sn_coap_protocol_linked_list_duplication_info_search(const struct coap_s *handle, - const sn_nsdl_addr_s *addr_ptr, const uint16_t msg_id) +static coap_duplication_info_s *sn_coap_protocol_linked_list_duplication_info_search(const struct coap_s *handle, + const sn_nsdl_addr_s *addr_ptr, const uint16_t msg_id) { /* Loop all nodes in Linked list for searching Message ID */ ns_list_foreach(coap_duplication_info_s, stored_duplication_info_ptr, &handle->linked_list_duplication_msgs) { @@ -1209,14 +1200,14 @@ void sn_coap_protocol_linked_list_duplication_info_remove(struct coap_s *handle, #if SN_COAP_DUPLICATION_MAX_MSGS_COUNT static void sn_coap_protocol_duplication_info_free(struct coap_s *handle, coap_duplication_info_s *duplication_info_ptr) { - if (duplication_info_ptr) { - if (duplication_info_ptr->address) { - handle->sn_coap_protocol_free(duplication_info_ptr->address->addr_ptr); - handle->sn_coap_protocol_free(duplication_info_ptr->address); - } - handle->sn_coap_protocol_free(duplication_info_ptr->packet_ptr); - handle->sn_coap_protocol_free(duplication_info_ptr); + // General purpose free functions ignore null pointer inputs - this + // private one knows it never receives null. + if (duplication_info_ptr->address) { + handle->sn_coap_protocol_free(duplication_info_ptr->address->addr_ptr); + handle->sn_coap_protocol_free(duplication_info_ptr->address); } + handle->sn_coap_protocol_free(duplication_info_ptr->packet_ptr); + handle->sn_coap_protocol_free(duplication_info_ptr); } #endif // SN_COAP_DUPLICATION_MAX_MSGS_COUNT @@ -1257,14 +1248,14 @@ static void sn_coap_protocol_linked_list_blockwise_msg_remove(struct coap_s *han * \param size1 Size of the whole incoming message *****************************************************************************/ -static void sn_coap_protocol_linked_list_blockwise_payload_store(struct coap_s *handle, sn_nsdl_addr_s *addr_ptr, - uint16_t payload_len, - uint8_t *payload_ptr, - uint8_t *token_ptr, - uint8_t token_len, - uint32_t block_number, - uint16_t block_size, - uint32_t size1) +static void sn_coap_protocol_linked_list_blockwise_payload_store(struct coap_s *restrict handle, sn_nsdl_addr_s *restrict addr_ptr, + uint16_t payload_len, + uint8_t *restrict payload_ptr, + uint8_t *restrict token_ptr, + uint8_t token_len, + uint32_t block_number, + uint16_t block_size, + uint32_t size1) { if (!addr_ptr || !payload_len || !payload_ptr) { return; @@ -1272,14 +1263,14 @@ static void sn_coap_protocol_linked_list_blockwise_payload_store(struct coap_s * // Do not add duplicates to list, this could happen if server needs to retransmit block message again if (sn_coap_protocol_linked_list_blockwise_payload_search_compare_block_number(handle, - addr_ptr, - token_ptr, - token_len, - block_number)) { + addr_ptr, + token_ptr, + token_len, + block_number)) { return; } - coap_blockwise_payload_s *stored_blockwise_payload_ptr = sn_coap_protocol_linked_list_blockwise_search(handle, addr_ptr, token_ptr, token_len); + coap_blockwise_payload_s *restrict stored_blockwise_payload_ptr = sn_coap_protocol_linked_list_blockwise_search(handle, addr_ptr, token_ptr, token_len); if (stored_blockwise_payload_ptr && stored_blockwise_payload_ptr->use_size1) { memcpy(stored_blockwise_payload_ptr->payload_ptr + (block_number * block_size), payload_ptr, payload_len); @@ -1287,7 +1278,7 @@ static void sn_coap_protocol_linked_list_blockwise_payload_store(struct coap_s * uint16_t new_len = stored_blockwise_payload_ptr->payload_len + payload_len; tr_debug("sn_coap_protocol_linked_list_blockwise_payload_store - reallocate from %d to %d", stored_blockwise_payload_ptr->payload_len, new_len); - uint8_t *temp_ptr = handle->sn_coap_protocol_malloc(stored_blockwise_payload_ptr->payload_len); + uint8_t *restrict temp_ptr = handle->sn_coap_protocol_malloc(stored_blockwise_payload_ptr->payload_len); if (temp_ptr == NULL) { tr_error("sn_coap_protocol_linked_list_blockwise_payload_store - failed to allocate temp buffer!"); sn_coap_protocol_linked_list_blockwise_payload_remove(handle, stored_blockwise_payload_ptr); @@ -1448,10 +1439,10 @@ static coap_blockwise_payload_s *sn_coap_protocol_linked_list_blockwise_search(s } static bool sn_coap_protocol_linked_list_blockwise_payload_search_compare_block_number(struct coap_s *handle, - const sn_nsdl_addr_s *src_addr_ptr, - const uint8_t *token_ptr, - uint8_t token_len, - uint32_t block_number) + const sn_nsdl_addr_s *src_addr_ptr, + const uint8_t *token_ptr, + uint8_t token_len, + uint32_t block_number) { /* Loop all stored blockwise payloads in Linked list */ ns_list_foreach(coap_blockwise_payload_s, stored_payload_info_ptr, &handle->linked_list_blockwise_received_payloads) { @@ -1515,7 +1506,7 @@ static uint32_t sn_coap_protocol_linked_list_blockwise_payloads_get_len(struct c if ((0 == memcmp(src_addr_ptr->addr_ptr, searched_payload_info_ptr->addr_ptr, src_addr_ptr->addr_len)) && (searched_payload_info_ptr->port == src_addr_ptr->port)) { /* Check token */ if (token_ptr) { - if(!searched_payload_info_ptr->token_ptr || (token_len != searched_payload_info_ptr->token_len) || (memcmp(searched_payload_info_ptr->token_ptr, token_ptr, token_len))) { + if (!searched_payload_info_ptr->token_ptr || (token_len != searched_payload_info_ptr->token_len) || (memcmp(searched_payload_info_ptr->token_ptr, token_ptr, token_len))) { continue; } } else if (searched_payload_info_ptr->token_ptr) { @@ -1530,50 +1521,15 @@ static uint32_t sn_coap_protocol_linked_list_blockwise_payloads_get_len(struct c } /**************************************************************************//** - * \fn static void sn_coap_protocol_handle_blockwise_timout(struct coap_s *handle) + * \fn static void sn_coap_protocol_handle_blockwise_timeout(struct coap_s *handle) * * \brief Check incoming and outgoing blockwise messages for time out. * Remove timed out messages from lists. Notify application if * outgoing message times out. *****************************************************************************/ -static void sn_coap_protocol_handle_blockwise_timout(struct coap_s *handle) +static void sn_coap_protocol_handle_blockwise_timeout(struct coap_s *handle) { - /* Loop all outgoing blockwise messages */ - /* foreach_safe isn't sufficient because callback routine could remove messages. */ -rescan: - ns_list_foreach_safe(coap_blockwise_msg_s, removed_blocwise_msg_ptr, &handle->linked_list_blockwise_sent_msgs) { - if ((handle->system_time - removed_blocwise_msg_ptr->timestamp) > SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED) { - bool callback_called = false; - // Item must be removed from the list before calling the rx_callback function. - // Callback could actually clear the list and free the item and cause a use after free when callback returns. - ns_list_remove(&handle->linked_list_blockwise_sent_msgs, removed_blocwise_msg_ptr); - - /* * * * This messages has timed out, remove it from Linked list * * * */ - if( removed_blocwise_msg_ptr->coap_msg_ptr ){ - if (handle->sn_coap_rx_callback) { - /* Notify the application about the time out */ - removed_blocwise_msg_ptr->coap_msg_ptr->coap_status = COAP_STATUS_BUILDER_BLOCK_SENDING_FAILED; - removed_blocwise_msg_ptr->coap_msg_ptr->msg_id = removed_blocwise_msg_ptr->msg_id; - sn_coap_protocol_delete_retransmission(handle, removed_blocwise_msg_ptr->msg_id); - handle->sn_coap_rx_callback(removed_blocwise_msg_ptr->coap_msg_ptr, NULL, removed_blocwise_msg_ptr->param); - callback_called = true; - } - handle->sn_coap_protocol_free(removed_blocwise_msg_ptr->coap_msg_ptr->payload_ptr); - sn_coap_parser_release_allocated_coap_msg_mem(handle, removed_blocwise_msg_ptr->coap_msg_ptr); - } - - handle->sn_coap_protocol_free(removed_blocwise_msg_ptr); - - if (callback_called) { - /* Callback routine could have wiped the list already */ - /* Be super cautious and rescan from the start */ - goto rescan; - } - } - } - - /* Loop all incoming Blockwise messages */ ns_list_foreach_safe(coap_blockwise_payload_s, removed_blocwise_payload_ptr, &handle->linked_list_blockwise_received_payloads) { if ((handle->system_time - removed_blocwise_payload_ptr->timestamp) > SN_COAP_BLOCKWISE_MAX_TIME_DATA_STORED) { @@ -1599,7 +1555,7 @@ rescan: * \return pointer to allocated struct *****************************************************************************/ -coap_send_msg_s *sn_coap_protocol_allocate_mem_for_msg(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint16_t packet_data_len) +coap_send_msg_s *sn_coap_protocol_allocate_mem_for_msg(struct coap_s *handle, sn_nsdl_addr_s *dst_addr_ptr, uint_fast16_t packet_data_len) { coap_send_msg_s *msg_ptr = sn_coap_protocol_calloc(handle, sizeof(coap_send_msg_s)); @@ -1613,7 +1569,7 @@ coap_send_msg_s *sn_coap_protocol_allocate_mem_for_msg(struct coap_s *handle, sn msg_ptr->send_msg_ptr.dst_addr_ptr.addr_ptr = sn_coap_protocol_calloc(handle, dst_addr_ptr->addr_len); if ((msg_ptr->send_msg_ptr.dst_addr_ptr.addr_ptr == NULL) || - (msg_ptr->send_msg_ptr.packet_ptr == NULL)) { + (msg_ptr->send_msg_ptr.packet_ptr == NULL)) { sn_coap_protocol_release_allocated_send_msg_mem(handle, msg_ptr); return 0; @@ -1650,9 +1606,9 @@ static void sn_coap_protocol_release_allocated_send_msg_mem(struct coap_s *handl * * \param const coap_send_msg_list_t *linked_list_ptr pointer to linked list *****************************************************************************/ -static uint16_t sn_coap_count_linked_list_size(const coap_send_msg_list_t *linked_list_ptr) +static uint_fast16_t sn_coap_count_linked_list_size(const coap_send_msg_list_t *linked_list_ptr) { - uint16_t total_size = 0; + uint_fast16_t total_size = 0; ns_list_foreach(coap_send_msg_s, stored_msg_ptr, linked_list_ptr) { total_size += stored_msg_ptr->send_msg_ptr.packet_len; @@ -1665,7 +1621,7 @@ static uint16_t sn_coap_count_linked_list_size(const coap_send_msg_list_t *linke #if SN_COAP_BLOCKWISE_ENABLED || SN_COAP_MAX_BLOCKWISE_PAYLOAD_SIZE -static coap_blockwise_msg_s* search_sent_blockwise_message(struct coap_s *handle, uint16_t msg_id) +static coap_blockwise_msg_s *search_sent_blockwise_message(struct coap_s *handle, uint16_t msg_id) { ns_list_foreach(coap_blockwise_msg_s, tmp, &handle->linked_list_blockwise_sent_msgs) { if (tmp->coap_msg_ptr && tmp->coap_msg_ptr->msg_id == msg_id) { @@ -1711,12 +1667,11 @@ void sn_coap_protocol_block_remove(struct coap_s *handle, sn_nsdl_addr_s *source } /* Check the payload */ - if(payload_length != stored_payload_info_ptr->payload_len){ + if (payload_length != stored_payload_info_ptr->payload_len) { continue; } - if(!memcmp(stored_payload_info_ptr->payload_ptr, payload, stored_payload_info_ptr->payload_len)) - { + if (!memcmp(stored_payload_info_ptr->payload_ptr, payload, stored_payload_info_ptr->payload_len)) { /* Everything matches, remove and return. */ sn_coap_protocol_linked_list_blockwise_payload_remove(handle, stored_payload_info_ptr); return; @@ -1754,11 +1709,11 @@ static coap_blockwise_msg_s *sn_coap_stored_blockwise_msg_get(struct coap_s *han * \param *received_coap_msg_ptr pointer to parsed CoAP message structure *****************************************************************************/ -static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn_nsdl_addr_s *src_addr_ptr, sn_coap_hdr_s *received_coap_msg_ptr, void *param) +static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn_nsdl_addr_s *src_addr_ptr, sn_coap_hdr_s *received_coap_msg_ptr, void *param, bool *keep_in_resend_queue) { sn_coap_hdr_s *src_coap_blockwise_ack_msg_ptr = NULL; uint16_t dst_packed_data_needed_mem = 0; - uint8_t *dst_ack_packet_data_ptr = NULL; + uint8_t *restrict dst_ack_packet_data_ptr = NULL; uint8_t block_temp = 0; uint16_t original_payload_len = 0; @@ -1768,27 +1723,29 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn // Blocked request sending, received ACK, sending next block.. if (received_coap_msg_ptr->options_list_ptr->block1 != COAP_OPTION_BLOCK_NONE) { if (received_coap_msg_ptr->msg_code > COAP_MSG_CODE_REQUEST_DELETE) { - if (received_coap_msg_ptr->options_list_ptr->block1 & 0x08) { - coap_blockwise_msg_s *stored_blockwise_msg_temp_ptr; - /* Get */ - stored_blockwise_msg_temp_ptr = search_sent_blockwise_message(handle, received_coap_msg_ptr->msg_id); + coap_blockwise_msg_s *stored_blockwise_msg_temp_ptr; + stored_blockwise_msg_temp_ptr = search_sent_blockwise_message(handle, received_coap_msg_ptr->msg_id); + + if (received_coap_msg_ptr->options_list_ptr->block1 & 0x08) { + received_coap_msg_ptr->coap_status = COAP_STATUS_PARSER_BLOCKWISE_ACK; if (stored_blockwise_msg_temp_ptr) { /* Build response message */ - uint16_t block_size; + uint_fast16_t block_size; uint32_t block_number; + uint32_t req_block_number; + + src_coap_blockwise_ack_msg_ptr = stored_blockwise_msg_temp_ptr->coap_msg_ptr; /* Get block option parameters from received message */ block_number = received_coap_msg_ptr->options_list_ptr->block1 >> 4; block_temp = received_coap_msg_ptr->options_list_ptr->block1 & 0x07; - block_size = 1u << (block_temp + 4); - - /* Build next block message */ - src_coap_blockwise_ack_msg_ptr = stored_blockwise_msg_temp_ptr->coap_msg_ptr; + block_size = 16u << block_temp; if (src_coap_blockwise_ack_msg_ptr->options_list_ptr) { + req_block_number = src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 >> 4; src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 = COAP_OPTION_BLOCK_NONE; // Do not clear block2 as it might have been set in the original request to request // specific size blocks @@ -1797,71 +1754,89 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn tr_error("sn_coap_handle_blockwise_message - (send block1) failed to allocate ack message!"); return 0; } + + // pass through to send a next request + req_block_number = block_number; } - block_number++; - src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 = (block_number << 4) | block_temp; + // Make sure that block number is the one we requested. If it's the old one just ignore it and wait for next response. + if (req_block_number == block_number) { - original_payload_len = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len; - original_payload_ptr = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_ptr; + /* Build next block message */ + block_number++; + src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 = (block_number << 4) | block_temp; - if ((block_size * (block_number + 1)) > stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len) { - src_coap_blockwise_ack_msg_ptr->payload_len = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len - (block_size * (block_number)); - src_coap_blockwise_ack_msg_ptr->payload_ptr = src_coap_blockwise_ack_msg_ptr->payload_ptr + (block_size * block_number); - } + original_payload_len = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len; + original_payload_ptr = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_ptr; - /* Not last block */ - else { - /* set more - bit */ - src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 |= 0x08; - src_coap_blockwise_ack_msg_ptr->payload_len = block_size; - src_coap_blockwise_ack_msg_ptr->payload_ptr = src_coap_blockwise_ack_msg_ptr->payload_ptr + (block_size * block_number); - } + if ((block_size * (block_number + 1)) > stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len) { + src_coap_blockwise_ack_msg_ptr->payload_len = stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len - (block_size * (block_number)); + src_coap_blockwise_ack_msg_ptr->payload_ptr = src_coap_blockwise_ack_msg_ptr->payload_ptr + (block_size * block_number); + } - /* Build and send block message */ - dst_packed_data_needed_mem = sn_coap_builder_calc_needed_packet_data_size_2(src_coap_blockwise_ack_msg_ptr, handle->sn_coap_block_data_size); + /* Not last block */ + else { + /* set more - bit */ + src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 |= 0x08; + src_coap_blockwise_ack_msg_ptr->payload_len = block_size; + src_coap_blockwise_ack_msg_ptr->payload_ptr = src_coap_blockwise_ack_msg_ptr->payload_ptr + (block_size * block_number); + } - dst_ack_packet_data_ptr = handle->sn_coap_protocol_malloc(dst_packed_data_needed_mem); - if (!dst_ack_packet_data_ptr) { - tr_error("sn_coap_handle_blockwise_message - (send block1) failed to allocate ack message!"); - handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr->options_list_ptr); - handle->sn_coap_protocol_free(original_payload_ptr); - handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr); - stored_blockwise_msg_temp_ptr->coap_msg_ptr = NULL; - return NULL; - } - src_coap_blockwise_ack_msg_ptr->msg_id = get_new_message_id(); + /* Build and send block message */ + dst_packed_data_needed_mem = sn_coap_builder_calc_needed_packet_data_size_2(src_coap_blockwise_ack_msg_ptr, handle->sn_coap_block_data_size); - sn_coap_builder_2(dst_ack_packet_data_ptr, src_coap_blockwise_ack_msg_ptr, handle->sn_coap_block_data_size); + dst_ack_packet_data_ptr = handle->sn_coap_protocol_malloc(dst_packed_data_needed_mem); + if (!dst_ack_packet_data_ptr) { + tr_error("sn_coap_handle_blockwise_message - (send block1) failed to allocate ack message!"); + handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr->options_list_ptr); + handle->sn_coap_protocol_free(original_payload_ptr); + handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr); + stored_blockwise_msg_temp_ptr->coap_msg_ptr = NULL; + return NULL; + } + src_coap_blockwise_ack_msg_ptr->msg_id = get_new_message_id(); - handle->sn_coap_tx_callback(dst_ack_packet_data_ptr, dst_packed_data_needed_mem, src_addr_ptr, param); + sn_coap_builder_2(dst_ack_packet_data_ptr, src_coap_blockwise_ack_msg_ptr, handle->sn_coap_block_data_size); + + handle->sn_coap_tx_callback(dst_ack_packet_data_ptr, dst_packed_data_needed_mem, src_addr_ptr, param); #if ENABLE_RESENDINGS - uint32_t resend_time = sn_coap_calculate_new_resend_time(handle->system_time, handle->sn_coap_resending_intervall, 0); - if (src_coap_blockwise_ack_msg_ptr->msg_type == COAP_MSG_TYPE_CONFIRMABLE) { - sn_coap_protocol_linked_list_send_msg_store(handle, src_addr_ptr, - dst_packed_data_needed_mem, - dst_ack_packet_data_ptr, - resend_time, param); - } + uint32_t resend_time = sn_coap_calculate_new_resend_time(handle->system_time, handle->sn_coap_resending_intervall, 0); + + if (src_coap_blockwise_ack_msg_ptr->msg_type == COAP_MSG_TYPE_CONFIRMABLE) { + sn_coap_protocol_linked_list_send_msg_store(handle, src_addr_ptr, + dst_packed_data_needed_mem, + dst_ack_packet_data_ptr, + resend_time, param); + } #endif - handle->sn_coap_protocol_free(dst_ack_packet_data_ptr); - dst_ack_packet_data_ptr = 0; + handle->sn_coap_protocol_free(dst_ack_packet_data_ptr); + dst_ack_packet_data_ptr = 0; - stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len = original_payload_len; - stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_ptr = original_payload_ptr; + stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_len = original_payload_len; + stored_blockwise_msg_temp_ptr->coap_msg_ptr->payload_ptr = original_payload_ptr; - received_coap_msg_ptr->coap_status = COAP_STATUS_PARSER_BLOCKWISE_ACK; - - // Remove original message from the list when last block has been sent. - if (!((src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1) & 0x08)) { - sn_coap_protocol_remove_sent_blockwise_message(handle, stored_blockwise_msg_temp_ptr->coap_msg_ptr->msg_id); + // Remove original message from the list when last block has been sent. + if (!((src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1) & 0x08)) { + sn_coap_protocol_remove_sent_blockwise_message(handle, stored_blockwise_msg_temp_ptr->coap_msg_ptr->msg_id); + } + } else { + tr_warn("sn_coap_handle_blockwise_message - blocks not in order, requested: %"PRIu32" received: %"PRIu32" --> ignore", req_block_number, block_number); + src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 = (req_block_number << 4) | block_temp; + *keep_in_resend_queue = true; } } } else { - // XXX what was this trying to free? - received_coap_msg_ptr->coap_status = COAP_STATUS_OK; + if (stored_blockwise_msg_temp_ptr) { + // Last block received but some blocks are not yet sent. Ignore it and wait for next response. + tr_warn("sn_coap_handle_blockwise_message - last block received but some blocks are missing --> ignore"); + received_coap_msg_ptr->coap_status = COAP_STATUS_PARSER_BLOCKWISE_ACK; + *keep_in_resend_queue = true; + } else { + // XXX what was this trying to free? + received_coap_msg_ptr->coap_status = COAP_STATUS_OK; + } } } @@ -1876,11 +1851,11 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn bool blocks_in_order = true; if (block_number > 0 && - !sn_coap_protocol_linked_list_blockwise_payload_search_compare_block_number(handle, - src_addr_ptr, - received_coap_msg_ptr->token_ptr, - received_coap_msg_ptr->token_len, - block_number - 1)) { + !sn_coap_protocol_linked_list_blockwise_payload_search_compare_block_number(handle, + src_addr_ptr, + received_coap_msg_ptr->token_ptr, + received_coap_msg_ptr->token_len, + block_number - 1)) { blocks_in_order = false; } @@ -1912,24 +1887,23 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn // Include maximum size that stack can handle into response tr_info("sn_coap_handle_blockwise_message - (recv block1) entity too large"); src_coap_blockwise_ack_msg_ptr->msg_code = COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE; - } - else { + } else { src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 = received_coap_msg_ptr->options_list_ptr->block1; src_coap_blockwise_ack_msg_ptr->msg_type = COAP_MSG_TYPE_ACKNOWLEDGEMENT; /* Check block size */ block_temp = (src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 & 0x07); - uint16_t block_size = 1u << (block_temp + 4); + uint_fast16_t block_size = 16u << block_temp; if (block_size > handle->sn_coap_block_data_size) { - // Include maximum size that stack can handle into response + // Include maximum size that stack can handle into response tr_info("sn_coap_handle_blockwise_message - (recv block1) entity too large"); - src_coap_blockwise_ack_msg_ptr->msg_code = COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE; - src_coap_blockwise_ack_msg_ptr->options_list_ptr->size1 = handle->sn_coap_block_data_size; + src_coap_blockwise_ack_msg_ptr->msg_code = COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE; + src_coap_blockwise_ack_msg_ptr->options_list_ptr->size1 = handle->sn_coap_block_data_size; } if (block_temp > sn_coap_convert_block_size(handle->sn_coap_block_data_size)) { - src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 &= 0xFFFFF8; + src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 &= 0xFFFFFFF8; src_coap_blockwise_ack_msg_ptr->options_list_ptr->block1 |= sn_coap_convert_block_size(handle->sn_coap_block_data_size); } } @@ -1968,7 +1942,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn #endif // Store only in success case if (src_coap_blockwise_ack_msg_ptr->msg_code != COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_INCOMPLETE && - src_coap_blockwise_ack_msg_ptr->msg_code != COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE) { + src_coap_blockwise_ack_msg_ptr->msg_code != COAP_MSG_CODE_RESPONSE_REQUEST_ENTITY_TOO_LARGE) { uint16_t block_size = 1u << ((received_coap_msg_ptr->options_list_ptr->block1 & 0x07) + 4); sn_coap_protocol_linked_list_blockwise_payload_store(handle, src_addr_ptr, @@ -2136,9 +2110,9 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn #if ENABLE_RESENDINGS uint32_t resend_time = sn_coap_calculate_new_resend_time(handle->system_time, handle->sn_coap_resending_intervall, 0); sn_coap_protocol_linked_list_send_msg_store(handle, src_addr_ptr, - dst_packed_data_needed_mem, - dst_ack_packet_data_ptr, - resend_time, param); + dst_packed_data_needed_mem, + dst_ack_packet_data_ptr, + resend_time, param); #endif handle->sn_coap_protocol_free(dst_ack_packet_data_ptr); dst_ack_packet_data_ptr = 0; @@ -2175,7 +2149,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn block_temp = received_coap_msg_ptr->options_list_ptr->block2 & 0x07; /* Resolve block parameters */ - const uint16_t block_size = 1u << (block_temp + 4); + const uint_fast16_t block_size = 16u << block_temp; const uint32_t block_number = received_coap_msg_ptr->options_list_ptr->block2 >> 4; @@ -2220,7 +2194,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn * This is needed only in case of notification message. */ if (src_coap_blockwise_ack_msg_ptr->options_list_ptr && - src_coap_blockwise_ack_msg_ptr->options_list_ptr->observe != COAP_OBSERVE_NONE) { + src_coap_blockwise_ack_msg_ptr->options_list_ptr->observe != COAP_OBSERVE_NONE) { if (src_coap_blockwise_ack_msg_ptr->token_ptr) { handle->sn_coap_protocol_free(src_coap_blockwise_ack_msg_ptr->token_ptr); if (received_coap_msg_ptr->token_len) { @@ -2228,8 +2202,7 @@ static sn_coap_hdr_s *sn_coap_handle_blockwise_message(struct coap_s *handle, sn if (src_coap_blockwise_ack_msg_ptr->token_ptr) { src_coap_blockwise_ack_msg_ptr->token_len = received_coap_msg_ptr->token_len; } - } - else { + } else { src_coap_blockwise_ack_msg_ptr->token_ptr = NULL; src_coap_blockwise_ack_msg_ptr->token_len = 0; } @@ -2318,28 +2291,17 @@ static bool sn_coap_handle_last_blockwise(struct coap_s *handle, const sn_nsdl_a int8_t sn_coap_convert_block_size(uint16_t block_size) { - if (block_size == 16) { - return 0; - } else if (block_size == 32) { - return 1; - } else if (block_size == 64) { - return 2; - } else if (block_size == 128) { - return 3; - } else if (block_size == 256) { - return 4; - } else if (block_size == 512) { - return 5; - } else if (block_size == 1024) { - return 6; - } else { - return 0; + for (int n = 0; n <= 6; n++) { + if (block_size == (16 << n)) { + return n; + } } + return -1; } -static sn_coap_hdr_s *sn_coap_protocol_copy_header(struct coap_s *handle, const sn_coap_hdr_s *source_header_ptr) +static sn_coap_hdr_s *sn_coap_protocol_copy_header(struct coap_s *restrict handle, const sn_coap_hdr_s *restrict source_header_ptr) { - sn_coap_hdr_s *destination_header_ptr; + sn_coap_hdr_s *restrict destination_header_ptr; destination_header_ptr = sn_coap_parser_alloc_message(handle); if (!destination_header_ptr) { @@ -2382,8 +2344,8 @@ static sn_coap_hdr_s *sn_coap_protocol_copy_header(struct coap_s *handle, const return 0; } - const sn_coap_options_list_s *source_options_list_ptr = source_header_ptr->options_list_ptr; - sn_coap_options_list_s *destination_options_list_ptr = destination_header_ptr->options_list_ptr; + const sn_coap_options_list_s *restrict source_options_list_ptr = source_header_ptr->options_list_ptr; + sn_coap_options_list_s *restrict destination_options_list_ptr = destination_header_ptr->options_list_ptr; destination_options_list_ptr->max_age = source_options_list_ptr->max_age; @@ -2464,11 +2426,11 @@ static sn_coap_hdr_s *sn_coap_protocol_copy_header(struct coap_s *handle, const static bool sn_coap_protocol_update_duplicate_package_data(const struct coap_s *handle, const sn_nsdl_addr_s *dst_addr_ptr, const sn_coap_hdr_s *coap_msg_ptr, - const int16_t data_size, + const int_fast16_t data_size, const uint8_t *dst_packet_data_ptr) { if (coap_msg_ptr->msg_type == COAP_MSG_TYPE_ACKNOWLEDGEMENT && - handle->sn_coap_duplication_buffer_size != 0) { + handle->sn_coap_duplication_buffer_size != 0) { return sn_coap_protocol_update_duplicate_package_data_all(handle, dst_addr_ptr, coap_msg_ptr, data_size, dst_packet_data_ptr); } return true; @@ -2477,10 +2439,10 @@ static bool sn_coap_protocol_update_duplicate_package_data(const struct coap_s * static bool sn_coap_protocol_update_duplicate_package_data_all(const struct coap_s *handle, const sn_nsdl_addr_s *dst_addr_ptr, const sn_coap_hdr_s *coap_msg_ptr, - const int16_t data_size, + const int_fast16_t data_size, const uint8_t *dst_packet_data_ptr) { - coap_duplication_info_s* info = sn_coap_protocol_linked_list_duplication_info_search(handle, + coap_duplication_info_s *info = sn_coap_protocol_linked_list_duplication_info_search(handle, dst_addr_ptr, coap_msg_ptr->msg_id); @@ -2500,7 +2462,7 @@ static bool sn_coap_protocol_update_duplicate_package_data_all(const struct coap } #endif -void *sn_coap_protocol_malloc_copy(struct coap_s *handle, const void *source, uint16_t length) +void *sn_coap_protocol_malloc_copy(struct coap_s *handle, const void *source, uint_fast16_t length) { void *dest = handle->sn_coap_protocol_malloc(length); @@ -2515,7 +2477,7 @@ void *sn_coap_protocol_malloc_copy(struct coap_s *handle, const void *source, ui * are, but that would require the client to fill one up, as a wrapper filled from this * class would need access to the handle itself. */ -void *sn_coap_protocol_calloc(struct coap_s *handle, uint16_t length) +void *sn_coap_protocol_calloc(struct coap_s *handle, uint_fast16_t length) { void *result = handle->sn_coap_protocol_malloc(length); @@ -2525,7 +2487,7 @@ void *sn_coap_protocol_calloc(struct coap_s *handle, uint16_t length) return result; } -static bool compare_port(const sn_nsdl_addr_s* left, const sn_nsdl_addr_s* right) +static bool compare_port(const sn_nsdl_addr_s *left, const sn_nsdl_addr_s *right) { bool match = false; if (left->port == right->port) { diff --git a/connectivity/lorawan/CMakeLists.txt b/connectivity/lorawan/CMakeLists.txt index 743a0ff9ae..941b01e04e 100644 --- a/connectivity/lorawan/CMakeLists.txt +++ b/connectivity/lorawan/CMakeLists.txt @@ -1,6 +1,10 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) + add_subdirectory(tests/UNITTESTS) +endif() + add_subdirectory(lorastack) add_subdirectory(system) diff --git a/connectivity/lorawan/tests/TESTS/lorawan/loraradio/main.cpp b/connectivity/lorawan/tests/TESTS/lorawan/loraradio/main.cpp index 54b3b73bd7..f1bdd7c0dd 100644 --- a/connectivity/lorawan/tests/TESTS/lorawan/loraradio/main.cpp +++ b/connectivity/lorawan/tests/TESTS/lorawan/loraradio/main.cpp @@ -15,17 +15,6 @@ * limitations under the License. */ -#include "utest.h" -#include "unity.h" -#include "greentea-client/test_env.h" - -#include "Semaphore.h" - -#include "mbed_trace.h" -#define TRACE_GROUP "RTST" - -#include "LoRaRadio.h" - #if COMPONENT_SX1272 #include "SX1272_LoRaRadio.h" #elif COMPONENT_SX1276 @@ -38,6 +27,17 @@ #error [NOT_SUPPORTED] Lora radio is not configured #endif +#include "utest.h" +#include "unity.h" +#include "greentea-client/test_env.h" + +#include "Semaphore.h" + +#include "mbed_trace.h" +#define TRACE_GROUP "RTST" + +#include "LoRaRadio.h" + using namespace utest::v1; using namespace mbed; diff --git a/connectivity/lorawan/tests/UNITTESTS/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/CMakeLists.txt new file mode 100644 index 0000000000..9efa3167f2 --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(features) diff --git a/connectivity/lorawan/tests/UNITTESTS/features/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/CMakeLists.txt new file mode 100644 index 0000000000..11270973b3 --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(lorawan) diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/CMakeLists.txt new file mode 100644 index 0000000000..68ab2ebc2b --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/CMakeLists.txt @@ -0,0 +1,20 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(lorawaninterface) +add_subdirectory(loraphyus915) +add_subdirectory(loraphykr920) +add_subdirectory(loraphyin865) +add_subdirectory(loraphyeu868) +add_subdirectory(loraphyeu433) +add_subdirectory(loraphycn779) +add_subdirectory(loraphycn470) +add_subdirectory(loraphyau915) +add_subdirectory(loraphyas923) +add_subdirectory(loraphy) +add_subdirectory(loramaccrypto) +add_subdirectory(loramaccommand) +add_subdirectory(loramacchannelplan) +add_subdirectory(loramac) +add_subdirectory(lorawantimer) +add_subdirectory(lorawanstack) diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramac/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramac/CMakeLists.txt new file mode 100644 index 0000000000..471c436070 --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramac/CMakeLists.txt @@ -0,0 +1,44 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loramac-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_ADR_ON=true + MBED_CONF_LORA_PUBLIC_NETWORK=true + MBED_CONF_LORA_NB_TRIALS=2 + MBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 + MBED_CONF_LORA_DUTY_CYCLE_ON=true + MBED_CONF_LORA_MAX_SYS_RX_ERROR=10 + MBED_CONF_LORA_TX_MAX_SIZE=255 + MBED_CONF_LORA_DEVICE_ADDRESS=0x00000000 +) + +target_compile_options(${TEST_NAME} + PRIVATE + "-DMBED_CONF_LORA_NWKSKEY={0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}" + "-DMBED_CONF_LORA_NWKSKEY={0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}" + "-DMBED_CONF_LORA_APPSKEY={0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}" + "-DMBED_CONF_LORA_APPSKEY={0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}" +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/mac/LoRaMac.cpp + Test_LoRaMac.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramac/Test_LoRaMac.cpp b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramac/Test_LoRaMac.cpp index 8edee42f0c..4e5b540e61 100644 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramac/Test_LoRaMac.cpp +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramac/Test_LoRaMac.cpp @@ -537,7 +537,7 @@ TEST_F(Test_LoRaMac, post_process_mlme_ind) uint8_t batt_cb() { - + return 100; } TEST_F(Test_LoRaMac, set_batterylevel_callback) diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramac/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramac/unittest.cmake deleted file mode 100644 index f1044ede03..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramac/unittest.cmake +++ /dev/null @@ -1,63 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaMac") - -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/mac/LoRaMac.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/mac -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaMac.cpp - stubs/LoRaPHY_stub.cpp - stubs/LoRaWANStack_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/LoRaMacCrypto_stub.cpp - stubs/LoRaMacChannelPlan_stub.cpp - stubs/LoRaWANTimer_stub.cpp - stubs/LoRaMacCommand_stub.cpp - stubs/EventQueue_stub.cpp - stubs/Mutex_stub.cpp -) - -set(unittest-test-flags - -DMBED_CONF_LORA_ADR_ON=true - -DMBED_CONF_LORA_PUBLIC_NETWORK=true - -DMBED_CONF_LORA_NB_TRIALS=2 - -DMBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 - -DMBED_CONF_LORA_DUTY_CYCLE_ON=true - -DMBED_CONF_LORA_MAX_SYS_RX_ERROR=10 - -DMBED_CONF_LORA_TX_MAX_SIZE=255 - -DMBED_CONF_LORA_DEVICE_ADDRESS=0x00000000 -) - -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBED_CONF_LORA_NWKSKEY=\"{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\"") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBED_CONF_LORA_NWKSKEY=\"{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\"") - -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBED_CONF_LORA_APPSKEY=\"{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\"") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBED_CONF_LORA_APPSKEY=\"{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}\"") - - diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramacchannelplan/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramacchannelplan/CMakeLists.txt new file mode 100644 index 0000000000..63928bfae7 --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramacchannelplan/CMakeLists.txt @@ -0,0 +1,29 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loramac-channel-plan-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_TX_MAX_SIZE=255 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/mac/LoRaMacChannelPlan.cpp + Test_LoRaMacChannelPlan.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramaccommand/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramaccommand/CMakeLists.txt new file mode 100644 index 0000000000..9a93feba3e --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramaccommand/CMakeLists.txt @@ -0,0 +1,29 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loramac-command-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_TX_MAX_SIZE=255 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/mac/LoRaMacCommand.cpp + Test_LoRaMacCommand.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramaccrypto/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramaccrypto/CMakeLists.txt new file mode 100644 index 0000000000..4ab65c6569 --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramaccrypto/CMakeLists.txt @@ -0,0 +1,29 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loramac-crypto-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_TX_MAX_SIZE=255 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/mac/LoRaMacCrypto.cpp + Test_LoRaMacCrypto.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramaccrypto/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramaccrypto/unittest.cmake deleted file mode 100644 index 19a752fe67..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramaccrypto/unittest.cmake +++ /dev/null @@ -1,45 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaMacCrypto") - -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/mac/LoRaMacCrypto.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/mac -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaMacCrypto.cpp - stubs/cipher_stub.c - stubs/aes_stub.c - stubs/cmac_stub.c - stubs/mbed_assert_stub.cpp - ../connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c - -) - -set(unittest-test-flags - -DMBED_CONF_LORA_TX_MAX_SIZE=255 - ) diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphy/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphy/CMakeLists.txt new file mode 100644 index 0000000000..f4dae3d71e --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphy/CMakeLists.txt @@ -0,0 +1,33 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loraphy-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_WAKEUP_TIME=5 + MBED_CONF_LORA_DUTY_CYCLE_ON_JOIN=true + MBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 + MBED_CONF_LORA_TX_MAX_SIZE=255 + MBED_CONF_LORA_NB_TRIALS=2 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/phy/LoRaPHY.cpp + Test_LoRaPHY.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphy/Test_LoRaPHY.cpp b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphy/Test_LoRaPHY.cpp index 6220649ec5..3664d40cf0 100644 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphy/Test_LoRaPHY.cpp +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphy/Test_LoRaPHY.cpp @@ -88,6 +88,7 @@ public: virtual uint32_t random(void) { + return 4; }; virtual uint8_t get_status(void) @@ -105,6 +106,7 @@ public: virtual uint32_t time_on_air(radio_modems_t modem, uint8_t pkt_len) { + return 0; }; virtual bool perform_carrier_sense(radio_modems_t modem, diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphy/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphy/unittest.cmake deleted file mode 100644 index 55d4df04f2..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphy/unittest.cmake +++ /dev/null @@ -1,46 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaPHY") - -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/phy/LoRaPHY.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/phy -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaPHY.cpp - stubs/LoRaWANTimer_stub.cpp - stubs/mbed_assert_stub.cpp -) - -set(unittest-test-flags - -DMBED_CONF_LORA_WAKEUP_TIME=5 - -DMBED_CONF_LORA_DUTY_CYCLE_ON_JOIN=true - -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 - -DMBED_CONF_LORA_TX_MAX_SIZE=255 - -DMBED_CONF_LORA_NB_TRIALS=2 -) - diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyas923/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyas923/CMakeLists.txt new file mode 100644 index 0000000000..aeff45c056 --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyas923/CMakeLists.txt @@ -0,0 +1,31 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loraphy-as923-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 + MBED_CONF_LORA_TX_MAX_SIZE=255 + MBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/phy/LoRaPHYAS923.cpp + Test_LoRaPHYAS923.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyas923/Test_LoRaPHYAS923.cpp b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyas923/Test_LoRaPHYAS923.cpp index 47e9b76212..8b4054c71e 100644 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyas923/Test_LoRaPHYAS923.cpp +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyas923/Test_LoRaPHYAS923.cpp @@ -71,6 +71,7 @@ public: virtual uint32_t random(void) { + return 4; }; virtual uint8_t get_status(void) @@ -88,6 +89,7 @@ public: virtual uint32_t time_on_air(radio_modems_t modem, uint8_t pkt_len) { + return 0; }; virtual bool perform_carrier_sense(radio_modems_t modem, diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyas923/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyas923/unittest.cmake deleted file mode 100644 index 27fe307244..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyas923/unittest.cmake +++ /dev/null @@ -1,46 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaPHYAS923") - -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/phy/LoRaPHYAS923.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/phy -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaPHYAS923.cpp - stubs/LoRaPHY_stub.cpp - stubs/LoRaWANTimer_stub.cpp - stubs/mbed_assert_stub.cpp - -) - -set(unittest-test-flags - -DMBED_CONF_LORA_TX_MAX_SIZE=255 - -DMBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 - -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 -) - diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyau915/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyau915/CMakeLists.txt new file mode 100644 index 0000000000..479491adb6 --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyau915/CMakeLists.txt @@ -0,0 +1,37 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loraphy-au915-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 + MBED_CONF_LORA_TX_MAX_SIZE=255 + MBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 +) + +target_compile_options(${TEST_NAME} + PRIVATE + "-DMBED_CONF_LORA_FSB_MASK={0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}" + "-DMBED_CONF_LORA_FSB_MASK={0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}" +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/phy/LoRaPHYAU915.cpp + Test_LoRaPHYAU915.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyau915/Test_LoRaPHYAU915.cpp b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyau915/Test_LoRaPHYAU915.cpp index 93ff3d29e0..36bec40536 100644 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyau915/Test_LoRaPHYAU915.cpp +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyau915/Test_LoRaPHYAU915.cpp @@ -71,6 +71,7 @@ public: virtual uint32_t random(void) { + return 4; }; virtual uint8_t get_status(void) @@ -88,6 +89,7 @@ public: virtual uint32_t time_on_air(radio_modems_t modem, uint8_t pkt_len) { + return 0; }; virtual bool perform_carrier_sense(radio_modems_t modem, diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyau915/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyau915/unittest.cmake deleted file mode 100644 index 713840c88e..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyau915/unittest.cmake +++ /dev/null @@ -1,50 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaPHYAU915") - -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/phy/LoRaPHYAU915.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/phy -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaPHYAU915.cpp - stubs/LoRaPHY_stub.cpp - stubs/LoRaWANTimer_stub.cpp - stubs/mbed_assert_stub.cpp - -) - -set(unittest-test-flags - -DMBED_CONF_LORA_TX_MAX_SIZE=255 - -DMBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 - -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 -) - -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBED_CONF_LORA_FSB_MASK=\"{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}\"") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBED_CONF_LORA_FSB_MASK=\"{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}\"") - - diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn470/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn470/CMakeLists.txt new file mode 100644 index 0000000000..e67ef1c9ad --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn470/CMakeLists.txt @@ -0,0 +1,37 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loraphy-cn470-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 + MBED_CONF_LORA_TX_MAX_SIZE=255 + MBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 +) + +target_compile_options(${TEST_NAME} + PRIVATE + "-DMBED_CONF_LORA_FSB_MASK_CHINA={0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}" + "-DMBED_CONF_LORA_FSB_MASK_CHINA={0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}" +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/phy/LoRaPHYCN470.cpp + Test_LoRaPHYCN470.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn470/Test_LoRaPHYCN470.cpp b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn470/Test_LoRaPHYCN470.cpp index 20e8fc3be2..967a855cdd 100644 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn470/Test_LoRaPHYCN470.cpp +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn470/Test_LoRaPHYCN470.cpp @@ -71,6 +71,7 @@ public: virtual uint32_t random(void) { + return 4; }; virtual uint8_t get_status(void) @@ -88,6 +89,7 @@ public: virtual uint32_t time_on_air(radio_modems_t modem, uint8_t pkt_len) { + return 0; }; virtual bool perform_carrier_sense(radio_modems_t modem, diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn470/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn470/unittest.cmake deleted file mode 100644 index a67f0dff5c..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn470/unittest.cmake +++ /dev/null @@ -1,49 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaPHYCN470") - -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/phy/LoRaPHYCN470.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/phy -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaPHYCN470.cpp - stubs/LoRaPHY_stub.cpp - stubs/LoRaWANTimer_stub.cpp - stubs/mbed_assert_stub.cpp - -) - -set(unittest-test-flags - -DMBED_CONF_LORA_TX_MAX_SIZE=255 - -DMBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 - -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 -) - -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBED_CONF_LORA_FSB_MASK_CHINA=\"{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}\"") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBED_CONF_LORA_FSB_MASK_CHINA=\"{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}\"") - diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn779/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn779/CMakeLists.txt new file mode 100644 index 0000000000..7a59436f5c --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn779/CMakeLists.txt @@ -0,0 +1,31 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loraphy-cn779-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 + MBED_CONF_LORA_TX_MAX_SIZE=255 + MBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/phy/LoRaPHYCN779.cpp + Test_LoRaPHYCN779.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn779/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn779/unittest.cmake deleted file mode 100644 index 7d2fb8fab6..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphycn779/unittest.cmake +++ /dev/null @@ -1,47 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaPHYCN779") - -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/phy/LoRaPHYCN779.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/phy -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaPHYCN779.cpp - stubs/LoRaPHY_stub.cpp - stubs/mbed_assert_stub.cpp - -) - -set(unittest-test-flags - -DMBED_CONF_LORA_TX_MAX_SIZE=255 - -DMBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 - -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 -) - -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBED_CONF_LORA_FSB_MASK_CHINA=\"{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}\"") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBED_CONF_LORA_FSB_MASK_CHINA=\"{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}\"") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyeu433/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyeu433/CMakeLists.txt new file mode 100644 index 0000000000..913dae3979 --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyeu433/CMakeLists.txt @@ -0,0 +1,31 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loraphy-eu433-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 + MBED_CONF_LORA_TX_MAX_SIZE=255 + MBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/phy/LoRaPHYEU433.cpp + Test_LoRaPHYEU433.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyeu433/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyeu433/unittest.cmake deleted file mode 100644 index d4722e7a03..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyeu433/unittest.cmake +++ /dev/null @@ -1,45 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaPHYEU433") - -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/phy/LoRaPHYEU433.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/phy -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaPHYEU433.cpp - stubs/LoRaPHY_stub.cpp - stubs/mbed_assert_stub.cpp - -) - -set(unittest-test-flags - -DMBED_CONF_LORA_TX_MAX_SIZE=255 - -DMBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 - -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 -) - diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyeu868/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyeu868/CMakeLists.txt new file mode 100644 index 0000000000..febdec3391 --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyeu868/CMakeLists.txt @@ -0,0 +1,31 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loraphy-eu868-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 + MBED_CONF_LORA_TX_MAX_SIZE=255 + MBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/phy/LoRaPHYEU868.cpp + Test_LoRaPHYEU868.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyeu868/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyeu868/unittest.cmake deleted file mode 100644 index cc43f25687..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyeu868/unittest.cmake +++ /dev/null @@ -1,45 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaPHYEU868") - -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/phy/LoRaPHYEU868.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/phy -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaPHYEU868.cpp - stubs/LoRaPHY_stub.cpp - stubs/mbed_assert_stub.cpp - -) - -set(unittest-test-flags - -DMBED_CONF_LORA_TX_MAX_SIZE=255 - -DMBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 - -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 -) - diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyin865/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyin865/CMakeLists.txt new file mode 100644 index 0000000000..8fb2940e36 --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyin865/CMakeLists.txt @@ -0,0 +1,31 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loraphy-in865-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 + MBED_CONF_LORA_TX_MAX_SIZE=255 + MBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/phy/LoRaPHYIN865.cpp + Test_LoRaPHYIN865.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyin865/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyin865/unittest.cmake deleted file mode 100644 index be47422a46..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyin865/unittest.cmake +++ /dev/null @@ -1,45 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaPHYIN865") - -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/phy/LoRaPHYIN865.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/phy -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaPHYIN865.cpp - stubs/LoRaPHY_stub.cpp - stubs/mbed_assert_stub.cpp - -) - -set(unittest-test-flags - -DMBED_CONF_LORA_TX_MAX_SIZE=255 - -DMBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 - -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 -) - diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphykr920/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphykr920/CMakeLists.txt new file mode 100644 index 0000000000..be56ff856f --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphykr920/CMakeLists.txt @@ -0,0 +1,31 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loraphy-kr920-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 + MBED_CONF_LORA_TX_MAX_SIZE=255 + MBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/phy/LoRaPHYKR920.cpp + Test_LoRaPHYKR920.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphykr920/Test_LoRaPHYKR920.cpp b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphykr920/Test_LoRaPHYKR920.cpp index 5a170a1f29..c38ddcf06f 100644 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphykr920/Test_LoRaPHYKR920.cpp +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphykr920/Test_LoRaPHYKR920.cpp @@ -71,10 +71,12 @@ public: virtual uint32_t random(void) { + return 4; }; virtual uint8_t get_status(void) { + return 0; }; virtual void set_max_payload_length(radio_modems_t modem, uint8_t max) @@ -87,6 +89,7 @@ public: virtual uint32_t time_on_air(radio_modems_t modem, uint8_t pkt_len) { + return 0; }; virtual bool perform_carrier_sense(radio_modems_t modem, diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphykr920/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphykr920/unittest.cmake deleted file mode 100644 index e7ac20cfa6..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphykr920/unittest.cmake +++ /dev/null @@ -1,46 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaPHYKR920") - -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/phy/LoRaPHYKR920.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/phy -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaPHYKR920.cpp - stubs/LoRaPHY_stub.cpp - stubs/LoRaWANTimer_stub.cpp - stubs/mbed_assert_stub.cpp - -) - -set(unittest-test-flags - -DMBED_CONF_LORA_TX_MAX_SIZE=255 - -DMBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 - -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 -) - diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyus915/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyus915/CMakeLists.txt new file mode 100644 index 0000000000..3e94d6ee1b --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyus915/CMakeLists.txt @@ -0,0 +1,37 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-loraphy-us915-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 + MBED_CONF_LORA_TX_MAX_SIZE=255 + MBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 +) + +target_compile_options(${TEST_NAME} + PRIVATE + "-DMBED_CONF_LORA_FSB_MASK={0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}" + "-DMBED_CONF_LORA_FSB_MASK={0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}" +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/lorastack/phy/LoRaPHYUS915.cpp + Test_LoRaPHYUS915.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyus915/Test_LoRaPHYUS915.cpp b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyus915/Test_LoRaPHYUS915.cpp index 82d9e7b685..d367b22edc 100644 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyus915/Test_LoRaPHYUS915.cpp +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyus915/Test_LoRaPHYUS915.cpp @@ -71,6 +71,7 @@ public: virtual uint32_t random(void) { + return 4; }; virtual uint8_t get_status(void) @@ -88,6 +89,7 @@ public: virtual uint32_t time_on_air(radio_modems_t modem, uint8_t pkt_len) { + return 0; }; virtual bool perform_carrier_sense(radio_modems_t modem, diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyus915/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyus915/unittest.cmake deleted file mode 100644 index 722f4fcc58..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loraphyus915/unittest.cmake +++ /dev/null @@ -1,48 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaPHYUS915") - -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/phy/LoRaPHYUS915.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/phy -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaPHYUS915.cpp - stubs/LoRaPHY_stub.cpp - stubs/LoRaWANTimer_stub.cpp - stubs/mbed_assert_stub.cpp - -) - -set(unittest-test-flags - -DMBED_CONF_LORA_TX_MAX_SIZE=255 - -DMBED_CONF_LORA_DOWNLINK_PREAMBLE_LENGTH=5 - -DMBED_CONF_LORA_UPLINK_PREAMBLE_LENGTH=8 -) - -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBED_CONF_LORA_FSB_MASK=\"{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}\"") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBED_CONF_LORA_FSB_MASK=\"{0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0x00FF}\"") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawaninterface/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawaninterface/CMakeLists.txt new file mode 100644 index 0000000000..489cece0c1 --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawaninterface/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-lorawan-interface-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_PHY=EU868 + MBED_CONF_LORA_TX_MAX_SIZE=255 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/source/LoRaWANInterface.cpp + Test_LoRaWANInterface.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawaninterface/Test_LoRaWANInterface.cpp b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawaninterface/Test_LoRaWANInterface.cpp index f4506a815c..75dbb6c347 100644 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawaninterface/Test_LoRaWANInterface.cpp +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawaninterface/Test_LoRaWANInterface.cpp @@ -70,10 +70,12 @@ public: virtual uint32_t random(void) { + return 4; }; virtual uint8_t get_status(void) { + return 0; }; virtual void set_max_payload_length(radio_modems_t modem, uint8_t max) @@ -86,6 +88,7 @@ public: virtual uint32_t time_on_air(radio_modems_t modem, uint8_t pkt_len) { + return 0; }; virtual bool perform_carrier_sense(radio_modems_t modem, @@ -93,6 +96,7 @@ public: int16_t rssi_threshold, uint32_t max_carrier_sense_time) { + return true; }; virtual void start_cad(void) @@ -101,6 +105,7 @@ public: virtual bool check_rf_frequency(uint32_t frequency) { + return true; }; virtual void set_tx_continuous_wave(uint32_t freq, int8_t power, uint16_t time) diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawaninterface/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawaninterface/unittest.cmake deleted file mode 100644 index e6c0466293..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawaninterface/unittest.cmake +++ /dev/null @@ -1,53 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaWANInterface") - -# Source files -set(unittest-sources - ../connectivity/lorawan/source/LoRaWANInterface.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaWANInterface.cpp - stubs/LoRaPHY_stub.cpp - stubs/LoRaWANStack_stub.cpp - stubs/LoRaMac_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/LoRaMacCrypto_stub.cpp - stubs/LoRaMacChannelPlan_stub.cpp - stubs/LoRaWANTimer_stub.cpp - stubs/LoRaMacCommand_stub.cpp - stubs/LoRaPHYEU868_stub.cpp - stubs/Mutex_stub.cpp -) - -set(unittest-test-flags - -DMBED_CONF_LORA_PHY=EU868 - -DMBED_CONF_LORA_TX_MAX_SIZE=255 -) - - - diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawanstack/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawanstack/CMakeLists.txt new file mode 100644 index 0000000000..3f678713c5 --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawanstack/CMakeLists.txt @@ -0,0 +1,31 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-lorawan-stack-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_LORA_OVER_THE_AIR_ACTIVATION=true + MBED_CONF_LORA_AUTOMATIC_UPLINK_MESSAGE=true + MBED_CONF_LORA_TX_MAX_SIZE=255 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/source/LoRaWANStack.cpp + Test_LoRaWANStack.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawanstack/Test_LoRaWANStack.cpp b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawanstack/Test_LoRaWANStack.cpp index 589e95b51f..13aca435fb 100644 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawanstack/Test_LoRaWANStack.cpp +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawanstack/Test_LoRaWANStack.cpp @@ -97,6 +97,7 @@ public: virtual uint32_t random(void) { + return 4; }; virtual uint8_t get_status(void) @@ -114,6 +115,7 @@ public: virtual uint32_t time_on_air(radio_modems_t modem, uint8_t pkt_len) { + return 0; }; virtual bool perform_carrier_sense(radio_modems_t modem, diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawanstack/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawanstack/unittest.cmake deleted file mode 100644 index 9607ac1f28..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawanstack/unittest.cmake +++ /dev/null @@ -1,53 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaWANStack") - -# Source files -set(unittest-sources - ../connectivity/lorawan/source/LoRaWANStack.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaWANStack.cpp - stubs/LoRaPHY_stub.cpp - stubs/LoRaMac_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/mbed_atomic_stub.c - stubs/LoRaMacCrypto_stub.cpp - stubs/LoRaMacChannelPlan_stub.cpp - stubs/LoRaWANTimer_stub.cpp - stubs/LoRaMacCommand_stub.cpp - stubs/EventQueue_stub.cpp - stubs/equeue_stub.c - stubs/Mutex_stub.cpp -) - -set(unittest-test-flags - -DMBED_CONF_LORA_OVER_THE_AIR_ACTIVATION=true - -DMBED_CONF_LORA_AUTOMATIC_UPLINK_MESSAGE=true - -DMBED_CONF_LORA_TX_MAX_SIZE=255 -) - diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawantimer/CMakeLists.txt b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawantimer/CMakeLists.txt new file mode 100644 index 0000000000..9efdd076cf --- /dev/null +++ b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawantimer/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME lorawan-lorawan-timer-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + NDEBUG=1 + MBED_CONF_LORA_TX_MAX_SIZE=255 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/lorawan/system/LoRaWANTimer.cpp + Test_LoRaWANTimer.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "lorawan") diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawantimer/unittest.cmake b/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawantimer/unittest.cmake deleted file mode 100644 index a95ab5dc29..0000000000 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/lorawantimer/unittest.cmake +++ /dev/null @@ -1,44 +0,0 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -]] - -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaWANTimer") - -# Source files -set(unittest-sources - ../connectivity/lorawan/system/LoRaWANTimer.cpp -) - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/system -) - -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaWANTimer.cpp - stubs/EventQueue_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/equeue_stub.c -) - -set(unittest-test-flags - -DNDEBUG=1 - -DMBED_CONF_LORA_TX_MAX_SIZE=255 -) - diff --git a/connectivity/lwipstack/source/LWIPStack.cpp b/connectivity/lwipstack/source/LWIPStack.cpp index dc807d7d60..db4adafb89 100644 --- a/connectivity/lwipstack/source/LWIPStack.cpp +++ b/connectivity/lwipstack/source/LWIPStack.cpp @@ -567,6 +567,22 @@ nsapi_error_t LWIP::setsockopt(nsapi_socket_t handle, int level, int optname, co } return 0; + case NSAPI_BROADCAST: + if (NETCONNTYPE_GROUP(s->conn->type) != NETCONN_UDP) { + return NSAPI_ERROR_UNSUPPORTED; + } + + if (optlen != sizeof(int)) { + return NSAPI_ERROR_UNSUPPORTED; + } + + if (*(const int *)optval) { + ip_set_option(s->conn->pcb.ip, SOF_BROADCAST); + } else { + ip_reset_option(s->conn->pcb.ip, SOF_BROADCAST); + } + return 0; + case NSAPI_ADD_MEMBERSHIP: case NSAPI_DROP_MEMBERSHIP: { if (optlen != sizeof(nsapi_ip_mreq_t)) { diff --git a/connectivity/mbedtls/CMakeLists.txt b/connectivity/mbedtls/CMakeLists.txt index e857db00fa..51938fe78d 100644 --- a/connectivity/mbedtls/CMakeLists.txt +++ b/connectivity/mbedtls/CMakeLists.txt @@ -16,6 +16,7 @@ target_sources(mbed-mbedtls platform/src/mbed_trng.cpp platform/src/platform_alt.cpp platform/src/shared_rng.cpp + platform/src/timing_mbed.cpp source/aes.c source/aesni.c @@ -84,6 +85,7 @@ target_sources(mbed-mbedtls source/ssl_srv.c source/ssl_ticket.c source/ssl_tls.c + source/ssl_tls13_keys.c source/threading.c source/timing.c source/version.c diff --git a/connectivity/mbedtls/VERSION.txt b/connectivity/mbedtls/VERSION.txt index 4961d31884..098c5314fa 100644 --- a/connectivity/mbedtls/VERSION.txt +++ b/connectivity/mbedtls/VERSION.txt @@ -1 +1 @@ -mbedtls-2.22.0 +v2.25.0 diff --git a/connectivity/mbedtls/include/mbedtls/bignum.h b/connectivity/mbedtls/include/mbedtls/bignum.h index 0d019b9c44..637360e30f 100644 --- a/connectivity/mbedtls/include/mbedtls/bignum.h +++ b/connectivity/mbedtls/include/mbedtls/bignum.h @@ -61,12 +61,12 @@ * Maximum window size used for modular exponentiation. Default: 6 * Minimum value: 1. Maximum value: 6. * - * Result is an array of ( 2 << MBEDTLS_MPI_WINDOW_SIZE ) MPIs used + * Result is an array of ( 2 ** MBEDTLS_MPI_WINDOW_SIZE ) MPIs used * for the sliding window calculation. (So 64 by default) * * Reduction in size, reduces speed. */ -#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum windows size used. */ +#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum window size used. */ #endif /* !MBEDTLS_MPI_WINDOW_SIZE */ #if !defined(MBEDTLS_MPI_MAX_SIZE) diff --git a/connectivity/mbedtls/include/mbedtls/ccm.h b/connectivity/mbedtls/include/mbedtls/ccm.h index 81965ba4df..7193863c37 100644 --- a/connectivity/mbedtls/include/mbedtls/ccm.h +++ b/connectivity/mbedtls/include/mbedtls/ccm.h @@ -148,7 +148,7 @@ void mbedtls_ccm_free( mbedtls_ccm_context *ctx ); * than zero, \p output must be a writable buffer of at least * that length. * \param tag The buffer holding the authentication field. This must be a - * readable buffer of at least \p tag_len Bytes. + * writable buffer of at least \p tag_len Bytes. * \param tag_len The length of the authentication field to generate in Bytes: * 4, 6, 8, 10, 12, 14 or 16. * @@ -193,7 +193,7 @@ int mbedtls_ccm_encrypt_and_tag( mbedtls_ccm_context *ctx, size_t length, * than zero, \p output must be a writable buffer of at least * that length. * \param tag The buffer holding the authentication field. This must be a - * readable buffer of at least \p tag_len Bytes. + * writable buffer of at least \p tag_len Bytes. * \param tag_len The length of the authentication field to generate in Bytes: * 0, 4, 6, 8, 10, 12, 14 or 16. * diff --git a/connectivity/mbedtls/include/mbedtls/check_config.h b/connectivity/mbedtls/include/mbedtls/check_config.h index 3a1929ba93..7e59accc70 100644 --- a/connectivity/mbedtls/include/mbedtls/check_config.h +++ b/connectivity/mbedtls/include/mbedtls/check_config.h @@ -55,9 +55,8 @@ #endif #endif /* _WIN32 */ -#if defined(TARGET_LIKE_MBED) && \ - ( defined(MBEDTLS_NET_C) || defined(MBEDTLS_TIMING_C) ) -#error "The NET and TIMING modules are not available for mbed OS - please use the network and timing functions provided by mbed OS" +#if defined(TARGET_LIKE_MBED) && defined(MBEDTLS_NET_C) +#error "The NET module is not available for mbed OS - please use the network functions provided by mbed OS" #endif #if defined(MBEDTLS_DEPRECATED_WARNING) && \ @@ -604,6 +603,11 @@ #error "MBEDTLS_PSA_ITS_FILE_C defined, but not all prerequisites" #endif +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) && \ + defined(MBEDTLS_USE_PSA_CRYPTO) +#error "MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER defined, but it cannot coexist with MBEDTLS_USE_PSA_CRYPTO." +#endif + #if defined(MBEDTLS_RSA_C) && ( !defined(MBEDTLS_BIGNUM_C) || \ !defined(MBEDTLS_OID_C) ) #error "MBEDTLS_RSA_C defined, but not all prerequisites" @@ -866,6 +870,10 @@ #endif /* MBEDTLS_DEPRECATED_REMOVED */ #endif /* MBEDTLS_SSL_HW_RECORD_ACCEL */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) && ( !defined(MBEDTLS_SSL_PROTO_DTLS) ) +#error "MBEDTLS_SSL_DTLS_SRTP defined, but not all prerequisites" +#endif + /* * Avoid warning from -pedantic. This is a convenient place for this * workaround since this is included by every single file before the diff --git a/connectivity/mbedtls/include/mbedtls/cipher.h b/connectivity/mbedtls/include/mbedtls/cipher.h index 014786ad51..1cafa6ec2e 100644 --- a/connectivity/mbedtls/include/mbedtls/cipher.h +++ b/connectivity/mbedtls/include/mbedtls/cipher.h @@ -227,10 +227,30 @@ enum { }; /** Maximum length of any IV, in Bytes. */ +/* This should ideally be derived automatically from list of ciphers. + * This should be kept in sync with MBEDTLS_SSL_MAX_IV_LENGTH defined + * in ssl_internal.h. */ #define MBEDTLS_MAX_IV_LENGTH 16 + /** Maximum block size of any cipher, in Bytes. */ +/* This should ideally be derived automatically from list of ciphers. + * This should be kept in sync with MBEDTLS_SSL_MAX_BLOCK_LENGTH defined + * in ssl_internal.h. */ #define MBEDTLS_MAX_BLOCK_LENGTH 16 +/** Maximum key length, in Bytes. */ +/* This should ideally be derived automatically from list of ciphers. + * For now, only check whether XTS is enabled which uses 64 Byte keys, + * and use 32 Bytes as an upper bound for the maximum key length otherwise. + * This should be kept in sync with MBEDTLS_SSL_MAX_BLOCK_LENGTH defined + * in ssl_internal.h, which however deliberately ignores the case of XTS + * since the latter isn't used in SSL/TLS. */ +#if defined(MBEDTLS_CIPHER_MODE_XTS) +#define MBEDTLS_MAX_KEY_LENGTH 64 +#else +#define MBEDTLS_MAX_KEY_LENGTH 32 +#endif /* MBEDTLS_CIPHER_MODE_XTS */ + /** * Base cipher information (opaque struct). */ @@ -837,30 +857,52 @@ int mbedtls_cipher_crypt( mbedtls_cipher_context_t *ctx, unsigned char *output, size_t *olen ); #if defined(MBEDTLS_CIPHER_MODE_AEAD) +#if ! defined(MBEDTLS_DEPRECATED_REMOVED) +#if defined(MBEDTLS_DEPRECATED_WARNING) +#define MBEDTLS_DEPRECATED __attribute__((deprecated)) +#else +#define MBEDTLS_DEPRECATED +#endif /* MBEDTLS_DEPRECATED_WARNING */ /** - * \brief The generic autenticated encryption (AEAD) function. + * \brief The generic authenticated encryption (AEAD) function. + * + * \deprecated Superseded by mbedtls_cipher_auth_encrypt_ext(). + * + * \note This function only supports AEAD algorithms, not key + * wrapping algorithms such as NIST_KW; for this, see + * mbedtls_cipher_auth_encrypt_ext(). * * \param ctx The generic cipher context. This must be initialized and - * bound to a key. - * \param iv The IV to use, or NONCE_COUNTER for CTR-mode ciphers. - * This must be a readable buffer of at least \p iv_len - * Bytes. - * \param iv_len The IV length for ciphers with variable-size IV. - * This parameter is discarded by ciphers with fixed-size IV. + * bound to a key associated with an AEAD algorithm. + * \param iv The nonce to use. This must be a readable buffer of + * at least \p iv_len Bytes and must not be \c NULL. + * \param iv_len The length of the nonce. This must satisfy the + * constraints imposed by the AEAD cipher used. * \param ad The additional data to authenticate. This must be a - * readable buffer of at least \p ad_len Bytes. + * readable buffer of at least \p ad_len Bytes, and may + * be \c NULL is \p ad_len is \c 0. * \param ad_len The length of \p ad. * \param input The buffer holding the input data. This must be a - * readable buffer of at least \p ilen Bytes. + * readable buffer of at least \p ilen Bytes, and may be + * \c NULL if \p ilen is \c 0. * \param ilen The length of the input data. - * \param output The buffer for the output data. This must be able to - * hold at least \p ilen Bytes. - * \param olen The length of the output data, to be updated with the - * actual number of Bytes written. This must not be - * \c NULL. + * \param output The buffer for the output data. This must be a + * writable buffer of at least \p ilen Bytes, and must + * not be \c NULL. + * \param olen This will be filled with the actual number of Bytes + * written to the \p output buffer. This must point to a + * writable object of type \c size_t. * \param tag The buffer for the authentication tag. This must be a - * writable buffer of at least \p tag_len Bytes. - * \param tag_len The desired length of the authentication tag. + * writable buffer of at least \p tag_len Bytes. See note + * below regarding restrictions with PSA-based contexts. + * \param tag_len The desired length of the authentication tag. This + * must match the constraints imposed by the AEAD cipher + * used, and in particular must not be \c 0. + * + * \note If the context is based on PSA (that is, it was set up + * with mbedtls_cipher_setup_psa()), then it is required + * that \c tag == output + ilen. That is, the tag must be + * appended to the ciphertext as recommended by RFC 5116. * * \return \c 0 on success. * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on @@ -872,36 +914,53 @@ int mbedtls_cipher_auth_encrypt( mbedtls_cipher_context_t *ctx, const unsigned char *ad, size_t ad_len, const unsigned char *input, size_t ilen, unsigned char *output, size_t *olen, - unsigned char *tag, size_t tag_len ); + unsigned char *tag, size_t tag_len ) + MBEDTLS_DEPRECATED; /** - * \brief The generic autenticated decryption (AEAD) function. + * \brief The generic authenticated decryption (AEAD) function. + * + * \deprecated Superseded by mbedtls_cipher_auth_decrypt_ext(). + * + * \note This function only supports AEAD algorithms, not key + * wrapping algorithms such as NIST_KW; for this, see + * mbedtls_cipher_auth_decrypt_ext(). * * \note If the data is not authentic, then the output buffer * is zeroed out to prevent the unauthentic plaintext being * used, making this interface safer. * * \param ctx The generic cipher context. This must be initialized and - * and bound to a key. - * \param iv The IV to use, or NONCE_COUNTER for CTR-mode ciphers. - * This must be a readable buffer of at least \p iv_len - * Bytes. - * \param iv_len The IV length for ciphers with variable-size IV. - * This parameter is discarded by ciphers with fixed-size IV. - * \param ad The additional data to be authenticated. This must be a - * readable buffer of at least \p ad_len Bytes. + * bound to a key associated with an AEAD algorithm. + * \param iv The nonce to use. This must be a readable buffer of + * at least \p iv_len Bytes and must not be \c NULL. + * \param iv_len The length of the nonce. This must satisfy the + * constraints imposed by the AEAD cipher used. + * \param ad The additional data to authenticate. This must be a + * readable buffer of at least \p ad_len Bytes, and may + * be \c NULL is \p ad_len is \c 0. * \param ad_len The length of \p ad. * \param input The buffer holding the input data. This must be a - * readable buffer of at least \p ilen Bytes. + * readable buffer of at least \p ilen Bytes, and may be + * \c NULL if \p ilen is \c 0. * \param ilen The length of the input data. - * \param output The buffer for the output data. - * This must be able to hold at least \p ilen Bytes. - * \param olen The length of the output data, to be updated with the - * actual number of Bytes written. This must not be - * \c NULL. - * \param tag The buffer holding the authentication tag. This must be - * a readable buffer of at least \p tag_len Bytes. - * \param tag_len The length of the authentication tag. + * \param output The buffer for the output data. This must be a + * writable buffer of at least \p ilen Bytes, and must + * not be \c NULL. + * \param olen This will be filled with the actual number of Bytes + * written to the \p output buffer. This must point to a + * writable object of type \c size_t. + * \param tag The buffer for the authentication tag. This must be a + * readable buffer of at least \p tag_len Bytes. See note + * below regarding restrictions with PSA-based contexts. + * \param tag_len The length of the authentication tag. This must match + * the constraints imposed by the AEAD cipher used, and in + * particular must not be \c 0. + * + * \note If the context is based on PSA (that is, it was set up + * with mbedtls_cipher_setup_psa()), then it is required + * that \c tag == input + len. That is, the tag must be + * appended to the ciphertext as recommended by RFC 5116. * * \return \c 0 on success. * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on @@ -914,9 +973,120 @@ int mbedtls_cipher_auth_decrypt( mbedtls_cipher_context_t *ctx, const unsigned char *ad, size_t ad_len, const unsigned char *input, size_t ilen, unsigned char *output, size_t *olen, - const unsigned char *tag, size_t tag_len ); + const unsigned char *tag, size_t tag_len ) + MBEDTLS_DEPRECATED; +#undef MBEDTLS_DEPRECATED +#endif /* MBEDTLS_DEPRECATED_REMOVED */ #endif /* MBEDTLS_CIPHER_MODE_AEAD */ +#if defined(MBEDTLS_CIPHER_MODE_AEAD) || defined(MBEDTLS_NIST_KW_C) +/** + * \brief The authenticated encryption (AEAD/NIST_KW) function. + * + * \note For AEAD modes, the tag will be appended to the + * ciphertext, as recommended by RFC 5116. + * (NIST_KW doesn't have a separate tag.) + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a key, with an AEAD algorithm or NIST_KW. + * \param iv The nonce to use. This must be a readable buffer of + * at least \p iv_len Bytes and may be \c NULL if \p + * iv_len is \c 0. + * \param iv_len The length of the nonce. For AEAD ciphers, this must + * satisfy the constraints imposed by the cipher used. + * For NIST_KW, this must be \c 0. + * \param ad The additional data to authenticate. This must be a + * readable buffer of at least \p ad_len Bytes, and may + * be \c NULL is \p ad_len is \c 0. + * \param ad_len The length of \p ad. For NIST_KW, this must be \c 0. + * \param input The buffer holding the input data. This must be a + * readable buffer of at least \p ilen Bytes, and may be + * \c NULL if \p ilen is \c 0. + * \param ilen The length of the input data. + * \param output The buffer for the output data. This must be a + * writable buffer of at least \p output_len Bytes, and + * must not be \c NULL. + * \param output_len The length of the \p output buffer in Bytes. For AEAD + * ciphers, this must be at least \p ilen + \p tag_len. + * For NIST_KW, this must be at least \p ilen + 8 + * (rounded up to a multiple of 8 if KWP is used); + * \p ilen + 15 is always a safe value. + * \param olen This will be filled with the actual number of Bytes + * written to the \p output buffer. This must point to a + * writable object of type \c size_t. + * \param tag_len The desired length of the authentication tag. For AEAD + * ciphers, this must match the constraints imposed by + * the cipher used, and in particular must not be \c 0. + * For NIST_KW, this must be \c 0. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_auth_encrypt_ext( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t output_len, + size_t *olen, size_t tag_len ); + +/** + * \brief The authenticated encryption (AEAD/NIST_KW) function. + * + * \note If the data is not authentic, then the output buffer + * is zeroed out to prevent the unauthentic plaintext being + * used, making this interface safer. + * + * \note For AEAD modes, the tag must be appended to the + * ciphertext, as recommended by RFC 5116. + * (NIST_KW doesn't have a separate tag.) + * + * \param ctx The generic cipher context. This must be initialized and + * bound to a key, with an AEAD algorithm or NIST_KW. + * \param iv The nonce to use. This must be a readable buffer of + * at least \p iv_len Bytes and may be \c NULL if \p + * iv_len is \c 0. + * \param iv_len The length of the nonce. For AEAD ciphers, this must + * satisfy the constraints imposed by the cipher used. + * For NIST_KW, this must be \c 0. + * \param ad The additional data to authenticate. This must be a + * readable buffer of at least \p ad_len Bytes, and may + * be \c NULL is \p ad_len is \c 0. + * \param ad_len The length of \p ad. For NIST_KW, this must be \c 0. + * \param input The buffer holding the input data. This must be a + * readable buffer of at least \p ilen Bytes, and may be + * \c NULL if \p ilen is \c 0. + * \param ilen The length of the input data. For AEAD ciphers this + * must be at least \p tag_len. For NIST_KW this must be + * at least \c 8. + * \param output The buffer for the output data. This must be a + * writable buffer of at least \p output_len Bytes, and + * may be \c NULL if \p output_len is \c 0. + * \param output_len The length of the \p output buffer in Bytes. For AEAD + * ciphers, this must be at least \p ilen - \p tag_len. + * For NIST_KW, this must be at least \p ilen - 8. + * \param olen This will be filled with the actual number of Bytes + * written to the \p output buffer. This must point to a + * writable object of type \c size_t. + * \param tag_len The actual length of the authentication tag. For AEAD + * ciphers, this must match the constraints imposed by + * the cipher used, and in particular must not be \c 0. + * For NIST_KW, this must be \c 0. + * + * \return \c 0 on success. + * \return #MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA on + * parameter-verification failure. + * \return #MBEDTLS_ERR_CIPHER_AUTH_FAILED if data is not authentic. + * \return A cipher-specific error code on failure. + */ +int mbedtls_cipher_auth_decrypt_ext( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t output_len, + size_t *olen, size_t tag_len ); +#endif /* MBEDTLS_CIPHER_MODE_AEAD || MBEDTLS_NIST_KW_C */ #ifdef __cplusplus } #endif diff --git a/connectivity/mbedtls/include/mbedtls/cipher_internal.h b/connectivity/mbedtls/include/mbedtls/cipher_internal.h index d28310847a..2484c01c7a 100644 --- a/connectivity/mbedtls/include/mbedtls/cipher_internal.h +++ b/connectivity/mbedtls/include/mbedtls/cipher_internal.h @@ -134,7 +134,7 @@ typedef enum typedef struct { psa_algorithm_t alg; - psa_key_handle_t slot; + psa_key_id_t slot; mbedtls_cipher_psa_key_ownership slot_state; } mbedtls_cipher_context_psa; #endif /* MBEDTLS_USE_PSA_CRYPTO */ diff --git a/connectivity/mbedtls/include/mbedtls/config-no-entropy.h b/connectivity/mbedtls/include/mbedtls/config-no-entropy.h index aa298ba7b7..19df6d1435 100644 --- a/connectivity/mbedtls/include/mbedtls/config-no-entropy.h +++ b/connectivity/mbedtls/include/mbedtls/config-no-entropy.h @@ -48,7 +48,7 @@ #define MBEDTLS_PK_RSA_ALT_SUPPORT #define MBEDTLS_PKCS1_V15 #define MBEDTLS_PKCS1_V21 -#define MBEDTLS_SELF_TEST +//#define MBEDTLS_SELF_TEST #define MBEDTLS_VERSION_FEATURES #define MBEDTLS_X509_CHECK_KEY_USAGE #define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE diff --git a/connectivity/mbedtls/include/mbedtls/config.h b/connectivity/mbedtls/include/mbedtls/config.h index 5ab37d996a..6201d9910c 100644 --- a/connectivity/mbedtls/include/mbedtls/config.h +++ b/connectivity/mbedtls/include/mbedtls/config.h @@ -880,7 +880,7 @@ * may result in a compromise of the long-term signing key. This is avoided by * the deterministic variant. * - * Requires: MBEDTLS_HMAC_DRBG_C + * Requires: MBEDTLS_HMAC_DRBG_C, MBEDTLS_ECDSA_C * * Comment this macro to disable deterministic ECDSA. */ @@ -1274,20 +1274,17 @@ */ //#define MBEDTLS_ENTROPY_NV_SEED -/* MBEDTLS_PSA_CRYPTO_KEY_FILE_ID_ENCODES_OWNER +/* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER * - * In PSA key storage, encode the owner of the key. + * Enable key identifiers that encode a key owner identifier. * - * This is only meaningful when building the library as part of a - * multi-client service. When you activate this option, you must provide - * an implementation of the type psa_key_owner_id_t and a translation - * from psa_key_file_id_t to file name in all the storage backends that - * you wish to support. + * The owner of a key is identified by a value of type ::mbedtls_key_owner_id_t + * which is currently hard-coded to be int32_t. * * Note that this option is meant for internal use only and may be removed - * without notice. + * without notice. It is incompatible with MBEDTLS_USE_PSA_CRYPTO. */ -//#define MBEDTLS_PSA_CRYPTO_KEY_FILE_ID_ENCODES_OWNER +//#define MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER /** * \def MBEDTLS_MEMORY_DEBUG @@ -1345,6 +1342,17 @@ */ #define MBEDTLS_PKCS1_V21 +/** \def MBEDTLS_PSA_CRYPTO_DRIVERS + * + * Enable support for the experimental PSA crypto driver interface. + * + * Requires: MBEDTLS_PSA_CRYPTO_C + * + * \warning This interface is experimental and may change or be removed + * without notice. + */ +//#define MBEDTLS_PSA_CRYPTO_DRIVERS + /** * \def MBEDTLS_PSA_CRYPTO_SPM * @@ -1388,7 +1396,7 @@ * * Enable the checkup functions (*_self_test). */ -#define MBEDTLS_SELF_TEST +//#define MBEDTLS_SELF_TEST /** * \def MBEDTLS_SHA256_SMALLER @@ -1820,6 +1828,37 @@ */ #define MBEDTLS_SSL_DTLS_HELLO_VERIFY +/** + * \def MBEDTLS_SSL_DTLS_SRTP + * + * Enable support for negotation of DTLS-SRTP (RFC 5764) + * through the use_srtp extension. + * + * \note This feature provides the minimum functionality required + * to negotiate the use of DTLS-SRTP and to allow the derivation of + * the associated SRTP packet protection key material. + * In particular, the SRTP packet protection itself, as well as the + * demultiplexing of RTP and DTLS packets at the datagram layer + * (see Section 5 of RFC 5764), are not handled by this feature. + * Instead, after successful completion of a handshake negotiating + * the use of DTLS-SRTP, the extended key exporter API + * mbedtls_ssl_conf_export_keys_ext_cb() should be used to implement + * the key exporter described in Section 4.2 of RFC 5764 and RFC 5705 + * (this is implemented in the SSL example programs). + * The resulting key should then be passed to an SRTP stack. + * + * Setting this option enables the runtime API + * mbedtls_ssl_conf_dtls_srtp_protection_profiles() + * through which the supported DTLS-SRTP protection + * profiles can be configured. You must call this API at + * runtime if you wish to negotiate the use of DTLS-SRTP. + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + * + * Uncomment this to enable support for use_srtp extension. + */ +//#define MBEDTLS_SSL_DTLS_SRTP + /** * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE * @@ -2027,6 +2066,24 @@ */ //#define MBEDTLS_USE_PSA_CRYPTO +/** + * \def MBEDTLS_PSA_CRYPTO_CONFIG + * + * This setting allows support for cryptographic mechanisms through the PSA + * API to be configured separately from support through the mbedtls API. + * + * Uncomment this to enable use of PSA Crypto configuration settings which + * can be found in include/psa/crypto_config.h. + * + * If you enable this option and write your own configuration file, you must + * include mbedtls/config_psa.h in your configuration file. The default + * provided mbedtls/config.h contains the necessary inclusion. + * + * This feature is still experimental and is not ready for production since + * it is not completed. + */ +//#define MBEDTLS_PSA_CRYPTO_CONFIG + /** * \def MBEDTLS_VERSION_FEATURES * @@ -3466,7 +3523,7 @@ */ /* MPI / BIGNUM options */ -//#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum windows size used. */ +//#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum window size used. */ #define MBEDTLS_MPI_MAX_SIZE 512 /* CTR_DRBG options */ @@ -3819,6 +3876,10 @@ #include MBEDTLS_USER_CONFIG_FILE #endif +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) +#include "mbedtls/config_psa.h" +#endif + #include "mbedtls/check_config.h" diff --git a/connectivity/mbedtls/include/mbedtls/config_psa.h b/connectivity/mbedtls/include/mbedtls/config_psa.h new file mode 100644 index 0000000000..6a55d8168e --- /dev/null +++ b/connectivity/mbedtls/include/mbedtls/config_psa.h @@ -0,0 +1,337 @@ +/** + * \file mbedtls/config_psa.h + * \brief PSA crypto configuration options (set of defines) + * + * This set of compile-time options takes settings defined in + * include/mbedtls/config.h and include/psa/crypto_config.h and uses + * those definitions to define symbols used in the library code. + * + * Users and integrators should not edit this file, please edit + * include/mbedtls/config.h for MBETLS_XXX settings or + * include/psa/crypto_config.h for PSA_WANT_XXX settings. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_CONFIG_PSA_H +#define MBEDTLS_CONFIG_PSA_H + +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) +#include "psa/crypto_config.h" +#endif /* defined(MBEDTLS_PSA_CRYPTO_CONFIG) */ + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) + +#if defined(PSA_WANT_ALG_DETERMINISTIC_ECDSA) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_DETERMINISTIC_ECDSA) +#define MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA 1 +#define MBEDTLS_ECDSA_DETERMINISTIC +#define MBEDTLS_ECDSA_C +#define MBEDTLS_HMAC_DRBG_C +#define MBEDTLS_MD_C +#endif /* !MBEDTLS_PSA_ACCEL_ALG_DETERMINISTIC_ECDSA */ +#endif /* PSA_WANT_ALG_DETERMINISTIC_ECDSA */ + +#if defined(PSA_WANT_ALG_ECDH) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_ECDH) +#define MBEDTLS_PSA_BUILTIN_ALG_ECDH 1 +#define MBEDTLS_ECDH_C +#define MBEDTLS_ECP_C +#define MBEDTLS_BIGNUM_C +#endif /* !MBEDTLS_PSA_ACCEL_ALG_ECDH */ +#endif /* PSA_WANT_ALG_ECDH */ + +#if defined(PSA_WANT_ALG_ECDSA) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_ECDSA) +#define MBEDTLS_PSA_BUILTIN_ALG_ECDSA 1 +#define MBEDTLS_ECDSA_C +#endif /* !MBEDTLS_PSA_ACCEL_ALG_ECDSA */ +#endif /* PSA_WANT_ALG_ECDSA */ + +#if defined(PSA_WANT_ALG_HKDF) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_HKDF) +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#define MBEDTLS_PSA_BUILTIN_ALG_HKDF 1 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_HKDF */ +#endif /* PSA_WANT_ALG_HKDF */ + +#if defined(PSA_WANT_ALG_HMAC) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_HMAC) +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_HMAC */ +#endif /* PSA_WANT_ALG_HMAC */ + +#if defined(PSA_WANT_ALG_MD2) && !defined(MBEDTLS_PSA_ACCEL_ALG_MD2) +#define MBEDTLS_PSA_BUILTIN_ALG_MD2 1 +#define MBEDTLS_MD2_C +#endif + +#if defined(PSA_WANT_ALG_MD4) && !defined(MBEDTLS_PSA_ACCEL_ALG_MD4) +#define MBEDTLS_PSA_BUILTIN_ALG_MD4 1 +#define MBEDTLS_MD4_C +#endif + +#if defined(PSA_WANT_ALG_MD5) && !defined(MBEDTLS_PSA_ACCEL_ALG_MD5) +#define MBEDTLS_PSA_BUILTIN_ALG_MD5 1 +#define MBEDTLS_MD5_C +#endif + +#if defined(PSA_WANT_ALG_RIPEMD160) && !defined(MBEDTLS_PSA_ACCEL_ALG_RIPEMD160) +#define MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160 1 +#define MBEDTLS_RIPEMD160_C +#endif + +#if defined(PSA_WANT_ALG_RSA_OAEP) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_RSA_OAEP) +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP 1 +#define MBEDTLS_RSA_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_OID_C +#define MBEDTLS_PKCS1_V21 +#define MBEDTLS_MD_C +#endif /* !MBEDTLS_PSA_ACCEL_ALG_RSA_OAEP */ +#endif /* PSA_WANT_ALG_RSA_OAEP */ + +#if defined(PSA_WANT_ALG_RSA_PKCS1V15_CRYPT) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_RSA_PKCS1V15_CRYPT) +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT 1 +#define MBEDTLS_RSA_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_OID_C +#define MBEDTLS_PKCS1_V15 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_RSA_PKCS1V15_CRYPT */ +#endif /* PSA_WANT_ALG_RSA_PKCS1V15_CRYPT */ + +#if defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_RSA_PKCS1V15_SIGN) +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN 1 +#define MBEDTLS_RSA_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_OID_C +#define MBEDTLS_PKCS1_V15 +#define MBEDTLS_MD_C +#endif /* !MBEDTLS_PSA_ACCEL_ALG_RSA_PKCS1V15_SIGN */ +#endif /* PSA_WANT_ALG_RSA_PKCS1V15_SIGN */ + +#if defined(PSA_WANT_ALG_RSA_PSS) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_RSA_PSS) +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS 1 +#define MBEDTLS_RSA_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_OID_C +#define MBEDTLS_PKCS1_V21 +#define MBEDTLS_MD_C +#endif /* !MBEDTLS_PSA_ACCEL_ALG_RSA_PSS */ +#endif /* PSA_WANT_ALG_RSA_PSS */ + +#if defined(PSA_WANT_ALG_SHA_1) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_1) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_1 1 +#define MBEDTLS_SHA1_C +#endif + +#if defined(PSA_WANT_ALG_SHA_224) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_224) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_224 1 +#define MBEDTLS_SHA256_C +#endif + +#if defined(PSA_WANT_ALG_SHA_256) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_256) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_256 1 +#define MBEDTLS_SHA256_C +#endif + +#if defined(PSA_WANT_ALG_SHA_384) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_384) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_384 1 +#define MBEDTLS_SHA512_C +#endif + +#if defined(PSA_WANT_ALG_SHA_512) && !defined(MBEDTLS_PSA_ACCEL_ALG_SHA_512) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_512 1 +#define MBEDTLS_SHA512_C +#endif + +#if defined(PSA_WANT_ALG_TLS12_PRF) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_TLS12_PRF) +#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF 1 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_TLS12_PRF */ +#endif /* PSA_WANT_ALG_TLS12_PRF */ + +#if defined(PSA_WANT_ALG_TLS12_PSK_TO_MS) +#if !defined(MBEDTLS_PSA_ACCEL_ALG_TLS12_PSK_TO_MS) +#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS 1 +#endif /* !MBEDTLS_PSA_ACCEL_ALG_TLS12_PSK_TO_MS */ +#endif /* PSA_WANT_ALG_TLS12_PSK_TO_MS */ + +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR 1 +#define MBEDTLS_ECP_C +#define MBEDTLS_BIGNUM_C +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR */ +#endif /* PSA_WANT_KEY_TYPE_ECC_KEY_PAIR */ + +#if defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY 1 +#define MBEDTLS_ECP_C +#define MBEDTLS_BIGNUM_C +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY */ +#endif /* PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY */ + +#if defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR 1 +#define MBEDTLS_RSA_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_OID_C +#define MBEDTLS_GENPRIME +#define MBEDTLS_PK_PARSE_C +#define MBEDTLS_PK_WRITE_C +#define MBEDTLS_PK_C +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_KEY_PAIR */ +#endif /* PSA_WANT_KEY_TYPE_RSA_KEY_PAIR */ + +#if defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) +#if !defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_PUBLIC_KEY) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY 1 +#define MBEDTLS_RSA_C +#define MBEDTLS_BIGNUM_C +#define MBEDTLS_OID_C +#define MBEDTLS_PK_PARSE_C +#define MBEDTLS_PK_WRITE_C +#define MBEDTLS_PK_C +#endif /* !MBEDTLS_PSA_ACCEL_KEY_TYPE_RSA_PUBLIC_KEY */ +#endif /* PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY */ + +#else /* MBEDTLS_PSA_CRYPTO_CONFIG */ + +/* + * Ensure PSA_WANT_* defines are setup properly if MBEDTLS_PSA_CRYPTO_CONFIG + * is not defined + */ + +#if defined(MBEDTLS_ECDH_C) +#define MBEDTLS_PSA_BUILTIN_ALG_ECDH 1 +#define PSA_WANT_ALG_ECDH 1 +#endif /* MBEDTLS_ECDH_C */ + +#if defined(MBEDTLS_ECDSA_C) +#define MBEDTLS_PSA_BUILTIN_ALG_ECDSA 1 +#define PSA_WANT_ALG_ECDSA 1 + +// Only add in DETERMINISTIC support if ECDSA is also enabled +#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +#define MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA 1 +#define PSA_WANT_ALG_DETERMINISTIC_ECDSA 1 +#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ + +#endif /* MBEDTLS_ECDSA_C */ + +#if defined(MBEDTLS_ECP_C) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR 1 +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY 1 +#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY 1 +#endif /* MBEDTLS_ECP_C */ + +#if defined(MBEDTLS_HKDF_C) +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#define PSA_WANT_ALG_HMAC 1 +#define MBEDTLS_PSA_BUILTIN_ALG_HKDF 1 +#define PSA_WANT_ALG_HKDF 1 +#endif /* MBEDTLS_HKDF_C */ + +#if defined(MBEDTLS_MD_C) +#define MBEDTLS_PSA_BUILTIN_ALG_HMAC 1 +#define PSA_WANT_ALG_HMAC 1 +#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF 1 +#define PSA_WANT_ALG_TLS12_PRF 1 +#define MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS 1 +#define PSA_WANT_ALG_TLS12_PSK_TO_MS 1 +#endif /* MBEDTLS_MD_C */ + +#if defined(MBEDTLS_MD2_C) +#define MBEDTLS_PSA_BUILTIN_ALG_MD2 1 +#define PSA_WANT_ALG_MD2 1 +#endif + +#if defined(MBEDTLS_MD4_C) +#define MBEDTLS_PSA_BUILTIN_ALG_MD4 1 +#define PSA_WANT_ALG_MD4 1 +#endif + +#if defined(MBEDTLS_MD5_C) +#define MBEDTLS_PSA_BUILTIN_ALG_MD5 1 +#define PSA_WANT_ALG_MD5 1 +#endif + +#if defined(MBEDTLS_RIPEMD160_C) +#define MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160 1 +#define PSA_WANT_ALG_RIPEMD160 1 +#endif + +#if defined(MBEDTLS_RSA_C) +#if defined(MBEDTLS_PKCS1_V15) +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT 1 +#define PSA_WANT_ALG_RSA_PKCS1V15_CRYPT 1 +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN 1 +#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN 1 +#endif /* MBEDTLSS_PKCS1_V15 */ +#if defined(MBEDTLS_PKCS1_V21) +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP 1 +#define PSA_WANT_ALG_RSA_OAEP 1 +#define MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS 1 +#define PSA_WANT_ALG_RSA_PSS 1 +#endif /* MBEDTLS_PKCS1_V21 */ +#if defined(MBEDTLS_GENPRIME) +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR 1 +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR 1 +#endif /* MBEDTLS_GENPRIME */ +#define MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY 1 +#define PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY 1 +#endif /* MBEDTLS_RSA_C */ + +#if defined(MBEDTLS_SHA1_C) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_1 1 +#define PSA_WANT_ALG_SHA_1 1 +#endif + +#if defined(MBEDTLS_SHA256_C) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_224 1 +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_256 1 +#define PSA_WANT_ALG_SHA_256 1 +#endif + +#if defined(MBEDTLS_SHA512_C) +#if !defined(MBEDTLS_SHA512_NO_SHA384) +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_384 1 +#define PSA_WANT_ALG_SHA_384 1 +#endif +#define MBEDTLS_PSA_BUILTIN_ALG_SHA_512 1 +#define PSA_WANT_ALG_SHA_512 1 +#endif + +#endif /* MBEDTLS_PSA_CRYPTO_CONFIG */ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_CONFIG_PSA_H */ diff --git a/connectivity/mbedtls/include/mbedtls/ctr_drbg.h b/connectivity/mbedtls/include/mbedtls/ctr_drbg.h index 6c48ec1edd..7f1d23253c 100644 --- a/connectivity/mbedtls/include/mbedtls/ctr_drbg.h +++ b/connectivity/mbedtls/include/mbedtls/ctr_drbg.h @@ -210,6 +210,11 @@ mbedtls_ctr_drbg_context; * and prepares it for mbedtls_ctr_drbg_seed() * or mbedtls_ctr_drbg_free(). * + * \note The reseed interval is + * #MBEDTLS_CTR_DRBG_RESEED_INTERVAL by default. + * You can override it by calling + * mbedtls_ctr_drbg_set_reseed_interval(). + * * \param ctx The CTR_DRBG context to initialize. */ void mbedtls_ctr_drbg_init( mbedtls_ctr_drbg_context *ctx ); @@ -309,7 +314,8 @@ int mbedtls_ctr_drbg_seed( mbedtls_ctr_drbg_context *ctx, size_t len ); /** - * \brief This function clears CTR_CRBG context data. + * \brief This function resets CTR_DRBG context to the state immediately + * after initial call of mbedtls_ctr_drbg_init(). * * \param ctx The CTR_DRBG context to clear. */ diff --git a/connectivity/mbedtls/include/mbedtls/gcm.h b/connectivity/mbedtls/include/mbedtls/gcm.h index ed23cb9c6c..6b673616f9 100644 --- a/connectivity/mbedtls/include/mbedtls/gcm.h +++ b/connectivity/mbedtls/include/mbedtls/gcm.h @@ -155,7 +155,7 @@ int mbedtls_gcm_setkey( mbedtls_gcm_context *ctx, * than zero, this must be a writable buffer of at least that * size in Bytes. * \param tag_len The length of the tag to generate. - * \param tag The buffer for holding the tag. This must be a readable + * \param tag The buffer for holding the tag. This must be a writable * buffer of at least \p tag_len Bytes. * * \return \c 0 if the encryption or decryption was performed @@ -283,7 +283,7 @@ int mbedtls_gcm_update( mbedtls_gcm_context *ctx, * tag. The tag can have a maximum length of 16 Bytes. * * \param ctx The GCM context. This must be initialized. - * \param tag The buffer for holding the tag. This must be a readable + * \param tag The buffer for holding the tag. This must be a writable * buffer of at least \p tag_len Bytes. * \param tag_len The length of the tag to generate. This must be at least * four. diff --git a/connectivity/mbedtls/include/mbedtls/hmac_drbg.h b/connectivity/mbedtls/include/mbedtls/hmac_drbg.h index 57ce9d98f4..91165415fb 100644 --- a/connectivity/mbedtls/include/mbedtls/hmac_drbg.h +++ b/connectivity/mbedtls/include/mbedtls/hmac_drbg.h @@ -111,6 +111,10 @@ typedef struct mbedtls_hmac_drbg_context * This function makes the context ready for mbedtls_hmac_drbg_seed(), * mbedtls_hmac_drbg_seed_buf() or mbedtls_hmac_drbg_free(). * + * \note The reseed interval is #MBEDTLS_HMAC_DRBG_RESEED_INTERVAL + * by default. Override this value by calling + * mbedtls_hmac_drbg_set_reseed_interval(). + * * \param ctx HMAC_DRBG context to be initialized. */ void mbedtls_hmac_drbg_init( mbedtls_hmac_drbg_context *ctx ); @@ -334,7 +338,8 @@ int mbedtls_hmac_drbg_random_with_add( void *p_rng, int mbedtls_hmac_drbg_random( void *p_rng, unsigned char *output, size_t out_len ); /** - * \brief Free an HMAC_DRBG context + * \brief This function resets HMAC_DRBG context to the state immediately + * after initial call of mbedtls_hmac_drbg_init(). * * \param ctx The HMAC_DRBG context to free. */ diff --git a/connectivity/mbedtls/include/mbedtls/pk.h b/connectivity/mbedtls/include/mbedtls/pk.h index 22fab13bda..7d0f977d5d 100644 --- a/connectivity/mbedtls/include/mbedtls/pk.h +++ b/connectivity/mbedtls/include/mbedtls/pk.h @@ -331,12 +331,13 @@ int mbedtls_pk_setup( mbedtls_pk_context *ctx, const mbedtls_pk_info_t *info ); * * \return \c 0 on success. * \return #MBEDTLS_ERR_PK_BAD_INPUT_DATA on invalid input - * (context already used, invalid key handle). + * (context already used, invalid key identifier). * \return #MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE if the key is not an * ECC key pair. * \return #MBEDTLS_ERR_PK_ALLOC_FAILED on allocation failure. */ -int mbedtls_pk_setup_opaque( mbedtls_pk_context *ctx, const psa_key_handle_t key ); +int mbedtls_pk_setup_opaque( mbedtls_pk_context *ctx, + const psa_key_id_t key ); #endif /* MBEDTLS_USE_PSA_CRYPTO */ #if defined(MBEDTLS_PK_RSA_ALT_SUPPORT) @@ -858,9 +859,9 @@ int mbedtls_pk_load_file( const char *path, unsigned char **buf, size_t *n ); * * \param pk Input: the EC key to import to a PSA key. * Output: a PK context wrapping that PSA key. - * \param handle Output: a PSA key handle. + * \param key Output: a PSA key identifier. * It's the caller's responsibility to call - * psa_destroy_key() on that handle after calling + * psa_destroy_key() on that key identifier after calling * mbedtls_pk_free() on the PK context. * \param hash_alg The hash algorithm to allow for use with that key. * @@ -868,7 +869,7 @@ int mbedtls_pk_load_file( const char *path, unsigned char **buf, size_t *n ); * \return An Mbed TLS error code otherwise. */ int mbedtls_pk_wrap_as_opaque( mbedtls_pk_context *pk, - psa_key_handle_t *handle, + psa_key_id_t *key, psa_algorithm_t hash_alg ); #endif /* MBEDTLS_USE_PSA_CRYPTO */ diff --git a/connectivity/mbedtls/include/mbedtls/psa_util.h b/connectivity/mbedtls/include/mbedtls/psa_util.h index 3c037068ed..d8a32c59e5 100644 --- a/connectivity/mbedtls/include/mbedtls/psa_util.h +++ b/connectivity/mbedtls/include/mbedtls/psa_util.h @@ -83,6 +83,8 @@ static inline psa_algorithm_t mbedtls_psa_translate_cipher_mode( { switch( mode ) { + case MBEDTLS_MODE_ECB: + return( PSA_ALG_ECB_NO_PADDING ); case MBEDTLS_MODE_GCM: return( PSA_ALG_AEAD_WITH_TAG_LENGTH( PSA_ALG_GCM, taglen ) ); case MBEDTLS_MODE_CCM: diff --git a/connectivity/mbedtls/include/mbedtls/sha512.h b/connectivity/mbedtls/include/mbedtls/sha512.h index 9036ed4990..4a8ab42564 100644 --- a/connectivity/mbedtls/include/mbedtls/sha512.h +++ b/connectivity/mbedtls/include/mbedtls/sha512.h @@ -131,8 +131,7 @@ int mbedtls_sha512_update_ret( mbedtls_sha512_context *ctx, /** * \brief This function finishes the SHA-512 operation, and writes - * the result to the output buffer. This function is for - * internal use only. + * the result to the output buffer. * * \param ctx The SHA-512 context. This must be initialized * and have a hash operation started. @@ -148,6 +147,7 @@ int mbedtls_sha512_finish_ret( mbedtls_sha512_context *ctx, /** * \brief This function processes a single data block within * the ongoing SHA-512 computation. + * This function is for internal use only. * * \param ctx The SHA-512 context. This must be initialized. * \param data The buffer holding one block of data. This diff --git a/connectivity/mbedtls/include/mbedtls/ssl.h b/connectivity/mbedtls/include/mbedtls/ssl.h index f086bdfdce..7815ad9d09 100644 --- a/connectivity/mbedtls/include/mbedtls/ssl.h +++ b/connectivity/mbedtls/include/mbedtls/ssl.h @@ -42,7 +42,12 @@ #include "mbedtls/dhm.h" #endif -#if defined(MBEDTLS_ECDH_C) +/* Adding guard for MBEDTLS_ECDSA_C to ensure no compile errors due + * to guards also being in ssl_srv.c and ssl_cli.c. There is a gap + * in functionality that access to ecdh_ctx structure is needed for + * MBEDTLS_ECDSA_C which does not seem correct. + */ +#if defined(MBEDTLS_ECDH_C) || defined(MBEDTLS_ECDSA_C) #include "mbedtls/ecdh.h" #endif @@ -214,6 +219,9 @@ #define MBEDTLS_SSL_CERT_REQ_CA_LIST_ENABLED 1 #define MBEDTLS_SSL_CERT_REQ_CA_LIST_DISABLED 0 +#define MBEDTLS_SSL_DTLS_SRTP_MKI_UNSUPPORTED 0 +#define MBEDTLS_SSL_DTLS_SRTP_MKI_SUPPORTED 1 + /* * Default range for DTLS retransmission timer value, in milliseconds. * RFC 6347 4.2.4.1 says from 1 second to 60 seconds. @@ -393,6 +401,8 @@ #define MBEDTLS_TLS_EXT_SIG_ALG 13 +#define MBEDTLS_TLS_EXT_USE_SRTP 14 + #define MBEDTLS_TLS_EXT_ALPN 16 #define MBEDTLS_TLS_EXT_ENCRYPT_THEN_MAC 22 /* 0x16 */ @@ -851,6 +861,41 @@ typedef void mbedtls_ssl_async_cancel_t( mbedtls_ssl_context *ssl ); #endif /* MBEDTLS_KEY_EXCHANGE_WITH_CERT_ENABLED && !MBEDTLS_SSL_KEEP_PEER_CERTIFICATE */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) + +#define MBEDTLS_TLS_SRTP_MAX_MKI_LENGTH 255 +#define MBEDTLS_TLS_SRTP_MAX_PROFILE_LIST_LENGTH 4 +/* + * For code readability use a typedef for DTLS-SRTP profiles + * + * Use_srtp extension protection profiles values as defined in + * http://www.iana.org/assignments/srtp-protection/srtp-protection.xhtml + * + * Reminder: if this list is expanded mbedtls_ssl_check_srtp_profile_value + * must be updated too. + */ +#define MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_80 ( (uint16_t) 0x0001) +#define MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_32 ( (uint16_t) 0x0002) +#define MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_80 ( (uint16_t) 0x0005) +#define MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_32 ( (uint16_t) 0x0006) +/* This one is not iana defined, but for code readability. */ +#define MBEDTLS_TLS_SRTP_UNSET ( (uint16_t) 0x0000) + +typedef uint16_t mbedtls_ssl_srtp_profile; + +typedef struct mbedtls_dtls_srtp_info_t +{ + /*! The SRTP profile that was negotiated. */ + mbedtls_ssl_srtp_profile chosen_dtls_srtp_profile; + /*! The length of mki_value. */ + uint16_t mki_len; + /*! The mki_value used, with max size of 256 bytes. */ + unsigned char mki_value[MBEDTLS_TLS_SRTP_MAX_MKI_LENGTH]; +} +mbedtls_dtls_srtp_info; + +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + /* * This structure is used for storing current session data. * @@ -1023,11 +1068,12 @@ struct mbedtls_ssl_config #if defined(MBEDTLS_KEY_EXCHANGE_SOME_PSK_ENABLED) #if defined(MBEDTLS_USE_PSA_CRYPTO) - psa_key_handle_t psk_opaque; /*!< PSA key slot holding opaque PSK. - * This field should only be set via - * mbedtls_ssl_conf_psk_opaque(). - * If either no PSK or a raw PSK have - * been configured, this has value \c 0. */ + psa_key_id_t psk_opaque; /*!< PSA key slot holding opaque PSK. This field + * should only be set via + * mbedtls_ssl_conf_psk_opaque(). + * If either no PSK or a raw PSK have been + * configured, this has value \c 0. + */ #endif /* MBEDTLS_USE_PSA_CRYPTO */ unsigned char *psk; /*!< The raw pre-shared key. This field should @@ -1057,6 +1103,13 @@ struct mbedtls_ssl_config const char **alpn_list; /*!< ordered list of protocols */ #endif +#if defined(MBEDTLS_SSL_DTLS_SRTP) + /*! ordered list of supported srtp profile */ + const mbedtls_ssl_srtp_profile *dtls_srtp_profile_list; + /*! number of supported profiles */ + size_t dtls_srtp_profile_list_len; +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + /* * Numerical settings (int then char) */ @@ -1137,9 +1190,12 @@ struct mbedtls_ssl_config * record with unexpected CID * should lead to failure. */ #endif /* MBEDTLS_SSL_DTLS_CONNECTION_ID */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) + unsigned int dtls_srtp_mki_support : 1; /* support having mki_value + in the use_srtp extension */ +#endif }; - struct mbedtls_ssl_context { const mbedtls_ssl_config *conf; /*!< configuration information */ @@ -1298,6 +1354,13 @@ struct mbedtls_ssl_context const char *alpn_chosen; /*!< negotiated protocol */ #endif /* MBEDTLS_SSL_ALPN */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) + /* + * use_srtp extension + */ + mbedtls_dtls_srtp_info dtls_srtp_info; +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + /* * Information for DTLS hello verify */ @@ -1559,7 +1622,7 @@ void mbedtls_ssl_conf_dbg( mbedtls_ssl_config *conf, * \note For DTLS, you need to provide either a non-NULL * f_recv_timeout callback, or a f_recv that doesn't block. * - * \note See the documentations of \c mbedtls_ssl_sent_t, + * \note See the documentations of \c mbedtls_ssl_send_t, * \c mbedtls_ssl_recv_t and \c mbedtls_ssl_recv_timeout_t for * the conventions those callbacks must follow. * @@ -2032,6 +2095,8 @@ void mbedtls_ssl_conf_export_keys_cb( mbedtls_ssl_config *conf, * (Default: none.) * * \note See \c mbedtls_ssl_export_keys_ext_t. + * \warning Exported key material must not be used for any purpose + * before the (D)TLS handshake is completed * * \param conf SSL configuration context * \param f_export_keys_ext Callback for exporting keys @@ -2755,7 +2820,7 @@ int mbedtls_ssl_conf_psk( mbedtls_ssl_config *conf, * \return An \c MBEDTLS_ERR_SSL_XXX error code on failure. */ int mbedtls_ssl_conf_psk_opaque( mbedtls_ssl_config *conf, - psa_key_handle_t psk, + psa_key_id_t psk, const unsigned char *psk_identity, size_t psk_identity_len ); #endif /* MBEDTLS_USE_PSA_CRYPTO */ @@ -2801,7 +2866,7 @@ int mbedtls_ssl_set_hs_psk( mbedtls_ssl_context *ssl, * \return An \c MBEDTLS_ERR_SSL_XXX error code on failure. */ int mbedtls_ssl_set_hs_psk_opaque( mbedtls_ssl_context *ssl, - psa_key_handle_t psk ); + psa_key_id_t psk ); #endif /* MBEDTLS_USE_PSA_CRYPTO */ /** @@ -3120,6 +3185,105 @@ int mbedtls_ssl_conf_alpn_protocols( mbedtls_ssl_config *conf, const char **prot const char *mbedtls_ssl_get_alpn_protocol( const mbedtls_ssl_context *ssl ); #endif /* MBEDTLS_SSL_ALPN */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) +#if defined(MBEDTLS_DEBUG_C) +static inline const char *mbedtls_ssl_get_srtp_profile_as_string( mbedtls_ssl_srtp_profile profile ) +{ + switch( profile ) + { + case MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_80: + return( "MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_80" ); + case MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_32: + return( "MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_32" ); + case MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_80: + return( "MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_80" ); + case MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_32: + return( "MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_32" ); + default: break; + } + return( "" ); +} +#endif /* MBEDTLS_DEBUG_C */ +/** + * \brief Manage support for mki(master key id) value + * in use_srtp extension. + * MKI is an optional part of SRTP used for key management + * and re-keying. See RFC3711 section 3.1 for details. + * The default value is + * #MBEDTLS_SSL_DTLS_SRTP_MKI_UNSUPPORTED. + * + * \param conf The SSL configuration to manage mki support. + * \param support_mki_value Enable or disable mki usage. Values are + * #MBEDTLS_SSL_DTLS_SRTP_MKI_UNSUPPORTED + * or #MBEDTLS_SSL_DTLS_SRTP_MKI_SUPPORTED. + */ +void mbedtls_ssl_conf_srtp_mki_value_supported( mbedtls_ssl_config *conf, + int support_mki_value ); + +/** + * \brief Set the supported DTLS-SRTP protection profiles. + * + * \param conf SSL configuration + * \param profiles Pointer to a List of MBEDTLS_TLS_SRTP_UNSET terminated + * supported protection profiles + * in decreasing preference order. + * The pointer to the list is recorded by the library + * for later reference as required, so the lifetime + * of the table must be at least as long as the lifetime + * of the SSL configuration structure. + * The list must not hold more than + * MBEDTLS_TLS_SRTP_MAX_PROFILE_LIST_LENGTH elements + * (excluding the terminating MBEDTLS_TLS_SRTP_UNSET). + * + * \return 0 on success + * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA when the list of + * protection profiles is incorrect. + */ +int mbedtls_ssl_conf_dtls_srtp_protection_profiles + ( mbedtls_ssl_config *conf, + const mbedtls_ssl_srtp_profile *profiles ); + +/** + * \brief Set the mki_value for the current DTLS-SRTP session. + * + * \param ssl SSL context to use. + * \param mki_value The MKI value to set. + * \param mki_len The length of the MKI value. + * + * \note This function is relevant on client side only. + * The server discovers the mki value during handshake. + * A mki value set on server side using this function + * is ignored. + * + * \return 0 on success + * \return #MBEDTLS_ERR_SSL_BAD_INPUT_DATA + * \return #MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE + */ +int mbedtls_ssl_dtls_srtp_set_mki_value( mbedtls_ssl_context *ssl, + unsigned char *mki_value, + uint16_t mki_len ); +/** + * \brief Get the negotiated DTLS-SRTP informations: + * Protection profile and MKI value. + * + * \warning This function must be called after the handshake is + * completed. The value returned by this function must + * not be trusted or acted upon before the handshake completes. + * + * \param ssl The SSL context to query. + * \param dtls_srtp_info The negotiated DTLS-SRTP informations: + * - Protection profile in use. + * A direct mapping of the iana defined value for protection + * profile on an uint16_t. + http://www.iana.org/assignments/srtp-protection/srtp-protection.xhtml + * #MBEDTLS_TLS_SRTP_UNSET if the use of SRTP was not negotiated + * or peer's Hello packet was not parsed yet. + * - mki size and value( if size is > 0 ). + */ +void mbedtls_ssl_get_dtls_srtp_negotiation_result( const mbedtls_ssl_context *ssl, + mbedtls_dtls_srtp_info *dtls_srtp_info ); +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + /** * \brief Set the maximum supported version sent from the client side * and/or accepted at the server side diff --git a/connectivity/mbedtls/include/mbedtls/ssl_internal.h b/connectivity/mbedtls/include/mbedtls/ssl_internal.h index b3d53d34ae..577c959b65 100644 --- a/connectivity/mbedtls/include/mbedtls/ssl_internal.h +++ b/connectivity/mbedtls/include/mbedtls/ssl_internal.h @@ -378,6 +378,49 @@ typedef int mbedtls_ssl_tls_prf_cb( const unsigned char *secret, size_t slen, const char *label, const unsigned char *random, size_t rlen, unsigned char *dstbuf, size_t dlen ); + +/* cipher.h exports the maximum IV, key and block length from + * all ciphers enabled in the config, regardless of whether those + * ciphers are actually usable in SSL/TLS. Notably, XTS is enabled + * in the default configuration and uses 64 Byte keys, but it is + * not used for record protection in SSL/TLS. + * + * In order to prevent unnecessary inflation of key structures, + * we introduce SSL-specific variants of the max-{key,block,IV} + * macros here which are meant to only take those ciphers into + * account which can be negotiated in SSL/TLS. + * + * Since the current definitions of MBEDTLS_MAX_{KEY|BLOCK|IV}_LENGTH + * in cipher.h are rough overapproximations of the real maxima, here + * we content ourselves with replicating those overapproximations + * for the maximum block and IV length, and excluding XTS from the + * computation of the maximum key length. */ +#define MBEDTLS_SSL_MAX_BLOCK_LENGTH 16 +#define MBEDTLS_SSL_MAX_IV_LENGTH 16 +#define MBEDTLS_SSL_MAX_KEY_LENGTH 32 + +/** + * \brief The data structure holding the cryptographic material (key and IV) + * used for record protection in TLS 1.3. + */ +struct mbedtls_ssl_key_set +{ + /*! The key for client->server records. */ + unsigned char client_write_key[ MBEDTLS_SSL_MAX_KEY_LENGTH ]; + /*! The key for server->client records. */ + unsigned char server_write_key[ MBEDTLS_SSL_MAX_KEY_LENGTH ]; + /*! The IV for client->server records. */ + unsigned char client_write_iv[ MBEDTLS_SSL_MAX_IV_LENGTH ]; + /*! The IV for server->client records. */ + unsigned char server_write_iv[ MBEDTLS_SSL_MAX_IV_LENGTH ]; + + size_t key_len; /*!< The length of client_write_key and + * server_write_key, in Bytes. */ + size_t iv_len; /*!< The length of client_write_iv and + * server_write_iv, in Bytes. */ +}; +typedef struct mbedtls_ssl_key_set mbedtls_ssl_key_set; + /* * This structure contains the parameters only needed during handshake. */ @@ -394,17 +437,22 @@ struct mbedtls_ssl_handshake_params #if defined(MBEDTLS_DHM_C) mbedtls_dhm_context dhm_ctx; /*!< DHM key exchange */ #endif -#if defined(MBEDTLS_ECDH_C) +/* Adding guard for MBEDTLS_ECDSA_C to ensure no compile errors due + * to guards also being in ssl_srv.c and ssl_cli.c. There is a gap + * in functionality that access to ecdh_ctx structure is needed for + * MBEDTLS_ECDSA_C which does not seem correct. + */ +#if defined(MBEDTLS_ECDH_C) || defined(MBEDTLS_ECDSA_C) mbedtls_ecdh_context ecdh_ctx; /*!< ECDH key exchange */ #if defined(MBEDTLS_USE_PSA_CRYPTO) psa_key_type_t ecdh_psa_type; uint16_t ecdh_bits; - psa_key_handle_t ecdh_psa_privkey; + psa_key_id_t ecdh_psa_privkey; unsigned char ecdh_psa_peerkey[MBEDTLS_PSA_MAX_EC_PUBKEY_LENGTH]; size_t ecdh_psa_peerkey_len; #endif /* MBEDTLS_USE_PSA_CRYPTO */ -#endif /* MBEDTLS_ECDH_C */ +#endif /* MBEDTLS_ECDH_C || MBEDTLS_ECDSA_C */ #if defined(MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED) mbedtls_ecjpake_context ecjpake_ctx; /*!< EC J-PAKE key exchange */ @@ -419,7 +467,7 @@ struct mbedtls_ssl_handshake_params #endif #if defined(MBEDTLS_KEY_EXCHANGE_SOME_PSK_ENABLED) #if defined(MBEDTLS_USE_PSA_CRYPTO) - psa_key_handle_t psk_opaque; /*!< Opaque PSK from the callback */ + psa_key_id_t psk_opaque; /*!< Opaque PSK from the callback */ #endif /* MBEDTLS_USE_PSA_CRYPTO */ unsigned char *psk; /*!< PSK from the callback */ size_t psk_len; /*!< Length of PSK from callback */ @@ -1018,16 +1066,16 @@ static inline int mbedtls_ssl_get_psk( const mbedtls_ssl_context *ssl, * 2. static PSK configured by \c mbedtls_ssl_conf_psk_opaque() * Return an opaque PSK */ -static inline psa_key_handle_t mbedtls_ssl_get_opaque_psk( +static inline psa_key_id_t mbedtls_ssl_get_opaque_psk( const mbedtls_ssl_context *ssl ) { - if( ssl->handshake->psk_opaque != 0 ) + if( ! mbedtls_svc_key_id_is_null( ssl->handshake->psk_opaque ) ) return( ssl->handshake->psk_opaque ); - if( ssl->conf->psk_opaque != 0 ) + if( ! mbedtls_svc_key_id_is_null( ssl->conf->psk_opaque ) ) return( ssl->conf->psk_opaque ); - return( 0 ); + return( MBEDTLS_SVC_KEY_ID_INIT ); } #endif /* MBEDTLS_USE_PSA_CRYPTO */ @@ -1052,6 +1100,23 @@ int mbedtls_ssl_check_sig_hash( const mbedtls_ssl_context *ssl, mbedtls_md_type_t md ); #endif +#if defined(MBEDTLS_SSL_DTLS_SRTP) +static inline mbedtls_ssl_srtp_profile mbedtls_ssl_check_srtp_profile_value + ( const uint16_t srtp_profile_value ) +{ + switch( srtp_profile_value ) + { + case MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_80: + case MBEDTLS_TLS_SRTP_AES128_CM_HMAC_SHA1_32: + case MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_80: + case MBEDTLS_TLS_SRTP_NULL_HMAC_SHA1_32: + return srtp_profile_value; + default: break; + } + return( MBEDTLS_TLS_SRTP_UNSET ); +} +#endif + #if defined(MBEDTLS_X509_CRT_PARSE_C) static inline mbedtls_pk_context *mbedtls_ssl_own_key( mbedtls_ssl_context *ssl ) { diff --git a/connectivity/mbedtls/include/mbedtls/version.h b/connectivity/mbedtls/include/mbedtls/version.h index 665a283e15..10c4316676 100644 --- a/connectivity/mbedtls/include/mbedtls/version.h +++ b/connectivity/mbedtls/include/mbedtls/version.h @@ -37,7 +37,7 @@ * Major, Minor, Patchlevel */ #define MBEDTLS_VERSION_MAJOR 2 -#define MBEDTLS_VERSION_MINOR 24 +#define MBEDTLS_VERSION_MINOR 25 #define MBEDTLS_VERSION_PATCH 0 /** @@ -45,9 +45,9 @@ * MMNNPP00 * Major version | Minor version | Patch version */ -#define MBEDTLS_VERSION_NUMBER 0x02180000 -#define MBEDTLS_VERSION_STRING "2.24.0" -#define MBEDTLS_VERSION_STRING_FULL "mbed TLS 2.24.0" +#define MBEDTLS_VERSION_NUMBER 0x02190000 +#define MBEDTLS_VERSION_STRING "2.25.0" +#define MBEDTLS_VERSION_STRING_FULL "mbed TLS 2.25.0" #if defined(MBEDTLS_VERSION_C) diff --git a/connectivity/mbedtls/platform/inc/platform_mbed.h b/connectivity/mbedtls/platform/inc/platform_mbed.h index f830e734c9..bce3339021 100644 --- a/connectivity/mbedtls/platform/inc/platform_mbed.h +++ b/connectivity/mbedtls/platform/inc/platform_mbed.h @@ -40,8 +40,10 @@ #endif // (defined(FEATURE_PSA) && defined(MBEDTLS_ENTROPY_NV_SEED)) #if DEVICE_TRNG +#if !defined(MBEDTLS_ENTROPY_HARDWARE_ALT) #define MBEDTLS_ENTROPY_HARDWARE_ALT #endif +#endif #if defined(MBEDTLS_CONFIG_HW_SUPPORT) #include "mbedtls_device.h" diff --git a/connectivity/mbedtls/platform/inc/timing_alt.h b/connectivity/mbedtls/platform/inc/timing_alt.h new file mode 100644 index 0000000000..533eab3d5b --- /dev/null +++ b/connectivity/mbedtls/platform/inc/timing_alt.h @@ -0,0 +1,40 @@ +/* + * timing_alt.h + * + * Copyright (C) 2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef TIMING_ALT_H +#define TIMING_ALT_H + +#include "mbedtls/timing.h" +#if defined(MBEDTLS_TIMING_ALT) + +struct mbedtls_timing_hr_time +{ + unsigned long start; +}; + +typedef struct mbedtls_timing_delay_context +{ + struct mbedtls_timing_hr_time timer; + uint32_t int_ms; + uint32_t fin_ms; +} mbedtls_timing_delay_context; + +#endif +#endif diff --git a/connectivity/mbedtls/platform/src/timing_mbed.cpp b/connectivity/mbedtls/platform/src/timing_mbed.cpp new file mode 100644 index 0000000000..dd35cb415e --- /dev/null +++ b/connectivity/mbedtls/platform/src/timing_mbed.cpp @@ -0,0 +1,145 @@ +/* + * timing.cpp + * + * Copyright The Mbed TLS Contributors + * Copyright (C) 2021, Arm Limited, All Rights Reserved + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#if !defined(MBEDTLS_CONFIG_FILE) +#include "mbedtls/config.h" +#else +#include MBEDTLS_CONFIG_FILE +#endif + +#if defined(MBEDTLS_TIMING_ALT) + +#include "mbedtls/timing.h" +#include "drivers/Timeout.h" +#include "drivers/LowPowerTimeout.h" +#include "drivers/Timer.h" +#include "drivers/LowPowerTimer.h" +#include + +extern "C" { + volatile int mbedtls_timing_alarmed = 0; +}; + +static void handle_alarm(void) +{ + mbedtls_timing_alarmed = 1; +} + +extern "C" void mbedtls_set_alarm(int seconds) +{ +#if DEVICE_LPTICKER + static mbed::LowPowerTimeout t; +#elif DEVICE_USTICKER + static mbed::Timeout t; +#else +#error "MBEDTLS_TIMING_C requires either LPTICKER or USTICKER" +#endif + + mbedtls_timing_alarmed = 0; + + t.attach(handle_alarm, std::chrono::seconds(seconds)); +} + +// The static Mbed timer here is initialized once only. +// Mbed TLS can have multiple timers (mbedtls_timing_hr_time) derived +// from the Mbed timer. +#if DEVICE_LPTICKER +static mbed::LowPowerTimer timer; +#elif DEVICE_USTICKER +static mbed::Timer timer; +#else +#error "MBEDTLS_TIMING_C requires either LPTICKER or USTICKER" +#endif +static int timer_init = 0; + +#if !defined(HAVE_HARDCLOCK) +#define HAVE_HARDCLOCK + +extern "C" unsigned long mbedtls_timing_hardclock(void) +{ + if (timer_init == 0) { + timer.reset(); + timer.start(); + timer_init = 1; + } + + return timer.elapsed_time().count(); +} +#endif /* !HAVE_HARDCLOCK */ + +extern "C" unsigned long mbedtls_timing_get_timer(struct mbedtls_timing_hr_time *val, int reset) +{ + if (timer_init == 0) { + timer.reset(); + timer.start(); + timer_init = 1; + } + + if (reset) { + val->start = std::chrono::duration_cast(timer.elapsed_time()).count(); + return 0; + } else { + return std::chrono::duration_cast(timer.elapsed_time()).count() - val->start; + } +} + +/** + * Note: The following implementations come from the default timing.c + * from Mbed TLS. They are disabled in timing.c when MBEDTLS_TIMING_ALT + * is defined, but the implementation is nonetheless applicable to + * Mbed OS, so we copy them over. + */ + +extern "C" void mbedtls_timing_set_delay(void *data, uint32_t int_ms, uint32_t fin_ms) +{ + mbedtls_timing_delay_context *ctx = (mbedtls_timing_delay_context *) data; + + ctx->int_ms = int_ms; + ctx->fin_ms = fin_ms; + + if (fin_ms != 0) { + (void) mbedtls_timing_get_timer(&ctx->timer, 1); + } +} + +extern "C" int mbedtls_timing_get_delay(void *data) +{ + mbedtls_timing_delay_context *ctx = (mbedtls_timing_delay_context *) data; + unsigned long elapsed_ms; + + if (ctx->fin_ms == 0) { + return -1; + } + + elapsed_ms = mbedtls_timing_get_timer(&ctx->timer, 0); + + if (elapsed_ms >= ctx->fin_ms) { + return 2; + } + + if (elapsed_ms >= ctx->int_ms) { + return 1; + } + + return 0; +} + +#endif // MBEDTLS_TIMING_ALT diff --git a/connectivity/mbedtls/source/aes.c b/connectivity/mbedtls/source/aes.c index ed48b24d3b..3f616427ac 100644 --- a/connectivity/mbedtls/source/aes.c +++ b/connectivity/mbedtls/source/aes.c @@ -730,6 +730,7 @@ exit: return( ret ); } +#endif /* !MBEDTLS_AES_SETKEY_DEC_ALT */ #if defined(MBEDTLS_CIPHER_MODE_XTS) static int mbedtls_aes_xts_decode_keys( const unsigned char *key, @@ -808,8 +809,6 @@ int mbedtls_aes_xts_setkey_dec( mbedtls_aes_xts_context *ctx, } #endif /* MBEDTLS_CIPHER_MODE_XTS */ -#endif /* !MBEDTLS_AES_SETKEY_DEC_ALT */ - #define AES_FROUND(X0,X1,X2,X3,Y0,Y1,Y2,Y3) \ do \ { \ @@ -867,63 +866,56 @@ int mbedtls_internal_aes_encrypt( mbedtls_aes_context *ctx, unsigned char output[16] ) { int i; - uint32_t *RK, X0, X1, X2, X3, Y0, Y1, Y2, Y3; + uint32_t *RK = ctx->rk; + struct + { + uint32_t X[4]; + uint32_t Y[4]; + } t; - RK = ctx->rk; - - GET_UINT32_LE( X0, input, 0 ); X0 ^= *RK++; - GET_UINT32_LE( X1, input, 4 ); X1 ^= *RK++; - GET_UINT32_LE( X2, input, 8 ); X2 ^= *RK++; - GET_UINT32_LE( X3, input, 12 ); X3 ^= *RK++; + GET_UINT32_LE( t.X[0], input, 0 ); t.X[0] ^= *RK++; + GET_UINT32_LE( t.X[1], input, 4 ); t.X[1] ^= *RK++; + GET_UINT32_LE( t.X[2], input, 8 ); t.X[2] ^= *RK++; + GET_UINT32_LE( t.X[3], input, 12 ); t.X[3] ^= *RK++; for( i = ( ctx->nr >> 1 ) - 1; i > 0; i-- ) { - AES_FROUND( Y0, Y1, Y2, Y3, X0, X1, X2, X3 ); - AES_FROUND( X0, X1, X2, X3, Y0, Y1, Y2, Y3 ); + AES_FROUND( t.Y[0], t.Y[1], t.Y[2], t.Y[3], t.X[0], t.X[1], t.X[2], t.X[3] ); + AES_FROUND( t.X[0], t.X[1], t.X[2], t.X[3], t.Y[0], t.Y[1], t.Y[2], t.Y[3] ); } - AES_FROUND( Y0, Y1, Y2, Y3, X0, X1, X2, X3 ); + AES_FROUND( t.Y[0], t.Y[1], t.Y[2], t.Y[3], t.X[0], t.X[1], t.X[2], t.X[3] ); - X0 = *RK++ ^ \ - ( (uint32_t) FSb[ ( Y0 ) & 0xFF ] ) ^ - ( (uint32_t) FSb[ ( Y1 >> 8 ) & 0xFF ] << 8 ) ^ - ( (uint32_t) FSb[ ( Y2 >> 16 ) & 0xFF ] << 16 ) ^ - ( (uint32_t) FSb[ ( Y3 >> 24 ) & 0xFF ] << 24 ); + t.X[0] = *RK++ ^ \ + ( (uint32_t) FSb[ ( t.Y[0] ) & 0xFF ] ) ^ + ( (uint32_t) FSb[ ( t.Y[1] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) FSb[ ( t.Y[2] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) FSb[ ( t.Y[3] >> 24 ) & 0xFF ] << 24 ); - X1 = *RK++ ^ \ - ( (uint32_t) FSb[ ( Y1 ) & 0xFF ] ) ^ - ( (uint32_t) FSb[ ( Y2 >> 8 ) & 0xFF ] << 8 ) ^ - ( (uint32_t) FSb[ ( Y3 >> 16 ) & 0xFF ] << 16 ) ^ - ( (uint32_t) FSb[ ( Y0 >> 24 ) & 0xFF ] << 24 ); + t.X[1] = *RK++ ^ \ + ( (uint32_t) FSb[ ( t.Y[1] ) & 0xFF ] ) ^ + ( (uint32_t) FSb[ ( t.Y[2] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) FSb[ ( t.Y[3] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) FSb[ ( t.Y[0] >> 24 ) & 0xFF ] << 24 ); - X2 = *RK++ ^ \ - ( (uint32_t) FSb[ ( Y2 ) & 0xFF ] ) ^ - ( (uint32_t) FSb[ ( Y3 >> 8 ) & 0xFF ] << 8 ) ^ - ( (uint32_t) FSb[ ( Y0 >> 16 ) & 0xFF ] << 16 ) ^ - ( (uint32_t) FSb[ ( Y1 >> 24 ) & 0xFF ] << 24 ); + t.X[2] = *RK++ ^ \ + ( (uint32_t) FSb[ ( t.Y[2] ) & 0xFF ] ) ^ + ( (uint32_t) FSb[ ( t.Y[3] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) FSb[ ( t.Y[0] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) FSb[ ( t.Y[1] >> 24 ) & 0xFF ] << 24 ); - X3 = *RK++ ^ \ - ( (uint32_t) FSb[ ( Y3 ) & 0xFF ] ) ^ - ( (uint32_t) FSb[ ( Y0 >> 8 ) & 0xFF ] << 8 ) ^ - ( (uint32_t) FSb[ ( Y1 >> 16 ) & 0xFF ] << 16 ) ^ - ( (uint32_t) FSb[ ( Y2 >> 24 ) & 0xFF ] << 24 ); + t.X[3] = *RK++ ^ \ + ( (uint32_t) FSb[ ( t.Y[3] ) & 0xFF ] ) ^ + ( (uint32_t) FSb[ ( t.Y[0] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) FSb[ ( t.Y[1] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) FSb[ ( t.Y[2] >> 24 ) & 0xFF ] << 24 ); - PUT_UINT32_LE( X0, output, 0 ); - PUT_UINT32_LE( X1, output, 4 ); - PUT_UINT32_LE( X2, output, 8 ); - PUT_UINT32_LE( X3, output, 12 ); + PUT_UINT32_LE( t.X[0], output, 0 ); + PUT_UINT32_LE( t.X[1], output, 4 ); + PUT_UINT32_LE( t.X[2], output, 8 ); + PUT_UINT32_LE( t.X[3], output, 12 ); - mbedtls_platform_zeroize( &X0, sizeof( X0 ) ); - mbedtls_platform_zeroize( &X1, sizeof( X1 ) ); - mbedtls_platform_zeroize( &X2, sizeof( X2 ) ); - mbedtls_platform_zeroize( &X3, sizeof( X3 ) ); - - mbedtls_platform_zeroize( &Y0, sizeof( Y0 ) ); - mbedtls_platform_zeroize( &Y1, sizeof( Y1 ) ); - mbedtls_platform_zeroize( &Y2, sizeof( Y2 ) ); - mbedtls_platform_zeroize( &Y3, sizeof( Y3 ) ); - - mbedtls_platform_zeroize( &RK, sizeof( RK ) ); + mbedtls_platform_zeroize( &t, sizeof( t ) ); return( 0 ); } @@ -947,63 +939,56 @@ int mbedtls_internal_aes_decrypt( mbedtls_aes_context *ctx, unsigned char output[16] ) { int i; - uint32_t *RK, X0, X1, X2, X3, Y0, Y1, Y2, Y3; + uint32_t *RK = ctx->rk; + struct + { + uint32_t X[4]; + uint32_t Y[4]; + } t; - RK = ctx->rk; - - GET_UINT32_LE( X0, input, 0 ); X0 ^= *RK++; - GET_UINT32_LE( X1, input, 4 ); X1 ^= *RK++; - GET_UINT32_LE( X2, input, 8 ); X2 ^= *RK++; - GET_UINT32_LE( X3, input, 12 ); X3 ^= *RK++; + GET_UINT32_LE( t.X[0], input, 0 ); t.X[0] ^= *RK++; + GET_UINT32_LE( t.X[1], input, 4 ); t.X[1] ^= *RK++; + GET_UINT32_LE( t.X[2], input, 8 ); t.X[2] ^= *RK++; + GET_UINT32_LE( t.X[3], input, 12 ); t.X[3] ^= *RK++; for( i = ( ctx->nr >> 1 ) - 1; i > 0; i-- ) { - AES_RROUND( Y0, Y1, Y2, Y3, X0, X1, X2, X3 ); - AES_RROUND( X0, X1, X2, X3, Y0, Y1, Y2, Y3 ); + AES_RROUND( t.Y[0], t.Y[1], t.Y[2], t.Y[3], t.X[0], t.X[1], t.X[2], t.X[3] ); + AES_RROUND( t.X[0], t.X[1], t.X[2], t.X[3], t.Y[0], t.Y[1], t.Y[2], t.Y[3] ); } - AES_RROUND( Y0, Y1, Y2, Y3, X0, X1, X2, X3 ); + AES_RROUND( t.Y[0], t.Y[1], t.Y[2], t.Y[3], t.X[0], t.X[1], t.X[2], t.X[3] ); - X0 = *RK++ ^ \ - ( (uint32_t) RSb[ ( Y0 ) & 0xFF ] ) ^ - ( (uint32_t) RSb[ ( Y3 >> 8 ) & 0xFF ] << 8 ) ^ - ( (uint32_t) RSb[ ( Y2 >> 16 ) & 0xFF ] << 16 ) ^ - ( (uint32_t) RSb[ ( Y1 >> 24 ) & 0xFF ] << 24 ); + t.X[0] = *RK++ ^ \ + ( (uint32_t) RSb[ ( t.Y[0] ) & 0xFF ] ) ^ + ( (uint32_t) RSb[ ( t.Y[3] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) RSb[ ( t.Y[2] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) RSb[ ( t.Y[1] >> 24 ) & 0xFF ] << 24 ); - X1 = *RK++ ^ \ - ( (uint32_t) RSb[ ( Y1 ) & 0xFF ] ) ^ - ( (uint32_t) RSb[ ( Y0 >> 8 ) & 0xFF ] << 8 ) ^ - ( (uint32_t) RSb[ ( Y3 >> 16 ) & 0xFF ] << 16 ) ^ - ( (uint32_t) RSb[ ( Y2 >> 24 ) & 0xFF ] << 24 ); + t.X[1] = *RK++ ^ \ + ( (uint32_t) RSb[ ( t.Y[1] ) & 0xFF ] ) ^ + ( (uint32_t) RSb[ ( t.Y[0] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) RSb[ ( t.Y[3] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) RSb[ ( t.Y[2] >> 24 ) & 0xFF ] << 24 ); - X2 = *RK++ ^ \ - ( (uint32_t) RSb[ ( Y2 ) & 0xFF ] ) ^ - ( (uint32_t) RSb[ ( Y1 >> 8 ) & 0xFF ] << 8 ) ^ - ( (uint32_t) RSb[ ( Y0 >> 16 ) & 0xFF ] << 16 ) ^ - ( (uint32_t) RSb[ ( Y3 >> 24 ) & 0xFF ] << 24 ); + t.X[2] = *RK++ ^ \ + ( (uint32_t) RSb[ ( t.Y[2] ) & 0xFF ] ) ^ + ( (uint32_t) RSb[ ( t.Y[1] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) RSb[ ( t.Y[0] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) RSb[ ( t.Y[3] >> 24 ) & 0xFF ] << 24 ); - X3 = *RK++ ^ \ - ( (uint32_t) RSb[ ( Y3 ) & 0xFF ] ) ^ - ( (uint32_t) RSb[ ( Y2 >> 8 ) & 0xFF ] << 8 ) ^ - ( (uint32_t) RSb[ ( Y1 >> 16 ) & 0xFF ] << 16 ) ^ - ( (uint32_t) RSb[ ( Y0 >> 24 ) & 0xFF ] << 24 ); + t.X[3] = *RK++ ^ \ + ( (uint32_t) RSb[ ( t.Y[3] ) & 0xFF ] ) ^ + ( (uint32_t) RSb[ ( t.Y[2] >> 8 ) & 0xFF ] << 8 ) ^ + ( (uint32_t) RSb[ ( t.Y[1] >> 16 ) & 0xFF ] << 16 ) ^ + ( (uint32_t) RSb[ ( t.Y[0] >> 24 ) & 0xFF ] << 24 ); - PUT_UINT32_LE( X0, output, 0 ); - PUT_UINT32_LE( X1, output, 4 ); - PUT_UINT32_LE( X2, output, 8 ); - PUT_UINT32_LE( X3, output, 12 ); + PUT_UINT32_LE( t.X[0], output, 0 ); + PUT_UINT32_LE( t.X[1], output, 4 ); + PUT_UINT32_LE( t.X[2], output, 8 ); + PUT_UINT32_LE( t.X[3], output, 12 ); - mbedtls_platform_zeroize( &X0, sizeof( X0 ) ); - mbedtls_platform_zeroize( &X1, sizeof( X1 ) ); - mbedtls_platform_zeroize( &X2, sizeof( X2 ) ); - mbedtls_platform_zeroize( &X3, sizeof( X3 ) ); - - mbedtls_platform_zeroize( &Y0, sizeof( Y0 ) ); - mbedtls_platform_zeroize( &Y1, sizeof( Y1 ) ); - mbedtls_platform_zeroize( &Y2, sizeof( Y2 ) ); - mbedtls_platform_zeroize( &Y3, sizeof( Y3 ) ); - - mbedtls_platform_zeroize( &RK, sizeof( RK ) ); + mbedtls_platform_zeroize( &t, sizeof( t ) ); return( 0 ); } diff --git a/connectivity/mbedtls/source/bignum.c b/connectivity/mbedtls/source/bignum.c index 9325632b42..9cc5d66e3a 100644 --- a/connectivity/mbedtls/source/bignum.c +++ b/connectivity/mbedtls/source/bignum.c @@ -1411,7 +1411,10 @@ int mbedtls_mpi_sub_abs( mbedtls_mpi *X, const mbedtls_mpi *A, const mbedtls_mpi /* If we ran out of space for the carry, it means that the result * is negative. */ if( n == X->n ) - return( MBEDTLS_ERR_MPI_NEGATIVE_VALUE ); + { + ret = MBEDTLS_ERR_MPI_NEGATIVE_VALUE; + goto cleanup; + } --X->p[n]; } @@ -2101,7 +2104,7 @@ int mbedtls_mpi_exp_mod( mbedtls_mpi *X, const mbedtls_mpi *A, size_t i, j, nblimbs; size_t bufsize, nbits; mbedtls_mpi_uint ei, mm, state; - mbedtls_mpi RR, T, W[ 2 << MBEDTLS_MPI_WINDOW_SIZE ], Apos; + mbedtls_mpi RR, T, W[ 1 << MBEDTLS_MPI_WINDOW_SIZE ], Apos; int neg; MPI_VALIDATE_RET( X != NULL ); @@ -2115,6 +2118,10 @@ int mbedtls_mpi_exp_mod( mbedtls_mpi *X, const mbedtls_mpi *A, if( mbedtls_mpi_cmp_int( E, 0 ) < 0 ) return( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + if( mbedtls_mpi_bitlen( E ) > MBEDTLS_MPI_MAX_BITS || + mbedtls_mpi_bitlen( N ) > MBEDTLS_MPI_MAX_BITS ) + return ( MBEDTLS_ERR_MPI_BAD_INPUT_DATA ); + /* * Init temps and window size */ @@ -2391,7 +2398,7 @@ int mbedtls_mpi_fill_random( mbedtls_mpi *X, size_t size, MBEDTLS_MPI_CHK( mbedtls_mpi_lset( X, 0 ) ); Xp = (unsigned char*) X->p; - f_rng( p_rng, Xp + overhead, size ); + MBEDTLS_MPI_CHK( f_rng( p_rng, Xp + overhead, size ) ); mpi_bigendian_to_host( X->p, limbs ); diff --git a/connectivity/mbedtls/source/ccm.c b/connectivity/mbedtls/source/ccm.c index e6ca588bab..424ee77b69 100644 --- a/connectivity/mbedtls/source/ccm.c +++ b/connectivity/mbedtls/source/ccm.c @@ -175,7 +175,7 @@ static int ccm_auth_crypt( mbedtls_ccm_context *ctx, int mode, size_t length, if( iv_len < 7 || iv_len > 13 ) return( MBEDTLS_ERR_CCM_BAD_INPUT ); - if( add_len > 0xFF00 ) + if( add_len >= 0xFF00 ) return( MBEDTLS_ERR_CCM_BAD_INPUT ); q = 16 - 1 - (unsigned char) iv_len; diff --git a/connectivity/mbedtls/source/check_crypto_config.h b/connectivity/mbedtls/source/check_crypto_config.h new file mode 100644 index 0000000000..cac90a0df2 --- /dev/null +++ b/connectivity/mbedtls/source/check_crypto_config.h @@ -0,0 +1,72 @@ +/** + * \file check_crypto_config.h + * + * \brief Consistency checks for PSA configuration options + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * It is recommended to include this file from your crypto_config.h + * in order to catch dependency issues early. + */ + +#ifndef MBEDTLS_CHECK_CRYPTO_CONFIG_H +#define MBEDTLS_CHECK_CRYPTO_CONFIG_H + +#if defined(PSA_WANT_ALG_DETERMINISTIC_ECDSA) && \ + !( defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR) || \ + defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) ) +#error "PSA_WANT_ALG_DETERMINISTIC_ECDSA defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_ECDSA) && \ + !( defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR) || \ + defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) ) +#error "PSA_WANT_ALG_ECDSA defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_RSA_PKCS1V15_CRYPT) && \ + !( defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR) || \ + defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) ) +#error "PSA_WANT_ALG_RSA_PKCS1V15_CRYPT defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_RSA_PKCS1V15_SIGN) && \ + !( defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR) || \ + defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) ) +#error "PSA_WANT_ALG_RSA_PKCS1V15_SIGN defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_RSA_OAEP) && \ + !( defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR) || \ + defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) ) +#error "PSA_WANT_ALG_RSA_OAEP defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_ALG_RSA_PSS) && \ + !( defined(PSA_WANT_KEY_TYPE_RSA_KEY_PAIR) || \ + defined(PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY) ) +#error "PSA_WANT_ALG_RSA_PSS defined, but not all prerequisites" +#endif + +#if defined(PSA_WANT_KEY_TYPE_ECC_KEY_PAIR) && \ + !defined(PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY) +#error "PSA_WANT_KEY_TYPE_ECC_KEY_PAIR defined, but not all prerequisites" +#endif + +#endif /* MBEDTLS_CHECK_CRYPTO_CONFIG_H */ diff --git a/connectivity/mbedtls/source/cipher.c b/connectivity/mbedtls/source/cipher.c index 853eeec203..457f8f6601 100644 --- a/connectivity/mbedtls/source/cipher.c +++ b/connectivity/mbedtls/source/cipher.c @@ -1288,23 +1288,16 @@ int mbedtls_cipher_crypt( mbedtls_cipher_context_t *ctx, #if defined(MBEDTLS_CIPHER_MODE_AEAD) /* - * Packet-oriented encryption for AEAD modes + * Packet-oriented encryption for AEAD modes: internal function shared by + * mbedtls_cipher_auth_encrypt() and mbedtls_cipher_auth_encrypt_ext(). */ -int mbedtls_cipher_auth_encrypt( mbedtls_cipher_context_t *ctx, +static int mbedtls_cipher_aead_encrypt( mbedtls_cipher_context_t *ctx, const unsigned char *iv, size_t iv_len, const unsigned char *ad, size_t ad_len, const unsigned char *input, size_t ilen, unsigned char *output, size_t *olen, unsigned char *tag, size_t tag_len ) { - CIPHER_VALIDATE_RET( ctx != NULL ); - CIPHER_VALIDATE_RET( iv != NULL ); - CIPHER_VALIDATE_RET( ad_len == 0 || ad != NULL ); - CIPHER_VALIDATE_RET( ilen == 0 || input != NULL ); - CIPHER_VALIDATE_RET( output != NULL ); - CIPHER_VALIDATE_RET( olen != NULL ); - CIPHER_VALIDATE_RET( tag_len == 0 || tag != NULL ); - #if defined(MBEDTLS_USE_PSA_CRYPTO) if( ctx->psa_enabled == 1 ) { @@ -1320,7 +1313,7 @@ int mbedtls_cipher_auth_encrypt( mbedtls_cipher_context_t *ctx, /* PSA Crypto API always writes the authentication tag * at the end of the encrypted message. */ - if( tag != output + ilen ) + if( output == NULL || tag != output + ilen ) return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE ); status = psa_aead_encrypt( cipher_psa->slot, @@ -1370,44 +1363,21 @@ int mbedtls_cipher_auth_encrypt( mbedtls_cipher_context_t *ctx, ilen, iv, ad, ad_len, input, output, tag ) ); } #endif /* MBEDTLS_CHACHAPOLY_C */ -#if defined(MBEDTLS_NIST_KW_C) - if( MBEDTLS_MODE_KW == ctx->cipher_info->mode || - MBEDTLS_MODE_KWP == ctx->cipher_info->mode ) - { - mbedtls_nist_kw_mode_t mode = ( MBEDTLS_MODE_KW == ctx->cipher_info->mode ) ? - MBEDTLS_KW_MODE_KW : MBEDTLS_KW_MODE_KWP; - - /* There is no iv, tag or ad associated with KW and KWP, these length should be 0 */ - if( iv_len != 0 || tag_len != 0 || ad_len != 0 ) - { - return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); - } - - return( mbedtls_nist_kw_wrap( ctx->cipher_ctx, mode, input, ilen, output, olen, SIZE_MAX ) ); - } -#endif /* MBEDTLS_NIST_KW_C */ return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE ); } /* - * Packet-oriented decryption for AEAD modes + * Packet-oriented encryption for AEAD modes: internal function shared by + * mbedtls_cipher_auth_encrypt() and mbedtls_cipher_auth_encrypt_ext(). */ -int mbedtls_cipher_auth_decrypt( mbedtls_cipher_context_t *ctx, +static int mbedtls_cipher_aead_decrypt( mbedtls_cipher_context_t *ctx, const unsigned char *iv, size_t iv_len, const unsigned char *ad, size_t ad_len, const unsigned char *input, size_t ilen, unsigned char *output, size_t *olen, const unsigned char *tag, size_t tag_len ) { - CIPHER_VALIDATE_RET( ctx != NULL ); - CIPHER_VALIDATE_RET( iv != NULL ); - CIPHER_VALIDATE_RET( ad_len == 0 || ad != NULL ); - CIPHER_VALIDATE_RET( ilen == 0 || input != NULL ); - CIPHER_VALIDATE_RET( output != NULL ); - CIPHER_VALIDATE_RET( olen != NULL ); - CIPHER_VALIDATE_RET( tag_len == 0 || tag != NULL ); - #if defined(MBEDTLS_USE_PSA_CRYPTO) if( ctx->psa_enabled == 1 ) { @@ -1423,7 +1393,7 @@ int mbedtls_cipher_auth_decrypt( mbedtls_cipher_context_t *ctx, /* PSA Crypto API always writes the authentication tag * at the end of the encrypted message. */ - if( tag != input + ilen ) + if( input == NULL || tag != input + ilen ) return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE ); status = psa_aead_decrypt( cipher_psa->slot, @@ -1495,25 +1465,169 @@ int mbedtls_cipher_auth_decrypt( mbedtls_cipher_context_t *ctx, return( ret ); } #endif /* MBEDTLS_CHACHAPOLY_C */ + + return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE ); +} + +#if !defined(MBEDTLS_DEPRECATED_REMOVED) +/* + * Packet-oriented encryption for AEAD modes: public legacy function. + */ +int mbedtls_cipher_auth_encrypt( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, + unsigned char *tag, size_t tag_len ) +{ + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( iv_len == 0 || iv != NULL ); + CIPHER_VALIDATE_RET( ad_len == 0 || ad != NULL ); + CIPHER_VALIDATE_RET( ilen == 0 || input != NULL ); + CIPHER_VALIDATE_RET( ilen == 0 || output != NULL ); + CIPHER_VALIDATE_RET( olen != NULL ); + CIPHER_VALIDATE_RET( tag_len == 0 || tag != NULL ); + + return( mbedtls_cipher_aead_encrypt( ctx, iv, iv_len, ad, ad_len, + input, ilen, output, olen, + tag, tag_len ) ); +} + +/* + * Packet-oriented decryption for AEAD modes: public legacy function. + */ +int mbedtls_cipher_auth_decrypt( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t *olen, + const unsigned char *tag, size_t tag_len ) +{ + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( iv_len == 0 || iv != NULL ); + CIPHER_VALIDATE_RET( ad_len == 0 || ad != NULL ); + CIPHER_VALIDATE_RET( ilen == 0 || input != NULL ); + CIPHER_VALIDATE_RET( ilen == 0 || output != NULL ); + CIPHER_VALIDATE_RET( olen != NULL ); + CIPHER_VALIDATE_RET( tag_len == 0 || tag != NULL ); + + return( mbedtls_cipher_aead_decrypt( ctx, iv, iv_len, ad, ad_len, + input, ilen, output, olen, + tag, tag_len ) ); +} +#endif /* !MBEDTLS_DEPRECATED_REMOVED */ +#endif /* MBEDTLS_CIPHER_MODE_AEAD */ + +#if defined(MBEDTLS_CIPHER_MODE_AEAD) || defined(MBEDTLS_NIST_KW_C) +/* + * Packet-oriented encryption for AEAD/NIST_KW: public function. + */ +int mbedtls_cipher_auth_encrypt_ext( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t output_len, + size_t *olen, size_t tag_len ) +{ + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( iv_len == 0 || iv != NULL ); + CIPHER_VALIDATE_RET( ad_len == 0 || ad != NULL ); + CIPHER_VALIDATE_RET( ilen == 0 || input != NULL ); + CIPHER_VALIDATE_RET( output != NULL ); + CIPHER_VALIDATE_RET( olen != NULL ); + #if defined(MBEDTLS_NIST_KW_C) - if( MBEDTLS_MODE_KW == ctx->cipher_info->mode || - MBEDTLS_MODE_KWP == ctx->cipher_info->mode ) + if( +#if defined(MBEDTLS_USE_PSA_CRYPTO) + ctx->psa_enabled == 0 && +#endif + ( MBEDTLS_MODE_KW == ctx->cipher_info->mode || + MBEDTLS_MODE_KWP == ctx->cipher_info->mode ) ) { mbedtls_nist_kw_mode_t mode = ( MBEDTLS_MODE_KW == ctx->cipher_info->mode ) ? MBEDTLS_KW_MODE_KW : MBEDTLS_KW_MODE_KWP; - /* There is no iv, tag or ad associated with KW and KWP, these length should be 0 */ + /* There is no iv, tag or ad associated with KW and KWP, + * so these length should be 0 as documented. */ if( iv_len != 0 || tag_len != 0 || ad_len != 0 ) - { return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); - } - return( mbedtls_nist_kw_unwrap( ctx->cipher_ctx, mode, input, ilen, output, olen, SIZE_MAX ) ); + (void) iv; + (void) ad; + + return( mbedtls_nist_kw_wrap( ctx->cipher_ctx, mode, input, ilen, + output, olen, output_len ) ); } #endif /* MBEDTLS_NIST_KW_C */ +#if defined(MBEDTLS_CIPHER_MODE_AEAD) + /* AEAD case: check length before passing on to shared function */ + if( output_len < ilen + tag_len ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + int ret = mbedtls_cipher_aead_encrypt( ctx, iv, iv_len, ad, ad_len, + input, ilen, output, olen, + output + ilen, tag_len ); + *olen += tag_len; + return( ret ); +#else return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE ); -} #endif /* MBEDTLS_CIPHER_MODE_AEAD */ +} + +/* + * Packet-oriented decryption for AEAD/NIST_KW: public function. + */ +int mbedtls_cipher_auth_decrypt_ext( mbedtls_cipher_context_t *ctx, + const unsigned char *iv, size_t iv_len, + const unsigned char *ad, size_t ad_len, + const unsigned char *input, size_t ilen, + unsigned char *output, size_t output_len, + size_t *olen, size_t tag_len ) +{ + CIPHER_VALIDATE_RET( ctx != NULL ); + CIPHER_VALIDATE_RET( iv_len == 0 || iv != NULL ); + CIPHER_VALIDATE_RET( ad_len == 0 || ad != NULL ); + CIPHER_VALIDATE_RET( ilen == 0 || input != NULL ); + CIPHER_VALIDATE_RET( output_len == 0 || output != NULL ); + CIPHER_VALIDATE_RET( olen != NULL ); + +#if defined(MBEDTLS_NIST_KW_C) + if( +#if defined(MBEDTLS_USE_PSA_CRYPTO) + ctx->psa_enabled == 0 && +#endif + ( MBEDTLS_MODE_KW == ctx->cipher_info->mode || + MBEDTLS_MODE_KWP == ctx->cipher_info->mode ) ) + { + mbedtls_nist_kw_mode_t mode = ( MBEDTLS_MODE_KW == ctx->cipher_info->mode ) ? + MBEDTLS_KW_MODE_KW : MBEDTLS_KW_MODE_KWP; + + /* There is no iv, tag or ad associated with KW and KWP, + * so these length should be 0 as documented. */ + if( iv_len != 0 || tag_len != 0 || ad_len != 0 ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + (void) iv; + (void) ad; + + return( mbedtls_nist_kw_unwrap( ctx->cipher_ctx, mode, input, ilen, + output, olen, output_len ) ); + } +#endif /* MBEDTLS_NIST_KW_C */ + +#if defined(MBEDTLS_CIPHER_MODE_AEAD) + /* AEAD case: check length before passing on to shared function */ + if( ilen < tag_len || output_len < ilen - tag_len ) + return( MBEDTLS_ERR_CIPHER_BAD_INPUT_DATA ); + + return( mbedtls_cipher_aead_decrypt( ctx, iv, iv_len, ad, ad_len, + input, ilen - tag_len, output, olen, + input + ilen - tag_len, tag_len ) ); +#else + return( MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE ); +#endif /* MBEDTLS_CIPHER_MODE_AEAD */ +} +#endif /* MBEDTLS_CIPHER_MODE_AEAD || MBEDTLS_NIST_KW_C */ #endif /* MBEDTLS_CIPHER_C */ diff --git a/connectivity/mbedtls/source/cipher_wrap.c b/connectivity/mbedtls/source/cipher_wrap.c index 8eb2ec02b8..57eb3cb67f 100644 --- a/connectivity/mbedtls/source/cipher_wrap.c +++ b/connectivity/mbedtls/source/cipher_wrap.c @@ -753,7 +753,7 @@ static const mbedtls_cipher_info_t camellia_128_ecb_info = { MBEDTLS_MODE_ECB, 128, "CAMELLIA-128-ECB", - 16, + 0, 0, 16, &camellia_info @@ -764,7 +764,7 @@ static const mbedtls_cipher_info_t camellia_192_ecb_info = { MBEDTLS_MODE_ECB, 192, "CAMELLIA-192-ECB", - 16, + 0, 0, 16, &camellia_info @@ -775,7 +775,7 @@ static const mbedtls_cipher_info_t camellia_256_ecb_info = { MBEDTLS_MODE_ECB, 256, "CAMELLIA-256-ECB", - 16, + 0, 0, 16, &camellia_info @@ -1129,7 +1129,7 @@ static const mbedtls_cipher_info_t aria_128_ecb_info = { MBEDTLS_MODE_ECB, 128, "ARIA-128-ECB", - 16, + 0, 0, 16, &aria_info @@ -1140,7 +1140,7 @@ static const mbedtls_cipher_info_t aria_192_ecb_info = { MBEDTLS_MODE_ECB, 192, "ARIA-192-ECB", - 16, + 0, 0, 16, &aria_info @@ -1151,7 +1151,7 @@ static const mbedtls_cipher_info_t aria_256_ecb_info = { MBEDTLS_MODE_ECB, 256, "ARIA-256-ECB", - 16, + 0, 0, 16, &aria_info @@ -1553,7 +1553,7 @@ static const mbedtls_cipher_info_t des_ecb_info = { MBEDTLS_MODE_ECB, MBEDTLS_KEY_LENGTH_DES, "DES-ECB", - 8, + 0, 0, 8, &des_info @@ -1604,7 +1604,7 @@ static const mbedtls_cipher_info_t des_ede_ecb_info = { MBEDTLS_MODE_ECB, MBEDTLS_KEY_LENGTH_DES_EDE, "DES-EDE-ECB", - 8, + 0, 0, 8, &des_ede_info @@ -1655,7 +1655,7 @@ static const mbedtls_cipher_info_t des_ede3_ecb_info = { MBEDTLS_MODE_ECB, MBEDTLS_KEY_LENGTH_DES_EDE3, "DES-EDE3-ECB", - 8, + 0, 0, 8, &des_ede3_info @@ -1770,7 +1770,7 @@ static const mbedtls_cipher_info_t blowfish_ecb_info = { MBEDTLS_MODE_ECB, 128, "BLOWFISH-ECB", - 8, + 0, MBEDTLS_CIPHER_VARIABLE_KEY_LEN, 8, &blowfish_info diff --git a/connectivity/mbedtls/source/cmac.c b/connectivity/mbedtls/source/cmac.c index 816bf13da3..59ece155ee 100644 --- a/connectivity/mbedtls/source/cmac.c +++ b/connectivity/mbedtls/source/cmac.c @@ -420,7 +420,7 @@ exit: */ int mbedtls_aes_cmac_prf_128( const unsigned char *key, size_t key_length, const unsigned char *input, size_t in_len, - unsigned char *output ) + unsigned char output[16] ) { int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; const mbedtls_cipher_info_t *cipher_info; diff --git a/connectivity/mbedtls/source/ctr_drbg.c b/connectivity/mbedtls/source/ctr_drbg.c index 54843a7be6..023aac51a3 100644 --- a/connectivity/mbedtls/source/ctr_drbg.c +++ b/connectivity/mbedtls/source/ctr_drbg.c @@ -55,11 +55,17 @@ void mbedtls_ctr_drbg_init( mbedtls_ctr_drbg_context *ctx ) * See mbedtls_ctr_drbg_set_nonce_len(). */ ctx->reseed_counter = -1; + ctx->reseed_interval = MBEDTLS_CTR_DRBG_RESEED_INTERVAL; + #if defined(MBEDTLS_THREADING_C) mbedtls_mutex_init( &ctx->mutex ); #endif } +/* + * This function resets CTR_DRBG context to the state immediately + * after initial call of mbedtls_ctr_drbg_init(). + */ void mbedtls_ctr_drbg_free( mbedtls_ctr_drbg_context *ctx ) { if( ctx == NULL ) @@ -70,6 +76,11 @@ void mbedtls_ctr_drbg_free( mbedtls_ctr_drbg_context *ctx ) #endif mbedtls_aes_free( &ctx->aes_ctx ); mbedtls_platform_zeroize( ctx, sizeof( mbedtls_ctr_drbg_context ) ); + ctx->reseed_interval = MBEDTLS_CTR_DRBG_RESEED_INTERVAL; + ctx->reseed_counter = -1; +#if defined(MBEDTLS_THREADING_C) + mbedtls_mutex_init( &ctx->mutex ); +#endif } void mbedtls_ctr_drbg_set_prediction_resistance( mbedtls_ctr_drbg_context *ctx, @@ -468,8 +479,6 @@ int mbedtls_ctr_drbg_seed( mbedtls_ctr_drbg_context *ctx, (size_t) ctx->reseed_counter : good_nonce_len( ctx->entropy_len ) ); - ctx->reseed_interval = MBEDTLS_CTR_DRBG_RESEED_INTERVAL; - /* Initialize with an empty key. */ if( ( ret = mbedtls_aes_setkey_enc( &ctx->aes_ctx, key, MBEDTLS_CTR_DRBG_KEYBITS ) ) != 0 ) diff --git a/connectivity/mbedtls/source/ecp.c b/connectivity/mbedtls/source/ecp.c index 5d00de5cf9..05a0b0175c 100644 --- a/connectivity/mbedtls/source/ecp.c +++ b/connectivity/mbedtls/source/ecp.c @@ -546,8 +546,11 @@ static const mbedtls_ecp_curve_info ecp_supported_curves[] = #if defined(MBEDTLS_ECP_DP_SECP192K1_ENABLED) { MBEDTLS_ECP_DP_SECP192K1, 18, 192, "secp192k1" }, #endif -#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) && defined(MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED) +#if defined(MBEDTLS_ECP_DP_CURVE25519_ENABLED) { MBEDTLS_ECP_DP_CURVE25519, 29, 256, "x25519" }, +#endif +#if defined(MBEDTLS_ECP_DP_CURVE448_ENABLED) + { MBEDTLS_ECP_DP_CURVE448, 30, 448, "x448" }, #endif { MBEDTLS_ECP_DP_NONE, 0, 0, NULL }, }; diff --git a/connectivity/mbedtls/source/ecp_curves.c b/connectivity/mbedtls/source/ecp_curves.c index 05df307cbe..839fb5e36e 100644 --- a/connectivity/mbedtls/source/ecp_curves.c +++ b/connectivity/mbedtls/source/ecp_curves.c @@ -1033,7 +1033,7 @@ static inline void sub32( uint32_t *dst, uint32_t src, signed char *carry ) STORE32; i++; \ cur = c > 0 ? c : 0; STORE32; \ cur = 0; while( ++i < MAX32 ) { STORE32; } \ - if( c < 0 ) fix_negative( N, c, &C, bits ); + if( c < 0 ) MBEDTLS_MPI_CHK( fix_negative( N, c, &C, bits ) ); /* * If the result is negative, we get it in the form diff --git a/connectivity/mbedtls/source/entropy_poll.c b/connectivity/mbedtls/source/entropy_poll.c index 4bf660e055..5250a7bfec 100644 --- a/connectivity/mbedtls/source/entropy_poll.c +++ b/connectivity/mbedtls/source/entropy_poll.c @@ -17,7 +17,7 @@ * limitations under the License. */ -#if defined(__linux__) +#if defined(__linux__) && !defined(_GNU_SOURCE) /* Ensure that syscall() is available even when compiling with -std=c99 */ #define _GNU_SOURCE #endif diff --git a/connectivity/mbedtls/source/error.c b/connectivity/mbedtls/source/error.c index cba61e9e7e..901a3699ae 100644 --- a/connectivity/mbedtls/source/error.c +++ b/connectivity/mbedtls/source/error.c @@ -19,20 +19,20 @@ #include "common.h" -#if defined(MBEDTLS_ERROR_STRERROR_DUMMY) -#include -#endif +#include "mbedtls/error.h" + +#if defined(MBEDTLS_ERROR_C) || defined(MBEDTLS_ERROR_STRERROR_DUMMY) + +#if defined(MBEDTLS_ERROR_C) #if defined(MBEDTLS_PLATFORM_C) #include "mbedtls/platform.h" #else #define mbedtls_snprintf snprintf -#define mbedtls_time_t time_t #endif -#if defined(MBEDTLS_ERROR_C) - #include +#include #if defined(MBEDTLS_AES_C) #include "mbedtls/aes.h" @@ -960,8 +960,6 @@ void mbedtls_strerror( int ret, char *buf, size_t buflen ) #else /* MBEDTLS_ERROR_C */ -#if defined(MBEDTLS_ERROR_STRERROR_DUMMY) - /* * Provide an non-function in case MBEDTLS_ERROR_C is not defined */ @@ -973,6 +971,6 @@ void mbedtls_strerror( int ret, char *buf, size_t buflen ) buf[0] = '\0'; } -#endif /* MBEDTLS_ERROR_STRERROR_DUMMY */ - #endif /* MBEDTLS_ERROR_C */ + +#endif /* MBEDTLS_ERROR_C || MBEDTLS_ERROR_STRERROR_DUMMY */ diff --git a/connectivity/mbedtls/source/hmac_drbg.c b/connectivity/mbedtls/source/hmac_drbg.c index aa3e251040..25a0225835 100644 --- a/connectivity/mbedtls/source/hmac_drbg.c +++ b/connectivity/mbedtls/source/hmac_drbg.c @@ -53,6 +53,8 @@ void mbedtls_hmac_drbg_init( mbedtls_hmac_drbg_context *ctx ) { memset( ctx, 0, sizeof( mbedtls_hmac_drbg_context ) ); + ctx->reseed_interval = MBEDTLS_HMAC_DRBG_RESEED_INTERVAL; + #if defined(MBEDTLS_THREADING_C) mbedtls_mutex_init( &ctx->mutex ); #endif @@ -266,8 +268,6 @@ int mbedtls_hmac_drbg_seed( mbedtls_hmac_drbg_context *ctx, ctx->f_entropy = f_entropy; ctx->p_entropy = p_entropy; - ctx->reseed_interval = MBEDTLS_HMAC_DRBG_RESEED_INTERVAL; - if( ctx->entropy_len == 0 ) { /* @@ -412,7 +412,8 @@ int mbedtls_hmac_drbg_random( void *p_rng, unsigned char *output, size_t out_len } /* - * Free an HMAC_DRBG context + * This function resets HMAC_DRBG context to the state immediately + * after initial call of mbedtls_hmac_drbg_init(). */ void mbedtls_hmac_drbg_free( mbedtls_hmac_drbg_context *ctx ) { @@ -424,6 +425,10 @@ void mbedtls_hmac_drbg_free( mbedtls_hmac_drbg_context *ctx ) #endif mbedtls_md_free( &ctx->md_ctx ); mbedtls_platform_zeroize( ctx, sizeof( mbedtls_hmac_drbg_context ) ); + ctx->reseed_interval = MBEDTLS_HMAC_DRBG_RESEED_INTERVAL; +#if defined(MBEDTLS_THREADING_C) + mbedtls_mutex_init( &ctx->mutex ); +#endif } #if defined(MBEDTLS_FS_IO) diff --git a/connectivity/mbedtls/source/md2.c b/connectivity/mbedtls/source/md2.c index 5ebf07232a..7264e30313 100644 --- a/connectivity/mbedtls/source/md2.c +++ b/connectivity/mbedtls/source/md2.c @@ -147,6 +147,9 @@ int mbedtls_internal_md2_process( mbedtls_md2_context *ctx ) t = ctx->cksum[i]; } + /* Zeroise variables to clear sensitive data from memory. */ + mbedtls_platform_zeroize( &t, sizeof( t ) ); + return( 0 ); } @@ -287,8 +290,7 @@ static const unsigned char md2_test_str[7][81] = { "message digest" }, { "abcdefghijklmnopqrstuvwxyz" }, { "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789" }, - { "12345678901234567890123456789012345678901234567890123456789012" - "345678901234567890" } + { "12345678901234567890123456789012345678901234567890123456789012345678901234567890" } }; static const size_t md2_test_strlen[7] = diff --git a/connectivity/mbedtls/source/md4.c b/connectivity/mbedtls/source/md4.c index ac9507454b..4fd6bc3e45 100644 --- a/connectivity/mbedtls/source/md4.c +++ b/connectivity/mbedtls/source/md4.c @@ -113,31 +113,34 @@ void mbedtls_md4_starts( mbedtls_md4_context *ctx ) int mbedtls_internal_md4_process( mbedtls_md4_context *ctx, const unsigned char data[64] ) { - uint32_t X[16], A, B, C, D; + struct + { + uint32_t X[16], A, B, C, D; + } local; - GET_UINT32_LE( X[ 0], data, 0 ); - GET_UINT32_LE( X[ 1], data, 4 ); - GET_UINT32_LE( X[ 2], data, 8 ); - GET_UINT32_LE( X[ 3], data, 12 ); - GET_UINT32_LE( X[ 4], data, 16 ); - GET_UINT32_LE( X[ 5], data, 20 ); - GET_UINT32_LE( X[ 6], data, 24 ); - GET_UINT32_LE( X[ 7], data, 28 ); - GET_UINT32_LE( X[ 8], data, 32 ); - GET_UINT32_LE( X[ 9], data, 36 ); - GET_UINT32_LE( X[10], data, 40 ); - GET_UINT32_LE( X[11], data, 44 ); - GET_UINT32_LE( X[12], data, 48 ); - GET_UINT32_LE( X[13], data, 52 ); - GET_UINT32_LE( X[14], data, 56 ); - GET_UINT32_LE( X[15], data, 60 ); + GET_UINT32_LE( local.X[ 0], data, 0 ); + GET_UINT32_LE( local.X[ 1], data, 4 ); + GET_UINT32_LE( local.X[ 2], data, 8 ); + GET_UINT32_LE( local.X[ 3], data, 12 ); + GET_UINT32_LE( local.X[ 4], data, 16 ); + GET_UINT32_LE( local.X[ 5], data, 20 ); + GET_UINT32_LE( local.X[ 6], data, 24 ); + GET_UINT32_LE( local.X[ 7], data, 28 ); + GET_UINT32_LE( local.X[ 8], data, 32 ); + GET_UINT32_LE( local.X[ 9], data, 36 ); + GET_UINT32_LE( local.X[10], data, 40 ); + GET_UINT32_LE( local.X[11], data, 44 ); + GET_UINT32_LE( local.X[12], data, 48 ); + GET_UINT32_LE( local.X[13], data, 52 ); + GET_UINT32_LE( local.X[14], data, 56 ); + GET_UINT32_LE( local.X[15], data, 60 ); #define S(x,n) (((x) << (n)) | (((x) & 0xFFFFFFFF) >> (32 - (n)))) - A = ctx->state[0]; - B = ctx->state[1]; - C = ctx->state[2]; - D = ctx->state[3]; + local.A = ctx->state[0]; + local.B = ctx->state[1]; + local.C = ctx->state[2]; + local.D = ctx->state[3]; #define F(x, y, z) (((x) & (y)) | ((~(x)) & (z))) #define P(a,b,c,d,x,s) \ @@ -148,22 +151,22 @@ int mbedtls_internal_md4_process( mbedtls_md4_context *ctx, } while( 0 ) - P( A, B, C, D, X[ 0], 3 ); - P( D, A, B, C, X[ 1], 7 ); - P( C, D, A, B, X[ 2], 11 ); - P( B, C, D, A, X[ 3], 19 ); - P( A, B, C, D, X[ 4], 3 ); - P( D, A, B, C, X[ 5], 7 ); - P( C, D, A, B, X[ 6], 11 ); - P( B, C, D, A, X[ 7], 19 ); - P( A, B, C, D, X[ 8], 3 ); - P( D, A, B, C, X[ 9], 7 ); - P( C, D, A, B, X[10], 11 ); - P( B, C, D, A, X[11], 19 ); - P( A, B, C, D, X[12], 3 ); - P( D, A, B, C, X[13], 7 ); - P( C, D, A, B, X[14], 11 ); - P( B, C, D, A, X[15], 19 ); + P( local.A, local.B, local.C, local.D, local.X[ 0], 3 ); + P( local.D, local.A, local.B, local.C, local.X[ 1], 7 ); + P( local.C, local.D, local.A, local.B, local.X[ 2], 11 ); + P( local.B, local.C, local.D, local.A, local.X[ 3], 19 ); + P( local.A, local.B, local.C, local.D, local.X[ 4], 3 ); + P( local.D, local.A, local.B, local.C, local.X[ 5], 7 ); + P( local.C, local.D, local.A, local.B, local.X[ 6], 11 ); + P( local.B, local.C, local.D, local.A, local.X[ 7], 19 ); + P( local.A, local.B, local.C, local.D, local.X[ 8], 3 ); + P( local.D, local.A, local.B, local.C, local.X[ 9], 7 ); + P( local.C, local.D, local.A, local.B, local.X[10], 11 ); + P( local.B, local.C, local.D, local.A, local.X[11], 19 ); + P( local.A, local.B, local.C, local.D, local.X[12], 3 ); + P( local.D, local.A, local.B, local.C, local.X[13], 7 ); + P( local.C, local.D, local.A, local.B, local.X[14], 11 ); + P( local.B, local.C, local.D, local.A, local.X[15], 19 ); #undef P #undef F @@ -176,22 +179,22 @@ int mbedtls_internal_md4_process( mbedtls_md4_context *ctx, (a) = S((a),(s)); \ } while( 0 ) - P( A, B, C, D, X[ 0], 3 ); - P( D, A, B, C, X[ 4], 5 ); - P( C, D, A, B, X[ 8], 9 ); - P( B, C, D, A, X[12], 13 ); - P( A, B, C, D, X[ 1], 3 ); - P( D, A, B, C, X[ 5], 5 ); - P( C, D, A, B, X[ 9], 9 ); - P( B, C, D, A, X[13], 13 ); - P( A, B, C, D, X[ 2], 3 ); - P( D, A, B, C, X[ 6], 5 ); - P( C, D, A, B, X[10], 9 ); - P( B, C, D, A, X[14], 13 ); - P( A, B, C, D, X[ 3], 3 ); - P( D, A, B, C, X[ 7], 5 ); - P( C, D, A, B, X[11], 9 ); - P( B, C, D, A, X[15], 13 ); + P( local.A, local.B, local.C, local.D, local.X[ 0], 3 ); + P( local.D, local.A, local.B, local.C, local.X[ 4], 5 ); + P( local.C, local.D, local.A, local.B, local.X[ 8], 9 ); + P( local.B, local.C, local.D, local.A, local.X[12], 13 ); + P( local.A, local.B, local.C, local.D, local.X[ 1], 3 ); + P( local.D, local.A, local.B, local.C, local.X[ 5], 5 ); + P( local.C, local.D, local.A, local.B, local.X[ 9], 9 ); + P( local.B, local.C, local.D, local.A, local.X[13], 13 ); + P( local.A, local.B, local.C, local.D, local.X[ 2], 3 ); + P( local.D, local.A, local.B, local.C, local.X[ 6], 5 ); + P( local.C, local.D, local.A, local.B, local.X[10], 9 ); + P( local.B, local.C, local.D, local.A, local.X[14], 13 ); + P( local.A, local.B, local.C, local.D, local.X[ 3], 3 ); + P( local.D, local.A, local.B, local.C, local.X[ 7], 5 ); + P( local.C, local.D, local.A, local.B, local.X[11], 9 ); + P( local.B, local.C, local.D, local.A, local.X[15], 13 ); #undef P #undef F @@ -204,30 +207,33 @@ int mbedtls_internal_md4_process( mbedtls_md4_context *ctx, (a) = S((a),(s)); \ } while( 0 ) - P( A, B, C, D, X[ 0], 3 ); - P( D, A, B, C, X[ 8], 9 ); - P( C, D, A, B, X[ 4], 11 ); - P( B, C, D, A, X[12], 15 ); - P( A, B, C, D, X[ 2], 3 ); - P( D, A, B, C, X[10], 9 ); - P( C, D, A, B, X[ 6], 11 ); - P( B, C, D, A, X[14], 15 ); - P( A, B, C, D, X[ 1], 3 ); - P( D, A, B, C, X[ 9], 9 ); - P( C, D, A, B, X[ 5], 11 ); - P( B, C, D, A, X[13], 15 ); - P( A, B, C, D, X[ 3], 3 ); - P( D, A, B, C, X[11], 9 ); - P( C, D, A, B, X[ 7], 11 ); - P( B, C, D, A, X[15], 15 ); + P( local.A, local.B, local.C, local.D, local.X[ 0], 3 ); + P( local.D, local.A, local.B, local.C, local.X[ 8], 9 ); + P( local.C, local.D, local.A, local.B, local.X[ 4], 11 ); + P( local.B, local.C, local.D, local.A, local.X[12], 15 ); + P( local.A, local.B, local.C, local.D, local.X[ 2], 3 ); + P( local.D, local.A, local.B, local.C, local.X[10], 9 ); + P( local.C, local.D, local.A, local.B, local.X[ 6], 11 ); + P( local.B, local.C, local.D, local.A, local.X[14], 15 ); + P( local.A, local.B, local.C, local.D, local.X[ 1], 3 ); + P( local.D, local.A, local.B, local.C, local.X[ 9], 9 ); + P( local.C, local.D, local.A, local.B, local.X[ 5], 11 ); + P( local.B, local.C, local.D, local.A, local.X[13], 15 ); + P( local.A, local.B, local.C, local.D, local.X[ 3], 3 ); + P( local.D, local.A, local.B, local.C, local.X[11], 9 ); + P( local.C, local.D, local.A, local.B, local.X[ 7], 11 ); + P( local.B, local.C, local.D, local.A, local.X[15], 15 ); #undef F #undef P - ctx->state[0] += A; - ctx->state[1] += B; - ctx->state[2] += C; - ctx->state[3] += D; + ctx->state[0] += local.A; + ctx->state[1] += local.B; + ctx->state[2] += local.C; + ctx->state[3] += local.D; + + /* Zeroise variables to clear sensitive data from memory. */ + mbedtls_platform_zeroize( &local, sizeof( local ) ); return( 0 ); } @@ -408,8 +414,7 @@ static const unsigned char md4_test_str[7][81] = { "message digest" }, { "abcdefghijklmnopqrstuvwxyz" }, { "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789" }, - { "12345678901234567890123456789012345678901234567890123456789012" - "345678901234567890" } + { "12345678901234567890123456789012345678901234567890123456789012345678901234567890" } }; static const size_t md4_test_strlen[7] = diff --git a/connectivity/mbedtls/source/md5.c b/connectivity/mbedtls/source/md5.c index 8cea902aea..c4f2dbfac8 100644 --- a/connectivity/mbedtls/source/md5.c +++ b/connectivity/mbedtls/source/md5.c @@ -112,128 +112,134 @@ void mbedtls_md5_starts( mbedtls_md5_context *ctx ) int mbedtls_internal_md5_process( mbedtls_md5_context *ctx, const unsigned char data[64] ) { - uint32_t X[16], A, B, C, D; + struct + { + uint32_t X[16], A, B, C, D; + } local; - GET_UINT32_LE( X[ 0], data, 0 ); - GET_UINT32_LE( X[ 1], data, 4 ); - GET_UINT32_LE( X[ 2], data, 8 ); - GET_UINT32_LE( X[ 3], data, 12 ); - GET_UINT32_LE( X[ 4], data, 16 ); - GET_UINT32_LE( X[ 5], data, 20 ); - GET_UINT32_LE( X[ 6], data, 24 ); - GET_UINT32_LE( X[ 7], data, 28 ); - GET_UINT32_LE( X[ 8], data, 32 ); - GET_UINT32_LE( X[ 9], data, 36 ); - GET_UINT32_LE( X[10], data, 40 ); - GET_UINT32_LE( X[11], data, 44 ); - GET_UINT32_LE( X[12], data, 48 ); - GET_UINT32_LE( X[13], data, 52 ); - GET_UINT32_LE( X[14], data, 56 ); - GET_UINT32_LE( X[15], data, 60 ); + GET_UINT32_LE( local.X[ 0], data, 0 ); + GET_UINT32_LE( local.X[ 1], data, 4 ); + GET_UINT32_LE( local.X[ 2], data, 8 ); + GET_UINT32_LE( local.X[ 3], data, 12 ); + GET_UINT32_LE( local.X[ 4], data, 16 ); + GET_UINT32_LE( local.X[ 5], data, 20 ); + GET_UINT32_LE( local.X[ 6], data, 24 ); + GET_UINT32_LE( local.X[ 7], data, 28 ); + GET_UINT32_LE( local.X[ 8], data, 32 ); + GET_UINT32_LE( local.X[ 9], data, 36 ); + GET_UINT32_LE( local.X[10], data, 40 ); + GET_UINT32_LE( local.X[11], data, 44 ); + GET_UINT32_LE( local.X[12], data, 48 ); + GET_UINT32_LE( local.X[13], data, 52 ); + GET_UINT32_LE( local.X[14], data, 56 ); + GET_UINT32_LE( local.X[15], data, 60 ); #define S(x,n) \ ( ( (x) << (n) ) | ( ( (x) & 0xFFFFFFFF) >> ( 32 - (n) ) ) ) -#define P(a,b,c,d,k,s,t) \ - do \ - { \ - (a) += F((b),(c),(d)) + X[(k)] + (t); \ - (a) = S((a),(s)) + (b); \ +#define P(a,b,c,d,k,s,t) \ + do \ + { \ + (a) += F((b),(c),(d)) + local.X[(k)] + (t); \ + (a) = S((a),(s)) + (b); \ } while( 0 ) - A = ctx->state[0]; - B = ctx->state[1]; - C = ctx->state[2]; - D = ctx->state[3]; + local.A = ctx->state[0]; + local.B = ctx->state[1]; + local.C = ctx->state[2]; + local.D = ctx->state[3]; #define F(x,y,z) ((z) ^ ((x) & ((y) ^ (z)))) - P( A, B, C, D, 0, 7, 0xD76AA478 ); - P( D, A, B, C, 1, 12, 0xE8C7B756 ); - P( C, D, A, B, 2, 17, 0x242070DB ); - P( B, C, D, A, 3, 22, 0xC1BDCEEE ); - P( A, B, C, D, 4, 7, 0xF57C0FAF ); - P( D, A, B, C, 5, 12, 0x4787C62A ); - P( C, D, A, B, 6, 17, 0xA8304613 ); - P( B, C, D, A, 7, 22, 0xFD469501 ); - P( A, B, C, D, 8, 7, 0x698098D8 ); - P( D, A, B, C, 9, 12, 0x8B44F7AF ); - P( C, D, A, B, 10, 17, 0xFFFF5BB1 ); - P( B, C, D, A, 11, 22, 0x895CD7BE ); - P( A, B, C, D, 12, 7, 0x6B901122 ); - P( D, A, B, C, 13, 12, 0xFD987193 ); - P( C, D, A, B, 14, 17, 0xA679438E ); - P( B, C, D, A, 15, 22, 0x49B40821 ); + P( local.A, local.B, local.C, local.D, 0, 7, 0xD76AA478 ); + P( local.D, local.A, local.B, local.C, 1, 12, 0xE8C7B756 ); + P( local.C, local.D, local.A, local.B, 2, 17, 0x242070DB ); + P( local.B, local.C, local.D, local.A, 3, 22, 0xC1BDCEEE ); + P( local.A, local.B, local.C, local.D, 4, 7, 0xF57C0FAF ); + P( local.D, local.A, local.B, local.C, 5, 12, 0x4787C62A ); + P( local.C, local.D, local.A, local.B, 6, 17, 0xA8304613 ); + P( local.B, local.C, local.D, local.A, 7, 22, 0xFD469501 ); + P( local.A, local.B, local.C, local.D, 8, 7, 0x698098D8 ); + P( local.D, local.A, local.B, local.C, 9, 12, 0x8B44F7AF ); + P( local.C, local.D, local.A, local.B, 10, 17, 0xFFFF5BB1 ); + P( local.B, local.C, local.D, local.A, 11, 22, 0x895CD7BE ); + P( local.A, local.B, local.C, local.D, 12, 7, 0x6B901122 ); + P( local.D, local.A, local.B, local.C, 13, 12, 0xFD987193 ); + P( local.C, local.D, local.A, local.B, 14, 17, 0xA679438E ); + P( local.B, local.C, local.D, local.A, 15, 22, 0x49B40821 ); #undef F #define F(x,y,z) ((y) ^ ((z) & ((x) ^ (y)))) - P( A, B, C, D, 1, 5, 0xF61E2562 ); - P( D, A, B, C, 6, 9, 0xC040B340 ); - P( C, D, A, B, 11, 14, 0x265E5A51 ); - P( B, C, D, A, 0, 20, 0xE9B6C7AA ); - P( A, B, C, D, 5, 5, 0xD62F105D ); - P( D, A, B, C, 10, 9, 0x02441453 ); - P( C, D, A, B, 15, 14, 0xD8A1E681 ); - P( B, C, D, A, 4, 20, 0xE7D3FBC8 ); - P( A, B, C, D, 9, 5, 0x21E1CDE6 ); - P( D, A, B, C, 14, 9, 0xC33707D6 ); - P( C, D, A, B, 3, 14, 0xF4D50D87 ); - P( B, C, D, A, 8, 20, 0x455A14ED ); - P( A, B, C, D, 13, 5, 0xA9E3E905 ); - P( D, A, B, C, 2, 9, 0xFCEFA3F8 ); - P( C, D, A, B, 7, 14, 0x676F02D9 ); - P( B, C, D, A, 12, 20, 0x8D2A4C8A ); + P( local.A, local.B, local.C, local.D, 1, 5, 0xF61E2562 ); + P( local.D, local.A, local.B, local.C, 6, 9, 0xC040B340 ); + P( local.C, local.D, local.A, local.B, 11, 14, 0x265E5A51 ); + P( local.B, local.C, local.D, local.A, 0, 20, 0xE9B6C7AA ); + P( local.A, local.B, local.C, local.D, 5, 5, 0xD62F105D ); + P( local.D, local.A, local.B, local.C, 10, 9, 0x02441453 ); + P( local.C, local.D, local.A, local.B, 15, 14, 0xD8A1E681 ); + P( local.B, local.C, local.D, local.A, 4, 20, 0xE7D3FBC8 ); + P( local.A, local.B, local.C, local.D, 9, 5, 0x21E1CDE6 ); + P( local.D, local.A, local.B, local.C, 14, 9, 0xC33707D6 ); + P( local.C, local.D, local.A, local.B, 3, 14, 0xF4D50D87 ); + P( local.B, local.C, local.D, local.A, 8, 20, 0x455A14ED ); + P( local.A, local.B, local.C, local.D, 13, 5, 0xA9E3E905 ); + P( local.D, local.A, local.B, local.C, 2, 9, 0xFCEFA3F8 ); + P( local.C, local.D, local.A, local.B, 7, 14, 0x676F02D9 ); + P( local.B, local.C, local.D, local.A, 12, 20, 0x8D2A4C8A ); #undef F #define F(x,y,z) ((x) ^ (y) ^ (z)) - P( A, B, C, D, 5, 4, 0xFFFA3942 ); - P( D, A, B, C, 8, 11, 0x8771F681 ); - P( C, D, A, B, 11, 16, 0x6D9D6122 ); - P( B, C, D, A, 14, 23, 0xFDE5380C ); - P( A, B, C, D, 1, 4, 0xA4BEEA44 ); - P( D, A, B, C, 4, 11, 0x4BDECFA9 ); - P( C, D, A, B, 7, 16, 0xF6BB4B60 ); - P( B, C, D, A, 10, 23, 0xBEBFBC70 ); - P( A, B, C, D, 13, 4, 0x289B7EC6 ); - P( D, A, B, C, 0, 11, 0xEAA127FA ); - P( C, D, A, B, 3, 16, 0xD4EF3085 ); - P( B, C, D, A, 6, 23, 0x04881D05 ); - P( A, B, C, D, 9, 4, 0xD9D4D039 ); - P( D, A, B, C, 12, 11, 0xE6DB99E5 ); - P( C, D, A, B, 15, 16, 0x1FA27CF8 ); - P( B, C, D, A, 2, 23, 0xC4AC5665 ); + P( local.A, local.B, local.C, local.D, 5, 4, 0xFFFA3942 ); + P( local.D, local.A, local.B, local.C, 8, 11, 0x8771F681 ); + P( local.C, local.D, local.A, local.B, 11, 16, 0x6D9D6122 ); + P( local.B, local.C, local.D, local.A, 14, 23, 0xFDE5380C ); + P( local.A, local.B, local.C, local.D, 1, 4, 0xA4BEEA44 ); + P( local.D, local.A, local.B, local.C, 4, 11, 0x4BDECFA9 ); + P( local.C, local.D, local.A, local.B, 7, 16, 0xF6BB4B60 ); + P( local.B, local.C, local.D, local.A, 10, 23, 0xBEBFBC70 ); + P( local.A, local.B, local.C, local.D, 13, 4, 0x289B7EC6 ); + P( local.D, local.A, local.B, local.C, 0, 11, 0xEAA127FA ); + P( local.C, local.D, local.A, local.B, 3, 16, 0xD4EF3085 ); + P( local.B, local.C, local.D, local.A, 6, 23, 0x04881D05 ); + P( local.A, local.B, local.C, local.D, 9, 4, 0xD9D4D039 ); + P( local.D, local.A, local.B, local.C, 12, 11, 0xE6DB99E5 ); + P( local.C, local.D, local.A, local.B, 15, 16, 0x1FA27CF8 ); + P( local.B, local.C, local.D, local.A, 2, 23, 0xC4AC5665 ); #undef F #define F(x,y,z) ((y) ^ ((x) | ~(z))) - P( A, B, C, D, 0, 6, 0xF4292244 ); - P( D, A, B, C, 7, 10, 0x432AFF97 ); - P( C, D, A, B, 14, 15, 0xAB9423A7 ); - P( B, C, D, A, 5, 21, 0xFC93A039 ); - P( A, B, C, D, 12, 6, 0x655B59C3 ); - P( D, A, B, C, 3, 10, 0x8F0CCC92 ); - P( C, D, A, B, 10, 15, 0xFFEFF47D ); - P( B, C, D, A, 1, 21, 0x85845DD1 ); - P( A, B, C, D, 8, 6, 0x6FA87E4F ); - P( D, A, B, C, 15, 10, 0xFE2CE6E0 ); - P( C, D, A, B, 6, 15, 0xA3014314 ); - P( B, C, D, A, 13, 21, 0x4E0811A1 ); - P( A, B, C, D, 4, 6, 0xF7537E82 ); - P( D, A, B, C, 11, 10, 0xBD3AF235 ); - P( C, D, A, B, 2, 15, 0x2AD7D2BB ); - P( B, C, D, A, 9, 21, 0xEB86D391 ); + P( local.A, local.B, local.C, local.D, 0, 6, 0xF4292244 ); + P( local.D, local.A, local.B, local.C, 7, 10, 0x432AFF97 ); + P( local.C, local.D, local.A, local.B, 14, 15, 0xAB9423A7 ); + P( local.B, local.C, local.D, local.A, 5, 21, 0xFC93A039 ); + P( local.A, local.B, local.C, local.D, 12, 6, 0x655B59C3 ); + P( local.D, local.A, local.B, local.C, 3, 10, 0x8F0CCC92 ); + P( local.C, local.D, local.A, local.B, 10, 15, 0xFFEFF47D ); + P( local.B, local.C, local.D, local.A, 1, 21, 0x85845DD1 ); + P( local.A, local.B, local.C, local.D, 8, 6, 0x6FA87E4F ); + P( local.D, local.A, local.B, local.C, 15, 10, 0xFE2CE6E0 ); + P( local.C, local.D, local.A, local.B, 6, 15, 0xA3014314 ); + P( local.B, local.C, local.D, local.A, 13, 21, 0x4E0811A1 ); + P( local.A, local.B, local.C, local.D, 4, 6, 0xF7537E82 ); + P( local.D, local.A, local.B, local.C, 11, 10, 0xBD3AF235 ); + P( local.C, local.D, local.A, local.B, 2, 15, 0x2AD7D2BB ); + P( local.B, local.C, local.D, local.A, 9, 21, 0xEB86D391 ); #undef F - ctx->state[0] += A; - ctx->state[1] += B; - ctx->state[2] += C; - ctx->state[3] += D; + ctx->state[0] += local.A; + ctx->state[1] += local.B; + ctx->state[2] += local.C; + ctx->state[3] += local.D; + + /* Zeroise variables to clear sensitive data from memory. */ + mbedtls_platform_zeroize( &local, sizeof( local ) ); return( 0 ); } @@ -422,8 +428,7 @@ static const unsigned char md5_test_buf[7][81] = { "message digest" }, { "abcdefghijklmnopqrstuvwxyz" }, { "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789" }, - { "12345678901234567890123456789012345678901234567890123456789012" - "345678901234567890" } + { "12345678901234567890123456789012345678901234567890123456789012345678901234567890" } }; static const size_t md5_test_buflen[7] = diff --git a/connectivity/mbedtls/source/net_sockets.c b/connectivity/mbedtls/source/net_sockets.c index 3f96cabe46..54c2b472f2 100644 --- a/connectivity/mbedtls/source/net_sockets.c +++ b/connectivity/mbedtls/source/net_sockets.c @@ -318,7 +318,7 @@ int mbedtls_net_accept( mbedtls_net_context *bind_ctx, #if defined(__socklen_t_defined) || defined(_SOCKLEN_T) || \ defined(_SOCKLEN_T_DECLARED) || defined(__DEFINED_socklen_t) || \ - defined(socklen_t) + defined(socklen_t) || (defined(_POSIX_VERSION) && _POSIX_VERSION >= 200112L) socklen_t n = (socklen_t) sizeof( client_addr ); socklen_t type_len = (socklen_t) sizeof( type ); #else diff --git a/connectivity/mbedtls/source/pem.c b/connectivity/mbedtls/source/pem.c index 534d071b32..969d492e3b 100644 --- a/connectivity/mbedtls/source/pem.c +++ b/connectivity/mbedtls/source/pem.c @@ -478,8 +478,12 @@ int mbedtls_pem_write_buffer( const char *header, const char *footer, *p++ = '\0'; *olen = p - buf; + /* Clean any remaining data previously written to the buffer */ + memset( buf + *olen, 0, buf_len - *olen ); + mbedtls_free( encode_buf ); return( 0 ); } #endif /* MBEDTLS_PEM_WRITE_C */ #endif /* MBEDTLS_PEM_PARSE_C || MBEDTLS_PEM_WRITE_C */ + diff --git a/connectivity/mbedtls/source/pk.c b/connectivity/mbedtls/source/pk.c index 8ffbed2a9a..ecf002d452 100644 --- a/connectivity/mbedtls/source/pk.c +++ b/connectivity/mbedtls/source/pk.c @@ -150,11 +150,12 @@ int mbedtls_pk_setup( mbedtls_pk_context *ctx, const mbedtls_pk_info_t *info ) /* * Initialise a PSA-wrapping context */ -int mbedtls_pk_setup_opaque( mbedtls_pk_context *ctx, const psa_key_handle_t key ) +int mbedtls_pk_setup_opaque( mbedtls_pk_context *ctx, + const psa_key_id_t key ) { const mbedtls_pk_info_t * const info = &mbedtls_pk_opaque_info; psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - psa_key_handle_t *pk_ctx; + psa_key_id_t *pk_ctx; psa_key_type_t type; if( ctx == NULL || ctx->pk_info != NULL ) @@ -174,7 +175,7 @@ int mbedtls_pk_setup_opaque( mbedtls_pk_context *ctx, const psa_key_handle_t key ctx->pk_info = info; - pk_ctx = (psa_key_handle_t *) ctx->pk_ctx; + pk_ctx = (psa_key_id_t *) ctx->pk_ctx; *pk_ctx = key; return( 0 ); @@ -587,10 +588,13 @@ mbedtls_pk_type_t mbedtls_pk_get_type( const mbedtls_pk_context *ctx ) * Currently only works for EC private keys. */ int mbedtls_pk_wrap_as_opaque( mbedtls_pk_context *pk, - psa_key_handle_t *handle, + psa_key_id_t *key, psa_algorithm_t hash_alg ) { #if !defined(MBEDTLS_ECP_C) + ((void) pk); + ((void) key); + ((void) hash_alg); return( MBEDTLS_ERR_PK_TYPE_MISMATCH ); #else const mbedtls_ecp_keypair *ec; @@ -621,14 +625,14 @@ int mbedtls_pk_wrap_as_opaque( mbedtls_pk_context *pk, psa_set_key_algorithm( &attributes, PSA_ALG_ECDSA(hash_alg) ); /* import private key into PSA */ - if( PSA_SUCCESS != psa_import_key( &attributes, d, d_len, handle ) ) + if( PSA_SUCCESS != psa_import_key( &attributes, d, d_len, key ) ) return( MBEDTLS_ERR_PK_HW_ACCEL_FAILED ); /* make PK context wrap the key slot */ mbedtls_pk_free( pk ); mbedtls_pk_init( pk ); - return( mbedtls_pk_setup_opaque( pk, *handle ) ); + return( mbedtls_pk_setup_opaque( pk, *key ) ); #endif /* MBEDTLS_ECP_C */ } #endif /* MBEDTLS_USE_PSA_CRYPTO */ diff --git a/connectivity/mbedtls/source/pk_wrap.c b/connectivity/mbedtls/source/pk_wrap.c index 6bf3169743..107e912ace 100644 --- a/connectivity/mbedtls/source/pk_wrap.c +++ b/connectivity/mbedtls/source/pk_wrap.c @@ -543,7 +543,7 @@ static int ecdsa_verify_wrap( void *ctx_arg, mbedtls_md_type_t md_alg, mbedtls_ecdsa_context *ctx = ctx_arg; int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; - psa_key_handle_t key_handle = 0; + psa_key_id_t key_id = 0; psa_status_t status; mbedtls_pk_context key; int key_len; @@ -551,11 +551,12 @@ static int ecdsa_verify_wrap( void *ctx_arg, mbedtls_md_type_t md_alg, unsigned char buf[30 + 2 * MBEDTLS_ECP_MAX_BYTES]; unsigned char *p; mbedtls_pk_info_t pk_info = mbedtls_eckey_info; - psa_algorithm_t psa_sig_md, psa_md; + psa_algorithm_t psa_sig_md = PSA_ALG_ECDSA_ANY; size_t curve_bits; psa_ecc_family_t curve = mbedtls_ecc_group_to_psa( ctx->grp.id, &curve_bits ); const size_t signature_part_size = ( ctx->grp.nbits + 7 ) / 8; + ((void) md_alg); if( curve == 0 ) return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); @@ -569,18 +570,13 @@ static int ecdsa_verify_wrap( void *ctx_arg, mbedtls_md_type_t md_alg, if( key_len <= 0 ) return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); - psa_md = mbedtls_psa_translate_md( md_alg ); - if( psa_md == 0 ) - return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); - psa_sig_md = PSA_ALG_ECDSA( psa_md ); - psa_set_key_type( &attributes, PSA_KEY_TYPE_ECC_PUBLIC_KEY( curve ) ); psa_set_key_usage_flags( &attributes, PSA_KEY_USAGE_VERIFY_HASH ); psa_set_key_algorithm( &attributes, psa_sig_md ); status = psa_import_key( &attributes, buf + sizeof( buf ) - key_len, key_len, - &key_handle ); + &key_id ); if( status != PSA_SUCCESS ) { ret = mbedtls_psa_err_translate_pk( status ); @@ -602,7 +598,7 @@ static int ecdsa_verify_wrap( void *ctx_arg, mbedtls_md_type_t md_alg, goto cleanup; } - if( psa_verify_hash( key_handle, psa_sig_md, + if( psa_verify_hash( key_id, psa_sig_md, hash, hash_len, buf, 2 * signature_part_size ) != PSA_SUCCESS ) @@ -619,7 +615,7 @@ static int ecdsa_verify_wrap( void *ctx_arg, mbedtls_md_type_t md_alg, ret = 0; cleanup: - psa_destroy_key( key_handle ); + psa_destroy_key( key_id ); return( ret ); } #else /* MBEDTLS_USE_PSA_CRYPTO */ @@ -874,7 +870,7 @@ const mbedtls_pk_info_t mbedtls_rsa_alt_info = { static void *pk_opaque_alloc_wrap( void ) { - void *ctx = mbedtls_calloc( 1, sizeof( psa_key_handle_t ) ); + void *ctx = mbedtls_calloc( 1, sizeof( psa_key_id_t ) ); /* no _init() function to call, an calloc() already zeroized */ @@ -883,13 +879,13 @@ static void *pk_opaque_alloc_wrap( void ) static void pk_opaque_free_wrap( void *ctx ) { - mbedtls_platform_zeroize( ctx, sizeof( psa_key_handle_t ) ); + mbedtls_platform_zeroize( ctx, sizeof( psa_key_id_t ) ); mbedtls_free( ctx ); } static size_t pk_opaque_get_bitlen( const void *ctx ) { - const psa_key_handle_t *key = (const psa_key_handle_t *) ctx; + const psa_key_id_t *key = (const psa_key_id_t *) ctx; size_t bits; psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; @@ -910,6 +906,8 @@ static int pk_opaque_can_do( mbedtls_pk_type_t type ) type == MBEDTLS_PK_ECDSA ); } +#if defined(MBEDTLS_ECDSA_C) + /* * Simultaneously convert and move raw MPI from the beginning of a buffer * to an ASN.1 MPI at the end of the buffer. @@ -992,12 +990,25 @@ static int pk_ecdsa_sig_asn1_from_psa( unsigned char *sig, size_t *sig_len, return( 0 ); } +#endif /* MBEDTLS_ECDSA_C */ + static int pk_opaque_sign_wrap( void *ctx, mbedtls_md_type_t md_alg, const unsigned char *hash, size_t hash_len, unsigned char *sig, size_t *sig_len, int (*f_rng)(void *, unsigned char *, size_t), void *p_rng ) { - const psa_key_handle_t *key = (const psa_key_handle_t *) ctx; +#if !defined(MBEDTLS_ECDSA_C) + ((void) ctx); + ((void) md_alg); + ((void) hash); + ((void) hash_len); + ((void) sig); + ((void) sig_len); + ((void) f_rng); + ((void) p_rng); + return( MBEDTLS_ERR_PK_FEATURE_UNAVAILABLE ); +#else /* !MBEDTLS_ECDSA_C */ + const psa_key_id_t *key = (const psa_key_id_t *) ctx; psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; psa_algorithm_t alg = PSA_ALG_ECDSA( mbedtls_psa_translate_md( md_alg ) ); size_t buf_len; @@ -1027,6 +1038,7 @@ static int pk_opaque_sign_wrap( void *ctx, mbedtls_md_type_t md_alg, /* transcode it to ASN.1 sequence */ return( pk_ecdsa_sig_asn1_from_psa( sig, sig_len, buf_len ) ); +#endif /* !MBEDTLS_ECDSA_C */ } const mbedtls_pk_info_t mbedtls_pk_opaque_info = { diff --git a/connectivity/mbedtls/source/pkcs5.c b/connectivity/mbedtls/source/pkcs5.c index f89cc643c3..e9e743fa90 100644 --- a/connectivity/mbedtls/source/pkcs5.c +++ b/connectivity/mbedtls/source/pkcs5.c @@ -221,7 +221,8 @@ int mbedtls_pkcs5_pbkdf2_hmac( mbedtls_md_context_t *ctx, unsigned int iteration_count, uint32_t key_length, unsigned char *output ) { - int ret, j; + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + int j; unsigned int i; unsigned char md1[MBEDTLS_MD_MAX_SIZE]; unsigned char work[MBEDTLS_MD_MAX_SIZE]; @@ -245,16 +246,16 @@ int mbedtls_pkcs5_pbkdf2_hmac( mbedtls_md_context_t *ctx, // U1 ends up in work // if( ( ret = mbedtls_md_hmac_update( ctx, salt, slen ) ) != 0 ) - return( ret ); + goto cleanup; if( ( ret = mbedtls_md_hmac_update( ctx, counter, 4 ) ) != 0 ) - return( ret ); + goto cleanup; if( ( ret = mbedtls_md_hmac_finish( ctx, work ) ) != 0 ) - return( ret ); + goto cleanup; if( ( ret = mbedtls_md_hmac_reset( ctx ) ) != 0 ) - return( ret ); + goto cleanup; memcpy( md1, work, md_size ); @@ -263,13 +264,13 @@ int mbedtls_pkcs5_pbkdf2_hmac( mbedtls_md_context_t *ctx, // U2 ends up in md1 // if( ( ret = mbedtls_md_hmac_update( ctx, md1, md_size ) ) != 0 ) - return( ret ); + goto cleanup; if( ( ret = mbedtls_md_hmac_finish( ctx, md1 ) ) != 0 ) - return( ret ); + goto cleanup; if( ( ret = mbedtls_md_hmac_reset( ctx ) ) != 0 ) - return( ret ); + goto cleanup; // U1 xor U2 // @@ -288,7 +289,12 @@ int mbedtls_pkcs5_pbkdf2_hmac( mbedtls_md_context_t *ctx, break; } - return( 0 ); +cleanup: + /* Zeroise buffers to clear sensitive data from memory. */ + mbedtls_platform_zeroize( work, MBEDTLS_MD_MAX_SIZE ); + mbedtls_platform_zeroize( md1, MBEDTLS_MD_MAX_SIZE ); + + return( ret ); } #if defined(MBEDTLS_SELF_TEST) diff --git a/connectivity/mbedtls/source/pkparse.c b/connectivity/mbedtls/source/pkparse.c index a106dbe3ed..0590f2b050 100644 --- a/connectivity/mbedtls/source/pkparse.c +++ b/connectivity/mbedtls/source/pkparse.c @@ -662,7 +662,7 @@ int mbedtls_pk_parse_subpubkey( unsigned char **p, const unsigned char *end, ret = MBEDTLS_ERR_PK_UNKNOWN_PK_ALG; if( ret == 0 && *p != end ) - ret = MBEDTLS_ERR_PK_INVALID_PUBKEY + ret = MBEDTLS_ERR_PK_INVALID_PUBKEY + MBEDTLS_ERR_ASN1_LENGTH_MISMATCH; if( ret != 0 ) diff --git a/connectivity/mbedtls/source/pkwrite.c b/connectivity/mbedtls/source/pkwrite.c index b317ccf223..0da3698189 100644 --- a/connectivity/mbedtls/source/pkwrite.c +++ b/connectivity/mbedtls/source/pkwrite.c @@ -198,13 +198,13 @@ int mbedtls_pk_write_pubkey( unsigned char **p, unsigned char *start, if( mbedtls_pk_get_type( key ) == MBEDTLS_PK_OPAQUE ) { size_t buffer_size; - psa_key_handle_t* key_slot = (psa_key_handle_t*) key->pk_ctx; + psa_key_id_t* key_id = (psa_key_id_t*) key->pk_ctx; if ( *p < start ) return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); buffer_size = (size_t)( *p - start ); - if ( psa_export_public_key( *key_slot, start, buffer_size, &len ) + if ( psa_export_public_key( *key_id, start, buffer_size, &len ) != PSA_SUCCESS ) { return( MBEDTLS_ERR_PK_BAD_INPUT_DATA ); @@ -265,12 +265,12 @@ int mbedtls_pk_write_pubkey_der( mbedtls_pk_context *key, unsigned char *buf, si { psa_key_attributes_t attributes = PSA_KEY_ATTRIBUTES_INIT; psa_key_type_t key_type; - psa_key_handle_t handle; + psa_key_id_t key_id; psa_ecc_family_t curve; size_t bits; - handle = *((psa_key_handle_t*) key->pk_ctx ); - if( PSA_SUCCESS != psa_get_key_attributes( handle, &attributes ) ) + key_id = *((psa_key_id_t*) key->pk_ctx ); + if( PSA_SUCCESS != psa_get_key_attributes( key_id, &attributes ) ) return( MBEDTLS_ERR_PK_HW_ACCEL_FAILED ); key_type = psa_get_key_type( &attributes ); bits = psa_get_key_bits( &attributes ); diff --git a/connectivity/mbedtls/source/platform_util.c b/connectivity/mbedtls/source/platform_util.c index 4e1d617bd1..98fe5deb2d 100644 --- a/connectivity/mbedtls/source/platform_util.c +++ b/connectivity/mbedtls/source/platform_util.c @@ -84,7 +84,7 @@ void mbedtls_platform_zeroize( void *buf, size_t len ) #if !( ( defined(_POSIX_VERSION) && _POSIX_VERSION >= 200809L ) || \ ( defined(_POSIX_THREAD_SAFE_FUNCTIONS ) && \ - _POSIX_THREAD_SAFE_FUNCTIONS >= 20112L ) ) + _POSIX_THREAD_SAFE_FUNCTIONS >= 200112L ) ) /* * This is a convenience shorthand macro to avoid checking the long * preprocessor conditions above. Ideally, we could expose this macro in @@ -98,7 +98,7 @@ void mbedtls_platform_zeroize( void *buf, size_t len ) #endif /* !( ( defined(_POSIX_VERSION) && _POSIX_VERSION >= 200809L ) || \ ( defined(_POSIX_THREAD_SAFE_FUNCTIONS ) && \ - _POSIX_THREAD_SAFE_FUNCTIONS >= 20112L ) ) */ + _POSIX_THREAD_SAFE_FUNCTIONS >= 200112L ) ) */ struct tm *mbedtls_platform_gmtime_r( const mbedtls_time_t *tt, struct tm *tm_buf ) diff --git a/connectivity/mbedtls/source/ripemd160.c b/connectivity/mbedtls/source/ripemd160.c index 830f61b3cd..ae4dee4121 100644 --- a/connectivity/mbedtls/source/ripemd160.c +++ b/connectivity/mbedtls/source/ripemd160.c @@ -117,30 +117,33 @@ void mbedtls_ripemd160_starts( mbedtls_ripemd160_context *ctx ) int mbedtls_internal_ripemd160_process( mbedtls_ripemd160_context *ctx, const unsigned char data[64] ) { - uint32_t A, B, C, D, E, Ap, Bp, Cp, Dp, Ep, X[16]; + struct + { + uint32_t A, B, C, D, E, Ap, Bp, Cp, Dp, Ep, X[16]; + } local; - GET_UINT32_LE( X[ 0], data, 0 ); - GET_UINT32_LE( X[ 1], data, 4 ); - GET_UINT32_LE( X[ 2], data, 8 ); - GET_UINT32_LE( X[ 3], data, 12 ); - GET_UINT32_LE( X[ 4], data, 16 ); - GET_UINT32_LE( X[ 5], data, 20 ); - GET_UINT32_LE( X[ 6], data, 24 ); - GET_UINT32_LE( X[ 7], data, 28 ); - GET_UINT32_LE( X[ 8], data, 32 ); - GET_UINT32_LE( X[ 9], data, 36 ); - GET_UINT32_LE( X[10], data, 40 ); - GET_UINT32_LE( X[11], data, 44 ); - GET_UINT32_LE( X[12], data, 48 ); - GET_UINT32_LE( X[13], data, 52 ); - GET_UINT32_LE( X[14], data, 56 ); - GET_UINT32_LE( X[15], data, 60 ); + GET_UINT32_LE( local.X[ 0], data, 0 ); + GET_UINT32_LE( local.X[ 1], data, 4 ); + GET_UINT32_LE( local.X[ 2], data, 8 ); + GET_UINT32_LE( local.X[ 3], data, 12 ); + GET_UINT32_LE( local.X[ 4], data, 16 ); + GET_UINT32_LE( local.X[ 5], data, 20 ); + GET_UINT32_LE( local.X[ 6], data, 24 ); + GET_UINT32_LE( local.X[ 7], data, 28 ); + GET_UINT32_LE( local.X[ 8], data, 32 ); + GET_UINT32_LE( local.X[ 9], data, 36 ); + GET_UINT32_LE( local.X[10], data, 40 ); + GET_UINT32_LE( local.X[11], data, 44 ); + GET_UINT32_LE( local.X[12], data, 48 ); + GET_UINT32_LE( local.X[13], data, 52 ); + GET_UINT32_LE( local.X[14], data, 56 ); + GET_UINT32_LE( local.X[15], data, 60 ); - A = Ap = ctx->state[0]; - B = Bp = ctx->state[1]; - C = Cp = ctx->state[2]; - D = Dp = ctx->state[3]; - E = Ep = ctx->state[4]; + local.A = local.Ap = ctx->state[0]; + local.B = local.Bp = ctx->state[1]; + local.C = local.Cp = ctx->state[2]; + local.D = local.Dp = ctx->state[3]; + local.E = local.Ep = ctx->state[4]; #define F1( x, y, z ) ( (x) ^ (y) ^ (z) ) #define F2( x, y, z ) ( ( (x) & (y) ) | ( ~(x) & (z) ) ) @@ -150,12 +153,12 @@ int mbedtls_internal_ripemd160_process( mbedtls_ripemd160_context *ctx, #define S( x, n ) ( ( (x) << (n) ) | ( (x) >> (32 - (n)) ) ) -#define P( a, b, c, d, e, r, s, f, k ) \ - do \ - { \ - (a) += f( (b), (c), (d) ) + X[r] + (k); \ - (a) = S( (a), (s) ) + (e); \ - (c) = S( (c), 10 ); \ +#define P( a, b, c, d, e, r, s, f, k ) \ + do \ + { \ + (a) += f( (b), (c), (d) ) + local.X[r] + (k); \ + (a) = S( (a), (s) ) + (e); \ + (c) = S( (c), 10 ); \ } while( 0 ) #define P2( a, b, c, d, e, r, s, rp, sp ) \ @@ -170,22 +173,22 @@ int mbedtls_internal_ripemd160_process( mbedtls_ripemd160_context *ctx, #define K 0x00000000 #define Fp F5 #define Kp 0x50A28BE6 - P2( A, B, C, D, E, 0, 11, 5, 8 ); - P2( E, A, B, C, D, 1, 14, 14, 9 ); - P2( D, E, A, B, C, 2, 15, 7, 9 ); - P2( C, D, E, A, B, 3, 12, 0, 11 ); - P2( B, C, D, E, A, 4, 5, 9, 13 ); - P2( A, B, C, D, E, 5, 8, 2, 15 ); - P2( E, A, B, C, D, 6, 7, 11, 15 ); - P2( D, E, A, B, C, 7, 9, 4, 5 ); - P2( C, D, E, A, B, 8, 11, 13, 7 ); - P2( B, C, D, E, A, 9, 13, 6, 7 ); - P2( A, B, C, D, E, 10, 14, 15, 8 ); - P2( E, A, B, C, D, 11, 15, 8, 11 ); - P2( D, E, A, B, C, 12, 6, 1, 14 ); - P2( C, D, E, A, B, 13, 7, 10, 14 ); - P2( B, C, D, E, A, 14, 9, 3, 12 ); - P2( A, B, C, D, E, 15, 8, 12, 6 ); + P2( local.A, local.B, local.C, local.D, local.E, 0, 11, 5, 8 ); + P2( local.E, local.A, local.B, local.C, local.D, 1, 14, 14, 9 ); + P2( local.D, local.E, local.A, local.B, local.C, 2, 15, 7, 9 ); + P2( local.C, local.D, local.E, local.A, local.B, 3, 12, 0, 11 ); + P2( local.B, local.C, local.D, local.E, local.A, 4, 5, 9, 13 ); + P2( local.A, local.B, local.C, local.D, local.E, 5, 8, 2, 15 ); + P2( local.E, local.A, local.B, local.C, local.D, 6, 7, 11, 15 ); + P2( local.D, local.E, local.A, local.B, local.C, 7, 9, 4, 5 ); + P2( local.C, local.D, local.E, local.A, local.B, 8, 11, 13, 7 ); + P2( local.B, local.C, local.D, local.E, local.A, 9, 13, 6, 7 ); + P2( local.A, local.B, local.C, local.D, local.E, 10, 14, 15, 8 ); + P2( local.E, local.A, local.B, local.C, local.D, 11, 15, 8, 11 ); + P2( local.D, local.E, local.A, local.B, local.C, 12, 6, 1, 14 ); + P2( local.C, local.D, local.E, local.A, local.B, 13, 7, 10, 14 ); + P2( local.B, local.C, local.D, local.E, local.A, 14, 9, 3, 12 ); + P2( local.A, local.B, local.C, local.D, local.E, 15, 8, 12, 6 ); #undef F #undef K #undef Fp @@ -195,22 +198,22 @@ int mbedtls_internal_ripemd160_process( mbedtls_ripemd160_context *ctx, #define K 0x5A827999 #define Fp F4 #define Kp 0x5C4DD124 - P2( E, A, B, C, D, 7, 7, 6, 9 ); - P2( D, E, A, B, C, 4, 6, 11, 13 ); - P2( C, D, E, A, B, 13, 8, 3, 15 ); - P2( B, C, D, E, A, 1, 13, 7, 7 ); - P2( A, B, C, D, E, 10, 11, 0, 12 ); - P2( E, A, B, C, D, 6, 9, 13, 8 ); - P2( D, E, A, B, C, 15, 7, 5, 9 ); - P2( C, D, E, A, B, 3, 15, 10, 11 ); - P2( B, C, D, E, A, 12, 7, 14, 7 ); - P2( A, B, C, D, E, 0, 12, 15, 7 ); - P2( E, A, B, C, D, 9, 15, 8, 12 ); - P2( D, E, A, B, C, 5, 9, 12, 7 ); - P2( C, D, E, A, B, 2, 11, 4, 6 ); - P2( B, C, D, E, A, 14, 7, 9, 15 ); - P2( A, B, C, D, E, 11, 13, 1, 13 ); - P2( E, A, B, C, D, 8, 12, 2, 11 ); + P2( local.E, local.A, local.B, local.C, local.D, 7, 7, 6, 9 ); + P2( local.D, local.E, local.A, local.B, local.C, 4, 6, 11, 13 ); + P2( local.C, local.D, local.E, local.A, local.B, 13, 8, 3, 15 ); + P2( local.B, local.C, local.D, local.E, local.A, 1, 13, 7, 7 ); + P2( local.A, local.B, local.C, local.D, local.E, 10, 11, 0, 12 ); + P2( local.E, local.A, local.B, local.C, local.D, 6, 9, 13, 8 ); + P2( local.D, local.E, local.A, local.B, local.C, 15, 7, 5, 9 ); + P2( local.C, local.D, local.E, local.A, local.B, 3, 15, 10, 11 ); + P2( local.B, local.C, local.D, local.E, local.A, 12, 7, 14, 7 ); + P2( local.A, local.B, local.C, local.D, local.E, 0, 12, 15, 7 ); + P2( local.E, local.A, local.B, local.C, local.D, 9, 15, 8, 12 ); + P2( local.D, local.E, local.A, local.B, local.C, 5, 9, 12, 7 ); + P2( local.C, local.D, local.E, local.A, local.B, 2, 11, 4, 6 ); + P2( local.B, local.C, local.D, local.E, local.A, 14, 7, 9, 15 ); + P2( local.A, local.B, local.C, local.D, local.E, 11, 13, 1, 13 ); + P2( local.E, local.A, local.B, local.C, local.D, 8, 12, 2, 11 ); #undef F #undef K #undef Fp @@ -220,22 +223,22 @@ int mbedtls_internal_ripemd160_process( mbedtls_ripemd160_context *ctx, #define K 0x6ED9EBA1 #define Fp F3 #define Kp 0x6D703EF3 - P2( D, E, A, B, C, 3, 11, 15, 9 ); - P2( C, D, E, A, B, 10, 13, 5, 7 ); - P2( B, C, D, E, A, 14, 6, 1, 15 ); - P2( A, B, C, D, E, 4, 7, 3, 11 ); - P2( E, A, B, C, D, 9, 14, 7, 8 ); - P2( D, E, A, B, C, 15, 9, 14, 6 ); - P2( C, D, E, A, B, 8, 13, 6, 6 ); - P2( B, C, D, E, A, 1, 15, 9, 14 ); - P2( A, B, C, D, E, 2, 14, 11, 12 ); - P2( E, A, B, C, D, 7, 8, 8, 13 ); - P2( D, E, A, B, C, 0, 13, 12, 5 ); - P2( C, D, E, A, B, 6, 6, 2, 14 ); - P2( B, C, D, E, A, 13, 5, 10, 13 ); - P2( A, B, C, D, E, 11, 12, 0, 13 ); - P2( E, A, B, C, D, 5, 7, 4, 7 ); - P2( D, E, A, B, C, 12, 5, 13, 5 ); + P2( local.D, local.E, local.A, local.B, local.C, 3, 11, 15, 9 ); + P2( local.C, local.D, local.E, local.A, local.B, 10, 13, 5, 7 ); + P2( local.B, local.C, local.D, local.E, local.A, 14, 6, 1, 15 ); + P2( local.A, local.B, local.C, local.D, local.E, 4, 7, 3, 11 ); + P2( local.E, local.A, local.B, local.C, local.D, 9, 14, 7, 8 ); + P2( local.D, local.E, local.A, local.B, local.C, 15, 9, 14, 6 ); + P2( local.C, local.D, local.E, local.A, local.B, 8, 13, 6, 6 ); + P2( local.B, local.C, local.D, local.E, local.A, 1, 15, 9, 14 ); + P2( local.A, local.B, local.C, local.D, local.E, 2, 14, 11, 12 ); + P2( local.E, local.A, local.B, local.C, local.D, 7, 8, 8, 13 ); + P2( local.D, local.E, local.A, local.B, local.C, 0, 13, 12, 5 ); + P2( local.C, local.D, local.E, local.A, local.B, 6, 6, 2, 14 ); + P2( local.B, local.C, local.D, local.E, local.A, 13, 5, 10, 13 ); + P2( local.A, local.B, local.C, local.D, local.E, 11, 12, 0, 13 ); + P2( local.E, local.A, local.B, local.C, local.D, 5, 7, 4, 7 ); + P2( local.D, local.E, local.A, local.B, local.C, 12, 5, 13, 5 ); #undef F #undef K #undef Fp @@ -245,22 +248,22 @@ int mbedtls_internal_ripemd160_process( mbedtls_ripemd160_context *ctx, #define K 0x8F1BBCDC #define Fp F2 #define Kp 0x7A6D76E9 - P2( C, D, E, A, B, 1, 11, 8, 15 ); - P2( B, C, D, E, A, 9, 12, 6, 5 ); - P2( A, B, C, D, E, 11, 14, 4, 8 ); - P2( E, A, B, C, D, 10, 15, 1, 11 ); - P2( D, E, A, B, C, 0, 14, 3, 14 ); - P2( C, D, E, A, B, 8, 15, 11, 14 ); - P2( B, C, D, E, A, 12, 9, 15, 6 ); - P2( A, B, C, D, E, 4, 8, 0, 14 ); - P2( E, A, B, C, D, 13, 9, 5, 6 ); - P2( D, E, A, B, C, 3, 14, 12, 9 ); - P2( C, D, E, A, B, 7, 5, 2, 12 ); - P2( B, C, D, E, A, 15, 6, 13, 9 ); - P2( A, B, C, D, E, 14, 8, 9, 12 ); - P2( E, A, B, C, D, 5, 6, 7, 5 ); - P2( D, E, A, B, C, 6, 5, 10, 15 ); - P2( C, D, E, A, B, 2, 12, 14, 8 ); + P2( local.C, local.D, local.E, local.A, local.B, 1, 11, 8, 15 ); + P2( local.B, local.C, local.D, local.E, local.A, 9, 12, 6, 5 ); + P2( local.A, local.B, local.C, local.D, local.E, 11, 14, 4, 8 ); + P2( local.E, local.A, local.B, local.C, local.D, 10, 15, 1, 11 ); + P2( local.D, local.E, local.A, local.B, local.C, 0, 14, 3, 14 ); + P2( local.C, local.D, local.E, local.A, local.B, 8, 15, 11, 14 ); + P2( local.B, local.C, local.D, local.E, local.A, 12, 9, 15, 6 ); + P2( local.A, local.B, local.C, local.D, local.E, 4, 8, 0, 14 ); + P2( local.E, local.A, local.B, local.C, local.D, 13, 9, 5, 6 ); + P2( local.D, local.E, local.A, local.B, local.C, 3, 14, 12, 9 ); + P2( local.C, local.D, local.E, local.A, local.B, 7, 5, 2, 12 ); + P2( local.B, local.C, local.D, local.E, local.A, 15, 6, 13, 9 ); + P2( local.A, local.B, local.C, local.D, local.E, 14, 8, 9, 12 ); + P2( local.E, local.A, local.B, local.C, local.D, 5, 6, 7, 5 ); + P2( local.D, local.E, local.A, local.B, local.C, 6, 5, 10, 15 ); + P2( local.C, local.D, local.E, local.A, local.B, 2, 12, 14, 8 ); #undef F #undef K #undef Fp @@ -270,33 +273,36 @@ int mbedtls_internal_ripemd160_process( mbedtls_ripemd160_context *ctx, #define K 0xA953FD4E #define Fp F1 #define Kp 0x00000000 - P2( B, C, D, E, A, 4, 9, 12, 8 ); - P2( A, B, C, D, E, 0, 15, 15, 5 ); - P2( E, A, B, C, D, 5, 5, 10, 12 ); - P2( D, E, A, B, C, 9, 11, 4, 9 ); - P2( C, D, E, A, B, 7, 6, 1, 12 ); - P2( B, C, D, E, A, 12, 8, 5, 5 ); - P2( A, B, C, D, E, 2, 13, 8, 14 ); - P2( E, A, B, C, D, 10, 12, 7, 6 ); - P2( D, E, A, B, C, 14, 5, 6, 8 ); - P2( C, D, E, A, B, 1, 12, 2, 13 ); - P2( B, C, D, E, A, 3, 13, 13, 6 ); - P2( A, B, C, D, E, 8, 14, 14, 5 ); - P2( E, A, B, C, D, 11, 11, 0, 15 ); - P2( D, E, A, B, C, 6, 8, 3, 13 ); - P2( C, D, E, A, B, 15, 5, 9, 11 ); - P2( B, C, D, E, A, 13, 6, 11, 11 ); + P2( local.B, local.C, local.D, local.E, local.A, 4, 9, 12, 8 ); + P2( local.A, local.B, local.C, local.D, local.E, 0, 15, 15, 5 ); + P2( local.E, local.A, local.B, local.C, local.D, 5, 5, 10, 12 ); + P2( local.D, local.E, local.A, local.B, local.C, 9, 11, 4, 9 ); + P2( local.C, local.D, local.E, local.A, local.B, 7, 6, 1, 12 ); + P2( local.B, local.C, local.D, local.E, local.A, 12, 8, 5, 5 ); + P2( local.A, local.B, local.C, local.D, local.E, 2, 13, 8, 14 ); + P2( local.E, local.A, local.B, local.C, local.D, 10, 12, 7, 6 ); + P2( local.D, local.E, local.A, local.B, local.C, 14, 5, 6, 8 ); + P2( local.C, local.D, local.E, local.A, local.B, 1, 12, 2, 13 ); + P2( local.B, local.C, local.D, local.E, local.A, 3, 13, 13, 6 ); + P2( local.A, local.B, local.C, local.D, local.E, 8, 14, 14, 5 ); + P2( local.E, local.A, local.B, local.C, local.D, 11, 11, 0, 15 ); + P2( local.D, local.E, local.A, local.B, local.C, 6, 8, 3, 13 ); + P2( local.C, local.D, local.E, local.A, local.B, 15, 5, 9, 11 ); + P2( local.B, local.C, local.D, local.E, local.A, 13, 6, 11, 11 ); #undef F #undef K #undef Fp #undef Kp - C = ctx->state[1] + C + Dp; - ctx->state[1] = ctx->state[2] + D + Ep; - ctx->state[2] = ctx->state[3] + E + Ap; - ctx->state[3] = ctx->state[4] + A + Bp; - ctx->state[4] = ctx->state[0] + B + Cp; - ctx->state[0] = C; + local.C = ctx->state[1] + local.C + local.Dp; + ctx->state[1] = ctx->state[2] + local.D + local.Ep; + ctx->state[2] = ctx->state[3] + local.E + local.Ap; + ctx->state[3] = ctx->state[4] + local.A + local.Bp; + ctx->state[4] = ctx->state[0] + local.B + local.Cp; + ctx->state[0] = local.C; + + /* Zeroise variables to clear sensitive data from memory. */ + mbedtls_platform_zeroize( &local, sizeof( local ) ); return( 0 ); } @@ -478,8 +484,7 @@ static const unsigned char ripemd160_test_str[TESTS][81] = { "abcdefghijklmnopqrstuvwxyz" }, { "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" }, { "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789" }, - { "12345678901234567890123456789012345678901234567890123456789012" - "345678901234567890" }, + { "12345678901234567890123456789012345678901234567890123456789012345678901234567890" }, }; static const size_t ripemd160_test_strlen[TESTS] = diff --git a/connectivity/mbedtls/source/rsa.c b/connectivity/mbedtls/source/rsa.c index 84d87de0d1..d6abd65d4c 100644 --- a/connectivity/mbedtls/source/rsa.c +++ b/connectivity/mbedtls/source/rsa.c @@ -811,15 +811,14 @@ static int rsa_prepare_blinding( mbedtls_rsa_context *ctx, * which one, we just loop and choose new values for both of them. * (Each iteration succeeds with overwhelming probability.) */ ret = mbedtls_mpi_inv_mod( &ctx->Vi, &ctx->Vi, &ctx->N ); - if( ret == MBEDTLS_ERR_MPI_NOT_ACCEPTABLE ) - continue; - if( ret != 0 ) + if( ret != 0 && ret != MBEDTLS_ERR_MPI_NOT_ACCEPTABLE ) goto cleanup; - /* Finish the computation of Vf^-1 = R * (R Vf)^-1 */ - MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ctx->Vi, &ctx->Vi, &R ) ); - MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &ctx->Vi, &ctx->Vi, &ctx->N ) ); - } while( 0 ); + } while( ret == MBEDTLS_ERR_MPI_NOT_ACCEPTABLE ); + + /* Finish the computation of Vf^-1 = R * (R Vf)^-1 */ + MBEDTLS_MPI_CHK( mbedtls_mpi_mul_mpi( &ctx->Vi, &ctx->Vi, &R ) ); + MBEDTLS_MPI_CHK( mbedtls_mpi_mod_mpi( &ctx->Vi, &ctx->Vi, &ctx->N ) ); /* Blinding value: Vi = Vf^(-e) mod N * (Vi already contains Vf^-1 at this point) */ diff --git a/connectivity/mbedtls/source/sha1.c b/connectivity/mbedtls/source/sha1.c index 593f79513a..6b0f58e7b6 100644 --- a/connectivity/mbedtls/source/sha1.c +++ b/connectivity/mbedtls/source/sha1.c @@ -125,35 +125,40 @@ void mbedtls_sha1_starts( mbedtls_sha1_context *ctx ) int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, const unsigned char data[64] ) { - uint32_t temp, W[16], A, B, C, D, E; + struct + { + uint32_t temp, W[16], A, B, C, D, E; + } local; SHA1_VALIDATE_RET( ctx != NULL ); SHA1_VALIDATE_RET( (const unsigned char *)data != NULL ); - GET_UINT32_BE( W[ 0], data, 0 ); - GET_UINT32_BE( W[ 1], data, 4 ); - GET_UINT32_BE( W[ 2], data, 8 ); - GET_UINT32_BE( W[ 3], data, 12 ); - GET_UINT32_BE( W[ 4], data, 16 ); - GET_UINT32_BE( W[ 5], data, 20 ); - GET_UINT32_BE( W[ 6], data, 24 ); - GET_UINT32_BE( W[ 7], data, 28 ); - GET_UINT32_BE( W[ 8], data, 32 ); - GET_UINT32_BE( W[ 9], data, 36 ); - GET_UINT32_BE( W[10], data, 40 ); - GET_UINT32_BE( W[11], data, 44 ); - GET_UINT32_BE( W[12], data, 48 ); - GET_UINT32_BE( W[13], data, 52 ); - GET_UINT32_BE( W[14], data, 56 ); - GET_UINT32_BE( W[15], data, 60 ); + GET_UINT32_BE( local.W[ 0], data, 0 ); + GET_UINT32_BE( local.W[ 1], data, 4 ); + GET_UINT32_BE( local.W[ 2], data, 8 ); + GET_UINT32_BE( local.W[ 3], data, 12 ); + GET_UINT32_BE( local.W[ 4], data, 16 ); + GET_UINT32_BE( local.W[ 5], data, 20 ); + GET_UINT32_BE( local.W[ 6], data, 24 ); + GET_UINT32_BE( local.W[ 7], data, 28 ); + GET_UINT32_BE( local.W[ 8], data, 32 ); + GET_UINT32_BE( local.W[ 9], data, 36 ); + GET_UINT32_BE( local.W[10], data, 40 ); + GET_UINT32_BE( local.W[11], data, 44 ); + GET_UINT32_BE( local.W[12], data, 48 ); + GET_UINT32_BE( local.W[13], data, 52 ); + GET_UINT32_BE( local.W[14], data, 56 ); + GET_UINT32_BE( local.W[15], data, 60 ); #define S(x,n) (((x) << (n)) | (((x) & 0xFFFFFFFF) >> (32 - (n)))) #define R(t) \ ( \ - temp = W[( (t) - 3 ) & 0x0F] ^ W[( (t) - 8 ) & 0x0F] ^ \ - W[( (t) - 14 ) & 0x0F] ^ W[ (t) & 0x0F], \ - ( W[(t) & 0x0F] = S(temp,1) ) \ + local.temp = local.W[( (t) - 3 ) & 0x0F] ^ \ + local.W[( (t) - 8 ) & 0x0F] ^ \ + local.W[( (t) - 14 ) & 0x0F] ^ \ + local.W[ (t) & 0x0F], \ + ( local.W[(t) & 0x0F] = S(local.temp,1) ) \ ) #define P(a,b,c,d,e,x) \ @@ -163,35 +168,35 @@ int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, (b) = S((b),30); \ } while( 0 ) - A = ctx->state[0]; - B = ctx->state[1]; - C = ctx->state[2]; - D = ctx->state[3]; - E = ctx->state[4]; + local.A = ctx->state[0]; + local.B = ctx->state[1]; + local.C = ctx->state[2]; + local.D = ctx->state[3]; + local.E = ctx->state[4]; #define F(x,y,z) ((z) ^ ((x) & ((y) ^ (z)))) #define K 0x5A827999 - P( A, B, C, D, E, W[0] ); - P( E, A, B, C, D, W[1] ); - P( D, E, A, B, C, W[2] ); - P( C, D, E, A, B, W[3] ); - P( B, C, D, E, A, W[4] ); - P( A, B, C, D, E, W[5] ); - P( E, A, B, C, D, W[6] ); - P( D, E, A, B, C, W[7] ); - P( C, D, E, A, B, W[8] ); - P( B, C, D, E, A, W[9] ); - P( A, B, C, D, E, W[10] ); - P( E, A, B, C, D, W[11] ); - P( D, E, A, B, C, W[12] ); - P( C, D, E, A, B, W[13] ); - P( B, C, D, E, A, W[14] ); - P( A, B, C, D, E, W[15] ); - P( E, A, B, C, D, R(16) ); - P( D, E, A, B, C, R(17) ); - P( C, D, E, A, B, R(18) ); - P( B, C, D, E, A, R(19) ); + P( local.A, local.B, local.C, local.D, local.E, local.W[0] ); + P( local.E, local.A, local.B, local.C, local.D, local.W[1] ); + P( local.D, local.E, local.A, local.B, local.C, local.W[2] ); + P( local.C, local.D, local.E, local.A, local.B, local.W[3] ); + P( local.B, local.C, local.D, local.E, local.A, local.W[4] ); + P( local.A, local.B, local.C, local.D, local.E, local.W[5] ); + P( local.E, local.A, local.B, local.C, local.D, local.W[6] ); + P( local.D, local.E, local.A, local.B, local.C, local.W[7] ); + P( local.C, local.D, local.E, local.A, local.B, local.W[8] ); + P( local.B, local.C, local.D, local.E, local.A, local.W[9] ); + P( local.A, local.B, local.C, local.D, local.E, local.W[10] ); + P( local.E, local.A, local.B, local.C, local.D, local.W[11] ); + P( local.D, local.E, local.A, local.B, local.C, local.W[12] ); + P( local.C, local.D, local.E, local.A, local.B, local.W[13] ); + P( local.B, local.C, local.D, local.E, local.A, local.W[14] ); + P( local.A, local.B, local.C, local.D, local.E, local.W[15] ); + P( local.E, local.A, local.B, local.C, local.D, R(16) ); + P( local.D, local.E, local.A, local.B, local.C, R(17) ); + P( local.C, local.D, local.E, local.A, local.B, R(18) ); + P( local.B, local.C, local.D, local.E, local.A, R(19) ); #undef K #undef F @@ -199,26 +204,26 @@ int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, #define F(x,y,z) ((x) ^ (y) ^ (z)) #define K 0x6ED9EBA1 - P( A, B, C, D, E, R(20) ); - P( E, A, B, C, D, R(21) ); - P( D, E, A, B, C, R(22) ); - P( C, D, E, A, B, R(23) ); - P( B, C, D, E, A, R(24) ); - P( A, B, C, D, E, R(25) ); - P( E, A, B, C, D, R(26) ); - P( D, E, A, B, C, R(27) ); - P( C, D, E, A, B, R(28) ); - P( B, C, D, E, A, R(29) ); - P( A, B, C, D, E, R(30) ); - P( E, A, B, C, D, R(31) ); - P( D, E, A, B, C, R(32) ); - P( C, D, E, A, B, R(33) ); - P( B, C, D, E, A, R(34) ); - P( A, B, C, D, E, R(35) ); - P( E, A, B, C, D, R(36) ); - P( D, E, A, B, C, R(37) ); - P( C, D, E, A, B, R(38) ); - P( B, C, D, E, A, R(39) ); + P( local.A, local.B, local.C, local.D, local.E, R(20) ); + P( local.E, local.A, local.B, local.C, local.D, R(21) ); + P( local.D, local.E, local.A, local.B, local.C, R(22) ); + P( local.C, local.D, local.E, local.A, local.B, R(23) ); + P( local.B, local.C, local.D, local.E, local.A, R(24) ); + P( local.A, local.B, local.C, local.D, local.E, R(25) ); + P( local.E, local.A, local.B, local.C, local.D, R(26) ); + P( local.D, local.E, local.A, local.B, local.C, R(27) ); + P( local.C, local.D, local.E, local.A, local.B, R(28) ); + P( local.B, local.C, local.D, local.E, local.A, R(29) ); + P( local.A, local.B, local.C, local.D, local.E, R(30) ); + P( local.E, local.A, local.B, local.C, local.D, R(31) ); + P( local.D, local.E, local.A, local.B, local.C, R(32) ); + P( local.C, local.D, local.E, local.A, local.B, R(33) ); + P( local.B, local.C, local.D, local.E, local.A, R(34) ); + P( local.A, local.B, local.C, local.D, local.E, R(35) ); + P( local.E, local.A, local.B, local.C, local.D, R(36) ); + P( local.D, local.E, local.A, local.B, local.C, R(37) ); + P( local.C, local.D, local.E, local.A, local.B, R(38) ); + P( local.B, local.C, local.D, local.E, local.A, R(39) ); #undef K #undef F @@ -226,26 +231,26 @@ int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, #define F(x,y,z) (((x) & (y)) | ((z) & ((x) | (y)))) #define K 0x8F1BBCDC - P( A, B, C, D, E, R(40) ); - P( E, A, B, C, D, R(41) ); - P( D, E, A, B, C, R(42) ); - P( C, D, E, A, B, R(43) ); - P( B, C, D, E, A, R(44) ); - P( A, B, C, D, E, R(45) ); - P( E, A, B, C, D, R(46) ); - P( D, E, A, B, C, R(47) ); - P( C, D, E, A, B, R(48) ); - P( B, C, D, E, A, R(49) ); - P( A, B, C, D, E, R(50) ); - P( E, A, B, C, D, R(51) ); - P( D, E, A, B, C, R(52) ); - P( C, D, E, A, B, R(53) ); - P( B, C, D, E, A, R(54) ); - P( A, B, C, D, E, R(55) ); - P( E, A, B, C, D, R(56) ); - P( D, E, A, B, C, R(57) ); - P( C, D, E, A, B, R(58) ); - P( B, C, D, E, A, R(59) ); + P( local.A, local.B, local.C, local.D, local.E, R(40) ); + P( local.E, local.A, local.B, local.C, local.D, R(41) ); + P( local.D, local.E, local.A, local.B, local.C, R(42) ); + P( local.C, local.D, local.E, local.A, local.B, R(43) ); + P( local.B, local.C, local.D, local.E, local.A, R(44) ); + P( local.A, local.B, local.C, local.D, local.E, R(45) ); + P( local.E, local.A, local.B, local.C, local.D, R(46) ); + P( local.D, local.E, local.A, local.B, local.C, R(47) ); + P( local.C, local.D, local.E, local.A, local.B, R(48) ); + P( local.B, local.C, local.D, local.E, local.A, R(49) ); + P( local.A, local.B, local.C, local.D, local.E, R(50) ); + P( local.E, local.A, local.B, local.C, local.D, R(51) ); + P( local.D, local.E, local.A, local.B, local.C, R(52) ); + P( local.C, local.D, local.E, local.A, local.B, R(53) ); + P( local.B, local.C, local.D, local.E, local.A, R(54) ); + P( local.A, local.B, local.C, local.D, local.E, R(55) ); + P( local.E, local.A, local.B, local.C, local.D, R(56) ); + P( local.D, local.E, local.A, local.B, local.C, R(57) ); + P( local.C, local.D, local.E, local.A, local.B, R(58) ); + P( local.B, local.C, local.D, local.E, local.A, R(59) ); #undef K #undef F @@ -253,35 +258,38 @@ int mbedtls_internal_sha1_process( mbedtls_sha1_context *ctx, #define F(x,y,z) ((x) ^ (y) ^ (z)) #define K 0xCA62C1D6 - P( A, B, C, D, E, R(60) ); - P( E, A, B, C, D, R(61) ); - P( D, E, A, B, C, R(62) ); - P( C, D, E, A, B, R(63) ); - P( B, C, D, E, A, R(64) ); - P( A, B, C, D, E, R(65) ); - P( E, A, B, C, D, R(66) ); - P( D, E, A, B, C, R(67) ); - P( C, D, E, A, B, R(68) ); - P( B, C, D, E, A, R(69) ); - P( A, B, C, D, E, R(70) ); - P( E, A, B, C, D, R(71) ); - P( D, E, A, B, C, R(72) ); - P( C, D, E, A, B, R(73) ); - P( B, C, D, E, A, R(74) ); - P( A, B, C, D, E, R(75) ); - P( E, A, B, C, D, R(76) ); - P( D, E, A, B, C, R(77) ); - P( C, D, E, A, B, R(78) ); - P( B, C, D, E, A, R(79) ); + P( local.A, local.B, local.C, local.D, local.E, R(60) ); + P( local.E, local.A, local.B, local.C, local.D, R(61) ); + P( local.D, local.E, local.A, local.B, local.C, R(62) ); + P( local.C, local.D, local.E, local.A, local.B, R(63) ); + P( local.B, local.C, local.D, local.E, local.A, R(64) ); + P( local.A, local.B, local.C, local.D, local.E, R(65) ); + P( local.E, local.A, local.B, local.C, local.D, R(66) ); + P( local.D, local.E, local.A, local.B, local.C, R(67) ); + P( local.C, local.D, local.E, local.A, local.B, R(68) ); + P( local.B, local.C, local.D, local.E, local.A, R(69) ); + P( local.A, local.B, local.C, local.D, local.E, R(70) ); + P( local.E, local.A, local.B, local.C, local.D, R(71) ); + P( local.D, local.E, local.A, local.B, local.C, R(72) ); + P( local.C, local.D, local.E, local.A, local.B, R(73) ); + P( local.B, local.C, local.D, local.E, local.A, R(74) ); + P( local.A, local.B, local.C, local.D, local.E, R(75) ); + P( local.E, local.A, local.B, local.C, local.D, R(76) ); + P( local.D, local.E, local.A, local.B, local.C, R(77) ); + P( local.C, local.D, local.E, local.A, local.B, R(78) ); + P( local.B, local.C, local.D, local.E, local.A, R(79) ); #undef K #undef F - ctx->state[0] += A; - ctx->state[1] += B; - ctx->state[2] += C; - ctx->state[3] += D; - ctx->state[4] += E; + ctx->state[0] += local.A; + ctx->state[1] += local.B; + ctx->state[2] += local.C; + ctx->state[3] += local.D; + ctx->state[4] += local.E; + + /* Zeroise buffers and variables to clear sensitive data from memory. */ + mbedtls_platform_zeroize( &local, sizeof( local ) ); return( 0 ); } diff --git a/connectivity/mbedtls/source/sha256.c b/connectivity/mbedtls/source/sha256.c index b4c4b3624f..be373d9cb0 100644 --- a/connectivity/mbedtls/source/sha256.c +++ b/connectivity/mbedtls/source/sha256.c @@ -179,77 +179,104 @@ static const uint32_t K[] = #define F0(x,y,z) (((x) & (y)) | ((z) & ((x) | (y)))) #define F1(x,y,z) ((z) ^ ((x) & ((y) ^ (z)))) -#define R(t) \ - ( \ - W[t] = S1(W[(t) - 2]) + W[(t) - 7] + \ - S0(W[(t) - 15]) + W[(t) - 16] \ +#define R(t) \ + ( \ + local.W[t] = S1(local.W[(t) - 2]) + local.W[(t) - 7] + \ + S0(local.W[(t) - 15]) + local.W[(t) - 16] \ ) -#define P(a,b,c,d,e,f,g,h,x,K) \ - do \ - { \ - temp1 = (h) + S3(e) + F1((e),(f),(g)) + (K) + (x); \ - temp2 = S2(a) + F0((a),(b),(c)); \ - (d) += temp1; (h) = temp1 + temp2; \ +#define P(a,b,c,d,e,f,g,h,x,K) \ + do \ + { \ + local.temp1 = (h) + S3(e) + F1((e),(f),(g)) + (K) + (x); \ + local.temp2 = S2(a) + F0((a),(b),(c)); \ + (d) += local.temp1; (h) = local.temp1 + local.temp2; \ } while( 0 ) int mbedtls_internal_sha256_process( mbedtls_sha256_context *ctx, const unsigned char data[64] ) { - uint32_t temp1, temp2, W[64]; - uint32_t A[8]; + struct + { + uint32_t temp1, temp2, W[64]; + uint32_t A[8]; + } local; + unsigned int i; SHA256_VALIDATE_RET( ctx != NULL ); SHA256_VALIDATE_RET( (const unsigned char *)data != NULL ); for( i = 0; i < 8; i++ ) - A[i] = ctx->state[i]; + local.A[i] = ctx->state[i]; #if defined(MBEDTLS_SHA256_SMALLER) for( i = 0; i < 64; i++ ) { if( i < 16 ) - GET_UINT32_BE( W[i], data, 4 * i ); + GET_UINT32_BE( local.W[i], data, 4 * i ); else R( i ); - P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i], K[i] ); + P( local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], + local.A[5], local.A[6], local.A[7], local.W[i], K[i] ); - temp1 = A[7]; A[7] = A[6]; A[6] = A[5]; A[5] = A[4]; A[4] = A[3]; - A[3] = A[2]; A[2] = A[1]; A[1] = A[0]; A[0] = temp1; + local.temp1 = local.A[7]; local.A[7] = local.A[6]; + local.A[6] = local.A[5]; local.A[5] = local.A[4]; + local.A[4] = local.A[3]; local.A[3] = local.A[2]; + local.A[2] = local.A[1]; local.A[1] = local.A[0]; + local.A[0] = local.temp1; } #else /* MBEDTLS_SHA256_SMALLER */ for( i = 0; i < 16; i++ ) - GET_UINT32_BE( W[i], data, 4 * i ); + GET_UINT32_BE( local.W[i], data, 4 * i ); for( i = 0; i < 16; i += 8 ) { - P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i+0], K[i+0] ); - P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], W[i+1], K[i+1] ); - P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], W[i+2], K[i+2] ); - P( A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], W[i+3], K[i+3] ); - P( A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], W[i+4], K[i+4] ); - P( A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], W[i+5], K[i+5] ); - P( A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], W[i+6], K[i+6] ); - P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], W[i+7], K[i+7] ); + P( local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], + local.A[5], local.A[6], local.A[7], local.W[i+0], K[i+0] ); + P( local.A[7], local.A[0], local.A[1], local.A[2], local.A[3], + local.A[4], local.A[5], local.A[6], local.W[i+1], K[i+1] ); + P( local.A[6], local.A[7], local.A[0], local.A[1], local.A[2], + local.A[3], local.A[4], local.A[5], local.W[i+2], K[i+2] ); + P( local.A[5], local.A[6], local.A[7], local.A[0], local.A[1], + local.A[2], local.A[3], local.A[4], local.W[i+3], K[i+3] ); + P( local.A[4], local.A[5], local.A[6], local.A[7], local.A[0], + local.A[1], local.A[2], local.A[3], local.W[i+4], K[i+4] ); + P( local.A[3], local.A[4], local.A[5], local.A[6], local.A[7], + local.A[0], local.A[1], local.A[2], local.W[i+5], K[i+5] ); + P( local.A[2], local.A[3], local.A[4], local.A[5], local.A[6], + local.A[7], local.A[0], local.A[1], local.W[i+6], K[i+6] ); + P( local.A[1], local.A[2], local.A[3], local.A[4], local.A[5], + local.A[6], local.A[7], local.A[0], local.W[i+7], K[i+7] ); } for( i = 16; i < 64; i += 8 ) { - P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], R(i+0), K[i+0] ); - P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], R(i+1), K[i+1] ); - P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], R(i+2), K[i+2] ); - P( A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], R(i+3), K[i+3] ); - P( A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], R(i+4), K[i+4] ); - P( A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], R(i+5), K[i+5] ); - P( A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], R(i+6), K[i+6] ); - P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], R(i+7), K[i+7] ); + P( local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], + local.A[5], local.A[6], local.A[7], R(i+0), K[i+0] ); + P( local.A[7], local.A[0], local.A[1], local.A[2], local.A[3], + local.A[4], local.A[5], local.A[6], R(i+1), K[i+1] ); + P( local.A[6], local.A[7], local.A[0], local.A[1], local.A[2], + local.A[3], local.A[4], local.A[5], R(i+2), K[i+2] ); + P( local.A[5], local.A[6], local.A[7], local.A[0], local.A[1], + local.A[2], local.A[3], local.A[4], R(i+3), K[i+3] ); + P( local.A[4], local.A[5], local.A[6], local.A[7], local.A[0], + local.A[1], local.A[2], local.A[3], R(i+4), K[i+4] ); + P( local.A[3], local.A[4], local.A[5], local.A[6], local.A[7], + local.A[0], local.A[1], local.A[2], R(i+5), K[i+5] ); + P( local.A[2], local.A[3], local.A[4], local.A[5], local.A[6], + local.A[7], local.A[0], local.A[1], R(i+6), K[i+6] ); + P( local.A[1], local.A[2], local.A[3], local.A[4], local.A[5], + local.A[6], local.A[7], local.A[0], R(i+7), K[i+7] ); } #endif /* MBEDTLS_SHA256_SMALLER */ for( i = 0; i < 8; i++ ) - ctx->state[i] += A[i]; + ctx->state[i] += local.A[i]; + + /* Zeroise buffers and variables to clear sensitive data from memory. */ + mbedtls_platform_zeroize( &local, sizeof( local ) ); return( 0 ); } diff --git a/connectivity/mbedtls/source/sha512.c b/connectivity/mbedtls/source/sha512.c index 80219d4281..06a628aedc 100644 --- a/connectivity/mbedtls/source/sha512.c +++ b/connectivity/mbedtls/source/sha512.c @@ -232,8 +232,11 @@ int mbedtls_internal_sha512_process( mbedtls_sha512_context *ctx, const unsigned char data[128] ) { int i; - uint64_t temp1, temp2, W[80]; - uint64_t A[8]; + struct + { + uint64_t temp1, temp2, W[80]; + uint64_t A[8]; + } local; SHA512_VALIDATE_RET( ctx != NULL ); SHA512_VALIDATE_RET( (const unsigned char *)data != NULL ); @@ -250,64 +253,79 @@ int mbedtls_internal_sha512_process( mbedtls_sha512_context *ctx, #define F0(x,y,z) (((x) & (y)) | ((z) & ((x) | (y)))) #define F1(x,y,z) ((z) ^ ((x) & ((y) ^ (z)))) -#define P(a,b,c,d,e,f,g,h,x,K) \ - do \ - { \ - temp1 = (h) + S3(e) + F1((e),(f),(g)) + (K) + (x); \ - temp2 = S2(a) + F0((a),(b),(c)); \ - (d) += temp1; (h) = temp1 + temp2; \ +#define P(a,b,c,d,e,f,g,h,x,K) \ + do \ + { \ + local.temp1 = (h) + S3(e) + F1((e),(f),(g)) + (K) + (x); \ + local.temp2 = S2(a) + F0((a),(b),(c)); \ + (d) += local.temp1; (h) = local.temp1 + local.temp2; \ } while( 0 ) for( i = 0; i < 8; i++ ) - A[i] = ctx->state[i]; + local.A[i] = ctx->state[i]; #if defined(MBEDTLS_SHA512_SMALLER) for( i = 0; i < 80; i++ ) { if( i < 16 ) { - GET_UINT64_BE( W[i], data, i << 3 ); + GET_UINT64_BE( local.W[i], data, i << 3 ); } else { - W[i] = S1(W[i - 2]) + W[i - 7] + - S0(W[i - 15]) + W[i - 16]; + local.W[i] = S1(local.W[i - 2]) + local.W[i - 7] + + S0(local.W[i - 15]) + local.W[i - 16]; } - P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i], K[i] ); + P( local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], + local.A[5], local.A[6], local.A[7], local.W[i], K[i] ); - temp1 = A[7]; A[7] = A[6]; A[6] = A[5]; A[5] = A[4]; A[4] = A[3]; - A[3] = A[2]; A[2] = A[1]; A[1] = A[0]; A[0] = temp1; + local.temp1 = local.A[7]; local.A[7] = local.A[6]; + local.A[6] = local.A[5]; local.A[5] = local.A[4]; + local.A[4] = local.A[3]; local.A[3] = local.A[2]; + local.A[2] = local.A[1]; local.A[1] = local.A[0]; + local.A[0] = local.temp1; } #else /* MBEDTLS_SHA512_SMALLER */ for( i = 0; i < 16; i++ ) { - GET_UINT64_BE( W[i], data, i << 3 ); + GET_UINT64_BE( local.W[i], data, i << 3 ); } for( ; i < 80; i++ ) { - W[i] = S1(W[i - 2]) + W[i - 7] + - S0(W[i - 15]) + W[i - 16]; + local.W[i] = S1(local.W[i - 2]) + local.W[i - 7] + + S0(local.W[i - 15]) + local.W[i - 16]; } i = 0; do { - P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i], K[i] ); i++; - P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], W[i], K[i] ); i++; - P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], W[i], K[i] ); i++; - P( A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], W[i], K[i] ); i++; - P( A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], W[i], K[i] ); i++; - P( A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], W[i], K[i] ); i++; - P( A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], W[i], K[i] ); i++; - P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], W[i], K[i] ); i++; + P( local.A[0], local.A[1], local.A[2], local.A[3], local.A[4], + local.A[5], local.A[6], local.A[7], local.W[i], K[i] ); i++; + P( local.A[7], local.A[0], local.A[1], local.A[2], local.A[3], + local.A[4], local.A[5], local.A[6], local.W[i], K[i] ); i++; + P( local.A[6], local.A[7], local.A[0], local.A[1], local.A[2], + local.A[3], local.A[4], local.A[5], local.W[i], K[i] ); i++; + P( local.A[5], local.A[6], local.A[7], local.A[0], local.A[1], + local.A[2], local.A[3], local.A[4], local.W[i], K[i] ); i++; + P( local.A[4], local.A[5], local.A[6], local.A[7], local.A[0], + local.A[1], local.A[2], local.A[3], local.W[i], K[i] ); i++; + P( local.A[3], local.A[4], local.A[5], local.A[6], local.A[7], + local.A[0], local.A[1], local.A[2], local.W[i], K[i] ); i++; + P( local.A[2], local.A[3], local.A[4], local.A[5], local.A[6], + local.A[7], local.A[0], local.A[1], local.W[i], K[i] ); i++; + P( local.A[1], local.A[2], local.A[3], local.A[4], local.A[5], + local.A[6], local.A[7], local.A[0], local.W[i], K[i] ); i++; } while( i < 80 ); #endif /* MBEDTLS_SHA512_SMALLER */ for( i = 0; i < 8; i++ ) - ctx->state[i] += A[i]; + ctx->state[i] += local.A[i]; + + /* Zeroise buffers and variables to clear sensitive data from memory. */ + mbedtls_platform_zeroize( &local, sizeof( local ) ); return( 0 ); } @@ -516,8 +534,7 @@ void mbedtls_sha512( const unsigned char *input, static const unsigned char sha512_test_buf[3][113] = { { "abc" }, - { "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmn" - "hijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu" }, + { "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhijklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu" }, { "" } }; diff --git a/connectivity/mbedtls/source/ssl_cli.c b/connectivity/mbedtls/source/ssl_cli.c index 083b720be1..a8331d9bb3 100644 --- a/connectivity/mbedtls/source/ssl_cli.c +++ b/connectivity/mbedtls/source/ssl_cli.c @@ -63,7 +63,7 @@ static int ssl_conf_has_static_psk( mbedtls_ssl_config const *conf ) return( 1 ); #if defined(MBEDTLS_USE_PSA_CRYPTO) - if( conf->psk_opaque != 0 ) + if( ! mbedtls_svc_key_id_is_null( conf->psk_opaque ) ) return( 1 ); #endif /* MBEDTLS_USE_PSA_CRYPTO */ @@ -756,6 +756,126 @@ static int ssl_write_alpn_ext( mbedtls_ssl_context *ssl, } #endif /* MBEDTLS_SSL_ALPN */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) +static int ssl_write_use_srtp_ext( mbedtls_ssl_context *ssl, + unsigned char *buf, + const unsigned char *end, + size_t *olen ) +{ + unsigned char *p = buf; + size_t protection_profiles_index = 0, ext_len = 0; + uint16_t mki_len = 0, profile_value = 0; + + *olen = 0; + + if( ( ssl->conf->transport != MBEDTLS_SSL_TRANSPORT_DATAGRAM ) || + ( ssl->conf->dtls_srtp_profile_list == NULL ) || + ( ssl->conf->dtls_srtp_profile_list_len == 0 ) ) + { + return( 0 ); + } + + /* RFC 5764 section 4.1.1 + * uint8 SRTPProtectionProfile[2]; + * + * struct { + * SRTPProtectionProfiles SRTPProtectionProfiles; + * opaque srtp_mki<0..255>; + * } UseSRTPData; + * SRTPProtectionProfile SRTPProtectionProfiles<2..2^16-1>; + */ + if( ssl->conf->dtls_srtp_mki_support == MBEDTLS_SSL_DTLS_SRTP_MKI_SUPPORTED ) + { + mki_len = ssl->dtls_srtp_info.mki_len; + } + /* Extension length = 2 bytes for profiles length, + * ssl->conf->dtls_srtp_profile_list_len * 2 (each profile is 2 bytes length ), + * 1 byte for srtp_mki vector length and the mki_len value + */ + ext_len = 2 + 2 * ( ssl->conf->dtls_srtp_profile_list_len ) + 1 + mki_len; + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "client hello, adding use_srtp extension" ) ); + + /* Check there is room in the buffer for the extension + 4 bytes + * - the extension tag (2 bytes) + * - the extension length (2 bytes) + */ + MBEDTLS_SSL_CHK_BUF_PTR( p, end, ext_len + 4 ); + + *p++ = (unsigned char)( ( MBEDTLS_TLS_EXT_USE_SRTP >> 8 ) & 0xFF ); + *p++ = (unsigned char)( ( MBEDTLS_TLS_EXT_USE_SRTP ) & 0xFF ); + + + *p++ = (unsigned char)( ( ( ext_len & 0xFF00 ) >> 8 ) & 0xFF ); + *p++ = (unsigned char)( ext_len & 0xFF ); + + /* protection profile length: 2*(ssl->conf->dtls_srtp_profile_list_len) */ + /* micro-optimization: + * the list size is limited to MBEDTLS_TLS_SRTP_MAX_PROFILE_LIST_LENGTH + * which is lower than 127, so the upper byte of the length is always 0 + * For the documentation, the more generic code is left in comments + * *p++ = (unsigned char)( ( ( 2 * ssl->conf->dtls_srtp_profile_list_len ) + * >> 8 ) & 0xFF ); + */ + *p++ = 0; + *p++ = (unsigned char)( ( 2 * ssl->conf->dtls_srtp_profile_list_len ) + & 0xFF ); + + for( protection_profiles_index=0; + protection_profiles_index < ssl->conf->dtls_srtp_profile_list_len; + protection_profiles_index++ ) + { + profile_value = mbedtls_ssl_check_srtp_profile_value + ( ssl->conf->dtls_srtp_profile_list[protection_profiles_index] ); + if( profile_value != MBEDTLS_TLS_SRTP_UNSET ) + { + MBEDTLS_SSL_DEBUG_MSG( 3, ( "ssl_write_use_srtp_ext, add profile: %04x", + profile_value ) ); + *p++ = ( ( profile_value >> 8 ) & 0xFF ); + *p++ = ( profile_value & 0xFF ); + } + else + { + /* + * Note: we shall never arrive here as protection profiles + * is checked by mbedtls_ssl_conf_dtls_srtp_protection_profiles function + */ + MBEDTLS_SSL_DEBUG_MSG( 3, + ( "client hello, " + "illegal DTLS-SRTP protection profile %d", + ssl->conf->dtls_srtp_profile_list[protection_profiles_index] + ) ); + return( MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED ); + } + } + + *p++ = mki_len & 0xFF; + + if( mki_len != 0 ) + { + memcpy( p, ssl->dtls_srtp_info.mki_value, mki_len ); + /* + * Increment p to point to the current position. + */ + p += mki_len; + MBEDTLS_SSL_DEBUG_BUF( 3, "sending mki", ssl->dtls_srtp_info.mki_value, + ssl->dtls_srtp_info.mki_len ); + } + + /* + * total extension length: extension type (2 bytes) + * + extension length (2 bytes) + * + protection profile length (2 bytes) + * + 2 * number of protection profiles + * + srtp_mki vector length(1 byte) + * + mki value + */ + *olen = p - buf; + + return( 0 ); +} +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + /* * Generate random bytes for ClientHello */ @@ -1277,6 +1397,16 @@ static int ssl_write_client_hello( mbedtls_ssl_context *ssl ) ext_len += olen; #endif +#if defined(MBEDTLS_SSL_DTLS_SRTP) + if( ( ret = ssl_write_use_srtp_ext( ssl, p + 2 + ext_len, + end, &olen ) ) != 0 ) + { + MBEDTLS_SSL_DEBUG_RET( 1, "ssl_write_use_srtp_ext", ret ); + return( ret ); + } + ext_len += olen; +#endif + #if defined(MBEDTLS_SSL_SESSION_TICKETS) if( ( ret = ssl_write_session_ticket_ext( ssl, p + 2 + ext_len, end, &olen ) ) != 0 ) @@ -1710,6 +1840,123 @@ static int ssl_parse_alpn_ext( mbedtls_ssl_context *ssl, } #endif /* MBEDTLS_SSL_ALPN */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) +static int ssl_parse_use_srtp_ext( mbedtls_ssl_context *ssl, + const unsigned char *buf, + size_t len ) +{ + mbedtls_ssl_srtp_profile server_protection = MBEDTLS_TLS_SRTP_UNSET; + size_t i, mki_len = 0; + uint16_t server_protection_profile_value = 0; + + /* If use_srtp is not configured, just ignore the extension */ + if( ( ssl->conf->transport != MBEDTLS_SSL_TRANSPORT_DATAGRAM ) || + ( ssl->conf->dtls_srtp_profile_list == NULL ) || + ( ssl->conf->dtls_srtp_profile_list_len == 0 ) ) + return( 0 ); + + /* RFC 5764 section 4.1.1 + * uint8 SRTPProtectionProfile[2]; + * + * struct { + * SRTPProtectionProfiles SRTPProtectionProfiles; + * opaque srtp_mki<0..255>; + * } UseSRTPData; + + * SRTPProtectionProfile SRTPProtectionProfiles<2..2^16-1>; + * + */ + if( ssl->conf->dtls_srtp_mki_support == MBEDTLS_SSL_DTLS_SRTP_MKI_SUPPORTED ) + { + mki_len = ssl->dtls_srtp_info.mki_len; + } + + /* + * Length is 5 + optional mki_value : one protection profile length (2 bytes) + * + protection profile (2 bytes) + * + mki_len(1 byte) + * and optional srtp_mki + */ + if( ( len < 5 ) || ( len != ( buf[4] + 5u ) ) ) + return( MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO ); + + /* + * get the server protection profile + */ + + /* + * protection profile length must be 0x0002 as we must have only + * one protection profile in server Hello + */ + if( ( buf[0] != 0 ) || ( buf[1] != 2 ) ) + return( MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO ); + + server_protection_profile_value = ( buf[2] << 8 ) | buf[3]; + server_protection = mbedtls_ssl_check_srtp_profile_value( + server_protection_profile_value ); + if( server_protection != MBEDTLS_TLS_SRTP_UNSET ) + { + MBEDTLS_SSL_DEBUG_MSG( 3, ( "found srtp profile: %s", + mbedtls_ssl_get_srtp_profile_as_string( + server_protection ) ) ); + } + + ssl->dtls_srtp_info.chosen_dtls_srtp_profile = MBEDTLS_TLS_SRTP_UNSET; + + /* + * Check we have the server profile in our list + */ + for( i=0; i < ssl->conf->dtls_srtp_profile_list_len; i++) + { + if( server_protection == ssl->conf->dtls_srtp_profile_list[i] ) + { + ssl->dtls_srtp_info.chosen_dtls_srtp_profile = ssl->conf->dtls_srtp_profile_list[i]; + MBEDTLS_SSL_DEBUG_MSG( 3, ( "selected srtp profile: %s", + mbedtls_ssl_get_srtp_profile_as_string( + server_protection ) ) ); + break; + } + } + + /* If no match was found : server problem, it shall never answer with incompatible profile */ + if( ssl->dtls_srtp_info.chosen_dtls_srtp_profile == MBEDTLS_TLS_SRTP_UNSET ) + { + mbedtls_ssl_send_alert_message( ssl, MBEDTLS_SSL_ALERT_LEVEL_FATAL, + MBEDTLS_SSL_ALERT_MSG_HANDSHAKE_FAILURE ); + return( MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO ); + } + + /* If server does not use mki in its reply, make sure the client won't keep + * one as negotiated */ + if( len == 5 ) + { + ssl->dtls_srtp_info.mki_len = 0; + } + + /* + * RFC5764: + * If the client detects a nonzero-length MKI in the server's response + * that is different than the one the client offered, then the client + * MUST abort the handshake and SHOULD send an invalid_parameter alert. + */ + if( len > 5 && ( buf[4] != mki_len || + ( memcmp( ssl->dtls_srtp_info.mki_value, &buf[5], mki_len ) ) ) ) + { + mbedtls_ssl_send_alert_message( ssl, MBEDTLS_SSL_ALERT_LEVEL_FATAL, + MBEDTLS_SSL_ALERT_MSG_ILLEGAL_PARAMETER ); + return( MBEDTLS_ERR_SSL_BAD_HS_SERVER_HELLO ); + } +#if defined (MBEDTLS_DEBUG_C) + if( len > 5 ) + { + MBEDTLS_SSL_DEBUG_BUF( 3, "received mki", ssl->dtls_srtp_info.mki_value, + ssl->dtls_srtp_info.mki_len ); + } +#endif + return( 0 ); +} +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + /* * Parse HelloVerifyRequest. Only called after verifying the HS type. */ @@ -2278,6 +2525,16 @@ static int ssl_parse_server_hello( mbedtls_ssl_context *ssl ) break; #endif /* MBEDTLS_SSL_ALPN */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) + case MBEDTLS_TLS_EXT_USE_SRTP: + MBEDTLS_SSL_DEBUG_MSG( 3, ( "found use_srtp extension" ) ); + + if( ( ret = ssl_parse_use_srtp_ext( ssl, ext + 4, ext_size ) ) != 0 ) + return( ret ); + + break; +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + default: MBEDTLS_SSL_DEBUG_MSG( 3, ( "unknown extension found: %d (ignoring)", ext_id ) ); @@ -3545,7 +3802,7 @@ static int ssl_write_client_key_exchange( mbedtls_ssl_context *ssl ) status = psa_destroy_key( handshake->ecdh_psa_privkey ); if( status != PSA_SUCCESS ) return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); - handshake->ecdh_psa_privkey = 0; + handshake->ecdh_psa_privkey = MBEDTLS_SVC_KEY_ID_INIT; } else #endif /* MBEDTLS_USE_PSA_CRYPTO && diff --git a/connectivity/mbedtls/source/ssl_msg.c b/connectivity/mbedtls/source/ssl_msg.c index 2ea35808ad..72f09bb42a 100644 --- a/connectivity/mbedtls/source/ssl_msg.c +++ b/connectivity/mbedtls/source/ssl_msg.c @@ -850,20 +850,21 @@ int mbedtls_ssl_encrypt_buf( mbedtls_ssl_context *ssl, * Encrypt and authenticate */ - if( ( ret = mbedtls_cipher_auth_encrypt( &transform->cipher_ctx_enc, + if( ( ret = mbedtls_cipher_auth_encrypt_ext( &transform->cipher_ctx_enc, iv, transform->ivlen, - add_data, add_data_len, /* add data */ - data, rec->data_len, /* source */ - data, &rec->data_len, /* destination */ - data + rec->data_len, transform->taglen ) ) != 0 ) + add_data, add_data_len, + data, rec->data_len, /* src */ + data, rec->buf_len - (data - rec->buf), /* dst */ + &rec->data_len, + transform->taglen ) ) != 0 ) { MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_auth_encrypt", ret ); return( ret ); } MBEDTLS_SSL_DEBUG_BUF( 4, "after encrypt: tag", - data + rec->data_len, transform->taglen ); + data + rec->data_len - transform->taglen, + transform->taglen ); /* Account for authentication tag. */ - rec->data_len += transform->taglen; post_avail -= transform->taglen; /* @@ -1045,21 +1046,86 @@ int mbedtls_ssl_encrypt_buf( mbedtls_ssl_context *ssl, #if defined(MBEDTLS_SSL_SOME_SUITES_USE_TLS_CBC) /* - * Constant-flow conditional memcpy: - * - if c1 == c2, equivalent to memcpy(dst, src, len), - * - otherwise, a no-op, - * but with execution flow independent of the values of c1 and c2. + * Turn a bit into a mask: + * - if bit == 1, return the all-bits 1 mask, aka (size_t) -1 + * - if bit == 0, return the all-bits 0 mask, aka 0 * - * Use only bit operations to avoid branches that could be used by some - * compilers on some platforms to translate comparison operators. + * This function can be used to write constant-time code by replacing branches + * with bit operations using masks. + * + * This function is implemented without using comparison operators, as those + * might be translated to branches by some compilers on some platforms. */ -static void mbedtls_ssl_cf_memcpy_if_eq( unsigned char *dst, - const unsigned char *src, - size_t len, - size_t c1, size_t c2 ) +static size_t mbedtls_ssl_cf_mask_from_bit( size_t bit ) { - /* diff = 0 if c1 == c2, non-zero otherwise */ - const size_t diff = c1 ^ c2; + /* MSVC has a warning about unary minus on unsigned integer types, + * but this is well-defined and precisely what we want to do here. */ +#if defined(_MSC_VER) +#pragma warning( push ) +#pragma warning( disable : 4146 ) +#endif + return -bit; +#if defined(_MSC_VER) +#pragma warning( pop ) +#endif +} + +/* + * Constant-flow mask generation for "less than" comparison: + * - if x < y, return all bits 1, that is (size_t) -1 + * - otherwise, return all bits 0, that is 0 + * + * This function can be used to write constant-time code by replacing branches + * with bit operations using masks. + * + * This function is implemented without using comparison operators, as those + * might be translated to branches by some compilers on some platforms. + */ +static size_t mbedtls_ssl_cf_mask_lt( size_t x, size_t y ) +{ + /* This has the most significant bit set if and only if x < y */ + const size_t sub = x - y; + + /* sub1 = (x < y) ? 1 : 0 */ + const size_t sub1 = sub >> ( sizeof( sub ) * 8 - 1 ); + + /* mask = (x < y) ? 0xff... : 0x00... */ + const size_t mask = mbedtls_ssl_cf_mask_from_bit( sub1 ); + + return( mask ); +} + +/* + * Constant-flow mask generation for "greater or equal" comparison: + * - if x >= y, return all bits 1, that is (size_t) -1 + * - otherwise, return all bits 0, that is 0 + * + * This function can be used to write constant-time code by replacing branches + * with bit operations using masks. + * + * This function is implemented without using comparison operators, as those + * might be translated to branches by some compilers on some platforms. + */ +static size_t mbedtls_ssl_cf_mask_ge( size_t x, size_t y ) +{ + return( ~mbedtls_ssl_cf_mask_lt( x, y ) ); +} + +/* + * Constant-flow boolean "equal" comparison: + * return x == y + * + * This function can be used to write constant-time code by replacing branches + * with bit operations - it can be used in conjunction with + * mbedtls_ssl_cf_mask_from_bit(). + * + * This function is implemented without using comparison operators, as those + * might be translated to branches by some compilers on some platforms. + */ +static size_t mbedtls_ssl_cf_bool_eq( size_t x, size_t y ) +{ + /* diff = 0 if x == y, non-zero otherwise */ + const size_t diff = x ^ y; /* MSVC has a warning about unary minus on unsigned integer types, * but this is well-defined and precisely what we want to do here. */ @@ -1068,22 +1134,40 @@ static void mbedtls_ssl_cf_memcpy_if_eq( unsigned char *dst, #pragma warning( disable : 4146 ) #endif - /* diff_msb's most significant bit is equal to c1 != c2 */ + /* diff_msb's most significant bit is equal to x != y */ const size_t diff_msb = ( diff | -diff ); - /* diff1 = c1 != c2 */ - const size_t diff1 = diff_msb >> ( sizeof( diff_msb ) * 8 - 1 ); - - /* mask = c1 != c2 ? 0xff : 0x00 */ - const unsigned char mask = (unsigned char) -diff1; - #if defined(_MSC_VER) #pragma warning( pop ) #endif - /* dst[i] = c1 != c2 ? dst[i] : src[i] */ + /* diff1 = (x != y) ? 1 : 0 */ + const size_t diff1 = diff_msb >> ( sizeof( diff_msb ) * 8 - 1 ); + + return( 1 ^ diff1 ); +} + +/* + * Constant-flow conditional memcpy: + * - if c1 == c2, equivalent to memcpy(dst, src, len), + * - otherwise, a no-op, + * but with execution flow independent of the values of c1 and c2. + * + * This function is implemented without using comparison operators, as those + * might be translated to branches by some compilers on some platforms. + */ +static void mbedtls_ssl_cf_memcpy_if_eq( unsigned char *dst, + const unsigned char *src, + size_t len, + size_t c1, size_t c2 ) +{ + /* mask = c1 == c2 ? 0xff : 0x00 */ + const size_t equal = mbedtls_ssl_cf_bool_eq( c1, c2 ); + const unsigned char mask = (unsigned char) mbedtls_ssl_cf_mask_from_bit( equal ); + + /* dst[i] = c1 == c2 ? src[i] : dst[i] */ for( size_t i = 0; i < len; i++ ) - dst[i] = ( dst[i] & mask ) | ( src[i] & ~mask ); + dst[i] = ( src[i] & mask ) | ( dst[i] & ~mask ); } /* @@ -1301,7 +1385,9 @@ int mbedtls_ssl_decrypt_buf( mbedtls_ssl_context const *ssl, /* Check that there's space for the authentication tag. */ if( rec->data_len < transform->taglen ) { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "msglen (%d) < taglen (%d) " ) ); + MBEDTLS_SSL_DEBUG_MSG( 1, ( "msglen (%d) < taglen (%d) ", + rec->data_len, + transform->taglen ) ); return( MBEDTLS_ERR_SSL_INVALID_MAC ); } rec->data_len -= transform->taglen; @@ -1337,12 +1423,11 @@ int mbedtls_ssl_decrypt_buf( mbedtls_ssl_context const *ssl, /* * Decrypt and authenticate */ - if( ( ret = mbedtls_cipher_auth_decrypt( &transform->cipher_ctx_dec, + if( ( ret = mbedtls_cipher_auth_decrypt_ext( &transform->cipher_ctx_dec, iv, transform->ivlen, add_data, add_data_len, - data, rec->data_len, - data, &olen, - data + rec->data_len, + data, rec->data_len + transform->taglen, /* src */ + data, rec->buf_len - (data - rec->buf), &olen, /* dst */ transform->taglen ) ) != 0 ) { MBEDTLS_SSL_DEBUG_RET( 1, "mbedtls_cipher_auth_decrypt", ret ); @@ -1528,8 +1613,11 @@ int mbedtls_ssl_decrypt_buf( mbedtls_ssl_context const *ssl, if( auth_done == 1 ) { - correct *= ( rec->data_len >= padlen + 1 ); - padlen *= ( rec->data_len >= padlen + 1 ); + const size_t mask = mbedtls_ssl_cf_mask_ge( + rec->data_len, + padlen + 1 ); + correct &= mask; + padlen &= mask; } else { @@ -1543,8 +1631,11 @@ int mbedtls_ssl_decrypt_buf( mbedtls_ssl_context const *ssl, } #endif - correct *= ( rec->data_len >= transform->maclen + padlen + 1 ); - padlen *= ( rec->data_len >= transform->maclen + padlen + 1 ); + const size_t mask = mbedtls_ssl_cf_mask_ge( + rec->data_len, + transform->maclen + padlen + 1 ); + correct &= mask; + padlen &= mask; } padlen++; @@ -1555,6 +1646,10 @@ int mbedtls_ssl_decrypt_buf( mbedtls_ssl_context const *ssl, #if defined(MBEDTLS_SSL_PROTO_SSL3) if( transform->minor_ver == MBEDTLS_SSL_MINOR_VERSION_0 ) { + /* This is the SSL 3.0 path, we don't have to worry about Lucky + * 13, because there's a strictly worse padding attack built in + * the protocol (known as part of POODLE), so we don't care if the + * code is not constant-time, in particular branches are OK. */ if( padlen > transform->ivlen ) { #if defined(MBEDTLS_SSL_DEBUG_ALL) @@ -1578,7 +1673,6 @@ int mbedtls_ssl_decrypt_buf( mbedtls_ssl_context const *ssl, * `min(256,plaintext_len)` reads (but take into account * only the last `padlen` bytes for the padding check). */ size_t pad_count = 0; - size_t real_count = 0; volatile unsigned char* const check = data; /* Index of first padding byte; it has been ensured above @@ -1590,16 +1684,21 @@ int mbedtls_ssl_decrypt_buf( mbedtls_ssl_context const *ssl, for( idx = start_idx; idx < rec->data_len; idx++ ) { - real_count |= ( idx >= padding_idx ); - pad_count += real_count * ( check[idx] == padlen - 1 ); + /* pad_count += (idx >= padding_idx) && + * (check[idx] == padlen - 1); + */ + const size_t mask = mbedtls_ssl_cf_mask_ge( idx, padding_idx ); + const size_t equal = mbedtls_ssl_cf_bool_eq( check[idx], + padlen - 1 ); + pad_count += mask & equal; } - correct &= ( pad_count == padlen ); + correct &= mbedtls_ssl_cf_bool_eq( pad_count, padlen ); #if defined(MBEDTLS_SSL_DEBUG_ALL) if( padlen > 0 && correct == 0 ) MBEDTLS_SSL_DEBUG_MSG( 1, ( "bad padding byte detected" ) ); #endif - padlen &= correct * 0x1FF; + padlen &= mbedtls_ssl_cf_mask_from_bit( correct ); } else #endif /* MBEDTLS_SSL_PROTO_TLS1 || MBEDTLS_SSL_PROTO_TLS1_1 || \ @@ -1921,14 +2020,6 @@ int mbedtls_ssl_fetch_input( mbedtls_ssl_context *ssl, size_t nb_want ) { uint32_t timeout; - /* Just to be sure */ - if( ssl->f_set_timer == NULL || ssl->f_get_timer == NULL ) - { - MBEDTLS_SSL_DEBUG_MSG( 1, ( "You must use " - "mbedtls_ssl_set_timer_cb() for DTLS" ) ); - return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - } - /* * The point is, we need to always read a full datagram at once, so we * sometimes read more then requested, and handle the additional data. diff --git a/connectivity/mbedtls/source/ssl_srv.c b/connectivity/mbedtls/source/ssl_srv.c index 2e63fced35..e33b828add 100644 --- a/connectivity/mbedtls/source/ssl_srv.c +++ b/connectivity/mbedtls/source/ssl_srv.c @@ -157,7 +157,7 @@ static int ssl_conf_has_psk_or_cb( mbedtls_ssl_config const *conf ) return( 1 ); #if defined(MBEDTLS_USE_PSA_CRYPTO) - if( conf->psk_opaque != 0 ) + if( ! mbedtls_svc_key_id_is_null( conf->psk_opaque ) ) return( 1 ); #endif /* MBEDTLS_USE_PSA_CRYPTO */ @@ -172,13 +172,13 @@ static int ssl_use_opaque_psk( mbedtls_ssl_context const *ssl ) /* If we've used a callback to select the PSK, * the static configuration is irrelevant. */ - if( ssl->handshake->psk_opaque != 0 ) + if( ! mbedtls_svc_key_id_is_null( ssl->handshake->psk_opaque ) ) return( 1 ); return( 0 ); } - if( ssl->conf->psk_opaque != 0 ) + if( ! mbedtls_svc_key_id_is_null( ssl->conf->psk_opaque ) ) return( 1 ); return( 0 ); @@ -776,6 +776,126 @@ static int ssl_parse_alpn_ext( mbedtls_ssl_context *ssl, } #endif /* MBEDTLS_SSL_ALPN */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) +static int ssl_parse_use_srtp_ext( mbedtls_ssl_context *ssl, + const unsigned char *buf, + size_t len ) +{ + mbedtls_ssl_srtp_profile client_protection = MBEDTLS_TLS_SRTP_UNSET; + size_t i,j; + size_t profile_length; + uint16_t mki_length; + /*! 2 bytes for profile length and 1 byte for mki len */ + const size_t size_of_lengths = 3; + + /* If use_srtp is not configured, just ignore the extension */ + if( ( ssl->conf->transport != MBEDTLS_SSL_TRANSPORT_DATAGRAM ) || + ( ssl->conf->dtls_srtp_profile_list == NULL ) || + ( ssl->conf->dtls_srtp_profile_list_len == 0 ) ) + { + return( 0 ); + } + + /* RFC5764 section 4.1.1 + * uint8 SRTPProtectionProfile[2]; + * + * struct { + * SRTPProtectionProfiles SRTPProtectionProfiles; + * opaque srtp_mki<0..255>; + * } UseSRTPData; + + * SRTPProtectionProfile SRTPProtectionProfiles<2..2^16-1>; + */ + + /* + * Min length is 5: at least one protection profile(2 bytes) + * and length(2 bytes) + srtp_mki length(1 byte) + * Check here that we have at least 2 bytes of protection profiles length + * and one of srtp_mki length + */ + if( len < size_of_lengths ) + { + mbedtls_ssl_send_alert_message( ssl, MBEDTLS_SSL_ALERT_LEVEL_FATAL, + MBEDTLS_SSL_ALERT_MSG_HANDSHAKE_FAILURE ); + return( MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO ); + } + + ssl->dtls_srtp_info.chosen_dtls_srtp_profile = MBEDTLS_TLS_SRTP_UNSET; + + /* first 2 bytes are protection profile length(in bytes) */ + profile_length = ( buf[0] << 8 ) | buf[1]; + buf += 2; + + /* The profile length cannot be bigger than input buffer size - lengths fields */ + if( profile_length > len - size_of_lengths || + profile_length % 2 != 0 ) /* profiles are 2 bytes long, so the length must be even */ + { + mbedtls_ssl_send_alert_message( ssl, MBEDTLS_SSL_ALERT_LEVEL_FATAL, + MBEDTLS_SSL_ALERT_MSG_HANDSHAKE_FAILURE ); + return( MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO ); + } + /* + * parse the extension list values are defined in + * http://www.iana.org/assignments/srtp-protection/srtp-protection.xhtml + */ + for( j = 0; j < profile_length; j += 2 ) + { + uint16_t protection_profile_value = buf[j] << 8 | buf[j + 1]; + client_protection = mbedtls_ssl_check_srtp_profile_value( protection_profile_value ); + + if( client_protection != MBEDTLS_TLS_SRTP_UNSET ) + { + MBEDTLS_SSL_DEBUG_MSG( 3, ( "found srtp profile: %s", + mbedtls_ssl_get_srtp_profile_as_string( + client_protection ) ) ); + } + else + { + continue; + } + /* check if suggested profile is in our list */ + for( i = 0; i < ssl->conf->dtls_srtp_profile_list_len; i++) + { + if( client_protection == ssl->conf->dtls_srtp_profile_list[i] ) + { + ssl->dtls_srtp_info.chosen_dtls_srtp_profile = ssl->conf->dtls_srtp_profile_list[i]; + MBEDTLS_SSL_DEBUG_MSG( 3, ( "selected srtp profile: %s", + mbedtls_ssl_get_srtp_profile_as_string( + client_protection ) ) ); + break; + } + } + if( ssl->dtls_srtp_info.chosen_dtls_srtp_profile != MBEDTLS_TLS_SRTP_UNSET ) + break; + } + buf += profile_length; /* buf points to the mki length */ + mki_length = *buf; + buf++; + + if( mki_length > MBEDTLS_TLS_SRTP_MAX_MKI_LENGTH || + mki_length + profile_length + size_of_lengths != len ) + { + mbedtls_ssl_send_alert_message( ssl, MBEDTLS_SSL_ALERT_LEVEL_FATAL, + MBEDTLS_SSL_ALERT_MSG_HANDSHAKE_FAILURE ); + return( MBEDTLS_ERR_SSL_BAD_HS_CLIENT_HELLO ); + } + + /* Parse the mki only if present and mki is supported locally */ + if( ssl->conf->dtls_srtp_mki_support == MBEDTLS_SSL_DTLS_SRTP_MKI_SUPPORTED && + mki_length > 0 ) + { + ssl->dtls_srtp_info.mki_len = mki_length; + + memcpy( ssl->dtls_srtp_info.mki_value, buf, mki_length ); + + MBEDTLS_SSL_DEBUG_BUF( 3, "using mki", ssl->dtls_srtp_info.mki_value, + ssl->dtls_srtp_info.mki_len ); + } + + return( 0 ); +} +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + /* * Auxiliary functions for ServerHello parsing and related actions */ @@ -1942,6 +2062,16 @@ read_record_header: break; #endif /* MBEDTLS_SSL_SESSION_TICKETS */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) + case MBEDTLS_TLS_EXT_USE_SRTP: + MBEDTLS_SSL_DEBUG_MSG( 3, ( "found use_srtp extension" ) ); + + ret = ssl_parse_use_srtp_ext( ssl, ext + 4, ext_size ); + if( ret != 0 ) + return( ret ); + break; +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + default: MBEDTLS_SSL_DEBUG_MSG( 3, ( "unknown extension found: %d (ignoring)", ext_id ) ); @@ -2500,6 +2630,78 @@ static void ssl_write_alpn_ext( mbedtls_ssl_context *ssl, } #endif /* MBEDTLS_ECDH_C || MBEDTLS_ECDSA_C */ +#if defined(MBEDTLS_SSL_DTLS_SRTP ) && defined(MBEDTLS_SSL_PROTO_DTLS) +static void ssl_write_use_srtp_ext( mbedtls_ssl_context *ssl, + unsigned char *buf, + size_t *olen ) +{ + size_t mki_len = 0, ext_len = 0; + uint16_t profile_value = 0; + const unsigned char *end = ssl->out_msg + MBEDTLS_SSL_OUT_CONTENT_LEN; + + *olen = 0; + + if( ( ssl->conf->transport != MBEDTLS_SSL_TRANSPORT_DATAGRAM ) || + ( ssl->dtls_srtp_info.chosen_dtls_srtp_profile == MBEDTLS_TLS_SRTP_UNSET ) ) + { + return; + } + + MBEDTLS_SSL_DEBUG_MSG( 3, ( "server hello, adding use_srtp extension" ) ); + + if( ssl->conf->dtls_srtp_mki_support == MBEDTLS_SSL_DTLS_SRTP_MKI_SUPPORTED ) + { + mki_len = ssl->dtls_srtp_info.mki_len; + } + + /* The extension total size is 9 bytes : + * - 2 bytes for the extension tag + * - 2 bytes for the total size + * - 2 bytes for the protection profile length + * - 2 bytes for the protection profile + * - 1 byte for the mki length + * + the actual mki length + * Check we have enough room in the output buffer */ + if( (size_t)( end - buf ) < mki_len + 9 ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "buffer too small" ) ); + return; + } + + /* extension */ + buf[0] = (unsigned char)( ( MBEDTLS_TLS_EXT_USE_SRTP >> 8 ) & 0xFF ); + buf[1] = (unsigned char)( ( MBEDTLS_TLS_EXT_USE_SRTP ) & 0xFF ); + /* + * total length 5 and mki value: only one profile(2 bytes) + * and length(2 bytes) and srtp_mki ) + */ + ext_len = 5 + mki_len; + buf[2] = (unsigned char)( ( ext_len >> 8 ) & 0xFF ); + buf[3] = (unsigned char)( ext_len & 0xFF ); + + /* protection profile length: 2 */ + buf[4] = 0x00; + buf[5] = 0x02; + profile_value = mbedtls_ssl_check_srtp_profile_value( + ssl->dtls_srtp_info.chosen_dtls_srtp_profile ); + if( profile_value != MBEDTLS_TLS_SRTP_UNSET ) + { + buf[6] = (unsigned char)( ( profile_value >> 8 ) & 0xFF ); + buf[7] = (unsigned char)( profile_value & 0xFF ); + } + else + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "use_srtp extension invalid profile" ) ); + return; + } + + buf[8] = mki_len & 0xFF; + memcpy( &buf[9], ssl->dtls_srtp_info.mki_value, mki_len ); + + *olen = 9 + mki_len; +} +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + #if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) static int ssl_write_hello_verify_request( mbedtls_ssl_context *ssl ) { @@ -2788,6 +2990,11 @@ static int ssl_write_server_hello( mbedtls_ssl_context *ssl ) ext_len += olen; #endif +#if defined(MBEDTLS_SSL_DTLS_SRTP) + ssl_write_use_srtp_ext( ssl, p + 2 + ext_len, &olen ); + ext_len += olen; +#endif + MBEDTLS_SSL_DEBUG_MSG( 3, ( "server hello, total extension length: %d", ext_len ) ); if( ext_len > 0 ) @@ -3722,11 +3929,12 @@ static int ssl_parse_encrypted_pms( mbedtls_ssl_context *ssl, /* In case of a failure in decryption, the decryption may write less than * 2 bytes of output, but we always read the first two bytes. It doesn't * matter in the end because diff will be nonzero in that case due to - * peer_pmslen being less than 48, and we only care whether diff is 0. - * But do initialize peer_pms for robustness anyway. This also makes - * memory analyzers happy (don't access uninitialized memory, even - * if it's an unsigned char). */ + * ret being nonzero, and we only care whether diff is 0. + * But do initialize peer_pms and peer_pmslen for robustness anyway. This + * also makes memory analyzers happy (don't access uninitialized memory, + * even if it's an unsigned char). */ peer_pms[0] = peer_pms[1] = ~0; + peer_pmslen = 0; ret = ssl_decrypt_encrypted_pms( ssl, p, end, peer_pms, diff --git a/connectivity/mbedtls/source/ssl_ticket.c b/connectivity/mbedtls/source/ssl_ticket.c index e3e802315a..626d137cc6 100644 --- a/connectivity/mbedtls/source/ssl_ticket.c +++ b/connectivity/mbedtls/source/ssl_ticket.c @@ -209,7 +209,6 @@ int mbedtls_ssl_ticket_write( void *p_ticket, unsigned char *iv = start + TICKET_KEY_NAME_BYTES; unsigned char *state_len_bytes = iv + TICKET_IV_BYTES; unsigned char *state = state_len_bytes + TICKET_CRYPT_LEN_BYTES; - unsigned char *tag; size_t clear_len, ciph_len; *tlen = 0; @@ -250,23 +249,23 @@ int mbedtls_ssl_ticket_write( void *p_ticket, state_len_bytes[1] = ( clear_len ) & 0xff; /* Encrypt and authenticate */ - tag = state + clear_len; - if( ( ret = mbedtls_cipher_auth_encrypt( &key->ctx, + if( ( ret = mbedtls_cipher_auth_encrypt_ext( &key->ctx, iv, TICKET_IV_BYTES, /* Additional data: key name, IV and length */ key_name, TICKET_ADD_DATA_LEN, - state, clear_len, state, &ciph_len, - tag, TICKET_AUTH_TAG_BYTES ) ) != 0 ) + state, clear_len, + state, end - state, &ciph_len, + TICKET_AUTH_TAG_BYTES ) ) != 0 ) { goto cleanup; } - if( ciph_len != clear_len ) + if( ciph_len != clear_len + TICKET_AUTH_TAG_BYTES ) { ret = MBEDTLS_ERR_SSL_INTERNAL_ERROR; goto cleanup; } - *tlen = TICKET_MIN_LEN + ciph_len; + *tlen = TICKET_MIN_LEN + ciph_len - TICKET_AUTH_TAG_BYTES; cleanup: #if defined(MBEDTLS_THREADING_C) @@ -308,7 +307,6 @@ int mbedtls_ssl_ticket_parse( void *p_ticket, unsigned char *iv = buf + TICKET_KEY_NAME_BYTES; unsigned char *enc_len_p = iv + TICKET_IV_BYTES; unsigned char *ticket = enc_len_p + TICKET_CRYPT_LEN_BYTES; - unsigned char *tag; size_t enc_len, clear_len; if( ctx == NULL || ctx->f_rng == NULL ) @@ -326,7 +324,6 @@ int mbedtls_ssl_ticket_parse( void *p_ticket, goto cleanup; enc_len = ( enc_len_p[0] << 8 ) | enc_len_p[1]; - tag = ticket + enc_len; if( len != TICKET_MIN_LEN + enc_len ) { @@ -344,13 +341,13 @@ int mbedtls_ssl_ticket_parse( void *p_ticket, } /* Decrypt and authenticate */ - if( ( ret = mbedtls_cipher_auth_decrypt( &key->ctx, + if( ( ret = mbedtls_cipher_auth_decrypt_ext( &key->ctx, iv, TICKET_IV_BYTES, /* Additional data: key name, IV and length */ key_name, TICKET_ADD_DATA_LEN, - ticket, enc_len, - ticket, &clear_len, - tag, TICKET_AUTH_TAG_BYTES ) ) != 0 ) + ticket, enc_len + TICKET_AUTH_TAG_BYTES, + ticket, enc_len, &clear_len, + TICKET_AUTH_TAG_BYTES ) ) != 0 ) { if( ret == MBEDTLS_ERR_CIPHER_AUTH_FAILED ) ret = MBEDTLS_ERR_SSL_INVALID_MAC; diff --git a/connectivity/mbedtls/source/ssl_tls.c b/connectivity/mbedtls/source/ssl_tls.c index 7062d53b78..a1a5859f05 100644 --- a/connectivity/mbedtls/source/ssl_tls.c +++ b/connectivity/mbedtls/source/ssl_tls.c @@ -446,7 +446,7 @@ exit: #if defined(MBEDTLS_USE_PSA_CRYPTO) static psa_status_t setup_psa_key_derivation( psa_key_derivation_operation_t* derivation, - psa_key_handle_t slot, + psa_key_id_t key, psa_algorithm_t alg, const unsigned char* seed, size_t seed_length, const unsigned char* label, size_t label_length, @@ -466,7 +466,7 @@ static psa_status_t setup_psa_key_derivation( psa_key_derivation_operation_t* de if( status != PSA_SUCCESS ) return( status ); - if( slot == 0 ) + if( mbedtls_svc_key_id_is_null( key ) ) { status = psa_key_derivation_input_bytes( derivation, PSA_KEY_DERIVATION_INPUT_SECRET, @@ -475,8 +475,7 @@ static psa_status_t setup_psa_key_derivation( psa_key_derivation_operation_t* de else { status = psa_key_derivation_input_key( - derivation, PSA_KEY_DERIVATION_INPUT_SECRET, - slot ); + derivation, PSA_KEY_DERIVATION_INPUT_SECRET, key ); } if( status != PSA_SUCCESS ) return( status ); @@ -507,7 +506,7 @@ static int tls_prf_generic( mbedtls_md_type_t md_type, { psa_status_t status; psa_algorithm_t alg; - psa_key_handle_t master_slot = 0; + psa_key_id_t master_key = MBEDTLS_SVC_KEY_ID_INIT; psa_key_derivation_operation_t derivation = PSA_KEY_DERIVATION_OPERATION_INIT; @@ -521,7 +520,7 @@ static int tls_prf_generic( mbedtls_md_type_t md_type, * this PRF is also used to derive an IV, in particular in EAP-TLS, * and for this use case it makes sense to have a 0-length "secret". * Since the key API doesn't allow importing a key of length 0, - * keep master_slot=0, which setup_psa_key_derivation() understands + * keep master_key=0, which setup_psa_key_derivation() understands * to mean a 0-length "secret" input. */ if( slen != 0 ) { @@ -530,13 +529,13 @@ static int tls_prf_generic( mbedtls_md_type_t md_type, psa_set_key_algorithm( &key_attributes, alg ); psa_set_key_type( &key_attributes, PSA_KEY_TYPE_DERIVE ); - status = psa_import_key( &key_attributes, secret, slen, &master_slot ); + status = psa_import_key( &key_attributes, secret, slen, &master_key ); if( status != PSA_SUCCESS ) return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); } status = setup_psa_key_derivation( &derivation, - master_slot, alg, + master_key, alg, random, rlen, (unsigned char const *) label, (size_t) strlen( label ), @@ -544,7 +543,7 @@ static int tls_prf_generic( mbedtls_md_type_t md_type, if( status != PSA_SUCCESS ) { psa_key_derivation_abort( &derivation ); - psa_destroy_key( master_slot ); + psa_destroy_key( master_key ); return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); } @@ -552,19 +551,19 @@ static int tls_prf_generic( mbedtls_md_type_t md_type, if( status != PSA_SUCCESS ) { psa_key_derivation_abort( &derivation ); - psa_destroy_key( master_slot ); + psa_destroy_key( master_key ); return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); } status = psa_key_derivation_abort( &derivation ); if( status != PSA_SUCCESS ) { - psa_destroy_key( master_slot ); + psa_destroy_key( master_key ); return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); } - if( master_slot != 0 ) - status = psa_destroy_key( master_slot ); + if( ! mbedtls_svc_key_id_is_null( master_key ) ) + status = psa_destroy_key( master_key ); if( status != PSA_SUCCESS ) return( MBEDTLS_ERR_SSL_HW_ACCEL_FAILED ); @@ -681,20 +680,20 @@ static void ssl_calc_finished_ssl( mbedtls_ssl_context *, unsigned char *, int ) #endif #if defined(MBEDTLS_SSL_PROTO_TLS1) || defined(MBEDTLS_SSL_PROTO_TLS1_1) -static void ssl_calc_verify_tls( const mbedtls_ssl_context *, unsigned char *, size_t * ); +static void ssl_calc_verify_tls( const mbedtls_ssl_context *, unsigned char*, size_t * ); static void ssl_calc_finished_tls( mbedtls_ssl_context *, unsigned char *, int ); #endif #if defined(MBEDTLS_SSL_PROTO_TLS1_2) #if defined(MBEDTLS_SHA256_C) static void ssl_update_checksum_sha256( mbedtls_ssl_context *, const unsigned char *, size_t ); -static void ssl_calc_verify_tls_sha256( const mbedtls_ssl_context *,unsigned char *, size_t * ); +static void ssl_calc_verify_tls_sha256( const mbedtls_ssl_context *,unsigned char*, size_t * ); static void ssl_calc_finished_tls_sha256( mbedtls_ssl_context *,unsigned char *, int ); #endif #if defined(MBEDTLS_SHA512_C) static void ssl_update_checksum_sha384( mbedtls_ssl_context *, const unsigned char *, size_t ); -static void ssl_calc_verify_tls_sha384( const mbedtls_ssl_context *, unsigned char *, size_t * ); +static void ssl_calc_verify_tls_sha384( const mbedtls_ssl_context *, unsigned char*, size_t * ); static void ssl_calc_finished_tls_sha384( mbedtls_ssl_context *, unsigned char *, int ); #endif #endif /* MBEDTLS_SSL_PROTO_TLS1_2 */ @@ -707,13 +706,13 @@ static int ssl_use_opaque_psk( mbedtls_ssl_context const *ssl ) { /* If we've used a callback to select the PSK, * the static configuration is irrelevant. */ - if( ssl->handshake->psk_opaque != 0 ) + if( ! mbedtls_svc_key_id_is_null( ssl->handshake->psk_opaque ) ) return( 1 ); return( 0 ); } - if( ssl->conf->psk_opaque != 0 ) + if( ! mbedtls_svc_key_id_is_null( ssl->conf->psk_opaque ) ) return( 1 ); return( 0 ); @@ -1514,7 +1513,7 @@ static int ssl_compute_master( mbedtls_ssl_handshake_params *handshake, /* Perform PSK-to-MS expansion in a single step. */ psa_status_t status; psa_algorithm_t alg; - psa_key_handle_t psk; + psa_key_id_t psk; psa_key_derivation_operation_t derivation = PSA_KEY_DERIVATION_OPERATION_INIT; mbedtls_md_type_t hash_alg = handshake->ciphersuite_info->mac; @@ -1668,7 +1667,7 @@ int mbedtls_ssl_derive_keys( mbedtls_ssl_context *ssl ) #if defined(MBEDTLS_SSL_PROTO_SSL3) void ssl_calc_verify_ssl( const mbedtls_ssl_context *ssl, - unsigned char hash[36], + unsigned char *hash, size_t *hlen ) { mbedtls_md5_context md5; @@ -1721,7 +1720,7 @@ void ssl_calc_verify_ssl( const mbedtls_ssl_context *ssl, #if defined(MBEDTLS_SSL_PROTO_TLS1) || defined(MBEDTLS_SSL_PROTO_TLS1_1) void ssl_calc_verify_tls( const mbedtls_ssl_context *ssl, - unsigned char hash[36], + unsigned char *hash, size_t *hlen ) { mbedtls_md5_context md5; @@ -1753,7 +1752,7 @@ void ssl_calc_verify_tls( const mbedtls_ssl_context *ssl, #if defined(MBEDTLS_SSL_PROTO_TLS1_2) #if defined(MBEDTLS_SHA256_C) void ssl_calc_verify_tls_sha256( const mbedtls_ssl_context *ssl, - unsigned char hash[32], + unsigned char *hash, size_t *hlen ) { #if defined(MBEDTLS_USE_PSA_CRYPTO) @@ -1802,7 +1801,7 @@ void ssl_calc_verify_tls_sha256( const mbedtls_ssl_context *ssl, #if defined(MBEDTLS_SHA512_C) void ssl_calc_verify_tls_sha384( const mbedtls_ssl_context *ssl, - unsigned char hash[48], + unsigned char *hash, size_t *hlen ) { #if defined(MBEDTLS_USE_PSA_CRYPTO) @@ -3198,6 +3197,9 @@ static void ssl_calc_finished_tls_sha256( #endif /* MBEDTLS_SHA256_C */ #if defined(MBEDTLS_SHA512_C) + +typedef int (*finish_sha384_t)(mbedtls_sha512_context*, unsigned char*); + static void ssl_calc_finished_tls_sha384( mbedtls_ssl_context *ssl, unsigned char *buf, int from ) { @@ -3256,8 +3258,14 @@ static void ssl_calc_finished_tls_sha384( MBEDTLS_SSL_DEBUG_BUF( 4, "finished sha512 state", (unsigned char *) sha512.state, sizeof( sha512.state ) ); #endif + /* + * For SHA-384, we can save 16 bytes by keeping padbuf 48 bytes long. + * However, to avoid stringop-overflow warning in gcc, we have to cast + * mbedtls_sha512_finish_ret(). + */ + finish_sha384_t finish = (finish_sha384_t)mbedtls_sha512_finish_ret; + finish( &sha512, padbuf ); - mbedtls_sha512_finish_ret( &sha512, padbuf ); mbedtls_sha512_free( &sha512 ); #endif @@ -3859,6 +3867,10 @@ int mbedtls_ssl_setup( mbedtls_ssl_context *ssl, mbedtls_ssl_reset_in_out_pointers( ssl ); +#if defined(MBEDTLS_SSL_DTLS_SRTP) + memset( &ssl->dtls_srtp_info, 0, sizeof(ssl->dtls_srtp_info) ); +#endif + if( ( ret = ssl_handshake_init( ssl ) ) != 0 ) goto error; @@ -4340,11 +4352,11 @@ static void ssl_conf_remove_psk( mbedtls_ssl_config *conf ) { /* Remove reference to existing PSK, if any. */ #if defined(MBEDTLS_USE_PSA_CRYPTO) - if( conf->psk_opaque != 0 ) + if( ! mbedtls_svc_key_id_is_null( conf->psk_opaque ) ) { /* The maintenance of the PSK key slot is the * user's responsibility. */ - conf->psk_opaque = 0; + conf->psk_opaque = MBEDTLS_SVC_KEY_ID_INIT; } /* This and the following branch should never * be taken simultaenously as we maintain the @@ -4428,9 +4440,9 @@ int mbedtls_ssl_conf_psk( mbedtls_ssl_config *conf, static void ssl_remove_psk( mbedtls_ssl_context *ssl ) { #if defined(MBEDTLS_USE_PSA_CRYPTO) - if( ssl->handshake->psk_opaque != 0 ) + if( ! mbedtls_svc_key_id_is_null( ssl->handshake->psk_opaque ) ) { - ssl->handshake->psk_opaque = 0; + ssl->handshake->psk_opaque = MBEDTLS_SVC_KEY_ID_INIT; } else #endif /* MBEDTLS_USE_PSA_CRYPTO */ @@ -4465,7 +4477,7 @@ int mbedtls_ssl_set_hs_psk( mbedtls_ssl_context *ssl, #if defined(MBEDTLS_USE_PSA_CRYPTO) int mbedtls_ssl_conf_psk_opaque( mbedtls_ssl_config *conf, - psa_key_handle_t psk_slot, + psa_key_id_t psk, const unsigned char *psk_identity, size_t psk_identity_len ) { @@ -4474,9 +4486,9 @@ int mbedtls_ssl_conf_psk_opaque( mbedtls_ssl_config *conf, ssl_conf_remove_psk( conf ); /* Check and set opaque PSK */ - if( psk_slot == 0 ) + if( mbedtls_svc_key_id_is_null( psk ) ) return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); - conf->psk_opaque = psk_slot; + conf->psk_opaque = psk; /* Check and set PSK Identity */ ret = ssl_conf_set_psk_identity( conf, psk_identity, @@ -4488,13 +4500,14 @@ int mbedtls_ssl_conf_psk_opaque( mbedtls_ssl_config *conf, } int mbedtls_ssl_set_hs_psk_opaque( mbedtls_ssl_context *ssl, - psa_key_handle_t psk_slot ) + psa_key_id_t psk ) { - if( psk_slot == 0 || ssl->handshake == NULL ) + if( ( mbedtls_svc_key_id_is_null( psk ) ) || + ( ssl->handshake == NULL ) ) return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); ssl_remove_psk( ssl ); - ssl->handshake->psk_opaque = psk_slot; + ssl->handshake->psk_opaque = psk; return( 0 ); } #endif /* MBEDTLS_USE_PSA_CRYPTO */ @@ -4685,6 +4698,86 @@ const char *mbedtls_ssl_get_alpn_protocol( const mbedtls_ssl_context *ssl ) } #endif /* MBEDTLS_SSL_ALPN */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) +void mbedtls_ssl_conf_srtp_mki_value_supported( mbedtls_ssl_config *conf, + int support_mki_value ) +{ + conf->dtls_srtp_mki_support = support_mki_value; +} + +int mbedtls_ssl_dtls_srtp_set_mki_value( mbedtls_ssl_context *ssl, + unsigned char *mki_value, + uint16_t mki_len ) +{ + if( mki_len > MBEDTLS_TLS_SRTP_MAX_MKI_LENGTH ) + { + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + } + + if( ssl->conf->dtls_srtp_mki_support == MBEDTLS_SSL_DTLS_SRTP_MKI_UNSUPPORTED ) + { + return( MBEDTLS_ERR_SSL_FEATURE_UNAVAILABLE ); + } + + memcpy( ssl->dtls_srtp_info.mki_value, mki_value, mki_len ); + ssl->dtls_srtp_info.mki_len = mki_len; + return( 0 ); +} + +int mbedtls_ssl_conf_dtls_srtp_protection_profiles( mbedtls_ssl_config *conf, + const mbedtls_ssl_srtp_profile *profiles ) +{ + const mbedtls_ssl_srtp_profile *p; + size_t list_size = 0; + + /* check the profiles list: all entry must be valid, + * its size cannot be more than the total number of supported profiles, currently 4 */ + for( p = profiles; *p != MBEDTLS_TLS_SRTP_UNSET && + list_size <= MBEDTLS_TLS_SRTP_MAX_PROFILE_LIST_LENGTH; + p++ ) + { + if( mbedtls_ssl_check_srtp_profile_value( *p ) != MBEDTLS_TLS_SRTP_UNSET ) + { + list_size++; + } + else + { + /* unsupported value, stop parsing and set the size to an error value */ + list_size = MBEDTLS_TLS_SRTP_MAX_PROFILE_LIST_LENGTH + 1; + } + } + + if( list_size > MBEDTLS_TLS_SRTP_MAX_PROFILE_LIST_LENGTH ) + { + conf->dtls_srtp_profile_list = NULL; + conf->dtls_srtp_profile_list_len = 0; + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + } + + conf->dtls_srtp_profile_list = profiles; + conf->dtls_srtp_profile_list_len = list_size; + + return( 0 ); +} + +void mbedtls_ssl_get_dtls_srtp_negotiation_result( const mbedtls_ssl_context *ssl, + mbedtls_dtls_srtp_info *dtls_srtp_info ) +{ + dtls_srtp_info->chosen_dtls_srtp_profile = ssl->dtls_srtp_info.chosen_dtls_srtp_profile; + /* do not copy the mki value if there is no chosen profile */ + if( dtls_srtp_info->chosen_dtls_srtp_profile == MBEDTLS_TLS_SRTP_UNSET ) + { + dtls_srtp_info->mki_len = 0; + } + else + { + dtls_srtp_info->mki_len = ssl->dtls_srtp_info.mki_len; + memcpy( dtls_srtp_info->mki_value, ssl->dtls_srtp_info.mki_value, + ssl->dtls_srtp_info.mki_len ); + } +} +#endif /* MBEDTLS_SSL_DTLS_SRTP */ + void mbedtls_ssl_conf_max_version( mbedtls_ssl_config *conf, int major, int minor ) { conf->max_major_ver = major; @@ -5682,11 +5775,24 @@ int mbedtls_ssl_handshake( mbedtls_ssl_context *ssl ) { int ret = 0; + /* Sanity checks */ + if( ssl == NULL || ssl->conf == NULL ) return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); +#if defined(MBEDTLS_SSL_PROTO_DTLS) + if( ssl->conf->transport == MBEDTLS_SSL_TRANSPORT_DATAGRAM && + ( ssl->f_set_timer == NULL || ssl->f_get_timer == NULL ) ) + { + MBEDTLS_SSL_DEBUG_MSG( 1, ( "You must use " + "mbedtls_ssl_set_timer_cb() for DTLS" ) ); + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + } +#endif /* MBEDTLS_SSL_PROTO_DTLS */ + MBEDTLS_SSL_DEBUG_MSG( 2, ( "=> handshake" ) ); + /* Main handshake loop */ while( ssl->state != MBEDTLS_SSL_HANDSHAKE_OVER ) { ret = mbedtls_ssl_handshake_step( ssl ); diff --git a/connectivity/mbedtls/source/ssl_tls13_keys.c b/connectivity/mbedtls/source/ssl_tls13_keys.c new file mode 100644 index 0000000000..c39e0322ba --- /dev/null +++ b/connectivity/mbedtls/source/ssl_tls13_keys.c @@ -0,0 +1,349 @@ +/* + * TLS 1.3 key schedule + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 ( the "License" ); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "common.h" + +#if defined(MBEDTLS_SSL_PROTO_TLS1_3_EXPERIMENTAL) + +#include "mbedtls/hkdf.h" +#include "mbedtls/ssl_internal.h" +#include "ssl_tls13_keys.h" + +#include +#include + +#define MBEDTLS_SSL_TLS1_3_LABEL( name, string ) \ + .name = string, + +struct mbedtls_ssl_tls1_3_labels_struct const mbedtls_ssl_tls1_3_labels = +{ + /* This seems to work in C, despite the string literal being one + * character too long due to the 0-termination. */ + MBEDTLS_SSL_TLS1_3_LABEL_LIST +}; + +#undef MBEDTLS_SSL_TLS1_3_LABEL + +/* + * This function creates a HkdfLabel structure used in the TLS 1.3 key schedule. + * + * The HkdfLabel is specified in RFC 8446 as follows: + * + * struct HkdfLabel { + * uint16 length; // Length of expanded key material + * opaque label<7..255>; // Always prefixed by "tls13 " + * opaque context<0..255>; // Usually a communication transcript hash + * }; + * + * Parameters: + * - desired_length: Length of expanded key material + * Even though the standard allows expansion to up to + * 2**16 Bytes, TLS 1.3 never uses expansion to more than + * 255 Bytes, so we require `desired_length` to be at most + * 255. This allows us to save a few Bytes of code by + * hardcoding the writing of the high bytes. + * - (label, llen): label + label length, without "tls13 " prefix + * The label length MUST be less than or equal to + * MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_LABEL_LEN + * It is the caller's responsibility to ensure this. + * All (label, label length) pairs used in TLS 1.3 + * can be obtained via MBEDTLS_SSL_TLS1_3_LBL_WITH_LEN(). + * - (ctx, clen): context + context length + * The context length MUST be less than or equal to + * MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_CONTEXT_LEN + * It is the caller's responsibility to ensure this. + * - dst: Target buffer for HkdfLabel structure, + * This MUST be a writable buffer of size + * at least SSL_TLS1_3_KEY_SCHEDULE_MAX_HKDF_LABEL_LEN Bytes. + * - dlen: Pointer at which to store the actual length of + * the HkdfLabel structure on success. + */ + +static const char tls1_3_label_prefix[6] = "tls13 "; + +#define SSL_TLS1_3_KEY_SCHEDULE_HKDF_LABEL_LEN( label_len, context_len ) \ + ( 2 /* expansion length */ \ + + 1 /* label length */ \ + + label_len \ + + 1 /* context length */ \ + + context_len ) + +#define SSL_TLS1_3_KEY_SCHEDULE_MAX_HKDF_LABEL_LEN \ + SSL_TLS1_3_KEY_SCHEDULE_HKDF_LABEL_LEN( \ + sizeof(tls1_3_label_prefix) + \ + MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_LABEL_LEN, \ + MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_CONTEXT_LEN ) + +static void ssl_tls1_3_hkdf_encode_label( + size_t desired_length, + const unsigned char *label, size_t llen, + const unsigned char *ctx, size_t clen, + unsigned char *dst, size_t *dlen ) +{ + size_t total_label_len = + sizeof(tls1_3_label_prefix) + llen; + size_t total_hkdf_lbl_len = + SSL_TLS1_3_KEY_SCHEDULE_HKDF_LABEL_LEN( total_label_len, clen ); + + unsigned char *p = dst; + + /* Add the size of the expanded key material. + * We're hardcoding the high byte to 0 here assuming that we never use + * TLS 1.3 HKDF key expansion to more than 255 Bytes. */ +#if MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_EXPANSION_LEN > 255 +#error "The implementation of ssl_tls1_3_hkdf_encode_label() is not fit for the \ + value of MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_EXPANSION_LEN" +#endif + + *p++ = 0; + *p++ = (unsigned char)( ( desired_length >> 0 ) & 0xFF ); + + /* Add label incl. prefix */ + *p++ = (unsigned char)( total_label_len & 0xFF ); + memcpy( p, tls1_3_label_prefix, sizeof(tls1_3_label_prefix) ); + p += sizeof(tls1_3_label_prefix); + memcpy( p, label, llen ); + p += llen; + + /* Add context value */ + *p++ = (unsigned char)( clen & 0xFF ); + if( clen != 0 ) + memcpy( p, ctx, clen ); + + /* Return total length to the caller. */ + *dlen = total_hkdf_lbl_len; +} + +int mbedtls_ssl_tls1_3_hkdf_expand_label( + mbedtls_md_type_t hash_alg, + const unsigned char *secret, size_t slen, + const unsigned char *label, size_t llen, + const unsigned char *ctx, size_t clen, + unsigned char *buf, size_t blen ) +{ + const mbedtls_md_info_t *md; + unsigned char hkdf_label[ SSL_TLS1_3_KEY_SCHEDULE_MAX_HKDF_LABEL_LEN ]; + size_t hkdf_label_len; + + if( llen > MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_LABEL_LEN ) + { + /* Should never happen since this is an internal + * function, and we know statically which labels + * are allowed. */ + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + if( clen > MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_CONTEXT_LEN ) + { + /* Should not happen, as above. */ + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + if( blen > MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_EXPANSION_LEN ) + { + /* Should not happen, as above. */ + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + md = mbedtls_md_info_from_type( hash_alg ); + if( md == NULL ) + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + + ssl_tls1_3_hkdf_encode_label( blen, + label, llen, + ctx, clen, + hkdf_label, + &hkdf_label_len ); + + return( mbedtls_hkdf_expand( md, + secret, slen, + hkdf_label, hkdf_label_len, + buf, blen ) ); +} + +/* + * The traffic keying material is generated from the following inputs: + * + * - One secret value per sender. + * - A purpose value indicating the specific value being generated + * - The desired lengths of key and IV. + * + * The expansion itself is based on HKDF: + * + * [sender]_write_key = HKDF-Expand-Label( Secret, "key", "", key_length ) + * [sender]_write_iv = HKDF-Expand-Label( Secret, "iv" , "", iv_length ) + * + * [sender] denotes the sending side and the Secret value is provided + * by the function caller. Note that we generate server and client side + * keys in a single function call. + */ +int mbedtls_ssl_tls1_3_make_traffic_keys( + mbedtls_md_type_t hash_alg, + const unsigned char *client_secret, + const unsigned char *server_secret, + size_t slen, size_t key_len, size_t iv_len, + mbedtls_ssl_key_set *keys ) +{ + int ret = 0; + + ret = mbedtls_ssl_tls1_3_hkdf_expand_label( hash_alg, + client_secret, slen, + MBEDTLS_SSL_TLS1_3_LBL_WITH_LEN( key ), + NULL, 0, + keys->client_write_key, key_len ); + if( ret != 0 ) + return( ret ); + + ret = mbedtls_ssl_tls1_3_hkdf_expand_label( hash_alg, + server_secret, slen, + MBEDTLS_SSL_TLS1_3_LBL_WITH_LEN( key ), + NULL, 0, + keys->server_write_key, key_len ); + if( ret != 0 ) + return( ret ); + + ret = mbedtls_ssl_tls1_3_hkdf_expand_label( hash_alg, + client_secret, slen, + MBEDTLS_SSL_TLS1_3_LBL_WITH_LEN( iv ), + NULL, 0, + keys->client_write_iv, iv_len ); + if( ret != 0 ) + return( ret ); + + ret = mbedtls_ssl_tls1_3_hkdf_expand_label( hash_alg, + server_secret, slen, + MBEDTLS_SSL_TLS1_3_LBL_WITH_LEN( iv ), + NULL, 0, + keys->server_write_iv, iv_len ); + if( ret != 0 ) + return( ret ); + + keys->key_len = key_len; + keys->iv_len = iv_len; + + return( 0 ); +} + +int mbedtls_ssl_tls1_3_derive_secret( + mbedtls_md_type_t hash_alg, + const unsigned char *secret, size_t slen, + const unsigned char *label, size_t llen, + const unsigned char *ctx, size_t clen, + int ctx_hashed, + unsigned char *dstbuf, size_t buflen ) +{ + int ret; + unsigned char hashed_context[ MBEDTLS_MD_MAX_SIZE ]; + + const mbedtls_md_info_t *md; + md = mbedtls_md_info_from_type( hash_alg ); + if( md == NULL ) + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + + if( ctx_hashed == MBEDTLS_SSL_TLS1_3_CONTEXT_UNHASHED ) + { + ret = mbedtls_md( md, ctx, clen, hashed_context ); + if( ret != 0 ) + return( ret ); + clen = mbedtls_md_get_size( md ); + } + else + { + if( clen > sizeof(hashed_context) ) + { + /* This should never happen since this function is internal + * and the code sets `ctx_hashed` correctly. + * Let's double-check nonetheless to not run at the risk + * of getting a stack overflow. */ + return( MBEDTLS_ERR_SSL_INTERNAL_ERROR ); + } + + memcpy( hashed_context, ctx, clen ); + } + + return( mbedtls_ssl_tls1_3_hkdf_expand_label( hash_alg, + secret, slen, + label, llen, + hashed_context, clen, + dstbuf, buflen ) ); +} + +int mbedtls_ssl_tls1_3_evolve_secret( + mbedtls_md_type_t hash_alg, + const unsigned char *secret_old, + const unsigned char *input, size_t input_len, + unsigned char *secret_new ) +{ + int ret = MBEDTLS_ERR_SSL_INTERNAL_ERROR; + size_t hlen, ilen; + unsigned char tmp_secret[ MBEDTLS_MD_MAX_SIZE ] = { 0 }; + unsigned char tmp_input [ MBEDTLS_MD_MAX_SIZE ] = { 0 }; + + const mbedtls_md_info_t *md; + md = mbedtls_md_info_from_type( hash_alg ); + if( md == NULL ) + return( MBEDTLS_ERR_SSL_BAD_INPUT_DATA ); + + hlen = mbedtls_md_get_size( md ); + + /* For non-initial runs, call Derive-Secret( ., "derived", "") + * on the old secret. */ + if( secret_old != NULL ) + { + ret = mbedtls_ssl_tls1_3_derive_secret( + hash_alg, + secret_old, hlen, + MBEDTLS_SSL_TLS1_3_LBL_WITH_LEN( derived ), + NULL, 0, /* context */ + MBEDTLS_SSL_TLS1_3_CONTEXT_UNHASHED, + tmp_secret, hlen ); + if( ret != 0 ) + goto cleanup; + } + + if( input != NULL ) + { + memcpy( tmp_input, input, input_len ); + ilen = input_len; + } + else + { + ilen = hlen; + } + + /* HKDF-Extract takes a salt and input key material. + * The salt is the old secret, and the input key material + * is the input secret (PSK / ECDHE). */ + ret = mbedtls_hkdf_extract( md, + tmp_secret, hlen, + tmp_input, ilen, + secret_new ); + if( ret != 0 ) + goto cleanup; + + ret = 0; + + cleanup: + + mbedtls_platform_zeroize( tmp_secret, sizeof(tmp_secret) ); + mbedtls_platform_zeroize( tmp_input, sizeof(tmp_input) ); + return( ret ); +} + +#endif /* MBEDTLS_SSL_PROTO_TLS1_3_EXPERIMENTAL */ diff --git a/connectivity/mbedtls/source/ssl_tls13_keys.h b/connectivity/mbedtls/source/ssl_tls13_keys.h new file mode 100644 index 0000000000..7089049ce2 --- /dev/null +++ b/connectivity/mbedtls/source/ssl_tls13_keys.h @@ -0,0 +1,274 @@ +/* + * TLS 1.3 key schedule + * + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 ( the "License" ); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#if !defined(MBEDTLS_SSL_TLS1_3_KEYS_H) +#define MBEDTLS_SSL_TLS1_3_KEYS_H + +/* This requires MBEDTLS_SSL_TLS1_3_LABEL( idx, name, string ) to be defined at + * the point of use. See e.g. the definition of mbedtls_ssl_tls1_3_labels_union + * below. */ +#define MBEDTLS_SSL_TLS1_3_LABEL_LIST \ + MBEDTLS_SSL_TLS1_3_LABEL( finished , "finished" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( resumption , "resumption" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( traffic_upd , "traffic upd" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( exporter , "exporter" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( key , "key" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( iv , "iv" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( c_hs_traffic, "c hs traffic" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( c_ap_traffic, "c ap traffic" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( c_e_traffic , "c e traffic" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( s_hs_traffic, "s hs traffic" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( s_ap_traffic, "s ap traffic" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( s_e_traffic , "s e traffic" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( e_exp_master, "e exp master" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( res_master , "res master" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( exp_master , "exp master" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( ext_binder , "ext binder" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( res_binder , "res binder" ) \ + MBEDTLS_SSL_TLS1_3_LABEL( derived , "derived" ) + +#define MBEDTLS_SSL_TLS1_3_LABEL( name, string ) \ + const unsigned char name [ sizeof(string) - 1 ]; + +union mbedtls_ssl_tls1_3_labels_union +{ + MBEDTLS_SSL_TLS1_3_LABEL_LIST +}; +struct mbedtls_ssl_tls1_3_labels_struct +{ + MBEDTLS_SSL_TLS1_3_LABEL_LIST +}; +#undef MBEDTLS_SSL_TLS1_3_LABEL + +extern const struct mbedtls_ssl_tls1_3_labels_struct mbedtls_ssl_tls1_3_labels; + +#define MBEDTLS_SSL_TLS1_3_LBL_WITH_LEN( LABEL ) \ + mbedtls_ssl_tls1_3_labels.LABEL, \ + sizeof(mbedtls_ssl_tls1_3_labels.LABEL) + +#define MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_LABEL_LEN \ + sizeof( union mbedtls_ssl_tls1_3_labels_union ) + +/* The maximum length of HKDF contexts used in the TLS 1.3 standard. + * Since contexts are always hashes of message transcripts, this can + * be approximated from above by the maximum hash size. */ +#define MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_CONTEXT_LEN \ + MBEDTLS_MD_MAX_SIZE + +/* Maximum desired length for expanded key material generated + * by HKDF-Expand-Label. + * + * Warning: If this ever needs to be increased, the implementation + * ssl_tls1_3_hkdf_encode_label() in ssl_tls13_keys.c needs to be + * adjusted since it currently assumes that HKDF key expansion + * is never used with more than 255 Bytes of output. */ +#define MBEDTLS_SSL_TLS1_3_KEY_SCHEDULE_MAX_EXPANSION_LEN 255 + +/** + * \brief The \c HKDF-Expand-Label function from + * the TLS 1.3 standard RFC 8446. + * + * + * HKDF-Expand-Label( Secret, Label, Context, Length ) = + * HKDF-Expand( Secret, HkdfLabel, Length ) + * + * + * \param hash_alg The identifier for the hash algorithm to use. + * \param secret The \c Secret argument to \c HKDF-Expand-Label. + * This must be a readable buffer of length \p slen Bytes. + * \param slen The length of \p secret in Bytes. + * \param label The \c Label argument to \c HKDF-Expand-Label. + * This must be a readable buffer of length \p llen Bytes. + * \param llen The length of \p label in Bytes. + * \param ctx The \c Context argument to \c HKDF-Expand-Label. + * This must be a readable buffer of length \p clen Bytes. + * \param clen The length of \p context in Bytes. + * \param buf The destination buffer to hold the expanded secret. + * This must be a writable buffer of length \p blen Bytes. + * \param blen The desired size of the expanded secret in Bytes. + * + * \returns \c 0 on success. + * \return A negative error code on failure. + */ + +int mbedtls_ssl_tls1_3_hkdf_expand_label( + mbedtls_md_type_t hash_alg, + const unsigned char *secret, size_t slen, + const unsigned char *label, size_t llen, + const unsigned char *ctx, size_t clen, + unsigned char *buf, size_t blen ); + +/** + * \brief This function is part of the TLS 1.3 key schedule. + * It extracts key and IV for the actual client/server traffic + * from the client/server traffic secrets. + * + * From RFC 8446: + * + * + * [sender]_write_key = HKDF-Expand-Label(Secret, "key", "", key_length) + * [sender]_write_iv = HKDF-Expand-Label(Secret, "iv", "", iv_length)* + * + * + * \param hash_alg The identifier for the hash algorithm to be used + * for the HKDF-based expansion of the secret. + * \param client_secret The client traffic secret. + * This must be a readable buffer of size \p slen Bytes + * \param server_secret The server traffic secret. + * This must be a readable buffer of size \p slen Bytes + * \param slen Length of the secrets \p client_secret and + * \p server_secret in Bytes. + * \param key_len The desired length of the key to be extracted in Bytes. + * \param iv_len The desired length of the IV to be extracted in Bytes. + * \param keys The address of the structure holding the generated + * keys and IVs. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ + +int mbedtls_ssl_tls1_3_make_traffic_keys( + mbedtls_md_type_t hash_alg, + const unsigned char *client_secret, + const unsigned char *server_secret, + size_t slen, size_t key_len, size_t iv_len, + mbedtls_ssl_key_set *keys ); + + +#define MBEDTLS_SSL_TLS1_3_CONTEXT_UNHASHED 0 +#define MBEDTLS_SSL_TLS1_3_CONTEXT_HASHED 1 + +/** + * \brief The \c Derive-Secret function from the TLS 1.3 standard RFC 8446. + * + * + * Derive-Secret( Secret, Label, Messages ) = + * HKDF-Expand-Label( Secret, Label, + * Hash( Messages ), + * Hash.Length ) ) + * + * + * \param hash_alg The identifier for the hash function used for the + * applications of HKDF. + * \param secret The \c Secret argument to the \c Derive-Secret function. + * This must be a readable buffer of length \p slen Bytes. + * \param slen The length of \p secret in Bytes. + * \param label The \c Label argument to the \c Derive-Secret function. + * This must be a readable buffer of length \p llen Bytes. + * \param llen The length of \p label in Bytes. + * \param ctx The hash of the \c Messages argument to the + * \c Derive-Secret function, or the \c Messages argument + * itself, depending on \p context_already_hashed. + * \param clen The length of \p hash. + * \param ctx_hashed This indicates whether the \p ctx contains the hash of + * the \c Messages argument in the application of the + * \c Derive-Secret function + * (value MBEDTLS_SSL_TLS1_3_CONTEXT_HASHED), or whether + * it is the content of \c Messages itself, in which case + * the function takes care of the hashing + * (value MBEDTLS_SSL_TLS1_3_CONTEXT_UNHASHED). + * \param dstbuf The target buffer to write the output of + * \c Derive-Secret to. This must be a writable buffer of + * size \p buflen Bytes. + * \param buflen The length of \p dstbuf in Bytes. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ +int mbedtls_ssl_tls1_3_derive_secret( + mbedtls_md_type_t hash_alg, + const unsigned char *secret, size_t slen, + const unsigned char *label, size_t llen, + const unsigned char *ctx, size_t clen, + int ctx_hashed, + unsigned char *dstbuf, size_t buflen ); + +/** + * \brief Compute the next secret in the TLS 1.3 key schedule + * + * The TLS 1.3 key schedule proceeds as follows to compute + * the three main secrets during the handshake: The early + * secret for early data, the handshake secret for all + * other encrypted handshake messages, and the master + * secret for all application traffic. + * + * + * 0 + * | + * v + * PSK -> HKDF-Extract = Early Secret + * | + * v + * Derive-Secret( ., "derived", "" ) + * | + * v + * (EC)DHE -> HKDF-Extract = Handshake Secret + * | + * v + * Derive-Secret( ., "derived", "" ) + * | + * v + * 0 -> HKDF-Extract = Master Secret + * + * + * Each of the three secrets in turn is the basis for further + * key derivations, such as the derivation of traffic keys and IVs; + * see e.g. mbedtls_ssl_tls1_3_make_traffic_keys(). + * + * This function implements one step in this evolution of secrets: + * + * + * old_secret + * | + * v + * Derive-Secret( ., "derived", "" ) + * | + * v + * input -> HKDF-Extract = new_secret + * + * + * \param hash_alg The identifier for the hash function used for the + * applications of HKDF. + * \param secret_old The address of the buffer holding the old secret + * on function entry. If not \c NULL, this must be a + * readable buffer whose size matches the output size + * of the hash function represented by \p hash_alg. + * If \c NULL, an all \c 0 array will be used instead. + * \param input The address of the buffer holding the additional + * input for the key derivation (e.g., the PSK or the + * ephemeral (EC)DH secret). If not \c NULL, this must be + * a readable buffer whose size \p input_len Bytes. + * If \c NULL, an all \c 0 array will be used instead. + * \param input_len The length of \p input in Bytes. + * \param secret_new The address of the buffer holding the new secret + * on function exit. This must be a writable buffer + * whose size matches the output size of the hash + * function represented by \p hash_alg. + * This may be the same as \p secret_old. + * + * \returns \c 0 on success. + * \returns A negative error code on failure. + */ + +int mbedtls_ssl_tls1_3_evolve_secret( + mbedtls_md_type_t hash_alg, + const unsigned char *secret_old, + const unsigned char *input, size_t input_len, + unsigned char *secret_new ); + +#endif /* MBEDTLS_SSL_TLS1_3_KEYS_H */ diff --git a/connectivity/mbedtls/source/threading.c b/connectivity/mbedtls/source/threading.c index 9268da1888..2bb932d2d0 100644 --- a/connectivity/mbedtls/source/threading.c +++ b/connectivity/mbedtls/source/threading.c @@ -42,7 +42,7 @@ #if !( ( defined(_POSIX_VERSION) && _POSIX_VERSION >= 200809L ) || \ ( defined(_POSIX_THREAD_SAFE_FUNCTIONS ) && \ - _POSIX_THREAD_SAFE_FUNCTIONS >= 20112L ) ) + _POSIX_THREAD_SAFE_FUNCTIONS >= 200112L ) ) /* * This is a convenience shorthand macro to avoid checking the long * preprocessor conditions above. Ideally, we could expose this macro in @@ -57,7 +57,7 @@ #endif /* !( ( defined(_POSIX_VERSION) && _POSIX_VERSION >= 200809L ) || \ ( defined(_POSIX_THREAD_SAFE_FUNCTIONS ) && \ - _POSIX_THREAD_SAFE_FUNCTIONS >= 20112L ) ) */ + _POSIX_THREAD_SAFE_FUNCTIONS >= 200112L ) ) */ #endif /* MBEDTLS_HAVE_TIME_DATE && !MBEDTLS_PLATFORM_GMTIME_R_ALT */ diff --git a/connectivity/mbedtls/source/version_features.c b/connectivity/mbedtls/source/version_features.c index d2840fa3cd..42ccaf9540 100644 --- a/connectivity/mbedtls/source/version_features.c +++ b/connectivity/mbedtls/source/version_features.c @@ -417,9 +417,9 @@ static const char * const features[] = { #if defined(MBEDTLS_ENTROPY_NV_SEED) "MBEDTLS_ENTROPY_NV_SEED", #endif /* MBEDTLS_ENTROPY_NV_SEED */ -#if defined(MBEDTLS_PSA_CRYPTO_KEY_FILE_ID_ENCODES_OWNER) - "MBEDTLS_PSA_CRYPTO_KEY_FILE_ID_ENCODES_OWNER", -#endif /* MBEDTLS_PSA_CRYPTO_KEY_FILE_ID_ENCODES_OWNER */ +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + "MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER", +#endif /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ #if defined(MBEDTLS_MEMORY_DEBUG) "MBEDTLS_MEMORY_DEBUG", #endif /* MBEDTLS_MEMORY_DEBUG */ @@ -435,6 +435,9 @@ static const char * const features[] = { #if defined(MBEDTLS_PKCS1_V21) "MBEDTLS_PKCS1_V21", #endif /* MBEDTLS_PKCS1_V21 */ +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) + "MBEDTLS_PSA_CRYPTO_DRIVERS", +#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ #if defined(MBEDTLS_PSA_CRYPTO_SPM) "MBEDTLS_PSA_CRYPTO_SPM", #endif /* MBEDTLS_PSA_CRYPTO_SPM */ @@ -531,6 +534,9 @@ static const char * const features[] = { #if defined(MBEDTLS_SSL_DTLS_HELLO_VERIFY) "MBEDTLS_SSL_DTLS_HELLO_VERIFY", #endif /* MBEDTLS_SSL_DTLS_HELLO_VERIFY */ +#if defined(MBEDTLS_SSL_DTLS_SRTP) + "MBEDTLS_SSL_DTLS_SRTP", +#endif /* MBEDTLS_SSL_DTLS_SRTP */ #if defined(MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE) "MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE", #endif /* MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE */ @@ -573,6 +579,9 @@ static const char * const features[] = { #if defined(MBEDTLS_USE_PSA_CRYPTO) "MBEDTLS_USE_PSA_CRYPTO", #endif /* MBEDTLS_USE_PSA_CRYPTO */ +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) + "MBEDTLS_PSA_CRYPTO_CONFIG", +#endif /* MBEDTLS_PSA_CRYPTO_CONFIG */ #if defined(MBEDTLS_VERSION_FEATURES) "MBEDTLS_VERSION_FEATURES", #endif /* MBEDTLS_VERSION_FEATURES */ diff --git a/connectivity/mbedtls/source/x509.c b/connectivity/mbedtls/source/x509.c index 1579c1abca..2a7be329b2 100644 --- a/connectivity/mbedtls/source/x509.c +++ b/connectivity/mbedtls/source/x509.c @@ -154,7 +154,7 @@ static int x509_get_hash_alg( const mbedtls_x509_buf *alg, mbedtls_md_type_t *md return( MBEDTLS_ERR_X509_INVALID_ALG + MBEDTLS_ERR_ASN1_UNEXPECTED_TAG ); - p = (unsigned char *) alg->p; + p = alg->p; end = p + alg->len; if( p >= end ) diff --git a/connectivity/mbedtls/source/x509_crt.c b/connectivity/mbedtls/source/x509_crt.c index 71e9cec372..a623c57a6c 100644 --- a/connectivity/mbedtls/source/x509_crt.c +++ b/connectivity/mbedtls/source/x509_crt.c @@ -1304,6 +1304,7 @@ static int x509_crt_parse_der_core( mbedtls_x509_crt *crt, if( crt->sig_oid.len != sig_oid2.len || memcmp( crt->sig_oid.p, sig_oid2.p, crt->sig_oid.len ) != 0 || + sig_params1.tag != sig_params2.tag || sig_params1.len != sig_params2.len || ( sig_params1.len != 0 && memcmp( sig_params1.p, sig_params2.p, sig_params1.len ) != 0 ) ) diff --git a/connectivity/mbedtls/tests/TESTS/mbedtls/selftest/main.cpp b/connectivity/mbedtls/tests/TESTS/mbedtls/selftest/main.cpp index 1f98c25755..bc39d8584a 100644 --- a/connectivity/mbedtls/tests/TESTS/mbedtls/selftest/main.cpp +++ b/connectivity/mbedtls/tests/TESTS/mbedtls/selftest/main.cpp @@ -31,10 +31,15 @@ using namespace utest::v1; #include MBEDTLS_CONFIG_FILE #endif +#if !defined(MBEDTLS_SELF_TEST) +#error [NOT_SUPPORTED] MBEDTLS_SELF_TEST undefined +#endif + #include "mbedtls/sha256.h" #include "mbedtls/sha512.h" #include "mbedtls/entropy.h" #include "mbedtls/entropy_poll.h" +#include "mbedtls/timing.h" #include @@ -65,6 +70,10 @@ MBEDTLS_SELF_TEST_TEST_CASE(mbedtls_sha512_self_test) MBEDTLS_SELF_TEST_TEST_CASE(mbedtls_entropy_self_test) #endif +#if defined(MBEDTLS_TIMING_C) +MBEDTLS_SELF_TEST_TEST_CASE(mbedtls_timing_self_test) +#endif + #else #warning "MBEDTLS_SELF_TEST not enabled" #endif /* MBEDTLS_SELF_TEST */ @@ -84,6 +93,10 @@ Case cases[] = { Case("mbedtls_entropy_self_test", mbedtls_entropy_self_test_test_case), #endif +#if defined(MBEDTLS_TIMING_C) + Case("mbedtls_timing_self_test", mbedtls_timing_self_test_test_case), +#endif + #endif /* MBEDTLS_SELF_TEST */ }; diff --git a/connectivity/mbedtls/tools/importer/Makefile b/connectivity/mbedtls/tools/importer/Makefile index bda34cb589..b1ca284762 100644 --- a/connectivity/mbedtls/tools/importer/Makefile +++ b/connectivity/mbedtls/tools/importer/Makefile @@ -27,7 +27,7 @@ # # Set the mbed TLS release to import (this can/should be edited before import) -MBED_TLS_RELEASE ?= mbedtls-2.24.0 +MBED_TLS_RELEASE ?= v2.25.0 MBED_TLS_REPO_URL ?= git@github.com:ARMmbed/mbedtls.git # Translate between mbed TLS namespace and mbed namespace diff --git a/connectivity/mbedtls/tools/importer/adjust-config.sh b/connectivity/mbedtls/tools/importer/adjust-config.sh index 4825661989..143bda1560 100755 --- a/connectivity/mbedtls/tools/importer/adjust-config.sh +++ b/connectivity/mbedtls/tools/importer/adjust-config.sh @@ -117,6 +117,9 @@ conf unset MBEDTLS_SSL_TRUNCATED_HMAC conf unset MBEDTLS_PLATFORM_TIME_TYPE_MACRO +# potentially save flash space by not enabling self-tests by default +conf unset MBEDTLS_SELF_TEST + # The default size of MBEDTLS_MPI_MAX_SIZE is 1024 bytes. # In some cases, this value is set to stack buffers. # Reduce the maximal MBEDTLS_MPI_MAX_SIZE to 512 bytes, diff --git a/connectivity/mbedtls/tools/importer/adjust-no-entropy-config.sh b/connectivity/mbedtls/tools/importer/adjust-no-entropy-config.sh index a6fb8c7403..10abcc264f 100755 --- a/connectivity/mbedtls/tools/importer/adjust-no-entropy-config.sh +++ b/connectivity/mbedtls/tools/importer/adjust-no-entropy-config.sh @@ -37,3 +37,6 @@ add_code() { conf set MBEDTLS_CMAC_C conf unset MBEDTLS_CIPHER_MODE_XTS + +# potentially save flash space by not enabling self-tests by default +conf unset MBEDTLS_SELF_TEST diff --git a/connectivity/nanostack/mbed-mesh-api/mbed-mesh-api/WisunInterface.h b/connectivity/nanostack/mbed-mesh-api/mbed-mesh-api/WisunInterface.h index 189c8327b2..570f1c492b 100644 --- a/connectivity/nanostack/mbed-mesh-api/mbed-mesh-api/WisunInterface.h +++ b/connectivity/nanostack/mbed-mesh-api/mbed-mesh-api/WisunInterface.h @@ -188,6 +188,48 @@ public: * */ mesh_error_t validate_network_regulatory_domain(uint8_t regulatory_domain, uint8_t operating_class, uint8_t operating_mode); + /** + * \brief Set Wi-SUN network regulatory domain, PHY mode ID and channel plan ID. + * + * Function stores new parameters to mbed-mesh-api and uses them when connect() is called next time. + * If device is already connected to the Wi-SUN network then device will restart network discovery after + * changing the regulatory_domain, phy_mode_id or channel_plan_id. + * + * \param regulatory_domain Values defined in Wi-SUN PHY-specification. Use 0 to leave parameter unchanged or 0xff to use default value. + * \param phy_mode_id Values defined in Wi-SUN PHY-specification. Use 0 to leave parameter unchanged or 0xff to use default value. + * \param channel_plan_id Values defined in Wi-SUN PHY-specification. Use 0 to leave parameter unchanged or 0xff to use default value. + * \return MESH_ERROR_NONE on success. + * \return MESH_ERROR_UNKNOWN in case of failure. + * */ + mesh_error_t set_network_domain_configuration(uint8_t regulatory_domain, uint8_t phy_mode_id, uint8_t channel_plan_id); + + /** + * \brief Get Wi-SUN network regulatory domain, PHY mode ID and channel plan ID. + * + * Function reads regulatory_domain, phy_mode_id and channel_plan_id from mbed-mesh-api. + * + * \param regulatory_domain Values defined in Wi-SUN PHY-specification. + * \param phy_mode_id Values defined in Wi-SUN PHY-specification. + * \param channel_plan_id Values defined in Wi-SUN PHY-specification. + * \return MESH_ERROR_NONE on success. + * \return MESH_ERROR_UNKNOWN in case of failure. + * */ + mesh_error_t get_network_domain_configuration(uint8_t *regulatory_domain, uint8_t *phy_mode_id, uint8_t *channel_plan_id); + + /** + * \brief Validate Wi-SUN network regulatory domain, PHY mode ID and channel plan ID. + * + * Function validates regulatory_domain, phy_mode_id and channel_plan_id. Function can be used to test that values that will + * be used on set function are valid. + * + * \param regulatory_domain Values defined in Wi-SUN PHY-specification. + * \param phy_mode_id Values defined in Wi-SUN PHY-specification. + * \param channel_plan_id Values defined in Wi-SUN PHY-specification. + * \return MESH_ERROR_NONE on success. + * \return MESH_ERROR_UNKNOWN in case of failure. + * */ + mesh_error_t validate_network_domain_configuration(uint8_t regulatory_domain, uint8_t phy_mode_id, uint8_t channel_plan_id); + /** * \brief Set Wi-SUN network size. * diff --git a/connectivity/nanostack/mbed-mesh-api/mbed_lib.json b/connectivity/nanostack/mbed-mesh-api/mbed_lib.json index 949c87acc4..f71df5fe18 100644 --- a/connectivity/nanostack/mbed-mesh-api/mbed_lib.json +++ b/connectivity/nanostack/mbed-mesh-api/mbed_lib.json @@ -136,6 +136,14 @@ "help": "Operating mode as specified in the Wi-SUN PHY Specification. Wi-SUN stack uses operating-mode suitable for EU-region if value 255 is used.", "value": "255" }, + "wisun-phy-mode-id": { + "help": "PHY mode ID as specified in the Wi-SUN PHY Specification. With default value 255, parameter is not used.", + "value": "255" + }, + "wisun-channel-plan-id": { + "help": "Channel plan ID as specified in the Wi-SUN PHY Specification. With default value 255, parameter is not used.", + "value": "255" + }, "wisun-uc-channel-function": { "help": "Unicast channel function as specified in the Wi-SUN FAN specification. Wi-SUN stack will select channel function if value 255 is used.", "value": 255 diff --git a/connectivity/nanostack/mbed-mesh-api/source/WisunInterface.cpp b/connectivity/nanostack/mbed-mesh-api/source/WisunInterface.cpp index 262aaac725..75f89eeca8 100644 --- a/connectivity/nanostack/mbed-mesh-api/source/WisunInterface.cpp +++ b/connectivity/nanostack/mbed-mesh-api/source/WisunInterface.cpp @@ -98,6 +98,16 @@ nsapi_error_t WisunInterface::configure() } #endif +#if (MBED_CONF_MBED_MESH_API_WISUN_PHY_MODE_ID != 255) || (MBED_CONF_MBED_MESH_API_WISUN_CHANNEL_PLAN_ID != 255) + status = set_network_domain_configuration(MBED_CONF_MBED_MESH_API_WISUN_REGULATORY_DOMAIN, + MBED_CONF_MBED_MESH_API_WISUN_PHY_MODE_ID, + MBED_CONF_MBED_MESH_API_WISUN_CHANNEL_PLAN_ID); + if (status != MESH_ERROR_NONE) { + tr_error("Failed to set domain configuration!"); + return NSAPI_ERROR_PARAMETER; + } +#endif + #if (MBED_CONF_MBED_MESH_API_WISUN_UC_CHANNEL_FUNCTION != 255) status = set_unicast_channel_function(static_cast(MBED_CONF_MBED_MESH_API_WISUN_UC_CHANNEL_FUNCTION), MBED_CONF_MBED_MESH_API_WISUN_UC_FIXED_CHANNEL, @@ -308,6 +318,36 @@ mesh_error_t WisunInterface::validate_network_regulatory_domain(uint8_t regulato return MESH_ERROR_NONE; } +mesh_error_t WisunInterface::set_network_domain_configuration(uint8_t regulatory_domain, uint8_t phy_mode_id, uint8_t channel_plan_id) +{ + int status = ws_management_domain_configuration_set(get_interface_id(), regulatory_domain, phy_mode_id, channel_plan_id); + if (status != 0) { + return MESH_ERROR_UNKNOWN; + } + + return MESH_ERROR_NONE; +} + +mesh_error_t WisunInterface::get_network_domain_configuration(uint8_t *regulatory_domain, uint8_t *phy_mode_id, uint8_t *channel_plan_id) +{ + int status = ws_management_domain_configuration_get(get_interface_id(), regulatory_domain, phy_mode_id, channel_plan_id); + if (status != 0) { + return MESH_ERROR_UNKNOWN; + } + + return MESH_ERROR_NONE; +} + +mesh_error_t WisunInterface::validate_network_domain_configuration(uint8_t regulatory_domain, uint8_t phy_mode_id, uint8_t channel_plan_id) +{ + int status = ws_management_domain_configuration_validate(get_interface_id(), regulatory_domain, phy_mode_id, channel_plan_id); + if (status != 0) { + return MESH_ERROR_UNKNOWN; + } + + return MESH_ERROR_NONE; +} + mesh_error_t WisunInterface::set_network_size(uint8_t network_size) { if (network_size == 0xff) { diff --git a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_ws.c b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_ws.c index 6c4e62e0d9..ed174150a5 100644 --- a/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_ws.c +++ b/connectivity/nanostack/sal-stack-nanostack/source/Service_Libs/fhss/fhss_ws.c @@ -499,16 +499,37 @@ static uint32_t fhss_ws_calculate_ufsi(fhss_structure_t *fhss_structure, uint32_ } } cur_slot--; - uint32_t remaining_time_ms = 0; - if (fhss_structure->ws->unicast_timer_running == true) { - remaining_time_ms = US_TO_MS(get_remaining_slots_us(fhss_structure, fhss_unicast_handler, MS_TO_US(dwell_time) - NS_TO_US((int64_t)(fhss_structure->ws->drift_per_millisecond_ns * dwell_time)))); - } + uint32_t time_to_tx = 0; uint32_t cur_time = fhss_structure->callbacks.read_timestamp(fhss_structure->fhss_api); - if (cur_time < tx_time) { + // High time to TX value (1000ms) is because actual TX time already passed. + if (US_TO_MS(tx_time - cur_time) < 1000) { time_to_tx = US_TO_MS(tx_time - cur_time); } - uint64_t ms_since_seq_start = (cur_slot * dwell_time) + (dwell_time - remaining_time_ms) + time_to_tx; + uint64_t ms_since_seq_start; + if (fhss_structure->ws->unicast_timer_running == true) { + // Allow timer interrupt to delay max 10 seconds, otherwise assume next_uc_timeout overflowed + if ((fhss_structure->ws->next_uc_timeout < cur_time) && ((cur_time - fhss_structure->ws->next_uc_timeout) < 10000000)) { + // The unicast timer has already expired, so count all previous slots + // plus 1 completed slot + // plus the time from timer expiration to now + // plus the time until Tx + ms_since_seq_start = ((cur_slot + 1) * dwell_time) + US_TO_MS(cur_time - fhss_structure->ws->next_uc_timeout) + time_to_tx; + } else { + // The unicast timer is still running, so count all previous slots + // plus the remaining time in the slot + // plus the time until Tx + uint32_t remaining_time_ms = US_TO_MS(fhss_structure->ws->next_uc_timeout - cur_time); + ms_since_seq_start = (cur_slot * dwell_time) + (dwell_time - remaining_time_ms) + time_to_tx; + } + } else { + // The unicast timer is not running. Act as if the slot has completed. + // count all previous slots + // plus 1 completed slot + // plus the time until Tx + ms_since_seq_start = ((cur_slot + 1) * dwell_time) + time_to_tx; + } + uint32_t seq_length = 0x10000; if (fhss_structure->ws->fhss_configuration.ws_uc_channel_function == WS_TR51CF) { ms_since_seq_start %= (dwell_time * fhss_structure->number_of_uc_channels); diff --git a/connectivity/netsocket/CMakeLists.txt b/connectivity/netsocket/CMakeLists.txt index f99ae1dbaa..62bea8cc63 100644 --- a/connectivity/netsocket/CMakeLists.txt +++ b/connectivity/netsocket/CMakeLists.txt @@ -1,6 +1,10 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) + add_subdirectory(tests/UNITTESTS) +endif() + # TODO CMake: Perhaps move this/these file(s) into connectivity/drivers/cellular target_sources(mbed-cellular INTERFACE diff --git a/connectivity/netsocket/include/netsocket/NetworkInterface.h b/connectivity/netsocket/include/netsocket/NetworkInterface.h index 25d9f546eb..9071a1e40b 100644 --- a/connectivity/netsocket/include/netsocket/NetworkInterface.h +++ b/connectivity/netsocket/include/netsocket/NetworkInterface.h @@ -377,6 +377,18 @@ public: */ virtual void attach(mbed::Callback status_cb); +#if MBED_CONF_NSAPI_ADD_EVENT_LISTENER_RETURN_CHANGE + /** Add event listener for interface. + * + * This API allows multiple callback to be registered for a single interface. + * of both leads to undefined behavior. + * + * @param status_cb The callback for status changes. + * @return NSAPI_ERROR_OK on success + * @return NSAPI_ERROR_NO_MEMORY if the function fails to create a new entry. + */ + nsapi_error_t add_event_listener(mbed::Callback status_cb); +#else /** Add event listener for interface. * * This API allows multiple callback to be registered for a single interface. @@ -386,9 +398,16 @@ public: * Application may only use attach() or add_event_listener() interface. Mixing usage * of both leads to undefined behavior. * + * @warning This version of the function does not use the `std::nothrow` feature. Subsequently, + * the function may fail to allocate memory and cause a system error. To use the new + * version with the changes, set "nsapi.add-event-listener-return-change": 1 in the + * target overrides section in your mbed_app.json file. + * * @param status_cb The callback for status changes. */ + MBED_DEPRECATED_SINCE("mbed-os-6.12", "This function return value will change to nsapi_error_t in the next major release. See documentation for details.") void add_event_listener(mbed::Callback status_cb); +#endif #if MBED_CONF_PLATFORM_CALLBACK_COMPARABLE /** Remove event listener from interface. @@ -512,6 +531,10 @@ public: * configuration). */ virtual void set_default_parameters(); + +private: + // Unified implementation for different versions of add_event_listener. + nsapi_error_t internal_add_event_listener(mbed::Callback status_cb); }; #endif diff --git a/connectivity/netsocket/include/netsocket/nsapi_types.h b/connectivity/netsocket/include/netsocket/nsapi_types.h index d8080e0754..eef8f34cc5 100644 --- a/connectivity/netsocket/include/netsocket/nsapi_types.h +++ b/connectivity/netsocket/include/netsocket/nsapi_types.h @@ -318,6 +318,7 @@ typedef enum nsapi_socket_option { NSAPI_LATENCY, /*!< Read estimated latency to destination */ NSAPI_STAGGER, /*!< Read estimated stagger value to destination */ NSAPI_IPTOS, /*!< Set IP type of service to set specific precedence */ + NSAPI_BROADCAST /*!< Set broadcast flag for UDP socket */ } nsapi_socket_option_t; typedef enum nsapi_tlssocket_level { diff --git a/connectivity/netsocket/mbed_lib.json b/connectivity/netsocket/mbed_lib.json index 5d1eccb4a5..d080275ba1 100644 --- a/connectivity/netsocket/mbed_lib.json +++ b/connectivity/netsocket/mbed_lib.json @@ -2,6 +2,10 @@ "name": "nsapi", "config": { "present": 1, + "add-event-listener-return-change": { + "help": "Updates the add_event_listener to return a nsapi_error_t value which can indicate allocation failure. See documents for more details.", + "value": 0 + }, "default-stack": { "help" : "Default stack to be used, valid values: LWIP, NANOSTACK.", "value" : "LWIP" diff --git a/connectivity/netsocket/source/NetworkInterface.cpp b/connectivity/netsocket/source/NetworkInterface.cpp index 3b2932ff8f..0f237f0e19 100644 --- a/connectivity/netsocket/source/NetworkInterface.cpp +++ b/connectivity/netsocket/source/NetworkInterface.cpp @@ -20,6 +20,7 @@ #include "netsocket/NetworkStack.h" #include "platform/Callback.h" #include "platform/mbed_error.h" +#include #include // Default network-interface state @@ -142,23 +143,49 @@ static void call_all_event_listeners(NetworkInterface *iface, nsapi_event_t even } } -void NetworkInterface::add_event_listener(mbed::Callback status_cb) +nsapi_error_t NetworkInterface::internal_add_event_listener(mbed::Callback status_cb) { iface_eventlist_t *event_list = get_interface_event_list_head(); #if MBED_CONF_PLATFORM_CALLBACK_COMPARABLE ns_list_foreach_safe(iface_eventlist_entry_t, entry, event_list) { if (entry->status_cb == status_cb && entry->iface == this) { - return; + return NSAPI_ERROR_OK; } } #endif - iface_eventlist_entry_t *entry = new iface_eventlist_entry_t; + + iface_eventlist_entry_t *entry = new (std::nothrow) iface_eventlist_entry_t; + if (!entry) { + return NSAPI_ERROR_NO_MEMORY; + } + entry->iface = this; entry->status_cb = status_cb; ns_list_add_to_end(event_list, entry); attach(mbed::callback(&call_all_event_listeners, this)); + return NSAPI_ERROR_OK; } +#if MBED_CONF_NSAPI_ADD_EVENT_LISTENER_RETURN_CHANGE +nsapi_error_t NetworkInterface::add_event_listener(mbed::Callback status_cb) +{ + return internal_add_event_listener(status_cb); +} +#else +void NetworkInterface::add_event_listener(mbed::Callback status_cb) +{ + auto error = internal_add_event_listener(status_cb); + switch (error) { + case NSAPI_ERROR_OK: + return; + case NSAPI_ERROR_NO_MEMORY: + MBED_ERROR(error, "Out of memory when adding an event listener"); + default: + MBED_UNREACHABLE; + } +} +#endif // MBED_CONF_NSAPI_ADD_EVENT_LISTENER_RETURN_CHANGE + #if MBED_CONF_PLATFORM_CALLBACK_COMPARABLE void NetworkInterface::remove_event_listener(mbed::Callback status_cb) { diff --git a/connectivity/netsocket/source/TCPSocket.cpp b/connectivity/netsocket/source/TCPSocket.cpp index 4b72ab09b3..a85c8eb26c 100644 --- a/connectivity/netsocket/source/TCPSocket.cpp +++ b/connectivity/netsocket/source/TCPSocket.cpp @@ -16,6 +16,7 @@ */ #include "netsocket/TCPSocket.h" +#include #include "Timer.h" #include "mbed_assert.h" @@ -266,7 +267,12 @@ TCPSocket *TCPSocket::accept(nsapi_error_t *error) ret = _stack->socket_accept(_socket, &socket, &address); if (0 == ret) { - connection = new TCPSocket(this, socket, address); + connection = new (std::nothrow) TCPSocket(this, socket, address); + if (!connection) { + ret = NSAPI_ERROR_NO_MEMORY; + break; + } + _socket_stats.stats_update_peer(connection, address); _socket_stats.stats_update_socket_state(connection, SOCK_CONNECTED); break; diff --git a/connectivity/netsocket/source/TLSSocketWrapper.cpp b/connectivity/netsocket/source/TLSSocketWrapper.cpp index 2ff807d2f6..d3f06c96bd 100644 --- a/connectivity/netsocket/source/TLSSocketWrapper.cpp +++ b/connectivity/netsocket/source/TLSSocketWrapper.cpp @@ -16,6 +16,7 @@ */ #include "netsocket/TLSSocketWrapper.h" +#include #include "platform/Callback.h" #include "drivers/Timer.h" #include "events/mbed_events.h" @@ -134,7 +135,10 @@ nsapi_error_t TLSSocketWrapper::set_client_cert_key(const void *client_cert, siz #else int ret; - mbedtls_x509_crt *crt = new mbedtls_x509_crt; + mbedtls_x509_crt *crt = new (std::nothrow) mbedtls_x509_crt; + if (!crt) { + return NSAPI_ERROR_NO_MEMORY; + } mbedtls_x509_crt_init(crt); if ((ret = mbedtls_x509_crt_parse(crt, static_cast(client_cert), client_cert_len)) != 0) { @@ -286,7 +290,11 @@ nsapi_error_t TLSSocketWrapper::continue_handshake() #if defined(MBEDTLS_X509_CRT_PARSE_C) && defined(FEA_TRACE_SUPPORT) && !defined(MBEDTLS_X509_REMOVE_INFO) /* Prints the server certificate and verify it. */ const size_t buf_size = 1024; - char *buf = new char[buf_size]; + char *buf = new (std::nothrow) char[buf_size]; + if (!buf) { + print_mbedtls_error("new (std::nothrow) char[buf_size] failed in continue_handshake", NSAPI_ERROR_NO_MEMORY); + return NSAPI_ERROR_NO_MEMORY; + } mbedtls_x509_crt_info(buf, buf_size, "\r ", mbedtls_ssl_get_peer_cert(&_ssl)); tr_debug("Server certificate:\r\n%s\r\n", buf); @@ -427,10 +435,9 @@ void TLSSocketWrapper::print_mbedtls_error(MBED_UNUSED const char *name, MBED_UN { // Avoid pulling in mbedtls_strerror when trace is not enabled #if defined FEA_TRACE_SUPPORT && defined MBEDTLS_ERROR_C - char *buf = new char[128]; + char buf[128]; mbedtls_strerror(err, buf, 128); tr_err("%s() failed: -0x%04x (%d): %s", name, -err, err, buf); - delete[] buf; #else tr_err("%s() failed: -0x%04x (%d)", name, -err, err); #endif @@ -569,7 +576,10 @@ mbedtls_ssl_config *TLSSocketWrapper::get_ssl_config() { if (!_ssl_conf) { int ret; - _ssl_conf = new mbedtls_ssl_config; + _ssl_conf = new (std::nothrow) mbedtls_ssl_config; + if (!_ssl_conf) { + return nullptr; + } mbedtls_ssl_config_init(_ssl_conf); _ssl_conf_allocated = true; diff --git a/connectivity/netsocket/source/nsapi_dns.cpp b/connectivity/netsocket/source/nsapi_dns.cpp index 4e250cd5af..2f6f8b533f 100644 --- a/connectivity/netsocket/source/nsapi_dns.cpp +++ b/connectivity/netsocket/source/nsapi_dns.cpp @@ -982,7 +982,12 @@ static void nsapi_dns_query_async_create(void *ptr) } if (!query->socket_cb_data) { - query->socket_cb_data = new SOCKET_CB_DATA; + query->socket_cb_data = new (std::nothrow) SOCKET_CB_DATA; + if (!query->socket_cb_data) { + delete socket; + nsapi_dns_query_async_resp(query, NSAPI_ERROR_NO_MEMORY, NULL); + return; + } } query->socket_cb_data->call_in_cb = query->call_in_cb; query->socket_cb_data->stack = query->stack; diff --git a/connectivity/netsocket/tests/UNITTESTS/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/CMakeLists.txt new file mode 100644 index 0000000000..e23c5d4290 --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(netsocket) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/CMakeLists.txt new file mode 100644 index 0000000000..fa4624a27b --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/CMakeLists.txt @@ -0,0 +1,18 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(CellularNonIPSocket) +add_subdirectory(DTLSSocket) +add_subdirectory(DTLSSocketWrapper) +add_subdirectory(EthernetInterface) +add_subdirectory(IfaceDnsSocket) +add_subdirectory(InternetSocket) +add_subdirectory(NetworkInterface) +add_subdirectory(NetworkStack) +add_subdirectory(PPPInterface) +add_subdirectory(SocketAddress) +add_subdirectory(TCPSocket) +add_subdirectory(TLSSocket) +add_subdirectory(TLSSocketWrapper) +add_subdirectory(UDPSocket) +add_subdirectory(WiFiAccessPoint) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/CellularNonIPSocket/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/CellularNonIPSocket/CMakeLists.txt new file mode 100644 index 0000000000..cc1022d152 --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/CellularNonIPSocket/CMakeLists.txt @@ -0,0 +1,33 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-cellular-nonip-socket-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_CELLULAR_PRESENT=1 + DEVICE_SERIAL=1 + DEVICE_INTERRUPTIN=1 + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 + MBED_CONF_CELLULAR_AT_HANDLER_BUFFER_SIZE=32 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/CellularNonIPSocket.cpp + test_CellularNonIPSocket.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/CellularNonIPSocket/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/CellularNonIPSocket/unittest.cmake deleted file mode 100644 index 18580aac9a..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/CellularNonIPSocket/unittest.cmake +++ /dev/null @@ -1,31 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Add test specific include paths -set(unittest-includes ${unittest-includes} -) - -set(unittest-sources - ../connectivity/netsocket/source/CellularNonIPSocket.cpp -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_CellularNonIPSocket.cpp - stubs/NetworkInterface_stub.cpp - stubs/NetworkInterfaceDefaults_stub.cpp - stubs/NetworkStack_stub.cpp - stubs/EventFlags_stub.cpp - stubs/Mutex_stub.cpp - stubs/CellularContext_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/mbed_atomic_stub.c -) - -set(unittest-test-flags - -DMBED_CONF_CELLULAR_PRESENT=1 - -DDEVICE_SERIAL=1 - -DDEVICE_INTERRUPTIN=1 - -DMBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 -) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocket/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocket/CMakeLists.txt new file mode 100644 index 0000000000..9f241884a2 --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocket/CMakeLists.txt @@ -0,0 +1,47 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-dtls-socket-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_NSAPI_DNS_ADDRESSES_LIMIT=10 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkStack.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/InternetSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/InternetDatagramSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/UDPSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/DTLSSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/DTLSSocketWrapper.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TLSSocketWrapper.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + test_DTLSSocket.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +set(MBEDTLS_USER_CONFIG_FILE_PATH "\"${mbed-os_SOURCE_DIR}/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocket/dtls_test_config.h\"") +set_source_files_properties(${mbed-os_SOURCE_DIR}/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocket/test_DTLSSocket.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) +set_source_files_properties(${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/DTLSSocket.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) +set_source_files_properties(${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/DTLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) +set_source_files_properties(${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocket/test_DTLSSocket.cpp b/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocket/test_DTLSSocket.cpp index 681366fe4d..854ec2c2b0 100644 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocket/test_DTLSSocket.cpp +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocket/test_DTLSSocket.cpp @@ -62,5 +62,6 @@ TEST_F(TestDTLSSocket, connect) stack.return_value = NSAPI_ERROR_OK; SocketAddress a("127.0.0.1", 1024); + stack.return_socketAddress = a; EXPECT_EQ(socket->connect(a), NSAPI_ERROR_OK); } diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocket/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocket/unittest.cmake deleted file mode 100644 index 4a3938be17..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocket/unittest.cmake +++ /dev/null @@ -1,43 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-sources - ../connectivity/netsocket/source/SocketAddress.cpp - ../connectivity/netsocket/source/NetworkStack.cpp - ../connectivity/netsocket/source/InternetSocket.cpp - ../connectivity/netsocket/source/InternetDatagramSocket.cpp - ../connectivity/netsocket/source/UDPSocket.cpp - ../connectivity/netsocket/source/DTLSSocket.cpp - ../connectivity/netsocket/source/DTLSSocketWrapper.cpp - ../connectivity/netsocket/source/TLSSocketWrapper.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_DTLSSocket.cpp - stubs/Mutex_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_critical_stub.c - stubs/equeue_stub.c - ../connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c - stubs/EventQueue_stub.cpp - stubs/mbed_shared_queues_stub.cpp - stubs/nsapi_dns_stub.cpp - stubs/EventFlags_stub.cpp - stubs/stoip4_stub.c - stubs/ip4tos_stub.c - stubs/Kernel_stub.cpp - stubs/SocketStats_Stub.cpp -) - -set(MBEDTLS_USER_CONFIG_FILE_PATH "\"${CMAKE_CURRENT_LIST_DIR}/dtls_test_config.h\"") -set_source_files_properties(${CMAKE_CURRENT_LIST_DIR}/test_DTLSSocket.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) -set_source_files_properties(../connectivity/netsocket/source/DTLSSocket.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) -set_source_files_properties(../connectivity/netsocket/source/DTLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocketWrapper/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocketWrapper/CMakeLists.txt new file mode 100644 index 0000000000..20a0e4cfc3 --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocketWrapper/CMakeLists.txt @@ -0,0 +1,46 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-dtls-socket-wrapper-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_NSAPI_DNS_ADDRESSES_LIMIT=10 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkStack.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/InternetSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/InternetDatagramSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/UDPSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/DTLSSocketWrapper.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TLSSocketWrapper.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + test_DTLSSocketWrapper.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + + +set(MBEDTLS_USER_CONFIG_FILE_PATH "\"${mbed-os_SOURCE_DIR}/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocketWrapper/dtls_test_config.h\"") +set_source_files_properties(${mbed-os_SOURCE_DIR}/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocketWrapper/test_DTLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) +set_source_files_properties(${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/DTLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) +set_source_files_properties(${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocketWrapper/test_DTLSSocketWrapper.cpp b/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocketWrapper/test_DTLSSocketWrapper.cpp index fcc72c64f9..d3e09383f3 100644 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocketWrapper/test_DTLSSocketWrapper.cpp +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocketWrapper/test_DTLSSocketWrapper.cpp @@ -19,7 +19,7 @@ #include "netsocket/UDPSocket.h" #include "netsocket/DTLSSocketWrapper.h" #include "NetworkStack_stub.h" -#include "connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.h" +#include "mbedtls_stub.h" #include //memset #include "mbed_error.h" diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocketWrapper/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocketWrapper/unittest.cmake deleted file mode 100644 index 817bd84874..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/DTLSSocketWrapper/unittest.cmake +++ /dev/null @@ -1,41 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-sources - ../connectivity/netsocket/source/SocketAddress.cpp - ../connectivity/netsocket/source/NetworkStack.cpp - ../connectivity/netsocket/source/InternetSocket.cpp - ../connectivity/netsocket/source/InternetDatagramSocket.cpp - ../connectivity/netsocket/source/UDPSocket.cpp - ../connectivity/netsocket/source/DTLSSocketWrapper.cpp - ../connectivity/netsocket/source/TLSSocketWrapper.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_DTLSSocketWrapper.cpp - stubs/Mutex_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_critical_stub.c - stubs/equeue_stub.c - ../connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c - stubs/EventQueue_stub.cpp - stubs/mbed_shared_queues_stub.cpp - stubs/nsapi_dns_stub.cpp - stubs/EventFlags_stub.cpp - stubs/stoip4_stub.c - stubs/ip4tos_stub.c - stubs/Kernel_stub.cpp - stubs/SocketStats_Stub.cpp -) - -set(MBEDTLS_USER_CONFIG_FILE_PATH "\"${CMAKE_CURRENT_LIST_DIR}/dtls_test_config.h\"") -set_source_files_properties(${CMAKE_CURRENT_LIST_DIR}/test_DTLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) -set_source_files_properties(../connectivity/netsocket/source/DTLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/EthernetInterface/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/EthernetInterface/CMakeLists.txt new file mode 100644 index 0000000000..2081cf2e94 --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/EthernetInterface/CMakeLists.txt @@ -0,0 +1,39 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-ethernet-interface-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_NSAPI_DNS_ADDRESSES_LIMIT=10 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/EthernetInterface.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/EMACInterface.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkInterface.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkStack.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libList/ns_list.c + test_EthernetInterface.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/EthernetInterface/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/EthernetInterface/unittest.cmake deleted file mode 100644 index 64ca41ea2d..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/EthernetInterface/unittest.cmake +++ /dev/null @@ -1,38 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Unit test suite name -set(TEST_SUITE_NAME "features_netsocket_EthernetInterface") - -# Source files -set(unittest-sources - ../connectivity/netsocket/source/SocketAddress.cpp - ../connectivity/netsocket/source/EthernetInterface.cpp - ../connectivity/netsocket/source/EMACInterface.cpp - ../connectivity/netsocket/source/NetworkInterface.cpp - ../connectivity/netsocket/source/NetworkStack.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c - ../connectivity/libraries/nanostack-libservice/source/libList/ns_list.c -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_EthernetInterface.cpp - stubs/Mutex_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/equeue_stub.c - stubs/EventQueue_stub.cpp - stubs/mbed_shared_queues_stub.cpp - stubs/nsapi_dns_stub.cpp - stubs/EventFlags_stub.cpp - stubs/NetworkStack_stub.cpp - stubs/NetworkInterfaceDefaults_stub.cpp - stubs/SocketStats_Stub.cpp - stubs/mbed_error.c -) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/IfaceDnsSocket/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/IfaceDnsSocket/CMakeLists.txt new file mode 100644 index 0000000000..68ee8fb941 --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/IfaceDnsSocket/CMakeLists.txt @@ -0,0 +1,53 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-iface-dns-socket-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_NSAPI_DNS_ADDRESSES_LIMIT=10 + DEVICE_EMAC + MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE=ETHERNET + MBED_CONF_NSAPI_DNS_RESPONSE_WAIT_TIME=10000 + MBED_CONF_NSAPI_DNS_RETRIES=1 + MBED_CONF_NSAPI_DNS_TOTAL_ATTEMPTS=10 + MBED_CONF_NSAPI_DNS_CACHE_SIZE=5 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkInterface.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkInterfaceDefaults.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkStack.cpp #nsapi_create_stack + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/InternetSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TCPSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/InternetDatagramSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/UDPSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketStats.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/EthernetInterface.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/EMACInterface.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/nsapi_dns.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libList/ns_list.c + moduletest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/IfaceDnsSocket/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/IfaceDnsSocket/unittest.cmake deleted file mode 100644 index d8107e5b3e..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/IfaceDnsSocket/unittest.cmake +++ /dev/null @@ -1,47 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-sources - ../connectivity/netsocket/source/SocketAddress.cpp - ../connectivity/netsocket/source/NetworkInterface.cpp - ../connectivity/netsocket/source/NetworkInterfaceDefaults.cpp - ../connectivity/netsocket/source/NetworkStack.cpp #nsapi_create_stack - ../connectivity/netsocket/source/InternetSocket.cpp - ../connectivity/netsocket/source/TCPSocket.cpp - ../connectivity/netsocket/source/InternetDatagramSocket.cpp - ../connectivity/netsocket/source/UDPSocket.cpp - ../connectivity/netsocket/source/SocketStats.cpp - ../connectivity/netsocket/source/EthernetInterface.cpp - ../connectivity/netsocket/source/EMACInterface.cpp - ../connectivity/netsocket/source/nsapi_dns.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c - ../connectivity/libraries/nanostack-libservice/source/libList/ns_list.c -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/moduletest.cpp - stubs/MeshInterface_stub.cpp - stubs/CellularInterface_stub.cpp - stubs/Mutex_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_critical_stub.c - stubs/mbed_rtos_rtx_stub.c - stubs/equeue_stub.c - stubs/EventQueue_stub.cpp - stubs/Kernel_stub.cpp - stubs/mbed_error.c - stubs/mbed_shared_queues_stub.cpp - stubs/rtx_mutex_stub.c - stubs/EventFlags_stub.cpp -) - -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DDEVICE_EMAC -DMBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE=ETHERNET -DMBED_CONF_NSAPI_DNS_RESPONSE_WAIT_TIME=10000 -DMBED_CONF_NSAPI_DNS_RETRIES=1 -DMBED_CONF_NSAPI_DNS_TOTAL_ATTEMPTS=10 -DMBED_CONF_NSAPI_DNS_CACHE_SIZE=5") -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DDEVICE_EMAC -DMBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE=ETHERNET -DMBED_CONF_NSAPI_DNS_RESPONSE_WAIT_TIME=10000 -DMBED_CONF_NSAPI_DNS_RETRIES=1 -DMBED_CONF_NSAPI_DNS_TOTAL_ATTEMPTS=10 -DMBED_CONF_NSAPI_DNS_CACHE_SIZE=5") \ No newline at end of file diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/InternetSocket/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/InternetSocket/CMakeLists.txt new file mode 100644 index 0000000000..981790d6ea --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/InternetSocket/CMakeLists.txt @@ -0,0 +1,36 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-internet-socket-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_NSAPI_DNS_ADDRESSES_LIMIT=10 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkStack.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/InternetSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + test_InternetSocket.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/InternetSocket/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/InternetSocket/unittest.cmake deleted file mode 100644 index ff4bba862d..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/InternetSocket/unittest.cmake +++ /dev/null @@ -1,34 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBED_CONF_NSAPI_DNS_ADDRESSES_LIMIT=10") - -set(unittest-sources - ../connectivity/netsocket/source/SocketAddress.cpp - ../connectivity/netsocket/source/NetworkStack.cpp - ../connectivity/netsocket/source/InternetSocket.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_InternetSocket.cpp - stubs/Mutex_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_critical_stub.c - stubs/equeue_stub.c - stubs/EventQueue_stub.cpp - stubs/mbed_error.c - stubs/mbed_shared_queues_stub.cpp - stubs/nsapi_dns_stub.cpp - stubs/EventFlags_stub.cpp - stubs/stoip4_stub.c - stubs/ip4tos_stub.c - stubs/SocketStats_Stub.cpp -) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/NetworkInterface/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/NetworkInterface/CMakeLists.txt new file mode 100644 index 0000000000..f92e9ed7fe --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/NetworkInterface/CMakeLists.txt @@ -0,0 +1,39 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-network-interface-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_PLATFORM_CALLBACK_COMPARABLE + MBED_CONF_NSAPI_DNS_ADDRESSES_LIMIT=10 + +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkStack.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkInterface.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libList/ns_list.c + test_NetworkInterface.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/NetworkInterface/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/NetworkInterface/unittest.cmake deleted file mode 100644 index c03690a4ca..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/NetworkInterface/unittest.cmake +++ /dev/null @@ -1,34 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBED_CONF_PLATFORM_CALLBACK_COMPARABLE") - -# Source files -set(unittest-sources - ../connectivity/netsocket/source/SocketAddress.cpp - ../connectivity/netsocket/source/NetworkStack.cpp - ../connectivity/netsocket/source/NetworkInterface.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c - ../connectivity/libraries/nanostack-libservice/source/libList/ns_list.c -) - -# Test files -set(unittest-test-sources - stubs/Mutex_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/equeue_stub.c - stubs/EventQueue_stub.cpp - stubs/mbed_shared_queues_stub.cpp - stubs/nsapi_dns_stub.cpp - stubs/EventFlags_stub.cpp - ${CMAKE_CURRENT_LIST_DIR}/test_NetworkInterface.cpp - stubs/NetworkInterfaceDefaults_stub.cpp - stubs/SocketStats_Stub.cpp - stubs/mbed_error.c -) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/NetworkStack/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/NetworkStack/CMakeLists.txt new file mode 100644 index 0000000000..f320819f41 --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/NetworkStack/CMakeLists.txt @@ -0,0 +1,35 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-network-stack-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_NSAPI_DNS_ADDRESSES_LIMIT=10 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkStack.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + test_NetworkStack.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/NetworkStack/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/NetworkStack/unittest.cmake deleted file mode 100644 index 239074a27f..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/NetworkStack/unittest.cmake +++ /dev/null @@ -1,33 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Unit test suite name -set(TEST_SUITE_NAME "features_netsocket_NetworkStack") - -# Source files -set(unittest-sources - ../connectivity/netsocket/source/SocketAddress.cpp - ../connectivity/netsocket/source/NetworkStack.cpp - ../connectivity/netsocket/source/NetworkInterface.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c -) - -# Test files -set(unittest-test-sources - stubs/Mutex_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/equeue_stub.c - stubs/EventQueue_stub.cpp - stubs/mbed_error.c - stubs/mbed_shared_queues_stub.cpp - stubs/nsapi_dns_stub.cpp - stubs/EventFlags_stub.cpp - ${CMAKE_CURRENT_LIST_DIR}/test_NetworkStack.cpp - stubs/SocketStats_Stub.cpp -) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/PPPInterface/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/PPPInterface/CMakeLists.txt new file mode 100644 index 0000000000..f78c6ccf6b --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/PPPInterface/CMakeLists.txt @@ -0,0 +1,39 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-ppp-interface-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_NSAPI_DNS_ADDRESSES_LIMIT=10 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/PPPInterface.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/EMACInterface.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkInterface.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkStack.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libList/ns_list.c + test_PPPInterface.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/PPPInterface/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/PPPInterface/unittest.cmake deleted file mode 100644 index 8fc42def39..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/PPPInterface/unittest.cmake +++ /dev/null @@ -1,39 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Unit test suite name -set(TEST_SUITE_NAME "features_netsocket_PPPInterface") - -# Source files -set(unittest-sources - ../connectivity/netsocket/source/SocketAddress.cpp - ../connectivity/netsocket/source/PPPInterface.cpp - ../connectivity/netsocket/source/EMACInterface.cpp - ../connectivity/netsocket/source/NetworkInterface.cpp - ../connectivity/netsocket/source/NetworkStack.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c - ../connectivity/libraries/nanostack-libservice/source/libList/ns_list.c -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_PPPInterface.cpp - stubs/Mutex_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/equeue_stub.c - stubs/EventQueue_stub.cpp - stubs/FileHandle_stub.cpp - stubs/mbed_shared_queues_stub.cpp - stubs/nsapi_dns_stub.cpp - stubs/EventFlags_stub.cpp - stubs/NetworkStack_stub.cpp - stubs/NetworkInterfaceDefaults_stub.cpp - stubs/SocketStats_Stub.cpp - stubs/mbed_error.c -) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/SocketAddress/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/SocketAddress/CMakeLists.txt new file mode 100644 index 0000000000..5ac15b6a54 --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/SocketAddress/CMakeLists.txt @@ -0,0 +1,29 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-socket-address-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + test_SocketAddress.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/SocketAddress/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/SocketAddress/unittest.cmake deleted file mode 100644 index 6cb641bc2d..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/SocketAddress/unittest.cmake +++ /dev/null @@ -1,22 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -# Unit test suite name -set(TEST_SUITE_NAME "features_netsocket_SocketAddress") - -# Source files -set(unittest-sources - ../connectivity/netsocket/source/SocketAddress.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c -) - -# Test files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_SocketAddress.cpp -) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/TCPSocket/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/TCPSocket/CMakeLists.txt new file mode 100644 index 0000000000..ca51a12f39 --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/TCPSocket/CMakeLists.txt @@ -0,0 +1,37 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-tcp-socket-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_NSAPI_DNS_ADDRESSES_LIMIT=10 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkStack.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/InternetSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TCPSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + test_TCPSocket.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/TCPSocket/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/TCPSocket/unittest.cmake deleted file mode 100644 index 1966b7c407..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/TCPSocket/unittest.cmake +++ /dev/null @@ -1,33 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-sources - ../connectivity/netsocket/source/SocketAddress.cpp - ../connectivity/netsocket/source/NetworkStack.cpp - ../connectivity/netsocket/source/InternetSocket.cpp - ../connectivity/netsocket/source/TCPSocket.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_TCPSocket.cpp - stubs/Mutex_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_critical_stub.c - stubs/equeue_stub.c - stubs/EventQueue_stub.cpp - stubs/mbed_error.c - stubs/mbed_shared_queues_stub.cpp - stubs/nsapi_dns_stub.cpp - stubs/EventFlags_stub.cpp - stubs/stoip4_stub.c - stubs/ip4tos_stub.c - stubs/SocketStats_Stub.cpp -) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocket/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocket/CMakeLists.txt new file mode 100644 index 0000000000..b9242f928c --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocket/CMakeLists.txt @@ -0,0 +1,44 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-tls-socket-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_NSAPI_DNS_ADDRESSES_LIMIT=10 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkStack.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/InternetSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TCPSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TLSSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TLSSocketWrapper.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + test_TLSSocket.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +set(MBEDTLS_USER_CONFIG_FILE_PATH "\"${mbed-os_SOURCE_DIR}/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocket/tls_test_config.h\"") +set_source_files_properties(${CMAKE_CURRENT_LIST_DIR}/test_TLSSocket.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) +set_source_files_properties(${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TLSSocket.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) +set_source_files_properties(${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocket/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocket/unittest.cmake deleted file mode 100644 index 112826e872..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocket/unittest.cmake +++ /dev/null @@ -1,41 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-sources - ../connectivity/netsocket/source/SocketAddress.cpp - ../connectivity/netsocket/source/NetworkStack.cpp - ../connectivity/netsocket/source/InternetSocket.cpp - ../connectivity/netsocket/source/TCPSocket.cpp - ../connectivity/netsocket/source/TLSSocket.cpp - ../connectivity/netsocket/source/TLSSocketWrapper.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_TLSSocket.cpp - stubs/Mutex_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_critical_stub.c - stubs/equeue_stub.c - ../connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c - stubs/EventQueue_stub.cpp - stubs/mbed_shared_queues_stub.cpp - stubs/nsapi_dns_stub.cpp - stubs/EventFlags_stub.cpp - stubs/stoip4_stub.c - stubs/ip4tos_stub.c - stubs/SocketStats_Stub.cpp -) - -set(MBEDTLS_USER_CONFIG_FILE_PATH "\"${CMAKE_CURRENT_LIST_DIR}/tls_test_config.h\"") -#set(MBEDTLS_USER_CONFIG_FILE_PATH "\"../connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/tls_test_config.h\"") -set_source_files_properties(${CMAKE_CURRENT_LIST_DIR}/test_TLSSocket.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) -set_source_files_properties(../connectivity/netsocket/source/TLSSocket.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) -set_source_files_properties(../connectivity/netsocket/source/TLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/CMakeLists.txt new file mode 100644 index 0000000000..459d5c689b --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/CMakeLists.txt @@ -0,0 +1,42 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-tls-socket-wrapper-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_NSAPI_DNS_ADDRESSES_LIMIT=10 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkStack.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/InternetSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TCPSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TLSSocketWrapper.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + test_TLSSocketWrapper.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +set(MBEDTLS_USER_CONFIG_FILE_PATH "\"${mbed-os_SOURCE_DIR}/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/tls_test_config.h\"") +set_source_files_properties(${mbed-os_SOURCE_DIR}/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) +set_source_files_properties(${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/TLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp b/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp index 056317d7aa..b0e473a401 100644 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/test_TLSSocketWrapper.cpp @@ -19,7 +19,7 @@ #include "netsocket/TCPSocket.h" #include "netsocket/TLSSocketWrapper.h" #include "NetworkStack_stub.h" -#include "connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.h" +#include "mbedtls_stub.h" #include //memset #include "mbed_error.h" diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/unittest.cmake deleted file mode 100644 index c7a111ae1b..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/TLSSocketWrapper/unittest.cmake +++ /dev/null @@ -1,36 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-sources - ../connectivity/netsocket/source/SocketAddress.cpp - ../connectivity/netsocket/source/NetworkStack.cpp - ../connectivity/netsocket/source/InternetSocket.cpp - ../connectivity/netsocket/source/TCPSocket.cpp - ../connectivity/netsocket/source/TLSSocketWrapper.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_TLSSocketWrapper.cpp - stubs/Mutex_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_critical_stub.c - stubs/equeue_stub.c - ../connectivity/nanostack/coap-service/test/coap-service/unittest/stub/mbedtls_stub.c - stubs/EventQueue_stub.cpp - stubs/mbed_shared_queues_stub.cpp - stubs/nsapi_dns_stub.cpp - stubs/EventFlags_stub.cpp - stubs/SocketStats_Stub.cpp -) - -set(MBEDTLS_USER_CONFIG_FILE_PATH "\"${CMAKE_CURRENT_LIST_DIR}/tls_test_config.h\"") -set_source_files_properties(${CMAKE_CURRENT_LIST_DIR}/test_TLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) -set_source_files_properties(../connectivity/netsocket/source/TLSSocketWrapper.cpp PROPERTIES COMPILE_DEFINITIONS MBEDTLS_USER_CONFIG_FILE=${MBEDTLS_USER_CONFIG_FILE_PATH}) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/UDPSocket/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/UDPSocket/CMakeLists.txt new file mode 100644 index 0000000000..e62438cd85 --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/UDPSocket/CMakeLists.txt @@ -0,0 +1,38 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-udp-socket-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_NSAPI_DNS_ADDRESSES_LIMIT=10 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/SocketAddress.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/NetworkStack.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/InternetSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/InternetDatagramSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/UDPSocket.cpp + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c + ${mbed-os_SOURCE_DIR}/connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c + test_UDPSocket.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/UDPSocket/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/UDPSocket/unittest.cmake deleted file mode 100644 index bf9b060330..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/UDPSocket/unittest.cmake +++ /dev/null @@ -1,34 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-sources - ../connectivity/netsocket/source/SocketAddress.cpp - ../connectivity/netsocket/source/NetworkStack.cpp - ../connectivity/netsocket/source/InternetSocket.cpp - ../connectivity/netsocket/source/InternetDatagramSocket.cpp - ../connectivity/netsocket/source/UDPSocket.cpp - ../connectivity/libraries/nanostack-libservice/source/libip4string/ip4tos.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/ip6tos.c - ../connectivity/libraries/nanostack-libservice/source/libip4string/stoip4.c - ../connectivity/libraries/nanostack-libservice/source/libip6string/stoip6.c - ../connectivity/libraries/nanostack-libservice/source/libBits/common_functions.c -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_UDPSocket.cpp - stubs/Mutex_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_critical_stub.c - stubs/equeue_stub.c - stubs/EventQueue_stub.cpp - stubs/mbed_error.c - stubs/mbed_shared_queues_stub.cpp - stubs/EventFlags_stub.cpp - stubs/nsapi_dns_stub.cpp - stubs/stoip4_stub.c - stubs/ip4tos_stub.c - stubs/SocketStats_Stub.cpp -) diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/WiFiAccessPoint/CMakeLists.txt b/connectivity/netsocket/tests/UNITTESTS/netsocket/WiFiAccessPoint/CMakeLists.txt new file mode 100644 index 0000000000..d51f755464 --- /dev/null +++ b/connectivity/netsocket/tests/UNITTESTS/netsocket/WiFiAccessPoint/CMakeLists.txt @@ -0,0 +1,24 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME netsocket-wifi-access-point-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/connectivity/netsocket/source/WiFiAccessPoint.cpp + test_WiFiAccessPoint.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs + mbed-stubs-headers + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "netsocket") diff --git a/connectivity/netsocket/tests/UNITTESTS/netsocket/WiFiAccessPoint/unittest.cmake b/connectivity/netsocket/tests/UNITTESTS/netsocket/WiFiAccessPoint/unittest.cmake deleted file mode 100644 index a4ffba1d4e..0000000000 --- a/connectivity/netsocket/tests/UNITTESTS/netsocket/WiFiAccessPoint/unittest.cmake +++ /dev/null @@ -1,12 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-sources - ../connectivity/netsocket/source/WiFiAccessPoint.cpp -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_WiFiAccessPoint.cpp -) diff --git a/connectivity/nfc/tests/TESTS/nfc/eeprom/main.cpp b/connectivity/nfc/tests/TESTS/nfc/eeprom/main.cpp index c8d40a012d..a084bd7e29 100644 --- a/connectivity/nfc/tests/TESTS/nfc/eeprom/main.cpp +++ b/connectivity/nfc/tests/TESTS/nfc/eeprom/main.cpp @@ -15,6 +15,10 @@ * limitations under the License. */ +#if !MBED_CONF_NFCEEPROM +#error [NOT_SUPPORTED] NFC EEPROM not supported for this target +#else + #include "mbed.h" #include "greentea-client/test_env.h" #include "unity.h" @@ -23,10 +27,6 @@ #include #include "NFCEEPROMDriver.h" -#if !MBED_CONF_NFCEEPROM -#error [NOT_SUPPORTED] NFC EEPROM not supported for this target -#else - using namespace utest::v1; using namespace mbed::nfc; diff --git a/drivers/CMakeLists.txt b/drivers/CMakeLists.txt index 83bb222309..9079d3d75a 100644 --- a/drivers/CMakeLists.txt +++ b/drivers/CMakeLists.txt @@ -1,6 +1,10 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) + add_subdirectory(tests/UNITTESTS) +endif() + target_include_directories(mbed-core INTERFACE . diff --git a/drivers/include/drivers/BufferedSerial.h b/drivers/include/drivers/BufferedSerial.h index dce9161b77..0b0803e1d3 100644 --- a/drivers/include/drivers/BufferedSerial.h +++ b/drivers/include/drivers/BufferedSerial.h @@ -302,9 +302,9 @@ private: ssize_t write_unbuffered(const char *buf_ptr, size_t length); /** Enable processing of byte reception IRQs and register a callback to - * process them. + * process them if the IRQs are not yet enabled and reception is enabled. */ - void enable_rx_irq(); + void update_rx_irq(); /** Disable processing of byte reception IRQs and de-register callback to * process them. @@ -312,9 +312,9 @@ private: void disable_rx_irq(); /** Enable processing of byte transmission IRQs and register a callback to - * process them. + * process them if the IRQs are not yet enabled and transmission is enabled. */ - void enable_tx_irq(); + void update_tx_irq(); /** Disable processing of byte transmission IRQs and de-register callback to * process them. @@ -335,8 +335,6 @@ private: bool _blocking = true; bool _tx_irq_enabled = false; bool _rx_irq_enabled = false; - bool _tx_enabled = true; - bool _rx_enabled = true; InterruptIn *_dcd_irq = nullptr; /** Device Hanged up diff --git a/drivers/include/drivers/interfaces/InterfaceCAN.h b/drivers/include/drivers/interfaces/InterfaceCAN.h index 54cf0d2c96..5fad158112 100644 --- a/drivers/include/drivers/interfaces/InterfaceCAN.h +++ b/drivers/include/drivers/interfaces/InterfaceCAN.h @@ -109,6 +109,35 @@ public: id = _id; memset(data, 0, 8); } + + /** + * "Deep" comparison operator (ie: compare value of each data member) + */ + bool operator ==(const CANMessage &b) const + { + if (id != b.id) { + return false; + } + if (len != b.len) { + return false; + } + if (format != b.format) { + return false; + } + if (type != b.type) { + return false; + } + if (memcmp(data, b.data, len) != 0) { + return false; + } + + return true; + } + + bool operator !=(const CANMessage &b) const + { + return !(*this == b); + } }; /** @}*/ diff --git a/drivers/source/BufferedSerial.cpp b/drivers/source/BufferedSerial.cpp index a2c8873b03..e88f5a6c3e 100644 --- a/drivers/source/BufferedSerial.cpp +++ b/drivers/source/BufferedSerial.cpp @@ -26,13 +26,13 @@ namespace mbed { BufferedSerial::BufferedSerial(PinName tx, PinName rx, int baud): SerialBase(tx, rx, baud) { - enable_rx_irq(); + update_rx_irq(); } BufferedSerial::BufferedSerial(const serial_pinmap_t &static_pinmap, int baud): SerialBase(static_pinmap, baud) { - enable_rx_irq(); + update_rx_irq(); } BufferedSerial::~BufferedSerial() @@ -184,15 +184,7 @@ ssize_t BufferedSerial::write(const void *buffer, size_t length) data_written++; } - core_util_critical_section_enter(); - if (_tx_enabled && !_tx_irq_enabled) { - // only write to hardware in one place - BufferedSerial::tx_irq(); - if (!_txbuf.empty()) { - enable_tx_irq(); - } - } - core_util_critical_section_exit(); + update_tx_irq(); } api_unlock(); @@ -228,15 +220,7 @@ ssize_t BufferedSerial::read(void *buffer, size_t length) data_read++; } - core_util_critical_section_enter(); - if (_rx_enabled && !_rx_irq_enabled) { - // only read from hardware in one place - BufferedSerial::rx_irq(); - if (!_rxbuf.full()) { - enable_rx_irq(); - } - } - core_util_critical_section_exit(); + update_rx_irq(); api_unlock(); @@ -329,27 +313,44 @@ void BufferedSerial::tx_irq(void) } } -/* These are all called from critical section - * Attatch IRQ routines to the serial device. +/* Attach Rx-IRQ routine to the serial device eventually. */ -void BufferedSerial::enable_rx_irq() +void BufferedSerial::update_rx_irq() { - SerialBase::attach(callback(this, &BufferedSerial::rx_irq), RxIrq); - _rx_irq_enabled = true; + core_util_critical_section_enter(); + if (_rx_enabled && !_rx_irq_enabled) { + BufferedSerial::rx_irq(); + if (!_rxbuf.full()) { + SerialBase::attach(callback(this, &BufferedSerial::rx_irq), RxIrq); + _rx_irq_enabled = true; + } + } + core_util_critical_section_exit(); } +/* This is called called from critical section or interrupt context */ void BufferedSerial::disable_rx_irq() { SerialBase::attach(NULL, RxIrq); _rx_irq_enabled = false; } -void BufferedSerial::enable_tx_irq() +/* Attach Tx-IRQ routine to the serial device eventually. + */ +void BufferedSerial::update_tx_irq() { - SerialBase::attach(callback(this, &BufferedSerial::tx_irq), TxIrq); - _tx_irq_enabled = true; + core_util_critical_section_enter(); + if (_tx_enabled && !_tx_irq_enabled) { + BufferedSerial::tx_irq(); + if (!_txbuf.empty()) { + SerialBase::attach(callback(this, &BufferedSerial::tx_irq), TxIrq); + _tx_irq_enabled = true; + } + } + core_util_critical_section_exit(); } +/* This is called called from critical section or interrupt context */ void BufferedSerial::disable_tx_irq() { SerialBase::attach(NULL, TxIrq); @@ -360,6 +361,7 @@ int BufferedSerial::enable_input(bool enabled) { api_lock(); SerialBase::enable_input(enabled); + update_rx_irq(); // Eventually enable rx-interrupt to handle incoming data api_unlock(); return 0; @@ -369,6 +371,7 @@ int BufferedSerial::enable_output(bool enabled) { api_lock(); SerialBase::enable_output(enabled); + update_tx_irq(); // Eventually enable tx-interrupt to flush buffered data api_unlock(); return 0; diff --git a/drivers/source/I2C.cpp b/drivers/source/I2C.cpp index 8ee0520d0e..4dd80b27c1 100644 --- a/drivers/source/I2C.cpp +++ b/drivers/source/I2C.cpp @@ -137,6 +137,7 @@ int I2C::read(int ack) void I2C::start(void) { lock(); + aquire(); i2c_start(&_i2c); unlock(); } diff --git a/drivers/tests/UNITTESTS/CMakeLists.txt b/drivers/tests/UNITTESTS/CMakeLists.txt new file mode 100644 index 0000000000..f417001488 --- /dev/null +++ b/drivers/tests/UNITTESTS/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +add_subdirectory(doubles) +add_subdirectory(PwmOut) +add_subdirectory(Watchdog) diff --git a/drivers/tests/UNITTESTS/PwmOut/CMakeLists.txt b/drivers/tests/UNITTESTS/PwmOut/CMakeLists.txt new file mode 100644 index 0000000000..eac893dc09 --- /dev/null +++ b/drivers/tests/UNITTESTS/PwmOut/CMakeLists.txt @@ -0,0 +1,32 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME pwmout-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_PWMOUT +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/PwmOut.cpp + test_pwmout.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-base + mbed-headers-platform + mbed-headers-hal + mbed-headers-drivers + mbed-stubs-hal + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/PwmOut/unittest.cmake b/drivers/tests/UNITTESTS/PwmOut/unittest.cmake deleted file mode 100644 index 20ed523875..0000000000 --- a/drivers/tests/UNITTESTS/PwmOut/unittest.cmake +++ /dev/null @@ -1,29 +0,0 @@ - -#################### -# UNIT TESTS -#################### -set(TEST_SUITE_NAME "PwmOut") - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - . - ../hal -) - -# Source files -set(unittest-sources - ../drivers/source/PwmOut.cpp -) - -# Test files -set(unittest-test-sources - ../drivers/tests/UNITTESTS/PwmOut/test_pwmout.cpp - stubs/mbed_critical_stub.c - stubs/mbed_assert_stub.cpp - stubs/pwmout_api_stub.c -) - -set(unittest-test-flags - -DDEVICE_PWMOUT -) - diff --git a/drivers/tests/UNITTESTS/Watchdog/CMakeLists.txt b/drivers/tests/UNITTESTS/Watchdog/CMakeLists.txt new file mode 100644 index 0000000000..1475a74d08 --- /dev/null +++ b/drivers/tests/UNITTESTS/Watchdog/CMakeLists.txt @@ -0,0 +1,33 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME watchdog-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_WATCHDOG + MBED_WDOG_ASSERT=1 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/drivers/source/Watchdog.cpp + test_watchdog.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-base + mbed-headers-hal + mbed-headers-drivers + mbed-headers-platform + mbed-stubs-platform + mbed-stubs-hal + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "drivers") diff --git a/drivers/tests/UNITTESTS/Watchdog/unittest.cmake b/drivers/tests/UNITTESTS/Watchdog/unittest.cmake deleted file mode 100644 index 92254cee56..0000000000 --- a/drivers/tests/UNITTESTS/Watchdog/unittest.cmake +++ /dev/null @@ -1,29 +0,0 @@ - -#################### -# UNIT TESTS -#################### -set(TEST_SUITE_NAME "Watchdog") - -# Add test specific include paths -set(unittest-includes ${unittest-includes} - . - ../hal -) - -# Source files -set(unittest-sources - ../drivers/source/Watchdog.cpp -) - -# Test files -set(unittest-test-sources - ../drivers/tests/UNITTESTS/Watchdog/test_watchdog.cpp - stubs/mbed_critical_stub.c - stubs/mbed_assert_stub.cpp - stubs/watchdog_api_stub.c -) - -set(unittest-test-flags - -DDEVICE_WATCHDOG - -DMBED_WDOG_ASSERT=1 -) diff --git a/UNITTESTS/stubs/BufferedSerial_stub.cpp b/drivers/tests/UNITTESTS/doubles/BufferedSerial_stub.cpp similarity index 99% rename from UNITTESTS/stubs/BufferedSerial_stub.cpp rename to drivers/tests/UNITTESTS/doubles/BufferedSerial_stub.cpp index e67c84bfda..54d0730652 100644 --- a/UNITTESTS/stubs/BufferedSerial_stub.cpp +++ b/drivers/tests/UNITTESTS/doubles/BufferedSerial_stub.cpp @@ -85,6 +85,7 @@ ssize_t BufferedSerial::write_unbuffered(const char *buf_ptr, size_t length) bool BufferedSerial::hup() const { + return false; } void BufferedSerial::wake() diff --git a/drivers/tests/UNITTESTS/doubles/CMakeLists.txt b/drivers/tests/UNITTESTS/doubles/CMakeLists.txt new file mode 100644 index 0000000000..a223876842 --- /dev/null +++ b/drivers/tests/UNITTESTS/doubles/CMakeLists.txt @@ -0,0 +1,34 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-headers-drivers INTERFACE) + +target_include_directories(mbed-headers-drivers + INTERFACE + ${mbed-os_SOURCE_DIR}/drivers + ${mbed-os_SOURCE_DIR}/drivers/include + ${mbed-os_SOURCE_DIR}/drivers/include/drivers +) + +add_library(mbed-stubs-drivers) + +target_sources(mbed-stubs-drivers + PRIVATE + BufferedSerial_stub.cpp + SerialBase_stub.cpp +) + +target_compile_definitions(mbed-stubs-drivers + PRIVATE + DEVICE_SERIAL=1 + DEVICE_INTERRUPTIN=1 + MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE=115200 +) + +target_link_libraries(mbed-stubs-drivers + PRIVATE + mbed-headers-base + mbed-headers-hal + mbed-headers-drivers + mbed-headers-platform +) diff --git a/UNITTESTS/stubs/SerialBase_stub.cpp b/drivers/tests/UNITTESTS/doubles/SerialBase_stub.cpp similarity index 100% rename from UNITTESTS/stubs/SerialBase_stub.cpp rename to drivers/tests/UNITTESTS/doubles/SerialBase_stub.cpp diff --git a/events/CMakeLists.txt b/events/CMakeLists.txt index 591b01259a..da4d693511 100644 --- a/events/CMakeLists.txt +++ b/events/CMakeLists.txt @@ -1,6 +1,10 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) + add_subdirectory(tests/UNITTESTS) +else() + add_library(mbed-events INTERFACE) target_include_directories(mbed-events @@ -24,3 +28,4 @@ target_compile_definitions(mbed-events INTERFACE MBED_CONF_EVENTS_PRESENT=1 ) +endif() diff --git a/events/tests/UNITTESTS/CMakeLists.txt b/events/tests/UNITTESTS/CMakeLists.txt new file mode 100644 index 0000000000..0c295bbc93 --- /dev/null +++ b/events/tests/UNITTESTS/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(equeue) diff --git a/events/tests/UNITTESTS/equeue/CMakeLists.txt b/events/tests/UNITTESTS/equeue/CMakeLists.txt new file mode 100644 index 0000000000..bafed4450e --- /dev/null +++ b/events/tests/UNITTESTS/equeue/CMakeLists.txt @@ -0,0 +1,36 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME equeue-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + EQUEUE_PLATFORM_POSIX +) + +target_compile_options(${TEST_NAME} + PRIVATE + "-pthread" +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/events/source/equeue.c + test_equeue.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers-base + mbed-headers-platform + mbed-headers-events + mbed-stubs-events + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "equeue") diff --git a/events/tests/UNITTESTS/equeue/unittest.cmake b/events/tests/UNITTESTS/equeue/unittest.cmake deleted file mode 100644 index fe0f05a871..0000000000 --- a/events/tests/UNITTESTS/equeue/unittest.cmake +++ /dev/null @@ -1,27 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -list(REMOVE_ITEM unittest-includes ${PROJECT_SOURCE_DIR}/../events/tests/UNITTESTS/target_h ${PROJECT_SOURCE_DIR}/../events/test/UNITTESTS/target_h/equeue) - -set(unittest-includes ${unittest-includes} - ../events/source - ../events/include/events - ../events/include/events/internal -) - -set(unittest-sources - ../events/source/equeue.c -) - -set(unittest-test-sources - ../events/tests/UNITTESTS/equeue/test_equeue.cpp - ../events/tests/UNITTESTS/stubs/EqueuePosix_stub.c -) - -set(unittest-test-flags - -pthread - -DEQUEUE_PLATFORM_POSIX -) - diff --git a/hal/include/hal/PinNameAliases.h b/hal/include/hal/PinNameAliases.h index 7f3bff2227..b35a2ea0d0 100644 --- a/hal/include/hal/PinNameAliases.h +++ b/hal/include/hal/PinNameAliases.h @@ -28,28 +28,93 @@ #ifdef TARGET_FF_ARDUINO_UNO +#ifndef A0 #define A0 ARDUINO_UNO_A0 +#endif + +#ifndef A1 #define A1 ARDUINO_UNO_A1 +#endif + +#ifndef A2 #define A2 ARDUINO_UNO_A2 +#endif + +#ifndef A3 #define A3 ARDUINO_UNO_A3 +#endif + +#ifndef A4 #define A4 ARDUINO_UNO_A4 +#endif + +#ifndef A5 #define A5 ARDUINO_UNO_A5 +#endif + +#ifndef D0 #define D0 ARDUINO_UNO_D0 +#endif + +#ifndef D1 #define D1 ARDUINO_UNO_D1 +#endif + +#ifndef D2 #define D2 ARDUINO_UNO_D2 +#endif + +#ifndef D3 #define D3 ARDUINO_UNO_D3 +#endif + +#ifndef D4 #define D4 ARDUINO_UNO_D4 +#endif + +#ifndef D5 #define D5 ARDUINO_UNO_D5 +#endif + +#ifndef D6 #define D6 ARDUINO_UNO_D6 +#endif + +#ifndef D7 #define D7 ARDUINO_UNO_D7 +#endif + +#ifndef D8 #define D8 ARDUINO_UNO_D8 +#endif + +#ifndef D9 #define D9 ARDUINO_UNO_D9 +#endif + +#ifndef D10 #define D10 ARDUINO_UNO_D10 +#endif + +#ifndef D11 #define D11 ARDUINO_UNO_D11 +#endif + +#ifndef D12 #define D12 ARDUINO_UNO_D12 +#endif + +#ifndef D13 #define D13 ARDUINO_UNO_D13 +#endif + +#ifndef D14 #define D14 ARDUINO_UNO_D14 +#endif + +#ifndef D15 #define D15 ARDUINO_UNO_D15 +#endif #endif // TARGET_FF_ARDUINO_UNO @@ -82,20 +147,46 @@ #endif // TARGET_FF_ARDUINO +#ifdef TARGET_FF_ARDUINO_UNO + // Arduino Uno I2C signals aliases #define ARDUINO_UNO_I2C_SDA ARDUINO_UNO_D14 #define ARDUINO_UNO_I2C_SCL ARDUINO_UNO_D15 +// Legacy I2C aliases +#ifndef I2C_SDA +#define I2C_SDA ARDUINO_UNO_I2C_SDA +#endif +#ifndef I2C_SCL +#define I2C_SCL ARDUINO_UNO_I2C_SCL +#endif + // Arduino Uno SPI signals aliases #define ARDUINO_UNO_SPI_CS ARDUINO_UNO_D10 #define ARDUINO_UNO_SPI_MOSI ARDUINO_UNO_D11 #define ARDUINO_UNO_SPI_MISO ARDUINO_UNO_D12 #define ARDUINO_UNO_SPI_SCK ARDUINO_UNO_D13 +// Legacy SPI aliases +#ifndef SPI_CS +#define SPI_CS ARDUINO_UNO_SPI_CS +#endif +#ifndef SPI_MOSI +#define SPI_MOSI ARDUINO_UNO_SPI_MOSI +#endif +#ifndef SPI_MISO +#define SPI_MISO ARDUINO_UNO_SPI_MISO +#endif +#ifndef SPI_SCK +#define SPI_SCK ARDUINO_UNO_SPI_SCK +#endif + // Arduino Uno UART signals aliases #define ARDUINO_UNO_UART_TX ARDUINO_UNO_D1 #define ARDUINO_UNO_UART_RX ARDUINO_UNO_D0 +#endif // TARGET_FF_ARDUINO_UNO + #endif // (TARGET_FF_ARDUINO) || (TARGET_FF_ARDUINO_UNO) #endif // MBED_PIN_NAME_ALIASES_H diff --git a/hal/tests/TESTS/pin_names/arduino_uno/main.cpp b/hal/tests/TESTS/pin_names/arduino_uno/main.cpp index 2a10b93799..c9be5e9759 100644 --- a/hal/tests/TESTS/pin_names/arduino_uno/main.cpp +++ b/hal/tests/TESTS/pin_names/arduino_uno/main.cpp @@ -124,9 +124,11 @@ void UART_test() { utest_printf("UART TX Pin 0x%x RX Pin 0x%x\n", TX_pin, RX_pin); + // 1. check if Arduino_uno pins are not already used by the console TEST_SKIP_UNLESS_MESSAGE(TX_pin != CONSOLE_TX, "ARDUINO_UNO_UART pin shared with CONSOLE_TX"); TEST_SKIP_UNLESS_MESSAGE(RX_pin != CONSOLE_RX, "ARDUINO_UNO_UART pin shared with CONSOLE_RX"); + // 2. check if Arduino_uno pins are part of pinmap table { const PinMap *maps = serial_tx_pinmap(); while (maps->pin != (PinName)NC) { // check each pin from PinMap table till NC pin @@ -151,8 +153,14 @@ void UART_test() TEST_ASSERT_NOT_EQUAL(NC, maps->pin); } + // 3. check if Arduino_uno pins are not using the same UART instance as console + int console_uart = pinmap_peripheral(CONSOLE_TX, serial_tx_pinmap()); + TEST_ASSERT_NOT_EQUAL(console_uart, pinmap_peripheral(TX_pin, serial_tx_pinmap())); + + // 4. check if UART pins can be initialized BufferedSerial TEST(TX_pin, RX_pin); - // Basic API call + + // 5. check a basic API call TEST.set_baud(115200); } diff --git a/hal/tests/TESTS/pin_names/generic/main.cpp b/hal/tests/TESTS/pin_names/generic/main.cpp index 839410691e..b498bf97b6 100644 --- a/hal/tests/TESTS/pin_names/generic/main.cpp +++ b/hal/tests/TESTS/pin_names/generic/main.cpp @@ -26,7 +26,6 @@ Requirements specified in docs/design-documents/hal/0004-pin-names-general-guide #ifndef LED1 #error [NOT_SUPPORTED] Target is not following mbed-os pin names standard // Test is set as Skipped -// #error [NOT_SUPPORTED] Target is not following mbed-os pin names standard // Test is set as Error #else using namespace utest::v1; @@ -82,6 +81,9 @@ Case cases[] = { #ifdef BUTTON2 Case("BUTTON2", BUTTON_test<2, BUTTON2>), #endif +#ifdef BUTTON3 + Case("BUTTON3", BUTTON_test<3, BUTTON3>), +#endif }; utest::v1::status_t greentea_test_setup(const size_t number_of_cases) diff --git a/platform/CMakeLists.txt b/platform/CMakeLists.txt index c68f815223..df83719fc6 100644 --- a/platform/CMakeLists.txt +++ b/platform/CMakeLists.txt @@ -1,6 +1,10 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) + add_subdirectory(tests/UNITTESTS) +endif() + # List of all optional platform libraries available. add_library(mbed-psa INTERFACE) diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/CMakeLists.txt b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/CMakeLists.txt index c0db16ec90..5fc1be9775 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/CMakeLists.txt +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/CMakeLists.txt @@ -23,6 +23,7 @@ target_sources(mbed-psa INTERFACE mbedtls/psa_crypto.c mbedtls/psa_crypto_se.c + mbedtls/psa_crypto_driver_wrappers.c mbedtls/psa_crypto_slot_management.c mbedtls/psa_crypto_storage.c mbedtls/psa_its_file.c diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/attestation/main.cpp b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/attestation/test/main.cpp similarity index 96% rename from platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/attestation/main.cpp rename to platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/attestation/test/main.cpp index 866123c784..aa947a23b5 100755 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/attestation/main.cpp +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/attestation/test/main.cpp @@ -22,8 +22,8 @@ #include "psa/crypto.h" -#if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) -#error [NOT_SUPPORTED] Mbed Crypto is OFF - skipping. +#if !defined(MBEDTLS_PSA_CRYPTO_C) +#error [NOT_SUPPORTED] Mbed TLS PSA Crypto is OFF - skipping. #else #include "greentea-client/test_env.h" @@ -160,5 +160,5 @@ int main() return !Harness::run(specification); } -#endif // ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) +#endif // !defined(MBEDTLS_PSA_CRYPTO_C) #endif // !defined(MBED_CONF_RTOS_PRESENT) diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/crypto_init/main.cpp b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/crypto_init/test/main.cpp similarity index 92% rename from platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/crypto_init/main.cpp rename to platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/crypto_init/test/main.cpp index 778b0fb6af..9e1525d831 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/crypto_init/main.cpp +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/crypto_init/test/main.cpp @@ -18,8 +18,8 @@ #include "psa/crypto.h" -#if ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) -#error [NOT_SUPPORTED] Mbed Crypto is OFF - skipping. +#if !defined(MBEDTLS_PSA_CRYPTO_C) +#error [NOT_SUPPORTED] Mbed TLS PSA Crypto is OFF - skipping. #else #include "greentea-client/test_env.h" @@ -87,4 +87,4 @@ int main() return !Harness::run(specification); } -#endif // ((!defined(TARGET_PSA)) || (!defined(MBEDTLS_PSA_CRYPTO_C))) +#endif // !defined(MBEDTLS_PSA_CRYPTO_C) diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/entropy_inject/main.cpp b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/entropy_inject/test/main.cpp similarity index 96% rename from platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/entropy_inject/main.cpp rename to platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/entropy_inject/test/main.cpp index 0098e8e244..7f5baa893e 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/entropy_inject/main.cpp +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/entropy_inject/test/main.cpp @@ -16,8 +16,8 @@ * limitations under the License. */ -#if ((!defined(TARGET_PSA) || (!defined(COMPONENT_PSA_SRV_IPC)) && !defined(MBEDTLS_ENTROPY_NV_SEED))) -#error [NOT_SUPPORTED] PSA entropy injection tests can run only on PSA-enabled targets. +#if !defined(MBEDTLS_ENTROPY_NV_SEED) +#error [NOT_SUPPORTED] PSA entropy injection tests can run only with MBEDTLS_ENTROPY_NV_SEED enabled. #else #include "greentea-client/test_env.h" @@ -184,4 +184,4 @@ int main() return !Harness::run(specification); } -#endif // ((!defined(TARGET_PSA) || (!defined(COMPONENT_PSA_SRV_IPC)) && !defined(MBEDTLS_ENTROPY_NV_SEED))) +#endif // !defined(MBEDTLS_ENTROPY_NV_SEED) diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/its_ps/main.cpp b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/its_ps/test/main.cpp similarity index 98% rename from platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/its_ps/main.cpp rename to platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/its_ps/test/main.cpp index 8e468b31d7..1282fb27fe 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/its_ps/main.cpp +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/TESTS/its_ps/test/main.cpp @@ -20,10 +20,6 @@ #error [NOT_SUPPORTED] ITS/PS test cases require RTOS to run. #else -#ifndef TARGET_PSA -#error [NOT_SUPPORTED] ITS/PS tests can run only on PSA-enabled targets. -#else - #include "greentea-client/test_env.h" #include "unity/unity.h" #include "utest/utest.h" @@ -243,5 +239,4 @@ int main() return !Harness::run(specification); } -#endif // TARGET_PSA #endif // !defined(MBED_CONF_RTOS_PRESENT) diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto.h index a3161666d7..b41a20bfc4 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto.h @@ -36,16 +36,6 @@ * @{ */ -/** \brief Key handle. - * - * This type represents open handles to keys. It must be an unsigned integral - * type. The choice of type is implementation-dependent. - * - * 0 is not a valid key handle. How other handle values are assigned is - * implementation-dependent. - */ -typedef _unsigned_integral_type_ psa_key_handle_t; - /**@}*/ #endif /* __DOXYGEN_ONLY__ */ @@ -146,11 +136,30 @@ static psa_key_attributes_t psa_key_attributes_init(void); * linkage). This function may be provided as a function-like macro, * but in this case it must evaluate each of its arguments exactly once. * - * \param[out] attributes The attribute structure to write to. - * \param id The persistent identifier for the key. + * \param[out] attributes The attribute structure to write to. + * \param key The persistent identifier for the key. */ -static void psa_set_key_id(psa_key_attributes_t *attributes, - psa_key_id_t id); +static void psa_set_key_id( psa_key_attributes_t *attributes, + mbedtls_svc_key_id_t key ); + +#ifdef MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER +/** Set the owner identifier of a key. + * + * When key identifiers encode key owner identifiers, psa_set_key_id() does + * not allow to define in key attributes the owner of volatile keys as + * psa_set_key_id() enforces the key to be persistent. + * + * This function allows to set in key attributes the owner identifier of a + * key. It is intended to be used for volatile keys. For persistent keys, + * it is recommended to use the PSA Cryptography API psa_set_key_id() to define + * the owner of a key. + * + * \param[out] attributes The attribute structure to write to. + * \param owner_id The key owner identifier. + */ +static void mbedtls_set_key_owner_id( psa_key_attributes_t *attributes, + mbedtls_key_owner_id_t owner_id ); +#endif /** Set the location of a persistent key. * @@ -192,7 +201,8 @@ static void psa_set_key_lifetime(psa_key_attributes_t *attributes, * This value is unspecified if the attribute structure declares * the key as volatile. */ -static psa_key_id_t psa_get_key_id(const psa_key_attributes_t *attributes); +static mbedtls_svc_key_id_t psa_get_key_id( + const psa_key_attributes_t *attributes); /** Retrieve the lifetime from key attributes. * @@ -347,7 +357,7 @@ static size_t psa_get_key_bits(const psa_key_attributes_t *attributes); * Once you have called this function on an attribute structure, * you must call psa_reset_key_attributes() to free these resources. * - * \param[in] handle Handle to the key to query. + * \param[in] key Identifier of the key to query. * \param[in,out] attributes On success, the attributes of the key. * On failure, equivalent to a * freshly-initialized structure. @@ -363,7 +373,7 @@ static size_t psa_get_key_bits(const psa_key_attributes_t *attributes); * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_get_key_attributes(psa_key_handle_t handle, +psa_status_t psa_get_key_attributes(mbedtls_svc_key_id_t key, psa_key_attributes_t *attributes); /** Reset a key attribute structure to a freshly initialized state. @@ -386,93 +396,28 @@ void psa_reset_key_attributes(psa_key_attributes_t *attributes); * @{ */ -/** Open a handle to an existing persistent key. +/** Remove non-essential copies of key material from memory. * - * Open a handle to a persistent key. A key is persistent if it was created - * with a lifetime other than #PSA_KEY_LIFETIME_VOLATILE. A persistent key - * always has a nonzero key identifier, set with psa_set_key_id() when - * creating the key. Implementations may provide additional pre-provisioned - * keys that can be opened with psa_open_key(). Such keys have a key identifier - * in the vendor range, as documented in the description of #psa_key_id_t. + * If the key identifier designates a volatile key, this functions does not do + * anything and returns successfully. * - * The application must eventually close the handle with psa_close_key() or - * psa_destroy_key() to release associated resources. If the application dies - * without calling one of these functions, the implementation should perform - * the equivalent of a call to psa_close_key(). + * If the key identifier designates a persistent key, then this function will + * free all resources associated with the key in volatile memory. The key + * data in persistent storage is not affected and the key can still be used. * - * Some implementations permit an application to open the same key multiple - * times. If this is successful, each call to psa_open_key() will return a - * different key handle. - * - * \note Applications that rely on opening a key multiple times will not be - * portable to implementations that only permit a single key handle to be - * opened. See also :ref:\`key-handles\`. - * - * \param id The persistent identifier of the key. - * \param[out] handle On success, a handle to the key. + * \param key Identifier of the key to purge. * * \retval #PSA_SUCCESS - * Success. The application can now use the value of `*handle` - * to access the key. - * \retval #PSA_ERROR_INSUFFICIENT_MEMORY - * The implementation does not have sufficient resources to open the - * key. This can be due to reaching an implementation limit on the - * number of open keys, the number of open key handles, or available - * memory. - * \retval #PSA_ERROR_DOES_NOT_EXIST - * There is no persistent key with key identifier \p id. + * The key material will have been removed from memory if it is not + * currently required. * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p id is not a valid persistent key identifier. - * \retval #PSA_ERROR_NOT_PERMITTED - * The specified key exists, but the application does not have the - * permission to access it. Note that this specification does not - * define any way to create such a key, but it may be possible - * through implementation-specific means. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE - * \retval #PSA_ERROR_CORRUPTION_DETECTED - * \retval #PSA_ERROR_STORAGE_FAILURE + * \p key is not a valid key identifier. * \retval #PSA_ERROR_BAD_STATE * The library has not been previously initialized by psa_crypto_init(). * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_open_key(psa_key_id_t id, - psa_key_handle_t *handle); - - -/** Close a key handle. - * - * If the handle designates a volatile key, this will destroy the key material - * and free all associated resources, just like psa_destroy_key(). - * - * If this is the last open handle to a persistent key, then closing the handle - * will free all resources associated with the key in volatile memory. The key - * data in persistent storage is not affected and can be opened again later - * with a call to psa_open_key(). - * - * Closing the key handle makes the handle invalid, and the key handle - * must not be used again by the application. - * - * \note If the key handle was used to set up an active - * :ref:\`multipart operation \`, then closing the - * key handle can cause the multipart operation to fail. Applications should - * maintain the key handle until after the multipart operation has finished. - * - * \param handle The key handle to close. - * If this is \c 0, do nothing and return \c PSA_SUCCESS. - * - * \retval #PSA_SUCCESS - * \p handle was a valid handle or \c 0. It is now closed. - * \retval #PSA_ERROR_INVALID_HANDLE - * \p handle is not a valid handle nor \c 0. - * \retval #PSA_ERROR_COMMUNICATION_FAILURE - * \retval #PSA_ERROR_CORRUPTION_DETECTED - * \retval #PSA_ERROR_BAD_STATE - * The library has not been previously initialized by psa_crypto_init(). - * It is implementation-dependent whether a failure to initialize - * results in this error code. - */ -psa_status_t psa_close_key(psa_key_handle_t handle); +psa_status_t psa_purge_key(mbedtls_svc_key_id_t key); /** Make a copy of a key. * @@ -511,7 +456,10 @@ psa_status_t psa_close_key(psa_key_handle_t handle); * The effect of this function on implementation-defined attributes is * implementation-defined. * - * \param source_handle The key to copy. It must be a valid key handle. + * \param source_key The key to copy. It must allow the usage + * #PSA_KEY_USAGE_COPY. If a private or secret key is + * being copied outside of a secure element it must + * also allow #PSA_KEY_USAGE_EXPORT. * \param[in] attributes The attributes for the new key. * They are used as follows: * - The key type and size may be 0. If either is @@ -525,12 +473,14 @@ psa_status_t psa_close_key(psa_key_handle_t handle); * the source key and \p attributes so that * both sets of restrictions apply, as * described in the documentation of this function. - * \param[out] target_handle On success, a handle to the newly created key. + * \param[out] target_key On success, an identifier for the newly created + * key. For persistent keys, this is the key + * identifier defined in \p attributes. * \c 0 on failure. * * \retval #PSA_SUCCESS * \retval #PSA_ERROR_INVALID_HANDLE - * \p source_handle is invalid. + * \p source_key is invalid. * \retval #PSA_ERROR_ALREADY_EXISTS * This is an attempt to create a persistent key, and there is * already a persistent key with the given identifier. @@ -558,9 +508,9 @@ psa_status_t psa_close_key(psa_key_handle_t handle); * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_copy_key(psa_key_handle_t source_handle, +psa_status_t psa_copy_key(mbedtls_svc_key_id_t source_key, const psa_key_attributes_t *attributes, - psa_key_handle_t *target_handle); + mbedtls_svc_key_id_t *target_key); /** @@ -571,28 +521,22 @@ psa_status_t psa_copy_key(psa_key_handle_t source_handle, * make a best effort to ensure that that the key material cannot be recovered. * * This function also erases any metadata such as policies and frees - * resources associated with the key. To free all resources associated with - * the key, all handles to the key must be closed or destroyed. - * - * Destroying the key makes the handle invalid, and the key handle - * must not be used again by the application. Using other open handles to the - * destroyed key in a cryptographic operation will result in an error. + * resources associated with the key. * * If a key is currently in use in a multipart operation, then destroying the * key will cause the multipart operation to fail. * - * \param handle Handle to the key to erase. - * If this is \c 0, do nothing and return \c PSA_SUCCESS. + * \param key Identifier of the key to erase. If this is \c 0, do nothing and + * return #PSA_SUCCESS. * * \retval #PSA_SUCCESS - * \p handle was a valid handle and the key material that it - * referred to has been erased. - * Alternatively, \p handle is \c 0. + * \p key was a valid identifier and the key material that it + * referred to has been erased. Alternatively, \p key is \c 0. * \retval #PSA_ERROR_NOT_PERMITTED * The key cannot be erased because it is * read-only, either due to a policy or due to physical restrictions. * \retval #PSA_ERROR_INVALID_HANDLE - * \p handle is not a valid handle nor \c 0. + * \p key is not a valid identifier nor \c 0. * \retval #PSA_ERROR_COMMUNICATION_FAILURE * There was an failure in communication with the cryptoprocessor. * The key material may still be present in the cryptoprocessor. @@ -610,7 +554,7 @@ psa_status_t psa_copy_key(psa_key_handle_t source_handle, * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_destroy_key(psa_key_handle_t handle); +psa_status_t psa_destroy_key(mbedtls_svc_key_id_t key); /**@}*/ @@ -645,7 +589,9 @@ psa_status_t psa_destroy_key(psa_key_handle_t handle); * \p data buffer. * If the key size in \p attributes is nonzero, * it must be equal to the size from \p data. - * \param[out] handle On success, a handle to the newly created key. + * \param[out] key On success, an identifier to the newly created key. + * For persistent keys, this is the key identifier + * defined in \p attributes. * \c 0 on failure. * \param[in] data Buffer containing the key data. The content of this * buffer is interpreted according to the type declared @@ -690,7 +636,7 @@ psa_status_t psa_destroy_key(psa_key_handle_t handle); psa_status_t psa_import_key(const psa_key_attributes_t *attributes, const uint8_t *data, size_t data_length, - psa_key_handle_t *handle); + mbedtls_svc_key_id_t *key); @@ -751,7 +697,9 @@ psa_status_t psa_import_key(const psa_key_attributes_t *attributes, * * The policy on the key must have the usage flag #PSA_KEY_USAGE_EXPORT set. * - * \param handle Handle to the key to export. + * \param key Identifier of the key to export. It must allow the + * usage #PSA_KEY_USAGE_EXPORT, unless it is a public + * key. * \param[out] data Buffer where the key data is to be written. * \param data_size Size of the \p data buffer in bytes. * \param[out] data_length On success, the number of bytes @@ -778,7 +726,7 @@ psa_status_t psa_import_key(const psa_key_attributes_t *attributes, * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_export_key(psa_key_handle_t handle, +psa_status_t psa_export_key(mbedtls_svc_key_id_t key, uint8_t *data, size_t data_size, size_t *data_length); @@ -821,7 +769,7 @@ psa_status_t psa_export_key(psa_key_handle_t handle, * Exporting a public key object or the public part of a key pair is * always permitted, regardless of the key's usage flags. * - * \param handle Handle to the key to export. + * \param key Identifier of the key to export. * \param[out] data Buffer where the key data is to be written. * \param data_size Size of the \p data buffer in bytes. * \param[out] data_length On success, the number of bytes @@ -848,7 +796,7 @@ psa_status_t psa_export_key(psa_key_handle_t handle, * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_export_public_key(psa_key_handle_t handle, +psa_status_t psa_export_public_key(mbedtls_svc_key_id_t key, uint8_t *data, size_t data_size, size_t *data_length); @@ -1225,7 +1173,8 @@ psa_status_t psa_hash_clone(const psa_hash_operation_t *source_operation, * about the MAC value which could allow an attacker to guess * a valid MAC and thereby bypass security controls. * - * \param handle Handle to the key to use for the operation. + * \param key Identifier of the key to use for the operation. It + * must allow the usage PSA_KEY_USAGE_SIGN_MESSAGE. * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value * such that #PSA_ALG_IS_MAC(\p alg) is true). * \param[in] input Buffer containing the input message. @@ -1240,7 +1189,7 @@ psa_status_t psa_hash_clone(const psa_hash_operation_t *source_operation, * \retval #PSA_ERROR_INVALID_HANDLE * \retval #PSA_ERROR_NOT_PERMITTED * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p handle is not compatible with \p alg. + * \p key is not compatible with \p alg. * \retval #PSA_ERROR_NOT_SUPPORTED * \p alg is not supported or is not a MAC algorithm. * \retval #PSA_ERROR_BUFFER_TOO_SMALL @@ -1256,7 +1205,7 @@ psa_status_t psa_hash_clone(const psa_hash_operation_t *source_operation, * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_mac_compute(psa_key_handle_t handle, +psa_status_t psa_mac_compute(mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *input, size_t input_length, @@ -1266,7 +1215,8 @@ psa_status_t psa_mac_compute(psa_key_handle_t handle, /** Calculate the MAC of a message and compare it with a reference value. * - * \param handle Handle to the key to use for the operation. + * \param key Identifier of the key to use for the operation. It + * must allow the usage PSA_KEY_USAGE_VERIFY_MESSAGE. * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value * such that #PSA_ALG_IS_MAC(\p alg) is true). * \param[in] input Buffer containing the input message. @@ -1282,7 +1232,7 @@ psa_status_t psa_mac_compute(psa_key_handle_t handle, * \retval #PSA_ERROR_INVALID_HANDLE * \retval #PSA_ERROR_NOT_PERMITTED * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p handle is not compatible with \p alg. + * \p key is not compatible with \p alg. * \retval #PSA_ERROR_NOT_SUPPORTED * \p alg is not supported or is not a MAC algorithm. * \retval #PSA_ERROR_INSUFFICIENT_MEMORY @@ -1296,7 +1246,7 @@ psa_status_t psa_mac_compute(psa_key_handle_t handle, * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_mac_verify(psa_key_handle_t handle, +psa_status_t psa_mac_verify(mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *input, size_t input_length, @@ -1381,9 +1331,9 @@ static psa_mac_operation_t psa_mac_operation_init(void); * \param[in,out] operation The operation object to set up. It must have * been initialized as per the documentation for * #psa_mac_operation_t and not yet in use. - * \param handle Handle to the key to use for the operation. - * It must remain valid until the operation - * terminates. + * \param key Identifier of the key to use for the operation. It + * must remain valid until the operation terminates. + * It must allow the usage PSA_KEY_USAGE_SIGN_MESSAGE. * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value * such that #PSA_ALG_IS_MAC(\p alg) is true). * @@ -1392,7 +1342,7 @@ static psa_mac_operation_t psa_mac_operation_init(void); * \retval #PSA_ERROR_INVALID_HANDLE * \retval #PSA_ERROR_NOT_PERMITTED * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p handle is not compatible with \p alg. + * \p key is not compatible with \p alg. * \retval #PSA_ERROR_NOT_SUPPORTED * \p alg is not supported or is not a MAC algorithm. * \retval #PSA_ERROR_INSUFFICIENT_MEMORY @@ -1409,7 +1359,7 @@ static psa_mac_operation_t psa_mac_operation_init(void); * results in this error code. */ psa_status_t psa_mac_sign_setup(psa_mac_operation_t *operation, - psa_key_handle_t handle, + mbedtls_svc_key_id_t key, psa_algorithm_t alg); /** Set up a multipart MAC verification operation. @@ -1443,9 +1393,10 @@ psa_status_t psa_mac_sign_setup(psa_mac_operation_t *operation, * \param[in,out] operation The operation object to set up. It must have * been initialized as per the documentation for * #psa_mac_operation_t and not yet in use. - * \param handle Handle to the key to use for the operation. - * It must remain valid until the operation - * terminates. + * \param key Identifier of the key to use for the operation. It + * must remain valid until the operation terminates. + * It must allow the usage + * PSA_KEY_USAGE_VERIFY_MESSAGE. * \param alg The MAC algorithm to compute (\c PSA_ALG_XXX value * such that #PSA_ALG_IS_MAC(\p alg) is true). * @@ -1471,7 +1422,7 @@ psa_status_t psa_mac_sign_setup(psa_mac_operation_t *operation, * results in this error code. */ psa_status_t psa_mac_verify_setup(psa_mac_operation_t *operation, - psa_key_handle_t handle, + mbedtls_svc_key_id_t key, psa_algorithm_t alg); /** Add a message fragment to a multipart MAC operation. @@ -1638,9 +1589,8 @@ psa_status_t psa_mac_abort(psa_mac_operation_t *operation); * vector). Use the multipart operation interface with a * #psa_cipher_operation_t object to provide other forms of IV. * - * \param handle Handle to the key to use for the operation. - * It must remain valid until the operation - * terminates. + * \param key Identifier of the key to use for the operation. + * It must allow the usage #PSA_KEY_USAGE_ENCRYPT. * \param alg The cipher algorithm to compute * (\c PSA_ALG_XXX value such that * #PSA_ALG_IS_CIPHER(\p alg) is true). @@ -1658,7 +1608,7 @@ psa_status_t psa_mac_abort(psa_mac_operation_t *operation); * \retval #PSA_ERROR_INVALID_HANDLE * \retval #PSA_ERROR_NOT_PERMITTED * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p handle is not compatible with \p alg. + * \p key is not compatible with \p alg. * \retval #PSA_ERROR_NOT_SUPPORTED * \p alg is not supported or is not a cipher algorithm. * \retval #PSA_ERROR_BUFFER_TOO_SMALL @@ -1672,7 +1622,7 @@ psa_status_t psa_mac_abort(psa_mac_operation_t *operation); * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_cipher_encrypt(psa_key_handle_t handle, +psa_status_t psa_cipher_encrypt(mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *input, size_t input_length, @@ -1684,9 +1634,10 @@ psa_status_t psa_cipher_encrypt(psa_key_handle_t handle, * * This function decrypts a message encrypted with a symmetric cipher. * - * \param handle Handle to the key to use for the operation. + * \param key Identifier of the key to use for the operation. * It must remain valid until the operation - * terminates. + * terminates. It must allow the usage + * #PSA_KEY_USAGE_DECRYPT. * \param alg The cipher algorithm to compute * (\c PSA_ALG_XXX value such that * #PSA_ALG_IS_CIPHER(\p alg) is true). @@ -1704,7 +1655,7 @@ psa_status_t psa_cipher_encrypt(psa_key_handle_t handle, * \retval #PSA_ERROR_INVALID_HANDLE * \retval #PSA_ERROR_NOT_PERMITTED * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p handle is not compatible with \p alg. + * \p key is not compatible with \p alg. * \retval #PSA_ERROR_NOT_SUPPORTED * \p alg is not supported or is not a cipher algorithm. * \retval #PSA_ERROR_BUFFER_TOO_SMALL @@ -1718,7 +1669,7 @@ psa_status_t psa_cipher_encrypt(psa_key_handle_t handle, * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_cipher_decrypt(psa_key_handle_t handle, +psa_status_t psa_cipher_decrypt(mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *input, size_t input_length, @@ -1804,9 +1755,10 @@ static psa_cipher_operation_t psa_cipher_operation_init(void); * \param[in,out] operation The operation object to set up. It must have * been initialized as per the documentation for * #psa_cipher_operation_t and not yet in use. - * \param handle Handle to the key to use for the operation. + * \param key Identifier of the key to use for the operation. * It must remain valid until the operation - * terminates. + * terminates. It must allow the usage + * #PSA_KEY_USAGE_ENCRYPT. * \param alg The cipher algorithm to compute * (\c PSA_ALG_XXX value such that * #PSA_ALG_IS_CIPHER(\p alg) is true). @@ -1816,7 +1768,7 @@ static psa_cipher_operation_t psa_cipher_operation_init(void); * \retval #PSA_ERROR_INVALID_HANDLE * \retval #PSA_ERROR_NOT_PERMITTED * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p handle is not compatible with \p alg. + * \p key is not compatible with \p alg. * \retval #PSA_ERROR_NOT_SUPPORTED * \p alg is not supported or is not a cipher algorithm. * \retval #PSA_ERROR_INSUFFICIENT_MEMORY @@ -1832,7 +1784,7 @@ static psa_cipher_operation_t psa_cipher_operation_init(void); * results in this error code. */ psa_status_t psa_cipher_encrypt_setup(psa_cipher_operation_t *operation, - psa_key_handle_t handle, + mbedtls_svc_key_id_t key, psa_algorithm_t alg); /** Set the key for a multipart symmetric decryption operation. @@ -1867,9 +1819,10 @@ psa_status_t psa_cipher_encrypt_setup(psa_cipher_operation_t *operation, * \param[in,out] operation The operation object to set up. It must have * been initialized as per the documentation for * #psa_cipher_operation_t and not yet in use. - * \param handle Handle to the key to use for the operation. + * \param key Identifier of the key to use for the operation. * It must remain valid until the operation - * terminates. + * terminates. It must allow the usage + * #PSA_KEY_USAGE_DECRYPT. * \param alg The cipher algorithm to compute * (\c PSA_ALG_XXX value such that * #PSA_ALG_IS_CIPHER(\p alg) is true). @@ -1879,7 +1832,7 @@ psa_status_t psa_cipher_encrypt_setup(psa_cipher_operation_t *operation, * \retval #PSA_ERROR_INVALID_HANDLE * \retval #PSA_ERROR_NOT_PERMITTED * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p handle is not compatible with \p alg. + * \p key is not compatible with \p alg. * \retval #PSA_ERROR_NOT_SUPPORTED * \p alg is not supported or is not a cipher algorithm. * \retval #PSA_ERROR_INSUFFICIENT_MEMORY @@ -1895,7 +1848,7 @@ psa_status_t psa_cipher_encrypt_setup(psa_cipher_operation_t *operation, * results in this error code. */ psa_status_t psa_cipher_decrypt_setup(psa_cipher_operation_t *operation, - psa_key_handle_t handle, + mbedtls_svc_key_id_t key, psa_algorithm_t alg); /** Generate an IV for a symmetric encryption operation. @@ -2109,7 +2062,9 @@ psa_status_t psa_cipher_abort(psa_cipher_operation_t *operation); /** Process an authenticated encryption operation. * - * \param handle Handle to the key to use for the operation. + * \param key Identifier of the key to use for the + * operation. It must allow the usage + * #PSA_KEY_USAGE_ENCRYPT. * \param alg The AEAD algorithm to compute * (\c PSA_ALG_XXX value such that * #PSA_ALG_IS_AEAD(\p alg) is true). @@ -2140,7 +2095,7 @@ psa_status_t psa_cipher_abort(psa_cipher_operation_t *operation); * \retval #PSA_ERROR_INVALID_HANDLE * \retval #PSA_ERROR_NOT_PERMITTED * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p handle is not compatible with \p alg. + * \p key is not compatible with \p alg. * \retval #PSA_ERROR_NOT_SUPPORTED * \p alg is not supported or is not an AEAD algorithm. * \retval #PSA_ERROR_INSUFFICIENT_MEMORY @@ -2155,7 +2110,7 @@ psa_status_t psa_cipher_abort(psa_cipher_operation_t *operation); * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_aead_encrypt(psa_key_handle_t handle, +psa_status_t psa_aead_encrypt(mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *nonce, size_t nonce_length, @@ -2169,7 +2124,9 @@ psa_status_t psa_aead_encrypt(psa_key_handle_t handle, /** Process an authenticated decryption operation. * - * \param handle Handle to the key to use for the operation. + * \param key Identifier of the key to use for the + * operation. It must allow the usage + * #PSA_KEY_USAGE_DECRYPT. * \param alg The AEAD algorithm to compute * (\c PSA_ALG_XXX value such that * #PSA_ALG_IS_AEAD(\p alg) is true). @@ -2200,7 +2157,7 @@ psa_status_t psa_aead_encrypt(psa_key_handle_t handle, * The ciphertext is not authentic. * \retval #PSA_ERROR_NOT_PERMITTED * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p handle is not compatible with \p alg. + * \p key is not compatible with \p alg. * \retval #PSA_ERROR_NOT_SUPPORTED * \p alg is not supported or is not an AEAD algorithm. * \retval #PSA_ERROR_INSUFFICIENT_MEMORY @@ -2215,7 +2172,7 @@ psa_status_t psa_aead_encrypt(psa_key_handle_t handle, * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_aead_decrypt(psa_key_handle_t handle, +psa_status_t psa_aead_decrypt(mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *nonce, size_t nonce_length, @@ -2311,9 +2268,10 @@ static psa_aead_operation_t psa_aead_operation_init(void); * \param[in,out] operation The operation object to set up. It must have * been initialized as per the documentation for * #psa_aead_operation_t and not yet in use. - * \param handle Handle to the key to use for the operation. + * \param key Identifier of the key to use for the operation. * It must remain valid until the operation - * terminates. + * terminates. It must allow the usage + * #PSA_KEY_USAGE_ENCRYPT. * \param alg The AEAD algorithm to compute * (\c PSA_ALG_XXX value such that * #PSA_ALG_IS_AEAD(\p alg) is true). @@ -2322,10 +2280,10 @@ static psa_aead_operation_t psa_aead_operation_init(void); * Success. * \retval #PSA_ERROR_BAD_STATE * The operation state is not valid (it must be inactive). - * \retval #PSA_ERROR_INVALID_HANDLE + * \retval #PSA_ERROR_INVALID_HANDLE * \retval #PSA_ERROR_NOT_PERMITTED * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p handle is not compatible with \p alg. + * \p key is not compatible with \p alg. * \retval #PSA_ERROR_NOT_SUPPORTED * \p alg is not supported or is not an AEAD algorithm. * \retval #PSA_ERROR_INSUFFICIENT_MEMORY @@ -2339,7 +2297,7 @@ static psa_aead_operation_t psa_aead_operation_init(void); * results in this error code. */ psa_status_t psa_aead_encrypt_setup(psa_aead_operation_t *operation, - psa_key_handle_t handle, + mbedtls_svc_key_id_t key, psa_algorithm_t alg); /** Set the key for a multipart authenticated decryption operation. @@ -2377,9 +2335,10 @@ psa_status_t psa_aead_encrypt_setup(psa_aead_operation_t *operation, * \param[in,out] operation The operation object to set up. It must have * been initialized as per the documentation for * #psa_aead_operation_t and not yet in use. - * \param handle Handle to the key to use for the operation. + * \param key Identifier of the key to use for the operation. * It must remain valid until the operation - * terminates. + * terminates. It must allow the usage + * #PSA_KEY_USAGE_DECRYPT. * \param alg The AEAD algorithm to compute * (\c PSA_ALG_XXX value such that * #PSA_ALG_IS_AEAD(\p alg) is true). @@ -2388,10 +2347,10 @@ psa_status_t psa_aead_encrypt_setup(psa_aead_operation_t *operation, * Success. * \retval #PSA_ERROR_BAD_STATE * The operation state is not valid (it must be inactive). - * \retval #PSA_ERROR_INVALID_HANDLE + * \retval #PSA_ERROR_INVALID_HANDLE * \retval #PSA_ERROR_NOT_PERMITTED * \retval #PSA_ERROR_INVALID_ARGUMENT - * \p handle is not compatible with \p alg. + * \p key is not compatible with \p alg. * \retval #PSA_ERROR_NOT_SUPPORTED * \p alg is not supported or is not an AEAD algorithm. * \retval #PSA_ERROR_INSUFFICIENT_MEMORY @@ -2405,7 +2364,7 @@ psa_status_t psa_aead_encrypt_setup(psa_aead_operation_t *operation, * results in this error code. */ psa_status_t psa_aead_decrypt_setup(psa_aead_operation_t *operation, - psa_key_handle_t handle, + mbedtls_svc_key_id_t key, psa_algorithm_t alg); /** Generate a random nonce for an authenticated encryption operation. @@ -2431,7 +2390,7 @@ psa_status_t psa_aead_decrypt_setup(psa_aead_operation_t *operation, * Success. * \retval #PSA_ERROR_BAD_STATE * The operation state is not valid (it must be an active aead encrypt - operation, with no nonce set). + * operation, with no nonce set). * \retval #PSA_ERROR_BUFFER_TOO_SMALL * The size of the \p nonce buffer is too small. * \retval #PSA_ERROR_INSUFFICIENT_MEMORY @@ -2863,10 +2822,11 @@ psa_status_t psa_aead_abort(psa_aead_operation_t *operation); * parameter to this function. You can use #PSA_ALG_SIGN_GET_HASH(\p alg) * to determine the hash algorithm to use. * - * \param handle Handle to the key to use for the operation. - * It must be an asymmetric key pair. + * \param key Identifier of the key to use for the operation. + * It must be an asymmetric key pair. The key must + * allow the usage #PSA_KEY_USAGE_SIGN_HASH. * \param alg A signature algorithm that is compatible with - * the type of \p handle. + * the type of \p key. * \param[in] hash The hash or message to sign. * \param hash_length Size of the \p hash buffer in bytes. * \param[out] signature Buffer where the signature is to be written. @@ -2882,7 +2842,7 @@ psa_status_t psa_aead_abort(psa_aead_operation_t *operation); * determine a sufficient buffer size by calling * #PSA_SIGN_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p handle. + * respectively of \p key. * \retval #PSA_ERROR_NOT_SUPPORTED * \retval #PSA_ERROR_INVALID_ARGUMENT * \retval #PSA_ERROR_INSUFFICIENT_MEMORY @@ -2896,7 +2856,7 @@ psa_status_t psa_aead_abort(psa_aead_operation_t *operation); * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_sign_hash(psa_key_handle_t handle, +psa_status_t psa_sign_hash(mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, @@ -2913,10 +2873,12 @@ psa_status_t psa_sign_hash(psa_key_handle_t handle, * parameter to this function. You can use #PSA_ALG_SIGN_GET_HASH(\p alg) * to determine the hash algorithm to use. * - * \param handle Handle to the key to use for the operation. - * It must be a public key or an asymmetric key pair. + * \param key Identifier of the key to use for the operation. It + * must be a public key or an asymmetric key pair. The + * key must allow the usage + * #PSA_KEY_USAGE_VERIFY_HASH. * \param alg A signature algorithm that is compatible with - * the type of \p handle. + * the type of \p key. * \param[in] hash The hash or message whose signature is to be * verified. * \param hash_length Size of the \p hash buffer in bytes. @@ -2942,7 +2904,7 @@ psa_status_t psa_sign_hash(psa_key_handle_t handle, * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_verify_hash(psa_key_handle_t handle, +psa_status_t psa_verify_hash(mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, @@ -2952,11 +2914,12 @@ psa_status_t psa_verify_hash(psa_key_handle_t handle, /** * \brief Encrypt a short message with a public key. * - * \param handle Handle to the key to use for the operation. - * It must be a public key or an asymmetric - * key pair. + * \param key Identifer of the key to use for the operation. + * It must be a public key or an asymmetric key + * pair. It must allow the usage + * #PSA_KEY_USAGE_ENCRYPT. * \param alg An asymmetric encryption algorithm that is - * compatible with the type of \p handle. + * compatible with the type of \p key. * \param[in] input The message to encrypt. * \param input_length Size of the \p input buffer in bytes. * \param[in] salt A salt or label, if supported by the @@ -2985,7 +2948,7 @@ psa_status_t psa_verify_hash(psa_key_handle_t handle, * determine a sufficient buffer size by calling * #PSA_ASYMMETRIC_ENCRYPT_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p handle. + * respectively of \p key. * \retval #PSA_ERROR_NOT_SUPPORTED * \retval #PSA_ERROR_INVALID_ARGUMENT * \retval #PSA_ERROR_INSUFFICIENT_MEMORY @@ -2999,7 +2962,7 @@ psa_status_t psa_verify_hash(psa_key_handle_t handle, * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_asymmetric_encrypt(psa_key_handle_t handle, +psa_status_t psa_asymmetric_encrypt(mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *input, size_t input_length, @@ -3012,10 +2975,11 @@ psa_status_t psa_asymmetric_encrypt(psa_key_handle_t handle, /** * \brief Decrypt a short message with a private key. * - * \param handle Handle to the key to use for the operation. - * It must be an asymmetric key pair. + * \param key Identifier of the key to use for the operation. + * It must be an asymmetric key pair. It must + * allow the usage #PSA_KEY_USAGE_DECRYPT. * \param alg An asymmetric encryption algorithm that is - * compatible with the type of \p handle. + * compatible with the type of \p key. * \param[in] input The message to decrypt. * \param input_length Size of the \p input buffer in bytes. * \param[in] salt A salt or label, if supported by the @@ -3044,7 +3008,7 @@ psa_status_t psa_asymmetric_encrypt(psa_key_handle_t handle, * determine a sufficient buffer size by calling * #PSA_ASYMMETRIC_DECRYPT_OUTPUT_SIZE(\c key_type, \c key_bits, \p alg) * where \c key_type and \c key_bits are the type and bit-size - * respectively of \p handle. + * respectively of \p key. * \retval #PSA_ERROR_NOT_SUPPORTED * \retval #PSA_ERROR_INVALID_ARGUMENT * \retval #PSA_ERROR_INSUFFICIENT_MEMORY @@ -3059,7 +3023,7 @@ psa_status_t psa_asymmetric_encrypt(psa_key_handle_t handle, * It is implementation-dependent whether a failure to initialize * results in this error code. */ -psa_status_t psa_asymmetric_decrypt(psa_key_handle_t handle, +psa_status_t psa_asymmetric_decrypt(mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *input, size_t input_length, @@ -3317,9 +3281,9 @@ psa_status_t psa_key_derivation_input_bytes( * psa_key_derivation_setup() and must not * have produced any output yet. * \param step Which step the input data is for. - * \param handle Handle to the key. It must have an - * appropriate type for \p step and must - * allow the usage #PSA_KEY_USAGE_DERIVE. + * \param key Identifier of the key. It must have an + * appropriate type for step and must allow the + * usage #PSA_KEY_USAGE_DERIVE. * * \retval #PSA_SUCCESS * Success. @@ -3345,7 +3309,7 @@ psa_status_t psa_key_derivation_input_bytes( psa_status_t psa_key_derivation_input_key( psa_key_derivation_operation_t *operation, psa_key_derivation_step_t step, - psa_key_handle_t handle); + mbedtls_svc_key_id_t key); /** Perform a key agreement and use the shared secret as input to a key * derivation. @@ -3370,7 +3334,8 @@ psa_status_t psa_key_derivation_input_key( * The operation must be ready for an * input of the type given by \p step. * \param step Which step the input data is for. - * \param private_key Handle to the private key to use. + * \param private_key Identifier of the private key to use. It must + * allow the usage #PSA_KEY_USAGE_DERIVE. * \param[in] peer_key Public key of the peer. The peer key must be in the * same format that psa_import_key() accepts for the * public key type corresponding to the type of @@ -3414,7 +3379,7 @@ psa_status_t psa_key_derivation_input_key( psa_status_t psa_key_derivation_key_agreement( psa_key_derivation_operation_t *operation, psa_key_derivation_step_t step, - psa_key_handle_t private_key, + mbedtls_svc_key_id_t private_key, const uint8_t *peer_key, size_t peer_key_length); @@ -3558,7 +3523,9 @@ psa_status_t psa_key_derivation_output_bytes( * * \param[in] attributes The attributes for the new key. * \param[in,out] operation The key derivation operation object to read from. - * \param[out] handle On success, a handle to the newly created key. + * \param[out] key On success, an identifier for the newly created + * key. For persistent keys, this is the key + * identifier defined in \p attributes. * \c 0 on failure. * * \retval #PSA_SUCCESS @@ -3598,7 +3565,7 @@ psa_status_t psa_key_derivation_output_bytes( psa_status_t psa_key_derivation_output_key( const psa_key_attributes_t *attributes, psa_key_derivation_operation_t *operation, - psa_key_handle_t *handle); + mbedtls_svc_key_id_t *key); /** Abort a key derivation operation. * @@ -3639,7 +3606,8 @@ psa_status_t psa_key_derivation_abort( * (\c PSA_ALG_XXX value such that * #PSA_ALG_IS_RAW_KEY_AGREEMENT(\p alg) * is true). - * \param private_key Handle to the private key to use. + * \param private_key Identifier of the private key to use. It must + * allow the usage #PSA_KEY_USAGE_DERIVE. * \param[in] peer_key Public key of the peer. It must be * in the same format that psa_import_key() * accepts. The standard formats for public @@ -3677,7 +3645,7 @@ psa_status_t psa_key_derivation_abort( * results in this error code. */ psa_status_t psa_raw_key_agreement(psa_algorithm_t alg, - psa_key_handle_t private_key, + mbedtls_svc_key_id_t private_key, const uint8_t *peer_key, size_t peer_key_length, uint8_t *output, @@ -3733,7 +3701,9 @@ psa_status_t psa_generate_random(uint8_t *output, * attributes. * * \param[in] attributes The attributes for the new key. - * \param[out] handle On success, a handle to the newly created key. + * \param[out] key On success, an identifier for the newly created + * key. For persistent keys, this is the key + * identifier defined in \p attributes. * \c 0 on failure. * * \retval #PSA_SUCCESS @@ -3758,7 +3728,7 @@ psa_status_t psa_generate_random(uint8_t *output, * results in this error code. */ psa_status_t psa_generate_key(const psa_key_attributes_t *attributes, - psa_key_handle_t *handle); + mbedtls_svc_key_id_t *key); /**@}*/ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_accel_driver.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_accel_driver.h index 1a193c5b9e..4488ea8ad8 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_accel_driver.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_accel_driver.h @@ -75,7 +75,7 @@ typedef struct psa_drv_hash_context_s psa_drv_hash_context_t; * \param[in,out] p_context A structure that will contain the * hardware-specific hash context * - * \retval PSA_SUCCESS Success. + * \retval #PSA_SUCCESS Success. */ typedef psa_status_t (*psa_drv_hash_setup_t)(psa_drv_hash_context_t *p_context); @@ -120,7 +120,7 @@ typedef psa_status_t (*psa_drv_hash_update_t)(psa_drv_hash_context_t *p_context, * \param[out] p_output_length The number of bytes placed in `p_output` after * success * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * Success. */ typedef psa_status_t (*psa_drv_hash_finish_t)(psa_drv_hash_context_t *p_context, @@ -188,7 +188,7 @@ typedef struct psa_drv_accel_mac_context_s psa_drv_accel_mac_context_t; * to be used in the operation * \param[in] key_length The size in bytes of the key material * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * Success. */ typedef psa_status_t (*psa_drv_accel_mac_setup_t)(psa_drv_accel_mac_context_t *p_context, @@ -235,7 +235,7 @@ typedef psa_status_t (*psa_drv_accel_mac_update_t)(psa_drv_accel_mac_context_t * * \param[in] mac_length The size in bytes of the buffer that has been * allocated for the `p_mac` buffer * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * Success. */ typedef psa_status_t (*psa_drv_accel_mac_finish_t)(psa_drv_accel_mac_context_t *p_context, @@ -261,7 +261,7 @@ typedef psa_status_t (*psa_drv_accel_mac_finish_t)(psa_drv_accel_mac_context_t * * \param[in] mac_length The size in bytes of the data in the `p_mac` * buffer * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * The operation completed successfully and the comparison matched */ typedef psa_status_t (*psa_drv_accel_mac_finish_verify_t)(psa_drv_accel_mac_context_t *p_context, @@ -335,7 +335,7 @@ typedef psa_status_t (*psa_drv_accel_mac_t)(const uint8_t *p_input, * \param[in] p_mac The MAC data to be compared * \param[in] mac_length The length in bytes of the `p_mac` buffer * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * The operation completed successfully and the comparison matched */ typedef psa_status_t (*psa_drv_accel_mac_verify_t)(const uint8_t *p_input, @@ -396,7 +396,7 @@ typedef struct psa_drv_accel_cipher_context_s psa_drv_accel_cipher_context_t; * to be used in the operation * \param[in] key_data_size The size in bytes of the key material * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_accel_cipher_setup_t)(psa_drv_accel_cipher_context_t *p_context, psa_encrypt_or_decrypt_t direction, @@ -419,7 +419,7 @@ typedef psa_status_t (*psa_drv_accel_cipher_setup_t)(psa_drv_accel_cipher_contex * \param[in] p_iv A buffer containing the initialization vecotr * \param[in] iv_length The size in bytes of the contents of `p_iv` * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_accel_cipher_set_iv_t)(psa_drv_accel_cipher_context_t *p_context, const uint8_t *p_iv, @@ -448,7 +448,7 @@ typedef psa_status_t (*psa_drv_accel_cipher_set_iv_t)(psa_drv_accel_cipher_conte * \param[out] p_output_length After completion, will contain the number * of bytes placed in the `p_output` buffer * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_accel_cipher_update_t)(psa_drv_accel_cipher_context_t *p_context, const uint8_t *p_input, @@ -477,7 +477,7 @@ typedef psa_status_t (*psa_drv_accel_cipher_update_t)(psa_drv_accel_cipher_conte * \param[out] p_output_length After completion, will contain the number of * bytes placed in the `p_output` buffer * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_accel_cipher_finish_t)(psa_drv_accel_cipher_context_t *p_context, uint8_t *p_output, @@ -499,7 +499,7 @@ typedef psa_status_t (*psa_drv_accel_cipher_finish_t)(psa_drv_accel_cipher_conte * \param[in,out] p_context A hardware-specific structure for the * previously started cipher operation * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_accel_cipher_abort_t)(psa_drv_accel_cipher_context_t *p_context); @@ -659,7 +659,7 @@ typedef psa_status_t (*psa_drv_accel_aead_decrypt_t)(const uint8_t *p_key, * \param[out] p_signature_length On success, the number of bytes * that make up the returned signature value * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_accel_asymmetric_sign_t)(const uint8_t *p_key, size_t key_size, @@ -697,7 +697,7 @@ typedef psa_status_t (*psa_drv_accel_asymmetric_sign_t)(const uint8_t *p_key, * \param[in] p_signature Buffer containing the signature to verify * \param[in] signature_length Size of the `p_signature` buffer in bytes * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * The signature is valid. */ typedef psa_status_t (*psa_drv_accel_asymmetric_verify_t)(const uint8_t *p_key, @@ -748,7 +748,7 @@ typedef psa_status_t (*psa_drv_accel_asymmetric_verify_t)(const uint8_t *p_key, * \param[out] p_output_length On success, the number of bytes * that make up the returned output * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_accel_asymmetric_encrypt_t)(const uint8_t *p_key, size_t key_size, @@ -800,7 +800,7 @@ typedef psa_status_t (*psa_drv_accel_asymmetric_encrypt_t)(const uint8_t *p_key, * \param[out] p_output_length On success, the number of bytes * that make up the returned output * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_accel_asymmetric_decrypt_t)(const uint8_t *p_key, size_t key_size, diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_compat.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_compat.h index 4b607b6ff6..5bb5669386 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_compat.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_compat.h @@ -34,6 +34,27 @@ extern "C" { #endif +/* + * To support both openless APIs and psa_open_key() temporarily, define + * psa_key_handle_t to be equal to mbedtls_svc_key_id_t. Do not mark the + * type and its utility macros and functions deprecated yet. This will be done + * in a subsequent phase. + */ +typedef mbedtls_svc_key_id_t psa_key_handle_t; + +#define PSA_KEY_HANDLE_INIT MBEDTLS_SVC_KEY_ID_INIT + +/** Check wether an handle is null. + * + * \param handle Handle + * + * \return Non-zero if the handle is null, zero otherwise. + */ +static inline int psa_key_handle_is_null( psa_key_handle_t handle ) +{ + return( mbedtls_svc_key_id_is_null( handle ) ); +} + #if !defined(MBEDTLS_DEPRECATED_REMOVED) /* @@ -52,6 +73,7 @@ typedef MBEDTLS_PSA_DEPRECATED psa_ecc_family_t mbedtls_deprecated_psa_ecc_famil typedef MBEDTLS_PSA_DEPRECATED psa_dh_family_t mbedtls_deprecated_psa_dh_family_t; typedef MBEDTLS_PSA_DEPRECATED psa_ecc_family_t psa_ecc_curve_t; typedef MBEDTLS_PSA_DEPRECATED psa_dh_family_t psa_dh_group_t; +typedef MBEDTLS_PSA_DEPRECATED psa_algorithm_t mbedtls_deprecated_psa_algorithm_t; #define PSA_KEY_TYPE_GET_CURVE PSA_KEY_TYPE_ECC_GET_FAMILY #define PSA_KEY_TYPE_GET_GROUP PSA_KEY_TYPE_DH_GET_FAMILY @@ -113,10 +135,6 @@ MBEDTLS_PSA_DEPRECATED static inline psa_status_t psa_asymmetric_verify( psa_key return psa_verify_hash( key, alg, hash, hash_length, signature, signature_length ); } - - -#endif /* MBEDTLS_DEPRECATED_REMOVED */ - /* * Size-specific elliptic curve families. */ @@ -223,6 +241,117 @@ MBEDTLS_PSA_DEPRECATED static inline psa_status_t psa_asymmetric_verify( psa_key #define PSA_DH_GROUP_CUSTOM \ MBEDTLS_DEPRECATED_CONSTANT( psa_dh_family_t, PSA_DH_FAMILY_CUSTOM ) +/* + * Deprecated PSA Crypto stream cipher algorithms (PSA Crypto API <= 1.0 beta3) + */ +#define PSA_ALG_ARC4 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_algorithm_t, PSA_ALG_STREAM_CIPHER ) +#define PSA_ALG_CHACHA20 \ + MBEDTLS_DEPRECATED_CONSTANT( psa_algorithm_t, PSA_ALG_STREAM_CIPHER ) + +#endif /* MBEDTLS_DEPRECATED_REMOVED */ + +/** Open a handle to an existing persistent key. + * + * Open a handle to a persistent key. A key is persistent if it was created + * with a lifetime other than #PSA_KEY_LIFETIME_VOLATILE. A persistent key + * always has a nonzero key identifier, set with psa_set_key_id() when + * creating the key. Implementations may provide additional pre-provisioned + * keys that can be opened with psa_open_key(). Such keys have an application + * key identifier in the vendor range, as documented in the description of + * #psa_key_id_t. + * + * The application must eventually close the handle with psa_close_key() or + * psa_destroy_key() to release associated resources. If the application dies + * without calling one of these functions, the implementation should perform + * the equivalent of a call to psa_close_key(). + * + * Some implementations permit an application to open the same key multiple + * times. If this is successful, each call to psa_open_key() will return a + * different key handle. + * + * \note This API is not part of the PSA Cryptography API Release 1.0.0 + * specification. It was defined in the 1.0 Beta 3 version of the + * specification but was removed in the 1.0.0 released version. This API is + * kept for the time being to not break applications relying on it. It is not + * deprecated yet but will be in the near future. + * + * \note Applications that rely on opening a key multiple times will not be + * portable to implementations that only permit a single key handle to be + * opened. See also :ref:\`key-handles\`. + * + * + * \param key The persistent identifier of the key. + * \param[out] handle On success, a handle to the key. + * + * \retval #PSA_SUCCESS + * Success. The application can now use the value of `*handle` + * to access the key. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * The implementation does not have sufficient resources to open the + * key. This can be due to reaching an implementation limit on the + * number of open keys, the number of open key handles, or available + * memory. + * \retval #PSA_ERROR_DOES_NOT_EXIST + * There is no persistent key with key identifier \p id. + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \p id is not a valid persistent key identifier. + * \retval #PSA_ERROR_NOT_PERMITTED + * The specified key exists, but the application does not have the + * permission to access it. Note that this specification does not + * define any way to create such a key, but it may be possible + * through implementation-specific means. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE + * \retval #PSA_ERROR_CORRUPTION_DETECTED + * \retval #PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_open_key( mbedtls_svc_key_id_t key, + psa_key_handle_t *handle ); + +/** Close a key handle. + * + * If the handle designates a volatile key, this will destroy the key material + * and free all associated resources, just like psa_destroy_key(). + * + * If this is the last open handle to a persistent key, then closing the handle + * will free all resources associated with the key in volatile memory. The key + * data in persistent storage is not affected and can be opened again later + * with a call to psa_open_key(). + * + * Closing the key handle makes the handle invalid, and the key handle + * must not be used again by the application. + * + * \note This API is not part of the PSA Cryptography API Release 1.0.0 + * specification. It was defined in the 1.0 Beta 3 version of the + * specification but was removed in the 1.0.0 released version. This API is + * kept for the time being to not break applications relying on it. It is not + * deprecated yet but will be in the near future. + * + * \note If the key handle was used to set up an active + * :ref:\`multipart operation \`, then closing the + * key handle can cause the multipart operation to fail. Applications should + * maintain the key handle until after the multipart operation has finished. + * + * \param handle The key handle to close. + * If this is \c 0, do nothing and return \c PSA_SUCCESS. + * + * \retval #PSA_SUCCESS + * \p handle was a valid handle or \c 0. It is now closed. + * \retval #PSA_ERROR_INVALID_HANDLE + * \p handle is not a valid handle nor \c 0. + * \retval #PSA_ERROR_COMMUNICATION_FAILURE + * \retval #PSA_ERROR_CORRUPTION_DETECTED + * \retval #PSA_ERROR_BAD_STATE + * The library has not been previously initialized by psa_crypto_init(). + * It is implementation-dependent whether a failure to initialize + * results in this error code. + */ +psa_status_t psa_close_key(psa_key_handle_t handle); + #ifdef __cplusplus } #endif diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_config.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_config.h new file mode 100644 index 0000000000..cf7f63a05d --- /dev/null +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_config.h @@ -0,0 +1,78 @@ +/** + * \file psa/crypto_config.h + * \brief PSA crypto configuration options (set of defines) + * + */ +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) +/** + * When #MBEDTLS_PSA_CRYPTO_CONFIG is enabled in config.h, + * this file determines which cryptographic mechanisms are enabled + * through the PSA Cryptography API (\c psa_xxx() functions). + * + * To enable a cryptographic mechanism, uncomment the definition of + * the corresponding \c PSA_WANT_xxx preprocessor symbol. + * To disable a cryptographic mechanism, comment out the definition of + * the corresponding \c PSA_WANT_xxx preprocessor symbol. + * The names of cryptographic mechanisms correspond to values + * defined in psa/crypto_values.h, with the prefix \c PSA_WANT_ instead + * of \c PSA_. + * + * Note that many cryptographic mechanisms involve two symbols: one for + * the key type (\c PSA_WANT_KEY_TYPE_xxx) and one for the algorithm + * (\c PSA_WANT_ALG_xxx). Mechanisms with additional parameters may involve + * additional symbols. + */ +#else +/** + * When \c MBEDTLS_PSA_CRYPTO_CONFIG is disabled in config.h, + * this file is not used, and cryptographic mechanisms are supported + * through the PSA API if and only if they are supported through the + * mbedtls_xxx API. + */ +#endif +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_CONFIG_H +#define PSA_CRYPTO_CONFIG_H + +#define PSA_WANT_ALG_DETERMINISTIC_ECDSA 1 +#define PSA_WANT_ALG_ECDH 1 +#define PSA_WANT_ALG_ECDSA 1 +#define PSA_WANT_ALG_HKDF 1 +#define PSA_WANT_ALG_HMAC 1 +#define PSA_WANT_ALG_MD2 1 +#define PSA_WANT_ALG_MD4 1 +#define PSA_WANT_ALG_MD5 1 +#define PSA_WANT_ALG_RIPEMD160 1 +#define PSA_WANT_ALG_RSA_OAEP 1 +#define PSA_WANT_ALG_RSA_PKCS1V15_CRYPT 1 +#define PSA_WANT_ALG_RSA_PKCS1V15_SIGN 1 +#define PSA_WANT_ALG_RSA_PSS 1 +#define PSA_WANT_ALG_SHA_1 1 +#define PSA_WANT_ALG_SHA_224 1 +#define PSA_WANT_ALG_SHA_256 1 +#define PSA_WANT_ALG_SHA_384 1 +#define PSA_WANT_ALG_SHA_512 1 +#define PSA_WANT_ALG_TLS12_PRF 1 +#define PSA_WANT_ALG_TLS12_PSK_TO_MS 1 +#define PSA_WANT_KEY_TYPE_ECC_KEY_PAIR 1 +#define PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY 1 +#define PSA_WANT_KEY_TYPE_RSA_KEY_PAIR 1 +#define PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY 1 + +#endif /* PSA_CRYPTO_CONFIG_H */ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_entropy_driver.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_entropy_driver.h index 61750448bb..9b6546ee94 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_entropy_driver.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_entropy_driver.h @@ -47,7 +47,7 @@ extern "C" { * containing any context information for * the implementation * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_entropy_init_t)(void *p_context); @@ -75,7 +75,7 @@ typedef psa_status_t (*psa_drv_entropy_init_t)(void *p_context); * \param[out] p_received_entropy_bits The amount of entropy (in bits) * actually provided in `p_buffer` * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_entropy_get_bits_t)(void *p_context, uint8_t *p_buffer, diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_extra.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_extra.h index 1e6a4bba26..f793a6cacb 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_extra.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_extra.h @@ -32,8 +32,6 @@ #include "crypto_compat.h" -#include "platform/mbed_toolchain.h" - #ifdef __cplusplus extern "C" { #endif @@ -56,17 +54,15 @@ extern "C" { * for, in addition to the algorithm set with * psa_set_key_algorithm(). * - * \deprecated This is for backward compatibility only. - * Setting an enrollment algorithm is not recommended, because - * using the same key with different algorithms can allow some - * attacks based on arithmetic relations between different - * computations made with the same key, or can escalate harmless - * side channels into exploitable ones. Use this function only - * if it is necessary to support a protocol for which it has been - * verified that the usage of the key with multiple algorithms - * is safe. + * \warning Setting an enrollment algorithm is not recommended, because + * using the same key with different algorithms can allow some + * attacks based on arithmetic relations between different + * computations made with the same key, or can escalate harmless + * side channels into exploitable ones. Use this function only + * if it is necessary to support a protocol for which it has been + * verified that the usage of the key with multiple algorithms + * is safe. */ -MBED_DEPRECATED("Setting enrollment algorithm is for backward compatibility and not recommended.") static inline void psa_set_key_enrollment_algorithm( psa_key_attributes_t *attributes, psa_algorithm_t alg2) @@ -79,10 +75,7 @@ static inline void psa_set_key_enrollment_algorithm( * \param[in] attributes The key attribute structure to query. * * \return The enrollment algorithm stored in the attribute structure. - * \deprecated This is for backward compatibility only. - * Deprecated along with psa_set_key_enrollment_algorithm(). */ -MBED_DEPRECATED("Getting enrollment algorithm is for backward compatibility and not recommended.") static inline psa_algorithm_t psa_get_key_enrollment_algorithm( const psa_key_attributes_t *attributes) { @@ -238,10 +231,12 @@ typedef struct mbedtls_psa_stats_s size_t cache_slots; /** Number of slots that are not used for anything. */ size_t empty_slots; + /** Number of slots that are locked. */ + size_t locked_slots; /** Largest key id value among open keys in internal persistent storage. */ - psa_app_key_id_t max_open_internal_key_id; + psa_key_id_t max_open_internal_key_id; /** Largest key id value among open keys in secure elements. */ - psa_app_key_id_t max_open_external_key_id; + psa_key_id_t max_open_external_key_id; } mbedtls_psa_stats_t; /** \brief Get statistics about @@ -358,7 +353,7 @@ psa_status_t mbedtls_psa_inject_entropy(const uint8_t *seed, #define PSA_KEY_TYPE_IS_DSA(type) \ (PSA_KEY_TYPE_PUBLIC_KEY_OF_KEY_PAIR(type) == PSA_KEY_TYPE_DSA_PUBLIC_KEY) -#define PSA_ALG_DSA_BASE ((psa_algorithm_t)0x10040000) +#define PSA_ALG_DSA_BASE ((psa_algorithm_t)0x06000400) /** DSA signature with hashing. * * This is the signature scheme defined by FIPS 186-4, @@ -375,7 +370,7 @@ psa_status_t mbedtls_psa_inject_entropy(const uint8_t *seed, */ #define PSA_ALG_DSA(hash_alg) \ (PSA_ALG_DSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -#define PSA_ALG_DETERMINISTIC_DSA_BASE ((psa_algorithm_t)0x10050000) +#define PSA_ALG_DETERMINISTIC_DSA_BASE ((psa_algorithm_t)0x06000500) #define PSA_ALG_DSA_DETERMINISTIC_FLAG PSA_ALG_ECDSA_DETERMINISTIC_FLAG /** Deterministic DSA signature with hashing. * diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_platform.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_platform.h index 77c0e5b2f0..567398dbfd 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_platform.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_platform.h @@ -41,60 +41,44 @@ #include MBEDTLS_CONFIG_FILE #endif +/* Translate between classic MBEDTLS_xxx feature symbols and PSA_xxx + * feature symbols. */ +#include "mbedtls/config_psa.h" + /* PSA requires several types which C99 provides in stdint.h. */ #include -/* Integral type representing a key handle. */ -typedef uint16_t psa_key_handle_t; - -/* This implementation distinguishes *application key identifiers*, which - * are the key identifiers specified by the application, from - * *key file identifiers*, which are the key identifiers that the library - * sees internally. The two types can be different if there is a remote - * call layer between the application and the library which supports - * multiple client applications that do not have access to each others' - * keys. The point of having different types is that the key file - * identifier may encode not only the key identifier specified by the - * application, but also the the identity of the application. - * - * Note that this is an internal concept of the library and the remote - * call layer. The application itself never sees anything other than - * #psa_app_key_id_t with its standard definition. - */ - -/* The application key identifier is always what the application sees as - * #psa_key_id_t. */ -typedef uint32_t psa_app_key_id_t; - -#if defined(MBEDTLS_PSA_CRYPTO_KEY_FILE_ID_ENCODES_OWNER) - -#if defined(PSA_CRYPTO_SECURE) -/* Building for the PSA Crypto service on a PSA platform. */ -/* A key owner is a PSA partition identifier. */ -typedef int32_t psa_key_owner_id_t; +#if ( defined(__ARMCC_VERSION) || defined(_MSC_VER) ) && \ + !defined(inline) && !defined(__cplusplus) +#define inline __inline #endif -typedef struct +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + +/* Building for the PSA Crypto service on a PSA platform, a key owner is a PSA + * partition identifier. + * + * The function psa_its_identifier_of_slot() in psa_crypto_storage.c that + * translates a key identifier to a key storage file name assumes that + * mbedtls_key_owner_id_t is an 32 bits integer. This function thus needs + * reworking if mbedtls_key_owner_id_t is not defined as a 32 bits integer + * here anymore. + */ +typedef int32_t mbedtls_key_owner_id_t; + +/** Compare two key owner identifiers. + * + * \param id1 First key owner identifier. + * \param id2 Second key owner identifier. + * + * \return Non-zero if the two key owner identifiers are equal, zero otherwise. + */ +static inline int mbedtls_key_owner_id_equal( mbedtls_key_owner_id_t id1, + mbedtls_key_owner_id_t id2 ) { - uint32_t key_id; - psa_key_owner_id_t owner; -} psa_key_file_id_t; -#define PSA_KEY_FILE_GET_KEY_ID( file_id ) ( ( file_id ).key_id ) + return( id1 == id2 ); +} -/* Since crypto.h is used as part of the PSA Cryptography API specification, - * it must use standard types for things like the argument of psa_open_key(). - * If it wasn't for that constraint, psa_open_key() would take a - * `psa_key_file_id_t` argument. As a workaround, make `psa_key_id_t` an - * alias for `psa_key_file_id_t` when building for a multi-client service. */ -typedef psa_key_file_id_t psa_key_id_t; -#define PSA_KEY_ID_INIT {0, 0} - -#else /* !MBEDTLS_PSA_CRYPTO_KEY_FILE_ID_ENCODES_OWNER */ - -/* By default, a key file identifier is just the application key identifier. */ -typedef psa_app_key_id_t psa_key_file_id_t; -#define PSA_KEY_FILE_GET_KEY_ID( id ) ( id ) - -#endif /* !MBEDTLS_PSA_CRYPTO_KEY_FILE_ID_ENCODES_OWNER */ +#endif /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ #endif /* PSA_CRYPTO_PLATFORM_H */ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_se_driver.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_se_driver.h index 46b2d645cb..1fae575161 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_se_driver.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_se_driver.h @@ -178,7 +178,7 @@ typedef uint64_t psa_key_slot_number_t; * \param[in] algorithm The algorithm to be used to underly the MAC * operation * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * Success. */ typedef psa_status_t (*psa_drv_se_mac_setup_t)(psa_drv_se_context_t *drv_context, @@ -213,7 +213,7 @@ typedef psa_status_t (*psa_drv_se_mac_update_t)(void *op_context, * \param[out] p_mac_length After completion, will contain the number of * bytes placed in the `p_mac` buffer * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * Success. */ typedef psa_status_t (*psa_drv_se_mac_finish_t)(void *op_context, @@ -230,10 +230,10 @@ typedef psa_status_t (*psa_drv_se_mac_finish_t)(void *op_context, * will be compared against * \param[in] mac_length The size in bytes of the value stored in `p_mac` * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * The operation completed successfully and the MACs matched each * other - * \retval PSA_ERROR_INVALID_SIGNATURE + * \retval #PSA_ERROR_INVALID_SIGNATURE * The operation completed successfully, but the calculated MAC did * not match the provided MAC */ @@ -264,7 +264,7 @@ typedef psa_status_t (*psa_drv_se_mac_abort_t)(void *op_context); * \param[out] p_mac_length After completion, will contain the number of * bytes placed in the `output` buffer * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * Success. */ typedef psa_status_t (*psa_drv_se_mac_generate_t)(psa_drv_se_context_t *drv_context, @@ -289,10 +289,10 @@ typedef psa_status_t (*psa_drv_se_mac_generate_t)(psa_drv_se_context_t *drv_cont * be compared against * \param[in] mac_length The size in bytes of `mac` * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * The operation completed successfully and the MACs matched each * other - * \retval PSA_ERROR_INVALID_SIGNATURE + * \retval #PSA_ERROR_INVALID_SIGNATURE * The operation completed successfully, but the calculated MAC did * not match the provided MAC */ @@ -384,8 +384,8 @@ typedef struct { * \param[in] direction Indicates whether the operation is an encrypt * or decrypt * - * \retval PSA_SUCCESS - * \retval PSA_ERROR_NOT_SUPPORTED + * \retval #PSA_SUCCESS + * \retval #PSA_ERROR_NOT_SUPPORTED */ typedef psa_status_t (*psa_drv_se_cipher_setup_t)(psa_drv_se_context_t *drv_context, void *op_context, @@ -406,7 +406,7 @@ typedef psa_status_t (*psa_drv_se_cipher_setup_t)(psa_drv_se_context_t *drv_cont * \param[in] p_iv A buffer containing the initialization vector * \param[in] iv_length The size (in bytes) of the `p_iv` buffer * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_se_cipher_set_iv_t)(void *op_context, const uint8_t *p_iv, @@ -428,7 +428,7 @@ typedef psa_status_t (*psa_drv_se_cipher_set_iv_t)(void *op_context, * \param[out] p_output_length After completion, will contain the number * of bytes placed in the `p_output` buffer * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_se_cipher_update_t)(void *op_context, const uint8_t *p_input, @@ -449,7 +449,7 @@ typedef psa_status_t (*psa_drv_se_cipher_update_t)(void *op_context, * \param[out] p_output_length After completion, will contain the number of * bytes placed in the `p_output` buffer * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_se_cipher_finish_t)(void *op_context, uint8_t *p_output, @@ -484,8 +484,8 @@ typedef psa_status_t (*psa_drv_se_cipher_abort_t)(void *op_context); * \param[in] output_size The allocated size in bytes of the `p_output` * buffer * - * \retval PSA_SUCCESS - * \retval PSA_ERROR_NOT_SUPPORTED + * \retval #PSA_SUCCESS + * \retval #PSA_ERROR_NOT_SUPPORTED */ typedef psa_status_t (*psa_drv_se_cipher_ecb_t)(psa_drv_se_context_t *drv_context, psa_key_slot_number_t key_slot, @@ -553,7 +553,7 @@ typedef struct { * \param[out] p_signature_length On success, the number of bytes * that make up the returned signature value * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_se_asymmetric_sign_t)(psa_drv_se_context_t *drv_context, psa_key_slot_number_t key_slot, @@ -578,7 +578,7 @@ typedef psa_status_t (*psa_drv_se_asymmetric_sign_t)(psa_drv_se_context_t *drv_c * \param[in] p_signature Buffer containing the signature to verify * \param[in] signature_length Size of the `p_signature` buffer in bytes * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * The signature is valid. */ typedef psa_status_t (*psa_drv_se_asymmetric_verify_t)(psa_drv_se_context_t *drv_context, @@ -617,7 +617,7 @@ typedef psa_status_t (*psa_drv_se_asymmetric_verify_t)(psa_drv_se_context_t *drv * \param[out] p_output_length On success, the number of bytes that make up * the returned output * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_se_asymmetric_encrypt_t)(psa_drv_se_context_t *drv_context, psa_key_slot_number_t key_slot, @@ -657,7 +657,7 @@ typedef psa_status_t (*psa_drv_se_asymmetric_encrypt_t)(psa_drv_se_context_t *dr * \param[out] p_output_length On success, the number of bytes * that make up the returned output * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_se_asymmetric_decrypt_t)(psa_drv_se_context_t *drv_context, psa_key_slot_number_t key_slot, @@ -1195,7 +1195,7 @@ typedef struct { * \param[in] source_key The key to be used as the source material for * the key derivation * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_se_key_derivation_setup_t)(psa_drv_se_context_t *drv_context, void *op_context, @@ -1215,7 +1215,7 @@ typedef psa_status_t (*psa_drv_se_key_derivation_setup_t)(psa_drv_se_context_t * * \param[in] p_collateral A buffer containing the collateral data * \param[in] collateral_size The size in bytes of the collateral * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_se_key_derivation_collateral_t)(void *op_context, uint32_t collateral_id, @@ -1230,7 +1230,7 @@ typedef psa_status_t (*psa_drv_se_key_derivation_collateral_t)(void *op_context, * \param[in] dest_key The slot where the generated key material * should be placed * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_se_key_derivation_derive_t)(void *op_context, psa_key_slot_number_t dest_key); @@ -1244,7 +1244,7 @@ typedef psa_status_t (*psa_drv_se_key_derivation_derive_t)(void *op_context, * \param[out] p_output_length Upon success, contains the number of bytes of * key material placed in `p_output` * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS */ typedef psa_status_t (*psa_drv_se_key_derivation_export_t)(void *op_context, uint8_t *p_output, @@ -1353,7 +1353,7 @@ typedef struct { * \param location The location value through which this driver will * be exposed to applications. * This driver will be used for all keys such that - * `location == PSA_KEY_LIFETIME_LOCATION( lifetime )`. + * `location == #PSA_KEY_LIFETIME_GET_LOCATION( lifetime )`. * The value #PSA_KEY_LOCATION_LOCAL_STORAGE is reserved * and may not be used for drivers. Implementations * may reserve other values. @@ -1362,22 +1362,22 @@ typedef struct { * module keeps running. It is typically a global * constant. * - * \return PSA_SUCCESS + * \return #PSA_SUCCESS * The driver was successfully registered. Applications can now * use \p lifetime to access keys through the methods passed to * this function. - * \return PSA_ERROR_BAD_STATE + * \return #PSA_ERROR_BAD_STATE * This function was called after the initialization of the * cryptography module, and this implementation does not support * driver registration at this stage. - * \return PSA_ERROR_ALREADY_EXISTS + * \return #PSA_ERROR_ALREADY_EXISTS * There is already a registered driver for this value of \p lifetime. - * \return PSA_ERROR_INVALID_ARGUMENT + * \return #PSA_ERROR_INVALID_ARGUMENT * \p lifetime is a reserved value. - * \return PSA_ERROR_NOT_SUPPORTED + * \return #PSA_ERROR_NOT_SUPPORTED * `methods->hal_version` is not supported by this implementation. - * \return PSA_ERROR_INSUFFICIENT_MEMORY - * \return PSA_ERROR_NOT_PERMITTED + * \return #PSA_ERROR_INSUFFICIENT_MEMORY + * \return #PSA_ERROR_NOT_PERMITTED */ psa_status_t psa_register_se_driver( psa_key_location_t location, diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_sizes.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_sizes.h index f6373b8c21..3df01b2ce8 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_sizes.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_sizes.h @@ -657,4 +657,91 @@ PSA_KEY_TYPE_IS_ECC_PUBLIC_KEY(key_type) ? PSA_KEY_EXPORT_ECC_PUBLIC_KEY_MAX_SIZE(key_bits) : \ 0) +/** The default nonce size for an AEAD algorithm, in bytes. + * + * This macro can be used to allocate a buffer of sufficient size to + * store the nonce output from #psa_aead_generate_nonce(). + * + * See also #PSA_AEAD_NONCE_MAX_SIZE. + * + * \note This is not the maximum size of nonce supported as input to #psa_aead_set_nonce(), + * #psa_aead_encrypt() or #psa_aead_decrypt(), just the default size that is generated by + * #psa_aead_generate_nonce(). + * + * \warning This macro may evaluate its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * \param key_type A symmetric key type that is compatible with algorithm \p alg. + * + * \param alg An AEAD algorithm (\c PSA_ALG_XXX value such that #PSA_ALG_IS_AEAD(\p alg) is true). + * + * \return The default nonce size for the specified key type and algorithm. + * If the key type or AEAD algorithm is not recognized, + * or the parameters are incompatible, return 0. + * An implementation can return either 0 or a correct size for a key type + * and AEAD algorithm that it recognizes, but does not support. + */ +#define PSA_AEAD_NONCE_LENGTH(key_type, alg) \ + (PSA_BLOCK_CIPHER_BLOCK_SIZE(key_type) == 16 && \ + (PSA_ALG_AEAD_WITH_DEFAULT_TAG_LENGTH(alg) == PSA_ALG_CCM || \ + PSA_ALG_AEAD_WITH_DEFAULT_TAG_LENGTH(alg) == PSA_ALG_GCM) ? 12 : \ + (key_type) == PSA_KEY_TYPE_CHACHA20 && \ + PSA_ALG_AEAD_WITH_DEFAULT_TAG_LENGTH(alg) == PSA_ALG_CHACHA20_POLY1305 ? 12 : \ + 0) + +/** The maximum default nonce size among all supported pairs of key types and AEAD algorithms, in bytes. + * + * This is equal to or greater than any value that #PSA_AEAD_NONCE_LENGTH() may return. + * + * \note This is not the maximum size of nonce supported as input to #psa_aead_set_nonce(), + * #psa_aead_encrypt() or #psa_aead_decrypt(), just the largest size that may be generated by + * #psa_aead_generate_nonce(). + */ +#define PSA_AEAD_NONCE_MAX_SIZE 12 + +/** The default IV size for a cipher algorithm, in bytes. + * + * The IV that is generated as part of a call to #psa_cipher_encrypt() is always + * the default IV length for the algorithm. + * + * This macro can be used to allocate a buffer of sufficient size to + * store the IV output from #psa_cipher_generate_iv() when using + * a multi-part cipher operation. + * + * See also #PSA_CIPHER_IV_MAX_SIZE. + * + * \warning This macro may evaluate its arguments multiple times or + * zero times, so you should not pass arguments that contain + * side effects. + * + * \param key_type A symmetric key type that is compatible with algorithm \p alg. + * + * \param alg A cipher algorithm (\c PSA_ALG_XXX value such that #PSA_ALG_IS_CIPHER(\p alg) is true). + * + * \return The default IV size for the specified key type and algorithm. + * If the algorithm does not use an IV, return 0. + * If the key type or cipher algorithm is not recognized, + * or the parameters are incompatible, return 0. + * An implementation can return either 0 or a correct size for a key type + * and cipher algorithm that it recognizes, but does not support. + */ +#define PSA_CIPHER_IV_LENGTH(key_type, alg) \ + (PSA_BLOCK_CIPHER_BLOCK_SIZE(key_type) > 1 && \ + ((alg) == PSA_ALG_CTR || \ + (alg) == PSA_ALG_CFB || \ + (alg) == PSA_ALG_OFB || \ + (alg) == PSA_ALG_XTS || \ + (alg) == PSA_ALG_CBC_NO_PADDING || \ + (alg) == PSA_ALG_CBC_PKCS7) ? PSA_BLOCK_CIPHER_BLOCK_SIZE(key_type) : \ + (key_type) == PSA_KEY_TYPE_CHACHA20 && \ + (alg) == PSA_ALG_STREAM_CIPHER ? 12 : \ + 0) + +/** The maximum IV size for all supported cipher algorithms, in bytes. + * + * See also #PSA_CIPHER_IV_LENGTH(). + */ +#define PSA_CIPHER_IV_MAX_SIZE 16 + #endif /* PSA_CRYPTO_SIZES_H */ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_types.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_types.h index 17718eb6dc..0a2ae54285 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_types.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_types.h @@ -33,6 +33,8 @@ #ifndef PSA_CRYPTO_TYPES_H #define PSA_CRYPTO_TYPES_H +#include "crypto_platform.h" + #include /** \defgroup error Error codes @@ -123,7 +125,7 @@ typedef uint32_t psa_algorithm_t; * implementation-specific device management event occurs (for example, * a factory reset). * - * Persistent keys have a key identifier of type #psa_key_id_t. + * Persistent keys have a key identifier of type #mbedtls_svc_key_id_t. * This identifier remains valid throughout the lifetime of the key, * even if the application instance that created the key terminates. * The application can call psa_open_key() to open a persistent key that @@ -226,15 +228,24 @@ typedef uint32_t psa_key_location_t; * - 0 is reserved as an invalid key identifier. * - Key identifiers outside these ranges are reserved for future use. */ -/* Implementation-specific quirk: The Mbed Crypto library can be built as - * part of a multi-client service that exposes the PSA Crypto API in each - * client and encodes the client identity in the key id argument of functions - * such as psa_open_key(). In this build configuration, we define - * psa_key_id_t in crypto_platform.h instead of here. */ -#if !defined(MBEDTLS_PSA_CRYPTO_KEY_FILE_ID_ENCODES_OWNER) typedef uint32_t psa_key_id_t; -#define PSA_KEY_ID_INIT 0 -#endif + +#if !defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) +typedef psa_key_id_t mbedtls_svc_key_id_t; + +#else /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ +/* Implementation-specific: The Mbed Cryptography library can be built as + * part of a multi-client service that exposes the PSA Cryptograpy API in each + * client and encodes the client identity in the key identifier argument of + * functions such as psa_open_key(). + */ +typedef struct +{ + psa_key_id_t key_id; + mbedtls_key_owner_id_t owner; +} mbedtls_svc_key_id_t; + +#endif /* !MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ /**@}*/ @@ -341,7 +352,7 @@ typedef uint32_t psa_key_usage_t; * -# Call a key creation function: psa_import_key(), psa_generate_key(), * psa_key_derivation_output_key() or psa_copy_key(). This function reads * the attribute structure, creates a key with these attributes, and - * outputs a handle to the newly created key. + * outputs a key identifier to the newly created key. * -# The attribute structure is now no longer necessary. * You may call psa_reset_key_attributes(), although this is optional * with the workflow presented here because the attributes currently diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_values.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_values.h index a940711803..f1b5c53ab2 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_values.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/inc/psa/crypto_values.h @@ -108,7 +108,7 @@ * as applicable. * * Implementations shall not return this error code to indicate that a - * key handle is invalid, but shall return #PSA_ERROR_INVALID_HANDLE + * key identifier is invalid, but shall return #PSA_ERROR_INVALID_HANDLE * instead. */ #define PSA_ERROR_BAD_STATE ((psa_status_t)-137) @@ -118,7 +118,7 @@ * combination of parameters are recognized as invalid. * * Implementations shall not return this error code to indicate that a - * key handle is invalid, but shall return #PSA_ERROR_INVALID_HANDLE + * key identifier is invalid, but shall return #PSA_ERROR_INVALID_HANDLE * instead. */ #define PSA_ERROR_INVALID_ARGUMENT ((psa_status_t)-135) @@ -266,7 +266,7 @@ * to read from a resource. */ #define PSA_ERROR_INSUFFICIENT_DATA ((psa_status_t)-143) -/** The key handle is not valid. See also :ref:\`key-handles\`. +/** The key identifier is not valid. See also :ref:\`key-handles\`. */ #define PSA_ERROR_INVALID_HANDLE ((psa_status_t)-136) @@ -609,14 +609,14 @@ #define PSA_ALG_VENDOR_FLAG ((psa_algorithm_t)0x80000000) #define PSA_ALG_CATEGORY_MASK ((psa_algorithm_t)0x7f000000) -#define PSA_ALG_CATEGORY_HASH ((psa_algorithm_t)0x01000000) -#define PSA_ALG_CATEGORY_MAC ((psa_algorithm_t)0x02000000) +#define PSA_ALG_CATEGORY_HASH ((psa_algorithm_t)0x02000000) +#define PSA_ALG_CATEGORY_MAC ((psa_algorithm_t)0x03000000) #define PSA_ALG_CATEGORY_CIPHER ((psa_algorithm_t)0x04000000) -#define PSA_ALG_CATEGORY_AEAD ((psa_algorithm_t)0x06000000) -#define PSA_ALG_CATEGORY_SIGN ((psa_algorithm_t)0x10000000) -#define PSA_ALG_CATEGORY_ASYMMETRIC_ENCRYPTION ((psa_algorithm_t)0x12000000) -#define PSA_ALG_CATEGORY_KEY_DERIVATION ((psa_algorithm_t)0x20000000) -#define PSA_ALG_CATEGORY_KEY_AGREEMENT ((psa_algorithm_t)0x30000000) +#define PSA_ALG_CATEGORY_AEAD ((psa_algorithm_t)0x05000000) +#define PSA_ALG_CATEGORY_SIGN ((psa_algorithm_t)0x06000000) +#define PSA_ALG_CATEGORY_ASYMMETRIC_ENCRYPTION ((psa_algorithm_t)0x07000000) +#define PSA_ALG_CATEGORY_KEY_DERIVATION ((psa_algorithm_t)0x08000000) +#define PSA_ALG_CATEGORY_KEY_AGREEMENT ((psa_algorithm_t)0x09000000) /** Whether an algorithm is vendor-defined. * @@ -718,35 +718,35 @@ #define PSA_ALG_HASH_MASK ((psa_algorithm_t)0x000000ff) /** MD2 */ -#define PSA_ALG_MD2 ((psa_algorithm_t)0x01000001) +#define PSA_ALG_MD2 ((psa_algorithm_t)0x02000001) /** MD4 */ -#define PSA_ALG_MD4 ((psa_algorithm_t)0x01000002) +#define PSA_ALG_MD4 ((psa_algorithm_t)0x02000002) /** MD5 */ -#define PSA_ALG_MD5 ((psa_algorithm_t)0x01000003) +#define PSA_ALG_MD5 ((psa_algorithm_t)0x02000003) /** PSA_ALG_RIPEMD160 */ -#define PSA_ALG_RIPEMD160 ((psa_algorithm_t)0x01000004) +#define PSA_ALG_RIPEMD160 ((psa_algorithm_t)0x02000004) /** SHA1 */ -#define PSA_ALG_SHA_1 ((psa_algorithm_t)0x01000005) +#define PSA_ALG_SHA_1 ((psa_algorithm_t)0x02000005) /** SHA2-224 */ -#define PSA_ALG_SHA_224 ((psa_algorithm_t)0x01000008) +#define PSA_ALG_SHA_224 ((psa_algorithm_t)0x02000008) /** SHA2-256 */ -#define PSA_ALG_SHA_256 ((psa_algorithm_t)0x01000009) +#define PSA_ALG_SHA_256 ((psa_algorithm_t)0x02000009) /** SHA2-384 */ -#define PSA_ALG_SHA_384 ((psa_algorithm_t)0x0100000a) +#define PSA_ALG_SHA_384 ((psa_algorithm_t)0x0200000a) /** SHA2-512 */ -#define PSA_ALG_SHA_512 ((psa_algorithm_t)0x0100000b) +#define PSA_ALG_SHA_512 ((psa_algorithm_t)0x0200000b) /** SHA2-512/224 */ -#define PSA_ALG_SHA_512_224 ((psa_algorithm_t)0x0100000c) +#define PSA_ALG_SHA_512_224 ((psa_algorithm_t)0x0200000c) /** SHA2-512/256 */ -#define PSA_ALG_SHA_512_256 ((psa_algorithm_t)0x0100000d) +#define PSA_ALG_SHA_512_256 ((psa_algorithm_t)0x0200000d) /** SHA3-224 */ -#define PSA_ALG_SHA3_224 ((psa_algorithm_t)0x01000010) +#define PSA_ALG_SHA3_224 ((psa_algorithm_t)0x02000010) /** SHA3-256 */ -#define PSA_ALG_SHA3_256 ((psa_algorithm_t)0x01000011) +#define PSA_ALG_SHA3_256 ((psa_algorithm_t)0x02000011) /** SHA3-384 */ -#define PSA_ALG_SHA3_384 ((psa_algorithm_t)0x01000012) +#define PSA_ALG_SHA3_384 ((psa_algorithm_t)0x02000012) /** SHA3-512 */ -#define PSA_ALG_SHA3_512 ((psa_algorithm_t)0x01000013) +#define PSA_ALG_SHA3_512 ((psa_algorithm_t)0x02000013) /** In a hash-and-sign algorithm policy, allow any hash algorithm. * @@ -769,9 +769,9 @@ * an algorithm built from `PSA_xxx_SIGNATURE` and a specific hash. Each * call to sign or verify a message may use a different hash. * ``` - * psa_sign_hash(handle, PSA_xxx_SIGNATURE(PSA_ALG_SHA_256), ...); - * psa_sign_hash(handle, PSA_xxx_SIGNATURE(PSA_ALG_SHA_512), ...); - * psa_sign_hash(handle, PSA_xxx_SIGNATURE(PSA_ALG_SHA3_256), ...); + * psa_sign_hash(key, PSA_xxx_SIGNATURE(PSA_ALG_SHA_256), ...); + * psa_sign_hash(key, PSA_xxx_SIGNATURE(PSA_ALG_SHA_512), ...); + * psa_sign_hash(key, PSA_xxx_SIGNATURE(PSA_ALG_SHA3_256), ...); * ``` * * This value may not be used to build other algorithms that are @@ -781,10 +781,10 @@ * This value may not be used to build an algorithm specification to * perform an operation. It is only valid to build policies. */ -#define PSA_ALG_ANY_HASH ((psa_algorithm_t)0x010000ff) +#define PSA_ALG_ANY_HASH ((psa_algorithm_t)0x020000ff) #define PSA_ALG_MAC_SUBCATEGORY_MASK ((psa_algorithm_t)0x00c00000) -#define PSA_ALG_HMAC_BASE ((psa_algorithm_t)0x02800000) +#define PSA_ALG_HMAC_BASE ((psa_algorithm_t)0x03800000) /** Macro to build an HMAC algorithm. * * For example, #PSA_ALG_HMAC(#PSA_ALG_SHA_256) is HMAC-SHA-256. @@ -823,8 +823,8 @@ * reach up to 63; the largest MAC is 64 bytes so its trivial truncation * to full length is correctly encoded as 0 and any non-trivial truncation * is correctly encoded as a value between 1 and 63. */ -#define PSA_ALG_MAC_TRUNCATION_MASK ((psa_algorithm_t)0x00003f00) -#define PSA_MAC_TRUNCATION_OFFSET 8 +#define PSA_ALG_MAC_TRUNCATION_MASK ((psa_algorithm_t)0x003f0000) +#define PSA_MAC_TRUNCATION_OFFSET 16 /** Macro to build a truncated MAC algorithm. * @@ -892,15 +892,15 @@ #define PSA_MAC_TRUNCATED_LENGTH(mac_alg) \ (((mac_alg) & PSA_ALG_MAC_TRUNCATION_MASK) >> PSA_MAC_TRUNCATION_OFFSET) -#define PSA_ALG_CIPHER_MAC_BASE ((psa_algorithm_t)0x02c00000) +#define PSA_ALG_CIPHER_MAC_BASE ((psa_algorithm_t)0x03c00000) /** The CBC-MAC construction over a block cipher * * \warning CBC-MAC is insecure in many cases. * A more secure mode, such as #PSA_ALG_CMAC, is recommended. */ -#define PSA_ALG_CBC_MAC ((psa_algorithm_t)0x02c00001) +#define PSA_ALG_CBC_MAC ((psa_algorithm_t)0x03c00100) /** The CMAC construction over a block cipher */ -#define PSA_ALG_CMAC ((psa_algorithm_t)0x02c00002) +#define PSA_ALG_CMAC ((psa_algorithm_t)0x03c00200) /** Whether the specified algorithm is a MAC algorithm based on a block cipher. * @@ -933,21 +933,13 @@ (((alg) & (PSA_ALG_CATEGORY_MASK | PSA_ALG_CIPHER_STREAM_FLAG)) == \ (PSA_ALG_CATEGORY_CIPHER | PSA_ALG_CIPHER_STREAM_FLAG)) -/** The ARC4 stream cipher algorithm. +/** The stream cipher mode of a stream cipher algorithm. + * + * The underlying stream cipher is determined by the key type. + * - To use ChaCha20, use a key type of #PSA_KEY_TYPE_CHACHA20. + * - To use ARC4, use a key type of #PSA_KEY_TYPE_ARC4. */ -#define PSA_ALG_ARC4 ((psa_algorithm_t)0x04800001) - -/** The ChaCha20 stream cipher. - * - * ChaCha20 is defined in RFC 7539. - * - * The nonce size for psa_cipher_set_iv() or psa_cipher_generate_iv() - * must be 12. - * - * The initial block counter is always 0. - * - */ -#define PSA_ALG_CHACHA20 ((psa_algorithm_t)0x04800005) +#define PSA_ALG_STREAM_CIPHER ((psa_algorithm_t)0x04800100) /** The CTR stream cipher mode. * @@ -956,19 +948,19 @@ * For example, to use AES-128-CTR, use this algorithm with * a key of type #PSA_KEY_TYPE_AES and a length of 128 bits (16 bytes). */ -#define PSA_ALG_CTR ((psa_algorithm_t)0x04c00001) +#define PSA_ALG_CTR ((psa_algorithm_t)0x04c01000) /** The CFB stream cipher mode. * * The underlying block cipher is determined by the key type. */ -#define PSA_ALG_CFB ((psa_algorithm_t)0x04c00002) +#define PSA_ALG_CFB ((psa_algorithm_t)0x04c01100) /** The OFB stream cipher mode. * * The underlying block cipher is determined by the key type. */ -#define PSA_ALG_OFB ((psa_algorithm_t)0x04c00003) +#define PSA_ALG_OFB ((psa_algorithm_t)0x04c01200) /** The XTS cipher mode. * @@ -976,7 +968,27 @@ * least one full block of input, but beyond this minimum the input * does not need to be a whole number of blocks. */ -#define PSA_ALG_XTS ((psa_algorithm_t)0x044000ff) +#define PSA_ALG_XTS ((psa_algorithm_t)0x0440ff00) + +/** The Electronic Code Book (ECB) mode of a block cipher, with no padding. + * + * \warning ECB mode does not protect the confidentiality of the encrypted data + * except in extremely narrow circumstances. It is recommended that applications + * only use ECB if they need to construct an operating mode that the + * implementation does not provide. Implementations are encouraged to provide + * the modes that applications need in preference to supporting direct access + * to ECB. + * + * The underlying block cipher is determined by the key type. + * + * This symmetric cipher mode can only be used with messages whose lengths are a + * multiple of the block size of the chosen block cipher. + * + * ECB mode does not accept an initialization vector (IV). When using a + * multi-part cipher operation with this algorithm, psa_cipher_generate_iv() + * and psa_cipher_set_iv() must not be called. + */ +#define PSA_ALG_ECB_NO_PADDING ((psa_algorithm_t)0x04404400) /** The CBC block cipher chaining mode, with no padding. * @@ -985,7 +997,7 @@ * This symmetric cipher mode can only be used with messages whose lengths * are whole number of blocks for the chosen block cipher. */ -#define PSA_ALG_CBC_NO_PADDING ((psa_algorithm_t)0x04600100) +#define PSA_ALG_CBC_NO_PADDING ((psa_algorithm_t)0x04404000) /** The CBC block cipher chaining mode with PKCS#7 padding. * @@ -993,7 +1005,7 @@ * * This is the padding method defined by PKCS#7 (RFC 2315) §10.3. */ -#define PSA_ALG_CBC_PKCS7 ((psa_algorithm_t)0x04600101) +#define PSA_ALG_CBC_PKCS7 ((psa_algorithm_t)0x04404100) #define PSA_ALG_AEAD_FROM_BLOCK_FLAG ((psa_algorithm_t)0x00400000) @@ -1014,13 +1026,13 @@ * * The underlying block cipher is determined by the key type. */ -#define PSA_ALG_CCM ((psa_algorithm_t)0x06401001) +#define PSA_ALG_CCM ((psa_algorithm_t)0x05500100) /** The GCM authenticated encryption algorithm. * * The underlying block cipher is determined by the key type. */ -#define PSA_ALG_GCM ((psa_algorithm_t)0x06401002) +#define PSA_ALG_GCM ((psa_algorithm_t)0x05500200) /** The Chacha20-Poly1305 AEAD algorithm. * @@ -1031,14 +1043,14 @@ * * Implementations must support 16-byte tags and should reject other sizes. */ -#define PSA_ALG_CHACHA20_POLY1305 ((psa_algorithm_t)0x06001005) +#define PSA_ALG_CHACHA20_POLY1305 ((psa_algorithm_t)0x05100500) /* In the encoding of a AEAD algorithm, the bits corresponding to * PSA_ALG_AEAD_TAG_LENGTH_MASK encode the length of the AEAD tag. * The constants for default lengths follow this encoding. */ -#define PSA_ALG_AEAD_TAG_LENGTH_MASK ((psa_algorithm_t)0x00003f00) -#define PSA_AEAD_TAG_LENGTH_OFFSET 8 +#define PSA_ALG_AEAD_TAG_LENGTH_MASK ((psa_algorithm_t)0x003f0000) +#define PSA_AEAD_TAG_LENGTH_OFFSET 16 /** Macro to build a shortened AEAD algorithm. * @@ -1082,7 +1094,7 @@ PSA_ALG_AEAD_WITH_TAG_LENGTH(ref, 0) ? \ ref : -#define PSA_ALG_RSA_PKCS1V15_SIGN_BASE ((psa_algorithm_t)0x10020000) +#define PSA_ALG_RSA_PKCS1V15_SIGN_BASE ((psa_algorithm_t)0x06000200) /** RSA PKCS#1 v1.5 signature with hashing. * * This is the signature scheme defined by RFC 8017 @@ -1110,7 +1122,7 @@ #define PSA_ALG_IS_RSA_PKCS1V15_SIGN(alg) \ (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_PKCS1V15_SIGN_BASE) -#define PSA_ALG_RSA_PSS_BASE ((psa_algorithm_t)0x10030000) +#define PSA_ALG_RSA_PSS_BASE ((psa_algorithm_t)0x06000300) /** RSA PSS signature with hashing. * * This is the signature scheme defined by RFC 8017 @@ -1134,7 +1146,7 @@ #define PSA_ALG_IS_RSA_PSS(alg) \ (((alg) & ~PSA_ALG_HASH_MASK) == PSA_ALG_RSA_PSS_BASE) -#define PSA_ALG_ECDSA_BASE ((psa_algorithm_t)0x10060000) +#define PSA_ALG_ECDSA_BASE ((psa_algorithm_t)0x06000600) /** ECDSA signature with hashing. * * This is the ECDSA signature scheme defined by ANSI X9.62, @@ -1167,7 +1179,7 @@ * the curve size. */ #define PSA_ALG_ECDSA_ANY PSA_ALG_ECDSA_BASE -#define PSA_ALG_DETERMINISTIC_ECDSA_BASE ((psa_algorithm_t)0x10070000) +#define PSA_ALG_DETERMINISTIC_ECDSA_BASE ((psa_algorithm_t)0x06000700) /** Deterministic ECDSA signature with hashing. * * This is the deterministic ECDSA signature scheme defined by RFC 6979. @@ -1192,7 +1204,7 @@ */ #define PSA_ALG_DETERMINISTIC_ECDSA(hash_alg) \ (PSA_ALG_DETERMINISTIC_ECDSA_BASE | ((hash_alg) & PSA_ALG_HASH_MASK)) -#define PSA_ALG_ECDSA_DETERMINISTIC_FLAG ((psa_algorithm_t)0x00010000) +#define PSA_ALG_ECDSA_DETERMINISTIC_FLAG ((psa_algorithm_t)0x00000100) #define PSA_ALG_IS_ECDSA(alg) \ (((alg) & ~PSA_ALG_HASH_MASK & ~PSA_ALG_ECDSA_DETERMINISTIC_FLAG) == \ PSA_ALG_ECDSA_BASE) @@ -1246,9 +1258,9 @@ /** RSA PKCS#1 v1.5 encryption. */ -#define PSA_ALG_RSA_PKCS1V15_CRYPT ((psa_algorithm_t)0x12020000) +#define PSA_ALG_RSA_PKCS1V15_CRYPT ((psa_algorithm_t)0x07000200) -#define PSA_ALG_RSA_OAEP_BASE ((psa_algorithm_t)0x12030000) +#define PSA_ALG_RSA_OAEP_BASE ((psa_algorithm_t)0x07000300) /** RSA OAEP encryption. * * This is the encryption scheme defined by RFC 8017 @@ -1272,7 +1284,7 @@ ((alg) & PSA_ALG_HASH_MASK) | PSA_ALG_CATEGORY_HASH : \ 0) -#define PSA_ALG_HKDF_BASE ((psa_algorithm_t)0x20000100) +#define PSA_ALG_HKDF_BASE ((psa_algorithm_t)0x08000100) /** Macro to build an HKDF algorithm. * * For example, `PSA_ALG_HKDF(PSA_ALG_SHA256)` is HKDF using HMAC-SHA-256. @@ -1311,7 +1323,7 @@ #define PSA_ALG_HKDF_GET_HASH(hkdf_alg) \ (PSA_ALG_CATEGORY_HASH | ((hkdf_alg) & PSA_ALG_HASH_MASK)) -#define PSA_ALG_TLS12_PRF_BASE ((psa_algorithm_t)0x20000200) +#define PSA_ALG_TLS12_PRF_BASE ((psa_algorithm_t)0x08000200) /** Macro to build a TLS-1.2 PRF algorithm. * * TLS 1.2 uses a custom pseudorandom function (PRF) for key schedule, @@ -1354,7 +1366,7 @@ #define PSA_ALG_TLS12_PRF_GET_HASH(hkdf_alg) \ (PSA_ALG_CATEGORY_HASH | ((hkdf_alg) & PSA_ALG_HASH_MASK)) -#define PSA_ALG_TLS12_PSK_TO_MS_BASE ((psa_algorithm_t)0x20000300) +#define PSA_ALG_TLS12_PSK_TO_MS_BASE ((psa_algorithm_t)0x08000300) /** Macro to build a TLS-1.2 PSK-to-MasterSecret algorithm. * * In a pure-PSK handshake in TLS 1.2, the master secret is derived @@ -1400,8 +1412,8 @@ #define PSA_ALG_TLS12_PSK_TO_MS_GET_HASH(hkdf_alg) \ (PSA_ALG_CATEGORY_HASH | ((hkdf_alg) & PSA_ALG_HASH_MASK)) -#define PSA_ALG_KEY_DERIVATION_MASK ((psa_algorithm_t)0x0803ffff) -#define PSA_ALG_KEY_AGREEMENT_MASK ((psa_algorithm_t)0x10fc0000) +#define PSA_ALG_KEY_DERIVATION_MASK ((psa_algorithm_t)0xfe00ffff) +#define PSA_ALG_KEY_AGREEMENT_MASK ((psa_algorithm_t)0xffff0000) /** Macro to build a combined algorithm that chains a key agreement with * a key derivation. @@ -1432,7 +1444,7 @@ * a key derivation function. * Usually, raw key agreement algorithms are constructed directly with * a \c PSA_ALG_xxx macro while non-raw key agreement algorithms are - * constructed with PSA_ALG_KEY_AGREEMENT(). + * constructed with #PSA_ALG_KEY_AGREEMENT(). * * \param alg An algorithm identifier (value of type #psa_algorithm_t). * @@ -1454,7 +1466,7 @@ * It is `ceiling(m / 8)` bytes long where `m` is the size of the prime `p` * in bits. */ -#define PSA_ALG_FFDH ((psa_algorithm_t)0x30100000) +#define PSA_ALG_FFDH ((psa_algorithm_t)0x09010000) /** Whether the specified algorithm is a finite field Diffie-Hellman algorithm. * @@ -1496,7 +1508,7 @@ * in big-endian byte order. * The bit size is `m` for the field `F_{2^m}`. */ -#define PSA_ALG_ECDH ((psa_algorithm_t)0x30200000) +#define PSA_ALG_ECDH ((psa_algorithm_t)0x09020000) /** Whether the specified algorithm is an elliptic curve Diffie-Hellman * algorithm. @@ -1541,7 +1553,7 @@ /** The default lifetime for volatile keys. * - * A volatile key only exists as long as the handle to it is not closed. + * A volatile key only exists as long as the identifier to it is not destroyed. * The key material is guaranteed to be erased on a power reset. * * A key with this lifetime is typically stored in the RAM area of the @@ -1636,16 +1648,105 @@ /** The minimum value for a key identifier chosen by the application. */ -#define PSA_KEY_ID_USER_MIN ((psa_app_key_id_t)0x00000001) +#define PSA_KEY_ID_USER_MIN ((psa_key_id_t)0x00000001) /** The maximum value for a key identifier chosen by the application. */ -#define PSA_KEY_ID_USER_MAX ((psa_app_key_id_t)0x3fffffff) +#define PSA_KEY_ID_USER_MAX ((psa_key_id_t)0x3fffffff) /** The minimum value for a key identifier chosen by the implementation. */ -#define PSA_KEY_ID_VENDOR_MIN ((psa_app_key_id_t)0x40000000) +#define PSA_KEY_ID_VENDOR_MIN ((psa_key_id_t)0x40000000) /** The maximum value for a key identifier chosen by the implementation. */ -#define PSA_KEY_ID_VENDOR_MAX ((psa_app_key_id_t)0x7fffffff) +#define PSA_KEY_ID_VENDOR_MAX ((psa_key_id_t)0x7fffffff) + + +#if !defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + +#define MBEDTLS_SVC_KEY_ID_INIT ( (psa_key_id_t)0 ) +#define MBEDTLS_SVC_KEY_ID_GET_KEY_ID( id ) ( id ) +#define MBEDTLS_SVC_KEY_ID_GET_OWNER_ID( id ) ( 0 ) + +/** Utility to initialize a key identifier at runtime. + * + * \param unused Unused parameter. + * \param key_id Identifier of the key. + */ +static inline mbedtls_svc_key_id_t mbedtls_svc_key_id_make( + unsigned int unused, psa_key_id_t key_id ) +{ + (void)unused; + + return( key_id ); +} + +/** Compare two key identifiers. + * + * \param id1 First key identifier. + * \param id2 Second key identifier. + * + * \return Non-zero if the two key identifier are equal, zero otherwise. + */ +static inline int mbedtls_svc_key_id_equal( mbedtls_svc_key_id_t id1, + mbedtls_svc_key_id_t id2 ) +{ + return( id1 == id2 ); +} + +/** Check whether a key identifier is null. + * + * \param key Key identifier. + * + * \return Non-zero if the key identifier is null, zero otherwise. + */ +static inline int mbedtls_svc_key_id_is_null( mbedtls_svc_key_id_t key ) +{ + return( key == 0 ); +} + +#else /* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ + +#define MBEDTLS_SVC_KEY_ID_INIT ( (mbedtls_svc_key_id_t){ 0, 0 } ) +#define MBEDTLS_SVC_KEY_ID_GET_KEY_ID( id ) ( ( id ).key_id ) +#define MBEDTLS_SVC_KEY_ID_GET_OWNER_ID( id ) ( ( id ).owner ) + +/** Utility to initialize a key identifier at runtime. + * + * \param owner_id Identifier of the key owner. + * \param key_id Identifier of the key. + */ +static inline mbedtls_svc_key_id_t mbedtls_svc_key_id_make( + mbedtls_key_owner_id_t owner_id, psa_key_id_t key_id ) +{ + return( (mbedtls_svc_key_id_t){ .key_id = key_id, + .owner = owner_id } ); +} + +/** Compare two key identifiers. + * + * \param id1 First key identifier. + * \param id2 Second key identifier. + * + * \return Non-zero if the two key identifier are equal, zero otherwise. + */ +static inline int mbedtls_svc_key_id_equal( mbedtls_svc_key_id_t id1, + mbedtls_svc_key_id_t id2 ) +{ + return( ( id1.key_id == id2.key_id ) && + mbedtls_key_owner_id_equal( id1.owner, id2.owner ) ); +} + +/** Check whether a key identifier is null. + * + * \param key Key identifier. + * + * \return Non-zero if the key identifier is null, zero otherwise. + */ +static inline int mbedtls_svc_key_id_is_null( mbedtls_svc_key_id_t key ) +{ + return( ( key.key_id == 0 ) && ( key.owner == 0 ) ); +} + +#endif /* !MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER */ /**@}*/ @@ -1712,7 +1813,7 @@ * * For a key pair, this concerns the private key. */ -#define PSA_KEY_USAGE_SIGN_HASH ((psa_key_usage_t)0x00000400) +#define PSA_KEY_USAGE_SIGN_HASH ((psa_key_usage_t)0x00001000) /** Whether the key may be used to verify a message signature. * @@ -1722,11 +1823,11 @@ * * For a key pair, this concerns the public key. */ -#define PSA_KEY_USAGE_VERIFY_HASH ((psa_key_usage_t)0x00000800) +#define PSA_KEY_USAGE_VERIFY_HASH ((psa_key_usage_t)0x00002000) /** Whether the key may be used to derive other keys. */ -#define PSA_KEY_USAGE_DERIVE ((psa_key_usage_t)0x00001000) +#define PSA_KEY_USAGE_DERIVE ((psa_key_usage_t)0x00004000) /**@}*/ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/crypto_struct.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/crypto_struct.h index 67c53db928..6a018e1f90 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/crypto_struct.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/crypto_struct.h @@ -77,6 +77,16 @@ extern "C" { #include "mbedtls/sha256.h" #include "mbedtls/sha512.h" +typedef struct { + /** Unique ID indicating which driver got assigned to do the + * operation. Since driver contexts are driver-specific, swapping + * drivers halfway through the operation is not supported. + * ID values are auto-generated in psa_driver_wrappers.h */ + unsigned int id; + /** Context structure for the assigned driver, when id is not zero. */ + void* ctx; +} psa_operation_driver_context_t; + struct psa_hash_operation_s { psa_algorithm_t alg; @@ -158,16 +168,18 @@ struct psa_cipher_operation_s unsigned int key_set : 1; unsigned int iv_required : 1; unsigned int iv_set : 1; + unsigned int mbedtls_in_use : 1; /* Indicates mbed TLS is handling the operation. */ uint8_t iv_size; uint8_t block_size; union { unsigned dummy; /* Enable easier initializing of the union. */ mbedtls_cipher_context_t cipher; + psa_operation_driver_context_t driver; } ctx; }; -#define PSA_CIPHER_OPERATION_INIT {0, 0, 0, 0, 0, 0, {0}} +#define PSA_CIPHER_OPERATION_INIT {0, 0, 0, 0, 0, 0, 0, {0}} static inline struct psa_cipher_operation_s psa_cipher_operation_init( void ) { const struct psa_cipher_operation_s v = PSA_CIPHER_OPERATION_INIT; @@ -330,12 +342,12 @@ typedef struct psa_key_type_t type; psa_key_bits_t bits; psa_key_lifetime_t lifetime; - psa_key_id_t id; + mbedtls_svc_key_id_t id; psa_key_policy_t policy; psa_key_attributes_flag_t flags; } psa_core_key_attributes_t; -#define PSA_CORE_KEY_ATTRIBUTES_INIT {PSA_KEY_TYPE_NONE, 0, PSA_KEY_LIFETIME_VOLATILE, PSA_KEY_ID_INIT, PSA_KEY_POLICY_INIT, 0} +#define PSA_CORE_KEY_ATTRIBUTES_INIT {PSA_KEY_TYPE_NONE, 0, PSA_KEY_LIFETIME_VOLATILE, MBEDTLS_SVC_KEY_ID_INIT, PSA_KEY_POLICY_INIT, 0} struct psa_key_attributes_s { @@ -359,29 +371,44 @@ static inline struct psa_key_attributes_s psa_key_attributes_init( void ) return( v ); } -static inline void psa_set_key_id(psa_key_attributes_t *attributes, - psa_key_id_t id) +static inline void psa_set_key_id( psa_key_attributes_t *attributes, + mbedtls_svc_key_id_t key ) { - attributes->core.id = id; - if( attributes->core.lifetime == PSA_KEY_LIFETIME_VOLATILE ) - attributes->core.lifetime = PSA_KEY_LIFETIME_PERSISTENT; + psa_key_lifetime_t lifetime = attributes->core.lifetime; + + attributes->core.id = key; + + if( PSA_KEY_LIFETIME_IS_VOLATILE( lifetime ) ) + { + attributes->core.lifetime = + PSA_KEY_LIFETIME_FROM_PERSISTENCE_AND_LOCATION( + PSA_KEY_LIFETIME_PERSISTENT, + PSA_KEY_LIFETIME_GET_LOCATION( lifetime ) ); + } } -static inline psa_key_id_t psa_get_key_id( +static inline mbedtls_svc_key_id_t psa_get_key_id( const psa_key_attributes_t *attributes) { return( attributes->core.id ); } +#ifdef MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER +static inline void mbedtls_set_key_owner_id( psa_key_attributes_t *attributes, + mbedtls_key_owner_id_t owner ) +{ + attributes->core.id.owner = owner; +} +#endif + static inline void psa_set_key_lifetime(psa_key_attributes_t *attributes, psa_key_lifetime_t lifetime) { attributes->core.lifetime = lifetime; - if( lifetime == PSA_KEY_LIFETIME_VOLATILE ) + if( PSA_KEY_LIFETIME_IS_VOLATILE( lifetime ) ) { -#ifdef MBEDTLS_PSA_CRYPTO_KEY_FILE_ID_ENCODES_OWNER +#ifdef MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER attributes->core.id.key_id = 0; - attributes->core.id.owner = 0; #else attributes->core.id = 0; #endif diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto.c b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto.c index bffddc995b..82b95dc6dd 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto.c +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto.c @@ -22,11 +22,16 @@ #if defined(MBEDTLS_PSA_CRYPTO_C) +#if defined(MBEDTLS_PSA_CRYPTO_CONFIG) +#include "check_crypto_config.h" +#endif + #include "psa_crypto_service_integration.h" #include "psa/crypto.h" #include "psa_crypto_core.h" #include "psa_crypto_invasive.h" +#include "psa_crypto_driver_wrappers.h" #if defined(MBEDTLS_PSA_CRYPTO_SE_C) #include "psa_crypto_se.h" #endif @@ -124,7 +129,7 @@ static psa_global_data_t global_data; if( global_data.initialized == 0 ) \ return( PSA_ERROR_BAD_STATE ); -static psa_status_t mbedtls_to_psa_error( int ret ) +psa_status_t mbedtls_to_psa_error( int ret ) { /* If there's both a high-level code and low-level code, dispatch on * the high-level code. */ @@ -198,7 +203,7 @@ static psa_status_t mbedtls_to_psa_error( int ret ) case MBEDTLS_ERR_CIPHER_INVALID_PADDING: return( PSA_ERROR_INVALID_PADDING ); case MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED: - return( PSA_ERROR_BAD_STATE ); + return( PSA_ERROR_INVALID_ARGUMENT ); case MBEDTLS_ERR_CIPHER_AUTH_FAILED: return( PSA_ERROR_INVALID_SIGNATURE ); case MBEDTLS_ERR_CIPHER_INVALID_CONTEXT: @@ -369,7 +374,15 @@ static inline int psa_key_slot_is_external( const psa_key_slot_t *slot ) } #endif /* MBEDTLS_PSA_CRYPTO_SE_C */ -#if defined(MBEDTLS_ECP_C) +/* For now the MBEDTLS_PSA_ACCEL_ guards are also used here since the + * current test driver in key_management.c is using this function + * when accelerators are used for ECC key pair and public key. + * Once that dependency is resolved these guards can be removed. + */ +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) || \ + defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR) || \ + defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY) mbedtls_ecp_group_id mbedtls_ecc_group_of_psa( psa_ecc_family_t curve, size_t byte_length ) { @@ -437,7 +450,10 @@ mbedtls_ecp_group_id mbedtls_ecc_group_of_psa( psa_ecc_family_t curve, return( MBEDTLS_ECP_DP_NONE ); } } -#endif /* defined(MBEDTLS_ECP_C) */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) || + * defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_KEY_PAIR) || + * defined(MBEDTLS_PSA_ACCEL_KEY_TYPE_ECC_PUBLIC_KEY) */ static psa_status_t validate_unstructured_key_bit_size( psa_key_type_t type, size_t bits ) @@ -446,9 +462,7 @@ static psa_status_t validate_unstructured_key_bit_size( psa_key_type_t type, switch( type ) { case PSA_KEY_TYPE_RAW_DATA: -#if defined(MBEDTLS_MD_C) case PSA_KEY_TYPE_HMAC: -#endif case PSA_KEY_TYPE_DERIVE: break; #if defined(MBEDTLS_AES_C) @@ -490,9 +504,13 @@ static psa_status_t validate_unstructured_key_bit_size( psa_key_type_t type, return( PSA_SUCCESS ); } -#if defined(MBEDTLS_RSA_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) -#if defined(MBEDTLS_PK_PARSE_C) /* Mbed TLS doesn't support non-byte-aligned key sizes (i.e. key sizes * that are not a multiple of 8) well. For example, there is only * mbedtls_rsa_get_len(), which returns a number of bytes, and no @@ -514,7 +532,6 @@ static psa_status_t psa_check_rsa_key_byte_aligned( mbedtls_mpi_free( &n ); return( status ); } -#endif /* MBEDTLS_PK_PARSE_C */ /** Load the contents of a key buffer into an internal RSA representation * @@ -531,7 +548,6 @@ static psa_status_t psa_load_rsa_representation( psa_key_type_t type, size_t data_length, mbedtls_rsa_context **p_rsa ) { -#if defined(MBEDTLS_PK_PARSE_C) psa_status_t status; mbedtls_pk_context ctx; size_t bits; @@ -576,15 +592,18 @@ static psa_status_t psa_load_rsa_representation( psa_key_type_t type, exit: mbedtls_pk_free( &ctx ); return( status ); -#else - (void) data; - (void) data_length; - (void) type; - (void) rsa; - return( PSA_ERROR_NOT_SUPPORTED ); -#endif /* MBEDTLS_PK_PARSE_C */ } +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) + /** Export an RSA key to export representation * * \param[in] type The type of key (public/private) to export @@ -708,9 +727,15 @@ exit: return( PSA_SUCCESS ); } -#endif /* defined(MBEDTLS_RSA_C) */ -#if defined(MBEDTLS_ECP_C) +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ + +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_ECDH) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) /** Load the contents of a key buffer into an internal ECP representation * * \param[in] type The type of key contained in \p data. @@ -738,7 +763,7 @@ static psa_status_t psa_load_ecp_representation( psa_key_type_t type, * - The byte 0x04; * - `x_P` as a `ceiling(m/8)`-byte string, big-endian; * - `y_P` as a `ceiling(m/8)`-byte string, big-endian. - * So its data length is 2m+1 where n is the key size in bits. + * So its data length is 2m+1 where m is the curve size in bits. */ if( ( data_length & 1 ) == 0 ) return( PSA_ERROR_INVALID_ARGUMENT ); @@ -810,7 +835,14 @@ exit: return( status ); } +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_ECDH) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) /** Export an ECP key to export representation * * \param[in] type The type of key (public/private) to export @@ -929,7 +961,8 @@ exit: return( PSA_SUCCESS ); } -#endif /* defined(MBEDTLS_ECP_C) */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) */ /** Return the size of the key in the given slot, in bits. * @@ -968,14 +1001,45 @@ static psa_status_t psa_allocate_buffer_to_slot( psa_key_slot_t *slot, return( PSA_SUCCESS ); } -/** Import key data into a slot. `slot->attr.type` must have been set - * previously. This function assumes that the slot does not contain - * any key material yet. On failure, the slot content is unchanged. */ -psa_status_t psa_import_key_into_slot( psa_key_slot_t *slot, - const uint8_t *data, - size_t data_length ) +psa_status_t psa_copy_key_material_into_slot( psa_key_slot_t *slot, + const uint8_t* data, + size_t data_length ) +{ + psa_status_t status = psa_allocate_buffer_to_slot( slot, + data_length ); + if( status != PSA_SUCCESS ) + return( status ); + + memcpy( slot->data.key.data, data, data_length ); + return( PSA_SUCCESS ); +} + +/** Import key data into a slot. + * + * `slot->type` must have been set previously. + * This function assumes that the slot does not contain any key material yet. + * On failure, the slot content is unchanged. + * + * Persistent storage is not affected. + * + * \param[in,out] slot The key slot to import data into. + * Its `type` field must have previously been set to + * the desired key type. + * It must not contain any key material yet. + * \param[in] data Buffer containing the key material to parse and import. + * \param data_length Size of \p data in bytes. + * + * \retval #PSA_SUCCESS + * \retval #PSA_ERROR_INVALID_ARGUMENT + * \retval #PSA_ERROR_NOT_SUPPORTED + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + */ +static psa_status_t psa_import_key_into_slot( psa_key_slot_t *slot, + const uint8_t *data, + size_t data_length ) { psa_status_t status = PSA_SUCCESS; + size_t bit_size; /* zero-length keys are never supported. */ if( data_length == 0 ) @@ -983,7 +1047,7 @@ psa_status_t psa_import_key_into_slot( psa_key_slot_t *slot, if( key_type_is_raw_bytes( slot->attr.type ) ) { - size_t bit_size = PSA_BYTES_TO_BITS( data_length ); + bit_size = PSA_BYTES_TO_BITS( data_length ); /* Ensure that the bytes-to-bits conversion hasn't overflown. */ if( data_length > SIZE_MAX / 8 ) @@ -999,47 +1063,69 @@ psa_status_t psa_import_key_into_slot( psa_key_slot_t *slot, return( status ); /* Allocate memory for the key */ - status = psa_allocate_buffer_to_slot( slot, data_length ); + status = psa_copy_key_material_into_slot( slot, data, data_length ); if( status != PSA_SUCCESS ) return( status ); - /* copy key into allocated buffer */ - memcpy( slot->data.key.data, data, data_length ); - /* Write the actual key size to the slot. * psa_start_key_creation() wrote the size declared by the * caller, which may be 0 (meaning unspecified) or wrong. */ slot->attr.bits = (psa_key_bits_t) bit_size; + + return( PSA_SUCCESS ); } - else if( PSA_KEY_TYPE_IS_ECC( slot->attr.type ) ) + else if( PSA_KEY_TYPE_IS_ASYMMETRIC( slot->attr.type ) ) { -#if defined(MBEDTLS_ECP_C) - status = psa_import_ecp_key( slot, - data, data_length ); -#else - /* No drivers have been implemented yet, so without mbed TLS backing - * there's no way to do ECP with the current library. */ + /* Try validation through accelerators first. */ + bit_size = slot->attr.bits; + psa_key_attributes_t attributes = { + .core = slot->attr + }; + status = psa_driver_wrapper_validate_key( &attributes, + data, + data_length, + &bit_size ); + if( status == PSA_SUCCESS ) + { + /* Key has been validated successfully by an accelerator. + * Copy key material into slot. */ + status = psa_copy_key_material_into_slot( slot, data, data_length ); + if( status != PSA_SUCCESS ) + return( status ); + + slot->attr.bits = (psa_key_bits_t) bit_size; + return( PSA_SUCCESS ); + } + else if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); + + /* Key format is not supported by any accelerator, try software fallback + * if present. */ +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) + if( PSA_KEY_TYPE_IS_ECC( slot->attr.type ) ) + { + return( psa_import_ecp_key( slot, data, data_length ) ); + } +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) */ +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) + if( PSA_KEY_TYPE_IS_RSA( slot->attr.type ) ) + { + return( psa_import_rsa_key( slot, data, data_length ) ); + } +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ + + /* Fell through the fallback as well, so have nothing else to try. */ return( PSA_ERROR_NOT_SUPPORTED ); -#endif /* defined(MBEDTLS_ECP_C) */ - } - else if( PSA_KEY_TYPE_IS_RSA( slot->attr.type ) ) - { -#if defined(MBEDTLS_RSA_C) - status = psa_import_rsa_key( slot, - data, data_length ); -#else - /* No drivers have been implemented yet, so without mbed TLS backing - * there's no way to do RSA with the current library. */ - status = PSA_ERROR_NOT_SUPPORTED; -#endif /* defined(MBEDTLS_RSA_C) */ } else { /* Unknown key type */ return( PSA_ERROR_NOT_SUPPORTED ); } - - return( status ); } /** Calculate the intersection of two algorithm usage policies. @@ -1083,6 +1169,15 @@ static int psa_key_algorithm_permits( psa_algorithm_t policy_alg, return( ( policy_alg & ~PSA_ALG_HASH_MASK ) == ( requested_alg & ~PSA_ALG_HASH_MASK ) ); } + /* If policy_alg is a generic key agreement operation, then using it for + * a key derivation with that key agreement should also be allowed. This + * behaviour is expected to be defined in a future specification version. */ + if( PSA_ALG_IS_RAW_KEY_AGREEMENT( policy_alg ) && + PSA_ALG_IS_KEY_AGREEMENT( requested_alg ) ) + { + return( PSA_ALG_KEY_AGREEMENT_GET_BASE( requested_alg ) == + policy_alg ); + } /* If it isn't permitted, it's forbidden. */ return( 0 ); } @@ -1128,22 +1223,31 @@ static psa_status_t psa_restrict_key_policy( return( PSA_SUCCESS ); } -/** Retrieve a slot which must contain a key. The key must have allow all the - * usage flags set in \p usage. If \p alg is nonzero, the key must allow - * operations with this algorithm. */ -static psa_status_t psa_get_key_from_slot( psa_key_handle_t handle, - psa_key_slot_t **p_slot, - psa_key_usage_t usage, - psa_algorithm_t alg ) +/** Get the description of a key given its identifier and policy constraints + * and lock it. + * + * The key must have allow all the usage flags set in \p usage. If \p alg is + * nonzero, the key must allow operations with this algorithm. + * + * In case of a persistent key, the function loads the description of the key + * into a key slot if not already done. + * + * On success, the returned key slot is locked. It is the responsibility of + * the caller to unlock the key slot when it does not access it anymore. + */ +static psa_status_t psa_get_and_lock_key_slot_with_policy( + mbedtls_svc_key_id_t key, + psa_key_slot_t **p_slot, + psa_key_usage_t usage, + psa_algorithm_t alg ) { - psa_status_t status; - psa_key_slot_t *slot = NULL; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot; - *p_slot = NULL; - - status = psa_get_key_slot( handle, &slot ); + status = psa_get_and_lock_key_slot( key, p_slot ); if( status != PSA_SUCCESS ) return( status ); + slot = *p_slot; /* Enforce that usage policy for the key slot contains all the flags * required by the usage parameter. There is one exception: public @@ -1151,45 +1255,61 @@ static psa_status_t psa_get_key_from_slot( psa_key_handle_t handle, * if they had the export flag. */ if( PSA_KEY_TYPE_IS_PUBLIC_KEY( slot->attr.type ) ) usage &= ~PSA_KEY_USAGE_EXPORT; + + status = PSA_ERROR_NOT_PERMITTED; if( ( slot->attr.policy.usage & usage ) != usage ) - return( PSA_ERROR_NOT_PERMITTED ); + goto error; /* Enforce that the usage policy permits the requested algortihm. */ if( alg != 0 && ! psa_key_policy_permits( &slot->attr.policy, alg ) ) - return( PSA_ERROR_NOT_PERMITTED ); + goto error; - *p_slot = slot; return( PSA_SUCCESS ); + +error: + *p_slot = NULL; + psa_unlock_key_slot( slot ); + + return( status ); } -/** Retrieve a slot which must contain a transparent key. +/** Get a key slot containing a transparent key and lock it. * * A transparent key is a key for which the key material is directly * available, as opposed to a key in a secure element. * - * This is a temporary function to use instead of psa_get_key_from_slot() - * until secure element support is fully implemented. + * This is a temporary function to use instead of + * psa_get_and_lock_key_slot_with_policy() until secure element support is + * fully implemented. + * + * On success, the returned key slot is locked. It is the responsibility of the + * caller to unlock the key slot when it does not access it anymore. */ #if defined(MBEDTLS_PSA_CRYPTO_SE_C) -static psa_status_t psa_get_transparent_key( psa_key_handle_t handle, - psa_key_slot_t **p_slot, - psa_key_usage_t usage, - psa_algorithm_t alg ) +static psa_status_t psa_get_and_lock_transparent_key_slot_with_policy( + mbedtls_svc_key_id_t key, + psa_key_slot_t **p_slot, + psa_key_usage_t usage, + psa_algorithm_t alg ) { - psa_status_t status = psa_get_key_from_slot( handle, p_slot, usage, alg ); + psa_status_t status = psa_get_and_lock_key_slot_with_policy( key, p_slot, + usage, alg ); if( status != PSA_SUCCESS ) return( status ); + if( psa_key_slot_is_external( *p_slot ) ) { + psa_unlock_key_slot( *p_slot ); *p_slot = NULL; return( PSA_ERROR_NOT_SUPPORTED ); } + return( PSA_SUCCESS ); } #else /* MBEDTLS_PSA_CRYPTO_SE_C */ /* With no secure element support, all keys are transparent. */ -#define psa_get_transparent_key( handle, p_slot, usage, alg ) \ - psa_get_key_from_slot( handle, p_slot, usage, alg ) +#define psa_get_and_lock_transparent_key_slot_with_policy( key, p_slot, usage, alg ) \ + psa_get_and_lock_key_slot_with_policy( key, p_slot, usage, alg ) #endif /* MBEDTLS_PSA_CRYPTO_SE_C */ /** Wipe key data from a slot. Preserve metadata such as the policy. */ @@ -1220,6 +1340,22 @@ static psa_status_t psa_remove_key_data_from_memory( psa_key_slot_t *slot ) psa_status_t psa_wipe_key_slot( psa_key_slot_t *slot ) { psa_status_t status = psa_remove_key_data_from_memory( slot ); + + /* + * As the return error code may not be handled in case of multiple errors, + * do our best to report an unexpected lock counter: if available + * call MBEDTLS_PARAM_FAILED that may terminate execution (if called as + * part of the execution of a test suite this will stop the test suite + * execution). + */ + if( slot->lock_count != 1 ) + { +#ifdef MBEDTLS_CHECK_PARAMS + MBEDTLS_PARAM_FAILED( slot->lock_count == 1 ); +#endif + status = PSA_ERROR_CORRUPTION_DETECTED; + } + /* Multipart operations may still be using the key. This is safe * because all multipart operation objects are independent from * the key slot: if they need to access the key after the setup @@ -1232,7 +1368,7 @@ psa_status_t psa_wipe_key_slot( psa_key_slot_t *slot ) return( status ); } -psa_status_t psa_destroy_key( psa_key_handle_t handle ) +psa_status_t psa_destroy_key( mbedtls_svc_key_id_t key ) { psa_key_slot_t *slot; psa_status_t status; /* status of the last operation */ @@ -1241,13 +1377,33 @@ psa_status_t psa_destroy_key( psa_key_handle_t handle ) psa_se_drv_table_entry_t *driver; #endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - if( handle == 0 ) + if( mbedtls_svc_key_id_is_null( key ) ) return( PSA_SUCCESS ); - status = psa_get_key_slot( handle, &slot ); + /* + * Get the description of the key in a key slot. In case of a persistent + * key, this will load the key description from persistent memory if not + * done yet. We cannot avoid this loading as without it we don't know if + * the key is operated by an SE or not and this information is needed by + * the current implementation. + */ + status = psa_get_and_lock_key_slot( key, &slot ); if( status != PSA_SUCCESS ) return( status ); + /* + * If the key slot containing the key description is under access by the + * library (apart from the present access), the key cannot be destroyed + * yet. For the time being, just return in error. Eventually (to be + * implemented), the key should be destroyed when all accesses have + * stopped. + */ + if( slot->lock_count > 1 ) + { + psa_unlock_key_slot( slot ); + return( PSA_ERROR_GENERIC_ERROR ); + } + #if defined(MBEDTLS_PSA_CRYPTO_SE_C) driver = psa_get_se_driver_entry( slot->attr.lifetime ); if( driver != NULL ) @@ -1283,7 +1439,7 @@ psa_status_t psa_destroy_key( psa_key_handle_t handle ) #endif /* MBEDTLS_PSA_CRYPTO_SE_C */ #if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) - if( slot->attr.lifetime != PSA_KEY_LIFETIME_VOLATILE ) + if( ! PSA_KEY_LIFETIME_IS_VOLATILE( slot->attr.lifetime ) ) { status = psa_destroy_persistent_key( slot->attr.id ); if( overall_status == PSA_SUCCESS ) @@ -1367,7 +1523,8 @@ psa_status_t psa_get_key_domain_parameters( return( PSA_SUCCESS ); } -#if defined(MBEDTLS_RSA_C) +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) static psa_status_t psa_get_rsa_public_exponent( const mbedtls_rsa_context *rsa, psa_key_attributes_t *attributes ) @@ -1407,19 +1564,21 @@ exit: mbedtls_free( buffer ); return( mbedtls_to_psa_error( ret ) ); } -#endif /* MBEDTLS_RSA_C */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ /** Retrieve all the publicly-accessible attributes of a key. */ -psa_status_t psa_get_key_attributes( psa_key_handle_t handle, +psa_status_t psa_get_key_attributes( mbedtls_svc_key_id_t key, psa_key_attributes_t *attributes ) { + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; psa_key_slot_t *slot; - psa_status_t status; psa_reset_key_attributes( attributes ); - status = psa_get_key_from_slot( handle, &slot, 0, 0 ); + status = psa_get_and_lock_key_slot_with_policy( key, &slot, 0, 0 ); if( status != PSA_SUCCESS ) return( status ); @@ -1434,7 +1593,8 @@ psa_status_t psa_get_key_attributes( psa_key_handle_t handle, switch( slot->attr.type ) { -#if defined(MBEDTLS_RSA_C) +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) case PSA_KEY_TYPE_RSA_KEY_PAIR: case PSA_KEY_TYPE_RSA_PUBLIC_KEY: #if defined(MBEDTLS_PSA_CRYPTO_SE_C) @@ -1461,7 +1621,8 @@ psa_status_t psa_get_key_attributes( psa_key_handle_t handle, mbedtls_free( rsa ); } break; -#endif /* MBEDTLS_RSA_C */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ default: /* Nothing else to do. */ break; @@ -1469,7 +1630,10 @@ psa_status_t psa_get_key_attributes( psa_key_handle_t handle, if( status != PSA_SUCCESS ) psa_reset_key_attributes( attributes ); - return( status ); + + unlock_status = psa_unlock_key_slot( slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); } #if defined(MBEDTLS_PSA_CRYPTO_SE_C) @@ -1557,13 +1721,24 @@ static psa_status_t psa_internal_export_key( const psa_key_slot_t *slot, /* Exporting private -> private */ return( psa_internal_export_key_buffer( slot, data, data_size, data_length ) ); } + /* Need to export the public part of a private key, - * so conversion is needed */ + * so conversion is needed. Try the accelerators first. */ + psa_status_t status = psa_driver_wrapper_export_public_key( slot, + data, + data_size, + data_length ); + + if( status != PSA_ERROR_NOT_SUPPORTED || + psa_key_lifetime_is_external( slot->attr.lifetime ) ) + return( status ); + if( PSA_KEY_TYPE_IS_RSA( slot->attr.type ) ) { -#if defined(MBEDTLS_RSA_C) +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) mbedtls_rsa_context *rsa = NULL; - psa_status_t status = psa_load_rsa_representation( + status = psa_load_rsa_representation( slot->attr.type, slot->data.key.data, slot->data.key.bytes, @@ -1584,13 +1759,15 @@ static psa_status_t psa_internal_export_key( const psa_key_slot_t *slot, #else /* We don't know how to convert a private RSA key to public. */ return( PSA_ERROR_NOT_SUPPORTED ); -#endif +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ } else { -#if defined(MBEDTLS_ECP_C) +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) mbedtls_ecp_keypair *ecp = NULL; - psa_status_t status = psa_load_ecp_representation( + status = psa_load_ecp_representation( slot->attr.type, slot->data.key.data, slot->data.key.bytes, @@ -1612,7 +1789,8 @@ static psa_status_t psa_internal_export_key( const psa_key_slot_t *slot, #else /* We don't know how to convert a private ECC key to public */ return( PSA_ERROR_NOT_SUPPORTED ); -#endif +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_PUBLIC_KEY) */ } } else @@ -1624,13 +1802,14 @@ static psa_status_t psa_internal_export_key( const psa_key_slot_t *slot, } } -psa_status_t psa_export_key( psa_key_handle_t handle, +psa_status_t psa_export_key( mbedtls_svc_key_id_t key, uint8_t *data, size_t data_size, size_t *data_length ) { + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; psa_key_slot_t *slot; - psa_status_t status; /* Set the key to empty now, so that even when there are errors, we always * set data_length to a value between 0 and data_size. On error, setting @@ -1639,22 +1818,28 @@ psa_status_t psa_export_key( psa_key_handle_t handle, *data_length = 0; /* Export requires the EXPORT flag. There is an exception for public keys, - * which don't require any flag, but psa_get_key_from_slot takes - * care of this. */ - status = psa_get_key_from_slot( handle, &slot, PSA_KEY_USAGE_EXPORT, 0 ); + * which don't require any flag, but + * psa_get_and_lock_key_slot_with_policy() takes care of this. + */ + status = psa_get_and_lock_key_slot_with_policy( key, &slot, + PSA_KEY_USAGE_EXPORT, 0 ); if( status != PSA_SUCCESS ) return( status ); - return( psa_internal_export_key( slot, data, data_size, - data_length, 0 ) ); + + status = psa_internal_export_key( slot, data, data_size, data_length, 0 ); + unlock_status = psa_unlock_key_slot( slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); } -psa_status_t psa_export_public_key( psa_key_handle_t handle, +psa_status_t psa_export_public_key( mbedtls_svc_key_id_t key, uint8_t *data, size_t data_size, size_t *data_length ) { + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; psa_key_slot_t *slot; - psa_status_t status; /* Set the key to empty now, so that even when there are errors, we always * set data_length to a value between 0 and data_size. On error, setting @@ -1663,11 +1848,14 @@ psa_status_t psa_export_public_key( psa_key_handle_t handle, *data_length = 0; /* Exporting a public key doesn't require a usage flag. */ - status = psa_get_key_from_slot( handle, &slot, 0, 0 ); + status = psa_get_and_lock_key_slot_with_policy( key, &slot, 0, 0 ); if( status != PSA_SUCCESS ) return( status ); - return( psa_internal_export_key( slot, data, data_size, - data_length, 1 ) ); + + status = psa_internal_export_key( slot, data, data_size, data_length, 1 ); + unlock_status = psa_unlock_key_slot( slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); } #if defined(static_assert) @@ -1717,17 +1905,29 @@ static psa_status_t psa_validate_key_attributes( psa_se_drv_table_entry_t **p_drv ) { psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + psa_key_lifetime_t lifetime = psa_get_key_lifetime( attributes ); + mbedtls_svc_key_id_t key = psa_get_key_id( attributes ); - status = psa_validate_key_location( psa_get_key_lifetime( attributes ), - p_drv ); + status = psa_validate_key_location( lifetime, p_drv ); if( status != PSA_SUCCESS ) return( status ); - status = psa_validate_key_persistence( psa_get_key_lifetime( attributes ), - psa_get_key_id( attributes ) ); + status = psa_validate_key_persistence( lifetime ); if( status != PSA_SUCCESS ) return( status ); + if ( PSA_KEY_LIFETIME_IS_VOLATILE( lifetime ) ) + { + if( MBEDTLS_SVC_KEY_ID_GET_KEY_ID( key ) != 0 ) + return( PSA_ERROR_INVALID_ARGUMENT ); + } + else + { + status = psa_validate_key_id( psa_get_key_id( attributes ), 0 ); + if( status != PSA_SUCCESS ) + return( status ); + } + status = psa_validate_key_policy( &attributes->core.policy ); if( status != PSA_SUCCESS ) return( status ); @@ -1755,15 +1955,18 @@ static psa_status_t psa_validate_key_attributes( * * This function is intended to be used as follows: * -# Call psa_start_key_creation() to allocate a key slot, prepare - * it with the specified attributes, and assign it a handle. + * it with the specified attributes, and in case of a volatile key assign it + * a volatile key identifier. * -# Populate the slot with the key material. * -# Call psa_finish_key_creation() to finalize the creation of the slot. * In case of failure at any step, stop the sequence and call * psa_fail_key_creation(). * + * On success, the key slot is locked. It is the responsibility of the caller + * to unlock the key slot when it does not access it anymore. + * * \param method An identification of the calling function. * \param[in] attributes Key attributes for the new key. - * \param[out] handle On success, a handle for the allocated slot. * \param[out] p_slot On success, a pointer to the prepared slot. * \param[out] p_drv On any return, the driver for the key, if any. * NULL for a transparent key. @@ -1776,11 +1979,11 @@ static psa_status_t psa_validate_key_attributes( static psa_status_t psa_start_key_creation( psa_key_creation_method_t method, const psa_key_attributes_t *attributes, - psa_key_handle_t *handle, psa_key_slot_t **p_slot, psa_se_drv_table_entry_t **p_drv ) { psa_status_t status; + psa_key_id_t volatile_key_id; psa_key_slot_t *slot; (void) method; @@ -1790,7 +1993,7 @@ static psa_status_t psa_start_key_creation( if( status != PSA_SUCCESS ) return( status ); - status = psa_get_empty_key_slot( handle, p_slot ); + status = psa_get_empty_key_slot( &volatile_key_id, p_slot ); if( status != PSA_SUCCESS ) return( status ); slot = *p_slot; @@ -1799,9 +2002,19 @@ static psa_status_t psa_start_key_creation( * creation mechanism to verify that this information is correct. * It's automatically correct for mechanisms that use the bit-size as * an input (generate, device) but not for those where the bit-size - * is optional (import, copy). */ + * is optional (import, copy). In case of a volatile key, assign it the + * volatile key identifier associated to the slot returned to contain its + * definition. */ slot->attr = attributes->core; + if( PSA_KEY_LIFETIME_IS_VOLATILE( slot->attr.lifetime ) ) + { +#if !defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) + slot->attr.id = volatile_key_id; +#else + slot->attr.id.key_id = volatile_key_id; +#endif + } /* Erase external-only flags from the internal copy. To access * external-only flags, query `attributes`. Thanks to the check @@ -1857,7 +2070,7 @@ static psa_status_t psa_start_key_creation( } #endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - return( status ); + return( PSA_SUCCESS ); } /** Finalize the creation of a key once its key material has been set. @@ -1868,18 +2081,25 @@ static psa_status_t psa_start_key_creation( * See the documentation of psa_start_key_creation() for the intended use * of this function. * + * If the finalization succeeds, the function unlocks the key slot (it was + * locked by psa_start_key_creation()) and the key slot cannot be accessed + * anymore as part of the key creation process. + * * \param[in,out] slot Pointer to the slot with key material. * \param[in] driver The secure element driver for the key, * or NULL for a transparent key. + * \param[out] key On success, identifier of the key. Note that the + * key identifier is also stored in the key slot. * * \retval #PSA_SUCCESS - * The key was successfully created. The handle is now valid. + * The key was successfully created. * \return If this function fails, the key slot is an invalid state. * You must call psa_fail_key_creation() to wipe and free the slot. */ static psa_status_t psa_finish_key_creation( psa_key_slot_t *slot, - psa_se_drv_table_entry_t *driver ) + psa_se_drv_table_entry_t *driver, + mbedtls_svc_key_id_t *key) { psa_status_t status = PSA_SUCCESS; (void) slot; @@ -1896,13 +2116,9 @@ static psa_status_t psa_finish_key_creation( static_assert( sizeof( slot->data.se.slot_number ) == sizeof( data.slot_number ), "Slot number size does not match psa_se_key_data_storage_t" ); - static_assert( sizeof( slot->attr.bits ) == sizeof( data.bits ), - "Bit-size size does not match psa_se_key_data_storage_t" ); #endif memcpy( &data.slot_number, &slot->data.se.slot_number, sizeof( slot->data.se.slot_number ) ); - memcpy( &data.bits, &slot->attr.bits, - sizeof( slot->attr.bits ) ); status = psa_save_persistent_key( &slot->attr, (uint8_t*) &data, sizeof( data ) ); @@ -1910,22 +2126,11 @@ static psa_status_t psa_finish_key_creation( else #endif /* MBEDTLS_PSA_CRYPTO_SE_C */ { - size_t buffer_size = - PSA_KEY_EXPORT_MAX_SIZE( slot->attr.type, - slot->attr.bits ); - uint8_t *buffer = mbedtls_calloc( 1, buffer_size ); - size_t length = 0; - if( buffer == NULL ) - return( PSA_ERROR_INSUFFICIENT_MEMORY ); - status = psa_internal_export_key( slot, - buffer, buffer_size, &length, - 0 ); - if( status == PSA_SUCCESS ) - status = psa_save_persistent_key( &slot->attr, - buffer, length ); - - mbedtls_platform_zeroize( buffer, buffer_size ); - mbedtls_free( buffer ); + /* Key material is saved in export representation in the slot, so + * just pass the slot buffer for storage. */ + status = psa_save_persistent_key( &slot->attr, + slot->data.key.data, + slot->data.key.bytes ); } } #endif /* defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) */ @@ -1946,11 +2151,17 @@ static psa_status_t psa_finish_key_creation( return( status ); } status = psa_crypto_stop_transaction( ); - if( status != PSA_SUCCESS ) - return( status ); } #endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + if( status == PSA_SUCCESS ) + { + *key = slot->attr.id; + status = psa_unlock_key_slot( slot ); + if( status != PSA_SUCCESS ) + *key = MBEDTLS_SVC_KEY_ID_INIT; + } + return( status ); } @@ -2015,7 +2226,8 @@ static psa_status_t psa_validate_optional_attributes( if( attributes->domain_parameters_size != 0 ) { -#if defined(MBEDTLS_RSA_C) +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || \ + defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) if( PSA_KEY_TYPE_IS_RSA( slot->attr.type ) ) { mbedtls_rsa_context *rsa = NULL; @@ -2052,7 +2264,8 @@ static psa_status_t psa_validate_optional_attributes( return( mbedtls_to_psa_error( ret ) ); } else -#endif +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) || + * defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_PUBLIC_KEY) */ { return( PSA_ERROR_INVALID_ARGUMENT ); } @@ -2070,12 +2283,14 @@ static psa_status_t psa_validate_optional_attributes( psa_status_t psa_import_key( const psa_key_attributes_t *attributes, const uint8_t *data, size_t data_length, - psa_key_handle_t *handle ) + mbedtls_svc_key_id_t *key ) { psa_status_t status; psa_key_slot_t *slot = NULL; psa_se_drv_table_entry_t *driver = NULL; + *key = MBEDTLS_SVC_KEY_ID_INIT; + /* Reject zero-length symmetric keys (including raw data key objects). * This also rejects any key which might be encoded as an empty string, * which is never valid. */ @@ -2083,7 +2298,7 @@ psa_status_t psa_import_key( const psa_key_attributes_t *attributes, return( PSA_ERROR_INVALID_ARGUMENT ); status = psa_start_key_creation( PSA_KEY_CREATION_IMPORT, attributes, - handle, &slot, &driver ); + &slot, &driver ); if( status != PSA_SUCCESS ) goto exit; @@ -2124,13 +2339,11 @@ psa_status_t psa_import_key( const psa_key_attributes_t *attributes, if( status != PSA_SUCCESS ) goto exit; - status = psa_finish_key_creation( slot, driver ); + status = psa_finish_key_creation( slot, driver, key ); exit: if( status != PSA_SUCCESS ) - { psa_fail_key_creation( slot, driver ); - *handle = 0; - } + return( status ); } @@ -2141,7 +2354,7 @@ psa_status_t mbedtls_psa_register_se_key( psa_status_t status; psa_key_slot_t *slot = NULL; psa_se_drv_table_entry_t *driver = NULL; - psa_key_handle_t handle = 0; + mbedtls_svc_key_id_t key = MBEDTLS_SVC_KEY_ID_INIT; /* Leaving attributes unspecified is not currently supported. * It could make sense to query the key type and size from the @@ -2153,19 +2366,18 @@ psa_status_t mbedtls_psa_register_se_key( return( PSA_ERROR_NOT_SUPPORTED ); status = psa_start_key_creation( PSA_KEY_CREATION_REGISTER, attributes, - &handle, &slot, &driver ); + &slot, &driver ); if( status != PSA_SUCCESS ) goto exit; - status = psa_finish_key_creation( slot, driver ); + status = psa_finish_key_creation( slot, driver, &key ); exit: if( status != PSA_SUCCESS ) - { psa_fail_key_creation( slot, driver ); - } + /* Registration doesn't keep the key in RAM. */ - psa_close_key( handle ); + psa_close_key( key ); return( status ); } #endif /* MBEDTLS_PSA_CRYPTO_SE_C */ @@ -2173,40 +2385,33 @@ exit: static psa_status_t psa_copy_key_material( const psa_key_slot_t *source, psa_key_slot_t *target ) { - psa_status_t status; - uint8_t *buffer = NULL; - size_t buffer_size = 0; - size_t length; - - buffer_size = PSA_KEY_EXPORT_MAX_SIZE( source->attr.type, - psa_get_key_slot_bits( source ) ); - buffer = mbedtls_calloc( 1, buffer_size ); - if( buffer == NULL ) - return( PSA_ERROR_INSUFFICIENT_MEMORY ); - status = psa_internal_export_key( source, buffer, buffer_size, &length, 0 ); + psa_status_t status = psa_copy_key_material_into_slot( target, + source->data.key.data, + source->data.key.bytes ); if( status != PSA_SUCCESS ) - goto exit; - target->attr.type = source->attr.type; - status = psa_import_key_into_slot( target, buffer, length ); + return( status ); -exit: - mbedtls_platform_zeroize( buffer, buffer_size ); - mbedtls_free( buffer ); - return( status ); + target->attr.type = source->attr.type; + target->attr.bits = source->attr.bits; + + return( PSA_SUCCESS ); } -psa_status_t psa_copy_key( psa_key_handle_t source_handle, +psa_status_t psa_copy_key( mbedtls_svc_key_id_t source_key, const psa_key_attributes_t *specified_attributes, - psa_key_handle_t *target_handle ) + mbedtls_svc_key_id_t *target_key ) { - psa_status_t status; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; psa_key_slot_t *source_slot = NULL; psa_key_slot_t *target_slot = NULL; psa_key_attributes_t actual_attributes = *specified_attributes; psa_se_drv_table_entry_t *driver = NULL; - status = psa_get_transparent_key( source_handle, &source_slot, - PSA_KEY_USAGE_COPY, 0 ); + *target_key = MBEDTLS_SVC_KEY_ID_INIT; + + status = psa_get_and_lock_transparent_key_slot_with_policy( + source_key, &source_slot, PSA_KEY_USAGE_COPY, 0 ); if( status != PSA_SUCCESS ) goto exit; @@ -2220,9 +2425,8 @@ psa_status_t psa_copy_key( psa_key_handle_t source_handle, if( status != PSA_SUCCESS ) goto exit; - status = psa_start_key_creation( PSA_KEY_CREATION_COPY, - &actual_attributes, - target_handle, &target_slot, &driver ); + status = psa_start_key_creation( PSA_KEY_CREATION_COPY, &actual_attributes, + &target_slot, &driver ); if( status != PSA_SUCCESS ) goto exit; @@ -2239,14 +2443,14 @@ psa_status_t psa_copy_key( psa_key_handle_t source_handle, if( status != PSA_SUCCESS ) goto exit; - status = psa_finish_key_creation( target_slot, driver ); + status = psa_finish_key_creation( target_slot, driver, target_key ); exit: if( status != PSA_SUCCESS ) - { psa_fail_key_creation( target_slot, driver ); - *target_handle = 0; - } - return( status ); + + unlock_status = psa_unlock_key_slot( source_slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); } @@ -2255,42 +2459,47 @@ exit: /* Message digests */ /****************************************************************/ -#if defined(MBEDTLS_RSA_C) || defined(MBEDTLS_ECDSA_DETERMINISTIC) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) static const mbedtls_md_info_t *mbedtls_md_info_from_psa( psa_algorithm_t alg ) { switch( alg ) { -#if defined(MBEDTLS_MD2_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD2) case PSA_ALG_MD2: return( &mbedtls_md2_info ); #endif -#if defined(MBEDTLS_MD4_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD4) case PSA_ALG_MD4: return( &mbedtls_md4_info ); #endif -#if defined(MBEDTLS_MD5_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) case PSA_ALG_MD5: return( &mbedtls_md5_info ); #endif -#if defined(MBEDTLS_RIPEMD160_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) case PSA_ALG_RIPEMD160: return( &mbedtls_ripemd160_info ); #endif -#if defined(MBEDTLS_SHA1_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) case PSA_ALG_SHA_1: return( &mbedtls_sha1_info ); #endif -#if defined(MBEDTLS_SHA256_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) case PSA_ALG_SHA_224: return( &mbedtls_sha224_info ); +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) case PSA_ALG_SHA_256: return( &mbedtls_sha256_info ); #endif -#if defined(MBEDTLS_SHA512_C) -#if !defined(MBEDTLS_SHA512_NO_SHA384) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) case PSA_ALG_SHA_384: return( &mbedtls_sha384_info ); #endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) case PSA_ALG_SHA_512: return( &mbedtls_sha512_info ); #endif @@ -2298,7 +2507,10 @@ static const mbedtls_md_info_t *mbedtls_md_info_from_psa( psa_algorithm_t alg ) return( NULL ); } } -#endif +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ psa_status_t psa_hash_abort( psa_hash_operation_t *operation ) { @@ -2309,41 +2521,47 @@ psa_status_t psa_hash_abort( psa_hash_operation_t *operation ) * in use. It's ok to call abort on such an object, and there's * nothing to do. */ break; -#if defined(MBEDTLS_MD2_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD2) case PSA_ALG_MD2: mbedtls_md2_free( &operation->ctx.md2 ); break; #endif -#if defined(MBEDTLS_MD4_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD4) case PSA_ALG_MD4: mbedtls_md4_free( &operation->ctx.md4 ); break; #endif -#if defined(MBEDTLS_MD5_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) case PSA_ALG_MD5: mbedtls_md5_free( &operation->ctx.md5 ); break; #endif -#if defined(MBEDTLS_RIPEMD160_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) case PSA_ALG_RIPEMD160: mbedtls_ripemd160_free( &operation->ctx.ripemd160 ); break; #endif -#if defined(MBEDTLS_SHA1_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) case PSA_ALG_SHA_1: mbedtls_sha1_free( &operation->ctx.sha1 ); break; #endif -#if defined(MBEDTLS_SHA256_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) case PSA_ALG_SHA_224: + mbedtls_sha256_free( &operation->ctx.sha256 ); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) case PSA_ALG_SHA_256: mbedtls_sha256_free( &operation->ctx.sha256 ); break; #endif -#if defined(MBEDTLS_SHA512_C) -#if !defined(MBEDTLS_SHA512_NO_SHA384) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) case PSA_ALG_SHA_384: + mbedtls_sha512_free( &operation->ctx.sha512 ); + break; #endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) case PSA_ALG_SHA_512: mbedtls_sha512_free( &operation->ctx.sha512 ); break; @@ -2368,53 +2586,55 @@ psa_status_t psa_hash_setup( psa_hash_operation_t *operation, switch( alg ) { -#if defined(MBEDTLS_MD2_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD2) case PSA_ALG_MD2: mbedtls_md2_init( &operation->ctx.md2 ); ret = mbedtls_md2_starts_ret( &operation->ctx.md2 ); break; #endif -#if defined(MBEDTLS_MD4_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD4) case PSA_ALG_MD4: mbedtls_md4_init( &operation->ctx.md4 ); ret = mbedtls_md4_starts_ret( &operation->ctx.md4 ); break; #endif -#if defined(MBEDTLS_MD5_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) case PSA_ALG_MD5: mbedtls_md5_init( &operation->ctx.md5 ); ret = mbedtls_md5_starts_ret( &operation->ctx.md5 ); break; #endif -#if defined(MBEDTLS_RIPEMD160_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) case PSA_ALG_RIPEMD160: mbedtls_ripemd160_init( &operation->ctx.ripemd160 ); ret = mbedtls_ripemd160_starts_ret( &operation->ctx.ripemd160 ); break; #endif -#if defined(MBEDTLS_SHA1_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) case PSA_ALG_SHA_1: mbedtls_sha1_init( &operation->ctx.sha1 ); ret = mbedtls_sha1_starts_ret( &operation->ctx.sha1 ); break; #endif -#if defined(MBEDTLS_SHA256_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) case PSA_ALG_SHA_224: mbedtls_sha256_init( &operation->ctx.sha256 ); ret = mbedtls_sha256_starts_ret( &operation->ctx.sha256, 1 ); break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) case PSA_ALG_SHA_256: mbedtls_sha256_init( &operation->ctx.sha256 ); ret = mbedtls_sha256_starts_ret( &operation->ctx.sha256, 0 ); break; #endif -#if defined(MBEDTLS_SHA512_C) -#if !defined(MBEDTLS_SHA512_NO_SHA384) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) case PSA_ALG_SHA_384: mbedtls_sha512_init( &operation->ctx.sha512 ); ret = mbedtls_sha512_starts_ret( &operation->ctx.sha512, 1 ); break; #endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) case PSA_ALG_SHA_512: mbedtls_sha512_init( &operation->ctx.sha512 ); ret = mbedtls_sha512_starts_ret( &operation->ctx.sha512, 0 ); @@ -2445,53 +2665,62 @@ psa_status_t psa_hash_update( psa_hash_operation_t *operation, switch( operation->alg ) { -#if defined(MBEDTLS_MD2_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD2) case PSA_ALG_MD2: ret = mbedtls_md2_update_ret( &operation->ctx.md2, input, input_length ); break; #endif -#if defined(MBEDTLS_MD4_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD4) case PSA_ALG_MD4: ret = mbedtls_md4_update_ret( &operation->ctx.md4, input, input_length ); break; #endif -#if defined(MBEDTLS_MD5_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) case PSA_ALG_MD5: ret = mbedtls_md5_update_ret( &operation->ctx.md5, input, input_length ); break; #endif -#if defined(MBEDTLS_RIPEMD160_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) case PSA_ALG_RIPEMD160: ret = mbedtls_ripemd160_update_ret( &operation->ctx.ripemd160, input, input_length ); break; #endif -#if defined(MBEDTLS_SHA1_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) case PSA_ALG_SHA_1: ret = mbedtls_sha1_update_ret( &operation->ctx.sha1, input, input_length ); break; #endif -#if defined(MBEDTLS_SHA256_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) case PSA_ALG_SHA_224: + ret = mbedtls_sha256_update_ret( &operation->ctx.sha256, + input, input_length ); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) case PSA_ALG_SHA_256: ret = mbedtls_sha256_update_ret( &operation->ctx.sha256, input, input_length ); break; #endif -#if defined(MBEDTLS_SHA512_C) -#if !defined(MBEDTLS_SHA512_NO_SHA384) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) case PSA_ALG_SHA_384: + ret = mbedtls_sha512_update_ret( &operation->ctx.sha512, + input, input_length ); + break; #endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) case PSA_ALG_SHA_512: ret = mbedtls_sha512_update_ret( &operation->ctx.sha512, input, input_length ); break; #endif default: + (void)input; return( PSA_ERROR_BAD_STATE ); } @@ -2526,41 +2755,47 @@ psa_status_t psa_hash_finish( psa_hash_operation_t *operation, switch( operation->alg ) { -#if defined(MBEDTLS_MD2_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD2) case PSA_ALG_MD2: ret = mbedtls_md2_finish_ret( &operation->ctx.md2, hash ); break; #endif -#if defined(MBEDTLS_MD4_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD4) case PSA_ALG_MD4: ret = mbedtls_md4_finish_ret( &operation->ctx.md4, hash ); break; #endif -#if defined(MBEDTLS_MD5_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) case PSA_ALG_MD5: ret = mbedtls_md5_finish_ret( &operation->ctx.md5, hash ); break; #endif -#if defined(MBEDTLS_RIPEMD160_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) case PSA_ALG_RIPEMD160: ret = mbedtls_ripemd160_finish_ret( &operation->ctx.ripemd160, hash ); break; #endif -#if defined(MBEDTLS_SHA1_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) case PSA_ALG_SHA_1: ret = mbedtls_sha1_finish_ret( &operation->ctx.sha1, hash ); break; #endif -#if defined(MBEDTLS_SHA256_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) case PSA_ALG_SHA_224: + ret = mbedtls_sha256_finish_ret( &operation->ctx.sha256, hash ); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) case PSA_ALG_SHA_256: ret = mbedtls_sha256_finish_ret( &operation->ctx.sha256, hash ); break; #endif -#if defined(MBEDTLS_SHA512_C) -#if !defined(MBEDTLS_SHA512_NO_SHA384) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) case PSA_ALG_SHA_384: + ret = mbedtls_sha512_finish_ret( &operation->ctx.sha512, hash ); + break; #endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) case PSA_ALG_SHA_512: ret = mbedtls_sha512_finish_ret( &operation->ctx.sha512, hash ); break; @@ -2663,47 +2898,55 @@ psa_status_t psa_hash_clone( const psa_hash_operation_t *source_operation, { case 0: return( PSA_ERROR_BAD_STATE ); -#if defined(MBEDTLS_MD2_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD2) case PSA_ALG_MD2: mbedtls_md2_clone( &target_operation->ctx.md2, &source_operation->ctx.md2 ); break; #endif -#if defined(MBEDTLS_MD4_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD4) case PSA_ALG_MD4: mbedtls_md4_clone( &target_operation->ctx.md4, &source_operation->ctx.md4 ); break; #endif -#if defined(MBEDTLS_MD5_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_MD5) case PSA_ALG_MD5: mbedtls_md5_clone( &target_operation->ctx.md5, &source_operation->ctx.md5 ); break; #endif -#if defined(MBEDTLS_RIPEMD160_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RIPEMD160) case PSA_ALG_RIPEMD160: mbedtls_ripemd160_clone( &target_operation->ctx.ripemd160, &source_operation->ctx.ripemd160 ); break; #endif -#if defined(MBEDTLS_SHA1_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_1) case PSA_ALG_SHA_1: mbedtls_sha1_clone( &target_operation->ctx.sha1, &source_operation->ctx.sha1 ); break; #endif -#if defined(MBEDTLS_SHA256_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_224) case PSA_ALG_SHA_224: + mbedtls_sha256_clone( &target_operation->ctx.sha256, + &source_operation->ctx.sha256 ); + break; +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_256) case PSA_ALG_SHA_256: mbedtls_sha256_clone( &target_operation->ctx.sha256, &source_operation->ctx.sha256 ); break; #endif -#if defined(MBEDTLS_SHA512_C) -#if !defined(MBEDTLS_SHA512_NO_SHA384) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_384) case PSA_ALG_SHA_384: + mbedtls_sha512_clone( &target_operation->ctx.sha512, + &source_operation->ctx.sha512 ); + break; #endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_SHA_512) case PSA_ALG_SHA_512: mbedtls_sha512_clone( &target_operation->ctx.sha512, &source_operation->ctx.sha512 ); @@ -2738,8 +2981,7 @@ static const mbedtls_cipher_info_t *mbedtls_cipher_info_from_psa( { switch( alg ) { - case PSA_ALG_ARC4: - case PSA_ALG_CHACHA20: + case PSA_ALG_STREAM_CIPHER: mode = MBEDTLS_MODE_STREAM; break; case PSA_ALG_CTR: @@ -2751,6 +2993,9 @@ static const mbedtls_cipher_info_t *mbedtls_cipher_info_from_psa( case PSA_ALG_OFB: mode = MBEDTLS_MODE_OFB; break; + case PSA_ALG_ECB_NO_PADDING: + mode = MBEDTLS_MODE_ECB; + break; case PSA_ALG_CBC_NO_PADDING: mode = MBEDTLS_MODE_CBC; break; @@ -2812,7 +3057,7 @@ static const mbedtls_cipher_info_t *mbedtls_cipher_info_from_psa( (int) key_bits, mode ) ); } -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) static size_t psa_get_hash_block_size( psa_algorithm_t alg ) { switch( alg ) @@ -2839,7 +3084,7 @@ static size_t psa_get_hash_block_size( psa_algorithm_t alg ) return( 0 ); } } -#endif /* MBEDTLS_MD_C */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) */ /* Initialize the MAC operation structure. Once this function has been * called, psa_mac_abort can run and will do the right thing. */ @@ -2864,7 +3109,7 @@ static psa_status_t psa_mac_init( psa_mac_operation_t *operation, } else #endif /* MBEDTLS_CMAC_C */ -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) if( PSA_ALG_IS_HMAC( operation->alg ) ) { /* We'll set up the hash operation later in psa_hmac_setup_internal. */ @@ -2872,7 +3117,7 @@ static psa_status_t psa_mac_init( psa_mac_operation_t *operation, status = PSA_SUCCESS; } else -#endif /* MBEDTLS_MD_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ { if( ! PSA_ALG_IS_MAC( alg ) ) status = PSA_ERROR_INVALID_ARGUMENT; @@ -2883,13 +3128,13 @@ static psa_status_t psa_mac_init( psa_mac_operation_t *operation, return( status ); } -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) static psa_status_t psa_hmac_abort_internal( psa_hmac_internal_data *hmac ) { mbedtls_platform_zeroize( hmac->opad, sizeof( hmac->opad ) ); return( psa_hash_abort( &hmac->hash_ctx ) ); } -#endif /* MBEDTLS_MD_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ psa_status_t psa_mac_abort( psa_mac_operation_t *operation ) { @@ -2908,13 +3153,13 @@ psa_status_t psa_mac_abort( psa_mac_operation_t *operation ) } else #endif /* MBEDTLS_CMAC_C */ -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) if( PSA_ALG_IS_HMAC( operation->alg ) ) { psa_hmac_abort_internal( &operation->ctx.hmac ); } else -#endif /* MBEDTLS_MD_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ { /* Sanity check (shouldn't happen: operation->alg should * always have been initialized to a valid value). */ @@ -2960,7 +3205,7 @@ static int psa_cmac_setup( psa_mac_operation_t *operation, } #endif /* MBEDTLS_CMAC_C */ -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) static psa_status_t psa_hmac_setup_internal( psa_hmac_internal_data *hmac, const uint8_t *key, size_t key_length, @@ -3022,14 +3267,15 @@ cleanup: return( status ); } -#endif /* MBEDTLS_MD_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ static psa_status_t psa_mac_setup( psa_mac_operation_t *operation, - psa_key_handle_t handle, + mbedtls_svc_key_id_t key, psa_algorithm_t alg, int is_sign ) { - psa_status_t status; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; psa_key_slot_t *slot; size_t key_bits; psa_key_usage_t usage = @@ -3049,7 +3295,8 @@ static psa_status_t psa_mac_setup( psa_mac_operation_t *operation, if( is_sign ) operation->is_sign = 1; - status = psa_get_transparent_key( handle, &slot, usage, alg ); + status = psa_get_and_lock_transparent_key_slot_with_policy( + key, &slot, usage, alg ); if( status != PSA_SUCCESS ) goto exit; key_bits = psa_get_key_slot_bits( slot ); @@ -3072,7 +3319,7 @@ static psa_status_t psa_mac_setup( psa_mac_operation_t *operation, } else #endif /* MBEDTLS_CMAC_C */ -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) if( PSA_ALG_IS_HMAC( full_length_alg ) ) { psa_algorithm_t hash_alg = PSA_ALG_HMAC_GET_HASH( alg ); @@ -3103,7 +3350,7 @@ static psa_status_t psa_mac_setup( psa_mac_operation_t *operation, hash_alg ); } else -#endif /* MBEDTLS_MD_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ { (void) key_bits; status = PSA_ERROR_NOT_SUPPORTED; @@ -3138,21 +3385,24 @@ exit: { operation->key_set = 1; } - return( status ); + + unlock_status = psa_unlock_key_slot( slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); } psa_status_t psa_mac_sign_setup( psa_mac_operation_t *operation, - psa_key_handle_t handle, + mbedtls_svc_key_id_t key, psa_algorithm_t alg ) { - return( psa_mac_setup( operation, handle, alg, 1 ) ); + return( psa_mac_setup( operation, key, alg, 1 ) ); } psa_status_t psa_mac_verify_setup( psa_mac_operation_t *operation, - psa_key_handle_t handle, + mbedtls_svc_key_id_t key, psa_algorithm_t alg ) { - return( psa_mac_setup( operation, handle, alg, 0 ) ); + return( psa_mac_setup( operation, key, alg, 0 ) ); } psa_status_t psa_mac_update( psa_mac_operation_t *operation, @@ -3175,14 +3425,14 @@ psa_status_t psa_mac_update( psa_mac_operation_t *operation, } else #endif /* MBEDTLS_CMAC_C */ -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) if( PSA_ALG_IS_HMAC( operation->alg ) ) { status = psa_hash_update( &operation->ctx.hmac.hash_ctx, input, input_length ); } else -#endif /* MBEDTLS_MD_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ { /* This shouldn't happen if `operation` was initialized by * a setup function. */ @@ -3194,7 +3444,7 @@ psa_status_t psa_mac_update( psa_mac_operation_t *operation, return( status ); } -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) static psa_status_t psa_hmac_finish_internal( psa_hmac_internal_data *hmac, uint8_t *mac, size_t mac_size ) @@ -3232,7 +3482,7 @@ exit: mbedtls_platform_zeroize( tmp, hash_size ); return( status ); } -#endif /* MBEDTLS_MD_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ static psa_status_t psa_mac_finish_internal( psa_mac_operation_t *operation, uint8_t *mac, @@ -3258,14 +3508,14 @@ static psa_status_t psa_mac_finish_internal( psa_mac_operation_t *operation, } else #endif /* MBEDTLS_CMAC_C */ -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HMAC) if( PSA_ALG_IS_HMAC( operation->alg ) ) { return( psa_hmac_finish_internal( &operation->ctx.hmac, mac, operation->mac_size ) ); } else -#endif /* MBEDTLS_MD_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HMAC */ { /* This shouldn't happen if `operation` was initialized by * a setup function. */ @@ -3361,7 +3611,8 @@ cleanup: /* Asymmetric cryptography */ /****************************************************************/ -#if defined(MBEDTLS_RSA_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) /* Decode the hash algorithm from alg and store the mbedtls encoding in * md_alg. Verify that the hash length is acceptable. */ static psa_status_t psa_rsa_decode_md_type( psa_algorithm_t alg, @@ -3380,7 +3631,7 @@ static psa_status_t psa_rsa_decode_md_type( psa_algorithm_t alg, return( PSA_ERROR_INVALID_ARGUMENT ); #endif -#if defined(MBEDTLS_PKCS1_V15) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) /* For PKCS#1 v1.5 signature, if using a hash, the hash length * must be correct. */ if( PSA_ALG_IS_RSA_PKCS1V15_SIGN( alg ) && @@ -3391,16 +3642,16 @@ static psa_status_t psa_rsa_decode_md_type( psa_algorithm_t alg, if( mbedtls_md_get_size( md_info ) != hash_length ) return( PSA_ERROR_INVALID_ARGUMENT ); } -#endif /* MBEDTLS_PKCS1_V15 */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN */ -#if defined(MBEDTLS_PKCS1_V21) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) /* PSS requires a hash internally. */ if( PSA_ALG_IS_RSA_PSS( alg ) ) { if( md_info == NULL ) return( PSA_ERROR_NOT_SUPPORTED ); } -#endif /* MBEDTLS_PKCS1_V21 */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS */ return( PSA_SUCCESS ); } @@ -3424,7 +3675,7 @@ static psa_status_t psa_rsa_sign( mbedtls_rsa_context *rsa, if( signature_size < mbedtls_rsa_get_len( rsa ) ) return( PSA_ERROR_BUFFER_TOO_SMALL ); -#if defined(MBEDTLS_PKCS1_V15) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) if( PSA_ALG_IS_RSA_PKCS1V15_SIGN( alg ) ) { mbedtls_rsa_set_padding( rsa, MBEDTLS_RSA_PKCS_V15, @@ -3439,8 +3690,8 @@ static psa_status_t psa_rsa_sign( mbedtls_rsa_context *rsa, signature ); } else -#endif /* MBEDTLS_PKCS1_V15 */ -#if defined(MBEDTLS_PKCS1_V21) +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) if( PSA_ALG_IS_RSA_PSS( alg ) ) { mbedtls_rsa_set_padding( rsa, MBEDTLS_RSA_PKCS_V21, md_alg ); @@ -3454,7 +3705,7 @@ static psa_status_t psa_rsa_sign( mbedtls_rsa_context *rsa, signature ); } else -#endif /* MBEDTLS_PKCS1_V21 */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS */ { return( PSA_ERROR_INVALID_ARGUMENT ); } @@ -3482,7 +3733,7 @@ static psa_status_t psa_rsa_verify( mbedtls_rsa_context *rsa, if( signature_length != mbedtls_rsa_get_len( rsa ) ) return( PSA_ERROR_INVALID_SIGNATURE ); -#if defined(MBEDTLS_PKCS1_V15) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) if( PSA_ALG_IS_RSA_PKCS1V15_SIGN( alg ) ) { mbedtls_rsa_set_padding( rsa, MBEDTLS_RSA_PKCS_V15, @@ -3497,8 +3748,8 @@ static psa_status_t psa_rsa_verify( mbedtls_rsa_context *rsa, signature ); } else -#endif /* MBEDTLS_PKCS1_V15 */ -#if defined(MBEDTLS_PKCS1_V21) +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) if( PSA_ALG_IS_RSA_PSS( alg ) ) { mbedtls_rsa_set_padding( rsa, MBEDTLS_RSA_PKCS_V21, md_alg ); @@ -3512,7 +3763,7 @@ static psa_status_t psa_rsa_verify( mbedtls_rsa_context *rsa, signature ); } else -#endif /* MBEDTLS_PKCS1_V21 */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS */ { return( PSA_ERROR_INVALID_ARGUMENT ); } @@ -3524,9 +3775,11 @@ static psa_status_t psa_rsa_verify( mbedtls_rsa_context *rsa, return( PSA_ERROR_INVALID_SIGNATURE ); return( mbedtls_to_psa_error( ret ) ); } -#endif /* MBEDTLS_RSA_C */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) */ -#if defined(MBEDTLS_ECDSA_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) /* `ecp` cannot be const because `ecp->grp` needs to be non-const * for mbedtls_ecdsa_sign() and mbedtls_ecdsa_sign_det() * (even though these functions don't modify it). */ @@ -3550,7 +3803,7 @@ static psa_status_t psa_ecdsa_sign( mbedtls_ecp_keypair *ecp, goto cleanup; } -#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) if( PSA_ALG_DSA_IS_DETERMINISTIC( alg ) ) { psa_algorithm_t hash_alg = PSA_ALG_SIGN_GET_HASH( alg ); @@ -3563,7 +3816,7 @@ static psa_status_t psa_ecdsa_sign( mbedtls_ecp_keypair *ecp, &global_data.ctr_drbg ) ); } else -#endif /* MBEDTLS_ECDSA_DETERMINISTIC */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ { (void) alg; MBEDTLS_MPI_CHK( mbedtls_ecdsa_sign( &ecp->grp, &r, &s, &ecp->d, @@ -3625,9 +3878,10 @@ cleanup: mbedtls_mpi_free( &s ); return( mbedtls_to_psa_error( ret ) ); } -#endif /* MBEDTLS_ECDSA_C */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ -psa_status_t psa_sign_hash( psa_key_handle_t handle, +psa_status_t psa_sign_hash( mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, @@ -3635,12 +3889,9 @@ psa_status_t psa_sign_hash( psa_key_handle_t handle, size_t signature_size, size_t *signature_length ) { + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; psa_key_slot_t *slot; - psa_status_t status; -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - const psa_drv_se_t *drv; - psa_drv_se_context_t *drv_context; -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ *signature_length = signature_size; /* Immediately reject a zero-length signature buffer. This guarantees @@ -3650,7 +3901,9 @@ psa_status_t psa_sign_hash( psa_key_handle_t handle, if( signature_size == 0 ) return( PSA_ERROR_BUFFER_TOO_SMALL ); - status = psa_get_key_from_slot( handle, &slot, PSA_KEY_USAGE_SIGN_HASH, alg ); + status = psa_get_and_lock_key_slot_with_policy( key, &slot, + PSA_KEY_USAGE_SIGN_HASH, + alg ); if( status != PSA_SUCCESS ) goto exit; if( ! PSA_KEY_TYPE_IS_KEY_PAIR( slot->attr.type ) ) @@ -3659,25 +3912,21 @@ psa_status_t psa_sign_hash( psa_key_handle_t handle, goto exit; } -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - if( psa_get_se_driver( slot->attr.lifetime, &drv, &drv_context ) ) - { - if( drv->asymmetric == NULL || - drv->asymmetric->p_sign == NULL ) - { - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - status = drv->asymmetric->p_sign( drv_context, - slot->data.se.slot_number, - alg, - hash, hash_length, - signature, signature_size, - signature_length ); - } - else -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ -#if defined(MBEDTLS_RSA_C) + /* Try any of the available accelerators first */ + status = psa_driver_wrapper_sign_hash( slot, + alg, + hash, + hash_length, + signature, + signature_size, + signature_length ); + if( status != PSA_ERROR_NOT_SUPPORTED || + psa_key_lifetime_is_external( slot->attr.lifetime ) ) + goto exit; + + /* If the operation was not supported by any accelerator, try fallback. */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) if( slot->attr.type == PSA_KEY_TYPE_RSA_KEY_PAIR ) { mbedtls_rsa_context *rsa = NULL; @@ -3699,13 +3948,14 @@ psa_status_t psa_sign_hash( psa_key_handle_t handle, mbedtls_free( rsa ); } else -#endif /* defined(MBEDTLS_RSA_C) */ -#if defined(MBEDTLS_ECP_C) +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) */ if( PSA_KEY_TYPE_IS_ECC( slot->attr.type ) ) { -#if defined(MBEDTLS_ECDSA_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) if( -#if defined(MBEDTLS_ECDSA_DETERMINISTIC) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) PSA_ALG_IS_ECDSA( alg ) #else PSA_ALG_IS_RANDOMIZED_ECDSA( alg ) @@ -3728,13 +3978,13 @@ psa_status_t psa_sign_hash( psa_key_handle_t handle, mbedtls_free( ecp ); } else -#endif /* defined(MBEDTLS_ECDSA_C) */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ { status = PSA_ERROR_INVALID_ARGUMENT; } } else -#endif /* defined(MBEDTLS_ECP_C) */ { status = PSA_ERROR_NOT_SUPPORTED; } @@ -3751,42 +4001,42 @@ exit: memset( signature, '!', signature_size ); /* If signature_size is 0 then we have nothing to do. We must not call * memset because signature may be NULL in this case. */ - return( status ); + + unlock_status = psa_unlock_key_slot( slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); } -psa_status_t psa_verify_hash( psa_key_handle_t handle, +psa_status_t psa_verify_hash( mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *hash, size_t hash_length, const uint8_t *signature, size_t signature_length ) { + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; psa_key_slot_t *slot; - psa_status_t status; -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - const psa_drv_se_t *drv; - psa_drv_se_context_t *drv_context; -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - status = psa_get_key_from_slot( handle, &slot, PSA_KEY_USAGE_VERIFY_HASH, alg ); + status = psa_get_and_lock_key_slot_with_policy( key, &slot, + PSA_KEY_USAGE_VERIFY_HASH, + alg ); if( status != PSA_SUCCESS ) return( status ); -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - if( psa_get_se_driver( slot->attr.lifetime, &drv, &drv_context ) ) - { - if( drv->asymmetric == NULL || - drv->asymmetric->p_verify == NULL ) - return( PSA_ERROR_NOT_SUPPORTED ); - return( drv->asymmetric->p_verify( drv_context, - slot->data.se.slot_number, - alg, - hash, hash_length, - signature, signature_length ) ); - } - else -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ -#if defined(MBEDTLS_RSA_C) + /* Try any of the available accelerators first */ + status = psa_driver_wrapper_verify_hash( slot, + alg, + hash, + hash_length, + signature, + signature_length ); + if( status != PSA_ERROR_NOT_SUPPORTED || + psa_key_lifetime_is_external( slot->attr.lifetime ) ) + goto exit; + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) if( PSA_KEY_TYPE_IS_RSA( slot->attr.type ) ) { mbedtls_rsa_context *rsa = NULL; @@ -3796,7 +4046,7 @@ psa_status_t psa_verify_hash( psa_key_handle_t handle, slot->data.key.bytes, &rsa ); if( status != PSA_SUCCESS ) - return( status ); + goto exit; status = psa_rsa_verify( rsa, alg, @@ -3804,14 +4054,15 @@ psa_status_t psa_verify_hash( psa_key_handle_t handle, signature, signature_length ); mbedtls_rsa_free( rsa ); mbedtls_free( rsa ); - return( status ); + goto exit; } else -#endif /* defined(MBEDTLS_RSA_C) */ -#if defined(MBEDTLS_ECP_C) +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_SIGN) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PSS) */ if( PSA_KEY_TYPE_IS_ECC( slot->attr.type ) ) { -#if defined(MBEDTLS_ECDSA_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) if( PSA_ALG_IS_ECDSA( alg ) ) { mbedtls_ecp_keypair *ecp = NULL; @@ -3820,28 +4071,34 @@ psa_status_t psa_verify_hash( psa_key_handle_t handle, slot->data.key.bytes, &ecp ); if( status != PSA_SUCCESS ) - return( status ); + goto exit; status = psa_ecdsa_verify( ecp, hash, hash_length, signature, signature_length ); mbedtls_ecp_keypair_free( ecp ); mbedtls_free( ecp ); - return( status ); + goto exit; } else -#endif /* defined(MBEDTLS_ECDSA_C) */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_ECDSA) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_DETERMINISTIC_ECDSA) */ { - return( PSA_ERROR_INVALID_ARGUMENT ); + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; } } else -#endif /* defined(MBEDTLS_ECP_C) */ { - return( PSA_ERROR_NOT_SUPPORTED ); + status = PSA_ERROR_NOT_SUPPORTED; } + +exit: + unlock_status = psa_unlock_key_slot( slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); } -#if defined(MBEDTLS_RSA_C) && defined(MBEDTLS_PKCS1_V21) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) static void psa_rsa_oaep_set_padding_mode( psa_algorithm_t alg, mbedtls_rsa_context *rsa ) { @@ -3850,9 +4107,9 @@ static void psa_rsa_oaep_set_padding_mode( psa_algorithm_t alg, mbedtls_md_type_t md_alg = mbedtls_md_get_type( md_info ); mbedtls_rsa_set_padding( rsa, MBEDTLS_RSA_PKCS_V21, md_alg ); } -#endif /* defined(MBEDTLS_RSA_C) && defined(MBEDTLS_PKCS1_V21) */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) */ -psa_status_t psa_asymmetric_encrypt( psa_key_handle_t handle, +psa_status_t psa_asymmetric_encrypt( mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *input, size_t input_length, @@ -3862,8 +4119,9 @@ psa_status_t psa_asymmetric_encrypt( psa_key_handle_t handle, size_t output_size, size_t *output_length ) { + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; psa_key_slot_t *slot; - psa_status_t status; (void) input; (void) input_length; @@ -3876,14 +4134,19 @@ psa_status_t psa_asymmetric_encrypt( psa_key_handle_t handle, if( ! PSA_ALG_IS_RSA_OAEP( alg ) && salt_length != 0 ) return( PSA_ERROR_INVALID_ARGUMENT ); - status = psa_get_transparent_key( handle, &slot, PSA_KEY_USAGE_ENCRYPT, alg ); + status = psa_get_and_lock_transparent_key_slot_with_policy( + key, &slot, PSA_KEY_USAGE_ENCRYPT, alg ); if( status != PSA_SUCCESS ) return( status ); if( ! ( PSA_KEY_TYPE_IS_PUBLIC_KEY( slot->attr.type ) || PSA_KEY_TYPE_IS_KEY_PAIR( slot->attr.type ) ) ) - return( PSA_ERROR_INVALID_ARGUMENT ); + { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } -#if defined(MBEDTLS_RSA_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) if( PSA_KEY_TYPE_IS_RSA( slot->attr.type ) ) { mbedtls_rsa_context *rsa = NULL; @@ -3899,7 +4162,7 @@ psa_status_t psa_asymmetric_encrypt( psa_key_handle_t handle, status = PSA_ERROR_BUFFER_TOO_SMALL; goto rsa_exit; } -#if defined(MBEDTLS_PKCS1_V15) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) if( alg == PSA_ALG_RSA_PKCS1V15_CRYPT ) { status = mbedtls_to_psa_error( @@ -3912,8 +4175,8 @@ psa_status_t psa_asymmetric_encrypt( psa_key_handle_t handle, output ) ); } else -#endif /* MBEDTLS_PKCS1_V15 */ -#if defined(MBEDTLS_PKCS1_V21) +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) if( PSA_ALG_IS_RSA_OAEP( alg ) ) { psa_rsa_oaep_set_padding_mode( alg, rsa ); @@ -3928,7 +4191,7 @@ psa_status_t psa_asymmetric_encrypt( psa_key_handle_t handle, output ) ); } else -#endif /* MBEDTLS_PKCS1_V21 */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP */ { status = PSA_ERROR_INVALID_ARGUMENT; goto rsa_exit; @@ -3939,16 +4202,21 @@ rsa_exit: mbedtls_rsa_free( rsa ); mbedtls_free( rsa ); - return( status ); } else -#endif /* defined(MBEDTLS_RSA_C) */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) */ { - return( PSA_ERROR_NOT_SUPPORTED ); + status = PSA_ERROR_NOT_SUPPORTED; } + +exit: + unlock_status = psa_unlock_key_slot( slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); } -psa_status_t psa_asymmetric_decrypt( psa_key_handle_t handle, +psa_status_t psa_asymmetric_decrypt( mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *input, size_t input_length, @@ -3958,8 +4226,9 @@ psa_status_t psa_asymmetric_decrypt( psa_key_handle_t handle, size_t output_size, size_t *output_length ) { + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; psa_key_slot_t *slot; - psa_status_t status; (void) input; (void) input_length; @@ -3972,13 +4241,18 @@ psa_status_t psa_asymmetric_decrypt( psa_key_handle_t handle, if( ! PSA_ALG_IS_RSA_OAEP( alg ) && salt_length != 0 ) return( PSA_ERROR_INVALID_ARGUMENT ); - status = psa_get_transparent_key( handle, &slot, PSA_KEY_USAGE_DECRYPT, alg ); + status = psa_get_and_lock_transparent_key_slot_with_policy( + key, &slot, PSA_KEY_USAGE_DECRYPT, alg ); if( status != PSA_SUCCESS ) return( status ); if( ! PSA_KEY_TYPE_IS_KEY_PAIR( slot->attr.type ) ) - return( PSA_ERROR_INVALID_ARGUMENT ); + { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } -#if defined(MBEDTLS_RSA_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) if( slot->attr.type == PSA_KEY_TYPE_RSA_KEY_PAIR ) { mbedtls_rsa_context *rsa = NULL; @@ -3987,7 +4261,7 @@ psa_status_t psa_asymmetric_decrypt( psa_key_handle_t handle, slot->data.key.bytes, &rsa ); if( status != PSA_SUCCESS ) - return( status ); + goto exit; if( input_length != mbedtls_rsa_get_len( rsa ) ) { @@ -3995,7 +4269,7 @@ psa_status_t psa_asymmetric_decrypt( psa_key_handle_t handle, goto rsa_exit; } -#if defined(MBEDTLS_PKCS1_V15) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) if( alg == PSA_ALG_RSA_PKCS1V15_CRYPT ) { status = mbedtls_to_psa_error( @@ -4009,8 +4283,8 @@ psa_status_t psa_asymmetric_decrypt( psa_key_handle_t handle, output_size ) ); } else -#endif /* MBEDTLS_PKCS1_V15 */ -#if defined(MBEDTLS_PKCS1_V21) +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) if( PSA_ALG_IS_RSA_OAEP( alg ) ) { psa_rsa_oaep_set_padding_mode( alg, rsa ); @@ -4026,7 +4300,7 @@ psa_status_t psa_asymmetric_decrypt( psa_key_handle_t handle, output_size ) ); } else -#endif /* MBEDTLS_PKCS1_V21 */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP */ { status = PSA_ERROR_INVALID_ARGUMENT; } @@ -4034,13 +4308,18 @@ psa_status_t psa_asymmetric_decrypt( psa_key_handle_t handle, rsa_exit: mbedtls_rsa_free( rsa ); mbedtls_free( rsa ); - return( status ); } else -#endif /* defined(MBEDTLS_RSA_C) */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_PKCS1V15_CRYPT) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_RSA_OAEP) */ { - return( PSA_ERROR_NOT_SUPPORTED ); + status = PSA_ERROR_NOT_SUPPORTED; } + +exit: + unlock_status = psa_unlock_key_slot( slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); } @@ -4049,34 +4328,14 @@ rsa_exit: /* Symmetric cryptography */ /****************************************************************/ -/* Initialize the cipher operation structure. Once this function has been - * called, psa_cipher_abort can run and will do the right thing. */ -static psa_status_t psa_cipher_init( psa_cipher_operation_t *operation, - psa_algorithm_t alg ) -{ - if( ! PSA_ALG_IS_CIPHER( alg ) ) - { - memset( operation, 0, sizeof( *operation ) ); - return( PSA_ERROR_INVALID_ARGUMENT ); - } - - operation->alg = alg; - operation->key_set = 0; - operation->iv_set = 0; - operation->iv_required = 1; - operation->iv_size = 0; - operation->block_size = 0; - mbedtls_cipher_init( &operation->ctx.cipher ); - return( PSA_SUCCESS ); -} - static psa_status_t psa_cipher_setup( psa_cipher_operation_t *operation, - psa_key_handle_t handle, + mbedtls_svc_key_id_t key, psa_algorithm_t alg, mbedtls_operation_t cipher_operation ) { + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; int ret = 0; - psa_status_t status = PSA_ERROR_GENERIC_ERROR; psa_key_slot_t *slot; size_t key_bits; const mbedtls_cipher_info_t *cipher_info = NULL; @@ -4086,19 +4345,63 @@ static psa_status_t psa_cipher_setup( psa_cipher_operation_t *operation, /* A context must be freshly initialized before it can be set up. */ if( operation->alg != 0 ) - { return( PSA_ERROR_BAD_STATE ); - } - status = psa_cipher_init( operation, alg ); - if( status != PSA_SUCCESS ) - return( status ); + /* The requested algorithm must be one that can be processed by cipher. */ + if( ! PSA_ALG_IS_CIPHER( alg ) ) + return( PSA_ERROR_INVALID_ARGUMENT ); - status = psa_get_transparent_key( handle, &slot, usage, alg); + /* Fetch key material from key storage. */ + status = psa_get_and_lock_key_slot_with_policy( key, &slot, usage, alg ); if( status != PSA_SUCCESS ) goto exit; - key_bits = psa_get_key_slot_bits( slot ); + /* Initialize the operation struct members, except for alg. The alg member + * is used to indicate to psa_cipher_abort that there are resources to free, + * so we only set it after resources have been allocated/initialized. */ + operation->key_set = 0; + operation->iv_set = 0; + operation->mbedtls_in_use = 0; + operation->iv_size = 0; + operation->block_size = 0; + if( alg == PSA_ALG_ECB_NO_PADDING ) + operation->iv_required = 0; + else + operation->iv_required = 1; + + /* Try doing the operation through a driver before using software fallback. */ + if( cipher_operation == MBEDTLS_ENCRYPT ) + status = psa_driver_wrapper_cipher_encrypt_setup( &operation->ctx.driver, + slot, + alg ); + else + status = psa_driver_wrapper_cipher_decrypt_setup( &operation->ctx.driver, + slot, + alg ); + + if( status == PSA_SUCCESS ) + { + /* Once the driver context is initialised, it needs to be freed using + * psa_cipher_abort. Indicate this through setting alg. */ + operation->alg = alg; + } + + if( status != PSA_ERROR_NOT_SUPPORTED || + psa_key_lifetime_is_external( slot->attr.lifetime ) ) + goto exit; + + /* Proceed with initializing an mbed TLS cipher context if no driver is + * available for the given algorithm & key. */ + mbedtls_cipher_init( &operation->ctx.cipher ); + + /* Once the cipher context is initialised, it needs to be freed using + * psa_cipher_abort. Indicate there is something to be freed through setting + * alg, and indicate the operation is being done using mbedtls crypto through + * setting mbedtls_in_use. */ + operation->alg = alg; + operation->mbedtls_in_use = 1; + + key_bits = psa_get_key_slot_bits( slot ); cipher_info = mbedtls_cipher_info_from_psa( alg, slot->attr.type, key_bits, NULL ); if( cipher_info == NULL ) { @@ -4151,39 +4454,49 @@ static psa_status_t psa_cipher_setup( psa_cipher_operation_t *operation, goto exit; #endif //MBEDTLS_CIPHER_MODE_WITH_PADDING - operation->key_set = 1; operation->block_size = ( PSA_ALG_IS_STREAM_CIPHER( alg ) ? 1 : PSA_BLOCK_CIPHER_BLOCK_SIZE( slot->attr.type ) ); - if( alg & PSA_ALG_CIPHER_FROM_BLOCK_FLAG ) + if( ( alg & PSA_ALG_CIPHER_FROM_BLOCK_FLAG ) != 0 && + alg != PSA_ALG_ECB_NO_PADDING ) { operation->iv_size = PSA_BLOCK_CIPHER_BLOCK_SIZE( slot->attr.type ); } #if defined(MBEDTLS_CHACHA20_C) else - if( alg == PSA_ALG_CHACHA20 ) + if( alg == PSA_ALG_STREAM_CIPHER && slot->attr.type == PSA_KEY_TYPE_CHACHA20 ) operation->iv_size = 12; #endif + status = PSA_SUCCESS; + exit: - if( status == 0 ) + if( ret != 0 ) status = mbedtls_to_psa_error( ret ); - if( status != 0 ) + if( status == PSA_SUCCESS ) + { + /* Update operation flags for both driver and software implementations */ + operation->key_set = 1; + } + else psa_cipher_abort( operation ); - return( status ); + + unlock_status = psa_unlock_key_slot( slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); } psa_status_t psa_cipher_encrypt_setup( psa_cipher_operation_t *operation, - psa_key_handle_t handle, + mbedtls_svc_key_id_t key, psa_algorithm_t alg ) { - return( psa_cipher_setup( operation, handle, alg, MBEDTLS_ENCRYPT ) ); + return( psa_cipher_setup( operation, key, alg, MBEDTLS_ENCRYPT ) ); } psa_status_t psa_cipher_decrypt_setup( psa_cipher_operation_t *operation, - psa_key_handle_t handle, + mbedtls_svc_key_id_t key, psa_algorithm_t alg ) { - return( psa_cipher_setup( operation, handle, alg, MBEDTLS_DECRYPT ) ); + return( psa_cipher_setup( operation, key, alg, MBEDTLS_DECRYPT ) ); } psa_status_t psa_cipher_generate_iv( psa_cipher_operation_t *operation, @@ -4197,6 +4510,16 @@ psa_status_t psa_cipher_generate_iv( psa_cipher_operation_t *operation, { return( PSA_ERROR_BAD_STATE ); } + + if( operation->mbedtls_in_use == 0 ) + { + status = psa_driver_wrapper_cipher_generate_iv( &operation->ctx.driver, + iv, + iv_size, + iv_length ); + goto exit; + } + if( iv_size < operation->iv_size ) { status = PSA_ERROR_BUFFER_TOO_SMALL; @@ -4214,7 +4537,9 @@ psa_status_t psa_cipher_generate_iv( psa_cipher_operation_t *operation, status = psa_cipher_set_iv( operation, iv, *iv_length ); exit: - if( status != PSA_SUCCESS ) + if( status == PSA_SUCCESS ) + operation->iv_set = 1; + else psa_cipher_abort( operation ); return( status ); } @@ -4229,6 +4554,15 @@ psa_status_t psa_cipher_set_iv( psa_cipher_operation_t *operation, { return( PSA_ERROR_BAD_STATE ); } + + if( operation->mbedtls_in_use == 0 ) + { + status = psa_driver_wrapper_cipher_set_iv( &operation->ctx.driver, + iv, + iv_length ); + goto exit; + } + if( iv_length != operation->iv_size ) { status = PSA_ERROR_INVALID_ARGUMENT; @@ -4244,6 +4578,94 @@ exit: return( status ); } +/* Process input for which the algorithm is set to ECB mode. This requires + * manual processing, since the PSA API is defined as being able to process + * arbitrary-length calls to psa_cipher_update() with ECB mode, but the + * underlying mbedtls_cipher_update only takes full blocks. */ +static psa_status_t psa_cipher_update_ecb_internal( + mbedtls_cipher_context_t *ctx, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + size_t block_size = ctx->cipher_info->block_size; + size_t internal_output_length = 0; + *output_length = 0; + + if( input_length == 0 ) + { + status = PSA_SUCCESS; + goto exit; + } + + if( ctx->unprocessed_len > 0 ) + { + /* Fill up to block size, and run the block if there's a full one. */ + size_t bytes_to_copy = block_size - ctx->unprocessed_len; + + if( input_length < bytes_to_copy ) + bytes_to_copy = input_length; + + memcpy( &( ctx->unprocessed_data[ctx->unprocessed_len] ), + input, bytes_to_copy ); + input_length -= bytes_to_copy; + input += bytes_to_copy; + ctx->unprocessed_len += bytes_to_copy; + + if( ctx->unprocessed_len == block_size ) + { + status = mbedtls_to_psa_error( + mbedtls_cipher_update( ctx, + ctx->unprocessed_data, + block_size, + output, &internal_output_length ) ); + + if( status != PSA_SUCCESS ) + goto exit; + + output += internal_output_length; + output_size -= internal_output_length; + *output_length += internal_output_length; + ctx->unprocessed_len = 0; + } + } + + while( input_length >= block_size ) + { + /* Run all full blocks we have, one by one */ + status = mbedtls_to_psa_error( + mbedtls_cipher_update( ctx, input, + block_size, + output, &internal_output_length ) ); + + if( status != PSA_SUCCESS ) + goto exit; + + input_length -= block_size; + input += block_size; + + output += internal_output_length; + output_size -= internal_output_length; + *output_length += internal_output_length; + } + + if( input_length > 0 ) + { + /* Save unprocessed bytes for later processing */ + memcpy( &( ctx->unprocessed_data[ctx->unprocessed_len] ), + input, input_length ); + ctx->unprocessed_len += input_length; + } + + status = PSA_SUCCESS; + +exit: + return( status ); +} + psa_status_t psa_cipher_update( psa_cipher_operation_t *operation, const uint8_t *input, size_t input_length, @@ -4251,14 +4673,27 @@ psa_status_t psa_cipher_update( psa_cipher_operation_t *operation, size_t output_size, size_t *output_length ) { - psa_status_t status; - int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; size_t expected_output_size; - if( operation->alg == 0 ) { return( PSA_ERROR_BAD_STATE ); } + if( operation->iv_required && ! operation->iv_set ) + { + return( PSA_ERROR_BAD_STATE ); + } + + if( operation->mbedtls_in_use == 0 ) + { + status = psa_driver_wrapper_cipher_update( &operation->ctx.driver, + input, + input_length, + output, + output_size, + output_length ); + goto exit; + } if( ! PSA_ALG_IS_STREAM_CIPHER( operation->alg ) ) { @@ -4281,9 +4716,24 @@ psa_status_t psa_cipher_update( psa_cipher_operation_t *operation, goto exit; } - ret = mbedtls_cipher_update( &operation->ctx.cipher, input, - input_length, output, output_length ); - status = mbedtls_to_psa_error( ret ); + if( operation->alg == PSA_ALG_ECB_NO_PADDING ) + { + /* mbedtls_cipher_update has an API inconsistency: it will only + * process a single block at a time in ECB mode. Abstract away that + * inconsistency here to match the PSA API behaviour. */ + status = psa_cipher_update_ecb_internal( &operation->ctx.cipher, + input, + input_length, + output, + output_size, + output_length ); + } + else + { + status = mbedtls_to_psa_error( + mbedtls_cipher_update( &operation->ctx.cipher, input, + input_length, output, output_length ) ); + } exit: if( status != PSA_SUCCESS ) psa_cipher_abort( operation ); @@ -4296,10 +4746,8 @@ psa_status_t psa_cipher_finish( psa_cipher_operation_t *operation, size_t *output_length ) { psa_status_t status = PSA_ERROR_GENERIC_ERROR; - int cipher_ret = MBEDTLS_ERR_CIPHER_FEATURE_UNAVAILABLE; uint8_t temp_output_buffer[MBEDTLS_MAX_BLOCK_LENGTH]; - - if( ! operation->key_set ) + if( operation->alg == 0 ) { return( PSA_ERROR_BAD_STATE ); } @@ -4308,53 +4756,59 @@ psa_status_t psa_cipher_finish( psa_cipher_operation_t *operation, return( PSA_ERROR_BAD_STATE ); } - if( operation->ctx.cipher.operation == MBEDTLS_ENCRYPT && - operation->alg == PSA_ALG_CBC_NO_PADDING && - operation->ctx.cipher.unprocessed_len != 0 ) + if( operation->mbedtls_in_use == 0 ) { - status = PSA_ERROR_INVALID_ARGUMENT; - goto error; + status = psa_driver_wrapper_cipher_finish( &operation->ctx.driver, + output, + output_size, + output_length ); + goto exit; } - cipher_ret = mbedtls_cipher_finish( &operation->ctx.cipher, - temp_output_buffer, - output_length ); - if( cipher_ret != 0 ) + if( operation->ctx.cipher.unprocessed_len != 0 ) { - status = mbedtls_to_psa_error( cipher_ret ); - goto error; + if( operation->alg == PSA_ALG_ECB_NO_PADDING || + operation->alg == PSA_ALG_CBC_NO_PADDING ) + { + status = PSA_ERROR_INVALID_ARGUMENT; + goto exit; + } } + status = mbedtls_to_psa_error( + mbedtls_cipher_finish( &operation->ctx.cipher, + temp_output_buffer, + output_length ) ); + if( status != PSA_SUCCESS ) + goto exit; + if( *output_length == 0 ) ; /* Nothing to copy. Note that output may be NULL in this case. */ else if( output_size >= *output_length ) memcpy( output, temp_output_buffer, *output_length ); else - { status = PSA_ERROR_BUFFER_TOO_SMALL; - goto error; + +exit: + if( operation->mbedtls_in_use == 1 ) + mbedtls_platform_zeroize( temp_output_buffer, sizeof( temp_output_buffer ) ); + + if( status == PSA_SUCCESS ) + return( psa_cipher_abort( operation ) ); + else + { + *output_length = 0; + (void) psa_cipher_abort( operation ); + + return( status ); } - - mbedtls_platform_zeroize( temp_output_buffer, sizeof( temp_output_buffer ) ); - status = psa_cipher_abort( operation ); - - return( status ); - -error: - - *output_length = 0; - - mbedtls_platform_zeroize( temp_output_buffer, sizeof( temp_output_buffer ) ); - (void) psa_cipher_abort( operation ); - - return( status ); } psa_status_t psa_cipher_abort( psa_cipher_operation_t *operation ) { if( operation->alg == 0 ) { - /* The object has (apparently) been initialized but it is not + /* The object has (apparently) been initialized but it is not (yet) * in use. It's ok to call abort on such an object, and there's * nothing to do. */ return( PSA_SUCCESS ); @@ -4365,11 +4819,15 @@ psa_status_t psa_cipher_abort( psa_cipher_operation_t *operation ) if( ! PSA_ALG_IS_CIPHER( operation->alg ) ) return( PSA_ERROR_BAD_STATE ); - mbedtls_cipher_free( &operation->ctx.cipher ); + if( operation->mbedtls_in_use == 0 ) + psa_driver_wrapper_cipher_abort( &operation->ctx.driver ); + else + mbedtls_cipher_free( &operation->ctx.cipher ); operation->alg = 0; operation->key_set = 0; operation->iv_set = 0; + operation->mbedtls_in_use = 0; operation->iv_size = 0; operation->block_size = 0; operation->iv_required = 0; @@ -4390,6 +4848,7 @@ typedef struct const mbedtls_cipher_info_t *cipher_info; union { + unsigned dummy; /* Make the union non-empty even with no supported algorithms. */ #if defined(MBEDTLS_CCM_C) mbedtls_ccm_context ccm; #endif /* MBEDTLS_CCM_C */ @@ -4405,6 +4864,8 @@ typedef struct uint8_t tag_length; } aead_operation_t; +#define AEAD_OPERATION_INIT {0, 0, {0}, 0, 0, 0} + static void psa_aead_abort_internal( aead_operation_t *operation ) { switch( operation->core_alg ) @@ -4420,10 +4881,12 @@ static void psa_aead_abort_internal( aead_operation_t *operation ) break; #endif /* MBEDTLS_GCM_C */ } + + psa_unlock_key_slot( operation->slot ); } static psa_status_t psa_aead_setup( aead_operation_t *operation, - psa_key_handle_t handle, + mbedtls_svc_key_id_t key, psa_key_usage_t usage, psa_algorithm_t alg ) { @@ -4431,7 +4894,8 @@ static psa_status_t psa_aead_setup( aead_operation_t *operation, size_t key_bits; mbedtls_cipher_id_t cipher_id; - status = psa_get_transparent_key( handle, &operation->slot, usage, alg ); + status = psa_get_and_lock_transparent_key_slot_with_policy( + key, &operation->slot, usage, alg ); if( status != PSA_SUCCESS ) return( status ); @@ -4441,7 +4905,10 @@ static psa_status_t psa_aead_setup( aead_operation_t *operation, mbedtls_cipher_info_from_psa( alg, operation->slot->attr.type, key_bits, &cipher_id ); if( operation->cipher_info == NULL ) - return( PSA_ERROR_NOT_SUPPORTED ); + { + status = PSA_ERROR_NOT_SUPPORTED; + goto cleanup; + } switch( PSA_ALG_AEAD_WITH_TAG_LENGTH( alg, 0 ) ) { @@ -4453,7 +4920,10 @@ static psa_status_t psa_aead_setup( aead_operation_t *operation, * The call to mbedtls_ccm_encrypt_and_tag or * mbedtls_ccm_auth_decrypt will validate the tag length. */ if( PSA_BLOCK_CIPHER_BLOCK_SIZE( operation->slot->attr.type ) != 16 ) - return( PSA_ERROR_INVALID_ARGUMENT ); + { + status = PSA_ERROR_INVALID_ARGUMENT; + goto cleanup; + } mbedtls_ccm_init( &operation->ctx.ccm ); status = mbedtls_to_psa_error( mbedtls_ccm_setkey( &operation->ctx.ccm, cipher_id, @@ -4472,7 +4942,10 @@ static psa_status_t psa_aead_setup( aead_operation_t *operation, * The call to mbedtls_gcm_crypt_and_tag or * mbedtls_gcm_auth_decrypt will validate the tag length. */ if( PSA_BLOCK_CIPHER_BLOCK_SIZE( operation->slot->attr.type ) != 16 ) - return( PSA_ERROR_INVALID_ARGUMENT ); + { + status = PSA_ERROR_INVALID_ARGUMENT; + goto cleanup; + } mbedtls_gcm_init( &operation->ctx.gcm ); status = mbedtls_to_psa_error( mbedtls_gcm_setkey( &operation->ctx.gcm, cipher_id, @@ -4489,7 +4962,10 @@ static psa_status_t psa_aead_setup( aead_operation_t *operation, operation->full_tag_length = 16; /* We only support the default tag length. */ if( alg != PSA_ALG_CHACHA20_POLY1305 ) - return( PSA_ERROR_NOT_SUPPORTED ); + { + status = PSA_ERROR_NOT_SUPPORTED; + goto cleanup; + } mbedtls_chachapoly_init( &operation->ctx.chachapoly ); status = mbedtls_to_psa_error( mbedtls_chachapoly_setkey( &operation->ctx.chachapoly, @@ -4500,7 +4976,8 @@ static psa_status_t psa_aead_setup( aead_operation_t *operation, #endif /* MBEDTLS_CHACHAPOLY_C */ default: - return( PSA_ERROR_NOT_SUPPORTED ); + status = PSA_ERROR_NOT_SUPPORTED; + goto cleanup; } if( PSA_AEAD_TAG_LENGTH( alg ) > operation->full_tag_length ) @@ -4517,7 +4994,7 @@ cleanup: return( status ); } -psa_status_t psa_aead_encrypt( psa_key_handle_t handle, +psa_status_t psa_aead_encrypt( mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *nonce, size_t nonce_length, @@ -4530,12 +5007,12 @@ psa_status_t psa_aead_encrypt( psa_key_handle_t handle, size_t *ciphertext_length ) { psa_status_t status; - aead_operation_t operation; + aead_operation_t operation = AEAD_OPERATION_INIT; uint8_t *tag; *ciphertext_length = 0; - status = psa_aead_setup( &operation, handle, PSA_KEY_USAGE_ENCRYPT, alg ); + status = psa_aead_setup( &operation, key, PSA_KEY_USAGE_ENCRYPT, alg ); if( status != PSA_SUCCESS ) return( status ); @@ -4631,7 +5108,7 @@ static psa_status_t psa_aead_unpadded_locate_tag( size_t tag_length, return( PSA_SUCCESS ); } -psa_status_t psa_aead_decrypt( psa_key_handle_t handle, +psa_status_t psa_aead_decrypt( mbedtls_svc_key_id_t key, psa_algorithm_t alg, const uint8_t *nonce, size_t nonce_length, @@ -4644,12 +5121,12 @@ psa_status_t psa_aead_decrypt( psa_key_handle_t handle, size_t *plaintext_length ) { psa_status_t status; - aead_operation_t operation; + aead_operation_t operation = AEAD_OPERATION_INIT; const uint8_t *tag = NULL; *plaintext_length = 0; - status = psa_aead_setup( &operation, handle, PSA_KEY_USAGE_DECRYPT, alg ); + status = psa_aead_setup( &operation, key, PSA_KEY_USAGE_DECRYPT, alg ); if( status != PSA_SUCCESS ) return( status ); @@ -4727,6 +5204,12 @@ exit: /* Generators */ /****************************************************************/ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) +#define AT_LEAST_ONE_BUILTIN_KDF +#endif + #define HKDF_STATE_INIT 0 /* no input yet */ #define HKDF_STATE_STARTED 1 /* got salt */ #define HKDF_STATE_KEYED 2 /* got key */ @@ -4741,7 +5224,6 @@ static psa_algorithm_t psa_key_derivation_get_kdf_alg( return( operation->alg ); } - psa_status_t psa_key_derivation_abort( psa_key_derivation_operation_t *operation ) { psa_status_t status = PSA_SUCCESS; @@ -4753,13 +5235,17 @@ psa_status_t psa_key_derivation_abort( psa_key_derivation_operation_t *operation * nothing to do. */ } else -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) if( PSA_ALG_IS_HKDF( kdf_alg ) ) { mbedtls_free( operation->ctx.hkdf.info ); status = psa_hmac_abort_internal( &operation->ctx.hkdf.hmac ); } - else if( PSA_ALG_IS_TLS12_PRF( kdf_alg ) || + else +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) + if( PSA_ALG_IS_TLS12_PRF( kdf_alg ) || /* TLS-1.2 PSK-to-MS KDF uses the same core as TLS-1.2 PRF */ PSA_ALG_IS_TLS12_PSK_TO_MS( kdf_alg ) ) { @@ -4783,7 +5269,8 @@ psa_status_t psa_key_derivation_abort( psa_key_derivation_operation_t *operation * mbedtls_platform_zeroize() in the end of this function. */ } else -#endif /* MBEDTLS_MD_C */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || + * defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) */ { status = PSA_ERROR_BAD_STATE; } @@ -4815,7 +5302,7 @@ psa_status_t psa_key_derivation_set_capacity( psa_key_derivation_operation_t *op return( PSA_SUCCESS ); } -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) /* Read some bytes from an HKDF-based operation. This performs a chunk * of the expand phase of the HKDF algorithm. */ static psa_status_t psa_key_derivation_hkdf_read( psa_hkdf_key_derivation_t *hkdf, @@ -4884,7 +5371,10 @@ static psa_status_t psa_key_derivation_hkdf_read( psa_hkdf_key_derivation_t *hkd return( PSA_SUCCESS ); } +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) static psa_status_t psa_key_derivation_tls12_prf_generate_next_block( psa_tls12_prf_key_derivation_t *tls12_prf, psa_algorithm_t alg ) @@ -5031,7 +5521,8 @@ static psa_status_t psa_key_derivation_tls12_prf_read( return( PSA_SUCCESS ); } -#endif /* MBEDTLS_MD_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF || + * MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ psa_status_t psa_key_derivation_output_bytes( psa_key_derivation_operation_t *operation, @@ -5067,7 +5558,7 @@ psa_status_t psa_key_derivation_output_bytes( } operation->capacity -= output_length; -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) if( PSA_ALG_IS_HKDF( kdf_alg ) ) { psa_algorithm_t hash_alg = PSA_ALG_HKDF_GET_HASH( kdf_alg ); @@ -5075,15 +5566,19 @@ psa_status_t psa_key_derivation_output_bytes( output, output_length ); } else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) if( PSA_ALG_IS_TLS12_PRF( kdf_alg ) || - PSA_ALG_IS_TLS12_PSK_TO_MS( kdf_alg ) ) + PSA_ALG_IS_TLS12_PSK_TO_MS( kdf_alg ) ) { status = psa_key_derivation_tls12_prf_read( &operation->ctx.tls12_prf, kdf_alg, output, output_length ); } else -#endif /* MBEDTLS_MD_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF || + * MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ { return( PSA_ERROR_BAD_STATE ); } @@ -5148,12 +5643,14 @@ exit: psa_status_t psa_key_derivation_output_key( const psa_key_attributes_t *attributes, psa_key_derivation_operation_t *operation, - psa_key_handle_t *handle ) + mbedtls_svc_key_id_t *key ) { psa_status_t status; psa_key_slot_t *slot = NULL; psa_se_drv_table_entry_t *driver = NULL; + *key = MBEDTLS_SVC_KEY_ID_INIT; + /* Reject any attempt to create a zero-length key so that we don't * risk tripping up later, e.g. on a malloc(0) that returns NULL. */ if( psa_get_key_bits( attributes ) == 0 ) @@ -5162,8 +5659,8 @@ psa_status_t psa_key_derivation_output_key( const psa_key_attributes_t *attribut if( ! operation->can_output_key ) return( PSA_ERROR_NOT_PERMITTED ); - status = psa_start_key_creation( PSA_KEY_CREATION_DERIVE, - attributes, handle, &slot, &driver ); + status = psa_start_key_creation( PSA_KEY_CREATION_DERIVE, attributes, + &slot, &driver ); #if defined(MBEDTLS_PSA_CRYPTO_SE_C) if( driver != NULL ) { @@ -5178,12 +5675,10 @@ psa_status_t psa_key_derivation_output_key( const psa_key_attributes_t *attribut operation ); } if( status == PSA_SUCCESS ) - status = psa_finish_key_creation( slot, driver ); + status = psa_finish_key_creation( slot, driver, key ); if( status != PSA_SUCCESS ) - { psa_fail_key_creation( slot, driver ); - *handle = 0; - } + return( status ); } @@ -5193,19 +5688,36 @@ psa_status_t psa_key_derivation_output_key( const psa_key_attributes_t *attribut /* Key derivation */ /****************************************************************/ +#ifdef AT_LEAST_ONE_BUILTIN_KDF static psa_status_t psa_key_derivation_setup_kdf( psa_key_derivation_operation_t *operation, psa_algorithm_t kdf_alg ) { + int is_kdf_alg_supported; + /* Make sure that operation->ctx is properly zero-initialised. (Macro * initialisers for this union leave some bytes unspecified.) */ memset( &operation->ctx, 0, sizeof( operation->ctx ) ); /* Make sure that kdf_alg is a supported key derivation algorithm. */ -#if defined(MBEDTLS_MD_C) - if( PSA_ALG_IS_HKDF( kdf_alg ) || - PSA_ALG_IS_TLS12_PRF( kdf_alg ) || - PSA_ALG_IS_TLS12_PSK_TO_MS( kdf_alg ) ) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) + if( PSA_ALG_IS_HKDF( kdf_alg ) ) + is_kdf_alg_supported = 1; + else +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) + if( PSA_ALG_IS_TLS12_PRF( kdf_alg ) ) + is_kdf_alg_supported = 1; + else +#endif +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) + if( PSA_ALG_IS_TLS12_PSK_TO_MS( kdf_alg ) ) + is_kdf_alg_supported = 1; + else +#endif + is_kdf_alg_supported = 0; + + if( is_kdf_alg_supported ) { psa_algorithm_t hash_alg = PSA_ALG_HKDF_GET_HASH( kdf_alg ); size_t hash_size = PSA_HASH_SIZE( hash_alg ); @@ -5220,10 +5732,10 @@ static psa_status_t psa_key_derivation_setup_kdf( operation->capacity = 255 * hash_size; return( PSA_SUCCESS ); } -#endif /* MBEDTLS_MD_C */ - else - return( PSA_ERROR_NOT_SUPPORTED ); + + return( PSA_ERROR_NOT_SUPPORTED ); } +#endif /* AT_LEAST_ONE_BUILTIN_KDF */ psa_status_t psa_key_derivation_setup( psa_key_derivation_operation_t *operation, psa_algorithm_t alg ) @@ -5235,6 +5747,7 @@ psa_status_t psa_key_derivation_setup( psa_key_derivation_operation_t *operation if( PSA_ALG_IS_RAW_KEY_AGREEMENT( alg ) ) return( PSA_ERROR_INVALID_ARGUMENT ); +#ifdef AT_LEAST_ONE_BUILTIN_KDF else if( PSA_ALG_IS_KEY_AGREEMENT( alg ) ) { psa_algorithm_t kdf_alg = PSA_ALG_KEY_AGREEMENT_GET_KDF( alg ); @@ -5244,6 +5757,7 @@ psa_status_t psa_key_derivation_setup( psa_key_derivation_operation_t *operation { status = psa_key_derivation_setup_kdf( operation, alg ); } +#endif else return( PSA_ERROR_INVALID_ARGUMENT ); @@ -5252,7 +5766,7 @@ psa_status_t psa_key_derivation_setup( psa_key_derivation_operation_t *operation return( status ); } -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) static psa_status_t psa_hkdf_input( psa_hkdf_key_derivation_t *hkdf, psa_algorithm_t hash_alg, psa_key_derivation_step_t step, @@ -5317,7 +5831,10 @@ static psa_status_t psa_hkdf_input( psa_hkdf_key_derivation_t *hkdf, return( PSA_ERROR_INVALID_ARGUMENT ); } } +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || \ + defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) static psa_status_t psa_tls12_prf_set_seed( psa_tls12_prf_key_derivation_t *prf, const uint8_t *data, size_t data_length ) @@ -5358,41 +5875,6 @@ static psa_status_t psa_tls12_prf_set_key( psa_tls12_prf_key_derivation_t *prf, return( PSA_SUCCESS ); } -static psa_status_t psa_tls12_prf_psk_to_ms_set_key( - psa_tls12_prf_key_derivation_t *prf, - psa_algorithm_t hash_alg, - const uint8_t *data, - size_t data_length ) -{ - psa_status_t status; - uint8_t pms[ 4 + 2 * PSA_ALG_TLS12_PSK_TO_MS_MAX_PSK_LEN ]; - uint8_t *cur = pms; - - if( data_length > PSA_ALG_TLS12_PSK_TO_MS_MAX_PSK_LEN ) - return( PSA_ERROR_INVALID_ARGUMENT ); - - /* Quoting RFC 4279, Section 2: - * - * The premaster secret is formed as follows: if the PSK is N octets - * long, concatenate a uint16 with the value N, N zero octets, a second - * uint16 with the value N, and the PSK itself. - */ - - *cur++ = ( data_length >> 8 ) & 0xff; - *cur++ = ( data_length >> 0 ) & 0xff; - memset( cur, 0, data_length ); - cur += data_length; - *cur++ = pms[0]; - *cur++ = pms[1]; - memcpy( cur, data, data_length ); - cur += data_length; - - status = psa_tls12_prf_set_key( prf, hash_alg, pms, cur - pms ); - - mbedtls_platform_zeroize( pms, sizeof( pms ) ); - return( status ); -} - static psa_status_t psa_tls12_prf_set_label( psa_tls12_prf_key_derivation_t *prf, const uint8_t *data, size_t data_length ) @@ -5433,6 +5915,44 @@ static psa_status_t psa_tls12_prf_input( psa_tls12_prf_key_derivation_t *prf, return( PSA_ERROR_INVALID_ARGUMENT ); } } +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) || + * MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ + +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) +static psa_status_t psa_tls12_prf_psk_to_ms_set_key( + psa_tls12_prf_key_derivation_t *prf, + psa_algorithm_t hash_alg, + const uint8_t *data, + size_t data_length ) +{ + psa_status_t status; + uint8_t pms[ 4 + 2 * PSA_ALG_TLS12_PSK_TO_MS_MAX_PSK_LEN ]; + uint8_t *cur = pms; + + if( data_length > PSA_ALG_TLS12_PSK_TO_MS_MAX_PSK_LEN ) + return( PSA_ERROR_INVALID_ARGUMENT ); + + /* Quoting RFC 4279, Section 2: + * + * The premaster secret is formed as follows: if the PSK is N octets + * long, concatenate a uint16 with the value N, N zero octets, a second + * uint16 with the value N, and the PSK itself. + */ + + *cur++ = ( data_length >> 8 ) & 0xff; + *cur++ = ( data_length >> 0 ) & 0xff; + memset( cur, 0, data_length ); + cur += data_length; + *cur++ = pms[0]; + *cur++ = pms[1]; + memcpy( cur, data, data_length ); + cur += data_length; + + status = psa_tls12_prf_set_key( prf, hash_alg, pms, cur - pms ); + + mbedtls_platform_zeroize( pms, sizeof( pms ) ); + return( status ); +} static psa_status_t psa_tls12_prf_psk_to_ms_input( psa_tls12_prf_key_derivation_t *prf, @@ -5449,7 +5969,7 @@ static psa_status_t psa_tls12_prf_psk_to_ms_input( return( psa_tls12_prf_input( prf, hash_alg, step, data, data_length ) ); } -#endif /* MBEDTLS_MD_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ /** Check whether the given key type is acceptable for the given * input step of a key derivation. @@ -5499,27 +6019,33 @@ static psa_status_t psa_key_derivation_input_internal( if( status != PSA_SUCCESS ) goto exit; -#if defined(MBEDTLS_MD_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_HKDF) if( PSA_ALG_IS_HKDF( kdf_alg ) ) { status = psa_hkdf_input( &operation->ctx.hkdf, PSA_ALG_HKDF_GET_HASH( kdf_alg ), step, data, data_length ); } - else if( PSA_ALG_IS_TLS12_PRF( kdf_alg ) ) + else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_HKDF */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF) + if( PSA_ALG_IS_TLS12_PRF( kdf_alg ) ) { status = psa_tls12_prf_input( &operation->ctx.tls12_prf, PSA_ALG_HKDF_GET_HASH( kdf_alg ), step, data, data_length ); } - else if( PSA_ALG_IS_TLS12_PSK_TO_MS( kdf_alg ) ) + else +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PRF */ +#if defined(MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS) + if( PSA_ALG_IS_TLS12_PSK_TO_MS( kdf_alg ) ) { status = psa_tls12_prf_psk_to_ms_input( &operation->ctx.tls12_prf, PSA_ALG_HKDF_GET_HASH( kdf_alg ), step, data, data_length ); } else -#endif /* MBEDTLS_MD_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_TLS12_PSK_TO_MS */ { /* This can't happen unless the operation object was not initialized */ return( PSA_ERROR_BAD_STATE ); @@ -5545,14 +6071,14 @@ psa_status_t psa_key_derivation_input_bytes( psa_status_t psa_key_derivation_input_key( psa_key_derivation_operation_t *operation, psa_key_derivation_step_t step, - psa_key_handle_t handle ) + mbedtls_svc_key_id_t key ) { + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; psa_key_slot_t *slot; - psa_status_t status; - status = psa_get_transparent_key( handle, &slot, - PSA_KEY_USAGE_DERIVE, - operation->alg ); + status = psa_get_and_lock_transparent_key_slot_with_policy( + key, &slot, PSA_KEY_USAGE_DERIVE, operation->alg ); if( status != PSA_SUCCESS ) { psa_key_derivation_abort( operation ); @@ -5564,10 +6090,14 @@ psa_status_t psa_key_derivation_input_key( if( step == PSA_KEY_DERIVATION_INPUT_SECRET ) operation->can_output_key = 1; - return( psa_key_derivation_input_internal( operation, - step, slot->attr.type, - slot->data.key.data, - slot->data.key.bytes ) ); + status = psa_key_derivation_input_internal( operation, + step, slot->attr.type, + slot->data.key.data, + slot->data.key.bytes ); + + unlock_status = psa_unlock_key_slot( slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); } @@ -5576,7 +6106,7 @@ psa_status_t psa_key_derivation_input_key( /* Key agreement */ /****************************************************************/ -#if defined(MBEDTLS_ECDH_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDH) static psa_status_t psa_key_agreement_ecdh( const uint8_t *peer_key, size_t peer_key_length, const mbedtls_ecp_keypair *our_key, @@ -5627,7 +6157,7 @@ exit: return( status ); } -#endif /* MBEDTLS_ECDH_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_ECDH */ #define PSA_KEY_AGREEMENT_MAX_SHARED_SECRET_SIZE MBEDTLS_ECP_MAX_BYTES @@ -5641,7 +6171,7 @@ static psa_status_t psa_key_agreement_raw_internal( psa_algorithm_t alg, { switch( alg ) { -#if defined(MBEDTLS_ECDH_C) +#if defined(MBEDTLS_PSA_BUILTIN_ALG_ECDH) case PSA_ALG_ECDH: if( ! PSA_KEY_TYPE_IS_ECC_KEY_PAIR( private_key->attr.type ) ) return( PSA_ERROR_INVALID_ARGUMENT ); @@ -5660,7 +6190,7 @@ static psa_status_t psa_key_agreement_raw_internal( psa_algorithm_t alg, mbedtls_ecp_keypair_free( ecp ); mbedtls_free( ecp ); return( status ); -#endif /* MBEDTLS_ECDH_C */ +#endif /* MBEDTLS_PSA_BUILTIN_ALG_ECDH */ default: (void) private_key; (void) peer_key; @@ -5704,7 +6234,6 @@ static psa_status_t psa_key_agreement_internal( psa_key_derivation_operation_t * PSA_KEY_TYPE_DERIVE, shared_secret, shared_secret_length ); - exit: mbedtls_platform_zeroize( shared_secret, shared_secret_length ); return( status ); @@ -5712,16 +6241,18 @@ exit: psa_status_t psa_key_derivation_key_agreement( psa_key_derivation_operation_t *operation, psa_key_derivation_step_t step, - psa_key_handle_t private_key, + mbedtls_svc_key_id_t private_key, const uint8_t *peer_key, size_t peer_key_length ) { + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; psa_key_slot_t *slot; - psa_status_t status; + if( ! PSA_ALG_IS_KEY_AGREEMENT( operation->alg ) ) return( PSA_ERROR_INVALID_ARGUMENT ); - status = psa_get_transparent_key( private_key, &slot, - PSA_KEY_USAGE_DERIVE, operation->alg ); + status = psa_get_and_lock_transparent_key_slot_with_policy( + private_key, &slot, PSA_KEY_USAGE_DERIVE, operation->alg ); if( status != PSA_SUCCESS ) return( status ); status = psa_key_agreement_internal( operation, step, @@ -5729,27 +6260,38 @@ psa_status_t psa_key_derivation_key_agreement( psa_key_derivation_operation_t *o peer_key, peer_key_length ); if( status != PSA_SUCCESS ) psa_key_derivation_abort( operation ); - return( status ); + else + { + /* If a private key has been added as SECRET, we allow the derived + * key material to be used as a key in PSA Crypto. */ + if( step == PSA_KEY_DERIVATION_INPUT_SECRET ) + operation->can_output_key = 1; + } + + unlock_status = psa_unlock_key_slot( slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); } psa_status_t psa_raw_key_agreement( psa_algorithm_t alg, - psa_key_handle_t private_key, + mbedtls_svc_key_id_t private_key, const uint8_t *peer_key, size_t peer_key_length, uint8_t *output, size_t output_size, size_t *output_length ) { - psa_key_slot_t *slot; - psa_status_t status; + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_status_t unlock_status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_slot_t *slot = NULL; if( ! PSA_ALG_IS_KEY_AGREEMENT( alg ) ) { status = PSA_ERROR_INVALID_ARGUMENT; goto exit; } - status = psa_get_transparent_key( private_key, &slot, - PSA_KEY_USAGE_DERIVE, alg ); + status = psa_get_and_lock_transparent_key_slot_with_policy( + private_key, &slot, PSA_KEY_USAGE_DERIVE, alg ); if( status != PSA_SUCCESS ) goto exit; @@ -5771,7 +6313,10 @@ exit: psa_generate_random( output, output_size ); *output_length = output_size; } - return( status ); + + unlock_status = psa_unlock_key_slot( slot ); + + return( ( status == PSA_SUCCESS ) ? unlock_status : status ); } @@ -5818,7 +6363,7 @@ psa_status_t mbedtls_psa_inject_entropy( const uint8_t *seed, } #endif /* MBEDTLS_PSA_INJECT_ENTROPY */ -#if defined(MBEDTLS_RSA_C) && defined(MBEDTLS_GENPRIME) +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) static psa_status_t psa_read_rsa_exponent( const uint8_t *domain_parameters, size_t domain_parameters_size, int *exponent ) @@ -5844,7 +6389,7 @@ static psa_status_t psa_read_rsa_exponent( const uint8_t *domain_parameters, *exponent = acc; return( PSA_SUCCESS ); } -#endif /* MBEDTLS_RSA_C && MBEDTLS_GENPRIME */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) */ static psa_status_t psa_generate_key_internal( psa_key_slot_t *slot, size_t bits, @@ -5882,7 +6427,7 @@ static psa_status_t psa_generate_key_internal( } else -#if defined(MBEDTLS_RSA_C) && defined(MBEDTLS_GENPRIME) +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) if ( type == PSA_KEY_TYPE_RSA_KEY_PAIR ) { mbedtls_rsa_context rsa; @@ -5930,9 +6475,9 @@ static psa_status_t psa_generate_key_internal( return( status ); } else -#endif /* MBEDTLS_RSA_C && MBEDTLS_GENPRIME */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_RSA_KEY_PAIR) */ -#if defined(MBEDTLS_ECP_C) +#if defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) if ( PSA_KEY_TYPE_IS_ECC( type ) && PSA_KEY_TYPE_IS_KEY_PAIR( type ) ) { psa_ecc_family_t curve = PSA_KEY_TYPE_ECC_GET_FAMILY( type ); @@ -5946,8 +6491,6 @@ static psa_status_t psa_generate_key_internal( return( PSA_ERROR_NOT_SUPPORTED ); if( grp_id == MBEDTLS_ECP_DP_NONE || curve_info == NULL ) return( PSA_ERROR_NOT_SUPPORTED ); - if( curve_info->bit_size != bits ) - return( PSA_ERROR_INVALID_ARGUMENT ); mbedtls_ecp_keypair_init( &ecp ); ret = mbedtls_ecp_gen_key( grp_id, &ecp, mbedtls_ctr_drbg_random, @@ -5979,7 +6522,7 @@ static psa_status_t psa_generate_key_internal( return( status ); } else -#endif /* MBEDTLS_ECP_C */ +#endif /* defined(MBEDTLS_PSA_BUILTIN_KEY_TYPE_ECC_KEY_PAIR) */ { return( PSA_ERROR_NOT_SUPPORTED ); } @@ -5988,54 +6531,40 @@ static psa_status_t psa_generate_key_internal( } psa_status_t psa_generate_key( const psa_key_attributes_t *attributes, - psa_key_handle_t *handle ) + mbedtls_svc_key_id_t *key ) { psa_status_t status; psa_key_slot_t *slot = NULL; psa_se_drv_table_entry_t *driver = NULL; + *key = MBEDTLS_SVC_KEY_ID_INIT; + /* Reject any attempt to create a zero-length key so that we don't * risk tripping up later, e.g. on a malloc(0) that returns NULL. */ if( psa_get_key_bits( attributes ) == 0 ) return( PSA_ERROR_INVALID_ARGUMENT ); - status = psa_start_key_creation( PSA_KEY_CREATION_GENERATE, - attributes, handle, &slot, &driver ); + status = psa_start_key_creation( PSA_KEY_CREATION_GENERATE, attributes, + &slot, &driver ); if( status != PSA_SUCCESS ) goto exit; -#if defined(MBEDTLS_PSA_CRYPTO_SE_C) - if( driver != NULL ) - { - const psa_drv_se_t *drv = psa_get_se_driver_methods( driver ); - size_t pubkey_length = 0; /* We don't support this feature yet */ - if( drv->key_management == NULL || - drv->key_management->p_generate == NULL ) - { - status = PSA_ERROR_NOT_SUPPORTED; - goto exit; - } - status = drv->key_management->p_generate( - psa_get_se_driver_context( driver ), - slot->data.se.slot_number, attributes, - NULL, 0, &pubkey_length ); - } - else -#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ - { - status = psa_generate_key_internal( - slot, attributes->core.bits, - attributes->domain_parameters, attributes->domain_parameters_size ); - } + status = psa_driver_wrapper_generate_key( attributes, + slot ); + if( status != PSA_ERROR_NOT_SUPPORTED || + psa_key_lifetime_is_external( attributes->core.lifetime ) ) + goto exit; + + status = psa_generate_key_internal( + slot, attributes->core.bits, + attributes->domain_parameters, attributes->domain_parameters_size ); exit: if( status == PSA_SUCCESS ) - status = psa_finish_key_creation( slot, driver ); + status = psa_finish_key_creation( slot, driver, key ); if( status != PSA_SUCCESS ) - { psa_fail_key_creation( slot, driver ); - *handle = 0; - } + return( status ); } diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_core.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_core.h index 9a61babb50..f61ef9550d 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_core.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_core.h @@ -36,6 +36,32 @@ typedef struct { psa_core_key_attributes_t attr; + + /* + * Number of locks on the key slot held by the library. + * + * This counter is incremented by one each time a library function + * retrieves through one of the dedicated internal API a pointer to the + * key slot. + * + * This counter is decremented by one each time a library function stops + * accessing the key slot and states it by calling the + * psa_unlock_key_slot() API. + * + * This counter is used to prevent resetting the key slot while the library + * may access it. For example, such control is needed in the following + * scenarios: + * . In case of key slot starvation, all key slots contain the description + * of a key, and the library asks for the description of a persistent + * key not present in the key slots, the key slots currently accessed by + * the library cannot be reclaimed to free a key slot to load the + * persistent key. + * . In case of a multi-threaded application where one thread asks to close + * or purge or destroy a key while it is in used by the library through + * another thread. + */ + size_t lock_count; + union { /* Dynamically allocated key data buffer. @@ -74,6 +100,19 @@ static inline int psa_is_key_slot_occupied( const psa_key_slot_t *slot ) return( slot->attr.type != 0 ); } +/** Test whether a key slot is locked. + * + * A key slot is locked iff its lock counter is strictly greater than 0. + * + * \param[in] slot The key slot to test. + * + * \return 1 if the slot is locked, 0 otherwise. + */ +static inline int psa_is_key_slot_locked( const psa_key_slot_t *slot ) +{ + return( slot->lock_count > 0 ); +} + /** Retrieve flags from psa_key_slot_t::attr::core::flags. * * \param[in] slot The key slot to query. @@ -130,35 +169,43 @@ static inline void psa_key_slot_clear_bits( psa_key_slot_t *slot, * * \param[in,out] slot The key slot to wipe. * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * Success. This includes the case of a key slot that was * already fully wiped. - * \retval PSA_ERROR_CORRUPTION_DETECTED + * \retval #PSA_ERROR_CORRUPTION_DETECTED */ psa_status_t psa_wipe_key_slot( psa_key_slot_t *slot ); -/** Import key data into a slot. +/** Copy key data (in export format) into an empty key slot. * - * `slot->type` must have been set previously. - * This function assumes that the slot does not contain any key material yet. - * On failure, the slot content is unchanged. + * This function assumes that the slot does not contain + * any key material yet. On failure, the slot content is unchanged. * - * Persistent storage is not affected. + * \param[in,out] slot Key slot to copy the key into. + * \param[in] data Buffer containing the key material. + * \param data_length Size of the key buffer. * - * \param[in,out] slot The key slot to import data into. - * Its `type` field must have previously been set to - * the desired key type. - * It must not contain any key material yet. - * \param[in] data Buffer containing the key material to parse and import. - * \param data_length Size of \p data in bytes. - * - * \retval PSA_SUCCESS - * \retval PSA_ERROR_INVALID_ARGUMENT - * \retval PSA_ERROR_NOT_SUPPORTED - * \retval PSA_ERROR_INSUFFICIENT_MEMORY + * \retval #PSA_SUCCESS + * The key has been copied successfully. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * Not enough memory was available for allocation of the + * copy buffer. + * \retval #PSA_ERROR_ALREADY_EXISTS + * There was other key material already present in the slot. */ -psa_status_t psa_import_key_into_slot( psa_key_slot_t *slot, - const uint8_t *data, - size_t data_length ); +psa_status_t psa_copy_key_material_into_slot( psa_key_slot_t *slot, + const uint8_t *data, + size_t data_length ); + +/** Convert an mbed TLS error code to a PSA error code + * + * \note This function is provided solely for the convenience of + * Mbed TLS and may be removed at any time without notice. + * + * \param ret An mbed TLS-thrown error code + * + * \return The corresponding PSA error code + */ +psa_status_t mbedtls_to_psa_error( int ret ); #endif /* PSA_CRYPTO_CORE_H */ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_driver_wrappers.c b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_driver_wrappers.c new file mode 100644 index 0000000000..c3ea6f1423 --- /dev/null +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_driver_wrappers.c @@ -0,0 +1,993 @@ +/* + * Functions to delegate cryptographic operations to an available + * and appropriate accelerator. + * Warning: This file will be auto-generated in the future. + */ +/* Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "psa_crypto_core.h" +#include "psa_crypto_driver_wrappers.h" +#include "mbedtls/platform.h" + +#if defined(MBEDTLS_PSA_CRYPTO_DRIVERS) + +/* Include test driver definition when running tests */ +#if defined(PSA_CRYPTO_DRIVER_TEST) +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#ifndef PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#define PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT +#endif +#include "test/drivers/test_driver.h" +#endif /* PSA_CRYPTO_DRIVER_TEST */ + +/* Repeat above block for each JSON-declared driver during autogeneration */ + +/* Auto-generated values depending on which drivers are registered. ID 0 is + * reserved for unallocated operations. */ +#if defined(PSA_CRYPTO_DRIVER_TEST) +#define PSA_CRYPTO_TRANSPARENT_TEST_DRIVER_ID (1) +#define PSA_CRYPTO_OPAQUE_TEST_DRIVER_ID (2) +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#endif /* MBEDTLS_PSA_CRYPTO_DRIVERS */ + +/* Support the 'old' SE interface when asked to */ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) +/* PSA_CRYPTO_DRIVER_PRESENT is defined when either a new-style or old-style + * SE driver is present, to avoid unused argument errors at compile time. */ +#ifndef PSA_CRYPTO_DRIVER_PRESENT +#define PSA_CRYPTO_DRIVER_PRESENT +#endif +#include "psa_crypto_se.h" +#endif + +/* Start delegation functions */ +psa_status_t psa_driver_wrapper_sign_hash( psa_key_slot_t *slot, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length ) +{ +#if defined(PSA_CRYPTO_DRIVER_PRESENT) + /* Try dynamically-registered SE interface first */ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + const psa_drv_se_t *drv; + psa_drv_se_context_t *drv_context; + + if( psa_get_se_driver( slot->attr.lifetime, &drv, &drv_context ) ) + { + if( drv->asymmetric == NULL || + drv->asymmetric->p_sign == NULL ) + { + /* Key is defined in SE, but we have no way to exercise it */ + return( PSA_ERROR_NOT_SUPPORTED ); + } + return( drv->asymmetric->p_sign( drv_context, + slot->data.se.slot_number, + alg, + hash, hash_length, + signature, signature_size, + signature_length ) ); + } +#endif /* PSA_CRYPTO_SE_C */ + + /* Then try accelerator API */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION(slot->attr.lifetime); + psa_key_attributes_t attributes = { + .core = slot->attr + }; + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = test_transparent_signature_sign_hash( &attributes, + slot->data.key.data, + slot->data.key.bytes, + alg, + hash, + hash_length, + signature, + signature_size, + signature_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + /* Fell through, meaning no accelerator supports this operation */ + return( PSA_ERROR_NOT_SUPPORTED ); + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LIFETIME: + return( test_opaque_signature_sign_hash( &attributes, + slot->data.key.data, + slot->data.key.bytes, + alg, + hash, + hash_length, + signature, + signature_size, + signature_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + default: + /* Key is declared with a lifetime not known to us */ + return( status ); + } +#else /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ +#else /* PSA_CRYPTO_DRIVER_PRESENT */ + (void)slot; + (void)alg; + (void)hash; + (void)hash_length; + (void)signature; + (void)signature_size; + (void)signature_length; + + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_PRESENT */ +} + +psa_status_t psa_driver_wrapper_verify_hash( psa_key_slot_t *slot, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length ) +{ +#if defined(PSA_CRYPTO_DRIVER_PRESENT) + /* Try dynamically-registered SE interface first */ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + const psa_drv_se_t *drv; + psa_drv_se_context_t *drv_context; + + if( psa_get_se_driver( slot->attr.lifetime, &drv, &drv_context ) ) + { + if( drv->asymmetric == NULL || + drv->asymmetric->p_verify == NULL ) + { + /* Key is defined in SE, but we have no way to exercise it */ + return( PSA_ERROR_NOT_SUPPORTED ); + } + return( drv->asymmetric->p_verify( drv_context, + slot->data.se.slot_number, + alg, + hash, hash_length, + signature, signature_length ) ); + } +#endif /* PSA_CRYPTO_SE_C */ + + /* Then try accelerator API */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION(slot->attr.lifetime); + psa_key_attributes_t attributes = { + .core = slot->attr + }; + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = test_transparent_signature_verify_hash( &attributes, + slot->data.key.data, + slot->data.key.bytes, + alg, + hash, + hash_length, + signature, + signature_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + /* Fell through, meaning no accelerator supports this operation */ + return( PSA_ERROR_NOT_SUPPORTED ); + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LIFETIME: + return( test_opaque_signature_verify_hash( &attributes, + slot->data.key.data, + slot->data.key.bytes, + alg, + hash, + hash_length, + signature, + signature_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + default: + /* Key is declared with a lifetime not known to us */ + return( status ); + } +#else /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ +#else /* PSA_CRYPTO_DRIVER_PRESENT */ + (void)slot; + (void)alg; + (void)hash; + (void)hash_length; + (void)signature; + (void)signature_length; + + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_PRESENT */ +} + +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) +/** Calculate the size to allocate for buffering a key with given attributes. + * + * This function provides a way to get the expected size for storing a key with + * the given attributes. This will be the size of the export representation for + * cleartext keys, and a driver-defined size for keys stored by opaque drivers. + * + * \param[in] attributes The key attribute structure of the key to store. + * \param[out] expected_size On success, a byte size large enough to contain + * the declared key. + * + * \retval #PSA_SUCCESS + * \retval #PSA_ERROR_NOT_SUPPORTED + */ +static psa_status_t get_expected_key_size( const psa_key_attributes_t *attributes, + size_t *expected_size ) +{ + size_t buffer_size = 0; + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION( attributes->core.lifetime ); + psa_key_type_t key_type = attributes->core.type; + size_t key_bits = attributes->core.bits; + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + buffer_size = PSA_KEY_EXPORT_MAX_SIZE( key_type, key_bits ); + + if( buffer_size == 0 ) + return( PSA_ERROR_NOT_SUPPORTED ); + + *expected_size = buffer_size; + return( PSA_SUCCESS ); + +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LIFETIME: +#ifdef TEST_DRIVER_KEY_CONTEXT_SIZE_FUNCTION + *expected_size = test_size_function( key_type, key_bits ); + return( PSA_SUCCESS ); +#else /* TEST_DRIVER_KEY_CONTEXT_SIZE_FUNCTION */ + if( PSA_KEY_TYPE_IS_KEY_PAIR( key_type ) ) + { + int public_key_overhead = ( ( TEST_DRIVER_KEY_CONTEXT_STORE_PUBLIC_KEY == 1 ) ? + PSA_KEY_EXPORT_MAX_SIZE( key_type, key_bits ) : 0 ); + *expected_size = TEST_DRIVER_KEY_CONTEXT_BASE_SIZE + + TEST_DRIVER_KEY_CONTEXT_PUBLIC_KEY_SIZE + + public_key_overhead; + } + else if( PSA_KEY_TYPE_IS_PUBLIC_KEY( attributes->core.type ) ) + { + *expected_size = TEST_DRIVER_KEY_CONTEXT_BASE_SIZE + + TEST_DRIVER_KEY_CONTEXT_PUBLIC_KEY_SIZE; + } + else if ( !PSA_KEY_TYPE_IS_KEY_PAIR( key_type ) && + !PSA_KEY_TYPE_IS_PUBLIC_KEY ( attributes->core.type ) ) + { + *expected_size = TEST_DRIVER_KEY_CONTEXT_BASE_SIZE + + TEST_DRIVER_KEY_CONTEXT_SYMMETRIC_FACTOR + * ( ( key_bits + 7 ) / 8 ); + } + else + { + return( PSA_ERROR_NOT_SUPPORTED ); + } + return( PSA_SUCCESS ); +#endif /* TEST_DRIVER_KEY_CONTEXT_SIZE_FUNCTION */ +#endif /* PSA_CRYPTO_DRIVER_TEST */ + + default: + return( PSA_ERROR_NOT_SUPPORTED ); + } +} +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + +psa_status_t psa_driver_wrapper_generate_key( const psa_key_attributes_t *attributes, + psa_key_slot_t *slot ) +{ +#if defined(PSA_CRYPTO_DRIVER_PRESENT) + /* Try dynamically-registered SE interface first */ +#if defined(MBEDTLS_PSA_CRYPTO_SE_C) + const psa_drv_se_t *drv; + psa_drv_se_context_t *drv_context; + + if( psa_get_se_driver( slot->attr.lifetime, &drv, &drv_context ) ) + { + size_t pubkey_length = 0; /* We don't support this feature yet */ + if( drv->key_management == NULL || + drv->key_management->p_generate == NULL ) + { + /* Key is defined as being in SE, but we have no way to generate it */ + return( PSA_ERROR_NOT_SUPPORTED ); + } + return( drv->key_management->p_generate( + drv_context, + slot->data.se.slot_number, attributes, + NULL, 0, &pubkey_length ) ); + } +#endif /* MBEDTLS_PSA_CRYPTO_SE_C */ + + /* Then try accelerator API */ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION(slot->attr.lifetime); + size_t export_size = 0; + + status = get_expected_key_size( attributes, &export_size ); + if( status != PSA_SUCCESS ) + return( status ); + + slot->data.key.data = mbedtls_calloc(1, export_size); + if( slot->data.key.data == NULL ) + return( PSA_ERROR_INSUFFICIENT_MEMORY ); + slot->data.key.bytes = export_size; + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ + + /* Transparent drivers are limited to generating asymmetric keys */ + if( ! PSA_KEY_TYPE_IS_ASYMMETRIC( slot->attr.type ) ) + { + status = PSA_ERROR_NOT_SUPPORTED; + break; + } +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = test_transparent_generate_key( attributes, + slot->data.key.data, + slot->data.key.bytes, + &slot->data.key.bytes ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + break; +#endif /* PSA_CRYPTO_DRIVER_TEST */ + /* Fell through, meaning no accelerator supports this operation */ + status = PSA_ERROR_NOT_SUPPORTED; + break; + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LIFETIME: + status = test_opaque_generate_key( attributes, + slot->data.key.data, + slot->data.key.bytes, + &slot->data.key.bytes ); + break; +#endif /* PSA_CRYPTO_DRIVER_TEST */ + default: + /* Key is declared with a lifetime not known to us */ + status = PSA_ERROR_INVALID_ARGUMENT; + break; + } + + if( status != PSA_SUCCESS ) + { + /* free allocated buffer */ + mbedtls_free( slot->data.key.data ); + slot->data.key.data = NULL; + slot->data.key.bytes = 0; + } + + return( status ); +#else /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ +#else /* PSA_CRYPTO_DRIVER_PRESENT */ + (void) attributes; + (void) slot; + + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_PRESENT */ +} + +psa_status_t psa_driver_wrapper_validate_key( const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + size_t *bits ) +{ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + /* Try accelerators in turn */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = test_transparent_validate_key( attributes, + data, + data_length, + bits ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + + return( PSA_ERROR_NOT_SUPPORTED ); +#else /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + (void) attributes; + (void) data; + (void) data_length; + (void) bits; + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_PRESENT */ +} + +psa_status_t psa_driver_wrapper_export_public_key( const psa_key_slot_t *slot, + uint8_t *data, + size_t data_size, + size_t *data_length ) +{ +#if defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION(slot->attr.lifetime); + psa_key_attributes_t attributes = { + .core = slot->attr + }; + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = test_transparent_export_public_key( &attributes, + slot->data.key.data, + slot->data.key.bytes, + data, + data_size, + data_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + /* Fell through, meaning no accelerator supports this operation */ + return( PSA_ERROR_NOT_SUPPORTED ); + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LIFETIME: + return( test_opaque_export_public_key( &attributes, + slot->data.key.data, + slot->data.key.bytes, + data, + data_size, + data_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + default: + /* Key is declared with a lifetime not known to us */ + return( status ); + } +#else /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ + (void) slot; + (void) data; + (void) data_size; + (void) data_length; + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT */ +} + +/* + * Cipher functions + */ +psa_status_t psa_driver_wrapper_cipher_encrypt( + psa_key_slot_t *slot, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length ) +{ +#if defined(PSA_CRYPTO_DRIVER_PRESENT) && defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION(slot->attr.lifetime); + psa_key_attributes_t attributes = { + .core = slot->attr + }; + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = test_transparent_cipher_encrypt( &attributes, + slot->data.key.data, + slot->data.key.bytes, + alg, + input, + input_length, + output, + output_size, + output_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + /* Fell through, meaning no accelerator supports this operation */ + return( PSA_ERROR_NOT_SUPPORTED ); + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LIFETIME: + return( test_opaque_cipher_encrypt( &attributes, + slot->data.key.data, + slot->data.key.bytes, + alg, + input, + input_length, + output, + output_size, + output_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + default: + /* Key is declared with a lifetime not known to us */ + return( status ); + } +#else /* PSA_CRYPTO_DRIVER_PRESENT */ + (void) slot; + (void) alg; + (void) input; + (void) input_length; + (void) output; + (void) output_size; + (void) output_length; + + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_PRESENT */ +} + +psa_status_t psa_driver_wrapper_cipher_decrypt( + psa_key_slot_t *slot, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length ) +{ +#if defined(PSA_CRYPTO_DRIVER_PRESENT) && defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION(slot->attr.lifetime); + psa_key_attributes_t attributes = { + .core = slot->attr + }; + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + status = test_transparent_cipher_decrypt( &attributes, + slot->data.key.data, + slot->data.key.bytes, + alg, + input, + input_length, + output, + output_size, + output_length ); + /* Declared with fallback == true */ + if( status != PSA_ERROR_NOT_SUPPORTED ) + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + /* Fell through, meaning no accelerator supports this operation */ + return( PSA_ERROR_NOT_SUPPORTED ); + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LIFETIME: + return( test_opaque_cipher_decrypt( &attributes, + slot->data.key.data, + slot->data.key.bytes, + alg, + input, + input_length, + output, + output_size, + output_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + default: + /* Key is declared with a lifetime not known to us */ + return( status ); + } +#else /* PSA_CRYPTO_DRIVER_PRESENT */ + (void) slot; + (void) alg; + (void) input; + (void) input_length; + (void) output; + (void) output_size; + (void) output_length; + + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_PRESENT */ +} + +psa_status_t psa_driver_wrapper_cipher_encrypt_setup( + psa_operation_driver_context_t *operation, + psa_key_slot_t *slot, + psa_algorithm_t alg ) +{ +#if defined(PSA_CRYPTO_DRIVER_PRESENT) && defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION(slot->attr.lifetime); + psa_key_attributes_t attributes = { + .core = slot->attr + }; + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + operation->ctx = mbedtls_calloc( 1, sizeof(test_transparent_cipher_operation_t) ); + if( operation->ctx == NULL ) + return PSA_ERROR_INSUFFICIENT_MEMORY; + + status = test_transparent_cipher_encrypt_setup( operation->ctx, + &attributes, + slot->data.key.data, + slot->data.key.bytes, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = PSA_CRYPTO_TRANSPARENT_TEST_DRIVER_ID; + else + { + mbedtls_platform_zeroize( + operation->ctx, + sizeof( test_transparent_cipher_operation_t ) ); + mbedtls_free( operation->ctx ); + operation->ctx = NULL; + } + + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + /* Fell through, meaning no accelerator supports this operation */ + return( PSA_ERROR_NOT_SUPPORTED ); + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LIFETIME: + operation->ctx = mbedtls_calloc( 1, sizeof(test_opaque_cipher_operation_t) ); + if( operation->ctx == NULL ) + return( PSA_ERROR_INSUFFICIENT_MEMORY ); + + status = test_opaque_cipher_encrypt_setup( operation->ctx, + &attributes, + slot->data.key.data, + slot->data.key.bytes, + alg ); + if( status == PSA_SUCCESS ) + operation->id = PSA_CRYPTO_OPAQUE_TEST_DRIVER_ID; + else + { + mbedtls_platform_zeroize( + operation->ctx, + sizeof( test_opaque_cipher_operation_t ) ); + mbedtls_free( operation->ctx ); + operation->ctx = NULL; + } + + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + default: + /* Key is declared with a lifetime not known to us */ + return( PSA_ERROR_NOT_SUPPORTED ); + } +#else /* PSA_CRYPTO_DRIVER_PRESENT */ + (void)slot; + (void)alg; + (void)operation; + + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_PRESENT */ +} + +psa_status_t psa_driver_wrapper_cipher_decrypt_setup( + psa_operation_driver_context_t *operation, + psa_key_slot_t *slot, + psa_algorithm_t alg ) +{ +#if defined(PSA_CRYPTO_DRIVER_PRESENT) && defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + psa_key_location_t location = PSA_KEY_LIFETIME_GET_LOCATION(slot->attr.lifetime); + psa_key_attributes_t attributes = { + .core = slot->attr + }; + + switch( location ) + { + case PSA_KEY_LOCATION_LOCAL_STORAGE: + /* Key is stored in the slot in export representation, so + * cycle through all known transparent accelerators */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + operation->ctx = mbedtls_calloc( 1, sizeof(test_transparent_cipher_operation_t) ); + if( operation->ctx == NULL ) + return( PSA_ERROR_INSUFFICIENT_MEMORY ); + + status = test_transparent_cipher_decrypt_setup( operation->ctx, + &attributes, + slot->data.key.data, + slot->data.key.bytes, + alg ); + /* Declared with fallback == true */ + if( status == PSA_SUCCESS ) + operation->id = PSA_CRYPTO_TRANSPARENT_TEST_DRIVER_ID; + else + { + mbedtls_platform_zeroize( + operation->ctx, + sizeof( test_transparent_cipher_operation_t ) ); + mbedtls_free( operation->ctx ); + operation->ctx = NULL; + } + + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + /* Fell through, meaning no accelerator supports this operation */ + return( PSA_ERROR_NOT_SUPPORTED ); + /* Add cases for opaque driver here */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TEST_DRIVER_LIFETIME: + operation->ctx = mbedtls_calloc( 1, sizeof(test_opaque_cipher_operation_t) ); + if( operation->ctx == NULL ) + return PSA_ERROR_INSUFFICIENT_MEMORY; + + status = test_opaque_cipher_decrypt_setup( operation->ctx, + &attributes, + slot->data.key.data, + slot->data.key.bytes, + alg ); + if( status == PSA_SUCCESS ) + operation->id = PSA_CRYPTO_OPAQUE_TEST_DRIVER_ID; + else + { + mbedtls_platform_zeroize( + operation->ctx, + sizeof( test_opaque_cipher_operation_t ) ); + mbedtls_free( operation->ctx ); + operation->ctx = NULL; + } + + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + default: + /* Key is declared with a lifetime not known to us */ + return( PSA_ERROR_NOT_SUPPORTED ); + } +#else /* PSA_CRYPTO_DRIVER_PRESENT */ + (void)slot; + (void)alg; + (void)operation; + + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_PRESENT */ +} + +psa_status_t psa_driver_wrapper_cipher_generate_iv( + psa_operation_driver_context_t *operation, + uint8_t *iv, + size_t iv_size, + size_t *iv_length ) +{ +#if defined(PSA_CRYPTO_DRIVER_PRESENT) && defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + switch( operation->id ) + { +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TRANSPARENT_TEST_DRIVER_ID: + return( test_transparent_cipher_generate_iv( operation->ctx, + iv, + iv_size, + iv_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_OPAQUE_TEST_DRIVER_ID: + return( test_opaque_cipher_generate_iv( operation->ctx, + iv, + iv_size, + iv_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + default: + /* Key is attached to a driver not known to us */ + return( PSA_ERROR_BAD_STATE ); + } +#else /* PSA_CRYPTO_DRIVER_PRESENT */ + (void) operation; + (void) iv; + (void) iv_size; + (void) iv_length; + + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_PRESENT */ +} + +psa_status_t psa_driver_wrapper_cipher_set_iv( + psa_operation_driver_context_t *operation, + const uint8_t *iv, + size_t iv_length ) +{ +#if defined(PSA_CRYPTO_DRIVER_PRESENT) && defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + switch( operation->id ) + { +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TRANSPARENT_TEST_DRIVER_ID: + return( test_transparent_cipher_set_iv( operation->ctx, + iv, + iv_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_OPAQUE_TEST_DRIVER_ID: + return( test_opaque_cipher_set_iv( operation->ctx, + iv, + iv_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + default: + /* Key is attached to a driver not known to us */ + return( PSA_ERROR_BAD_STATE ); + } +#else /* PSA_CRYPTO_DRIVER_PRESENT */ + (void) operation; + (void) iv; + (void) iv_length; + + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_PRESENT */ +} + +psa_status_t psa_driver_wrapper_cipher_update( + psa_operation_driver_context_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length ) +{ +#if defined(PSA_CRYPTO_DRIVER_PRESENT) && defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + switch( operation->id ) + { +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TRANSPARENT_TEST_DRIVER_ID: + return( test_transparent_cipher_update( operation->ctx, + input, + input_length, + output, + output_size, + output_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_OPAQUE_TEST_DRIVER_ID: + return( test_opaque_cipher_update( operation->ctx, + input, + input_length, + output, + output_size, + output_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + default: + /* Key is attached to a driver not known to us */ + return( PSA_ERROR_BAD_STATE ); + } +#else /* PSA_CRYPTO_DRIVER_PRESENT */ + (void) operation; + (void) input; + (void) input_length; + (void) output; + (void) output_length; + (void) output_size; + + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_PRESENT */ +} + +psa_status_t psa_driver_wrapper_cipher_finish( + psa_operation_driver_context_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length ) +{ +#if defined(PSA_CRYPTO_DRIVER_PRESENT) && defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + switch( operation->id ) + { +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TRANSPARENT_TEST_DRIVER_ID: + return( test_transparent_cipher_finish( operation->ctx, + output, + output_size, + output_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_OPAQUE_TEST_DRIVER_ID: + return( test_opaque_cipher_finish( operation->ctx, + output, + output_size, + output_length ) ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + default: + /* Key is attached to a driver not known to us */ + return( PSA_ERROR_BAD_STATE ); + } +#else /* PSA_CRYPTO_DRIVER_PRESENT */ + (void) operation; + (void) output; + (void) output_size; + (void) output_length; + + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_PRESENT */ +} + +psa_status_t psa_driver_wrapper_cipher_abort( + psa_operation_driver_context_t *operation ) +{ +#if defined(PSA_CRYPTO_DRIVER_PRESENT) && defined(PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT) + psa_status_t status = PSA_ERROR_INVALID_ARGUMENT; + + /* The object has (apparently) been initialized but it is not in use. It's + * ok to call abort on such an object, and there's nothing to do. */ + if( operation->ctx == NULL && operation->id == 0 ) + return( PSA_SUCCESS ); + + switch( operation->id ) + { +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_TRANSPARENT_TEST_DRIVER_ID: + status = test_transparent_cipher_abort( operation->ctx ); + mbedtls_platform_zeroize( + operation->ctx, + sizeof( test_transparent_cipher_operation_t ) ); + mbedtls_free( operation->ctx ); + operation->ctx = NULL; + operation->id = 0; + + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ +#if defined(PSA_CRYPTO_DRIVER_TEST) + case PSA_CRYPTO_OPAQUE_TEST_DRIVER_ID: + status = test_opaque_cipher_abort( operation->ctx ); + mbedtls_platform_zeroize( + operation->ctx, + sizeof( test_opaque_cipher_operation_t ) ); + mbedtls_free( operation->ctx ); + operation->ctx = NULL; + operation->id = 0; + + return( status ); +#endif /* PSA_CRYPTO_DRIVER_TEST */ + default: + /* Operation is attached to a driver not known to us */ + return( PSA_ERROR_BAD_STATE ); + } +#else /* PSA_CRYPTO_DRIVER_PRESENT */ + (void)operation; + + return( PSA_ERROR_NOT_SUPPORTED ); +#endif /* PSA_CRYPTO_DRIVER_PRESENT */ +} + +/* End of automatically generated file. */ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_driver_wrappers.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_driver_wrappers.h new file mode 100644 index 0000000000..6b5143781b --- /dev/null +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_driver_wrappers.h @@ -0,0 +1,124 @@ +/* + * Function signatures for functionality that can be provided by + * cryptographic accelerators. + * Warning: This file will be auto-generated in the future. + */ +/* Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PSA_CRYPTO_DRIVER_WRAPPERS_H +#define PSA_CRYPTO_DRIVER_WRAPPERS_H + +#include "psa/crypto.h" +#include "psa/crypto_driver_common.h" + +/* + * Signature functions + */ +psa_status_t psa_driver_wrapper_sign_hash( psa_key_slot_t *slot, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + uint8_t *signature, + size_t signature_size, + size_t *signature_length ); + +psa_status_t psa_driver_wrapper_verify_hash( psa_key_slot_t *slot, + psa_algorithm_t alg, + const uint8_t *hash, + size_t hash_length, + const uint8_t *signature, + size_t signature_length ); + +/* + * Key handling functions + */ + +psa_status_t psa_driver_wrapper_generate_key( const psa_key_attributes_t *attributes, + psa_key_slot_t *slot ); + +psa_status_t psa_driver_wrapper_validate_key( const psa_key_attributes_t *attributes, + const uint8_t *data, + size_t data_length, + size_t *bits ); + +psa_status_t psa_driver_wrapper_export_public_key( const psa_key_slot_t *slot, + uint8_t *data, + size_t data_size, + size_t *data_length ); + +/* + * Cipher functions + */ +psa_status_t psa_driver_wrapper_cipher_encrypt( + psa_key_slot_t *slot, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length ); + +psa_status_t psa_driver_wrapper_cipher_decrypt( + psa_key_slot_t *slot, + psa_algorithm_t alg, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length ); + +psa_status_t psa_driver_wrapper_cipher_encrypt_setup( + psa_operation_driver_context_t *operation, + psa_key_slot_t *slot, + psa_algorithm_t alg ); + +psa_status_t psa_driver_wrapper_cipher_decrypt_setup( + psa_operation_driver_context_t *operation, + psa_key_slot_t *slot, + psa_algorithm_t alg ); + +psa_status_t psa_driver_wrapper_cipher_generate_iv( + psa_operation_driver_context_t *operation, + uint8_t *iv, + size_t iv_size, + size_t *iv_length ); + +psa_status_t psa_driver_wrapper_cipher_set_iv( + psa_operation_driver_context_t *operation, + const uint8_t *iv, + size_t iv_length ); + +psa_status_t psa_driver_wrapper_cipher_update( + psa_operation_driver_context_t *operation, + const uint8_t *input, + size_t input_length, + uint8_t *output, + size_t output_size, + size_t *output_length ); + +psa_status_t psa_driver_wrapper_cipher_finish( + psa_operation_driver_context_t *operation, + uint8_t *output, + size_t output_size, + size_t *output_length ); + +psa_status_t psa_driver_wrapper_cipher_abort( + psa_operation_driver_context_t *operation ); + +#endif /* PSA_CRYPTO_DRIVER_WRAPPERS_H */ + +/* End of automatically generated file. */ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_invasive.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_invasive.h index c609c777ed..2b4ee1f348 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_invasive.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_invasive.h @@ -62,12 +62,12 @@ * It is called by mbedtls_psa_crypto_free(). * By default this is mbedtls_entropy_free(). * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * Success. - * \retval PSA_ERROR_NOT_PERMITTED + * \retval #PSA_ERROR_NOT_PERMITTED * The caller does not have the permission to configure * entropy sources. - * \retval PSA_ERROR_BAD_STATE + * \retval #PSA_ERROR_BAD_STATE * The library has already been initialized. */ psa_status_t mbedtls_psa_crypto_configure_entropy_sources( diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_its.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_its.h index 93c4ce981c..11703a08f1 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_its.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_its.h @@ -72,12 +72,12 @@ struct psa_storage_info_t * * \return A status indicating the success/failure of the operation * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided `uid` value was already created with PSA_STORAGE_WRITE_ONCE_FLAG - * \retval PSA_ERROR_NOT_SUPPORTED The operation failed because one or more of the flags provided in `create_flags` is not supported or is not valid - * \retval PSA_ERROR_INSUFFICIENT_STORAGE The operation failed because there was insufficient space on the storage medium - * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`) + * \retval #PSA_SUCCESS The operation completed successfully + * \retval #PSA_ERROR_NOT_PERMITTED The operation failed because the provided `uid` value was already created with PSA_STORAGE_WRITE_ONCE_FLAG + * \retval #PSA_ERROR_NOT_SUPPORTED The operation failed because one or more of the flags provided in `create_flags` is not supported or is not valid + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE The operation failed because there was insufficient space on the storage medium + * \retval #PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval #PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`) * is invalid, for example is `NULL` or references memory the caller cannot access */ psa_status_t psa_its_set(psa_storage_uid_t uid, @@ -97,11 +97,11 @@ psa_status_t psa_its_set(psa_storage_uid_t uid, * * \return A status indicating the success/failure of the operation * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided `uid` value was not found in the storage - * \retval PSA_ERROR_INVALID_SIZE The operation failed because the data associated with provided uid is larger than `data_size` - * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`, `p_data_length`) + * \retval #PSA_SUCCESS The operation completed successfully + * \retval #PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided `uid` value was not found in the storage + * \retval #PSA_ERROR_INVALID_SIZE The operation failed because the data associated with provided uid is larger than `data_size` + * \retval #PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval #PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_data`, `p_data_length`) * is invalid. For example is `NULL` or references memory the caller cannot access. * In addition, this can also happen if an invalid offset was provided. */ @@ -119,10 +119,10 @@ psa_status_t psa_its_get(psa_storage_uid_t uid, * * \return A status indicating the success/failure of the operation * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided uid value was not found in the storage - * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) - * \retval PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_info`) + * \retval #PSA_SUCCESS The operation completed successfully + * \retval #PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided uid value was not found in the storage + * \retval #PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval #PSA_ERROR_INVALID_ARGUMENT The operation failed because one of the provided pointers(`p_info`) * is invalid, for example is `NULL` or references memory the caller cannot access */ psa_status_t psa_its_get_info(psa_storage_uid_t uid, @@ -135,11 +135,15 @@ psa_status_t psa_its_get_info(psa_storage_uid_t uid, * * \return A status indicating the success/failure of the operation * - * \retval PSA_SUCCESS The operation completed successfully - * \retval PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided key value was not found in the storage - * \retval PSA_ERROR_NOT_PERMITTED The operation failed because the provided key value was created with PSA_STORAGE_WRITE_ONCE_FLAG - * \retval PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) + * \retval #PSA_SUCCESS The operation completed successfully + * \retval #PSA_ERROR_DOES_NOT_EXIST The operation failed because the provided key value was not found in the storage + * \retval #PSA_ERROR_NOT_PERMITTED The operation failed because the provided key value was created with PSA_STORAGE_WRITE_ONCE_FLAG + * \retval #PSA_ERROR_STORAGE_FAILURE The operation failed because the physical storage has failed (Fatal error) */ psa_status_t psa_its_remove(psa_storage_uid_t uid); +#ifdef __cplusplus +} +#endif + #endif /* PSA_CRYPTO_ITS_H */ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_se.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_se.h index a464232563..67fadf8965 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_se.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_se.h @@ -45,7 +45,7 @@ /** The base of the range of ITS file identifiers for secure element * driver persistent data. * - * We use a slice of the implemenation reserved range 0xffff0000..0xffffffff, + * We use a slice of the implementation reserved range 0xffff0000..0xffffffff, * specifically the range 0xfffffe00..0xfffffeff. The length of this range * drives the value of #PSA_MAX_SE_LOCATION. The identifier 0xfffffe00 is * actually not used since it corresponds to #PSA_KEY_LOCATION_LOCAL_STORAGE @@ -182,7 +182,6 @@ psa_status_t psa_destroy_se_persistent_data( psa_key_location_t location ); typedef struct { uint8_t slot_number[sizeof( psa_key_slot_number_t )]; - uint8_t bits[sizeof( psa_key_bits_t )]; } psa_se_key_data_storage_t; #endif /* PSA_CRYPTO_SE_H */ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_slot_management.c b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_slot_management.c index a32a027980..4c4ad0331a 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_slot_management.c +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_slot_management.c @@ -51,30 +51,101 @@ typedef struct static psa_global_data_t global_data; -/* Access a key slot at the given handle. The handle of a key slot is - * the index of the slot in the global slot array, plus one so that handles - * start at 1 and not 0. */ -psa_status_t psa_get_key_slot( psa_key_handle_t handle, - psa_key_slot_t **p_slot ) +psa_status_t psa_validate_key_id( + mbedtls_svc_key_id_t key, int vendor_ok ) { + psa_key_id_t key_id = MBEDTLS_SVC_KEY_ID_GET_KEY_ID( key ); + + if( ( PSA_KEY_ID_USER_MIN <= key_id ) && + ( key_id <= PSA_KEY_ID_USER_MAX ) ) + return( PSA_SUCCESS ); + + if( vendor_ok && + ( PSA_KEY_ID_VENDOR_MIN <= key_id ) && + ( key_id <= PSA_KEY_ID_VENDOR_MAX ) ) + return( PSA_SUCCESS ); + + return( PSA_ERROR_INVALID_HANDLE ); +} + +/** Get the description in memory of a key given its identifier and lock it. + * + * The descriptions of volatile keys and loaded persistent keys are + * stored in key slots. This function returns a pointer to the key slot + * containing the description of a key given its identifier. + * + * The function searches the key slots containing the description of the key + * with \p key identifier. The function does only read accesses to the key + * slots. The function does not load any persistent key thus does not access + * any storage. + * + * For volatile key identifiers, only one key slot is queried as a volatile + * key with identifier key_id can only be stored in slot of index + * ( key_id - #PSA_KEY_ID_VOLATILE_MIN ). + * + * On success, the function locks the key slot. It is the responsibility of + * the caller to unlock the key slot when it does not access it anymore. + * + * \param key Key identifier to query. + * \param[out] p_slot On success, `*p_slot` contains a pointer to the + * key slot containing the description of the key + * identified by \p key. + * + * \retval #PSA_SUCCESS + * The pointer to the key slot containing the description of the key + * identified by \p key was returned. + * \retval #PSA_ERROR_INVALID_HANDLE + * \p key is not a valid key identifier. + * \retval #PSA_ERROR_DOES_NOT_EXIST + * There is no key with key identifier \p key in the key slots. + */ +static psa_status_t psa_get_and_lock_key_slot_in_memory( + mbedtls_svc_key_id_t key, psa_key_slot_t **p_slot ) +{ + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + psa_key_id_t key_id = MBEDTLS_SVC_KEY_ID_GET_KEY_ID( key ); + size_t slot_idx; psa_key_slot_t *slot = NULL; - if( ! global_data.key_slots_initialized ) - return( PSA_ERROR_BAD_STATE ); + if( psa_key_id_is_volatile( key_id ) ) + { + slot = &global_data.key_slots[ key_id - PSA_KEY_ID_VOLATILE_MIN ]; - /* 0 is not a valid handle under any circumstance. This - * implementation provides slots number 1 to N where N is the - * number of available slots. */ - if( handle == 0 || handle > ARRAY_LENGTH( global_data.key_slots ) ) - return( PSA_ERROR_INVALID_HANDLE ); - slot = &global_data.key_slots[handle - 1]; + /* + * Check if both the PSA key identifier key_id and the owner + * identifier of key match those of the key slot. + * + * Note that, if the key slot is not occupied, its PSA key identifier + * is equal to zero. This is an invalid value for a PSA key identifier + * and thus cannot be equal to the valid PSA key identifier key_id. + */ + status = mbedtls_svc_key_id_equal( key, slot->attr.id ) ? + PSA_SUCCESS : PSA_ERROR_DOES_NOT_EXIST; + } + else + { + status = psa_validate_key_id( key, 1 ); + if( status != PSA_SUCCESS ) + return( status ); - /* If the slot isn't occupied, the handle is invalid. */ - if( ! psa_is_key_slot_occupied( slot ) ) - return( PSA_ERROR_INVALID_HANDLE ); + for( slot_idx = 0; slot_idx < PSA_KEY_SLOT_COUNT; slot_idx++ ) + { + slot = &global_data.key_slots[ slot_idx ]; + if( mbedtls_svc_key_id_equal( key, slot->attr.id ) ) + break; + } + status = ( slot_idx < PSA_KEY_SLOT_COUNT ) ? + PSA_SUCCESS : PSA_ERROR_DOES_NOT_EXIST; + } - *p_slot = slot; - return( PSA_SUCCESS ); + if( status == PSA_SUCCESS ) + { + status = psa_lock_key_slot( slot ); + if( status == PSA_SUCCESS ) + *p_slot = slot; + } + + return( status ); } psa_status_t psa_initialize_key_slots( void ) @@ -88,29 +159,80 @@ psa_status_t psa_initialize_key_slots( void ) void psa_wipe_all_key_slots( void ) { - psa_key_handle_t key; - for( key = 1; key <= PSA_KEY_SLOT_COUNT; key++ ) + size_t slot_idx; + + for( slot_idx = 0; slot_idx < PSA_KEY_SLOT_COUNT; slot_idx++ ) { - psa_key_slot_t *slot = &global_data.key_slots[key - 1]; + psa_key_slot_t *slot = &global_data.key_slots[ slot_idx ]; + slot->lock_count = 1; (void) psa_wipe_key_slot( slot ); } global_data.key_slots_initialized = 0; } -psa_status_t psa_get_empty_key_slot( psa_key_handle_t *handle, - psa_key_slot_t **p_slot ) +psa_status_t psa_get_empty_key_slot( psa_key_id_t *volatile_key_id, + psa_key_slot_t **p_slot ) { - if( ! global_data.key_slots_initialized ) - return( PSA_ERROR_BAD_STATE ); + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + size_t slot_idx; + psa_key_slot_t *selected_slot, *unlocked_persistent_key_slot; - for( *handle = PSA_KEY_SLOT_COUNT; *handle != 0; --( *handle ) ) + if( ! global_data.key_slots_initialized ) { - *p_slot = &global_data.key_slots[*handle - 1]; - if( ! psa_is_key_slot_occupied( *p_slot ) ) - return( PSA_SUCCESS ); + status = PSA_ERROR_BAD_STATE; + goto error; } + + selected_slot = unlocked_persistent_key_slot = NULL; + for( slot_idx = 0; slot_idx < PSA_KEY_SLOT_COUNT; slot_idx++ ) + { + psa_key_slot_t *slot = &global_data.key_slots[ slot_idx ]; + if( ! psa_is_key_slot_occupied( slot ) ) + { + selected_slot = slot; + break; + } + + if( ( unlocked_persistent_key_slot == NULL ) && + ( ! PSA_KEY_LIFETIME_IS_VOLATILE( slot->attr.lifetime ) ) && + ( ! psa_is_key_slot_locked( slot ) ) ) + unlocked_persistent_key_slot = slot; + } + + /* + * If there is no unused key slot and there is at least one unlocked key + * slot containing the description of a persistent key, recycle the first + * such key slot we encountered. If we later need to operate on the + * persistent key we are evicting now, we will reload its description from + * storage. + */ + if( ( selected_slot == NULL ) && + ( unlocked_persistent_key_slot != NULL ) ) + { + selected_slot = unlocked_persistent_key_slot; + selected_slot->lock_count = 1; + psa_wipe_key_slot( selected_slot ); + } + + if( selected_slot != NULL ) + { + status = psa_lock_key_slot( selected_slot ); + if( status != PSA_SUCCESS ) + goto error; + + *volatile_key_id = PSA_KEY_ID_VOLATILE_MIN + + ( (psa_key_id_t)( selected_slot - global_data.key_slots ) ); + *p_slot = selected_slot; + + return( PSA_SUCCESS ); + } + status = PSA_ERROR_INSUFFICIENT_MEMORY; + +error: *p_slot = NULL; - return( PSA_ERROR_INSUFFICIENT_MEMORY ); + *volatile_key_id = 0; + + return( status ); } #if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) @@ -137,47 +259,84 @@ static psa_status_t psa_load_persistent_key_into_slot( psa_key_slot_t *slot ) data = (psa_se_key_data_storage_t *) key_data; memcpy( &slot->data.se.slot_number, &data->slot_number, sizeof( slot->data.se.slot_number ) ); - memcpy( &slot->attr.bits, &data->bits, - sizeof( slot->attr.bits ) ); } else #endif /* MBEDTLS_PSA_CRYPTO_SE_C */ { - status = psa_import_key_into_slot( slot, key_data, key_data_length ); + status = psa_copy_key_material_into_slot( slot, key_data, key_data_length ); + if( status != PSA_SUCCESS ) + goto exit; } exit: psa_free_persistent_key_data( key_data, key_data_length ); return( status ); } +#endif /* MBEDTLS_PSA_CRYPTO_STORAGE_C */ -/** Check whether a key identifier is acceptable. - * - * For backward compatibility, key identifiers that were valid in a - * past released version must remain valid, unless a migration path - * is provided. - * - * \param file_id The key identifier to check. - * \param vendor_ok Nonzero to allow key ids in the vendor range. - * 0 to allow only key ids in the application range. - * - * \return 1 if \p file_id is acceptable, otherwise 0. - */ -static int psa_is_key_id_valid( psa_key_file_id_t file_id, - int vendor_ok ) +psa_status_t psa_get_and_lock_key_slot( mbedtls_svc_key_id_t key, + psa_key_slot_t **p_slot ) { - psa_app_key_id_t key_id = PSA_KEY_FILE_GET_KEY_ID( file_id ); - if( PSA_KEY_ID_USER_MIN <= key_id && key_id <= PSA_KEY_ID_USER_MAX ) - return( 1 ); - else if( vendor_ok && - PSA_KEY_ID_VENDOR_MIN <= key_id && - key_id <= PSA_KEY_ID_VENDOR_MAX ) - return( 1 ); - else - return( 0 ); -} + psa_status_t status = PSA_ERROR_CORRUPTION_DETECTED; + + *p_slot = NULL; + if( ! global_data.key_slots_initialized ) + return( PSA_ERROR_BAD_STATE ); + + /* + * On success, the pointer to the slot is passed directly to the caller + * thus no need to unlock the key slot here. + */ + status = psa_get_and_lock_key_slot_in_memory( key, p_slot ); + if( status != PSA_ERROR_DOES_NOT_EXIST ) + return( status ); + +#if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) + psa_key_id_t volatile_key_id; + + status = psa_get_empty_key_slot( &volatile_key_id, p_slot ); + if( status != PSA_SUCCESS ) + return( status ); + + (*p_slot)->attr.lifetime = PSA_KEY_LIFETIME_PERSISTENT; + (*p_slot)->attr.id = key; + + status = psa_load_persistent_key_into_slot( *p_slot ); + if( status != PSA_SUCCESS ) + psa_wipe_key_slot( *p_slot ); + + return( status ); +#else + return( PSA_ERROR_DOES_NOT_EXIST ); #endif /* defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) */ +} + +psa_status_t psa_unlock_key_slot( psa_key_slot_t *slot ) +{ + if( slot == NULL ) + return( PSA_SUCCESS ); + + if( slot->lock_count > 0 ) + { + slot->lock_count--; + return( PSA_SUCCESS ); + } + + /* + * As the return error code may not be handled in case of multiple errors, + * do our best to report if the lock counter is equal to zero: if + * available call MBEDTLS_PARAM_FAILED that may terminate execution (if + * called as part of the execution of a unit test suite this will stop the + * test suite execution). + */ +#ifdef MBEDTLS_CHECK_PARAMS + MBEDTLS_PARAM_FAILED( slot->lock_count > 0 ); +#endif + + return( PSA_ERROR_CORRUPTION_DETECTED ); +} + psa_status_t psa_validate_key_location( psa_key_lifetime_t lifetime, psa_se_drv_table_entry_t **p_drv ) { @@ -203,8 +362,7 @@ psa_status_t psa_validate_key_location( psa_key_lifetime_t lifetime, return( PSA_SUCCESS ); } -psa_status_t psa_validate_key_persistence( psa_key_lifetime_t lifetime, - psa_key_id_t key_id ) +psa_status_t psa_validate_key_persistence( psa_key_lifetime_t lifetime ) { if ( PSA_KEY_LIFETIME_IS_VOLATILE( lifetime ) ) { @@ -215,47 +373,33 @@ psa_status_t psa_validate_key_persistence( psa_key_lifetime_t lifetime, { /* Persistent keys require storage support */ #if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) - if( psa_is_key_id_valid( key_id, - psa_key_lifetime_is_external( lifetime ) ) ) - return( PSA_SUCCESS ); - else - return( PSA_ERROR_INVALID_ARGUMENT ); + return( PSA_SUCCESS ); #else /* MBEDTLS_PSA_CRYPTO_STORAGE_C */ - (void) key_id; return( PSA_ERROR_NOT_SUPPORTED ); #endif /* !MBEDTLS_PSA_CRYPTO_STORAGE_C */ } } -psa_status_t psa_open_key( psa_key_file_id_t id, psa_key_handle_t *handle ) +psa_status_t psa_open_key( mbedtls_svc_key_id_t key, psa_key_handle_t *handle ) { #if defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) psa_status_t status; psa_key_slot_t *slot; - *handle = 0; - - if( ! psa_is_key_id_valid( id, 1 ) ) - return( PSA_ERROR_INVALID_ARGUMENT ); - - status = psa_get_empty_key_slot( handle, &slot ); - if( status != PSA_SUCCESS ) - return( status ); - - slot->attr.lifetime = PSA_KEY_LIFETIME_PERSISTENT; - slot->attr.id = id; - - status = psa_load_persistent_key_into_slot( slot ); + status = psa_get_and_lock_key_slot( key, &slot ); if( status != PSA_SUCCESS ) { - psa_wipe_key_slot( slot ); - *handle = 0; + *handle = PSA_KEY_HANDLE_INIT; + return( status ); } - return( status ); + + *handle = key; + + return( psa_unlock_key_slot( slot ) ); #else /* defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) */ - (void) id; - *handle = 0; + (void) key; + *handle = PSA_KEY_HANDLE_INIT; return( PSA_ERROR_NOT_SUPPORTED ); #endif /* !defined(MBEDTLS_PSA_CRYPTO_STORAGE_C) */ } @@ -265,23 +409,48 @@ psa_status_t psa_close_key( psa_key_handle_t handle ) psa_status_t status; psa_key_slot_t *slot; - if( handle == 0 ) + if( psa_key_handle_is_null( handle ) ) return( PSA_SUCCESS ); - status = psa_get_key_slot( handle, &slot ); + status = psa_get_and_lock_key_slot_in_memory( handle, &slot ); if( status != PSA_SUCCESS ) return( status ); - return( psa_wipe_key_slot( slot ) ); + if( slot->lock_count <= 1 ) + return( psa_wipe_key_slot( slot ) ); + else + return( psa_unlock_key_slot( slot ) ); +} + +psa_status_t psa_purge_key( mbedtls_svc_key_id_t key ) +{ + psa_status_t status; + psa_key_slot_t *slot; + + status = psa_get_and_lock_key_slot_in_memory( key, &slot ); + if( status != PSA_SUCCESS ) + return( status ); + + if( ( ! PSA_KEY_LIFETIME_IS_VOLATILE( slot->attr.lifetime ) ) && + ( slot->lock_count <= 1 ) ) + return( psa_wipe_key_slot( slot ) ); + else + return( psa_unlock_key_slot( slot ) ); } void mbedtls_psa_get_stats( mbedtls_psa_stats_t *stats ) { - psa_key_handle_t key; + size_t slot_idx; + memset( stats, 0, sizeof( *stats ) ); - for( key = 1; key <= PSA_KEY_SLOT_COUNT; key++ ) + + for( slot_idx = 0; slot_idx < PSA_KEY_SLOT_COUNT; slot_idx++ ) { - const psa_key_slot_t *slot = &global_data.key_slots[key - 1]; + const psa_key_slot_t *slot = &global_data.key_slots[ slot_idx ]; + if( psa_is_key_slot_locked( slot ) ) + { + ++stats->locked_slots; + } if( ! psa_is_key_slot_occupied( slot ) ) { ++stats->empty_slots; @@ -291,14 +460,14 @@ void mbedtls_psa_get_stats( mbedtls_psa_stats_t *stats ) ++stats->volatile_slots; else if( slot->attr.lifetime == PSA_KEY_LIFETIME_PERSISTENT ) { - psa_app_key_id_t id = PSA_KEY_FILE_GET_KEY_ID(slot->attr.id); + psa_key_id_t id = MBEDTLS_SVC_KEY_ID_GET_KEY_ID( slot->attr.id ); ++stats->persistent_slots; if( id > stats->max_open_internal_key_id ) stats->max_open_internal_key_id = id; } else { - psa_app_key_id_t id = PSA_KEY_FILE_GET_KEY_ID(slot->attr.id); + psa_key_id_t id = MBEDTLS_SVC_KEY_ID_GET_KEY_ID( slot->attr.id ); ++stats->external_slots; if( id > stats->max_open_external_key_id ) stats->max_open_external_key_id = id; diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_slot_management.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_slot_management.h index 676a77e5a0..ef0814ac9e 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_slot_management.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_slot_management.h @@ -22,32 +22,86 @@ #define PSA_CRYPTO_SLOT_MANAGEMENT_H #include "psa/crypto.h" +#include "psa_crypto_core.h" #include "psa_crypto_se.h" /* Number of key slots (plus one because 0 is not used). * The value is a compile-time constant for now, for simplicity. */ #define PSA_KEY_SLOT_COUNT 32 -/** Access a key slot at the given handle. +/** Range of volatile key identifiers. * - * \param handle Key handle to query. - * \param[out] p_slot On success, `*p_slot` contains a pointer to the - * key slot in memory designated by \p handle. - * - * \retval PSA_SUCCESS - * Success: \p handle is a handle to `*p_slot`. Note that `*p_slot` - * may be empty or occupied. - * \retval PSA_ERROR_INVALID_HANDLE - * \p handle is out of range or is not in use. - * \retval PSA_ERROR_BAD_STATE - * The library has not been initialized. + * The last PSA_KEY_SLOT_COUNT identifiers of the implementation range + * of key identifiers are reserved for volatile key identifiers. + * A volatile key identifier is equal to #PSA_KEY_ID_VOLATILE_MIN plus the + * index of the key slot containing the volatile key definition. */ -psa_status_t psa_get_key_slot( psa_key_handle_t handle, - psa_key_slot_t **p_slot ); + +/** The minimum value for a volatile key identifier. + */ +#define PSA_KEY_ID_VOLATILE_MIN ( PSA_KEY_ID_VENDOR_MAX - \ + PSA_KEY_SLOT_COUNT + 1 ) + +/** The maximum value for a volatile key identifier. + */ +#define PSA_KEY_ID_VOLATILE_MAX PSA_KEY_ID_VENDOR_MAX + +/** Test whether a key identifier is a volatile key identifier. + * + * \param key_id Key identifier to test. + * + * \retval 1 + * The key identifier is a volatile key identifier. + * \retval 0 + * The key identifier is not a volatile key identifier. + */ +static inline int psa_key_id_is_volatile( psa_key_id_t key_id ) +{ + return( ( key_id >= PSA_KEY_ID_VOLATILE_MIN ) && + ( key_id <= PSA_KEY_ID_VOLATILE_MAX ) ); +} + +/** Get the description of a key given its identifier and lock it. + * + * The descriptions of volatile keys and loaded persistent keys are stored in + * key slots. This function returns a pointer to the key slot containing the + * description of a key given its identifier. + * + * In case of a persistent key, the function loads the description of the key + * into a key slot if not already done. + * + * On success, the returned key slot is locked. It is the responsibility of + * the caller to unlock the key slot when it does not access it anymore. + * + * \param key Key identifier to query. + * \param[out] p_slot On success, `*p_slot` contains a pointer to the + * key slot containing the description of the key + * identified by \p key. + * + * \retval #PSA_SUCCESS + * \p *p_slot contains a pointer to the key slot containing the + * description of the key identified by \p key. + * The key slot counter has been incremented. + * \retval #PSA_ERROR_BAD_STATE + * The library has not been initialized. + * \retval #PSA_ERROR_INVALID_HANDLE + * \p key is not a valid key identifier. + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * \p key is a persistent key identifier. The implementation does not + * have sufficient resources to load the persistent key. This can be + * due to a lack of empty key slot, or available memory. + * \retval #PSA_ERROR_DOES_NOT_EXIST + * There is no key with key identifier \p key. + * \retval #PSA_ERROR_CORRUPTION_DETECTED + * \retval #PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_ERROR_DATA_CORRUPT + */ +psa_status_t psa_get_and_lock_key_slot( mbedtls_svc_key_id_t key, + psa_key_slot_t **p_slot ); /** Initialize the key slot structures. * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * Currently this function always succeeds. */ psa_status_t psa_initialize_key_slots( void ); @@ -60,19 +114,61 @@ void psa_wipe_all_key_slots( void ); /** Find a free key slot. * * This function returns a key slot that is available for use and is in its - * ground state (all-bits-zero). + * ground state (all-bits-zero). On success, the key slot is locked. It is + * the responsibility of the caller to unlock the key slot when it does not + * access it anymore. * - * \param[out] handle On success, a slot number that can be used as a - * handle to the slot. - * \param[out] p_slot On success, a pointer to the slot. + * \param[out] volatile_key_id On success, volatile key identifier + * associated to the returned slot. + * \param[out] p_slot On success, a pointer to the slot. * * \retval #PSA_SUCCESS * \retval #PSA_ERROR_INSUFFICIENT_MEMORY * \retval #PSA_ERROR_BAD_STATE */ -psa_status_t psa_get_empty_key_slot( psa_key_handle_t *handle, +psa_status_t psa_get_empty_key_slot( psa_key_id_t *volatile_key_id, psa_key_slot_t **p_slot ); +/** Lock a key slot. + * + * This function increments the key slot lock counter by one. + * + * \param[in] slot The key slot. + * + * \retval #PSA_SUCCESS + The key slot lock counter was incremented. + * \retval #PSA_ERROR_CORRUPTION_DETECTED + * The lock counter already reached its maximum value and was not + * increased. + */ +static inline psa_status_t psa_lock_key_slot( psa_key_slot_t *slot ) +{ + if( slot->lock_count >= SIZE_MAX ) + return( PSA_ERROR_CORRUPTION_DETECTED ); + + slot->lock_count++; + + return( PSA_SUCCESS ); +} + +/** Unlock a key slot. + * + * This function decrements the key slot lock counter by one. + * + * \note To ease the handling of errors in retrieving a key slot + * a NULL input pointer is valid, and the function returns + * successfully without doing anything in that case. + * + * \param[in] slot The key slot. + * \retval #PSA_SUCCESS + * \p slot is NULL or the key slot lock counter has been + * decremented successfully. + * \retval #PSA_ERROR_CORRUPTION_DETECTED + * The lock counter was equal to 0. + * + */ +psa_status_t psa_unlock_key_slot( psa_key_slot_t *slot ); + /** Test whether a lifetime designates a key in an external cryptoprocessor. * * \param lifetime The lifetime to test. @@ -108,19 +204,26 @@ static inline int psa_key_lifetime_is_external( psa_key_lifetime_t lifetime ) psa_status_t psa_validate_key_location( psa_key_lifetime_t lifetime, psa_se_drv_table_entry_t **p_drv ); -/** Validate that a key's persistence attributes are valid. +/** Validate the persistence of a key. * - * This function checks whether a key's declared persistence level and key ID - * attributes are valid and known to the PSA Core in its actual configuration. - * - * \param[in] lifetime The key lifetime attribute. - * \param[in] key_id The key ID attribute + * \param[in] lifetime The key lifetime attribute. * * \retval #PSA_SUCCESS - * \retval #PSA_ERROR_INVALID_ARGUMENT + * \retval #PSA_ERROR_INVALID_ARGUMENT The key is persistent but persistent + * keys are not supported. */ -psa_status_t psa_validate_key_persistence( psa_key_lifetime_t lifetime, - psa_key_id_t key_id ); +psa_status_t psa_validate_key_persistence( psa_key_lifetime_t lifetime ); +/** Validate a key identifier. + * + * \param[in] key The key identifier. + * \param[in] vendor_ok Non-zero to indicate that key identifiers in the + * vendor range are allowed, volatile key identifiers + * excepted \c 0 otherwise. + * + * \retval #PSA_SUCCESS The identifier is valid. + * \retval #PSA_ERROR_INVALID_ARGUMENT The key identifier is not valid. + */ +psa_status_t psa_validate_key_id( mbedtls_svc_key_id_t key, int vendor_ok ); #endif /* PSA_CRYPTO_SLOT_MANAGEMENT_H */ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_storage.c b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_storage.c index 103c9bbb8e..1ebd20ee37 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_storage.c +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_storage.c @@ -55,27 +55,27 @@ /* Key storage */ /****************************************************************/ -/* Determine a file name (ITS file identifier) for the given key file - * identifier. The file name must be distinct from any file that is used - * for a purpose other than storing a key. Currently, the only such file - * is the random seed file whose name is PSA_CRYPTO_ITS_RANDOM_SEED_UID - * and whose value is 0xFFFFFF52. */ -static psa_storage_uid_t psa_its_identifier_of_slot( psa_key_file_id_t file_id ) +/* Determine a file name (ITS file identifier) for the given key identifier. + * The file name must be distinct from any file that is used for a purpose + * other than storing a key. Currently, the only such file is the random seed + * file whose name is PSA_CRYPTO_ITS_RANDOM_SEED_UID and whose value is + * 0xFFFFFF52. */ +static psa_storage_uid_t psa_its_identifier_of_slot( mbedtls_svc_key_id_t key ) { -#if defined(MBEDTLS_PSA_CRYPTO_KEY_FILE_ID_ENCODES_OWNER) && \ - defined(PSA_CRYPTO_SECURE) +#if defined(MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER) /* Encode the owner in the upper 32 bits. This means that if * owner values are nonzero (as they are on a PSA platform), * no key file will ever have a value less than 0x100000000, so * the whole range 0..0xffffffff is available for non-key files. */ - uint32_t unsigned_owner = (uint32_t) file_id.owner; - return( (uint64_t) unsigned_owner << 32 | file_id.key_id ); + uint32_t unsigned_owner_id = MBEDTLS_SVC_KEY_ID_GET_OWNER_ID( key ); + return( ( (uint64_t) unsigned_owner_id << 32 ) | + MBEDTLS_SVC_KEY_ID_GET_KEY_ID( key ) ); #else /* Use the key id directly as a file name. - * psa_is_key_file_id_valid() in psa_crypto_slot_management.c + * psa_is_key_id_valid() in psa_crypto_slot_management.c * is responsible for ensuring that key identifiers do not have a * value that is reserved for non-key files. */ - return( file_id ); + return( key ); #endif } @@ -90,13 +90,12 @@ static psa_storage_uid_t psa_its_identifier_of_slot( psa_key_file_id_t file_id ) * \param[out] data Buffer where the data is to be written. * \param data_size Size of the \c data buffer in bytes. * - * \retval PSA_SUCCESS - * \retval PSA_ERROR_STORAGE_FAILURE - * \retval PSA_ERROR_DOES_NOT_EXIST + * \retval #PSA_SUCCESS + * \retval #PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_ERROR_DOES_NOT_EXIST */ -static psa_status_t psa_crypto_storage_load( const psa_key_file_id_t key, - uint8_t *data, - size_t data_size ) +static psa_status_t psa_crypto_storage_load( + const mbedtls_svc_key_id_t key, uint8_t *data, size_t data_size ) { psa_status_t status; psa_storage_uid_t data_identifier = psa_its_identifier_of_slot( key ); @@ -114,7 +113,7 @@ static psa_status_t psa_crypto_storage_load( const psa_key_file_id_t key, return( status ); } -int psa_is_key_present_in_storage( const psa_key_file_id_t key ) +int psa_is_key_present_in_storage( const mbedtls_svc_key_id_t key ) { psa_status_t ret; psa_storage_uid_t data_identifier = psa_its_identifier_of_slot( key ); @@ -138,12 +137,12 @@ int psa_is_key_present_in_storage( const psa_key_file_id_t key ) * \param data_length The number of bytes * that make up the data. * - * \retval PSA_SUCCESS - * \retval PSA_ERROR_INSUFFICIENT_STORAGE - * \retval PSA_ERROR_STORAGE_FAILURE - * \retval PSA_ERROR_ALREADY_EXISTS + * \retval #PSA_SUCCESS + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE + * \retval #PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_ERROR_ALREADY_EXISTS */ -static psa_status_t psa_crypto_storage_store( const psa_key_file_id_t key, +static psa_status_t psa_crypto_storage_store( const mbedtls_svc_key_id_t key, const uint8_t *data, size_t data_length ) { @@ -184,7 +183,7 @@ exit: return( status ); } -psa_status_t psa_destroy_persistent_key( const psa_key_file_id_t key ) +psa_status_t psa_destroy_persistent_key( const mbedtls_svc_key_id_t key ) { psa_status_t ret; psa_storage_uid_t data_identifier = psa_its_identifier_of_slot( key ); @@ -211,11 +210,11 @@ psa_status_t psa_destroy_persistent_key( const psa_key_file_id_t key ) * is to be obtained. * \param[out] data_length The number of bytes that make up the data. * - * \retval PSA_SUCCESS - * \retval PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_SUCCESS + * \retval #PSA_ERROR_STORAGE_FAILURE */ static psa_status_t psa_crypto_storage_get_data_length( - const psa_key_file_id_t key, + const mbedtls_svc_key_id_t key, size_t *data_length ) { psa_status_t status; @@ -254,6 +253,25 @@ static psa_status_t psa_crypto_storage_get_data_length( } #endif +/* + * 16-bit integer manipulation macros (little endian) + */ +#ifndef GET_UINT16_LE +#define GET_UINT16_LE( n, b, i ) \ +{ \ + (n) = ( (uint16_t) (b)[(i) ] ) \ + | ( (uint16_t) (b)[(i) + 1] << 8 ); \ +} +#endif + +#ifndef PUT_UINT16_LE +#define PUT_UINT16_LE( n, b, i ) \ +{ \ + (b)[(i) ] = (unsigned char) ( ( (n) ) & 0xFF ); \ + (b)[(i) + 1] = (unsigned char) ( ( (n) >> 8 ) & 0xFF ); \ +} +#endif + /** * Persistent key storage magic header. */ @@ -264,9 +282,8 @@ typedef struct { uint8_t magic[PSA_KEY_STORAGE_MAGIC_HEADER_LENGTH]; uint8_t version[4]; uint8_t lifetime[sizeof( psa_key_lifetime_t )]; - uint8_t type[4]; /* Size=4 for a 2-byte type to keep the structure more - * regular and aligned and to make potential future - * extensibility easier. */ + uint8_t type[2]; + uint8_t bits[2]; uint8_t policy[sizeof( psa_key_policy_t )]; uint8_t data_len[4]; uint8_t key_data[]; @@ -283,7 +300,8 @@ void psa_format_key_data_for_storage( const uint8_t *data, memcpy( storage_format->magic, PSA_KEY_STORAGE_MAGIC_HEADER, PSA_KEY_STORAGE_MAGIC_HEADER_LENGTH ); PUT_UINT32_LE( 0, storage_format->version, 0 ); PUT_UINT32_LE( attr->lifetime, storage_format->lifetime, 0 ); - PUT_UINT32_LE( (uint32_t) attr->type, storage_format->type, 0 ); + PUT_UINT16_LE( (uint16_t) attr->type, storage_format->type, 0 ); + PUT_UINT16_LE( (uint16_t) attr->bits, storage_format->bits, 0 ); PUT_UINT32_LE( attr->policy.usage, storage_format->policy, 0 ); PUT_UINT32_LE( attr->policy.alg, storage_format->policy, sizeof( uint32_t ) ); PUT_UINT32_LE( attr->policy.alg2, storage_format->policy, 2 * sizeof( uint32_t ) ); @@ -309,7 +327,6 @@ psa_status_t psa_parse_key_data_from_storage( const uint8_t *storage_data, const psa_persistent_key_storage_format *storage_format = (const psa_persistent_key_storage_format *)storage_data; uint32_t version; - uint32_t type; if( storage_data_length < sizeof(*storage_format) ) return( PSA_ERROR_STORAGE_FAILURE ); @@ -340,11 +357,8 @@ psa_status_t psa_parse_key_data_from_storage( const uint8_t *storage_data, } GET_UINT32_LE( attr->lifetime, storage_format->lifetime, 0 ); - GET_UINT32_LE( type, storage_format->type, 0 ); - if( type <= (psa_key_type_t) -1 ) - attr->type = (psa_key_type_t) type; - else - return( PSA_ERROR_STORAGE_FAILURE ); + GET_UINT16_LE( attr->type, storage_format->type, 0 ); + GET_UINT16_LE( attr->bits, storage_format->bits, 0 ); GET_UINT32_LE( attr->policy.usage, storage_format->policy, 0 ); GET_UINT32_LE( attr->policy.alg, storage_format->policy, sizeof( uint32_t ) ); GET_UINT32_LE( attr->policy.alg2, storage_format->policy, 2 * sizeof( uint32_t ) ); @@ -394,7 +408,7 @@ psa_status_t psa_load_persistent_key( psa_core_key_attributes_t *attr, psa_status_t status = PSA_SUCCESS; uint8_t *loaded_data; size_t storage_data_length = 0; - psa_key_id_t key = attr->id; + mbedtls_svc_key_id_t key = attr->id; status = psa_crypto_storage_get_data_length( key, &storage_data_length ); if( status != PSA_SUCCESS ) diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_storage.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_storage.h index debc742bd1..fbc94fc387 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_storage.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/mbedtls/psa_crypto_storage.h @@ -72,7 +72,7 @@ extern "C" { * \retval 1 * Persistent data present for slot number */ -int psa_is_key_present_in_storage( const psa_key_file_id_t key ); +int psa_is_key_present_in_storage( const mbedtls_svc_key_id_t key ); /** * \brief Format key data and metadata and save to a location for given key @@ -81,9 +81,10 @@ int psa_is_key_present_in_storage( const psa_key_file_id_t key ); * This function formats the key data and metadata and saves it to a * persistent storage backend. The storage location corresponding to the * key slot must be empty, otherwise this function will fail. This function - * should be called after psa_import_key_into_slot() to ensure the + * should be called after loading the key into an internal slot to ensure the * persistent key is not saved into a storage location corresponding to an - * already occupied non-persistent key, as well as validating the key data. + * already occupied non-persistent key, as well as ensuring the key data is + * validated. * * * \param[in] attr The attributes of the key to save. @@ -92,11 +93,11 @@ int psa_is_key_present_in_storage( const psa_key_file_id_t key ); * \param[in] data Buffer containing the key data. * \param data_length The number of bytes that make up the key data. * - * \retval PSA_SUCCESS - * \retval PSA_ERROR_INSUFFICIENT_MEMORY - * \retval PSA_ERROR_INSUFFICIENT_STORAGE - * \retval PSA_ERROR_STORAGE_FAILURE - * \retval PSA_ERROR_ALREADY_EXISTS + * \retval #PSA_SUCCESS + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE + * \retval #PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_ERROR_ALREADY_EXISTS */ psa_status_t psa_save_persistent_key( const psa_core_key_attributes_t *attr, const uint8_t *data, @@ -121,10 +122,10 @@ psa_status_t psa_save_persistent_key( const psa_core_key_attributes_t *attr, * \param[out] data Pointer to an allocated key data buffer on return. * \param[out] data_length The number of bytes that make up the key data. * - * \retval PSA_SUCCESS - * \retval PSA_ERROR_INSUFFICIENT_MEMORY - * \retval PSA_ERROR_STORAGE_FAILURE - * \retval PSA_ERROR_DOES_NOT_EXIST + * \retval #PSA_SUCCESS + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * \retval #PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_ERROR_DOES_NOT_EXIST */ psa_status_t psa_load_persistent_key( psa_core_key_attributes_t *attr, uint8_t **data, @@ -136,12 +137,12 @@ psa_status_t psa_load_persistent_key( psa_core_key_attributes_t *attr, * \param key Persistent identifier of the key to remove * from persistent storage. * - * \retval PSA_SUCCESS + * \retval #PSA_SUCCESS * The key was successfully removed, * or the key did not exist. - * \retval PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_ERROR_STORAGE_FAILURE */ -psa_status_t psa_destroy_persistent_key( const psa_key_file_id_t key ); +psa_status_t psa_destroy_persistent_key( const mbedtls_svc_key_id_t key ); /** * \brief Free the temporary buffer allocated by psa_load_persistent_key(). @@ -181,10 +182,10 @@ void psa_format_key_data_for_storage( const uint8_t *data, * \param[out] attr On success, the attribute structure is filled * with the loaded key metadata. * - * \retval PSA_SUCCESS - * \retval PSA_ERROR_INSUFFICIENT_STORAGE - * \retval PSA_ERROR_INSUFFICIENT_MEMORY - * \retval PSA_ERROR_STORAGE_FAILURE + * \retval #PSA_SUCCESS + * \retval #PSA_ERROR_INSUFFICIENT_STORAGE + * \retval #PSA_ERROR_INSUFFICIENT_MEMORY + * \retval #PSA_ERROR_STORAGE_FAILURE */ psa_status_t psa_parse_key_data_from_storage( const uint8_t *storage_data, size_t storage_data_length, @@ -292,7 +293,7 @@ typedef union uint16_t unused1; psa_key_lifetime_t lifetime; psa_key_slot_number_t slot; - psa_key_id_t id; + mbedtls_svc_key_id_t id; } key; } psa_crypto_transaction_t; diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/val/val_client_defs.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/val/val_client_defs.h index d1d18d7b6e..eaef75cc1f 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/val/val_client_defs.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_MBED_PSA_SRV/val/val_client_defs.h @@ -20,7 +20,8 @@ #include "val.h" #include "psa/client.h" -#include "crypto_values.h" +#include "psa/crypto_types.h" +#include "psa/crypto_values.h" #define INVALID_SID 0x0000FA20 diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_LATEST/include/mbedtls_svc_key_id.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_LATEST/include/mbedtls_svc_key_id.h new file mode 100644 index 0000000000..9679b914bb --- /dev/null +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_LATEST/include/mbedtls_svc_key_id.h @@ -0,0 +1,53 @@ +/** + * \file mbedtls_svc_key_id.h + * + * Excerpted from Mbed TLS for internal use by Mbed TLS's PSK key exchange to + * interface with generic PSA Crypto implementations. + * + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_SVC_KEY_ID_H +#define MBEDTLS_SVC_KEY_ID_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef psa_key_id_t mbedtls_svc_key_id_t; + +#define MBEDTLS_SVC_KEY_ID_INIT ( (psa_key_id_t)0 ) + +/** Check whether a key identifier is null. + * + * \param key Key identifier. + * + * \return Non-zero if the key identifier is null, zero otherwise. + */ +static inline int mbedtls_svc_key_id_is_null( mbedtls_svc_key_id_t key ) +{ + return( key == 0 ); +} + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_SVC_KEY_ID_H */ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_LATEST/include/psa/crypto_values.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_LATEST/include/psa/crypto_values.h index 9cca6b24cf..f813280e0f 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_LATEST/include/psa/crypto_values.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_LATEST/include/psa/crypto_values.h @@ -24,6 +24,8 @@ #ifndef PSA_CRYPTO_VALUES_H #define PSA_CRYPTO_VALUES_H +#include "mbedtls_svc_key_id.h" + /** \defgroup error Error codes * @{ */ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_V1_0/include/mbedtls_svc_key_id.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_V1_0/include/mbedtls_svc_key_id.h new file mode 100644 index 0000000000..9679b914bb --- /dev/null +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_V1_0/include/mbedtls_svc_key_id.h @@ -0,0 +1,53 @@ +/** + * \file mbedtls_svc_key_id.h + * + * Excerpted from Mbed TLS for internal use by Mbed TLS's PSK key exchange to + * interface with generic PSA Crypto implementations. + * + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBEDTLS_SVC_KEY_ID_H +#define MBEDTLS_SVC_KEY_ID_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef psa_key_id_t mbedtls_svc_key_id_t; + +#define MBEDTLS_SVC_KEY_ID_INIT ( (psa_key_id_t)0 ) + +/** Check whether a key identifier is null. + * + * \param key Key identifier. + * + * \return Non-zero if the key identifier is null, zero otherwise. + */ +static inline int mbedtls_svc_key_id_is_null( mbedtls_svc_key_id_t key ) +{ + return( key == 0 ); +} + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* MBEDTLS_SVC_KEY_ID_H */ diff --git a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_V1_0/include/psa/crypto_values.h b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_V1_0/include/psa/crypto_values.h index d8a575bb8a..a7587fe605 100644 --- a/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_V1_0/include/psa/crypto_values.h +++ b/platform/FEATURE_EXPERIMENTAL_API/FEATURE_PSA/TARGET_TFM/TARGET_TFM_V1_0/include/psa/crypto_values.h @@ -24,6 +24,8 @@ #ifndef PSA_CRYPTO_VALUES_H #define PSA_CRYPTO_VALUES_H +#include "mbedtls_svc_key_id.h" + /** \defgroup error Error codes * @{ */ @@ -983,6 +985,26 @@ */ #define PSA_ALG_CBC_NO_PADDING ((psa_algorithm_t)0x04600100) +/** The Electronic Code Book (ECB) mode of a block cipher, with no padding. + * + * \warning ECB mode does not protect the confidentiality of the encrypted data + * except in extremely narrow circumstances. It is recommended that applications + * only use ECB if they need to construct an operating mode that the + * implementation does not provide. Implementations are encouraged to provide + * the modes that applications need in preference to supporting direct access + * to ECB. + * + * The underlying block cipher is determined by the key type. + * + * This symmetric cipher mode can only be used with messages whose lengths are a + * multiple of the block size of the chosen block cipher. + * + * ECB mode does not accept an initialization vector (IV). When using a + * multi-part cipher operation with this algorithm, psa_cipher_generate_iv() + * and psa_cipher_set_iv() must not be called. + */ +#define PSA_ALG_ECB_NO_PADDING ((psa_algorithm_t)0x04404400) + /** The CBC block cipher chaining mode with PKCS#7 padding. * * The underlying block cipher is determined by the key type. diff --git a/platform/cxxsupport/mstd_atomic b/platform/cxxsupport/mstd_atomic index 95d2bc7870..4ad93a8af4 100644 --- a/platform/cxxsupport/mstd_atomic +++ b/platform/cxxsupport/mstd_atomic @@ -186,7 +186,7 @@ struct AtomicBaseRaw { T val; } ret; { - CriticalSectionLock lock; + mbed::CriticalSectionLock lock; memcpy(std::addressof(ret.val), const_cast(std::addressof(data)), sizeof(T)); } return std::move(ret.val); @@ -194,19 +194,19 @@ struct AtomicBaseRaw { T load(memory_order order = memory_order_seq_cst) const noexcept { MBED_CHECK_LOAD_ORDER(order); - CriticalSectionLock lock; + mbed::CriticalSectionLock lock; return data; } void store(T desired, memory_order order = memory_order_seq_cst) volatile noexcept { MBED_CHECK_STORE_ORDER(order); - CriticalSectionLock lock; + mbed::CriticalSectionLock lock; memcpy(const_cast(std::addressof(data)), std::addressof(desired), sizeof(T)); } void store(T desired, memory_order order = memory_order_seq_cst) noexcept { MBED_CHECK_STORE_ORDER(order); - CriticalSectionLock lock; + mbed::CriticalSectionLock lock; data = std::move(desired); // MoveAssignable } T exchange(T desired, memory_order = memory_order_seq_cst) volatile noexcept @@ -217,7 +217,7 @@ struct AtomicBaseRaw { T val; } old; { - CriticalSectionLock lock; + mbed::CriticalSectionLock lock; memcpy(std::addressof(old.val), const_cast(std::addressof(data)), sizeof(T)); memcpy(const_cast(std::addressof(data)), std::addressof(desired), sizeof(T)); } @@ -225,7 +225,7 @@ struct AtomicBaseRaw { } T exchange(T desired, memory_order = memory_order_seq_cst) noexcept { - CriticalSectionLock lock; + mbed::CriticalSectionLock lock; T old = std::move(data); // MoveConstructible data = std::move(desired); // MoveAssignable return old; @@ -233,7 +233,7 @@ struct AtomicBaseRaw { bool compare_exchange_strong(T &expected, T desired, memory_order success, memory_order failure) volatile noexcept { MBED_CHECK_CAS_ORDER(success, failure); - CriticalSectionLock lock; + mbed::CriticalSectionLock lock; if (memcmp(const_cast(std::addressof(data)), std::addressof(expected), sizeof(T)) == 0) { memcpy(const_cast(std::addressof(data)), std::addressof(desired), sizeof(T)); return true; @@ -245,7 +245,7 @@ struct AtomicBaseRaw { bool compare_exchange_strong(T &expected, T desired, memory_order success, memory_order failure) noexcept { MBED_CHECK_CAS_ORDER(success, failure); - CriticalSectionLock lock; + mbed::CriticalSectionLock lock; if (memcmp(std::addressof(data), std::addressof(expected), sizeof(T)) == 0) { data = std::move(desired); // MoveAssignable return true; diff --git a/platform/include/platform/mbed_retarget.h b/platform/include/platform/mbed_retarget.h index b40125fcf3..bfc4183bec 100644 --- a/platform/include/platform/mbed_retarget.h +++ b/platform/include/platform/mbed_retarget.h @@ -37,6 +37,10 @@ #endif #include +#if !defined(__ARMCC_VERSION) +#include +#endif + #if defined __has_include # if __has_include () # include @@ -63,17 +67,36 @@ typedef unsigned int gid_t; ///< Group ID /* Flags for open() and fcntl(GETFL/SETFL) * At present, fcntl only supports reading and writing O_NONBLOCK */ +#ifndef O_RDONLY #define O_RDONLY 0 ///< Open for reading +#endif +#ifndef O_WRONLY #define O_WRONLY 1 ///< Open for writing +#endif +#ifndef O_RDWR #define O_RDWR 2 ///< Open for reading and writing +#endif +#ifndef O_NONBLOCK #define O_NONBLOCK 0x0004 ///< Non-blocking mode +#endif +#ifndef O_APPEND #define O_APPEND 0x0008 ///< Set file offset to end of file prior to each write +#endif +#ifndef O_CREAT #define O_CREAT 0x0200 ///< Create file if it does not exist +#endif +#ifndef O_TRUNC #define O_TRUNC 0x0400 ///< Truncate file to zero length +#endif +#ifndef O_EXCL #define O_EXCL 0x0800 ///< Fail if file exists +#endif +#ifndef O_BINARY #define O_BINARY 0x8000 ///< Open file in binary mode - +#endif +#ifndef O_ACCMODE #define O_ACCMODE (O_RDONLY|O_WRONLY|O_RDWR) +#endif #define NAME_MAX 255 ///< Maximum size of a name in a file path @@ -196,268 +219,399 @@ typedef struct DIR_impl DIR; * the GCC_ARM/IAR/standard POSIX definitions. The definitions guard against * this and future changes by changing the symbol definition as shown below. */ -#undef EPERM +#ifndef EPERM #define EPERM 1 /* Operation not permitted */ -#undef ENOENT +#endif +#ifndef ENOENT #define ENOENT 2 /* No such file or directory */ -#undef ESRCH +#endif +#ifndef ESRCH #define ESRCH 3 /* No such process */ -#undef EINTR +#endif +#ifndef EINTR #define EINTR 4 /* Interrupted system call */ -#undef EIO +#endif +#ifndef EIO #define EIO 5 /* I/O error */ -#undef ENXIO +#endif +#ifndef ENXIO #define ENXIO 6 /* No such device or address */ -#undef E2BIG +#endif +#ifndef E2BIG #define E2BIG 7 /* Argument list too long */ -#undef ENOEXEC +#endif +#ifndef ENOEXEC #define ENOEXEC 8 /* Exec format error */ -#undef EBADF +#endif +#ifndef EBADF #define EBADF 9 /* Bad file number */ -#undef ECHILD +#endif +#ifndef ECHILD #define ECHILD 10 /* No child processes */ -#undef EAGAIN +#endif +#ifndef EAGAIN #define EAGAIN 11 /* Try again */ -#undef ENOMEM +#endif +#ifndef ENOMEM #define ENOMEM 12 /* Out of memory */ -#undef EACCES +#endif +#ifndef EACCES #define EACCES 13 /* Permission denied */ -#undef EFAULT +#endif +#ifndef EFAULT #define EFAULT 14 /* Bad address */ -#undef ENOTBLK +#endif +#ifndef ENOTBLK #define ENOTBLK 15 /* Block device required */ -#undef EBUSY +#endif +#ifndef EBUSY #define EBUSY 16 /* Device or resource busy */ -#undef EEXIST +#endif +#ifndef EEXIST #define EEXIST 17 /* File exists */ -#undef EXDEV +#endif +#ifndef EXDEV #define EXDEV 18 /* Cross-device link */ -#undef ENODEV +#endif +#ifndef ENODEV #define ENODEV 19 /* No such device */ -#undef ENOTDIR +#endif +#ifndef ENOTDIR #define ENOTDIR 20 /* Not a directory */ -#undef EISDIR +#endif +#ifndef EISDIR #define EISDIR 21 /* Is a directory */ -#undef EINVAL +#endif +#ifndef EINVAL #define EINVAL 22 /* Invalid argument */ -#undef ENFILE +#endif +#ifndef ENFILE #define ENFILE 23 /* File table overflow */ -#undef EMFILE +#endif +#ifndef EMFILE #define EMFILE 24 /* Too many open files */ -#undef ENOTTY +#endif +#ifndef ENOTTY #define ENOTTY 25 /* Not a typewriter */ -#undef ETXTBSY +#endif +#ifndef ETXTBSY #define ETXTBSY 26 /* Text file busy */ -#undef EFBIG +#endif +#ifndef EFBIG #define EFBIG 27 /* File too large */ -#undef ENOSPC +#endif +#ifndef ENOSPC #define ENOSPC 28 /* No space left on device */ -#undef ESPIPE +#endif +#ifndef ESPIPE #define ESPIPE 29 /* Illegal seek */ -#undef EROFS +#endif +#ifndef EROFS #define EROFS 30 /* Read-only file system */ -#undef EMLINK +#endif +#ifndef EMLINK #define EMLINK 31 /* Too many links */ -#undef EPIPE +#endif +#ifndef EPIPE #define EPIPE 32 /* Broken pipe */ -#undef EDOM +#endif +#ifndef EDOM #define EDOM 33 /* Math argument out of domain of func */ -#undef ERANGE +#endif +#ifndef ERANGE #define ERANGE 34 /* Math result not representable */ -#undef EDEADLK +#endif +#ifndef EDEADLK #define EDEADLK 35 /* Resource deadlock would occur */ -#undef ENAMETOOLONG +#endif +#ifndef ENAMETOOLONG #define ENAMETOOLONG 36 /* File name too long */ -#undef ENOLCK +#endif +#ifndef ENOLCK #define ENOLCK 37 /* No record locks available */ -#undef ENOSYS +#endif +#ifndef ENOSYS #define ENOSYS 38 /* Function not implemented */ -#undef ENOTEMPTY +#endif +#ifndef ENOTEMPTY #define ENOTEMPTY 39 /* Directory not empty */ -#undef ELOOP +#endif +#ifndef ELOOP #define ELOOP 40 /* Too many symbolic links encountered */ -#undef EWOULDBLOCK +#endif +#ifndef EWOULDBLOCK #define EWOULDBLOCK EAGAIN /* Operation would block */ -#undef ENOMSG +#endif +#ifndef ENOMSG #define ENOMSG 42 /* No message of desired type */ -#undef EIDRM +#endif +#ifndef EIDRM #define EIDRM 43 /* Identifier removed */ -#undef ECHRNG +#endif +#ifndef ECHRNG #define ECHRNG 44 /* Channel number out of range */ -#undef EL2NSYNC -#define EL2NSYNC 45 /* Level 2 not synchronized */ -#undef EL3HLT -#define EL3HLT 46 /* Level 3 halted */ -#undef EL3RST +#endif +#ifndef EL2NSYNC +#define EL2NSYNC 245 /* Level 2 not synchronized */ +#endif +#ifndef EL3HLT +#define EL3HLT 246 /* Level 3 halted */ +#endif +#ifndef EL3RST #define EL3RST 47 /* Level 3 reset */ -#undef ELNRNG +#endif +#ifndef ELNRNG #define ELNRNG 48 /* Link number out of range */ -#undef EUNATCH +#endif +#ifndef EUNATCH #define EUNATCH 49 /* Protocol driver not attached */ -#undef ENOCSI +#endif +#ifndef ENOCSI #define ENOCSI 50 /* No CSI structure available */ -#undef EL2HLT +#endif +#ifndef EL2HLT #define EL2HLT 51 /* Level 2 halted */ -#undef EBADE +#endif +#ifndef EBADE #define EBADE 52 /* Invalid exchange */ -#undef EBADR +#endif +#ifndef EBADR #define EBADR 53 /* Invalid request descriptor */ -#undef EXFULL +#endif +#ifndef EXFULL #define EXFULL 54 /* Exchange full */ -#undef ENOANO +#endif +#ifndef ENOANO #define ENOANO 55 /* No anode */ -#undef EBADRQC +#endif +#ifndef EBADRQC #define EBADRQC 56 /* Invalid request code */ -#undef EBADSLT +#endif +#ifndef EBADSLT #define EBADSLT 57 /* Invalid slot */ -#undef EDEADLOCK +#endif +#ifndef EDEADLOCK #define EDEADLOCK EDEADLK /* Resource deadlock would occur */ -#undef EBFONT +#endif +#ifndef EBFONT #define EBFONT 59 /* Bad font file format */ -#undef ENOSTR +#endif +#ifndef ENOSTR #define ENOSTR 60 /* Device not a stream */ -#undef ENODATA +#endif +#ifndef ENODATA #define ENODATA 61 /* No data available */ -#undef ETIME +#endif +#ifndef ETIME #define ETIME 62 /* Timer expired */ -#undef ENOSR +#endif +#ifndef ENOSR #define ENOSR 63 /* Out of streams resources */ -#undef ENONET +#endif +#ifndef ENONET #define ENONET 64 /* Machine is not on the network */ -#undef ENOPKG +#endif +#ifndef ENOPKG #define ENOPKG 65 /* Package not installed */ -#undef EREMOTE +#endif +#ifndef EREMOTE #define EREMOTE 66 /* Object is remote */ -#undef ENOLINK +#endif +#ifndef ENOLINK #define ENOLINK 67 /* Link has been severed */ -#undef EADV +#endif +#ifndef EADV #define EADV 68 /* Advertise error */ -#undef ESRMNT +#endif +#ifndef ESRMNT #define ESRMNT 69 /* Srmount error */ -#undef ECOMM +#endif +#ifndef ECOMM #define ECOMM 70 /* Communication error on send */ -#undef EPROTO +#endif +#ifndef EPROTO #define EPROTO 71 /* Protocol error */ -#undef EMULTIHOP +#endif +#ifndef EMULTIHOP #define EMULTIHOP 72 /* Multihop attempted */ -#undef EDOTDOT +#endif +#ifndef EDOTDOT #define EDOTDOT 73 /* RFS specific error */ -#undef EBADMSG +#endif +#ifndef EBADMSG #define EBADMSG 74 /* Not a data message */ -#undef EOVERFLOW +#endif +#ifndef EOVERFLOW #define EOVERFLOW 75 /* Value too large for defined data type */ -#undef ENOTUNIQ +#endif +#ifndef ENOTUNIQ #define ENOTUNIQ 76 /* Name not unique on network */ -#undef EBADFD -#define EBADFD 77 /* File descriptor in bad state */ -#undef EREMCHG +#endif +#ifndef EBADFD +#define EBADFD 277 /* File descriptor in bad state */ +#endif +#ifndef EREMCHG #define EREMCHG 78 /* Remote address changed */ -#undef ELIBACC +#endif +#ifndef ELIBACC #define ELIBACC 79 /* Can not access a needed shared library */ -#undef ELIBBAD +#endif +#ifndef ELIBBAD #define ELIBBAD 80 /* Accessing a corrupted shared library */ -#undef ELIBSCN +#endif +#ifndef ELIBSCN #define ELIBSCN 81 /* .lib section in a.out corrupted */ -#undef ELIBMAX +#endif +#ifndef ELIBMAX #define ELIBMAX 82 /* Attempting to link in too many shared libraries */ -#undef ELIBEXEC +#endif +#ifndef ELIBEXEC #define ELIBEXEC 83 /* Cannot exec a shared library directly */ -#undef EILSEQ +#endif +#ifndef EILSEQ #define EILSEQ 84 /* Illegal byte sequence */ -#undef ERESTART -#define ERESTART 85 /* Interrupted system call should be restarted */ -#undef ESTRPIPE +#endif +#ifndef ERESTART +#define ERESTART 285 /* Interrupted system call should be restarted */ +#endif +#ifndef ESTRPIPE #define ESTRPIPE 86 /* Streams pipe error */ -#undef EUSERS +#endif +#ifndef EUSERS #define EUSERS 87 /* Too many users */ -#undef ENOTSOCK +#endif +#ifndef ENOTSOCK #define ENOTSOCK 88 /* Socket operation on non-socket */ -#undef EDESTADDRREQ +#endif +#ifndef EDESTADDRREQ #define EDESTADDRREQ 89 /* Destination address required */ -#undef EMSGSIZE +#endif +#ifndef EMSGSIZE #define EMSGSIZE 90 /* Message too long */ -#undef EPROTOTYPE +#endif +#ifndef EPROTOTYPE #define EPROTOTYPE 91 /* Protocol wrong type for socket */ -#undef ENOPROTOOPT +#endif +#ifndef ENOPROTOOPT #define ENOPROTOOPT 92 /* Protocol not available */ -#undef EPROTONOSUPPORT +#endif +#ifndef EPROTONOSUPPORT #define EPROTONOSUPPORT 93 /* Protocol not supported */ -#undef ESOCKTNOSUPPORT +#endif +#ifndef ESOCKTNOSUPPORT #define ESOCKTNOSUPPORT 94 /* Socket type not supported */ -#undef EOPNOTSUPP +#endif +#ifndef EOPNOTSUPP #define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ -#undef EPFNOSUPPORT +#endif +#ifndef EPFNOSUPPORT #define EPFNOSUPPORT 96 /* Protocol family not supported */ -#undef EAFNOSUPPORT +#endif +#ifndef EAFNOSUPPORT #define EAFNOSUPPORT 97 /* Address family not supported by protocol */ -#undef EADDRINUSE +#endif +#ifndef EADDRINUSE #define EADDRINUSE 98 /* Address already in use */ -#undef EADDRNOTAVAIL +#endif +#ifndef EADDRNOTAVAIL #define EADDRNOTAVAIL 99 /* Cannot assign requested address */ -#undef ENETDOWN +#endif +#ifndef ENETDOWN #define ENETDOWN 100 /* Network is down */ -#undef ENETUNREACH +#endif +#ifndef ENETUNREACH #define ENETUNREACH 101 /* Network is unreachable */ -#undef ENETRESET +#endif +#ifndef ENETRESET #define ENETRESET 102 /* Network dropped connection because of reset */ -#undef ECONNABORTED +#endif +#ifndef ECONNABORTED #define ECONNABORTED 103 /* Software caused connection abort */ -#undef ECONNRESET +#endif +#ifndef ECONNRESET #define ECONNRESET 104 /* Connection reset by peer */ -#undef ENOBUFS +#endif +#ifndef ENOBUFS #define ENOBUFS 105 /* No buffer space available */ -#undef EISCONN +#endif +#ifndef EISCONN #define EISCONN 106 /* Transport endpoint is already connected */ -#undef ENOTCONN +#endif +#ifndef ENOTCONN #define ENOTCONN 107 /* Transport endpoint is not connected */ -#undef ESHUTDOWN -#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ -#undef ETOOMANYREFS +#endif +#ifndef ESHUTDOWN +#define ESHUTDOWN 208 /* Cannot send after transport endpoint shutdown */ +#endif +#ifndef ETOOMANYREFS #define ETOOMANYREFS 109 /* Too many references: cannot splice */ -#undef ETIMEDOUT +#endif +#ifndef ETIMEDOUT #define ETIMEDOUT 110 /* Connection timed out */ -#undef ECONNREFUSED +#endif +#ifndef ECONNREFUSED #define ECONNREFUSED 111 /* Connection refused */ -#undef EHOSTDOWN +#endif +#ifndef EHOSTDOWN #define EHOSTDOWN 112 /* Host is down */ -#undef EHOSTUNREACH +#endif +#ifndef EHOSTUNREACH #define EHOSTUNREACH 113 /* No route to host */ -#undef EALREADY +#endif +#ifndef EALREADY #define EALREADY 114 /* Operation already in progress */ -#undef EINPROGRESS +#endif +#ifndef EINPROGRESS #define EINPROGRESS 115 /* Operation now in progress */ -#undef ESTALE +#endif +#ifndef ESTALE #define ESTALE 116 /* Stale NFS file handle */ -#undef EUCLEAN -#define EUCLEAN 117 /* Structure needs cleaning */ -#undef ENOTNAM -#define ENOTNAM 118 /* Not a XENIX named type file */ -#undef ENAVAIL -#define ENAVAIL 119 /* No XENIX semaphores available */ -#undef EISNAM -#define EISNAM 120 /* Is a named type file */ -#undef EREMOTEIO -#define EREMOTEIO 121 /* Remote I/O error */ -#undef EDQUOT +#endif +#ifndef EUCLEAN +#define EUCLEAN 217 /* Structure needs cleaning */ +#endif +#ifndef ENOTNAM +#define ENOTNAM 218 /* Not a XENIX named type file */ +#endif +#ifndef ENAVAIL +#define ENAVAIL 219 /* No XENIX semaphores available */ +#endif +#ifndef EISNAM +#define EISNAM 220 /* Is a named type file */ +#endif +#ifndef EREMOTEIO +#define EREMOTEIO 221 /* Remote I/O error */ +#endif +#ifndef EDQUOT #define EDQUOT 122 /* Quota exceeded */ -#undef ENOMEDIUM -#define ENOMEDIUM 123 /* No medium found */ -#undef EMEDIUMTYPE -#define EMEDIUMTYPE 124 /* Wrong medium type */ -#undef ECANCELED +#endif +#ifndef ENOMEDIUM +#define ENOMEDIUM 223 /* No medium found */ +#endif +#ifndef EMEDIUMTYPE +#define EMEDIUMTYPE 224 /* Wrong medium type */ +#endif +#ifndef ECANCELED #define ECANCELED 125 /* Operation Canceled */ -#undef ENOKEY -#define ENOKEY 126 /* Required key not available */ -#undef EKEYEXPIRED -#define EKEYEXPIRED 127 /* Key has expired */ -#undef EKEYREVOKED -#define EKEYREVOKED 128 /* Key has been revoked */ -#undef EKEYREJECTED -#define EKEYREJECTED 129 /* Key was rejected by service */ -#undef EOWNERDEAD +#endif +#ifndef ENOKEY +#define ENOKEY 226 /* Required key not available */ +#endif +#ifndef EKEYEXPIRED +#define EKEYEXPIRED 227 /* Key has expired */ +#endif +#ifndef EKEYREVOKED +#define EKEYREVOKED 228 /* Key has been revoked */ +#endif +#ifndef EKEYREJECTED +#define EKEYREJECTED 229 /* Key was rejected by service */ +#endif +#ifndef EOWNERDEAD #define EOWNERDEAD 130 /* Owner died */ -#undef ENOTRECOVERABLE +#endif +#ifndef ENOTRECOVERABLE #define ENOTRECOVERABLE 131 /* State not recoverable */ +#endif /* Missing stat.h defines. * The following are sys/stat.h definitions not currently present in the ARMCC diff --git a/platform/include/platform/mbed_version.h b/platform/include/platform/mbed_version.h index 93a3ae0cd9..17e8512d4b 100644 --- a/platform/include/platform/mbed_version.h +++ b/platform/include/platform/mbed_version.h @@ -38,7 +38,7 @@ * * @note 99 is default value for development version (master branch) */ -#define MBED_MINOR_VERSION 11 +#define MBED_MINOR_VERSION 12 /** MBED_PATCH_VERSION * Mbed OS patch version diff --git a/platform/mbed_lib.json b/platform/mbed_lib.json index 756c1981d2..73ae742940 100644 --- a/platform/mbed_lib.json +++ b/platform/mbed_lib.json @@ -208,6 +208,9 @@ "NU_PFM_M2351": { "stdio-baud-rate": 115200 }, + "NU_M2354": { + "stdio-baud-rate": 115200 + }, "NRF52840_DK": { "crash-capture-enabled": true, "fatal-error-auto-reboot-enabled": true diff --git a/platform/source/TARGET_CORTEX_M/CMakeLists.txt b/platform/source/TARGET_CORTEX_M/CMakeLists.txt index 481d09bd21..298fa20a28 100644 --- a/platform/source/TARGET_CORTEX_M/CMakeLists.txt +++ b/platform/source/TARGET_CORTEX_M/CMakeLists.txt @@ -1,11 +1,7 @@ # Copyright (c) 2020-2021 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 -if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") - target_sources(mbed-core INTERFACE TOOLCHAIN_GCC/except.S) -elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") - target_sources(mbed-core INTERFACE TOOLCHAIN_ARM/except.S) -endif() +target_sources(mbed-core INTERFACE TOOLCHAIN_GCC/except.S) target_sources(mbed-core INTERFACE diff --git a/platform/source/TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S b/platform/source/TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S index a40e743cf1..ac95155fd4 100644 --- a/platform/source/TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S +++ b/platform/source/TARGET_CORTEX_M/TOOLCHAIN_GCC/except.S @@ -105,7 +105,11 @@ UsageFault_Handler: Fault_Handler: #if (DOMAIN_NS == 1) #if MBED_CONF_PLATFORM_CRASH_CAPTURE_ENABLED +#if defined(__ARMCC_VERSION) +#define mbed_fault_context Image$$RW_m_crash_data$$ZI$$Base +#else #define mbed_fault_context __CRASH_DATA_RAM_START__ +#endif #endif MOV R12,R3 diff --git a/platform/source/mbed_retarget.cpp b/platform/source/mbed_retarget.cpp index 57cef972c4..28201757a2 100644 --- a/platform/source/mbed_retarget.cpp +++ b/platform/source/mbed_retarget.cpp @@ -1181,7 +1181,7 @@ extern "C" int fcntl(int fildes, int cmd, ...) switch (cmd) { case F_GETFL: { int flags = 0; - if (fhc->is_blocking()) { + if (!fhc->is_blocking()) { flags |= O_NONBLOCK; } return flags; @@ -1191,11 +1191,12 @@ extern "C" int fcntl(int fildes, int cmd, ...) va_start(ap, cmd); int flags = va_arg(ap, int); va_end(ap); - int ret = fhc->set_blocking(flags & O_NONBLOCK); + int ret = fhc->set_blocking(!(flags & O_NONBLOCK)); if (ret < 0) { errno = -ret; return -1; } + return 0; } @@ -1933,3 +1934,298 @@ extern "C" MBED_WEAK long int _scanf_mbtowc( { return 0; } + +static void validate_errno_values(int value) +{ + + switch (value) { + case EPERM: + break; + case ENOENT: + break; + case ESRCH: + break; + case EINTR: + break; + case EIO: + break; + case ENXIO: + break; + case E2BIG: + break; + case ENOEXEC: + break; + case EBADF: + break; + case ECHILD: + break; + case ENOMEM: + break; + case EACCES: + break; + case EFAULT: + break; + case ENOTBLK: + break; + case EBUSY: + break; + case EEXIST: + break; + case EXDEV: + break; + case ENODEV: + break; + case ENOTDIR: + break; + case EISDIR: + break; + case EINVAL: + break; + case ENFILE: + break; + case EMFILE: + break; + case ENOTTY: + break; + case ETXTBSY: + break; + case EFBIG: + break; + case ENOSPC: + break; + case ESPIPE: + break; + case EROFS: + break; + case EMLINK: + break; + case EPIPE: + break; + case EDOM: + break; + case ERANGE: + break; + case EDEADLK: + break; + case ENAMETOOLONG: + break; + case ENOLCK: + break; + case ENOSYS: + break; + case ENOTEMPTY: + break; + case ELOOP: + break; + case ENOMSG: + break; + case EIDRM: + break; + case ECHRNG: + break; + case EL2NSYNC: + break; + case EL3HLT: + break; + case EL3RST: + break; + case ELNRNG: + break; + case EUNATCH: + break; + case ENOCSI: + break; + case EL2HLT: + break; + case EBADE: + break; + case EBADR: + break; + case EXFULL: + break; + case ENOANO: + break; + case EBADRQC: + break; + case EBADSLT: + break; + case EBFONT: + break; + case ENOSTR: + break; + case ENODATA: + break; + case ETIME: + break; + case ENOSR: + break; + case ENONET: + break; + case ENOPKG: + break; + case EREMOTE: + break; + case ENOLINK: + break; + case EADV: + break; + case ESRMNT: + break; + case ECOMM: + break; + case EPROTO: + break; + case EMULTIHOP: + break; + case EDOTDOT: + break; + case EBADMSG: + break; + case EOVERFLOW: + break; + case ENOTUNIQ: + break; + case EBADFD: + break; + case EREMCHG: + break; + case ELIBACC: + break; + case ELIBBAD: + break; + case ELIBSCN: + break; + case ELIBMAX: + break; + case ELIBEXEC: + break; + case EILSEQ: + break; + case ERESTART: + break; + case ESTRPIPE: + break; + case EUSERS: + break; + case ENOTSOCK: + break; + case EDESTADDRREQ: + break; + case EMSGSIZE: + break; + case EPROTOTYPE: + break; + case ENOPROTOOPT: + break; + case EPROTONOSUPPORT: + break; + case ESOCKTNOSUPPORT: + break; + case EOPNOTSUPP: + break; + case EPFNOSUPPORT: + break; + case EAFNOSUPPORT: + break; + case EADDRINUSE: + break; + case EADDRNOTAVAIL: + break; + case ENETDOWN: + break; + case ENETUNREACH: + break; + case ENETRESET: + break; + case ECONNABORTED: + break; + case ECONNRESET: + break; + case ENOBUFS: + break; + case EISCONN: + break; + case ENOTCONN: + break; + case ESHUTDOWN: + break; + case ETOOMANYREFS: + break; + case ETIMEDOUT: + break; + case ECONNREFUSED: + break; + case EHOSTDOWN: + break; + case EHOSTUNREACH: + break; + case EALREADY: + break; + case EINPROGRESS: + break; + case ESTALE: + break; + case EUCLEAN: + break; + case ENOTNAM: + break; + case ENAVAIL: + break; + case EISNAM: + break; + case EREMOTEIO: + break; + case EDQUOT: + break; + case ENOMEDIUM: + break; + case EMEDIUMTYPE: + break; + case ECANCELED: + break; + case ENOKEY: + break; + case EKEYEXPIRED: + break; + case EKEYREVOKED: + break; + case EKEYREJECTED: + break; + case EOWNERDEAD: + break; + case ENOTRECOVERABLE: + break; +#if EAGAIN != EWOULDBLOCK + case EAGAIN: +#endif + case EWOULDBLOCK: + break; + }; + + switch (value) { + case O_RDONLY: + break; + case O_WRONLY: + break; + case O_RDWR: + break; + case O_NONBLOCK: + break; + case O_APPEND: + break; + case O_CREAT: + break; + case O_TRUNC: + break; + case O_EXCL: + break; + case O_BINARY: + break; + case O_ACCMODE: + break; + }; + + + static_assert((O_ACCMODE & (O_NONBLOCK | O_APPEND | O_CREAT | O_TRUNC | O_EXCL | O_BINARY)) == 0, "O_ACCMODE clash"); + +} diff --git a/platform/tests/UNITTESTS/ATCmdParser/CMakeLists.txt b/platform/tests/UNITTESTS/ATCmdParser/CMakeLists.txt new file mode 100644 index 0000000000..eeda6edee1 --- /dev/null +++ b/platform/tests/UNITTESTS/ATCmdParser/CMakeLists.txt @@ -0,0 +1,24 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME atcmdparser-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/platform/source/ATCmdParser.cpp + test_ATCmdParser.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "platform") diff --git a/platform/tests/UNITTESTS/ATCmdParser/unittest.cmake b/platform/tests/UNITTESTS/ATCmdParser/unittest.cmake deleted file mode 100644 index 77c8433dfd..0000000000 --- a/platform/tests/UNITTESTS/ATCmdParser/unittest.cmake +++ /dev/null @@ -1,16 +0,0 @@ -#################### -# UNIT TESTS -#################### - -# Source files -set(unittest-sources - ../platform/source/ATCmdParser.cpp -) - -# Test files -set(unittest-test-sources - ../platform/tests/UNITTESTS/ATCmdParser/test_ATCmdParser.cpp - stubs/FileHandle_stub.cpp - stubs/mbed_assert_stub.cpp - stubs/mbed_poll_stub.cpp -) diff --git a/platform/tests/UNITTESTS/CMakeLists.txt b/platform/tests/UNITTESTS/CMakeLists.txt new file mode 100644 index 0000000000..65eb23055d --- /dev/null +++ b/platform/tests/UNITTESTS/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(ATCmdParser) +add_subdirectory(CircularBuffer) diff --git a/platform/tests/UNITTESTS/CircularBuffer/CMakeLists.txt b/platform/tests/UNITTESTS/CircularBuffer/CMakeLists.txt new file mode 100644 index 0000000000..45fd750888 --- /dev/null +++ b/platform/tests/UNITTESTS/CircularBuffer/CMakeLists.txt @@ -0,0 +1,22 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME circularbuffer-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + test_CircularBuffer.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "platform") diff --git a/platform/tests/UNITTESTS/CircularBuffer/unittest.cmake b/platform/tests/UNITTESTS/CircularBuffer/unittest.cmake deleted file mode 100644 index b9c59e0ece..0000000000 --- a/platform/tests/UNITTESTS/CircularBuffer/unittest.cmake +++ /dev/null @@ -1,13 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-sources -) - -set(unittest-test-sources - ../platform/tests/UNITTESTS/CircularBuffer/test_CircularBuffer.cpp - stubs/mbed_critical_stub.c - stubs/mbed_assert_stub.cpp -) diff --git a/storage/CMakeLists.txt b/storage/CMakeLists.txt index 95d984e077..df4d8a2932 100644 --- a/storage/CMakeLists.txt +++ b/storage/CMakeLists.txt @@ -26,11 +26,17 @@ add_library(mbed-storage-kv-config INTERFACE) add_library(mbed-storage-direct-access-devicekey INTERFACE) add_library(mbed-storage-kv-global-api INTERFACE) - -add_subdirectory(blockdevice) -add_subdirectory(filesystem) -add_subdirectory(kvstore) -add_subdirectory(platform) +if(${CMAKE_CROSSCOMPILING}) + # The directories below contain optional target libraries + add_subdirectory(blockdevice EXCLUDE_FROM_ALL) + add_subdirectory(filesystem EXCLUDE_FROM_ALL) + add_subdirectory(kvstore EXCLUDE_FROM_ALL) + add_subdirectory(platform EXCLUDE_FROM_ALL) +else() + # Add these subdirectories for the Unit test + add_subdirectory(blockdevice) + add_subdirectory(kvstore) +endif() target_include_directories(mbed-storage INTERFACE diff --git a/storage/blockdevice/CMakeLists.txt b/storage/blockdevice/CMakeLists.txt index 6181735cd3..9f847d4360 100644 --- a/storage/blockdevice/CMakeLists.txt +++ b/storage/blockdevice/CMakeLists.txt @@ -1,6 +1,10 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) + add_subdirectory(tests/UNITTESTS) +endif() + if("DATAFLASH" IN_LIST MBED_TARGET_LABELS) add_subdirectory(COMPONENT_DATAFLASH) endif() diff --git a/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/MX25LM51245G_config.h b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/MX25LM51245G_config.h index 2eeb4f2308..de45f6125e 100644 --- a/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/MX25LM51245G_config.h +++ b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/MX25LM51245G_config.h @@ -17,7 +17,6 @@ #ifndef MBED_OSPI_FLASH_MX25LM51245G_H #define MBED_OSPI_FLASH_MX25LM51245G_H - #define OSPI_FLASH_CHIP_STRING "macronix MX25LM51245G" // This is a workaround, @@ -26,20 +25,13 @@ // The code below can be removed when users test with the new flash. #define NEED_DEFINE_SFDP_PARA -#ifdef NEED_DEFINE_SFDP_PARA -uint8_t _sfdp_head_table[32] = {0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x02, 0xFF, 0x00, 0x06, 0x01, - 0x10, 0x30, 0x00, 0x00, 0xFF, 0xC2, 0x00, 0x01, 0x04, 0x10, 0x01, - 0x00, 0xFF, 0x84, 0x00, 0x01, 0x02, 0xC0, 0x00, 0x00, 0xFF - }; -uint8_t _sfdp_basic_param_table[64] = {0x30, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x14, 0xEC, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0C, 0x20, - 0x10, 0xDC, 0x00, 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0x81, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0x50, 0xF9, 0x80 - }; -uint8_t _sfdp_4_byte_inst_table[8] = {0x7F, 0xEF, 0xFF, 0xFF, 0x21, 0x5C, 0xDC, 0x14}; -#endif +#define OSPIF_CR2_OPI_EN_ADDR 0x00000000 + +#define MX_FLASH_BLOCK_SIZE 0x10000 /* 1024 blocks of 64 KBytes */ +#define MX_FLASH_SECTOR_SIZE 0x1000 /* 16384 sectors of 4 kBytes */ +#define MX_FLASH_PAGE_SIZE 0x100 /* 262144 pages of 256 bytes */ +#define MX_FLASH_CHUNK_SIZE 0x10 /* 16 bytes */ +#define MX_FLASH_BANK_SIZE 0x01000000 /* 16 MBytes */ +#define MX_FLASH_BANK_SIZE_MASK ~(MX_FLASH_BANK_SIZE - 1) /* 0xFF000000 */ #endif // MBED_OSPI_FLASH_MX25LM51245G_H diff --git a/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/MX25LW51245G_config.h b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/MX25LW51245G_config.h new file mode 100644 index 0000000000..73aefc61f3 --- /dev/null +++ b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/MX25LW51245G_config.h @@ -0,0 +1,44 @@ +/* mbed Microcontroller Library + * Copyright (c) 2020 ARM Limited + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_OSPI_FLASH_MX25LW51245G_H +#define MBED_OSPI_FLASH_MX25LW51245G_H + +#define OSPI_FLASH_CHIP_STRING "macronix MX25LW51245G" + +// This is a workaround, +// The sfdp parameter values in Macronix old octaflash(include the MX25LW51245G on L4R9I_DISCO) are all 0xFF, +// so we need to define the parameter values by software to support SFDP parsing. +// The code below can be removed when users test with the new flash. +#define NEED_DEFINE_SFDP_PARA + +#define MX_FLASH_SUPPORT_RWW 1 + +// Configuration Register2 address +#define OSPIF_CR2_OPI_EN_ADDR 0x00000000 +#define OSPIF_CR2_BANK_STATUS_ADDR 0xc0000000 +#define OSPIF_CR2_RWWDI ((uint8_t)0x00) /*!< No active program or erase operation */ +#define OSPIF_CR2_RWWDS ((uint8_t)0x01) /*!< Program/erase in other bank */ +#define OSPIF_CR2_RWWBS ((uint8_t)0x03) /*!< program/erase operation in addressed bank */ + +#define MX_FLASH_BLOCK_SIZE 0x10000 /* 1024 blocks of 64 KBytes */ +#define MX_FLASH_SECTOR_SIZE 0x1000 /* 16384 sectors of 4 kBytes */ +#define MX_FLASH_PAGE_SIZE 0x100 /* 262144 pages of 256 bytes */ +#define MX_FLASH_CHUNK_SIZE 0x10 /* 16 bytes */ +#define MX_FLASH_BANK_SIZE 0x01000000 /* 16 MBytes */ +#define MX_FLASH_BANK_SIZE_MASK ~(MX_FLASH_BANK_SIZE - 1) /* 0xFF000000 */ + +#endif // MBED_OSPI_FLASH_MX25LW51245G_H diff --git a/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h index b61f0ebb1e..2b0799dd8e 100644 --- a/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h +++ b/storage/blockdevice/COMPONENT_OSPIF/include/OSPIF/OSPIFBlockDevice.h @@ -22,6 +22,14 @@ #include "blockdevice/BlockDevice.h" #include "platform/Callback.h" +#if defined(TARGET_MX25LM51245G) +#include "MX25LM51245G_config.h" +#endif + +#if defined(TARGET_MX25LW51245G) +#include "MX25LW51245G_config.h" +#endif + #ifndef MBED_CONF_OSPIF_OSPI_IO0 #define MBED_CONF_OSPIF_OSPI_IO0 NC #endif @@ -381,6 +389,10 @@ private: // Detect 4-byte addressing mode and enable it if supported int _sfdp_detect_and_enable_4byte_addressing(uint8_t *basic_param_table_ptr, int basic_param_table_size); +#ifdef MX_FLASH_SUPPORT_RWW + bool _is_mem_ready_rww(bd_addr_t addr, uint8_t rw); +#endif + private: enum ospif_clear_protection_method_t { OSPIF_BP_ULBPR, // Issue global protection unlock instruction @@ -449,6 +461,16 @@ private: uint32_t _init_ref_count; bool _is_initialized; +#ifdef MX_FLASH_SUPPORT_RWW + enum wait_flag { + NOT_STARTED, // no wait is started + WRITE_WAIT_STARTED, // write wait is started + ERASE_WAIT_STARTED, // erase wait is started + }; + uint32_t _busy_bank; // Current busy bank + wait_flag _wait_flag; // wait flag + PlatformMutex _busy_mutex; +#endif }; #endif diff --git a/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp b/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp index e03bc89f7f..f6857e6ca7 100644 --- a/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp +++ b/storage/blockdevice/COMPONENT_OSPIF/source/OSPIFBlockDevice.cpp @@ -20,9 +20,6 @@ #include "OSPIFBlockDevice.h" #include #include "rtos/ThisThread.h" -#if defined(TARGET_MX25LM51245G) -#include "MX25LM51245G_config.h" -#endif #ifndef MBED_CONF_MBED_TRACE_ENABLE #define MBED_CONF_MBED_TRACE_ENABLE 0 @@ -51,9 +48,6 @@ using namespace mbed; #define OSPIF_STATUS_BIT_WEL 0x2 // Write Enable Latch #define OSPIF_NO_QUAD_ENABLE (-1) -// Configuration Register2 address -#define OSPIF_CR2_OPI_EN_ADDR 0x00000000 - /* SFDP Header Parsing */ /***********************/ #define OSPIF_RSFDP_DUMMY_CYCLES 8 @@ -168,6 +162,21 @@ using namespace mbed; // Length of data returned from RDID instruction #define OSPI_RDID_DATA_LENGTH 3 +#ifdef NEED_DEFINE_SFDP_PARA +static const uint8_t _sfdp_head_table[32] = {0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x02, 0xFF, 0x00, 0x06, 0x01, + 0x10, 0x30, 0x00, 0x00, 0xFF, 0xC2, 0x00, 0x01, 0x04, 0x10, 0x01, + 0x00, 0xFF, 0x84, 0x00, 0x01, 0x02, 0xC0, 0x00, 0x00, 0xFF + }; +static const uint8_t _sfdp_basic_param_table[64] = {0x30, 0xFF, 0xFB, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x14, 0xEC, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0C, 0x20, + 0x10, 0xDC, 0x00, 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0x81, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0x50, 0xF9, 0x80 + }; +static const uint8_t _sfdp_4_byte_inst_table[8] = {0x7F, 0xEF, 0xFF, 0xFF, 0x21, 0x5C, 0xDC, 0x14}; +#endif /* Init function to initialize Different Devices CS static list */ static PinName *generate_initialized_active_ospif_csel_arr(); @@ -232,6 +241,11 @@ OSPIFBlockDevice::OSPIFBlockDevice(PinName io0, PinName io1, PinName io2, PinNam _attempt_4_byte_addressing = true; _4byte_msb_reg_write_inst = OSPIF_INST_4BYTE_REG_WRITE_DEFAULT; _support_4_byte_inst = false; + +#ifdef MX_FLASH_SUPPORT_RWW + _wait_flag = NOT_STARTED; + _busy_bank = 0xffffffff; +#endif } int OSPIFBlockDevice::init() @@ -358,6 +372,14 @@ int OSPIFBlockDevice::deinit() return result; } + if (false == _is_mem_ready()) { + tr_error("Device not ready after write, failed"); + } + +#ifdef MX_FLASH_SUPPORT_RWW + _wait_flag = NOT_STARTED; +#endif + change_mode(SPI); // Disable Device for Writing @@ -383,6 +405,29 @@ int OSPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size) int status = OSPIF_BD_ERROR_OK; tr_debug("Read Inst: 0x%xh", _read_instruction); +#ifdef MX_FLASH_SUPPORT_RWW + bool need_wait; + need_wait = (_wait_flag != NOT_STARTED) && ((addr & MX_FLASH_BANK_SIZE_MASK) == _busy_bank); + + // Wait for ready + if (need_wait) { + + _busy_mutex.lock(); + + if (_is_mem_ready_rww(addr, false) == false) { + return OSPIF_BD_ERROR_OK; + } + + } else { + if (_wait_flag == WRITE_WAIT_STARTED) { + tr_debug("\r\n RWW1 CNT"); + } else if (_wait_flag == ERASE_WAIT_STARTED) { + tr_debug("\r\n RWE2 CNT"); + } + } + +#endif + _mutex.lock(); // In DOPI mode, the number of read data should be even @@ -397,8 +442,13 @@ int OSPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size) _mutex.unlock(); - return status; +#ifdef MX_FLASH_SUPPORT_RWW + if (need_wait) { + _busy_mutex.unlock(); + } +#endif + return status; } int OSPIFBlockDevice::program(const void *buffer, bd_addr_t addr, bd_size_t size) @@ -418,6 +468,16 @@ int OSPIFBlockDevice::program(const void *buffer, bd_addr_t addr, bd_size_t size chunk = (offset + size < _page_size_bytes) ? size : (_page_size_bytes - offset); written_bytes = chunk; +#ifdef MX_FLASH_SUPPORT_RWW + _busy_mutex.lock(); + + // Wait for ready + if (_is_mem_ready_rww(addr, true) == false) { + return OSPIF_BD_ERROR_OK; + } + +#endif + _mutex.lock(); //Send WREN @@ -437,10 +497,14 @@ int OSPIFBlockDevice::program(const void *buffer, bd_addr_t addr, bd_size_t size goto exit_point; } - buffer = static_cast(buffer) + chunk; - addr += chunk; - size -= chunk; +#ifdef MX_FLASH_SUPPORT_RWW + _wait_flag = WRITE_WAIT_STARTED; + _busy_bank = addr & MX_FLASH_BANK_SIZE_MASK; + _mutex.unlock(); + + _busy_mutex.unlock(); +#else if (false == _is_mem_ready()) { tr_error("Device not ready after write, failed"); program_failed = true; @@ -448,6 +512,10 @@ int OSPIFBlockDevice::program(const void *buffer, bd_addr_t addr, bd_size_t size goto exit_point; } _mutex.unlock(); +#endif + buffer = static_cast(buffer) + chunk; + addr += chunk; + size -= chunk; } exit_point: @@ -511,6 +579,15 @@ int OSPIFBlockDevice::erase(bd_addr_t addr, bd_size_t size) tr_debug("Erase - Region: %d, Type:%d ", region, type); +#ifdef MX_FLASH_SUPPORT_RWW + _busy_mutex.lock(); + + // Wait for ready + if (_is_mem_ready_rww(addr, true) == false) { + return OSPIF_BD_ERROR_OK; + } +#endif + _mutex.lock(); if (_set_write_enable() != 0) { @@ -527,15 +604,14 @@ int OSPIFBlockDevice::erase(bd_addr_t addr, bd_size_t size) goto exit_point; } - addr += eu_size; - size -= eu_size; +#ifdef MX_FLASH_SUPPORT_RWW + _wait_flag = ERASE_WAIT_STARTED; + _busy_bank = addr & MX_FLASH_BANK_SIZE_MASK; - if ((size > 0) && (addr > _sfdp_info.smptbl.region_high_boundary[region])) { - // erase crossed to next region - region++; - bitfield = _sfdp_info.smptbl.region_erase_types_bitfld[region]; - } + _mutex.unlock(); + _busy_mutex.unlock(); +#else if (false == _is_mem_ready()) { tr_error("OSPI After Erase Device not ready - failed"); erase_failed = true; @@ -544,6 +620,16 @@ int OSPIFBlockDevice::erase(bd_addr_t addr, bd_size_t size) } _mutex.unlock(); +#endif + + addr += eu_size; + size -= eu_size; + + if ((size > 0) && (addr > _sfdp_info.smptbl.region_high_boundary[region])) { + // erase crossed to next region + region++; + bitfield = _sfdp_info.smptbl.region_erase_types_bitfld[region]; + } } exit_point: @@ -1537,6 +1623,51 @@ bool OSPIFBlockDevice::_is_mem_ready() return mem_ready; } +#ifdef MX_FLASH_SUPPORT_RWW +bool OSPIFBlockDevice::_is_mem_ready_rww(bd_addr_t addr, uint8_t rw) +{ + uint16_t cr2_value = 0; + bool mem_ready = true; + static uint32_t rww_cnt = 0; // For testing + static uint32_t rwe_cnt = 0; // For testing + + bd_addr_t bank_addr = addr & MX_FLASH_BANK_SIZE_MASK; + + if ((_wait_flag == NOT_STARTED) || (!rw && bank_addr != _busy_bank)) { + return mem_ready; + } + //Read CR2 Register 1 from device, the number of read byte need to be even in octa flash DOPI mode + if (OSPI_STATUS_OK != _ospi_send_general_command(OSPIF_INST_RDCR2, bank_addr + OSPIF_CR2_BANK_STATUS_ADDR, + NULL, 0, + (char *) &cr2_value, OSPI_DEFAULT_STATUS_REGISTERS)) { // store received value in cr2_value + tr_error("Reading CR2 Register failed"); + } + + cr2_value &= OSPIF_CR2_RWWBS; + + if ((cr2_value == OSPIF_CR2_RWWBS) || (rw && (cr2_value == OSPIF_CR2_RWWDS))) { + + // Wait until device ready + if (false == _is_mem_ready()) { + tr_error(" _is_mem_ready Failed"); + mem_ready = false; + } + _wait_flag = NOT_STARTED; + } else if (!rw && (cr2_value == OSPIF_CR2_RWWDS)) { + // For testing + if (_wait_flag == WRITE_WAIT_STARTED) { + rww_cnt++; + tr_debug("rww_cnt = 0x%x ", rww_cnt); + } else { + rwe_cnt++; + tr_debug("rwe_cnt = 0x%x ", rwe_cnt); + } + } + + return mem_ready; +} +#endif + /***************************************************/ /*********** OSPI Driver API Functions *************/ /***************************************************/ @@ -1665,9 +1796,12 @@ ospi_status_t OSPIFBlockDevice::_ospi_send_general_command(ospi_inst_t instructi if ((_inst_width == OSPI_CFG_BUS_OCTA) || (_inst_width == OSPI_CFG_BUS_OCTA_DTR)) { if ((instruction == OSPIF_INST_RSR1) || (instruction == OSPIF_INST_RDID) || (instruction == OSPIF_INST_RDCR2) || (instruction == OSPIF_INST_RDCR)) { - _ospi.configure_format(_inst_width, _inst_size, _address_width, _address_size, OSPI_CFG_BUS_SINGLE, 0, _data_width, _dummy_cycles); - addr = 0; - } else if (instruction == OSPIF_INST_WSR1) { + _ospi.configure_format(_inst_width, _inst_size, _address_width, _address_size, OSPI_CFG_BUS_SINGLE, + 0, _data_width, _dummy_cycles); + if (instruction != OSPIF_INST_RDCR2) { + addr = 0; + } + } else if ((instruction == OSPIF_INST_WSR1)) { addr = 0; } } diff --git a/storage/blockdevice/tests/TESTS/blockdevice/general_block_device/main.cpp b/storage/blockdevice/tests/TESTS/blockdevice/general_block_device/main.cpp index ff6bd9e1f8..dd1063d219 100644 --- a/storage/blockdevice/tests/TESTS/blockdevice/general_block_device/main.cpp +++ b/storage/blockdevice/tests/TESTS/blockdevice/general_block_device/main.cpp @@ -433,6 +433,89 @@ void test_multi_threads() } #endif +#if defined(MX_FLASH_SUPPORT_RWW) +void test_rww_rwe() +{ + utest_printf("\nTest rww and rwe Starts..\n"); + + TEST_SKIP_UNLESS_MESSAGE(block_device != NULL, "no block device found."); + + utest_printf("\ntest read bank1 data when write bank0\n"); + + // Determine start_address in bank 0 + bd_addr_t start_address_B0 = sectors_addr[rand() % num_of_sectors]; + utest_printf("start_address_B0=0x%016" PRIx64 "\n", start_address_B0); + + // Determine start_address in bank 1 + bd_addr_t start_address_B1 = start_address_B0 | 0x1000000; + utest_printf("start_address_B1=0x%016" PRIx64 "\n", start_address_B1); + + // Determine data_buf_size + bd_size_t erase_size = block_device->get_erase_size(start_address_B0); + TEST_ASSERT(erase_size > 0); + bd_size_t data_buf_size = block_device->get_program_size();; + + // Allocate buffer for write test data + uint8_t *data_buf = new (std::nothrow) uint8_t[data_buf_size]; + TEST_SKIP_UNLESS_MESSAGE(data_buf != NULL, "Not enough memory for test"); + + // Allocate buffer for read test data + uint8_t *out_data_buf = new (std::nothrow) uint8_t[data_buf_size]; + TEST_SKIP_UNLESS_MESSAGE(out_data_buf != NULL, "Not enough memory for test"); + + // First must Erase given memory region + utest_printf("erasing given memory region in bank0\n"); + int err = block_device->erase(start_address_B0, erase_size); + TEST_ASSERT_EQUAL(0, err); + utest_printf("erasing given memory region in bank1\n"); + err = block_device->erase(start_address_B1, erase_size); + TEST_ASSERT_EQUAL(0, err); + + // Write random data to selected region to make sure data is not accidentally set to "erased" value. + // With this pre-write, the test case will fail even if block_device->erase() is broken. + for (bd_size_t i = 0; i < data_buf_size; i++) { + data_buf[i] = (uint8_t) rand(); + } + + utest_printf("writing given memory region in bank1\n"); + err = block_device->program((const void *)data_buf, start_address_B1, data_buf_size); + TEST_ASSERT_EQUAL(0, err); + + memset(out_data_buf, 0, data_buf_size); + + utest_printf("writing given memory region in bank0\n"); + err = block_device->program((const void *)data_buf, start_address_B0, data_buf_size); + TEST_ASSERT_EQUAL(0, err); + + // Read written memory region in bank1 to verify it contains information +// utest_printf("reading written memory region in bank1 when write bank0\n"); + err = block_device->read((void *)out_data_buf, start_address_B1, data_buf_size); + TEST_ASSERT_EQUAL(0, err); + + // Verify erased memory region + utest_printf("verifying written memory region\n"); + for (bd_size_t i = 0; i < data_buf_size; i++) { + TEST_ASSERT_EQUAL(out_data_buf[i], data_buf[i]); + } + + utest_printf("\ntest read bank1 data when erase bank0\n"); + + utest_printf("erasing given memory region in bank0\n"); + memset(out_data_buf, 0, data_buf_size); + err = block_device->erase(start_address_B0, erase_size); + TEST_ASSERT_EQUAL(0, err); + + // Read written memory region in bank1 to verify it contains information + + utest_printf("reading written memory region in bank1 when erase bank0\n"); + err = block_device->read((void *)out_data_buf, start_address_B1, data_buf_size); + TEST_ASSERT_EQUAL(0, err); + + delete[] out_data_buf; + delete[] data_buf; +} +#endif + void test_erase_functionality() { utest_printf("\nTest BlockDevice::get_erase_value()..\n"); @@ -816,6 +899,9 @@ template_case_t template_cases[] = { {"Testing BlockDevice erase functionality", test_erase_functionality, greentea_failure_handler}, {"Testing program read small data sizes", test_program_read_small_data_sizes, greentea_failure_handler}, {"Testing unaligned erase blocks", test_unaligned_erase_blocks, greentea_failure_handler}, +#if defined(MX_FLASH_SUPPORT_RWW) + {"Testing read while write and read while erase", test_rww_rwe, greentea_failure_handler}, +#endif {"Testing Deinit block device", test_deinit_bd, greentea_failure_handler}, }; diff --git a/storage/blockdevice/tests/UNITTESTS/CMakeLists.txt b/storage/blockdevice/tests/UNITTESTS/CMakeLists.txt new file mode 100644 index 0000000000..c4980cb0db --- /dev/null +++ b/storage/blockdevice/tests/UNITTESTS/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(blockdevice) +add_subdirectory(SFDP) diff --git a/storage/blockdevice/tests/UNITTESTS/SFDP/CMakeLists.txt b/storage/blockdevice/tests/UNITTESTS/SFDP/CMakeLists.txt new file mode 100644 index 0000000000..a2bbd95796 --- /dev/null +++ b/storage/blockdevice/tests/UNITTESTS/SFDP/CMakeLists.txt @@ -0,0 +1,28 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME sfdp-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + DEVICE_SPI +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/SFDP.cpp + test_sfdp.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "storage") diff --git a/storage/blockdevice/tests/UNITTESTS/SFDP/unittest.cmake b/storage/blockdevice/tests/UNITTESTS/SFDP/unittest.cmake deleted file mode 100644 index 479a36fc05..0000000000 --- a/storage/blockdevice/tests/UNITTESTS/SFDP/unittest.cmake +++ /dev/null @@ -1,20 +0,0 @@ - -#################### -# UNIT TESTS -#################### -set(TEST_SUITE_NAME "SFDP") - -# Source files -set(unittest-sources - ../storage/blockdevice/source/SFDP.cpp -) - -# Test files -set(unittest-test-sources - ../storage/blockdevice/tests/UNITTESTS/SFDP/test_sfdp.cpp - stubs/mbed_assert_stub.cpp -) - -set(unittest-test-flags - -DDEVICE_SPI -) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/BufferedBlockDevice/CMakeLists.txt b/storage/blockdevice/tests/UNITTESTS/blockdevice/BufferedBlockDevice/CMakeLists.txt new file mode 100644 index 0000000000..4fdbe0e969 --- /dev/null +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/BufferedBlockDevice/CMakeLists.txt @@ -0,0 +1,24 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME buffered-blockdevice-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/BufferedBlockDevice.cpp + test_BufferedBlockDevice.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "storage") diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/BufferedBlockDevice/test_BufferedBlockDevice.cpp b/storage/blockdevice/tests/UNITTESTS/blockdevice/BufferedBlockDevice/test_BufferedBlockDevice.cpp index 8b4caa55f1..91658839b2 100644 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/BufferedBlockDevice/test_BufferedBlockDevice.cpp +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/BufferedBlockDevice/test_BufferedBlockDevice.cpp @@ -16,7 +16,7 @@ #include "gtest/gtest.h" #include "blockdevice/BufferedBlockDevice.h" -#include "stubs/BlockDevice_mock.h" +#include "BlockDevice_mock.h" using ::testing::_; using ::testing::Return; diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/BufferedBlockDevice/unittest.cmake b/storage/blockdevice/tests/UNITTESTS/blockdevice/BufferedBlockDevice/unittest.cmake deleted file mode 100644 index 96569edeae..0000000000 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/BufferedBlockDevice/unittest.cmake +++ /dev/null @@ -1,19 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-includes ${unittest-includes} - . - .. -) - -set(unittest-sources - ../storage/blockdevice/source/BufferedBlockDevice.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_assert_stub.cpp -) -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_BufferedBlockDevice.cpp - stubs/BlockDevice_mock.h -) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/CMakeLists.txt b/storage/blockdevice/tests/UNITTESTS/blockdevice/CMakeLists.txt new file mode 100644 index 0000000000..ec2780a7b5 --- /dev/null +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/CMakeLists.txt @@ -0,0 +1,13 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(ChainingBlockDevice) +add_subdirectory(BufferedBlockDevice) +add_subdirectory(SlicingBlockDevice) +add_subdirectory(ReadOnlyBlockDevice) +add_subdirectory(ProfilingBlockDevice) +add_subdirectory(ObservingBlockDevice) +add_subdirectory(MBRBlockDevice) +add_subdirectory(HeapBlockDevice) +add_subdirectory(FlashSimBlockDevice) +add_subdirectory(ExhaustibleBlockDevice) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ChainingBlockDevice/CMakeLists.txt b/storage/blockdevice/tests/UNITTESTS/blockdevice/ChainingBlockDevice/CMakeLists.txt new file mode 100644 index 0000000000..f80de82a18 --- /dev/null +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/ChainingBlockDevice/CMakeLists.txt @@ -0,0 +1,25 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME chaining-blockdevice-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/ChainingBlockDevice.cpp + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/HeapBlockDevice.cpp + test_ChainingBlockDevice.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "storage") diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ChainingBlockDevice/test_ChainingBlockDevice.cpp b/storage/blockdevice/tests/UNITTESTS/blockdevice/ChainingBlockDevice/test_ChainingBlockDevice.cpp index a566084c06..e7dfb09d33 100644 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/ChainingBlockDevice/test_ChainingBlockDevice.cpp +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/ChainingBlockDevice/test_ChainingBlockDevice.cpp @@ -15,8 +15,8 @@ */ #include "gtest/gtest.h" -#include "ChainingBlockDevice.cpp" -#include "stubs/BlockDevice_mock.h" +#include "blockdevice/ChainingBlockDevice.h" +#include "BlockDevice_mock.h" using ::testing::_; using ::testing::Return; @@ -96,7 +96,7 @@ TEST_F(ChainingBlockModuleTest, init) EXPECT_EQ(b.read(buf, 0, BLOCK_SIZE), BD_ERROR_DEVICE_ERROR); // EXPECT_EQ(b.deinit(), BD_ERROR_OK); EXPECT_EQ(b.sync(), BD_ERROR_DEVICE_ERROR); - EXPECT_EQ(b.get_type(), "CHAINING"); + EXPECT_STREQ(b.get_type(), "CHAINING"); EXPECT_CALL(bd_mock1, init()); EXPECT_CALL(bd_mock1, size()).WillOnce(Return((SECTORS_NUM / 2)*BLOCK_SIZE)); diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ChainingBlockDevice/unittest.cmake b/storage/blockdevice/tests/UNITTESTS/blockdevice/ChainingBlockDevice/unittest.cmake deleted file mode 100644 index cf954f3aa9..0000000000 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/ChainingBlockDevice/unittest.cmake +++ /dev/null @@ -1,21 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-includes ${unittest-includes} - . - .. - ../storage/blockdevice/source -) - -set(unittest-sources - ../storage/blockdevice/source/ChainingBlockDevice.cpp - ../storage/blockdevice/source/HeapBlockDevice.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_assert_stub.cpp -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_ChainingBlockDevice.cpp -) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ExhaustibleBlockDevice/CMakeLists.txt b/storage/blockdevice/tests/UNITTESTS/blockdevice/ExhaustibleBlockDevice/CMakeLists.txt new file mode 100644 index 0000000000..80c47486be --- /dev/null +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/ExhaustibleBlockDevice/CMakeLists.txt @@ -0,0 +1,24 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME exhaustible-blockdevice-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/ExhaustibleBlockDevice.cpp + test_ExhaustibleBlockDevice.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "storage") diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ExhaustibleBlockDevice/test_ExhaustibleBlockDevice.cpp b/storage/blockdevice/tests/UNITTESTS/blockdevice/ExhaustibleBlockDevice/test_ExhaustibleBlockDevice.cpp index a1625c125e..be8999a7a9 100644 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/ExhaustibleBlockDevice/test_ExhaustibleBlockDevice.cpp +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/ExhaustibleBlockDevice/test_ExhaustibleBlockDevice.cpp @@ -16,7 +16,7 @@ #include "gtest/gtest.h" #include "blockdevice/ExhaustibleBlockDevice.h" -#include "stubs/BlockDevice_mock.h" +#include "BlockDevice_mock.h" #define BLOCK_SIZE (512) #define DEVICE_SIZE (BLOCK_SIZE*10) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ExhaustibleBlockDevice/unittest.cmake b/storage/blockdevice/tests/UNITTESTS/blockdevice/ExhaustibleBlockDevice/unittest.cmake deleted file mode 100644 index efc460bdb3..0000000000 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/ExhaustibleBlockDevice/unittest.cmake +++ /dev/null @@ -1,19 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-includes ${unittest-includes} - . - .. -) - -set(unittest-sources - ../storage/blockdevice/source/ExhaustibleBlockDevice.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_assert_stub.cpp -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_ExhaustibleBlockDevice.cpp -) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/FlashSimBlockDevice/CMakeLists.txt b/storage/blockdevice/tests/UNITTESTS/blockdevice/FlashSimBlockDevice/CMakeLists.txt new file mode 100644 index 0000000000..99e4a37809 --- /dev/null +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/FlashSimBlockDevice/CMakeLists.txt @@ -0,0 +1,24 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME flash-sim-blockdevice-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/FlashSimBlockDevice.cpp + test_FlashSimBlockDevice.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "storage") diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/FlashSimBlockDevice/test_FlashSimBlockDevice.cpp b/storage/blockdevice/tests/UNITTESTS/blockdevice/FlashSimBlockDevice/test_FlashSimBlockDevice.cpp index be0e797dba..d9ce67d7ec 100644 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/FlashSimBlockDevice/test_FlashSimBlockDevice.cpp +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/FlashSimBlockDevice/test_FlashSimBlockDevice.cpp @@ -16,7 +16,7 @@ #include "gtest/gtest.h" #include "blockdevice/FlashSimBlockDevice.h" -#include "stubs/BlockDevice_mock.h" +#include "BlockDevice_mock.h" #define BLOCK_SIZE (512) #define DEVICE_SIZE (BLOCK_SIZE*10) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/FlashSimBlockDevice/unittest.cmake b/storage/blockdevice/tests/UNITTESTS/blockdevice/FlashSimBlockDevice/unittest.cmake deleted file mode 100644 index afbd9f69fe..0000000000 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/FlashSimBlockDevice/unittest.cmake +++ /dev/null @@ -1,19 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-includes ${unittest-includes} - . - .. -) - -set(unittest-sources - ../storage/blockdevice/source/FlashSimBlockDevice.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_assert_stub.cpp -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_FlashSimBlockDevice.cpp -) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/HeapBlockDevice/CMakeLists.txt b/storage/blockdevice/tests/UNITTESTS/blockdevice/HeapBlockDevice/CMakeLists.txt new file mode 100644 index 0000000000..e2bbd7323d --- /dev/null +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/HeapBlockDevice/CMakeLists.txt @@ -0,0 +1,67 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME heap-blockdevice-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + MBED_CONF_FAT_CHAN_FFS_DBG=0 + MBED_CONF_FAT_CHAN_FF_FS_READONLY=0 + MBED_CONF_FAT_CHAN_FF_FS_MINIMIZE=0 + MBED_CONF_FAT_CHAN_FF_USE_STRFUNC=0 + MBED_CONF_FAT_CHAN_FF_USE_FIND=0 + MBED_CONF_FAT_CHAN_FF_USE_MKFS=1 + MBED_CONF_FAT_CHAN_FF_USE_FASTSEEK=0 + MBED_CONF_FAT_CHAN_FF_USE_EXPAND=0 + MBED_CONF_FAT_CHAN_FF_USE_CHMOD=0 + MBED_CONF_FAT_CHAN_FF_USE_LABEL=0 + MBED_CONF_FAT_CHAN_FF_USE_FORWARD=0 + MBED_CONF_FAT_CHAN_FF_CODE_PAGE=437 + MBED_CONF_FAT_CHAN_FF_USE_LFN=3 + MBED_CONF_FAT_CHAN_FF_MAX_LFN=255 + MBED_CONF_FAT_CHAN_FF_LFN_UNICODE=0 + MBED_CONF_FAT_CHAN_FF_LFN_BUF=255 + MBED_CONF_FAT_CHAN_FF_SFN_BUF=12 + MBED_CONF_FAT_CHAN_FF_STRF_ENCODE=3 + MBED_CONF_FAT_CHAN_FF_FS_RPATH=1 + MBED_CONF_FAT_CHAN_FF_VOLUMES=4 + MBED_CONF_FAT_CHAN_FF_STR_VOLUME_ID=0 + MBED_CONF_FAT_CHAN_FF_VOLUME_STRS=\"RAM\",\"NAND\",\"CF\",\"SD\",\"SD2\",\"USB\",\"USB2\",\"USB3\" + MBED_CONF_FAT_CHAN_FF_MULTI_PARTITION=0 + MBED_CONF_FAT_CHAN_FF_MIN_SS=512 + MBED_CONF_FAT_CHAN_FF_MAX_SS=4096 + MBED_CONF_FAT_CHAN_FF_USE_TRIM=1 + MBED_CONF_FAT_CHAN_FF_FS_NOFSINFO=0 + MBED_CONF_FAT_CHAN_FF_FS_TINY=1 + MBED_CONF_FAT_CHAN_FF_FS_EXFAT=0 + MBED_CONF_FAT_CHAN_FF_FS_HEAPBUF=1 + MBED_CONF_FAT_CHAN_FF_FS_NORTC=0 + MBED_CONF_FAT_CHAN_FF_NORTC_MON=1 + MBED_CONF_FAT_CHAN_FF_NORTC_MDAY=1 + MBED_CONF_FAT_CHAN_FF_NORTC_YEAR=2017 + MBED_CONF_FAT_CHAN_FF_FS_LOCK=0 + MBED_CONF_FAT_CHAN_FF_FS_REENTRANT=0 + MBED_CONF_FAT_CHAN_FF_FS_TIMEOUT=1000 + MBED_CONF_FAT_CHAN_FF_SYNC_t=HANDLE + MBED_CONF_FAT_CHAN_FLUSH_ON_NEW_CLUSTER=0 + MBED_CONF_FAT_CHAN_FLUSH_ON_NEW_SECTOR=1 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/HeapBlockDevice.cpp + test.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "storage") diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/HeapBlockDevice/unittest.cmake b/storage/blockdevice/tests/UNITTESTS/blockdevice/HeapBlockDevice/unittest.cmake deleted file mode 100644 index 48be0ec9bd..0000000000 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/HeapBlockDevice/unittest.cmake +++ /dev/null @@ -1,63 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-includes ${unittest-includes} - . - .. - ../storage/blockdevice/include -) - -set(unittest-sources - ../storage/blockdevice/source/HeapBlockDevice.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_assert_stub.cpp -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test.cpp -) - -set(unittest-test-flags - -DMBED_CONF_FAT_CHAN_FFS_DBG=0 - -DMBED_CONF_FAT_CHAN_FF_FS_READONLY=0 - -DMBED_CONF_FAT_CHAN_FF_FS_MINIMIZE=0 - -DMBED_CONF_FAT_CHAN_FF_USE_STRFUNC=0 - -DMBED_CONF_FAT_CHAN_FF_USE_FIND=0 - -DMBED_CONF_FAT_CHAN_FF_USE_MKFS=1 - -DMBED_CONF_FAT_CHAN_FF_USE_FASTSEEK=0 - -DMBED_CONF_FAT_CHAN_FF_USE_EXPAND=0 - -DMBED_CONF_FAT_CHAN_FF_USE_CHMOD=0 - -DMBED_CONF_FAT_CHAN_FF_USE_LABEL=0 - -DMBED_CONF_FAT_CHAN_FF_USE_FORWARD=0 - -DMBED_CONF_FAT_CHAN_FF_CODE_PAGE=437 - -DMBED_CONF_FAT_CHAN_FF_USE_LFN=3 - -DMBED_CONF_FAT_CHAN_FF_MAX_LFN=255 - -DMBED_CONF_FAT_CHAN_FF_LFN_UNICODE=0 - -DMBED_CONF_FAT_CHAN_FF_LFN_BUF=255 - -DMBED_CONF_FAT_CHAN_FF_SFN_BUF=12 - -DMBED_CONF_FAT_CHAN_FF_STRF_ENCODE=3 - -DMBED_CONF_FAT_CHAN_FF_FS_RPATH=1 - -DMBED_CONF_FAT_CHAN_FF_VOLUMES=4 - -DMBED_CONF_FAT_CHAN_FF_STR_VOLUME_ID=0 - -DMBED_CONF_FAT_CHAN_FF_VOLUME_STRS=\"RAM\",\"NAND\",\"CF\",\"SD\",\"SD2\",\"USB\",\"USB2\",\"USB3\" - -DMBED_CONF_FAT_CHAN_FF_MULTI_PARTITION=0 - -DMBED_CONF_FAT_CHAN_FF_MIN_SS=512 - -DMBED_CONF_FAT_CHAN_FF_MAX_SS=4096 - -DMBED_CONF_FAT_CHAN_FF_USE_TRIM=1 - -DMBED_CONF_FAT_CHAN_FF_FS_NOFSINFO=0 - -DMBED_CONF_FAT_CHAN_FF_FS_TINY=1 - -DMBED_CONF_FAT_CHAN_FF_FS_EXFAT=0 - -DMBED_CONF_FAT_CHAN_FF_FS_HEAPBUF=1 - -DMBED_CONF_FAT_CHAN_FF_FS_NORTC=0 - -DMBED_CONF_FAT_CHAN_FF_NORTC_MON=1 - -DMBED_CONF_FAT_CHAN_FF_NORTC_MDAY=1 - -DMBED_CONF_FAT_CHAN_FF_NORTC_YEAR=2017 - -DMBED_CONF_FAT_CHAN_FF_FS_LOCK=0 - -DMBED_CONF_FAT_CHAN_FF_FS_REENTRANT=0 - -DMBED_CONF_FAT_CHAN_FF_FS_TIMEOUT=1000 - -DMBED_CONF_FAT_CHAN_FF_SYNC_t=HANDLE - -DMBED_CONF_FAT_CHAN_FLUSH_ON_NEW_CLUSTER=0 - -DMBED_CONF_FAT_CHAN_FLUSH_ON_NEW_SECTOR=1 -) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/MBRBlockDevice/CMakeLists.txt b/storage/blockdevice/tests/UNITTESTS/blockdevice/MBRBlockDevice/CMakeLists.txt new file mode 100644 index 0000000000..6a0fa5f8fa --- /dev/null +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/MBRBlockDevice/CMakeLists.txt @@ -0,0 +1,24 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME mbr-blockdevice-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/MBRBlockDevice.cpp + test_MBRBlockDevice.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "storage") diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/MBRBlockDevice/test_MBRBlockDevice.cpp b/storage/blockdevice/tests/UNITTESTS/blockdevice/MBRBlockDevice/test_MBRBlockDevice.cpp index 663bb24990..c066aa127c 100644 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/MBRBlockDevice/test_MBRBlockDevice.cpp +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/MBRBlockDevice/test_MBRBlockDevice.cpp @@ -16,7 +16,7 @@ #include "gtest/gtest.h" #include "blockdevice/MBRBlockDevice.h" -#include "stubs/BlockDevice_mock.h" +#include "BlockDevice_mock.h" #define BLOCK_SIZE (512) #define PART_DESC_SIZE (16) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/MBRBlockDevice/unittest.cmake b/storage/blockdevice/tests/UNITTESTS/blockdevice/MBRBlockDevice/unittest.cmake deleted file mode 100644 index 6368772180..0000000000 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/MBRBlockDevice/unittest.cmake +++ /dev/null @@ -1,19 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-includes ${unittest-includes} - . - .. -) - -set(unittest-sources - ../storage/blockdevice/source/MBRBlockDevice.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_assert_stub.cpp -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_MBRBlockDevice.cpp -) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ObservingBlockDevice/CMakeLists.txt b/storage/blockdevice/tests/UNITTESTS/blockdevice/ObservingBlockDevice/CMakeLists.txt new file mode 100644 index 0000000000..ab71b4e3f2 --- /dev/null +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/ObservingBlockDevice/CMakeLists.txt @@ -0,0 +1,25 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME observing-blockdevice-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/ObservingBlockDevice.cpp + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/ReadOnlyBlockDevice.cpp + test_ObservingBlockDevice.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "storage") diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ObservingBlockDevice/test_ObservingBlockDevice.cpp b/storage/blockdevice/tests/UNITTESTS/blockdevice/ObservingBlockDevice/test_ObservingBlockDevice.cpp index 860c808302..43dff8cf8a 100644 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/ObservingBlockDevice/test_ObservingBlockDevice.cpp +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/ObservingBlockDevice/test_ObservingBlockDevice.cpp @@ -17,7 +17,7 @@ #include "gtest/gtest.h" #include "blockdevice/ObservingBlockDevice.h" #include "blockdevice/ReadOnlyBlockDevice.h" -#include "stubs/BlockDevice_mock.h" +#include "BlockDevice_mock.h" using ::testing::_; using ::testing::Return; diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ObservingBlockDevice/unittest.cmake b/storage/blockdevice/tests/UNITTESTS/blockdevice/ObservingBlockDevice/unittest.cmake deleted file mode 100644 index 16376589a7..0000000000 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/ObservingBlockDevice/unittest.cmake +++ /dev/null @@ -1,22 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-includes ${unittest-includes} - . - .. -) - -set(unittest-sources - ../storage/blockdevice/source/ObservingBlockDevice.cpp - ../storage/blockdevice/source/ReadOnlyBlockDevice.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_assert_stub.cpp - stubs/mbed_error.c -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_ObservingBlockDevice.cpp - stubs/BlockDevice_mock.h -) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ProfilingBlockDevice/CMakeLists.txt b/storage/blockdevice/tests/UNITTESTS/blockdevice/ProfilingBlockDevice/CMakeLists.txt new file mode 100644 index 0000000000..9d60f63dd3 --- /dev/null +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/ProfilingBlockDevice/CMakeLists.txt @@ -0,0 +1,25 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME profiling-blockdevice-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/ProfilingBlockDevice.cpp + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/HeapBlockDevice.cpp + test_ProfilingBlockDevice.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "storage") diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ProfilingBlockDevice/test_ProfilingBlockDevice.cpp b/storage/blockdevice/tests/UNITTESTS/blockdevice/ProfilingBlockDevice/test_ProfilingBlockDevice.cpp index 883e50277d..4a1010e0bb 100644 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/ProfilingBlockDevice/test_ProfilingBlockDevice.cpp +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/ProfilingBlockDevice/test_ProfilingBlockDevice.cpp @@ -15,7 +15,7 @@ */ #include "gtest/gtest.h" -#include "stubs/BlockDevice_mock.h" +#include "BlockDevice_mock.h" #include "blockdevice/ProfilingBlockDevice.h" #define BLOCK_SIZE (512) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ProfilingBlockDevice/unittest.cmake b/storage/blockdevice/tests/UNITTESTS/blockdevice/ProfilingBlockDevice/unittest.cmake deleted file mode 100644 index a17a4f5a99..0000000000 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/ProfilingBlockDevice/unittest.cmake +++ /dev/null @@ -1,21 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-includes ${unittest-includes} - . - .. -) - -set(unittest-sources - ../storage/blockdevice/source/ProfilingBlockDevice.cpp - ../storage/blockdevice/source/HeapBlockDevice.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_assert_stub.cpp -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_ProfilingBlockDevice.cpp - stubs/mbed_error.c -) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ReadOnlyBlockDevice/CMakeLists.txt b/storage/blockdevice/tests/UNITTESTS/blockdevice/ReadOnlyBlockDevice/CMakeLists.txt new file mode 100644 index 0000000000..a8314edbe1 --- /dev/null +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/ReadOnlyBlockDevice/CMakeLists.txt @@ -0,0 +1,25 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME read-only-blockdevice-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/ReadOnlyBlockDevice.cpp + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/HeapBlockDevice.cpp + test_ReadOnlyBlockDevice.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "storage") diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ReadOnlyBlockDevice/test_ReadOnlyBlockDevice.cpp b/storage/blockdevice/tests/UNITTESTS/blockdevice/ReadOnlyBlockDevice/test_ReadOnlyBlockDevice.cpp index 1cde364abb..1523a951e7 100644 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/ReadOnlyBlockDevice/test_ReadOnlyBlockDevice.cpp +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/ReadOnlyBlockDevice/test_ReadOnlyBlockDevice.cpp @@ -15,7 +15,7 @@ */ #include "gtest/gtest.h" -#include "stubs/BlockDevice_mock.h" +#include "BlockDevice_mock.h" #include "blockdevice/ReadOnlyBlockDevice.h" #include "platform/mbed_error.h" diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/ReadOnlyBlockDevice/unittest.cmake b/storage/blockdevice/tests/UNITTESTS/blockdevice/ReadOnlyBlockDevice/unittest.cmake deleted file mode 100644 index 90a9247f57..0000000000 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/ReadOnlyBlockDevice/unittest.cmake +++ /dev/null @@ -1,21 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-includes ${unittest-includes} - . - .. -) - -set(unittest-sources - ../storage/blockdevice/source/ReadOnlyBlockDevice.cpp - ../storage/blockdevice/source/HeapBlockDevice.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_assert_stub.cpp -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/test_ReadOnlyBlockDevice.cpp - stubs/mbed_error.c -) diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/SlicingBlockDevice/CMakeLists.txt b/storage/blockdevice/tests/UNITTESTS/blockdevice/SlicingBlockDevice/CMakeLists.txt new file mode 100644 index 0000000000..8d6e078392 --- /dev/null +++ b/storage/blockdevice/tests/UNITTESTS/blockdevice/SlicingBlockDevice/CMakeLists.txt @@ -0,0 +1,24 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME slicing-blockdevice-unittest) + +add_executable(${TEST_NAME}) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/SlicingBlockDevice.cpp + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/HeapBlockDevice.cpp + moduletest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "storage") diff --git a/storage/blockdevice/tests/UNITTESTS/blockdevice/SlicingBlockDevice/unittest.cmake b/storage/blockdevice/tests/UNITTESTS/blockdevice/SlicingBlockDevice/unittest.cmake deleted file mode 100644 index 268e9b6ff9..0000000000 --- a/storage/blockdevice/tests/UNITTESTS/blockdevice/SlicingBlockDevice/unittest.cmake +++ /dev/null @@ -1,20 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-includes ${unittest-includes} - . - .. -) - -set(unittest-sources - ../storage/blockdevice/source/SlicingBlockDevice.cpp - ../storage/blockdevice/source/HeapBlockDevice.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_assert_stub.cpp -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/moduletest.cpp -) diff --git a/storage/filesystem/littlefs/include/littlefs/LittleFileSystem.h b/storage/filesystem/littlefs/include/littlefs/LittleFileSystem.h index 5cf5e71f45..c1e3a3c299 100644 --- a/storage/filesystem/littlefs/include/littlefs/LittleFileSystem.h +++ b/storage/filesystem/littlefs/include/littlefs/LittleFileSystem.h @@ -24,7 +24,7 @@ #include "filesystem/FileSystem.h" #include "blockdevice/BlockDevice.h" #include "platform/PlatformMutex.h" -#include "storage/filesystem/littlefs/littlefs/lfs.h" +#include "littlefs/lfs.h" namespace mbed { diff --git a/storage/filesystem/littlefs/source/LittleFileSystem.cpp b/storage/filesystem/littlefs/source/LittleFileSystem.cpp index 5f76a04861..752fa99aa5 100644 --- a/storage/filesystem/littlefs/source/LittleFileSystem.cpp +++ b/storage/filesystem/littlefs/source/LittleFileSystem.cpp @@ -17,8 +17,8 @@ #include "filesystem/mbed_filesystem.h" #include "littlefs/LittleFileSystem.h" #include "errno.h" -#include "storage/filesystem/littlefs/littlefs/lfs.h" -#include "storage/filesystem/littlefs/littlefs/lfs_util.h" +#include "littlefs/lfs.h" +#include "littlefs/lfs_util.h" #include "MbedCRC.h" namespace mbed { diff --git a/storage/kvstore/filesystemstore/CMakeLists.txt b/storage/kvstore/filesystemstore/CMakeLists.txt index 116a5abf2a..7289fe8b8d 100644 --- a/storage/kvstore/filesystemstore/CMakeLists.txt +++ b/storage/kvstore/filesystemstore/CMakeLists.txt @@ -1,6 +1,10 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) + add_subdirectory(tests/UNITTESTS) +endif() + target_include_directories(mbed-storage-filesystemstore INTERFACE . diff --git a/storage/kvstore/filesystemstore/tests/UNITTESTS/CMakeLists.txt b/storage/kvstore/filesystemstore/tests/UNITTESTS/CMakeLists.txt new file mode 100644 index 0000000000..d1af4569d2 --- /dev/null +++ b/storage/kvstore/filesystemstore/tests/UNITTESTS/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(FileSystemStore) diff --git a/storage/kvstore/filesystemstore/tests/UNITTESTS/FileSystemStore/CMakeLists.txt b/storage/kvstore/filesystemstore/tests/UNITTESTS/FileSystemStore/CMakeLists.txt new file mode 100644 index 0000000000..bd120f19a5 --- /dev/null +++ b/storage/kvstore/filesystemstore/tests/UNITTESTS/FileSystemStore/CMakeLists.txt @@ -0,0 +1,43 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME filesystemstore-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + UNITTEST + MBED_LFS_READ_SIZE=64 + MBED_LFS_PROG_SIZE=64 + MBED_LFS_BLOCK_SIZE=512 + MBED_LFS_LOOKAHEAD=512 +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/HeapBlockDevice.cpp + ${mbed-os_SOURCE_DIR}/storage/kvstore/filesystemstore/source/FileSystemStore.cpp + ${mbed-os_SOURCE_DIR}/storage/filesystem/littlefs/source/LittleFileSystem.cpp + ${mbed-os_SOURCE_DIR}/storage/filesystem/source/Dir.cpp + ${mbed-os_SOURCE_DIR}/storage/filesystem/source/File.cpp + ${mbed-os_SOURCE_DIR}/storage/filesystem/source/FileSystem.cpp + ${mbed-os_SOURCE_DIR}/platform/mbed-trace/source/mbed_trace.c + ${mbed-os_SOURCE_DIR}/storage/filesystem/littlefs/littlefs/lfs.c + ${mbed-os_SOURCE_DIR}/platform/source/FileBase.cpp + ${mbed-os_SOURCE_DIR}/platform/source/FileSystemHandle.cpp + ${mbed-os_SOURCE_DIR}/platform/source/FileHandle.cpp + moduletest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-platform + mbed-stubs-storage + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "storage") diff --git a/storage/kvstore/filesystemstore/tests/UNITTESTS/FileSystemStore/unittest.cmake b/storage/kvstore/filesystemstore/tests/UNITTESTS/FileSystemStore/unittest.cmake deleted file mode 100644 index b12cabe869..0000000000 --- a/storage/kvstore/filesystemstore/tests/UNITTESTS/FileSystemStore/unittest.cmake +++ /dev/null @@ -1,40 +0,0 @@ -#################### -# UNIT TESTS -#################### - -set(unittest-includes ${unittest-includes} - . - .. - ../platform/mbed-trace/mbed-trace -) - -set(unittest-sources - ../storage/blockdevice/source/HeapBlockDevice.cpp - ../storage/kvstore/filesystemstore/source/FileSystemStore.cpp - ../storage/filesystem/littlefs/source/LittleFileSystem.cpp - ../storage/filesystem/source/Dir.cpp - ../storage/filesystem/source/File.cpp - ../storage/filesystem/source/FileSystem.cpp - ../platform/mbed-trace/source/mbed_trace.c - ../storage/filesystem/littlefs/littlefs/lfs_util.c - ../storage/filesystem/littlefs/littlefs/lfs.c - ../platform/source/FileBase.cpp - ../platform/source/FileSystemHandle.cpp - ../platform/source/FileHandle.cpp -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/moduletest.cpp - stubs/mbed_atomic_stub.c - stubs/mbed_assert_stub.cpp - stubs/mbed_error.c - stubs/kv_config_stub.cpp - stubs/mbed_retarget_stub.cpp -) - -set(unittest-test-flags - -DMBED_LFS_READ_SIZE=64 - -DMBED_LFS_PROG_SIZE=64 - -DMBED_LFS_BLOCK_SIZE=512 - -DMBED_LFS_LOOKAHEAD=512 -) diff --git a/storage/kvstore/tdbstore/CMakeLists.txt b/storage/kvstore/tdbstore/CMakeLists.txt index 38a992a488..d4f8d92ed5 100644 --- a/storage/kvstore/tdbstore/CMakeLists.txt +++ b/storage/kvstore/tdbstore/CMakeLists.txt @@ -1,6 +1,10 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +if(CMAKE_PROJECT_NAME STREQUAL PROJECT_NAME AND BUILD_TESTING) + add_subdirectory(tests/UNITTESTS) +endif() + target_include_directories(mbed-storage-tdbstore INTERFACE . diff --git a/storage/kvstore/tdbstore/tests/UNITTESTS/CMakeLists.txt b/storage/kvstore/tdbstore/tests/UNITTESTS/CMakeLists.txt new file mode 100644 index 0000000000..3c1fde3c16 --- /dev/null +++ b/storage/kvstore/tdbstore/tests/UNITTESTS/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(TDBStore) diff --git a/storage/kvstore/tdbstore/tests/UNITTESTS/TDBStore/CMakeLists.txt b/storage/kvstore/tdbstore/tests/UNITTESTS/TDBStore/CMakeLists.txt new file mode 100644 index 0000000000..1c1606c41b --- /dev/null +++ b/storage/kvstore/tdbstore/tests/UNITTESTS/TDBStore/CMakeLists.txt @@ -0,0 +1,30 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(TEST_NAME tdbstore-unittest) + +add_executable(${TEST_NAME}) + +target_compile_definitions(${TEST_NAME} + PRIVATE + UNITTEST +) + +target_sources(${TEST_NAME} + PRIVATE + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/HeapBlockDevice.cpp + ${mbed-os_SOURCE_DIR}/storage/blockdevice/source/BufferedBlockDevice.cpp + ${mbed-os_SOURCE_DIR}/storage/kvstore/tdbstore/source/TDBStore.cpp + moduletest.cpp +) + +target_link_libraries(${TEST_NAME} + PRIVATE + mbed-headers + mbed-stubs-platform + gmock_main +) + +add_test(NAME "${TEST_NAME}" COMMAND ${TEST_NAME}) + +set_tests_properties(${TEST_NAME} PROPERTIES LABELS "storage") diff --git a/storage/kvstore/tdbstore/tests/UNITTESTS/TDBStore/unittest.cmake b/storage/kvstore/tdbstore/tests/UNITTESTS/TDBStore/unittest.cmake deleted file mode 100644 index 5d1a3a5081..0000000000 --- a/storage/kvstore/tdbstore/tests/UNITTESTS/TDBStore/unittest.cmake +++ /dev/null @@ -1,26 +0,0 @@ - -#################### -# UNIT TESTS -#################### - -set(unittest-includes ${unittest-includes} - . - .. - ../platform/mbed-trace/mbed-trace -) - -set(unittest-sources - ../storage/blockdevice/source/HeapBlockDevice.cpp - ../storage/blockdevice/source/BufferedBlockDevice.cpp - ../storage/kvstore/tdbstore/source/TDBStore.cpp - ../platform/mbed-trace/source/mbed_trace.c - stubs/mbed_atomic_stub.c - stubs/mbed_assert_stub.cpp - stubs/mbed_error.c -) - -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/moduletest.cpp -) - -set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS}") diff --git a/targets/CMakeLists.txt b/targets/CMakeLists.txt index fce00d6fdb..36c9454e67 100644 --- a/targets/CMakeLists.txt +++ b/targets/CMakeLists.txt @@ -1,21 +1,23 @@ # Copyright (c) 2020-2021 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 -include(mbed_set_linker_script) - -add_subdirectory(TARGET_Ambiq_Micro EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_Analog_Devices EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_ARM_FM EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_ARM_SSG EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_Cypress EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_Freescale EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_GigaDevice EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_Maxim EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_NORDIC EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_NUVOTON EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_NXP EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_RENESAS EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_Samsung EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_Silicon_Labs EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_STM EXCLUDE_FROM_ALL) -add_subdirectory(TARGET_TOSHIBA EXCLUDE_FROM_ALL) +if(${CMAKE_CROSSCOMPILING}) + include(mbed_set_linker_script) + + add_subdirectory(TARGET_Ambiq_Micro EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_Analog_Devices EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_ARM_FM EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_ARM_SSG EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_Cypress EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_Freescale EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_GigaDevice EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_Maxim EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_NORDIC EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_NUVOTON EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_NXP EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_RENESAS EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_Samsung EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_Silicon_Labs EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_STM EXCLUDE_FROM_ALL) + add_subdirectory(TARGET_TOSHIBA EXCLUDE_FROM_ALL) +endif() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/CMakeLists.txt b/targets/TARGET_Cypress/TARGET_PSOC6/CMakeLists.txt index 7fe1b4c5f0..42d0566a8d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/CMakeLists.txt +++ b/targets/TARGET_Cypress/TARGET_PSOC6/CMakeLists.txt @@ -2,8 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 add_subdirectory(COMPONENT_SCL EXCLUDE_FROM_ALL) -add_subdirectory(COMPONENT_WHD EXCLUDE_FROM_ALL) -add_subdirectory(common/COMPONENT_WHD EXCLUDE_FROM_ALL) add_library(mbed-cat1a INTERFACE) diff --git a/targets/TARGET_Maxim/TARGET_MAX32620C/sleep.c b/targets/TARGET_Maxim/TARGET_MAX32620C/sleep.c index 7907bd0f94..28b48e3129 100644 --- a/targets/TARGET_Maxim/TARGET_MAX32620C/sleep.c +++ b/targets/TARGET_Maxim/TARGET_MAX32620C/sleep.c @@ -1,5 +1,5 @@ /******************************************************************************* - * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. + * Copyright (C) Maxim Integrated Products, Inc., All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,6 +33,7 @@ #include "sleep_api.h" #include "lp.h" +#include "clkman.h" void hal_sleep(void) { @@ -42,5 +43,7 @@ void hal_sleep(void) // Low-power stop mode void hal_deepsleep(void) { + MXC_CLKMAN->clk_gate_ctrl1 &= ~MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER; hal_sleep(); + MXC_CLKMAN->clk_gate_ctrl1 |= MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER; } diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_15_0/CMakeLists.txt b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_15_0/CMakeLists.txt index fb9303f57b..25d6aa1cb1 100644 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_15_0/CMakeLists.txt +++ b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_15_0/CMakeLists.txt @@ -3,9 +3,12 @@ add_library(mbed-sdk-15-0 INTERFACE) +# Silence unfixable warning in nrfx +target_compile_options(mbed-sdk-15-0 INTERFACE -Wno-expansion-to-defined) + add_subdirectory(TARGET_SOFTDEVICE_NONE EXCLUDE_FROM_ALL) add_subdirectory(components EXCLUDE_FROM_ALL) add_subdirectory(integration EXCLUDE_FROM_ALL) add_subdirectory(modules EXCLUDE_FROM_ALL) -target_link_libraries(mbed-sdk-15-0 INTERFACE mbed-softdevice-none) \ No newline at end of file +target_link_libraries(mbed-sdk-15-0 INTERFACE mbed-softdevice-none) diff --git a/targets/TARGET_NUVOTON/CMakeLists.txt b/targets/TARGET_NUVOTON/CMakeLists.txt index bc9a0bbaf3..2618b54fe5 100644 --- a/targets/TARGET_NUVOTON/CMakeLists.txt +++ b/targets/TARGET_NUVOTON/CMakeLists.txt @@ -9,6 +9,7 @@ add_subdirectory(TARGET_M451 EXCLUDE_FROM_ALL) add_subdirectory(TARGET_M480 EXCLUDE_FROM_ALL) add_subdirectory(TARGET_NANO100 EXCLUDE_FROM_ALL) add_subdirectory(TARGET_NUC472 EXCLUDE_FROM_ALL) +add_subdirectory(TARGET_M2354 EXCLUDE_FROM_ALL) target_include_directories(mbed-nuvoton INTERFACE diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/CMakeLists.txt b/targets/TARGET_NUVOTON/TARGET_M2354/CMakeLists.txt new file mode 100644 index 0000000000..0a6d86f22e --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/CMakeLists.txt @@ -0,0 +1,105 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") + set(LINKER_FILE device/TOOLCHAIN_GCC_ARM/M2354.ld) +elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") + set(LINKER_FILE device/TOOLCHAIN_ARMC6/M2354.sct) +endif() + +add_library(mbed-m2354 INTERFACE) + +target_sources(mbed-m2354 + INTERFACE + analogin_api.c + analogout_api.c + + device/startup_M2354.c + device/system_M2354.c + device/StdDriver/src/m2354_acmp.c + device/StdDriver/src/m2354_bpwm.c + device/StdDriver/src/m2354_can.c + device/StdDriver/src/m2354_clk.c + device/StdDriver/src/m2354_crc.c + device/StdDriver/src/m2354_crypto.c + device/StdDriver/src/m2354_dac.c + device/StdDriver/src/m2354_dpm.c + device/StdDriver/src/m2354_eadc.c + device/StdDriver/src/m2354_ebi.c + device/StdDriver/src/m2354_ecap.c + device/StdDriver/src/m2354_epwm.c + device/StdDriver/src/m2354_ewdt.c + device/StdDriver/src/m2354_ewwdt.c + device/StdDriver/src/m2354_fmc.c + device/StdDriver/src/m2354_fvc.c + device/StdDriver/src/m2354_gpio.c + device/StdDriver/src/m2354_i2c.c + device/StdDriver/src/m2354_i2s.c + device/StdDriver/src/m2354_keystore.c + device/StdDriver/src/m2354_lcd.c + device/StdDriver/src/m2354_pdma.c + device/StdDriver/src/m2354_qei.c + device/StdDriver/src/m2354_qspi.c + device/StdDriver/src/m2354_rng.c + device/StdDriver/src/m2354_rtc.c + device/StdDriver/src/m2354_sc.c + device/StdDriver/src/m2354_scuart.c + device/StdDriver/src/m2354_sdh.c + device/StdDriver/src/m2354_spi.c + device/StdDriver/src/m2354_sys.c + device/StdDriver/src/m2354_tamper.c + device/StdDriver/src/m2354_timer.c + device/StdDriver/src/m2354_timer_pwm.c + device/StdDriver/src/m2354_uart.c + device/StdDriver/src/m2354_usbd.c + device/StdDriver/src/m2354_usci_i2c.c + device/StdDriver/src/m2354_usci_spi.c + device/StdDriver/src/m2354_usci_uart.c + device/StdDriver/src/m2354_wdt.c + device/StdDriver/src/m2354_wwdt.c + + dma_api.c + gpio_api.c + gpio_irq_api.c + i2c_api.c + lp_ticker.c + mbed_overrides.c + PeripheralPins.c + pinmap.c + port_api.c + pwmout_api.c + rtc_api.c + serial_api.c + sleep.c + spi_api.c + us_ticker.c +) + +target_include_directories(mbed-m2354 + INTERFACE + . + device + device/Reg + device/StdDriver/inc +) + +target_link_libraries(mbed-m2354 INTERFACE mbed-nuvoton) + +mbed_set_linker_script(mbed-m2354 ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) + +add_library(mbed-nu-m2354 INTERFACE) + +if("TFM" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_TFM) +endif() + +target_include_directories(mbed-nu-m2354 + INTERFACE + TARGET_NU_M2354 +) + +target_link_libraries(mbed-nu-m2354 + INTERFACE + mbed-m2354 + mbed-m2354-tfm +) diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/PeripheralNames.h b/targets/TARGET_NUVOTON/TARGET_M2354/PeripheralNames.h new file mode 100644 index 0000000000..98518508ed --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/PeripheralNames.h @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALNAMES_H +#define MBED_PERIPHERALNAMES_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// NOTE: Check all module base addresses (XXX_BASE in BSP) for free bit fields to define module name +// which encodes module base address and module index/subindex. +#define NU_MODSUBINDEX_Pos 0 +#define NU_MODSUBINDEX_Msk (0x1Ful << NU_MODSUBINDEX_Pos) +#define NU_MODINDEX_Pos 20 +#define NU_MODINDEX_Msk (0xFul << NU_MODINDEX_Pos) + +#define NU_MODNAME(MODBASE, INDEX, SUBINDEX) ((MODBASE) | ((INDEX) << NU_MODINDEX_Pos) | ((SUBINDEX) << NU_MODSUBINDEX_Pos)) +#define NU_MODBASE(MODNAME) ((MODNAME) & ~(NU_MODINDEX_Msk | NU_MODSUBINDEX_Msk)) +#define NU_MODINDEX(MODNAME) (((MODNAME) & NU_MODINDEX_Msk) >> NU_MODINDEX_Pos) +#define NU_MODSUBINDEX(MODNAME) (((MODNAME) & NU_MODSUBINDEX_Msk) >> NU_MODSUBINDEX_Pos) + +#if 0 +typedef enum { + + GPIO_A = (int) NU_MODNAME(GPIOA_BASE + NS_OFFSET, 0, 0), + GPIO_B = (int) NU_MODNAME(GPIOB_BASE + NS_OFFSET, 1, 0), + GPIO_C = (int) NU_MODNAME(GPIOC_BASE + NS_OFFSET, 2, 0), + GPIO_D = (int) NU_MODNAME(GPIOD_BASE + NS_OFFSET, 3, 0), + GPIO_E = (int) NU_MODNAME(GPIOE_BASE + NS_OFFSET, 4, 0), + GPIO_F = (int) NU_MODNAME(GPIOF_BASE + NS_OFFSET, 5, 0), + GPIO_G = (int) NU_MODNAME(GPIOG_BASE + NS_OFFSET, 6, 0), + GPIO_H = (int) NU_MODNAME(GPIOH_BASE + NS_OFFSET, 7, 0), + +} GPIOName; +#endif + +typedef enum { + + ADC_0_0 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 0), + ADC_0_1 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 1), + ADC_0_2 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 2), + ADC_0_3 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 3), + ADC_0_4 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 4), + ADC_0_5 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 5), + ADC_0_6 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 6), + ADC_0_7 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 7), + ADC_0_8 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 8), + ADC_0_9 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 9), + ADC_0_10 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 10), + ADC_0_11 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 11), + ADC_0_12 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 12), + ADC_0_13 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 13), + ADC_0_14 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 14), + ADC_0_15 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 15), + +} ADCName; + +typedef enum { + + DAC_0_0 = (int) NU_MODNAME(DAC0_BASE + NS_OFFSET, 0, 0), + DAC_1_0 = (int) NU_MODNAME(DAC1_BASE + NS_OFFSET, 1, 0), + +} DACName; + +typedef enum { + + UART_0 = (int) NU_MODNAME(UART0_BASE + NS_OFFSET, 0, 0), + UART_1 = (int) NU_MODNAME(UART1_BASE + NS_OFFSET, 1, 0), + UART_2 = (int) NU_MODNAME(UART2_BASE + NS_OFFSET, 2, 0), + UART_3 = (int) NU_MODNAME(UART3_BASE + NS_OFFSET, 3, 0), + UART_4 = (int) NU_MODNAME(UART4_BASE + NS_OFFSET, 4, 0), + UART_5 = (int) NU_MODNAME(UART5_BASE + NS_OFFSET, 5, 0), + + // NOTE: board-specific +#if defined(MBED_CONF_TARGET_USB_UART) + USB_UART = MBED_CONF_TARGET_USB_UART, +#else + USB_UART = NC, +#endif +#if defined(MBED_CONF_TARGET_STDIO_UART) + STDIO_UART = MBED_CONF_TARGET_STDIO_UART, +#else + STDIO_UART = USB_UART, +#endif + +} UARTName; + +typedef enum { + + SPI_0 = (int) NU_MODNAME(SPI0_BASE + NS_OFFSET, 0, 0), + SPI_1 = (int) NU_MODNAME(SPI1_BASE + NS_OFFSET, 1, 0), + SPI_2 = (int) NU_MODNAME(SPI2_BASE + NS_OFFSET, 2, 0), + SPI_3 = (int) NU_MODNAME(SPI3_BASE + NS_OFFSET, 3, 0), + + /* No SPI4 H/W, degrade QSPI0 H/W to SPI_4 for standard SPI usage */ + SPI_4 = (int) NU_MODNAME(QSPI0_BASE + NS_OFFSET, 4, 0), + +} SPIName; + +typedef enum { + + I2C_0 = (int) NU_MODNAME(I2C0_BASE + NS_OFFSET, 0, 0), + I2C_1 = (int) NU_MODNAME(I2C1_BASE + NS_OFFSET, 1, 0), + I2C_2 = (int) NU_MODNAME(I2C2_BASE + NS_OFFSET, 2, 0), + +} I2CName; + +typedef enum { + + PWM_0_0 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 0), + PWM_0_1 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 1), + PWM_0_2 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 2), + PWM_0_3 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 3), + PWM_0_4 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 4), + PWM_0_5 = (int) NU_MODNAME(EPWM0_BASE + NS_OFFSET, 0, 5), + + PWM_1_0 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 0), + PWM_1_1 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 1), + PWM_1_2 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 2), + PWM_1_3 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 3), + PWM_1_4 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 4), + PWM_1_5 = (int) NU_MODNAME(EPWM1_BASE + NS_OFFSET, 1, 5), + +} PWMName; + +typedef enum { + + TIMER_2 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET, 2, 0), + TIMER_3 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET + 0x100, 3, 0), + TIMER_4 = (int) NU_MODNAME(TMR45_BASE + NS_OFFSET, 4, 0), + TIMER_5 = (int) NU_MODNAME(TMR45_BASE + NS_OFFSET + 0x100, 5, 0), + +} TIMERName; + +typedef enum { + + DMA_1 = (int) NU_MODNAME(PDMA1_BASE + NS_OFFSET, 1, 0), + +} DMAName; + +typedef enum { + + SD_0 = (int) NU_MODNAME(SDH0_BASE + NS_OFFSET, 0, 0), + +} SDName; + +typedef enum { + + CAN_0 = (int) NU_MODNAME(CAN0_BASE + NS_OFFSET, 0, 0), + +} CANName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/PeripheralPins.c b/targets/TARGET_NUVOTON/TARGET_M2354/PeripheralPins.c new file mode 100644 index 0000000000..e2c1722022 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/PeripheralPins.c @@ -0,0 +1,536 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralPins.h" + +//*** ADC *** + +const PinMap PinMap_ADC[] = { + {PB_0, ADC_0_0, SYS_GPB_MFPL_PB0MFP_EADC0_CH0}, + {PB_1, ADC_0_1, SYS_GPB_MFPL_PB1MFP_EADC0_CH1}, + {PB_2, ADC_0_2, SYS_GPB_MFPL_PB2MFP_EADC0_CH2}, + {PB_3, ADC_0_3, SYS_GPB_MFPL_PB3MFP_EADC0_CH3}, + {PB_4, ADC_0_4, SYS_GPB_MFPL_PB4MFP_EADC0_CH4}, + {PB_5, ADC_0_5, SYS_GPB_MFPL_PB5MFP_EADC0_CH5}, + {PB_6, ADC_0_6, SYS_GPB_MFPL_PB6MFP_EADC0_CH6}, + {PB_7, ADC_0_7, SYS_GPB_MFPL_PB7MFP_EADC0_CH7}, + {PB_8, ADC_0_8, SYS_GPB_MFPH_PB8MFP_EADC0_CH8}, + {PB_9, ADC_0_9, SYS_GPB_MFPH_PB9MFP_EADC0_CH9}, + {PB_10, ADC_0_10, SYS_GPB_MFPH_PB10MFP_EADC0_CH10}, + {PB_11, ADC_0_11, SYS_GPB_MFPH_PB11MFP_EADC0_CH11}, + {PB_12, ADC_0_12, SYS_GPB_MFPH_PB12MFP_EADC0_CH12}, + {PB_13, ADC_0_13, SYS_GPB_MFPH_PB13MFP_EADC0_CH13}, + {PB_14, ADC_0_14, SYS_GPB_MFPH_PB14MFP_EADC0_CH14}, + {PB_15, ADC_0_15, SYS_GPB_MFPH_PB15MFP_EADC0_CH15}, + + {NC, NC, 0} +}; + +//*** DAC *** + +const PinMap PinMap_DAC[] = { + {PB_12, DAC_0_0, SYS_GPB_MFPH_PB12MFP_DAC0_OUT}, + {PB_13, DAC_1_0, SYS_GPB_MFPH_PB13MFP_DAC1_OUT}, + + {NC, NC, 0} +}; + +//*** I2C *** + +const PinMap PinMap_I2C_SDA[] = { + {PA_0, I2C_2, SYS_GPA_MFPL_PA0MFP_I2C2_SDA}, + {PA_2, I2C_1, SYS_GPA_MFPL_PA2MFP_I2C1_SDA}, + {PA_4, I2C_0, SYS_GPA_MFPL_PA4MFP_I2C0_SDA}, + {PA_6, I2C_1, SYS_GPA_MFPL_PA6MFP_I2C1_SDA}, + {PA_10, I2C_2, SYS_GPA_MFPH_PA10MFP_I2C2_SDA}, + {PA_13, I2C_1, SYS_GPA_MFPH_PA13MFP_I2C1_SDA}, + {PA_15, I2C_2, SYS_GPA_MFPH_PA15MFP_I2C2_SDA}, + {PB_0, I2C_1, SYS_GPB_MFPL_PB0MFP_I2C1_SDA}, + {PB_2, I2C_1, SYS_GPB_MFPL_PB2MFP_I2C1_SDA}, + {PB_4, I2C_0, SYS_GPB_MFPL_PB4MFP_I2C0_SDA}, + {PB_8, I2C_0, SYS_GPB_MFPH_PB8MFP_I2C0_SDA}, + {PB_10, I2C_1, SYS_GPB_MFPH_PB10MFP_I2C1_SDA}, + {PB_12, I2C_2, SYS_GPB_MFPH_PB12MFP_I2C2_SDA}, + {PC_0, I2C_0, SYS_GPC_MFPL_PC0MFP_I2C0_SDA}, + {PC_4, I2C_1, SYS_GPC_MFPL_PC4MFP_I2C1_SDA}, + {PC_8, I2C_0, SYS_GPC_MFPH_PC8MFP_I2C0_SDA}, + {PC_11, I2C_0, SYS_GPC_MFPH_PC11MFP_I2C0_SDA}, + {PD_0, I2C_2, SYS_GPD_MFPL_PD0MFP_I2C2_SDA}, + {PD_4, I2C_1, SYS_GPD_MFPL_PD4MFP_I2C1_SDA}, + {PD_6, I2C_0, SYS_GPD_MFPL_PD6MFP_I2C0_SDA}, + {PD_8, I2C_2, SYS_GPD_MFPH_PD8MFP_I2C2_SDA}, + {PE_0, I2C_1, SYS_GPE_MFPL_PE0MFP_I2C1_SDA}, + {PF_1, I2C_1, SYS_GPF_MFPL_PF1MFP_I2C1_SDA}, + {PF_2, I2C_0, SYS_GPF_MFPL_PF2MFP_I2C0_SDA}, + {PG_3, I2C_1, SYS_GPG_MFPL_PG3MFP_I2C1_SDA}, + {PH_9, I2C_2, SYS_GPH_MFPH_PH9MFP_I2C2_SDA}, + + {NC, NC, 0} +}; + +const PinMap PinMap_I2C_SCL[] = { + {PA_1, I2C_2, SYS_GPA_MFPL_PA1MFP_I2C2_SCL}, + {PA_3, I2C_1, SYS_GPA_MFPL_PA3MFP_I2C1_SCL}, + {PA_5, I2C_0, SYS_GPA_MFPL_PA5MFP_I2C0_SCL}, + {PA_7, I2C_1, SYS_GPA_MFPL_PA7MFP_I2C1_SCL}, + {PA_11, I2C_2, SYS_GPA_MFPH_PA11MFP_I2C2_SCL}, + {PA_12, I2C_1, SYS_GPA_MFPH_PA12MFP_I2C1_SCL}, + {PA_14, I2C_2, SYS_GPA_MFPH_PA14MFP_I2C2_SCL}, + {PB_1, I2C_1, SYS_GPB_MFPL_PB1MFP_I2C1_SCL}, + {PB_3, I2C_1, SYS_GPB_MFPL_PB3MFP_I2C1_SCL}, + {PB_5, I2C_0, SYS_GPB_MFPL_PB5MFP_I2C0_SCL}, + {PB_9, I2C_0, SYS_GPB_MFPH_PB9MFP_I2C0_SCL}, + {PB_11, I2C_1, SYS_GPB_MFPH_PB11MFP_I2C1_SCL}, + {PB_13, I2C_2, SYS_GPB_MFPH_PB13MFP_I2C2_SCL}, + {PC_1, I2C_0, SYS_GPC_MFPL_PC1MFP_I2C0_SCL}, + {PC_5, I2C_1, SYS_GPC_MFPL_PC5MFP_I2C1_SCL}, + {PC_12, I2C_0, SYS_GPC_MFPH_PC12MFP_I2C0_SCL}, + {PD_1, I2C_2, SYS_GPD_MFPL_PD1MFP_I2C2_SCL}, + {PD_5, I2C_1, SYS_GPD_MFPL_PD5MFP_I2C1_SCL}, + {PD_7, I2C_0, SYS_GPD_MFPL_PD7MFP_I2C0_SCL}, + {PD_9, I2C_2, SYS_GPD_MFPH_PD9MFP_I2C2_SCL}, + {PE_1, I2C_1, SYS_GPE_MFPL_PE1MFP_I2C1_SCL}, + {PE_13, I2C_0, SYS_GPE_MFPH_PE13MFP_I2C0_SCL}, + {PF_0, I2C_1, SYS_GPF_MFPL_PF0MFP_I2C1_SCL}, + {PF_3, I2C_0, SYS_GPF_MFPL_PF3MFP_I2C0_SCL}, + {PG_2, I2C_1, SYS_GPG_MFPL_PG2MFP_I2C1_SCL}, + {PH_8, I2C_2, SYS_GPH_MFPH_PH8MFP_I2C2_SCL}, + + {NC, NC, 0} +}; + +//*** PWM *** + +const PinMap PinMap_PWM[] = { + {PA_0, PWM_0_5, SYS_GPA_MFPL_PA0MFP_EPWM0_CH5}, + {PA_1, PWM_0_4, SYS_GPA_MFPL_PA1MFP_EPWM0_CH4}, + {PA_2, PWM_0_3, SYS_GPA_MFPL_PA2MFP_EPWM0_CH3}, + {PA_3, PWM_0_2, SYS_GPA_MFPL_PA3MFP_EPWM0_CH2}, + {PA_4, PWM_0_1, SYS_GPA_MFPL_PA4MFP_EPWM0_CH1}, + {PA_5, PWM_0_0, SYS_GPA_MFPL_PA5MFP_EPWM0_CH0}, + {PA_6, PWM_1_5, SYS_GPA_MFPL_PA6MFP_EPWM1_CH5}, + {PA_7, PWM_1_4, SYS_GPA_MFPL_PA7MFP_EPWM1_CH4}, + {PB_0, PWM_0_5, SYS_GPB_MFPL_PB0MFP_EPWM0_CH5}, + {NU_PINNAME_BIND(PB_0, PWM_0_5), PWM_0_5, SYS_GPB_MFPL_PB0MFP_EPWM0_CH5}, + {PB_0, PWM_1_5, SYS_GPB_MFPL_PB0MFP_EPWM1_CH5}, + {NU_PINNAME_BIND(PB_0, PWM_1_5), PWM_1_5, SYS_GPB_MFPL_PB0MFP_EPWM1_CH5}, + {PB_1, PWM_0_4, SYS_GPB_MFPL_PB1MFP_EPWM0_CH4}, + {NU_PINNAME_BIND(PB_1, PWM_0_4), PWM_0_4, SYS_GPB_MFPL_PB1MFP_EPWM0_CH4}, + {PB_1, PWM_1_4, SYS_GPB_MFPL_PB1MFP_EPWM1_CH4}, + {NU_PINNAME_BIND(PB_1, PWM_1_4), PWM_1_4, SYS_GPB_MFPL_PB1MFP_EPWM1_CH4}, + {PB_2, PWM_0_3, SYS_GPB_MFPL_PB2MFP_EPWM0_CH3}, + {PB_3, PWM_0_2, SYS_GPB_MFPL_PB3MFP_EPWM0_CH2}, + {PB_4, PWM_0_1, SYS_GPB_MFPL_PB4MFP_EPWM0_CH1}, + {PB_5, PWM_0_0, SYS_GPB_MFPL_PB5MFP_EPWM0_CH0}, + {PB_6, PWM_1_5, SYS_GPB_MFPL_PB6MFP_EPWM1_CH5}, + {PB_7, PWM_1_4, SYS_GPB_MFPL_PB7MFP_EPWM1_CH4}, + {PB_12, PWM_1_3, SYS_GPB_MFPH_PB12MFP_EPWM1_CH3}, + {PB_13, PWM_1_2, SYS_GPB_MFPH_PB13MFP_EPWM1_CH2}, + {PB_14, PWM_1_1, SYS_GPB_MFPH_PB14MFP_EPWM1_CH1}, + {PB_15, PWM_1_0, SYS_GPB_MFPH_PB15MFP_EPWM1_CH0}, + {PC_0, PWM_1_5, SYS_GPC_MFPL_PC0MFP_EPWM1_CH5}, + {PC_1, PWM_1_4, SYS_GPC_MFPL_PC1MFP_EPWM1_CH4}, + {PC_2, PWM_1_3, SYS_GPC_MFPL_PC2MFP_EPWM1_CH3}, + {PC_3, PWM_1_2, SYS_GPC_MFPL_PC3MFP_EPWM1_CH2}, + {PC_4, PWM_1_1, SYS_GPC_MFPL_PC4MFP_EPWM1_CH1}, + {PC_5, PWM_1_0, SYS_GPC_MFPL_PC5MFP_EPWM1_CH0}, + {PC_6, PWM_1_3, SYS_GPC_MFPL_PC6MFP_EPWM1_CH3}, + {PC_7, PWM_1_2, SYS_GPC_MFPL_PC7MFP_EPWM1_CH2}, + {PC_8, PWM_1_1, SYS_GPC_MFPH_PC8MFP_EPWM1_CH1}, + {PC_9, PWM_1_3, SYS_GPC_MFPH_PC9MFP_EPWM1_CH3}, + {PC_10, PWM_1_2, SYS_GPC_MFPH_PC10MFP_EPWM1_CH2}, + {PC_11, PWM_1_1, SYS_GPC_MFPH_PC11MFP_EPWM1_CH1}, + {PC_12, PWM_1_0, SYS_GPC_MFPH_PC12MFP_EPWM1_CH0}, + {PD_14, PWM_0_4, SYS_GPD_MFPH_PD14MFP_EPWM0_CH4}, + {PE_2, PWM_0_5, SYS_GPE_MFPL_PE2MFP_EPWM0_CH5}, + {PE_3, PWM_0_4, SYS_GPE_MFPL_PE3MFP_EPWM0_CH4}, + {PE_4, PWM_0_3, SYS_GPE_MFPL_PE4MFP_EPWM0_CH3}, + {PE_5, PWM_0_2, SYS_GPE_MFPL_PE5MFP_EPWM0_CH2}, + {PE_6, PWM_0_1, SYS_GPE_MFPL_PE6MFP_EPWM0_CH1}, + {PE_7, PWM_0_0, SYS_GPE_MFPL_PE7MFP_EPWM0_CH0}, + {PE_8, PWM_0_0, SYS_GPE_MFPH_PE8MFP_EPWM0_CH0}, + {PE_9, PWM_0_1, SYS_GPE_MFPH_PE9MFP_EPWM0_CH1}, + {PE_10, PWM_0_2, SYS_GPE_MFPH_PE10MFP_EPWM0_CH2}, + {PE_11, PWM_0_3, SYS_GPE_MFPH_PE11MFP_EPWM0_CH3}, + {PE_12, PWM_0_4, SYS_GPE_MFPH_PE12MFP_EPWM0_CH4}, + {PE_13, PWM_0_5, SYS_GPE_MFPH_PE13MFP_EPWM0_CH5}, + {NU_PINNAME_BIND(PE_13, PWM_0_5), PWM_0_5, SYS_GPE_MFPH_PE13MFP_EPWM0_CH5}, + {PE_13, PWM_1_0, SYS_GPE_MFPH_PE13MFP_EPWM1_CH0}, + {NU_PINNAME_BIND(PE_13, PWM_1_0), PWM_1_0, SYS_GPE_MFPH_PE13MFP_EPWM1_CH0}, + {PF_4, PWM_0_1, SYS_GPF_MFPL_PF4MFP_EPWM0_CH1}, + {PF_5, PWM_0_0, SYS_GPF_MFPL_PF5MFP_EPWM0_CH0}, + {PH_11, PWM_0_5, SYS_GPH_MFPH_PH11MFP_EPWM0_CH5}, + + {NC, NC, 0} +}; + +//*** SERIAL *** + +const PinMap PinMap_UART_TX[] = { + {PA_1, UART_0, SYS_GPA_MFPL_PA1MFP_UART0_TXD}, + {PA_3, UART_1, SYS_GPA_MFPL_PA3MFP_UART1_TXD}, + {NU_PINNAME_BIND(PA_3, UART_1), UART_1, SYS_GPA_MFPL_PA3MFP_UART1_TXD}, + {PA_3, UART_4, SYS_GPA_MFPL_PA3MFP_UART4_TXD}, + {NU_PINNAME_BIND(PA_3, UART_4), UART_4, SYS_GPA_MFPL_PA3MFP_UART4_TXD}, + {PA_5, UART_0, SYS_GPA_MFPL_PA5MFP_UART0_TXD}, + {PA_5, UART_5, SYS_GPA_MFPL_PA5MFP_UART5_TXD}, + {PA_7, UART_0, SYS_GPA_MFPL_PA7MFP_UART0_TXD}, + {PA_9, UART_1, SYS_GPA_MFPH_PA9MFP_UART1_TXD}, + {PA_12, UART_4, SYS_GPA_MFPH_PA12MFP_UART4_TXD}, + {PA_14, UART_0, SYS_GPA_MFPH_PA14MFP_UART0_TXD}, + {PB_1, UART_2, SYS_GPB_MFPL_PB1MFP_UART2_TXD}, + {PB_3, UART_1, SYS_GPB_MFPL_PB3MFP_UART1_TXD}, + {PB_5, UART_2, SYS_GPB_MFPL_PB5MFP_UART2_TXD}, + {PB_5, UART_5, SYS_GPB_MFPL_PB5MFP_UART5_TXD}, + {PB_7, UART_1, SYS_GPB_MFPL_PB7MFP_UART1_TXD}, + {PB_9, UART_0, SYS_GPB_MFPH_PB9MFP_UART0_TXD}, + {PB_11, UART_4, SYS_GPB_MFPH_PB11MFP_UART4_TXD}, + {PB_13, UART_0, SYS_GPB_MFPH_PB13MFP_UART0_TXD}, + {PB_15, UART_3, SYS_GPB_MFPH_PB15MFP_UART3_TXD}, + {PC_1, UART_2, SYS_GPC_MFPL_PC1MFP_UART2_TXD}, + {PC_3, UART_3, SYS_GPC_MFPL_PC3MFP_UART3_TXD}, + {PC_5, UART_2, SYS_GPC_MFPL_PC5MFP_UART2_TXD}, + {NU_PINNAME_BIND(PC_5, UART_2), UART_2, SYS_GPC_MFPL_PC5MFP_UART2_TXD}, + {PC_5, UART_4, SYS_GPC_MFPL_PC5MFP_UART4_TXD}, + {NU_PINNAME_BIND(PC_5, UART_4), UART_4, SYS_GPC_MFPL_PC5MFP_UART4_TXD}, + {PC_7, UART_4, SYS_GPC_MFPL_PC7MFP_UART4_TXD}, + {PC_10, UART_3, SYS_GPC_MFPH_PC10MFP_UART3_TXD}, + {PC_12, UART_0, SYS_GPC_MFPH_PC12MFP_UART0_TXD}, + {PC_13, UART_2, SYS_GPC_MFPH_PC13MFP_UART2_TXD}, + {PD_1, UART_3, SYS_GPD_MFPL_PD1MFP_UART3_TXD}, + {PD_3, UART_0, SYS_GPD_MFPL_PD3MFP_UART0_TXD}, + {PD_7, UART_1, SYS_GPD_MFPL_PD7MFP_UART1_TXD}, + {PD_11, UART_1, SYS_GPD_MFPH_PD11MFP_UART1_TXD}, + {PE_1, UART_3, SYS_GPE_MFPL_PE1MFP_UART3_TXD}, + {PE_7, UART_5, SYS_GPE_MFPL_PE7MFP_UART5_TXD}, + {PE_8, UART_2, SYS_GPE_MFPH_PE8MFP_UART2_TXD}, + {PE_10, UART_3, SYS_GPE_MFPH_PE10MFP_UART3_TXD}, + {PE_13, UART_1, SYS_GPE_MFPH_PE13MFP_UART1_TXD}, + {PE_14, UART_2, SYS_GPE_MFPH_PE14MFP_UART2_TXD}, + {PF_0, UART_0, SYS_GPF_MFPL_PF0MFP_UART0_TXD}, + {PF_0, UART_1, SYS_GPF_MFPL_PF0MFP_UART1_TXD}, + {PF_3, UART_0, SYS_GPF_MFPL_PF3MFP_UART0_TXD}, + {PF_4, UART_2, SYS_GPF_MFPL_PF4MFP_UART2_TXD}, + {PF_7, UART_4, SYS_GPF_MFPL_PF7MFP_UART4_TXD}, + {PF_11, UART_5, SYS_GPF_MFPH_PF11MFP_UART5_TXD}, + {PH_8, UART_1, SYS_GPH_MFPH_PH8MFP_UART1_TXD}, + {PH_10, UART_0, SYS_GPH_MFPH_PH10MFP_UART0_TXD}, + {NU_PINNAME_BIND(PH_10, UART_0), UART_0, SYS_GPH_MFPH_PH10MFP_UART0_TXD}, + {PH_10, UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD}, + {NU_PINNAME_BIND(PH_10, UART_4), UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD}, + + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RX[] = { + {PA_0, UART_0, SYS_GPA_MFPL_PA0MFP_UART0_RXD}, + {PA_2, UART_1, SYS_GPA_MFPL_PA2MFP_UART1_RXD}, + {NU_PINNAME_BIND(PA_2, UART_1), UART_1, SYS_GPA_MFPL_PA2MFP_UART1_RXD}, +#if !COMPONENT_FPGA_CI_TEST_SHIELD || !TARGET_NU_M2354 + /* Get around one pin-to-many peripherals issue to pass FPGA CI Test Shield tests */ + {PA_2, UART_4, SYS_GPA_MFPL_PA2MFP_UART4_RXD}, + {NU_PINNAME_BIND(PA_2, UART_4), UART_4, SYS_GPA_MFPL_PA2MFP_UART4_RXD}, +#endif + {PA_4, UART_0, SYS_GPA_MFPL_PA4MFP_UART0_RXD}, + {PA_4, UART_5, SYS_GPA_MFPL_PA4MFP_UART5_RXD}, + {PA_6, UART_0, SYS_GPA_MFPL_PA6MFP_UART0_RXD}, + {PA_8, UART_1, SYS_GPA_MFPH_PA8MFP_UART1_RXD}, + {PA_13, UART_4, SYS_GPA_MFPH_PA13MFP_UART4_RXD}, + {PA_15, UART_0, SYS_GPA_MFPH_PA15MFP_UART0_RXD}, + {PB_0, UART_2, SYS_GPB_MFPL_PB0MFP_UART2_RXD}, + {PB_2, UART_1, SYS_GPB_MFPL_PB2MFP_UART1_RXD}, + {PB_4, UART_2, SYS_GPB_MFPL_PB4MFP_UART2_RXD}, + {PB_4, UART_5, SYS_GPB_MFPL_PB4MFP_UART5_RXD}, + {PB_6, UART_1, SYS_GPB_MFPL_PB6MFP_UART1_RXD}, + {PB_8, UART_0, SYS_GPB_MFPH_PB8MFP_UART0_RXD}, +#if !COMPONENT_FPGA_CI_TEST_SHIELD || !TARGET_NU_M2354 + /* Need NU_PINNAME_BIND(...) to pick up the correct peripheral on + * the TX part. Remove to pass FPGA CI Test Shield tests. */ + {PB_10, UART_4, SYS_GPB_MFPH_PB10MFP_UART4_RXD}, +#endif + {PB_12, UART_0, SYS_GPB_MFPH_PB12MFP_UART0_RXD}, + {PB_14, UART_3, SYS_GPB_MFPH_PB14MFP_UART3_RXD}, + {PC_0, UART_2, SYS_GPC_MFPL_PC0MFP_UART2_RXD}, + {PC_2, UART_3, SYS_GPC_MFPL_PC2MFP_UART3_RXD}, + {PC_4, UART_2, SYS_GPC_MFPL_PC4MFP_UART2_RXD}, + {NU_PINNAME_BIND(PC_4, UART_2), UART_2, SYS_GPC_MFPL_PC4MFP_UART2_RXD}, + {PC_4, UART_4, SYS_GPC_MFPL_PC4MFP_UART4_RXD}, + {NU_PINNAME_BIND(PC_4, UART_4), UART_4, SYS_GPC_MFPL_PC4MFP_UART4_RXD}, + {PC_6, UART_4, SYS_GPC_MFPL_PC6MFP_UART4_RXD}, + {PC_8, UART_1, SYS_GPC_MFPH_PC8MFP_UART1_RXD}, + {PC_9, UART_3, SYS_GPC_MFPH_PC9MFP_UART3_RXD}, + {PC_11, UART_0, SYS_GPC_MFPH_PC11MFP_UART0_RXD}, + {PD_0, UART_3, SYS_GPD_MFPL_PD0MFP_UART3_RXD}, + {PD_2, UART_0, SYS_GPD_MFPL_PD2MFP_UART0_RXD}, + {PD_6, UART_1, SYS_GPD_MFPL_PD6MFP_UART1_RXD}, + {PD_10, UART_1, SYS_GPD_MFPH_PD10MFP_UART1_RXD}, + {PD_12, UART_2, SYS_GPD_MFPH_PD12MFP_UART2_RXD}, + {PE_0, UART_3, SYS_GPE_MFPL_PE0MFP_UART3_RXD}, + {PE_6, UART_5, SYS_GPE_MFPL_PE6MFP_UART5_RXD}, + {PE_9, UART_2, SYS_GPE_MFPH_PE9MFP_UART2_RXD}, + {PE_11, UART_3, SYS_GPE_MFPH_PE11MFP_UART3_RXD}, + {PE_15, UART_2, SYS_GPE_MFPH_PE15MFP_UART2_RXD}, + {PF_1, UART_0, SYS_GPF_MFPL_PF1MFP_UART0_RXD}, + {PF_1, UART_1, SYS_GPF_MFPL_PF1MFP_UART1_RXD}, + {PF_2, UART_0, SYS_GPF_MFPL_PF2MFP_UART0_RXD}, + {PF_5, UART_2, SYS_GPF_MFPL_PF5MFP_UART2_RXD}, + {PF_6, UART_4, SYS_GPF_MFPL_PF6MFP_UART4_RXD}, + {PF_10, UART_5, SYS_GPF_MFPH_PF10MFP_UART5_RXD}, + {PH_9, UART_1, SYS_GPH_MFPH_PH9MFP_UART1_RXD}, + {PH_11, UART_0, SYS_GPH_MFPH_PH11MFP_UART0_RXD}, + {NU_PINNAME_BIND(PH_11, UART_0), UART_0, SYS_GPH_MFPH_PH11MFP_UART0_RXD}, + {PH_11, UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD}, + {NU_PINNAME_BIND(PH_11, UART_4), UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD}, + + {NC, NC, 0} +}; + +const PinMap PinMap_UART_RTS[] = { + {PA_0, UART_1, SYS_GPA_MFPL_PA0MFP_UART1_nRTS}, + {PA_4, UART_0, SYS_GPA_MFPL_PA4MFP_UART0_nRTS}, + {PB_3, UART_5, SYS_GPB_MFPL_PB3MFP_UART5_nRTS}, + {PB_8, UART_1, SYS_GPB_MFPH_PB8MFP_UART1_nRTS}, + {PB_10, UART_0, SYS_GPB_MFPH_PB10MFP_UART0_nRTS}, + {PB_13, UART_3, SYS_GPB_MFPH_PB13MFP_UART3_nRTS}, + {PB_14, UART_0, SYS_GPB_MFPH_PB14MFP_UART0_nRTS}, + {PC_3, UART_2, SYS_GPC_MFPL_PC3MFP_UART2_nRTS}, + {PC_6, UART_0, SYS_GPC_MFPL_PC6MFP_UART0_nRTS}, + {PD_3, UART_3, SYS_GPD_MFPL_PD3MFP_UART3_nRTS}, + {PD_8, UART_2, SYS_GPD_MFPH_PD8MFP_UART2_nRTS}, + {PE_0, UART_4, SYS_GPE_MFPL_PE0MFP_UART4_nRTS}, + {PE_12, UART_1, SYS_GPE_MFPH_PE12MFP_UART1_nRTS}, + {PE_13, UART_4, SYS_GPE_MFPH_PE13MFP_UART4_nRTS}, + {PF_4, UART_2, SYS_GPF_MFPL_PF4MFP_UART2_nRTS}, + {PF_9, UART_5, SYS_GPF_MFPH_PF9MFP_UART5_nRTS}, + {PH_8, UART_3, SYS_GPH_MFPH_PH8MFP_UART3_nRTS}, + + {NC, NC, 0} +}; + +const PinMap PinMap_UART_CTS[] = { + {PA_1, UART_1, SYS_GPA_MFPL_PA1MFP_UART1_nCTS}, + {PA_5, UART_0, SYS_GPA_MFPL_PA5MFP_UART0_nCTS}, + {PB_2, UART_5, SYS_GPB_MFPL_PB2MFP_UART5_nCTS}, + {PB_9, UART_1, SYS_GPB_MFPH_PB9MFP_UART1_nCTS}, + {PB_11, UART_0, SYS_GPB_MFPH_PB11MFP_UART0_nCTS}, + {PB_12, UART_3, SYS_GPB_MFPH_PB12MFP_UART3_nCTS}, + {PB_15, UART_0, SYS_GPB_MFPH_PB15MFP_UART0_nCTS}, + {PC_2, UART_2, SYS_GPC_MFPL_PC2MFP_UART2_nCTS}, + {PC_7, UART_0, SYS_GPC_MFPL_PC7MFP_UART0_nCTS}, + {PC_8, UART_4, SYS_GPC_MFPH_PC8MFP_UART4_nCTS}, + {PD_2, UART_3, SYS_GPD_MFPL_PD2MFP_UART3_nCTS}, + {PD_9, UART_2, SYS_GPD_MFPH_PD9MFP_UART2_nCTS}, + {PE_1, UART_4, SYS_GPE_MFPL_PE1MFP_UART4_nCTS}, + {PE_11, UART_1, SYS_GPE_MFPH_PE11MFP_UART1_nCTS}, + {PF_5, UART_2, SYS_GPF_MFPL_PF5MFP_UART2_nCTS}, + {PF_8, UART_5, SYS_GPF_MFPH_PF8MFP_UART5_nCTS}, + {PH_9, UART_3, SYS_GPH_MFPH_PH9MFP_UART3_nCTS}, + + {NC, NC, 0} +}; + +//*** SPI *** + +const PinMap PinMap_SPI_MOSI[] = { + {PA_0, SPI_4, SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0}, + {NU_PINNAME_BIND(PA_0, SPI_4), SPI_4, SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0}, + {PA_0, SPI_0, SYS_GPA_MFPL_PA0MFP_SPI0_MOSI}, + {NU_PINNAME_BIND(PA_0, SPI_0), SPI_0, SYS_GPA_MFPL_PA0MFP_SPI0_MOSI}, + {PA_8, SPI_2, SYS_GPA_MFPH_PA8MFP_SPI2_MOSI}, + {PA_15, SPI_2, SYS_GPA_MFPH_PA15MFP_SPI2_MOSI}, + {PB_4, SPI_1, SYS_GPB_MFPL_PB4MFP_SPI1_MOSI}, + {PB_8, SPI_3, SYS_GPB_MFPH_PB8MFP_SPI3_MOSI}, + {PB_12, SPI_0, SYS_GPB_MFPH_PB12MFP_SPI0_MOSI}, + {PC_0, SPI_4, SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0}, + {PC_2, SPI_1, SYS_GPC_MFPL_PC2MFP_SPI1_MOSI}, + {PC_6, SPI_1, SYS_GPC_MFPL_PC6MFP_SPI1_MOSI}, + {PC_11, SPI_3, SYS_GPC_MFPH_PC11MFP_SPI3_MOSI}, + {PD_0, SPI_0, SYS_GPD_MFPL_PD0MFP_SPI0_MOSI}, + {PD_6, SPI_1, SYS_GPD_MFPL_PD6MFP_SPI1_MOSI}, + {PE_0, SPI_4, SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0}, + {NU_PINNAME_BIND(PE_0, SPI_4), SPI_4, SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0}, + {PE_0, SPI_1, SYS_GPE_MFPL_PE0MFP_SPI1_MOSI}, + {NU_PINNAME_BIND(PE_0, SPI_1), SPI_1, SYS_GPE_MFPL_PE0MFP_SPI1_MOSI}, + {PE_2, SPI_3, SYS_GPE_MFPL_PE2MFP_SPI3_MOSI}, + {PE_10, SPI_2, SYS_GPE_MFPH_PE10MFP_SPI2_MOSI}, + {PF_6, SPI_0, SYS_GPF_MFPL_PF6MFP_SPI0_MOSI}, + {PF_11, SPI_2, SYS_GPF_MFPH_PF11MFP_SPI2_MOSI}, + {PH_5, SPI_1, SYS_GPH_MFPL_PH5MFP_SPI1_MOSI}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_MISO[] = { + {PA_1, SPI_4, SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0}, + {NU_PINNAME_BIND(PA_1, SPI_4), SPI_4, SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0}, + {PA_1, SPI_0, SYS_GPA_MFPL_PA1MFP_SPI0_MISO}, + {NU_PINNAME_BIND(PA_1, SPI_0), SPI_0, SYS_GPA_MFPL_PA1MFP_SPI0_MISO}, + {PA_9, SPI_2, SYS_GPA_MFPH_PA9MFP_SPI2_MISO}, + {PA_14, SPI_2, SYS_GPA_MFPH_PA14MFP_SPI2_MISO}, + {PB_5, SPI_1, SYS_GPB_MFPL_PB5MFP_SPI1_MISO}, + {PB_9, SPI_3, SYS_GPB_MFPH_PB9MFP_SPI3_MISO}, + {PB_13, SPI_0, SYS_GPB_MFPH_PB13MFP_SPI0_MISO}, + {PC_1, SPI_4, SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0}, + {PC_3, SPI_1, SYS_GPC_MFPL_PC3MFP_SPI1_MISO}, + {PC_7, SPI_1, SYS_GPC_MFPL_PC7MFP_SPI1_MISO}, + {PC_12, SPI_3, SYS_GPC_MFPH_PC12MFP_SPI3_MISO}, + {PD_1, SPI_0, SYS_GPD_MFPL_PD1MFP_SPI0_MISO}, + {PD_7, SPI_1, SYS_GPD_MFPL_PD7MFP_SPI1_MISO}, + {PE_1, SPI_4, SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0}, + {NU_PINNAME_BIND(PE_1, SPI_4), SPI_4, SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0}, + {PE_1, SPI_1, SYS_GPE_MFPL_PE1MFP_SPI1_MISO}, + {NU_PINNAME_BIND(PE_1, SPI_1), SPI_1, SYS_GPE_MFPL_PE1MFP_SPI1_MISO}, + {PE_3, SPI_3, SYS_GPE_MFPL_PE3MFP_SPI3_MISO}, + {PE_9, SPI_2, SYS_GPE_MFPH_PE9MFP_SPI2_MISO}, + {PF_7, SPI_0, SYS_GPF_MFPL_PF7MFP_SPI0_MISO}, + {PG_4, SPI_2, SYS_GPG_MFPL_PG4MFP_SPI2_MISO}, + {PH_4, SPI_1, SYS_GPH_MFPL_PH4MFP_SPI1_MISO}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SCLK[] = { + {PA_2, SPI_4, SYS_GPA_MFPL_PA2MFP_QSPI0_CLK}, + {NU_PINNAME_BIND(PA_2, SPI_4), SPI_4, SYS_GPA_MFPL_PA2MFP_QSPI0_CLK}, + {PA_2, SPI_0, SYS_GPA_MFPL_PA2MFP_SPI0_CLK}, + {NU_PINNAME_BIND(PA_2, SPI_0), SPI_0, SYS_GPA_MFPL_PA2MFP_SPI0_CLK}, + {PA_7, SPI_1, SYS_GPA_MFPL_PA7MFP_SPI1_CLK}, + {PA_10, SPI_2, SYS_GPA_MFPH_PA10MFP_SPI2_CLK}, + {PA_13, SPI_2, SYS_GPA_MFPH_PA13MFP_SPI2_CLK}, + {PB_3, SPI_1, SYS_GPB_MFPL_PB3MFP_SPI1_CLK}, + {PB_11, SPI_3, SYS_GPB_MFPH_PB11MFP_SPI3_CLK}, + {PB_14, SPI_0, SYS_GPB_MFPH_PB14MFP_SPI0_CLK}, + {PC_1, SPI_1, SYS_GPC_MFPL_PC1MFP_SPI1_CLK}, + {PC_2, SPI_4, SYS_GPC_MFPL_PC2MFP_QSPI0_CLK}, + {PC_10, SPI_3, SYS_GPC_MFPH_PC10MFP_SPI3_CLK}, + {PD_2, SPI_0, SYS_GPD_MFPL_PD2MFP_SPI0_CLK}, + {PD_5, SPI_1, SYS_GPD_MFPL_PD5MFP_SPI1_CLK}, + {PE_4, SPI_3, SYS_GPE_MFPL_PE4MFP_SPI3_CLK}, + {PE_8, SPI_2, SYS_GPE_MFPH_PE8MFP_SPI2_CLK}, + {PF_2, SPI_4, SYS_GPF_MFPL_PF2MFP_QSPI0_CLK}, + {PF_8, SPI_0, SYS_GPF_MFPH_PF8MFP_SPI0_CLK}, + {PG_3, SPI_2, SYS_GPG_MFPL_PG3MFP_SPI2_CLK}, + {PH_6, SPI_1, SYS_GPH_MFPL_PH6MFP_SPI1_CLK}, + {PH_8, SPI_4, SYS_GPH_MFPH_PH8MFP_QSPI0_CLK}, + {NU_PINNAME_BIND(PH_8, SPI_4), SPI_4, SYS_GPH_MFPH_PH8MFP_QSPI0_CLK}, + {PH_8, SPI_1, SYS_GPH_MFPH_PH8MFP_SPI1_CLK}, + {NU_PINNAME_BIND(PH_8, SPI_1), SPI_1, SYS_GPH_MFPH_PH8MFP_SPI1_CLK}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SPI_SSEL[] = { + {PA_3, SPI_4, SYS_GPA_MFPL_PA3MFP_QSPI0_SS}, + {NU_PINNAME_BIND(PA_3, SPI_4), SPI_4, SYS_GPA_MFPL_PA3MFP_QSPI0_SS}, + {PA_3, SPI_0, SYS_GPA_MFPL_PA3MFP_SPI0_SS}, + {NU_PINNAME_BIND(PA_3, SPI_0), SPI_0, SYS_GPA_MFPL_PA3MFP_SPI0_SS}, + {PA_6, SPI_1, SYS_GPA_MFPL_PA6MFP_SPI1_SS}, + {PA_11, SPI_2, SYS_GPA_MFPH_PA11MFP_SPI2_SS}, + {PA_12, SPI_2, SYS_GPA_MFPH_PA12MFP_SPI2_SS}, + {PB_2, SPI_1, SYS_GPB_MFPL_PB2MFP_SPI1_SS}, + {PB_10, SPI_3, SYS_GPB_MFPH_PB10MFP_SPI3_SS}, + {PB_15, SPI_0, SYS_GPB_MFPH_PB15MFP_SPI0_SS}, + {PC_0, SPI_1, SYS_GPC_MFPL_PC0MFP_SPI1_SS}, + {PC_3, SPI_4, SYS_GPC_MFPL_PC3MFP_QSPI0_SS}, + {PC_9, SPI_3, SYS_GPC_MFPH_PC9MFP_SPI3_SS}, + {PD_3, SPI_0, SYS_GPD_MFPL_PD3MFP_SPI0_SS}, + {PD_4, SPI_1, SYS_GPD_MFPL_PD4MFP_SPI1_SS}, + {PE_5, SPI_3, SYS_GPE_MFPL_PE5MFP_SPI3_SS}, + {PE_11, SPI_2, SYS_GPE_MFPH_PE11MFP_SPI2_SS}, + {PF_9, SPI_0, SYS_GPF_MFPH_PF9MFP_SPI0_SS}, + {PG_2, SPI_2, SYS_GPG_MFPL_PG2MFP_SPI2_SS}, + {PH_7, SPI_1, SYS_GPH_MFPL_PH7MFP_SPI1_SS}, + {PH_9, SPI_4, SYS_GPH_MFPH_PH9MFP_QSPI0_SS}, + {NU_PINNAME_BIND(PH_9, SPI_4), SPI_4, SYS_GPH_MFPH_PH9MFP_QSPI0_SS}, + {PH_9, SPI_1, SYS_GPH_MFPH_PH9MFP_SPI1_SS}, + {NU_PINNAME_BIND(PH_9, SPI_1), SPI_1, SYS_GPH_MFPH_PH9MFP_SPI1_SS}, + + {NC, NC, 0} +}; + +//*** SD *** + +const PinMap PinMap_SD_DAT0[] = { + {PB_2, SD_0, SYS_GPB_MFPL_PB2MFP_SD0_DAT0}, + {PE_2, SD_0, SYS_GPE_MFPL_PE2MFP_SD0_DAT0}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SD_DAT1[] = { + {PB_3, SD_0, SYS_GPB_MFPL_PB3MFP_SD0_DAT1}, + {PE_3, SD_0, SYS_GPE_MFPL_PE3MFP_SD0_DAT1}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SD_DAT2[] = { + {PB_4, SD_0, SYS_GPB_MFPL_PB4MFP_SD0_DAT2}, + {PE_4, SD_0, SYS_GPE_MFPL_PE4MFP_SD0_DAT2}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SD_DAT3[] = { + {PB_5, SD_0, SYS_GPB_MFPL_PB5MFP_SD0_DAT3}, + {PE_5, SD_0, SYS_GPE_MFPL_PE5MFP_SD0_DAT3}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SD_CMD[] = { + {PB_0, SD_0, SYS_GPB_MFPL_PB0MFP_SD0_CMD}, + {PE_7, SD_0, SYS_GPE_MFPL_PE7MFP_SD0_CMD}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SD_CLK[] = { + {PB_1, SD_0, SYS_GPB_MFPL_PB1MFP_SD0_CLK}, + {PE_6, SD_0, SYS_GPE_MFPL_PE6MFP_SD0_CLK}, + + {NC, NC, 0} +}; + +const PinMap PinMap_SD_CD[] = { + {PB_12, SD_0, SYS_GPB_MFPH_PB12MFP_SD0_nCD}, + + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_TD[] = { + {PA_5, CAN_0, SYS_GPA_MFPL_PA5MFP_CAN0_TXD}, + {PA_12, CAN_0, SYS_GPA_MFPH_PA12MFP_CAN0_TXD}, + {PB_11, CAN_0, SYS_GPB_MFPH_PB11MFP_CAN0_TXD}, + {PC_5, CAN_0, SYS_GPC_MFPL_PC5MFP_CAN0_TXD}, + {PD_11, CAN_0, SYS_GPD_MFPH_PD11MFP_CAN0_TXD}, + {PE_14, CAN_0, SYS_GPE_MFPH_PE14MFP_CAN0_TXD}, + + {NC, NC, 0} +}; + +const PinMap PinMap_CAN_RD[] = { + {PA_4, CAN_0, SYS_GPA_MFPL_PA4MFP_CAN0_RXD}, + {PA_13, CAN_0, SYS_GPA_MFPH_PA13MFP_CAN0_RXD}, + {PB_10, CAN_0, SYS_GPB_MFPH_PB10MFP_CAN0_RXD}, + {PC_4, CAN_0, SYS_GPC_MFPL_PC4MFP_CAN0_RXD}, + {PD_10, CAN_0, SYS_GPD_MFPH_PD10MFP_CAN0_RXD}, + {PE_15, CAN_0, SYS_GPE_MFPH_PE15MFP_CAN0_RXD}, + + {NC, NC, 0} +}; diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/PeripheralPins.h b/targets/TARGET_NUVOTON/TARGET_M2354/PeripheralPins.h new file mode 100644 index 0000000000..3fc2efaf72 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/PeripheralPins.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_PERIPHERALPINS_H +#define MBED_PERIPHERALPINS_H + +#include "pinmap.h" +#include "PeripheralNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +//*** GPIO *** + +extern const PinMap PinMap_GPIO[]; + +//*** ADC *** + +extern const PinMap PinMap_ADC[]; + +//*** DAC *** + +extern const PinMap PinMap_DAC[]; + +//*** I2C *** + +extern const PinMap PinMap_I2C_SDA[]; +extern const PinMap PinMap_I2C_SCL[]; + +//*** PWM *** + +extern const PinMap PinMap_PWM[]; + +//*** SERIAL *** + +extern const PinMap PinMap_UART_TX[]; +extern const PinMap PinMap_UART_RX[]; +extern const PinMap PinMap_UART_RTS[]; +extern const PinMap PinMap_UART_CTS[]; + +//*** SPI *** + +extern const PinMap PinMap_SPI_MOSI[]; +extern const PinMap PinMap_SPI_MISO[]; +extern const PinMap PinMap_SPI_SCLK[]; +extern const PinMap PinMap_SPI_SSEL[]; + +//*** SD *** + +extern const PinMap PinMap_SD_CD[]; +extern const PinMap PinMap_SD_CMD[]; +extern const PinMap PinMap_SD_CLK[]; +extern const PinMap PinMap_SD_DAT0[]; +extern const PinMap PinMap_SD_DAT1[]; +extern const PinMap PinMap_SD_DAT2[]; +extern const PinMap PinMap_SD_DAT3[]; + +//*** CAN *** + +extern PinMap const PinMap_CAN_TD[]; +extern PinMap const PinMap_CAN_RD[]; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/PinNamesCommon.h b/targets/TARGET_NUVOTON/TARGET_M2354/PinNamesCommon.h new file mode 100644 index 0000000000..9b43dd91d7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/PinNamesCommon.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __PIN_NAMES_COMMON_H__ +#define __PIN_NAMES_COMMON_H__ + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define NU_PININDEX_Pos 0 +#define NU_PININDEX_Msk (0xFFul << NU_PININDEX_Pos) +#define NU_PINPORT_Pos 8 +#define NU_PINPORT_Msk (0xFul << NU_PINPORT_Pos) +#define NU_PIN_MODINDEX_Pos 12 +#define NU_PIN_MODINDEX_Msk (0xFul << NU_PIN_MODINDEX_Pos) +#define NU_PIN_BIND_Pos 16 +#define NU_PIN_BIND_Msk (0x1ul << NU_PIN_BIND_Pos) + +#define NU_PININDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PININDEX_Msk) >> NU_PININDEX_Pos) +#define NU_PINPORT(PINNAME) (((unsigned int)(PINNAME) & NU_PINPORT_Msk) >> NU_PINPORT_Pos) +#define NU_PIN_BIND(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_BIND_Msk) >> NU_PIN_BIND_Pos) +#define NU_PIN_MODINDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_MODINDEX_Msk) >> NU_PIN_MODINDEX_Pos) +#define NU_PINNAME(PORT, PIN) ((((unsigned int) (PORT)) << (NU_PINPORT_Pos)) | (((unsigned int) (PIN)) << NU_PININDEX_Pos)) +#define NU_PINNAME_BIND(PINNAME, modname) ((PinName) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname)) +#define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk) + +/* Revise NU_PORT_BASE to be TrustZone-aware */ +__STATIC_INLINE GPIO_T *NU_PORT_BASE(uint32_t PORT) +{ + uint32_t port_base = ((uint32_t) GPIOA_BASE) + 0x40 * PORT; + + /* No support for secure build. Fixed to non-secure. */ + port_base += NS_OFFSET; + + return ((GPIO_T *) port_base); +} + +#define NU_MFP_POS(pin) ((pin % 8) * 4) +#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin)) + +/* TrustZone-aware version of GPIO_PIN_DATA to get GPIO pin data */ +__STATIC_INLINE uint32_t NU_GET_GPIO_PIN_DATA(uint32_t PORT, uint32_t PIN) +{ + /* No support for secure build. Fixed to non-secure. */ + return GPIO_PIN_DATA_NS(PORT, PIN); +} + +/* TrustZone-aware version of GPIO_PIN_DATA to set GPIO pin data */ +__STATIC_INLINE void NU_SET_GPIO_PIN_DATA(uint32_t PORT, uint32_t PIN, uint32_t VALUE) +{ + /* No support for secure build. Fixed to non-secure. */ + GPIO_PIN_DATA_NS(PORT, PIN) = VALUE; +} + +// LEGACY +#define NU_PINNAME_TO_PIN(PINNAME) NU_PININDEX(PINNAME) +#define NU_PINNAME_TO_PORT(PINNAME) NU_PINPORT(PINNAME) +#define NU_PINNAME_TO_MODSUBINDEX(PINNAME) NU_PIN_MODINDEX(PINNAME) +#define NU_PORT_N_PIN_TO_PINNAME(PORT, PIN) NU_PINNAME((PORT), (PIN)) + +typedef enum { + PIN_INPUT, + PIN_OUTPUT +} PinDirection; + +typedef enum { + /* Input pull mode */ + PullNone = 0, + PullDown, + PullUp, + + /* I/O mode */ + InputOnly, + PushPullOutput, + OpenDrain, + QuasiBidirectional, + + /* Default input pull mode */ + PullDefault = PullUp +} PinMode; + +#ifdef __cplusplus +} +#endif + +#endif // __PIN_NAMES_COMMON_H__ diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramaccommand/unittest.cmake b/targets/TARGET_NUVOTON/TARGET_M2354/PortNames.h similarity index 51% rename from connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramaccommand/unittest.cmake rename to targets/TARGET_NUVOTON/TARGET_M2354/PortNames.h index c6497c781e..347a96af4f 100644 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramaccommand/unittest.cmake +++ b/targets/TARGET_NUVOTON/TARGET_M2354/PortNames.h @@ -1,5 +1,6 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -13,29 +14,27 @@ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. -]] + */ -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaMacCommand") +#ifndef MBED_PORTNAMES_H +#define MBED_PORTNAMES_H -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/mac/LoRaMacCommand.cpp -) +#ifdef __cplusplus +extern "C" { +#endif -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/mac -) +typedef enum { + PortA = 0, + PortB = 1, + PortC = 2, + PortD = 3, + PortE = 4, + PortF = 5, + PortG = 6, + PortH = 7 +} PortName; -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaMacCommand.cpp - stubs/mbed_assert_stub.cpp - stubs/LoRaPHY_stub.cpp -) - -set(unittest-test-flags - -DMBED_CONF_LORA_TX_MAX_SIZE=255 -) +#ifdef __cplusplus +} +#endif +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_NU_M2354/PinNames.h b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_NU_M2354/PinNames.h new file mode 100644 index 0000000000..e24f0814f7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_NU_M2354/PinNames.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* MBED TARGET LIST: NU_M2354 */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesCommon.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + // Not connected + NC = (int)0xFFFFFFFF, + + // Generic naming + PA_INIT = NU_PORT_N_PIN_TO_PINNAME(0, 0), PA_0 = PA_INIT, PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7, PA_8, PA_9, PA_10, PA_11, PA_12, PA_13, PA_14, PA_15, + PB_INIT = NU_PORT_N_PIN_TO_PINNAME(1, 0), PB_0 = PB_INIT, PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PB_10, PB_11, PB_12, PB_13, PB_14, PB_15, + PC_INIT = NU_PORT_N_PIN_TO_PINNAME(2, 0), PC_0 = PC_INIT, PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7, PC_8, PC_9, PC_10, PC_11, PC_12, PC_13, + PD_INIT = NU_PORT_N_PIN_TO_PINNAME(3, 0), PD_0 = PD_INIT, PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7, PD_8, PD_9, PD_10, PD_11, PD_12, PD_14 = PD_12 + 2, + PE_INIT = NU_PORT_N_PIN_TO_PINNAME(4, 0), PE_0 = PE_INIT, PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, PE_7, PE_8, PE_9, PE_10, PE_11, PE_12, PE_13, PE_14, PE_15, + PF_INIT = NU_PORT_N_PIN_TO_PINNAME(5, 0), PF_0 = PF_INIT, PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PF_7, PF_8, PF_9, PF_10, PF_11, + PG_INIT = NU_PORT_N_PIN_TO_PINNAME(6, 0), PG_2 = PG_INIT + 2, PG_3, PG_4, PG_9 = PG_4 + 5, PG_10, PG_11, PG_12, PG_13, PG_14, PG_15, + PH_INIT = NU_PORT_N_PIN_TO_PINNAME(7, 0), PH_4 = PH_INIT + 4, PH_5, PH_6, PH_7, PH_8, PH_9, PH_10, PH_11, + + // Arduino UNO naming + ARDUINO_UNO_A0 = PB_11, + ARDUINO_UNO_A1 = PB_10, + ARDUINO_UNO_A2 = PB_9, + ARDUINO_UNO_A3 = PB_8, + ARDUINO_UNO_A4 = PB_7, + ARDUINO_UNO_A5 = PB_6, + + ARDUINO_UNO_D0 = PA_8, + ARDUINO_UNO_D1 = PA_9, + ARDUINO_UNO_D2 = PC_1, + ARDUINO_UNO_D3 = PC_0, + ARDUINO_UNO_D4 = PE_7, + ARDUINO_UNO_D5 = PE_6, + ARDUINO_UNO_D6 = PC_12, + ARDUINO_UNO_D7 = PC_11, + ARDUINO_UNO_D8 = PC_9, + ARDUINO_UNO_D9 = PC_10, + ARDUINO_UNO_D10 = PA_3, + ARDUINO_UNO_D11 = PA_0, + ARDUINO_UNO_D12 = PA_1, + ARDUINO_UNO_D13 = PA_2, + ARDUINO_UNO_D14 = PG_3, + ARDUINO_UNO_D15 = PG_2, + + // Other board-specific naming + + // UART naming + CONSOLE_TX = MBED_CONF_TARGET_USB_UART_TX, + CONSOLE_RX = MBED_CONF_TARGET_USB_UART_RX, + +#if defined(MBED_CONF_TARGET_STDIO_UART_TX) + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = CONSOLE_TX, +#endif +#if defined(MBED_CONF_TARGET_STDIO_UART_RX) + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = CONSOLE_RX, +#endif + + // Force PinName to 32-bit required by NU_PINNAME_BIND(...) + FORCE_ENUM_PINNAME_32BIT = 0x7FFFFFFF, + +} PinName; + +// LED naming +#define LED1 PD_2 +#define LED2 PD_3 + +// Button naming +#define BUTTON1 PF_11 // SW2 + +#ifdef __cplusplus +} +#endif + +#endif // MBED_PINNAMES_H diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/CMakeLists.txt b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/CMakeLists.txt new file mode 100644 index 0000000000..ce7edc9c85 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/CMakeLists.txt @@ -0,0 +1,20 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-m2354-tfm INTERFACE) + +if("NU_M2354" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_NU_M2354) +endif() + +target_include_directories(mbed-m2354-tfm + INTERFACE + . +) + +target_sources(mbed-m2354-tfm + INTERFACE + platform_extra_secure.c + platform_extra_secure_compat.c + tfm_ns_interface.c +) diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/CMakeLists.txt b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/CMakeLists.txt new file mode 100644 index 0000000000..1bb9197988 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if("TFM_S_FW" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(COMPONENT_TFM_S_FW) +endif() diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/CMakeLists.txt b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/CMakeLists.txt new file mode 100644 index 0000000000..03127cc5a5 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/CMakeLists.txt @@ -0,0 +1,27 @@ +# Copyright (c) 2020-2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(${MBED_PATH}/targets/TARGET_NUVOTON/scripts/mbed_set_post_build_nuvoton.cmake) + +target_link_libraries(mbed-m2354-tfm + INTERFACE + ${CMAKE_CURRENT_SOURCE_DIR}/s_veneers.o +) + +mbed_post_build_nuvoton_tfm_sign_image_tgt( + NU_M2354 + ${CMAKE_CURRENT_SOURCE_DIR} + nuvoton_m2354-root-rsa-3072.pem +) + +set(bl2 true) +set(mcuboot_image_number 1) +set(region_defs_h_path "${CMAKE_CURRENT_SOURCE_DIR}/partition/region_defs.h") + +target_compile_definitions(mbed-m2354-tfm + INTERFACE + NU_TFM_S_BL2=$,1,0> + NU_TFM_S_MCUBOOT_IMAGE_NUMBER=${mcuboot_image_number} + # TODO: Fix escape sequence in NU_TFM_S_REGION_DEFS_H_PATH + #NU_TFM_S_REGION_DEFS_H_PATH=\"${region_defs_h_path}\" +) diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/LICENSE b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/LICENSE new file mode 100644 index 0000000000..161bfd20eb --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/LICENSE @@ -0,0 +1,49 @@ +Permissive Binary License + +Version 1.0, September 2015 + +Redistribution. Redistribution and use in binary form, without +modification, are permitted provided that the following conditions are +met: + +1) Redistributions must reproduce the above copyright notice and the + following disclaimer in the documentation and/or other materials + provided with the distribution. + +2) Unless to the extent explicitly permitted by law, no reverse + engineering, decompilation, or disassembly of this software is + permitted. + +3) Redistribution as part of a software development kit must include the + accompanying file named "DEPENDENCIES" and any dependencies listed in + that file. + +4) Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +Limited patent license. The copyright holders (and contributors) grant a +worldwide, non-exclusive, no-charge, royalty-free patent license to +make, have made, use, offer to sell, sell, import, and otherwise +transfer this software, where such license applies only to those patent +claims licensable by the copyright holders (and contributors) that are +necessarily infringed by this software. This patent license shall not +apply to any combinations that include this software. No hardware is +licensed hereunder. + +If you institute patent litigation against any entity (including a +cross-claim or counterclaim in a lawsuit) alleging that the software +itself infringes your patent(s), then your rights granted under this +license shall terminate as of the date such litigation is filed. + +DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT +NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/README.md b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/README.md new file mode 100644 index 0000000000..ba0f1507d9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/README.md @@ -0,0 +1,131 @@ +# Rebuild TF-M and integrate with Mbed on M2354 + +This document guides how to rebuild TF-M and integrate with Mbed on M2354. + +### Downloading TF-M source + +The M2354 port in TF-M must patch to enable TF-M integration with Mbed. +For TF-M 1.3/Mbed integration on M2354, the [mainstream TF-M](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git) is patched as follows: +- Apply Mbed-enabled patch to `nuvoton/m2354` TF-M target. + +Run the following command to fetch and switch to the intended version: +```sh +git clone https://github.com/OpenNuvoton/trusted-firmware-m -b nuvoton_mbed_m2354_tfm-1.3 +``` + +## Customizing TF-M + +TF-M is out of scope of Mbed. +We only provide limited support for customizing M2354 port in TF-M. + +### Default hardware partition + +In TF-M, by default, the M2354 hardware is partitioned as follows: + +- Flash (1024KiB in total): 448KiB for secure and 576KiB for nonsecure. +- SRAM (256KiB in total): 80KiB for secure and 176KiB for nonsecure. +- Peripherals: Most are configured to nonsecure except the following, which are hardwired or reserved: + - **SYS/CLK**: Hardwired to secure. Accessible to Mbed through secure gateway. + - **FMC**: Hardwired to secure. Inaccessible to Mbed. + - **WDT**: Hardwired to secure. Inaccessible to Mbed. + - **RTC**: Configured to secure. Accessible to Mbed through secure gateway. + - **TMR0/1**: Hardwired to secure. Inaccessible to Mbed. + - **TMR2/3**: Configured to nonsecure. TMR2 is used for TF-M NSPE test when enabled. + - **TMR4/5**: Configured to nonsecure for Mbed `us_ticker`/`lp_ticker`. + - **PDMA0**: Hardwired to secure. Inaccessible to Mbed. + - **PDMA1**: Configured to nonsecure for Mbed asynchronous transfer. + - **CRYPTO**: Configured to secure. Inaccessible to Mbed. + - **TRNG**: Hardwired to secure. Accessible to Mbed indirectly through PSA Cryptography API. + +### Defining Flash for TF-M/Mbed + +To define memory spec of Flash for TF-M/Mbed, search/change the line: + +**trusted-firmware-m/platform/ext/target/nuvoton/m2354/partition/flash_layout.h**: +```C +/* Max Flash size for TF-M + bootloader information */ +#define FLASH_S_PARTITION_SIZE (0x50000) +/* Max Flash size for Mbed + bootloader information */ +#define FLASH_NS_PARTITION_SIZE (0x90000) +``` + +M2354 has 1024KiB Flash in total, among which 128KiB have been allocated for bootloader code and ITS/PS storage. +896KiB are left for `FLASH_S_PARTITION_SIZE` and `FLASH_NS_PARTITION_SIZE`. + +**NOTE**: `FLASH_S_PARTITION_SIZE` and `FLASH_NS_PARTITION_SIZE` must be sector size (2KiB)-aligned. + +### Defining SRAM for TF-M/Mbed + +To define memory spec of SRAM for TF-M/Mbed, search/change the line: + +**trusted-firmware-m/platform/ext/target/nuvoton/m2354/partition/region_defs.h**: +```C +/* Max SRAM size for TF-M */ +#define S_DATA_SIZE (80 * 1024) +/* Max SRAM size for Mbed = Total - Max SRAM size for TF-M */ +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +``` + +**NOTE**: `S_DATA_SIZE` and `NS_DATA_SIZE` must be 16KiB-aligned required by M2354 Security Configuration Unit (SCU). + +## Rebuilding TF-M + +### Environment + +Navigate [TF-M](https://www.trustedfirmware.org/projects/tf-m/). +Then go through **DOCS** → **Getting Started Guides** → **Software requirements** for TF-M build environment setup. + +**NOTE**: **GNU Arm Embedded Toolchain 10-2020-q4-major** built code **FAILS** to run. Avoid this toolchain version. Check [its bug report](https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99157). + +### Compile + +To compile TF-M on M2354, run: + +```sh +cmake -S . \ +-B cmake_build \ +-DTFM_PLATFORM=nuvoton/m2354 \ +-DTFM_TOOLCHAIN_FILE=toolchain_GNUARM.cmake \ +-DTFM_PSA_API=ON \ +-DTFM_ISOLATION_LEVEL=2 \ +-G"Unix Makefiles" +``` + +Then: + +```sh +cmake --build cmake_build -- install +``` + +## Integrating with Mbed + +### Updating TF-M exported stuff + +The following TF-M exported stuffs must update into Mbed: + +- bl2.bin: [MCUboot](https://github.com/mcu-tools/mcuboot) bootloader binary + +- tfm_s.bin: TF-M secure binary + +- s_veneers.o: TF-M secure gateway library + +- partition/: Flash layout for image signing and concatenating in post-build process + + **NOTE**: On import, `signing_layout_s_ns.o` is renamed to `signing_layout_preprocessed.h` for the following reasons: + - Post-build script checks file name with `_s`/`_ns` to resolve `sw_type` as `SPE`/`NSPE` respectively. + To recognize as `NSPE_SPE`, don't use `_s_ns`/`_ns_s` file name to avoid mis-recognized. + - Use `.h` instead of `.c` as file extension name. + This is to enable custom TF-M build where the locatioin of this directory can change elsewhere. + In Greentea build process, `.c` file isn't but`.h` file is copied into `BUILD` directory, so that post-build script can still access the file. + +- [signing_key/](signing_key/nuvoton_m2354-root-rsa-3072.md) + +Below summarizes the copy paths from TF-M into Mbed: + +- trusted-firmware-m/cmake_build/bin/bl2.bin → bl2.bin +- trusted-firmware-m/cmake_build/install/export/tfm/lib/s_veneers.o → s_veneers.o +- trusted-firmware-m/cmake_build/bin/tfm_s.bin → tfm_s.bin +- trusted-firmware-m/platform/ext/target/nuvoton/m2354/partition/flash_layout.h → partition/flash_layout.h +- trusted-firmware-m/platform/ext/target/nuvoton/m2354/partition/region_defs.h → partition/region_defs.h +- trusted-firmware-m/cmake_build/bl2/ext/mcuboot/CMakeFiles/signing_layout_s.dir/signing_layout_s_ns.o → partition/signing_layout_preprocessed.h +- trusted-firmware-m/bl2/ext/mcuboot/root-RSA-3072.pem → signing_key/nuvoton_m2354-root-rsa-3072.pem diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/bl2.bin b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/bl2.bin new file mode 100644 index 0000000000..a80002a162 Binary files /dev/null and b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/bl2.bin differ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/flash_layout.h b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/flash_layout.h new file mode 100644 index 0000000000..819faca5ad --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/flash_layout.h @@ -0,0 +1,178 @@ +/* + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __FLASH_LAYOUT_H__ +#define __FLASH_LAYOUT_H__ + +/* Flash layout on M2354 with BL2 (single image boot): + * + * 0x0000_0000 BL2 - MCUBoot (64KB) + * 0x0001_0000 Protected Storage Area (32 KB) + * 0x0000_8000 Internal Trusted Storage Area (28 KB) + * 0x0000_F000 NV counters area (4 KB) + * 0x0002_0000 Primary image area (320KB): + * 0x0002_0000 Secure image primary + * 0x0007_0000 Non-secure image primary + * 0x0010_0000 Scratch area (4KB) + * + */ + +/* This header file is included from linker scatter file as well, where only a + * limited C constructs are allowed. Therefore it is not possible to include + * here the platform_retarget.h to access flash related defines. To resolve this + * some of the values are redefined here with different names, these are marked + * with comment. + */ + +/* Size of a Secure and of a Non-secure image */ +#define FLASH_S_PARTITION_SIZE (0x50000) /* S partition : 192+64+64 KB */ +#define FLASH_NS_PARTITION_SIZE (0x90000) /* NS partition: 768-64-64 KB */ +#define FLASH_MAX_PARTITION_SIZE ((FLASH_S_PARTITION_SIZE > \ + FLASH_NS_PARTITION_SIZE) ? \ + FLASH_S_PARTITION_SIZE : \ + FLASH_NS_PARTITION_SIZE) + +/* Sector size of the flash hardware; same as FLASH0_SECTOR_SIZE */ +#define FLASH_AREA_IMAGE_SECTOR_SIZE (0x800) /* 2 KB */ +/* Same as FLASH0_SIZE */ +#define FLASH_TOTAL_SIZE (0x00100000) /* 512 KB */ + +/* Flash layout info for BL2 bootloader */ +/* Same as FLASH0_BASE_S */ +#define FLASH_BASE_ADDRESS (0x00000000) + +/* Offset and size definitions of the flash partitions that are handled by the + * bootloader. The image swapping is done between IMAGE_PRIMARY and + * IMAGE_SECONDARY, SCRATCH is used as a temporary storage during image + * swapping. + */ +#define FLASH_AREA_BL2_OFFSET (0x0) +#define FLASH_AREA_BL2_SIZE (0x10000) /* 64 KB */ + +#if !defined(MCUBOOT_IMAGE_NUMBER) || (MCUBOOT_IMAGE_NUMBER == 1) +/* Secure + Non-secure image primary slot */ +#define FLASH_AREA_0_ID (1) +#define FLASH_AREA_0_OFFSET (FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE + 0x10000) /* 0x10000 */ +#define FLASH_AREA_0_SIZE (FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE) /* 480 KB */ +/* Secure + Non-secure secondary slot */ +#define FLASH_AREA_2_ID (FLASH_AREA_0_ID + 1) +#define FLASH_AREA_2_OFFSET (0x100000) +#define FLASH_AREA_2_SIZE (0x800) + +/* Scratch area */ +#define FLASH_AREA_SCRATCH_ID (FLASH_AREA_2_ID + 1) +#define FLASH_AREA_SCRATCH_OFFSET (0x100800) +#define FLASH_AREA_SCRATCH_SIZE (0x800) + +/* The maximum number of status entries supported by the bootloader. */ +#define MCUBOOT_STATUS_MAX_ENTRIES ((FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) / \ + FLASH_AREA_SCRATCH_SIZE) + +/* Maximum number of image sectors supported by the bootloader. */ +#define MCUBOOT_MAX_IMG_SECTORS ((FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) / \ + FLASH_AREA_IMAGE_SECTOR_SIZE) + +#else +#error "Only MCUBOOT_IMAGE_NUMBER 1 are supported!" +#endif /* MCUBOOT_IMAGE_NUMBER */ + +/* Protected Storage (PS) Service definitions */ +#define FLASH_PS_AREA_OFFSET (0x10000) +#define FLASH_PS_AREA_SIZE (0x8000) + +/* Internal Trusted Storage (ITS) Service definitions */ +#define FLASH_ITS_AREA_OFFSET (FLASH_PS_AREA_OFFSET + \ + FLASH_PS_AREA_SIZE) +#define FLASH_ITS_AREA_SIZE (0x7000) + +/* NV Counters definitions */ +#define FLASH_NV_COUNTERS_AREA_OFFSET (FLASH_ITS_AREA_OFFSET + \ + FLASH_ITS_AREA_SIZE) +#define FLASH_NV_COUNTERS_AREA_SIZE (FLASH_AREA_IMAGE_SECTOR_SIZE) + +/* Offset and size definition in flash area used by assemble.py */ +#define SECURE_IMAGE_OFFSET (0x0) +#define SECURE_IMAGE_MAX_SIZE FLASH_S_PARTITION_SIZE + +#define NON_SECURE_IMAGE_OFFSET (SECURE_IMAGE_OFFSET + \ + SECURE_IMAGE_MAX_SIZE) +#define NON_SECURE_IMAGE_MAX_SIZE FLASH_NS_PARTITION_SIZE + +/* Flash device name used by BL2 + * Name is defined in flash driver file: Driver_Flash.c + */ +#define FLASH_DEV_NAME Driver_FLASH0 + +/* Protected Storage (PS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M PS Integration Guide. + */ +#define TFM_HAL_PS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +#define TFM_HAL_PS_FLASH_AREA_ADDR FLASH_PS_AREA_OFFSET +/* Dedicated flash area for PS */ +#define TFM_HAL_PS_FLASH_AREA_SIZE FLASH_PS_AREA_SIZE +#define PS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE +/* Number of PS_SECTOR_SIZE per block */ +#define TFM_HAL_PS_SECTORS_PER_BLOCK (0x1) +/* Specifies the smallest flash programmable unit in bytes */ +#define TFM_HAL_PS_PROGRAM_UNIT (0x4) + +/* Internal Trusted Storage (ITS) Service definitions + * Note: Further documentation of these definitions can be found in the + * TF-M ITS Integration Guide. The ITS should be in the internal flash, but is + * allocated in the external flash just for development platforms that don't + * have internal flash available. + */ +#define TFM_HAL_ITS_FLASH_DRIVER Driver_FLASH0 + +/* In this target the CMSIS driver requires only the offset from the base + * address instead of the full memory address. + */ +#define TFM_HAL_ITS_FLASH_AREA_ADDR FLASH_ITS_AREA_OFFSET +/* Dedicated flash area for ITS */ +#define TFM_HAL_ITS_FLASH_AREA_SIZE FLASH_ITS_AREA_SIZE +#define ITS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE +/* Number of ITS_SECTOR_SIZE per block */ +#define TFM_HAL_ITS_SECTORS_PER_BLOCK (0x1) +/* Specifies the smallest flash programmable unit in bytes */ +#define TFM_HAL_ITS_PROGRAM_UNIT (0x4) + +/* NV Counters definitions */ +#define TFM_NV_COUNTERS_AREA_ADDR FLASH_NV_COUNTERS_AREA_OFFSET +#define TFM_NV_COUNTERS_AREA_SIZE (0x18) /* 24 Bytes */ +#define TFM_NV_COUNTERS_SECTOR_ADDR FLASH_NV_COUNTERS_AREA_OFFSET +#define TFM_NV_COUNTERS_SECTOR_SIZE FLASH_AREA_IMAGE_SECTOR_SIZE + +/* Use SRAM1 memory to store Code data */ +#define S_ROM_ALIAS_BASE (0x00000000) +#define NS_ROM_ALIAS_BASE (0x10000000) + +/* FIXME: Use SRAM2 memory to store RW data */ +#define S_RAM_ALIAS_BASE (0x20000000) +#define NS_RAM_ALIAS_BASE (0x30000000) + +#define TOTAL_ROM_SIZE FLASH_TOTAL_SIZE +#define TOTAL_RAM_SIZE (0x00040000) /* 256 KB */ + +#endif /* __FLASH_LAYOUT_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/region_defs.h b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/region_defs.h new file mode 100644 index 0000000000..219d89a01b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/region_defs.h @@ -0,0 +1,148 @@ +/* + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * Copyright (c) 2020 Nuvoton Technology Corp. All rights reserved. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __REGION_DEFS_H__ +#define __REGION_DEFS_H__ + +#include "flash_layout.h" + +#define BL2_HEAP_SIZE (0x0001000) +#define BL2_MSP_STACK_SIZE (0x0001800) + +#define S_HEAP_SIZE (0x0001000) +#define S_MSP_STACK_SIZE_INIT (0x0000400) +#define S_MSP_STACK_SIZE (0x0000800) +#define S_PSP_STACK_SIZE (0x0000800) + +#define NS_HEAP_SIZE (0x0001000) +#define NS_MSP_STACK_SIZE (0x0000800) +#define NS_PSP_STACK_SIZE (0x0000800) + +/* This size of buffer is big enough to store an attestation + * token produced by initial attestation service + */ +#define PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE (0x250) + +/* MPC granularity is 128 KB on AN519 MPS2 FPGA image. Alignment + * of partitions is defined in accordance with this constraint. + */ + +#ifdef BL2 +#ifndef LINK_TO_SECONDARY_PARTITION +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#define S_IMAGE_SECONDARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET) +#else +#error "No secondary partition supported!" +#endif /* !LINK_TO_SECONDARY_PARTITION */ +#else +#define S_IMAGE_PRIMARY_PARTITION_OFFSET (0x0) +#endif /* BL2 */ + +#ifndef LINK_TO_SECONDARY_PARTITION +#define NS_IMAGE_PRIMARY_PARTITION_OFFSET (FLASH_AREA_0_OFFSET + FLASH_S_PARTITION_SIZE) +#else +#error "No secondary partition supported!" +#endif /* !LINK_TO_SECONDARY_PARTITION */ + +/* Boot partition structure if MCUBoot is used: + * 0x0_0000 Bootloader header + * 0x0_0400 Image area + * 0x7_0000 Trailer + */ +/* IMAGE_CODE_SIZE is the space available for the software binary image. + * It is less than the FLASH_S_PARTITION_SIZE + FLASH_NS_PARTITION_SIZE + * because we reserve space for the image header and trailer introduced + * by the bootloader. + */ +#ifdef BL2 +#define BL2_HEADER_SIZE (0x400) /* 1 KB */ +#define BL2_TRAILER_SIZE (0x800) /* 2 KB */ +#else +/* No header if no bootloader, but keep IMAGE_CODE_SIZE the same */ +#define BL2_HEADER_SIZE (0x0) +#define BL2_TRAILER_SIZE (0x800) +#endif /* BL2 */ + +#define IMAGE_S_CODE_SIZE (FLASH_S_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) +#define IMAGE_NS_CODE_SIZE (FLASH_NS_PARTITION_SIZE - BL2_HEADER_SIZE - BL2_TRAILER_SIZE) + +#define CMSE_VENEER_REGION_SIZE (0x340) + +/* Alias definitions for secure and non-secure areas*/ +#define S_ROM_ALIAS(x) (S_ROM_ALIAS_BASE + (x)) +#define NS_ROM_ALIAS(x) (NS_ROM_ALIAS_BASE + (x)) + +#define S_RAM_ALIAS(x) (S_RAM_ALIAS_BASE + (x)) +#define NS_RAM_ALIAS(x) (NS_RAM_ALIAS_BASE + (x)) + +/* Secure regions */ +#define S_IMAGE_PRIMARY_AREA_OFFSET \ + (S_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) /* 0x8400 */ +#define S_CODE_START (S_ROM_ALIAS(S_IMAGE_PRIMARY_AREA_OFFSET)) /* 0x8400 */ +#define S_CODE_SIZE (IMAGE_S_CODE_SIZE - CMSE_VENEER_REGION_SIZE) +#define S_CODE_LIMIT (S_CODE_START + S_CODE_SIZE - 1) + +#define S_DATA_START (S_RAM_ALIAS(0x0)) +#define S_DATA_SIZE (80 * 1024) +#define S_DATA_LIMIT (S_DATA_START + S_DATA_SIZE - 1) + +/* CMSE Veneers region */ +#define CMSE_VENEER_REGION_START (S_CODE_LIMIT + 1) + +/* Non-secure regions */ +#define NS_IMAGE_PRIMARY_AREA_OFFSET \ + (NS_IMAGE_PRIMARY_PARTITION_OFFSET + BL2_HEADER_SIZE) +#define NS_CODE_START (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_AREA_OFFSET)) +#define NS_CODE_SIZE (IMAGE_NS_CODE_SIZE) +#define NS_CODE_LIMIT (NS_CODE_START + NS_CODE_SIZE - 1) + +#define NS_DATA_START (NS_RAM_ALIAS(S_DATA_SIZE)) +#define NS_DATA_SIZE (TOTAL_RAM_SIZE - S_DATA_SIZE) +#define NS_DATA_LIMIT (NS_DATA_START + NS_DATA_SIZE - 1) + +/* NS partition information is used for MPC and SAU configuration */ +#define NS_PARTITION_START \ + (NS_ROM_ALIAS(NS_IMAGE_PRIMARY_PARTITION_OFFSET)) +#define NS_PARTITION_SIZE (FLASH_NS_PARTITION_SIZE) + +/* Secondary partition for new images in case of firmware upgrade */ +#define SECONDARY_PARTITION_START \ + (NS_ROM_ALIAS(S_IMAGE_SECONDARY_PARTITION_OFFSET)) +#define SECONDARY_PARTITION_SIZE (FLASH_S_PARTITION_SIZE + \ + FLASH_NS_PARTITION_SIZE) + +#ifdef BL2 +/* Bootloader regions */ +#define BL2_CODE_START (S_ROM_ALIAS(FLASH_AREA_BL2_OFFSET)) +#define BL2_CODE_SIZE (FLASH_AREA_BL2_SIZE) +#define BL2_CODE_LIMIT (BL2_CODE_START + BL2_CODE_SIZE - 1) + +#define BL2_DATA_START (S_RAM_ALIAS(0x0)) +#define BL2_DATA_SIZE (TOTAL_RAM_SIZE) +#define BL2_DATA_LIMIT (BL2_DATA_START + BL2_DATA_SIZE - 1) +#endif /* BL2 */ + +/* Shared data area between bootloader and runtime firmware. + * Shared data area is allocated at the beginning of the RAM, it is overlapping + * with TF-M Secure code's MSP stack + */ +#define BOOT_TFM_SHARED_DATA_BASE S_RAM_ALIAS_BASE +#define BOOT_TFM_SHARED_DATA_SIZE (0x400) +#define BOOT_TFM_SHARED_DATA_LIMIT (BOOT_TFM_SHARED_DATA_BASE + BOOT_TFM_SHARED_DATA_SIZE - 1) + +#endif /* __REGION_DEFS_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/signing_layout_preprocessed.h b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/signing_layout_preprocessed.h new file mode 100644 index 0000000000..a0c3875886 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/signing_layout_preprocessed.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2020 Arm Limited + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +enum image_attributes { + RE_SECURE_IMAGE_OFFSET = (0x0), + RE_SECURE_IMAGE_MAX_SIZE = (0x50000), + RE_NON_SECURE_IMAGE_OFFSET = ((0x0) + (0x50000)), + RE_NON_SECURE_IMAGE_MAX_SIZE = (0x90000), + RE_SIGN_BIN_SIZE = ((0x50000) + (0x90000)), +}; diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/s_veneers.o b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/s_veneers.o new file mode 100644 index 0000000000..c963835056 Binary files /dev/null and b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/s_veneers.o differ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/signing_key/nuvoton_m2354-root-rsa-3072.md b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/signing_key/nuvoton_m2354-root-rsa-3072.md new file mode 100644 index 0000000000..0ca0675c49 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/signing_key/nuvoton_m2354-root-rsa-3072.md @@ -0,0 +1,11 @@ +# Nuvoton M2354 RSA keypair + +A default RSA key pair is given to the Nuvoton M2354 target. + +Public key was pre-compiled to `targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/bl2.bin` and private key is in `nuvoton_m2354-root-rsa-3072.pem` for Secure image and Non-Secure image together. + +DO NOT use them in production code, they are exclusively for testing! + +Private key must be stored in a safe place outside of the repository. + +`tools/psa/tfm/bin_utils/imgtool.py` can be used to generate new key pairs. diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/signing_key/nuvoton_m2354-root-rsa-3072.pem b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/signing_key/nuvoton_m2354-root-rsa-3072.pem new file mode 100644 index 0000000000..23288bc101 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/signing_key/nuvoton_m2354-root-rsa-3072.pem @@ -0,0 +1,39 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIG4gIBAAKCAYEAnLrCWr/MxU8gDE9vbFFPXAqrgLhrEMSbK8RSMglLOyeUah3V +TKhcoMB2lXsmBLETfngn1gy06LAtklKK+2n/QhCqVgyDyGVuug1fjvcrKZL8Qi0t ++YD1hSGH6qxAqMvQqDvi0uzwFEgOzyuKS6TNoQVbF2Yd3m5E/kajDdBpv4ytqRZo +Uet5kSDmgQMHiUBVS+vPZ/gxxxxUTlILYOiiUAfRz84SJs2Ogo1OZKn3xyGZJQfd +xdVf9GP6zCvaBlxZZ7AGNemqkkU15aAD/xwCtcdOlEturXOdzm8Js7GPYGyi+s13 +D8wn5jZYs1L3j75JmLfpYP2XV83q0wvfokL3RNOH3uAQA5Ta/LzdvpOzSitY3JYS +8m8jujs3/vwYH3V9VAEOvj0YE7MouTQs1fvFM72HvTvkHdcCPRxyZXJDQzao+uZz +LaRh6AKcOlZNHNF2nIyqXxvrHEr1ubhvQUsnh972lB/d5vGpwgLCT6P8pANa2W94 +/YTw5f09pU0brVtLAgMBAAECggGAG786mltbctEL0PIdPVV10cs3yq2bktfjys9S +Z/ZaQcpDjbfjY9NotrLsK5GmTO1WkKzQDKaqPom2P7HqVhFRdg5CQcKscAV5IWot +sT9T/mO90i9ydLoefWfOyr6dIeUXdzlG8mWtKUIKkSXZsYOnPesXUeCryA3InCXA +RzlPB3Dt68ICTQJ9vrJO7KcvJd7kWvEQAo2frmr3B/iheBInbji8LeiDMShyIu3G +Y67tpWzu0m3+lsAsYTV0GMJosniVulaZ3hYQQazHUk+zDzMSC7zryICrpjEbgzWU +HZI9EGi1B890nwUtdhlCpkr8zoWDb0BjawpftiGz7fRm7q2TQkYAWGzNKm3DZlIS +4LsRACvHnPZ17wUSze9tqP14Pb593WR3nOTiVjrJWm+4Z5hgV3QfoEqW5swOAYl4 +6QmKZsCXAfGkozJiHnYcyaULkGBVegn1LQ5rcb8JUMribQddrHZxCVHrbgwh2zm/ +v9CYfTtpWCnKHq+wF3mwjl6w7m4JAoHBALolVbgs919Dx0xjcPnW5MSxW3ctflI9 +2ZE1BOH/Rtg5gfBwR/aToUM3a/ZgIJHQYhVty2TzUVtthtmLNTRKu2FSqWN8//GJ +wmj4bcNBshMgniHEfkutlBiP9exhdvCZX4bYpdTkJAyvOmUGjEM8QBFsod60u0z7 +Bd0EIXs7PIURP0fNAUXCgSHMPjdICLljhwHinr31VEIU2/xehw8DBIJwkR/rCsPq +xBmlIwPWVjzCRTnYUxQuxCAYf+qvgNylKQKBwQDXi3UGI7t30rYNMdIjMn1GPkhW +o62BOJNCusoXiGnbVOkj8qBayf7kPu10ONBzHcYL7+SQYeVVXQY+DH033ji8oa0J +p1xMGIlx4JZEduQYlk0ke4hUNrcBQczTRA47DmMm2kIdWlaTHtB7aCJNx72IrwWn +lVTY9TWm6+yOPcpV5JfyCMM6GqoRycikgNS5IQug5hl2pFVLw+UTfxo6msYaAOnp +ICUjoeDUKS0Z8+FtzGhAkWTk8GXIiPbfu7RoN1MCgcAcah6Poq2QKTR/AJ76REdf +jwM7SgKCY1aWx9Ua+nDCCOVA4qLZjOeM7yTX0wyltX2Db+MgYdQFdM6k3o8ckFvS +G2AoA6i+Ih0/EM0QhTK9oLkCxo/Q1YpJxY/wqWASkhb26pNF0B2Aoi7zxPAcQ1I0 +VrTO3h/JPHhEqKDDwuMWHO/f8fdDwtEba6YDokdSpVKygvlgXdaiz7RU7ckIDZne +n3hHuwVFqsyMbZzOtSUs2SrgDZmA9zKRA6xjEq9E/yECgcAnm7XecfSCGVNg61XN +J/sDTHCokx1QEKBm88ItPuEM7/aDp5M1+8Z+FN43rDUJ4l/BU8zxhzvISvbZshvU +h15vs1oD2yBHz356UaXrYNmbdwsn+BdeOku4zGmiLPBcg9FOk27wy+f60v/GnaUo +G9tFYbwtRnC4CZ9ZVCM9JDepPv9494lAhSPZbvYS3KW6e0sSvxXQynPuH0paIdIl +EMn0f1R8hW6ttJKHCiYCjeFP9u71ZoJe25oolpqfFHQbbocCgcAuBR4w3Qmnbscm +3b7fyy8n3AXa1gIfYjjPpR35qyp1K9thiLyj66YZIl0ACC/dt08lmI9/lguRoNIQ +AfjzZ8DByZa0caiSiFIMlgNZXdh7N3BUNNbIQk98Wd91gBlWDAiFEhrJKFPpRkmv +FySATPYcq0lcrjJb3IW2GDK4uo/jb4Nb7Cfog95W6T76XcSKHS5O8k1aI4kFPRsr +1wGZw64OkA8VXVaCaEBQ4brZ1YKB3mx4/tDqwn0I6bqkGRX3RJg= +-----END RSA PRIVATE KEY----- diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.bin b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.bin new file mode 100644 index 0000000000..787bd0378b Binary files /dev/null and b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/tfm_s.bin differ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/cmsis_nvic_virtual.h b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/cmsis_nvic_virtual.h new file mode 100644 index 0000000000..d515b8101a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/cmsis_nvic_virtual.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cmsis.h" + +#ifndef NVIC_VIRTUAL_H +#define NVIC_VIRTUAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* NVIC functions */ +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority + +/** + * \brief Overriding the default CMSIS system reset implementation by calling + * secure TFM service. + * + */ +void NVIC_SystemReset(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/platform_extra_secure.c b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/platform_extra_secure.c new file mode 100644 index 0000000000..956dfedc8b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/platform_extra_secure.c @@ -0,0 +1,915 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "cmsis.h" +#include "platform_extra_secure.h" + +#if __MBED__ +#include "mbed_error.h" +#include "nu_bitutil.h" +#include "tfm_platform_api.h" +#elif NU_TFM_PLAT_IOCTL_NS +#include "tfm_platform_api.h" +#elif NU_TFM_PLAT_IOCTL_S +#include "tfm_platform_system.h" +#include +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS + +#if __MBED__ +#define PLAT_NSC_ERROR(SEC_FUNC, RC) \ + MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_HAL, MBED_ERROR_CODE_UNDERFLOW), \ + #SEC_FUNC "() failed with: ", RC) + +#elif NU_TFM_PLAT_IOCTL_NS +#define PLAT_NSC_ERROR(SEC_FUNC, RC) \ + do { \ + printf(#SEC_FUNC "() failed with: %d\n", RC); \ + while(1); \ + } while(0) + +#endif + +/* Secure function call via platform ioctl */ +#define PLAT_NSC_CALL(SEC_FUNC, INBUF, INSIZE, OUTBUF, OUTSIZE) \ + PLAT_NSC_CALL_(NU_PLAT_XTRA_SEC_REQ(SEC_FUNC), INBUF, INSIZE, OUTBUF, OUTSIZE) \ + if (rc != TFM_PLATFORM_ERR_SUCCESS) { \ + PLAT_NSC_ERROR(SEC_FUNC, rc); \ + } + +#define PLAT_NSC_CALL_(REQ, INBUF, INSIZE, OUTBUF, OUTSIZE) \ + enum tfm_platform_err_t rc; \ + tfm_platform_ioctl_req_t request; \ + psa_invec invec; \ + psa_outvec outvec; \ + request = (tfm_platform_ioctl_req_t) REQ; \ + if ((INBUF)) { \ + invec.base = (INBUF); \ + invec.len = (INSIZE); \ + if ((OUTBUF)) { \ + outvec.base = (OUTBUF); \ + outvec.len = (OUTSIZE); \ + rc = tfm_platform_ioctl(request, &invec, &outvec); \ + } else { \ + rc = tfm_platform_ioctl(request, &invec, NULL); \ + } \ + } else if ((OUTBUF)) { \ + outvec.base = (OUTBUF); \ + outvec.len = (OUTSIZE); \ + rc = tfm_platform_ioctl(request, NULL, &outvec); \ + } else { \ + rc = tfm_platform_ioctl(request, NULL, NULL); \ + } + +#elif NU_TFM_PLAT_IOCTL_S + +/* NOTE: Hazard of passing struct argument between client and service + * + * In TF-M IPC mode (TFM_PSA_API), struct argument is serialized and struct + * alignment doesn't guarantee as original. We resolve it by introducing + * intermediate struct during struct de-serialize, reglardless library or IPC + * mode. + * + * Check platform_sp_ioctl_ipc for struct serialize and align hazard: + * trusted-firmware-m > secure_fw > partitions > platform > platform_sp.c + */ + +/* Check parameter validity */ +#define NU_CHK_PARAM_VAL(INSIZE, OUTSIZE) \ + if (INSIZE) { \ + if (!in_vec || \ + !in_vec->base || \ + (in_vec->len != INSIZE && INSIZE != INT_MAX)) { \ + return TFM_PLATFORM_ERR_INVALID_PARAM; \ + } \ + } else { \ + if (in_vec) { \ + return TFM_PLATFORM_ERR_INVALID_PARAM; \ + } \ + } \ + if (OUTSIZE) { \ + if (!out_vec || \ + !out_vec->base || \ + (out_vec->len != OUTSIZE && OUTSIZE != INT_MAX)) { \ + return TFM_PLATFORM_ERR_INVALID_PARAM; \ + } \ + } else { \ + if (out_vec) { \ + return TFM_PLATFORM_ERR_INVALID_PARAM; \ + } \ + } \ + +#define NU_MFP_POS(pin) ((pin % 8) * 4) +#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin)) + +bool nu_check_sys_ns(uint32_t modidx); +bool nu_check_clk_ns(uint32_t modidx); +bool nu_check_gpio_ns(uint32_t port_index, uint32_t pin_index); + +#endif + +#if NU_TFM_PLAT_IOCTL_NS || NU_TFM_PLAT_IOCTL_S + +__STATIC_INLINE uint32_t nu_get32_be(const uint8_t *pos) +{ + uint32_t val; + + val = *pos ++; + val <<= 8; + val += *pos ++; + val <<= 8; + val += *pos ++; + val <<= 8; + val += *pos; + + return val; +} + +__STATIC_INLINE void nu_set32_be(uint8_t *pos, uint32_t val) +{ + *pos ++ = val >> 24; + *pos ++ = val >> 16; + *pos ++ = val >> 8; + *pos ++ = (val & 0xFF); +} + +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void SYS_ResetModule_S(uint32_t u32ModuleIndex) +{ + /* Set up input parameter for NSC call */ + uint8_t inbuf[4]; + nu_set32_be(inbuf, u32ModuleIndex); + + /* Invoke NSC function */ + PLAT_NSC_CALL(SYS_ResetModule_S, inbuf, sizeof(inbuf), NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(SYS_ResetModule_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(4, 0); + + uint32_t u32ModuleIndex = nu_get32_be(in_vec->base); + + /* Guard access to secure module from non-secure domain */ + if (!nu_check_sys_ns(u32ModuleIndex)) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + SYS_ResetModule(u32ModuleIndex); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void SYS_LockReg_S(void) +{ + /* Invoke NSC function */ + PLAT_NSC_CALL(SYS_LockReg_S, NULL, 0, NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(SYS_LockReg_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 0); + + SYS_LockReg(); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void SYS_UnlockReg_S(void) +{ + /* Invoke NSC function */ + PLAT_NSC_CALL(SYS_UnlockReg_S, NULL, 0, NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(SYS_UnlockReg_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 0); + + SYS_UnlockReg(); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void CLK_SetModuleClock_S(uint32_t u32ModuleIndex, uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + /* Set up input parameter for NSC call */ + uint8_t inbuf[12]; + nu_set32_be(inbuf, u32ModuleIndex); + nu_set32_be(inbuf + 4, u32ClkSrc); + nu_set32_be(inbuf + 8, u32ClkDiv); + + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_SetModuleClock_S, inbuf, sizeof(inbuf), NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_SetModuleClock_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(12, 0); + + uint32_t u32ModuleIndex = nu_get32_be(in_vec->base); + uint32_t u32ClkSrc = nu_get32_be(((const uint8_t *) in_vec->base) + 4); + uint32_t u32ClkDiv = nu_get32_be(((const uint8_t *) in_vec->base) + 8); + + /* Guard access to secure module from non-secure domain */ + if (!nu_check_clk_ns(u32ModuleIndex)) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + CLK_SetModuleClock(u32ModuleIndex, u32ClkSrc, u32ClkDiv); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void CLK_EnableModuleClock_S(uint32_t u32ModuleIndex) +{ + /* Set up input parameter for NSC call */ + uint8_t inbuf[4]; + nu_set32_be(inbuf, u32ModuleIndex); + + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_EnableModuleClock_S, inbuf, sizeof(inbuf), NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_EnableModuleClock_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(4, 0); + + uint32_t u32ModuleIndex = nu_get32_be(in_vec->base); + + /* Guard access to secure module from non-secure domain */ + if (!nu_check_clk_ns(u32ModuleIndex)) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + CLK_EnableModuleClock(u32ModuleIndex); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void CLK_DisableModuleClock_S(uint32_t u32ModuleIndex) +{ + /* Set up input parameter for NSC call */ + uint8_t inbuf[4]; + nu_set32_be(inbuf, u32ModuleIndex); + + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_DisableModuleClock_S, inbuf, sizeof(inbuf), NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_DisableModuleClock_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(4, 0); + + uint32_t u32ModuleIndex = nu_get32_be(in_vec->base); + + /* Guard access to secure module from non-secure domain */ + if (!nu_check_clk_ns(u32ModuleIndex)) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + CLK_DisableModuleClock(u32ModuleIndex); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void CLK_Idle_S(void) +{ + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_Idle_S, NULL, 0, NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_Idle_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 0); + + SYS_UnlockReg(); + CLK_Idle(); + SYS_LockReg(); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void CLK_PowerDown_S(void) +{ + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_PowerDown_S, NULL, 0, NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_PowerDown_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 0); + + SYS_UnlockReg(); + CLK_PowerDown(); + SYS_LockReg(); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetHXTFreq_S(void) +{ + /* Set up output parameter for NSC call */ + uint8_t outbuf[4]; + + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_GetHXTFreq_S, NULL, 0, outbuf, sizeof(outbuf)); + + /* Finalize output */ + uint32_t output = nu_get32_be(outbuf); + return output; +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetHXTFreq_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 4); + + uint32_t output = CLK_GetHXTFreq(); + nu_set32_be(out_vec->base, output); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetLXTFreq_S(void) +{ + /* Set up output parameter for NSC call */ + uint8_t outbuf[4]; + + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_GetLXTFreq_S, NULL, 0, outbuf, sizeof(outbuf)); + + /* Finalize output */ + uint32_t output = nu_get32_be(outbuf); + return output; +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetLXTFreq_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 4); + + uint32_t output = CLK_GetLXTFreq(); + nu_set32_be(out_vec->base, output); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetHCLKFreq_S(void) +{ + /* Set up output parameter for NSC call */ + uint8_t outbuf[4]; + + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_GetHCLKFreq_S, NULL, 0, outbuf, sizeof(outbuf)); + + /* Finalize output */ + uint32_t output = nu_get32_be(outbuf); + return output; +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetHCLKFreq_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 4); + + uint32_t output = CLK_GetHCLKFreq(); + nu_set32_be(out_vec->base, output); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetPCLK0Freq_S(void) +{ + /* Set up output parameter for NSC call */ + uint8_t outbuf[4]; + + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_GetPCLK0Freq_S, NULL, 0, outbuf, sizeof(outbuf)); + + /* Finalize output */ + uint32_t output = nu_get32_be(outbuf); + return output; +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetPCLK0Freq_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 4); + + uint32_t output = CLK_GetPCLK0Freq(); + nu_set32_be(out_vec->base, output); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetPCLK1Freq_S(void) +{ + /* Set up output parameter for NSC call */ + uint8_t outbuf[4]; + + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_GetPCLK1Freq_S, NULL, 0, outbuf, sizeof(outbuf)); + + /* Finalize output */ + uint32_t output = nu_get32_be(outbuf); + return output; +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetPCLK1Freq_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 4); + + uint32_t output = CLK_GetPCLK1Freq(); + nu_set32_be(out_vec->base, output); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetCPUFreq_S(void) +{ + /* Set up output parameter for NSC call */ + uint8_t outbuf[4]; + + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_GetCPUFreq_S, NULL, 0, outbuf, sizeof(outbuf)); + + /* Finalize output */ + uint32_t output = nu_get32_be(outbuf); + return output; +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetCPUFreq_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 4); + + uint32_t output = CLK_GetCPUFreq(); + nu_set32_be(out_vec->base, output); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetPLLClockFreq_S(void) +{ + /* Set up output parameter for NSC call */ + uint8_t outbuf[4]; + + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_GetPLLClockFreq_S, NULL, 0, outbuf, sizeof(outbuf)); + + /* Finalize output */ + uint32_t output = nu_get32_be(outbuf); + return output; +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetPLLClockFreq_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 4); + + uint32_t output = CLK_GetPLLClockFreq(); + nu_set32_be(out_vec->base, output); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetModuleClockSource_S(uint32_t u32ModuleIndex) +{ + /* Set up input parameter for NSC call */ + uint8_t inbuf[4]; + nu_set32_be(inbuf, u32ModuleIndex); + + /* Set up output parameter for NSC call */ + uint8_t outbuf[4]; + + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_GetModuleClockSource_S, inbuf, sizeof(inbuf), outbuf, sizeof(outbuf)); + + /* Finalize output */ + uint32_t output = nu_get32_be(outbuf); + return output; +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetModuleClockSource_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(4, 4); + + uint32_t u32ModuleIndex = nu_get32_be(in_vec->base); + uint32_t output = CLK_GetModuleClockSource(u32ModuleIndex); + nu_set32_be(out_vec->base, output); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetModuleClockDivider_S(uint32_t u32ModuleIndex) +{ + /* Set up input parameter for NSC call */ + uint8_t inbuf[4]; + nu_set32_be(inbuf, u32ModuleIndex); + + /* Set up output parameter for NSC call */ + uint8_t outbuf[4]; + + /* Invoke NSC function */ + PLAT_NSC_CALL(CLK_GetModuleClockDivider_S, inbuf, sizeof(inbuf), outbuf, sizeof(outbuf)); + + /* Finalize output */ + uint32_t output = nu_get32_be(outbuf); + return output; +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetModuleClockDivider_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(4, 4); + + uint32_t u32ModuleIndex = nu_get32_be(in_vec->base); + uint32_t output = CLK_GetModuleClockDivider(u32ModuleIndex); + nu_set32_be(out_vec->base, output); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_Open_S(S_RTC_TIME_DATA_T_PTR sPt) +{ + /* Invoke NSC function */ + PLAT_NSC_CALL(RTC_Open_S, sPt, (sPt ? sizeof(S_RTC_TIME_DATA_T) : 0), NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_Open_S) +{ + /* Check parameter validity */ + if (!in_vec) { + RTC_Open(NULL); + } else if (in_vec->base && in_vec->len == sizeof(S_RTC_TIME_DATA_T)) { + S_RTC_TIME_DATA_T sPt; + memcpy(&sPt, in_vec->base, sizeof(S_RTC_TIME_DATA_T)); + RTC_Open(&sPt); + } else { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_Close_S(void) +{ + /* Invoke NSC function */ + PLAT_NSC_CALL(RTC_Close_S, NULL, 0, NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_Close_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 0); + + RTC_Close(); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_WaitAccessEnable_S(void) +{ + /* On M2354, RTC_WaitAccessEnable() is unnecessary and is not provided by BSP. + * Provide a dummy one to make code consistent. */ +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_WaitAccessEnable_S) +{ + /* On M2354, RTC_WaitAccessEnable() is unnecessary and is not provided by BSP. + * Provide a dummy one to make code consistent. */ + + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 0); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_GetDateAndTime_S(S_RTC_TIME_DATA_T_PTR sPt) +{ + /* Invoke NSC function */ + PLAT_NSC_CALL(RTC_GetDateAndTime_S, NULL, 0, sPt, sizeof(S_RTC_TIME_DATA_T)); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_GetDateAndTime_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, sizeof(S_RTC_TIME_DATA_T)); + + S_RTC_TIME_DATA_T sPt; + RTC_GetDateAndTime(&sPt); + memcpy(out_vec->base, &sPt, sizeof(S_RTC_TIME_DATA_T)); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_GetAlarmDateAndTime_S(S_RTC_TIME_DATA_T_PTR sPt) +{ + /* Invoke NSC function */ + PLAT_NSC_CALL(RTC_GetAlarmDateAndTime_S, NULL, 0, sPt, sizeof(S_RTC_TIME_DATA_T)); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_GetAlarmDateAndTime_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, sizeof(S_RTC_TIME_DATA_T)); + + S_RTC_TIME_DATA_T sPt; + RTC_GetAlarmDateAndTime(&sPt); + memcpy(out_vec->base, &sPt, sizeof(S_RTC_TIME_DATA_T)); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_SetDateAndTime_S(S_RTC_TIME_DATA_T_PTR sPt) +{ + /* Invoke NSC function */ + PLAT_NSC_CALL(RTC_SetDateAndTime_S, sPt, sizeof(S_RTC_TIME_DATA_T), NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_SetDateAndTime_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(sizeof(S_RTC_TIME_DATA_T), 0); + + S_RTC_TIME_DATA_T sPt; + memcpy(&sPt, in_vec->base, sizeof(S_RTC_TIME_DATA_T)); + RTC_SetDateAndTime(&sPt); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_SetAlarmDateAndTime_S(S_RTC_TIME_DATA_T_PTR sPt) +{ + /* Invoke NSC function */ + PLAT_NSC_CALL(RTC_SetAlarmDateAndTime_S, sPt, sizeof(S_RTC_TIME_DATA_T), NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_SetAlarmDateAndTime_S) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(sizeof(S_RTC_TIME_DATA_T), 0); + + S_RTC_TIME_DATA_T sPt; + memcpy(&sPt, in_vec->base, sizeof(S_RTC_TIME_DATA_T)); + RTC_SetAlarmDateAndTime(&sPt); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void nu_pin_function_s(uint32_t port_index, uint32_t pin_index, uint32_t data) +{ + /* Set up input parameter for NSC call */ + uint8_t inbuf[12]; + nu_set32_be(inbuf, port_index); + nu_set32_be(inbuf + 4, pin_index); + nu_set32_be(inbuf + 8, data); + + /* Invoke NSC function */ + PLAT_NSC_CALL(nu_pin_function_s, inbuf, sizeof(inbuf), NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(nu_pin_function_s) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(12, 0); + + uint32_t port_index = nu_get32_be(in_vec->base); + uint32_t pin_index = nu_get32_be(((const uint8_t *) in_vec->base) + 4); + uint32_t data = nu_get32_be(((const uint8_t *) in_vec->base) + 8); + + /* Guard access to secure GPIO from non-secure domain */ + if (!nu_check_gpio_ns(port_index, pin_index)) { + return TFM_PLATFORM_ERR_INVALID_PARAM; + } + + __IO uint32_t *GPx_MFPx = ((__IO uint32_t *) &SYS->GPA_MFPL) + port_index * 2 + (pin_index / 8); + uint32_t MFP_Msk = NU_MFP_MSK(pin_index); + + // E.g.: SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0MFP_SC0_CD ; + *GPx_MFPx = (*GPx_MFPx & (~MFP_Msk)) | data; + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void nu_idle_s(void) +{ + /* We should have had default (shallow) sleep/idle mode configuration guaranteed by SPE. + * Just call WFI in NSPE. This is to remove SPE/NSPE boundary latency (200us) and to pass + * (shallow) sleep-related tests. */ + __WFI(); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(nu_idle_s) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 0); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void nu_powerdown_s(void) +{ + /* Invoke NSC function */ + PLAT_NSC_CALL(nu_powerdown_s, NULL, 0, NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(nu_powerdown_s) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 0); + + /* Switch to deep sleep/power-down mode configuration */ + SYS_UnlockReg(); + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + CLK->PWRCTL |= CLK_PWRCTL_PDEN_Msk; + SYS_LockReg(); + + /* Enter deep sleep/power-down mode */ + __WFI(); + + /* Switch back to default (shallow) sleep/idle mode configuration to enable entering + * (shallow) sleep/idle mode without crossing SPE/NSPE boundary */ + SYS_UnlockReg(); + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk; + SYS_LockReg(); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t nu_rtc_read_spare_register_s(uint32_t reg_num) +{ + /* Set up input parameter for NSC call */ + uint8_t inbuf[4]; + nu_set32_be(inbuf, reg_num); + + /* Set up output parameter for NSC call */ + uint8_t outbuf[4]; + + /* Invoke NSC function */ + PLAT_NSC_CALL(nu_rtc_read_spare_register_s, inbuf, sizeof(inbuf), outbuf, sizeof(outbuf)); + + /* Finalize output */ + int32_t reg_val = nu_get32_be(outbuf); + return reg_val; +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(nu_rtc_read_spare_register_s) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(4, 4); + + uint32_t reg_num = nu_get32_be(in_vec->base); + RTC_WaitAccessEnable(); + RTC_EnableSpareAccess(); + RTC_WaitAccessEnable(); + uint32_t reg_val = RTC_READ_SPARE_REGISTER(RTC_S, reg_num); + nu_set32_be(out_vec->base, reg_val); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void nu_rtc_write_spare_register_s(uint32_t reg_num, uint32_t reg_val) +{ + /* Set up input parameter for NSC call */ + uint8_t inbuf[8]; + nu_set32_be(inbuf, reg_num); + nu_set32_be(inbuf + 4, reg_val); + + /* Invoke NSC function */ + PLAT_NSC_CALL(nu_rtc_write_spare_register_s, inbuf, sizeof(inbuf), NULL, 0); +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(nu_rtc_write_spare_register_s) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(8, 0); + + uint32_t reg_num = nu_get32_be(in_vec->base); + uint32_t reg_val = nu_get32_be(((const uint8_t *) in_vec->base) + 4); + RTC_WaitAccessEnable(); + RTC_EnableSpareAccess(); + RTC_WaitAccessEnable(); + RTC_WRITE_SPARE_REGISTER(RTC_S, reg_num, reg_val); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +int32_t nu_rtc_isenabled_s(void) +{ + /* Set up output parameter for NSC call */ + uint8_t outbuf[4]; + + /* Invoke NSC function */ + PLAT_NSC_CALL(nu_rtc_isenabled_s, NULL, 0, outbuf, sizeof(outbuf)); + + /* Finalize output */ + int32_t enabled = nu_get32_be(outbuf); + return enabled; +} +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(nu_rtc_isenabled_s) +{ + /* Check parameter validity */ + NU_CHK_PARAM_VAL(0, 4); + + // To access (RTC) registers, clock must be enabled first. + // For TZ, with RTC being secure, we needn't call the secure gateway versions. + CLK_EnableModuleClock(RTC_MODULE); + + CLK_SetModuleClock(RTC_MODULE, RTC_LXTCTL_RTCCKSEL_LXT, 0); + + // NOTE: Check RTC Init Active flag to support crossing reset cycle. + int32_t enabled = !! (RTC_S->INIT & RTC_INIT_ACTIVE_Msk); + nu_set32_be(out_vec->base, enabled); + + return TFM_PLATFORM_ERR_SUCCESS; +} +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/platform_extra_secure.h b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/platform_extra_secure.h new file mode 100644 index 0000000000..00bd958e2c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/platform_extra_secure.h @@ -0,0 +1,350 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef PLATFORM_EXTRA_SECURE_H +#define PLATFORM_EXTRA_SECURE_H + +#include +#include + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +typedef void * S_RTC_TIME_DATA_T_PTR; +#elif NU_TFM_PLAT_IOCTL_S +#include "tfm_platform_system.h" +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/* NOTE: This header file is designed to be across Mbed OS and TF-M. */ + +/* Helper to define request code with platform extra secure function */ +#define NU_PLAT_XTRA_SEC_REQ(SEC_FUNC) \ + NU_PLAT_XTRA_SEC_REQ_##SEC_FUNC + +/* Table of request code with platform extra secure function */ +typedef enum { + /* Prefix with "SYS" */ + NU_PLAT_XTRA_SEC_REQ(SYS_ResetModule_S) = 0, + NU_PLAT_XTRA_SEC_REQ(SYS_LockReg_S), + NU_PLAT_XTRA_SEC_REQ(SYS_UnlockReg_S), + + /* Prefix with "CLK" */ + NU_PLAT_XTRA_SEC_REQ(CLK_SetModuleClock_S), + NU_PLAT_XTRA_SEC_REQ(CLK_EnableModuleClock_S), + NU_PLAT_XTRA_SEC_REQ(CLK_DisableModuleClock_S), + NU_PLAT_XTRA_SEC_REQ(CLK_Idle_S), + NU_PLAT_XTRA_SEC_REQ(CLK_PowerDown_S), + NU_PLAT_XTRA_SEC_REQ(CLK_GetHXTFreq_S), + NU_PLAT_XTRA_SEC_REQ(CLK_GetLXTFreq_S), + NU_PLAT_XTRA_SEC_REQ(CLK_GetHCLKFreq_S), + NU_PLAT_XTRA_SEC_REQ(CLK_GetPCLK0Freq_S), + NU_PLAT_XTRA_SEC_REQ(CLK_GetPCLK1Freq_S), + NU_PLAT_XTRA_SEC_REQ(CLK_GetCPUFreq_S), + NU_PLAT_XTRA_SEC_REQ(CLK_GetPLLClockFreq_S), + NU_PLAT_XTRA_SEC_REQ(CLK_GetModuleClockSource_S), + NU_PLAT_XTRA_SEC_REQ(CLK_GetModuleClockDivider_S), + + /* Prefix with "RTC" */ + NU_PLAT_XTRA_SEC_REQ(RTC_Open_S), + NU_PLAT_XTRA_SEC_REQ(RTC_Close_S), + NU_PLAT_XTRA_SEC_REQ(RTC_WaitAccessEnable_S), + NU_PLAT_XTRA_SEC_REQ(RTC_GetDateAndTime_S), + NU_PLAT_XTRA_SEC_REQ(RTC_GetAlarmDateAndTime_S), + NU_PLAT_XTRA_SEC_REQ(RTC_SetDateAndTime_S), + NU_PLAT_XTRA_SEC_REQ(RTC_SetAlarmDateAndTime_S), + + /* Prefix with "nu" */ + NU_PLAT_XTRA_SEC_REQ(nu_pin_function_s), + NU_PLAT_XTRA_SEC_REQ(nu_idle_s), + NU_PLAT_XTRA_SEC_REQ(nu_powerdown_s), + NU_PLAT_XTRA_SEC_REQ(nu_rtc_read_spare_register_s), + NU_PLAT_XTRA_SEC_REQ(nu_rtc_write_spare_register_s), + NU_PLAT_XTRA_SEC_REQ(nu_rtc_isenabled_s), + + /* Max request code, plays as number of valid request code */ + NU_PLAT_XTRA_SEC_REQ(MAX), + + /* Following entry is only to ensure the error code of int size */ + NU_PLAT_XTRA_SEC_REQ(INT_SIZE) = INT_MAX +} nu_plat_req_t; + +#if NU_TFM_PLAT_IOCTL_S + +#define NU_PLAT_XTRA_SEC_HDLR(SEC_FUN) \ + enum tfm_platform_err_t SEC_FUN(psa_invec *in_vec, psa_outvec *out_vec) + +#endif + +/* Secure SYS_ResetModule + * + * Guard access to secure module from non-secure domain before SYS_ResetModule. + * Its synopsis is the same as SYS_ResetModule. + */ +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void SYS_ResetModule_S(uint32_t u32ModuleIndex); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(SYS_ResetModule_S); +#endif + +/* Secure SYS_LockReg + * + * Guard access to secure module from non-secure domain before SYS_LockReg. + * Its synopsis is the same as SYS_LockReg. + */ +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void SYS_LockReg_S(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(SYS_LockReg_S); +#endif + +/* Secure SYS_UnlockReg + * + * Guard access to secure module from non-secure domain before SYS_UnlockReg. + * Its synopsis is the same as SYS_UnlockReg. + */ +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void SYS_UnlockReg_S(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(SYS_UnlockReg_S); +#endif + +/* Secure CLK_SetModuleClock + * + * Guard access to secure module from non-secure domain before CLK_SetModuleClock. + * Its synopsis is the same as CLK_SetModuleClock. + */ +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void CLK_SetModuleClock_S(uint32_t u32ModuleIndex, uint32_t u32ClkSrc, uint32_t u32ClkDiv); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_SetModuleClock_S); +#endif + +/* Secure CLK_EnableModuleClock + * + * Guard access to secure module from non-secure domain before CLK_EnableModuleClock. + * Its synopsis is the same as CLK_EnableModuleClock. + */ +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void CLK_EnableModuleClock_S(uint32_t u32ModuleIndex); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_EnableModuleClock_S); +#endif + +/* Secure CLK_DisableModuleClock + * + * Guard access to secure module from non-secure domain before CLK_DisableModuleClock. + * Its synopsis is the same as CLK_DisableModuleClock. + */ + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void CLK_DisableModuleClock_S(uint32_t u32ModuleIndex); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_DisableModuleClock_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void CLK_Idle_S(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_Idle_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void CLK_PowerDown_S(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_PowerDown_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetHXTFreq_S(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetHXTFreq_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetLXTFreq_S(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetLXTFreq_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetHCLKFreq_S(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetHCLKFreq_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetPCLK0Freq_S(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetPCLK0Freq_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetPCLK1Freq_S(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetPCLK1Freq_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetCPUFreq_S(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetCPUFreq_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetPLLClockFreq_S(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetPLLClockFreq_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetModuleClockSource_S(uint32_t u32ModuleIndex); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetModuleClockSource_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t CLK_GetModuleClockDivider_S(uint32_t u32ModuleIndex); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(CLK_GetModuleClockDivider_S); +#endif + +/* NOTE: time_t + * + * time_t may be defined to int32_t/int64_t dependent on compilers. For binary-compatible + * among compilers, we must replace time_t with int32_t/int64_t explicitly in rtc secure + * functions. We determine to choose int64_t rather than int32_t to avoid 'Year 2038 problem'. + */ + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_Open_S(S_RTC_TIME_DATA_T_PTR sPt); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_Open_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_Close_S(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_Close_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_WaitAccessEnable_S(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_WaitAccessEnable_S); + +__STATIC_INLINE void RTC_WaitAccessEnable(void) +{ + /* On M2354, RTC_WaitAccessEnable() is unnecessary and is not provided by BSP. + * Provide a dummy one to make code consistent. */ +} +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_GetDateAndTime_S(S_RTC_TIME_DATA_T_PTR sPt); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_GetDateAndTime_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_GetAlarmDateAndTime_S(S_RTC_TIME_DATA_T_PTR sPt); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_GetAlarmDateAndTime_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_SetDateAndTime_S(S_RTC_TIME_DATA_T_PTR sPt); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_SetDateAndTime_S); +#endif + +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void RTC_SetAlarmDateAndTime_S(S_RTC_TIME_DATA_T_PTR sPt); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(RTC_SetAlarmDateAndTime_S); +#endif + +/* Secure pin_function + * + * Guard access to secure GPIO from non-secure domain. + */ +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void nu_pin_function_s(uint32_t port_index, uint32_t pin_index, uint32_t data); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(nu_pin_function_s); +#endif + +/* Secure sequence of SYS_UnlockReg > CLK_Idle > SYS_LockReg */ +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void nu_idle_s(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(nu_idle_s); +#endif + +/* Secure sequence of SYS_UnlockReg > CLK_PowerDown > SYS_LockReg */ +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void nu_powerdown_s(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(nu_powerdown_s); +#endif + +/* Read RTC spare register + * + * Secure sequence: + * RTC_WaitAccessEnable(); + * RTC_EnableSpareAccess(); + * RTC_WaitAccessEnable(); + * RTC_READ_SPARE_REGISTER(RTC, reg_num); + */ +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +uint32_t nu_rtc_read_spare_register_s(uint32_t reg_num); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(nu_rtc_read_spare_register_s); +#endif + +/* Write RTC spare register + * + * Secure sequence: + * RTC_WaitAccessEnable(); + * RTC_EnableSpareAccess(); + * RTC_WaitAccessEnable(); + * RTC_WRITE_SPARE_REGISTER(RTC, reg_num, reg_val); + */ +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +void nu_rtc_write_spare_register_s(uint32_t reg_num, uint32_t reg_val); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(nu_rtc_write_spare_register_s); +#endif + +/* Secure rtc_isenabled + * + * Its synopsis is the same as normal version except change of return/argument type for + * binary-compatible across compilers. + */ +#if __MBED__ || NU_TFM_PLAT_IOCTL_NS +int32_t nu_rtc_isenabled_s(void); +#elif NU_TFM_PLAT_IOCTL_S +NU_PLAT_XTRA_SEC_HDLR(nu_rtc_isenabled_s); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/platform_extra_secure_compat.c b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/platform_extra_secure_compat.c new file mode 100644 index 0000000000..ce5db00d5a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/platform_extra_secure_compat.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "cmsis.h" + +/* BSP driver call no-suffix '_S'/'_s' version. To not change them, provide no-suffix version. */ + +uint32_t CLK_GetHXTFreq(void) +{ + return CLK_GetHXTFreq_S(); +} + +uint32_t CLK_GetLXTFreq(void) +{ + return CLK_GetLXTFreq_S(); +} + +uint32_t CLK_GetHCLKFreq(void) +{ + return CLK_GetHCLKFreq_S(); +} + +uint32_t CLK_GetPCLK0Freq(void) +{ + return CLK_GetPCLK0Freq_S(); +} + +uint32_t CLK_GetPCLK1Freq(void) +{ + return CLK_GetPCLK1Freq_S(); +} + +uint32_t CLK_GetCPUFreq(void) +{ + return CLK_GetCPUFreq_S(); +} + +uint32_t CLK_GetPLLClockFreq(void) +{ + return CLK_GetPLLClockFreq_S(); +} + +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIndex) +{ + return CLK_GetModuleClockSource_S(u32ModuleIndex); +} + +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIndex) +{ + return CLK_GetModuleClockDivider_S(u32ModuleIndex); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/tfm_ns_interface.c b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/tfm_ns_interface.c new file mode 100644 index 0000000000..c5f999f509 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/tfm_ns_interface.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include + +#include "cmsis.h" +#include "tfm_api.h" +#include "tfm_ns_interface.h" +#include "cmsis_os2.h" + +#include "mbed_critical.h" +#include "mbed_assert.h" +#include "mbed_error.h" + +/* Approach to serialization of NS secure calls required by TF-M secure world + * + * Default implementation of NS interface uses mutex to meet the requirement, + * but it cannot support NS secure call in interrupt-disabled context. Instead, + * in this override, NS secure call is guaranteed to be non-preemptive during + * this period by locking kernel scheduler. Apparently, this approach has one + * weakness: all other threads are also locked during this period. Until there's + * a better approach coming out, we can just use this expedient one. + * + * For the 'lock kernel scheduler' approach to work thoroughly, we must also + * address some side issues: + * + * - Prohibit NS secure call from ISR except SVC, so non-preemptive doesn't break. + * - Allow NS secure call in SVC context because it is synchronous. Here, we lock + * interrupt instead of kernel scheduler because svcRtxKernelLock()/svcRtxKernelRestoreLock(...) + * are inaccessible outside rtx_kernel.c. Currently, this is rare case and would cause + * little trouble (see known paths below). + * - Call into secure world straight in interrupt-disabled context. When in + * interrupt-disabled context, NS secure call is guaranteed to be non-preemptive + * naturally. + * - Call into secure world straight at pre-rtos stage. When at pre-rtos stage, + * NS secure call is guaranteed to be non-preemptive naturally. + * - osKernelLock() will error when kernel state is 'osKernelSuspended'. Address + * it separately. Known path of NS secure call when kernel state is 'osKernelSuspended': + * - default idle thread > osKernelSuspend() > lp_ticker_init > SYS_ResetModule_S/ + * CLK_SetModuleClock_S/CLK_EnableModuleClock_S + * + * Known paths of NS secure call in interrupt-disabled context: + * - mbed-os/platform/mbed_sleep_manager.c > sleep_manager_sleep_auto > + * hal_sleep/hal_deepsleep > nu_idle_s/nu_powerdown_s + * - mbed-os/hal/LowPowerTickerWrapper.cpp > LowPowerTickerWrapper::init > + * lp_ticker_init > SYS_ResetModule_S/CLK_SetModuleClock_S/CLK_EnableModuleClock_S + * - mbed-os/platform/mbed_board.c > mbed_die > nu_pin_function_s + * - mbed-os-tests-mbed_hal-rtc > rtc_write_read_test > rtc_write > + * CLK_IsRTCClockEnabled_S + * + * Known paths of NS secure call in SVC context: + * - In tickless mode, osKernelStart > svcRtxKernelStart > OS_Tick_Enable > + * us_ticker_init/lp_ticker_init > SYS_ResetModule_S/CLK_SetModuleClock_S/ + * CLK_EnableModuleClock_S + */ + +struct ns_interface_state +{ + bool init; // Initialized or not +}; + +static struct ns_interface_state ns_interface = { + .init = false +}; + +/* Override tfm_ns_interface_dispatch(...) */ +int32_t tfm_ns_interface_dispatch(veneer_fn fn, + uint32_t arg0, uint32_t arg1, + uint32_t arg2, uint32_t arg3) +{ + /* Prohibit NS secure call from ISR except SVC, so non-preemptive doesn't break */ + uint32_t ipsr = __get_IPSR(); + if (ipsr == 11U) { + /* Allow NS secure call in SVC context because it is synchronous. Here, + * we lock interrupt instead of kernel scheduler because svcRtxKernelLock()/ + * svcRtxKernelRestoreLock(...) are inaccessible outside rtx_kernel.c. */ + core_util_critical_section_enter(); + int32_t result = fn(arg0, arg1, arg2, arg3); + core_util_critical_section_exit(); + + return result; + } else if (ipsr) { + MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_KERNEL, MBED_ERROR_CODE_PROHIBITED_IN_ISR_CONTEXT), "Prohibited in ISR context", (uintptr_t) fn); + } + + /* Call into secure world straight in interrupt-disabled context because + * NS secure call is non-preemptive naturally */ + if (!core_util_are_interrupts_enabled()) { + return fn(arg0, arg1, arg2, arg3); + } + + osKernelState_t kernel_state = osKernelGetState(); + + /* Call into secure world straight at pre-rtos stage because NS secure + * call is non-preemptive naturally */ + if (kernel_state == osKernelInactive || kernel_state == osKernelReady) { + return fn(arg0, arg1, arg2, arg3); + } + + /* osKernelLock() will error when kernel state is 'osKernelSuspended'. Address + * it separately. */ + if (kernel_state == osKernelSuspended) { + return fn(arg0, arg1, arg2, arg3); + } else if (kernel_state == osKernelError) { + MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_KERNEL, MBED_ERROR_CODE_UNKNOWN), "RTX kernel state error", (uintptr_t) fn); + } + + /* Lock kernel scheduler and save previous lock state for restore */ + int32_t lock_state = osKernelLock(); + if (lock_state == osError) { + MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_KERNEL, MBED_ERROR_CODE_UNKNOWN), "Unknown RTX error", (uintptr_t) fn); + } + MBED_ASSERT(lock_state >= 0); + + /* NS secure call is non-preemptive because kernel scheduler is locked */ + int32_t result = fn(arg0, arg1, arg2, arg3); + + /* Restore previous lock state */ + lock_state = osKernelRestoreLock(lock_state); + if (lock_state == osError) { + MBED_ERROR1(MBED_MAKE_ERROR(MBED_MODULE_KERNEL, MBED_ERROR_CODE_UNKNOWN), "Unknown RTX error", (uintptr_t) fn); + } + MBED_ASSERT(lock_state >= 0); + + return result; +} + +/* Override tfm_ns_lock_init() + * + * Since Mbed OS 6, this function is called at the very start of main thread (mbed_start), + * not before scheduler is started, so we cannot use this call to distinguish pre-rtos stage + * and rtos stage in tfm_ns_interface_dispatch() as before. Instead, we use osKernelGetState() + * to check if scheduler has started. + */ +enum tfm_status_e tfm_ns_interface_init(void) +{ + if (!ns_interface.init) { + ns_interface.init = true; + } + + return TFM_SUCCESS; +} diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/analogin_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/analogin_api.c new file mode 100644 index 0000000000..6b380a6901 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/analogin_api.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogin_api.h" + +#if DEVICE_ANALOGIN + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "nu_modutil.h" + +static uint32_t eadc_modinit_mask = 0; + +static const struct nu_modinit_s adc_modinit_tab[] = { + {ADC_0_0, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_1, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_2, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_3, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_4, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_5, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_6, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_7, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_8, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_9, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_10, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_11, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_12, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_13, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_14, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, + {ADC_0_15, EADC_MODULE, 0, CLK_CLKDIV0_EADC(8), EADC_RST, EADC0_IRQn, NULL}, +}; + +void analogin_init(analogin_t *obj, PinName pin) +{ + obj->adc = (ADCName) pinmap_peripheral(pin, PinMap_ADC); + MBED_ASSERT(obj->adc != (ADCName) NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->adc); + + obj->pin = pin; + + // Wire pinout + pinmap_pinout(pin, PinMap_ADC); + + EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc); + + // NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module. + if (! eadc_modinit_mask) { + /* Select IP clock source + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + /* Enable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_EnableModuleClock_S(modinit->clkidx); + + /* Reset module + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule_S(modinit->rsetidx); + + // Set the ADC internal sampling time, input mode as single-end and enable the A/D converter + EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END); + } + + uint32_t chn = NU_MODSUBINDEX(obj->adc); + + // Configure the sample module Nmod for analog input channel Nch and software trigger source + EADC_ConfigSampleModule(eadc_base, chn, EADC_SOFTWARE_TRIGGER, chn); + + eadc_modinit_mask |= 1 << chn; +} + +void analogin_free(analogin_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab); + MBED_ASSERT(modinit->modname == (int) obj->adc); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->adc); + + EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc); + + /* Channel-level windup from here */ + + /* Mark channel free */ + eadc_modinit_mask &= ~(1 << chn); + + /* Module-level windup from here */ + + /* See analogin_init() for reason */ + if (! eadc_modinit_mask) { + /* Disable EADC module */ + EADC_Close(eadc_base); + + /* Disable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_DisableModuleClock_S(modinit->clkidx); + } + + /* Free up pins */ + gpio_set(obj->pin); + obj->pin = NC; +} + +uint16_t analogin_read_u16(analogin_t *obj) +{ + EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc); + uint32_t chn = NU_MODSUBINDEX(obj->adc); + + EADC_START_CONV(eadc_base, 1 << chn); + while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != ((uint32_t) (1 << chn))); + uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn); + // Just 12 bits are effective. Convert to 16 bits. + // conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0 + // conv_res_16: b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8 + uint16_t conv_res_16 = (conv_res_12 << 4) | (conv_res_12 >> 8); + + return conv_res_16; +} + +float analogin_read(analogin_t *obj) +{ + uint16_t value = analogin_read_u16(obj); + return (float) value * (1.0f / (float) 0xFFFF); +} + +const PinMap *analogin_pinmap() +{ + return PinMap_ADC; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/analogout_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/analogout_api.c new file mode 100644 index 0000000000..a57a1db829 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/analogout_api.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "analogout_api.h" + +#if DEVICE_ANALOGOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "nu_modutil.h" + +/* Maximum DAC modules */ +#define NU_DACMOD_MAXNUM 2 +/* Maximum DAC channels per module */ +#define NU_DACCHN_MAXNUM 1 + +static uint32_t dac_modinit_mask[NU_DACMOD_MAXNUM]; + +static const struct nu_modinit_s dac_modinit_tab[] = { + {DAC_0_0, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL}, + {DAC_1_0, DAC_MODULE, 0, 0, DAC_RST, DAC_IRQn, NULL} +}; + +void analogout_init(dac_t *obj, PinName pin) +{ + obj->dac = (DACName) pinmap_peripheral(pin, PinMap_DAC); + MBED_ASSERT(obj->dac != (DACName) NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + obj->pin = pin; + + /* Wire pinout */ + pinmap_pinout(pin, PinMap_DAC); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Module-level setup from here */ + + /* DAC0/DAC1 are designed to share the same RESET/clock/IRQ for group + * function. So we: + * + * 1. Go to setup flow (analogout_init()) only when none of DAC0/DAC1 + * channels are activated. + * 2. Go to windup flow (analogout_free()) only when all DAC0/DAC1 + * channels are deactivated. + */ + if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) { + /* Select IP clock source and clock divider + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + /* Enable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_EnableModuleClock_S(modinit->clkidx); + + /* Reset IP + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule_S(modinit->rsetidx); + + /* The conversion settling time is 8us when 12-bit input code transition from + * lowest code (0x000) to highest code (0xFFF). */ + DAC_SetDelayTime(dac_base, 8); + + /* Configure DAT data format to left-aligned + * Effective 12-bits are aligned to left of 16-bit DAC_DAT. */ + DAC_ENABLE_LEFT_ALIGN(dac_base); + } + + /* Channel-level setup from here: */ + + /* Set the software trigger, enable DAC event trigger mode and enable D/A converter */ + DAC_Open(dac_base, chn, DAC_SOFTWARE_TRIGGER); + + + + /* Mark channel allocated */ + dac_modinit_mask[modidx] |= 1 << chn; +} + +void analogout_free(dac_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->dac, dac_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == obj->dac); + + /* Module index */ + uint32_t modidx = NU_MODINDEX(obj->dac); + MBED_ASSERT(modidx < NU_DACMOD_MAXNUM); + + /* Module subindex (aka channel) */ + uint32_t chn = NU_MODSUBINDEX(obj->dac); + MBED_ASSERT(chn < NU_DACCHN_MAXNUM); + + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + + /* Channel-level windup from here */ + + /* Mark channel free */ + dac_modinit_mask[modidx] &= ~(1 << chn); + + /* Close channel */ + DAC_Close(dac_base, chn); + + /* Module-level windup from here: */ + + /* See analogout_init() for reason */ + if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) { + + /* Disable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_DisableModuleClock_S(modinit->clkidx); + } + + /* Free up pin */ + gpio_set(obj->pin); + obj->pin = NC; +} + +void analogout_write(dac_t *obj, float value) +{ + if (value <= 0.0f) { + analogout_write_u16(obj, 0); + } else if (value >= 1.0f) { + analogout_write_u16(obj, 0xFFFF); + } else { + analogout_write_u16(obj, (uint16_t) (value * ((float) 0xFFFF))); + } +} + +void analogout_write_u16(dac_t *obj, uint16_t value) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + uint32_t chn = NU_MODSUBINDEX(obj->dac); + + /* We should have configured DAC data format to left-aligned */ + MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk); + DAC_WRITE_DATA(dac_base, chn, value); + + /* Clear the DAC conversion complete finish flag for safe */ + DAC_CLR_INT_FLAG(dac_base, chn); + + /* Start A/D conversion */ + DAC_START_CONV(dac_base); + + /* Wait for completed */ + while (DAC_IS_BUSY(dac_base, chn)); +} + +float analogout_read(dac_t *obj) +{ + uint32_t value = analogout_read_u16(obj); + return (float) value * (1.0f / (float) 0xFFFF); +} + +uint16_t analogout_read_u16(dac_t *obj) +{ + DAC_T *dac_base = (DAC_T *) NU_MODBASE(obj->dac); + uint32_t chn = NU_MODSUBINDEX(obj->dac); + + /* We should have configured DAC data format to left-aligned */ + MBED_ASSERT(dac_base->CTL & DAC_CTL_LALIGN_Msk); + uint16_t dat12_4 = DAC_READ_DATA(dac_base, chn); + /* Just 12 bits are effective. Convert to 16 bits. + * + * dat12_4 : b11b10b9b8 b7b6b5b4 b3b2b1b0 0000 + * dat16 : b11b10b9b8 b7b6b5b4 b3b2b1b0 b11b10b9b8 + */ + uint16_t dat16 = (dat12_4 & 0xFFF0) | (dat12_4 >> 12); + + return dat16; +} + +const PinMap *analogout_pinmap() +{ + return PinMap_DAC; +} + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32WB/flash_data.h b/targets/TARGET_NUVOTON/TARGET_M2354/device.h similarity index 66% rename from targets/TARGET_STM/TARGET_STM32WB/flash_data.h rename to targets/TARGET_NUVOTON/TARGET_M2354/device.h index f8c376b02f..bd261fd8ae 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/flash_data.h +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device.h @@ -1,5 +1,6 @@ -/* mbed Microcontroller Library - * Copyright (c) 2019 STMicroelectronics +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,17 +16,11 @@ * limitations under the License. */ -#ifndef MBED_FLASH_DATA_H -#define MBED_FLASH_DATA_H +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H -#if DEVICE_FLASH +#define DEVICE_ID_LENGTH 24 -#ifdef FLASH_SIZE -#undef FLASH_SIZE -#endif - -// Only the first the application side is accessible. -#define FLASH_SIZE ((uint32_t)0xC0000) // 768 Kbytes +#include "objects.h" #endif -#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/M2354.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/M2354.h new file mode 100644 index 0000000000..4f2274d879 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/M2354.h @@ -0,0 +1,1105 @@ +/**************************************************************************//** + * @file M2354.h + * @version V3.0 + * @brief Peripheral Access Layer Header File + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ + +/** + \mainpage Introduction + * + * + * This user manual describes the usage of M2354 device driver + * + * Disclaimer + * + * The Software is furnished "AS IS", without warranty as to performance or results, and + * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all + * warranties, express, implied or otherwise, with regard to the Software, its use, or + * operation, including without limitation any and all warranties of merchantability, fitness + * for a particular purpose, and non-infringement of intellectual property rights. + * + * Copyright Notice + * + * Copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. + */ + + +#ifndef __M2354_H__ +#define __M2354_H__ + +/*=============================================================================*/ +typedef volatile unsigned char vu8; +typedef volatile unsigned int vu32; +typedef volatile unsigned short vu16; +#define M8(adr) (*((vu8 *) (adr))) +#define M16(adr) (*((vu16 *) (adr))) +#define M32(adr) (*((vu32 *) (adr))) + +#define outpw(port,value) (*((volatile unsigned int *)(port))=(value)) +#define inpw(port) ((*((volatile unsigned int *)(port)))) +#define outpb(port,value) (*((volatile unsigned char *)(port))=(value)) +#define inpb(port) ((*((volatile unsigned char *)(port)))) +#define outps(port,value) (*((volatile unsigned short *)(port))=(value)) +#define inps(port) ((*((volatile unsigned short *)(port)))) + +#define outp32(port,value) (*((volatile unsigned int *)(port))=(value)) +#define inp32(port) ((*((volatile unsigned int *)(port)))) +#define outp8(port,value) (*((volatile unsigned char *)(port))=(value)) +#define inp8(port) ((*((volatile unsigned char *)(port)))) +#define outp16(port,value) (*((volatile unsigned short *)(port))=(value)) +#define inp16(port) ((*((volatile unsigned short *)(port)))) + + +#define E_SUCCESS 0 + +#define TRUE (1L) +#define FALSE (0L) + +/* Not used on Mbed OS. Remove to get around name conflict */ +//#define ENABLE 1 +//#define DISABLE 0 + +/* Bit Mask Definitions */ +#define BIT0 0x00000001UL +#define BIT1 0x00000002UL +#define BIT2 0x00000004UL +#define BIT3 0x00000008UL +#define BIT4 0x00000010UL +#define BIT5 0x00000020UL +#define BIT6 0x00000040UL +#define BIT7 0x00000080UL +#define BIT8 0x00000100UL +#define BIT9 0x00000200UL +#define BIT10 0x00000400UL +#define BIT11 0x00000800UL +#define BIT12 0x00001000UL +#define BIT13 0x00002000UL +#define BIT14 0x00004000UL +#define BIT15 0x00008000UL +#define BIT16 0x00010000UL +#define BIT17 0x00020000UL +#define BIT18 0x00040000UL +#define BIT19 0x00080000UL +#define BIT20 0x00100000UL +#define BIT21 0x00200000UL +#define BIT22 0x00400000UL +#define BIT23 0x00800000UL +#define BIT24 0x01000000UL +#define BIT25 0x02000000UL +#define BIT26 0x04000000UL +#define BIT27 0x08000000UL +#define BIT28 0x10000000UL +#define BIT29 0x20000000UL +#define BIT30 0x40000000UL +#define BIT31 0x80000000UL + + +/* Byte Mask Definitions */ +#define BYTE0_Msk (0x000000FFUL) +#define BYTE1_Msk (0x0000FF00UL) +#define BYTE2_Msk (0x00FF0000UL) +#define BYTE3_Msk (0xFF000000UL) + +#define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ +#define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8UL) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ +#define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16UL) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ +#define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24UL) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ + + + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup CMSIS_Device CMSIS Definitions + Configuration of the Cortex-M23 Processor and Core Peripherals + @{ +*/ + + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +/** + * @details Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible. + */ +typedef enum IRQn +{ + /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M23 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M23 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M23 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M23 System Tick Interrupt */ + + /****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/ + + BOD_IRQn = 0, /*!< Brown Out detection Interrupt */ + IRC_IRQn = 1, /*!< Internal RC Interrupt */ + PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */ + RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */ + CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */ + ISP_IRQn = 5, /*!< FMC ISP Interrupt */ + RTC_IRQn = 6, /*!< Real Time Clock Interrupt */ + RTC_TAMPER_IRQn = 7, /*!< RTC Tamper detection Interrupt */ + WDT_IRQn = 8, /*!< Watchdog Timer Interrupt */ + WWDT_IRQn = 9, /*!< Window Watchdog Timer Interrupt */ + EINT0_IRQn = 10, /*!< External Input 0 Interrupt */ + EINT1_IRQn = 11, /*!< External Input 1 Interrupt */ + EINT2_IRQn = 12, /*!< External Input 2 Interrupt */ + EINT3_IRQn = 13, /*!< External Input 3 Interrupt */ + EINT4_IRQn = 14, /*!< External Input 4 Interrupt */ + EINT5_IRQn = 15, /*!< External Input 5 Interrupt */ + GPA_IRQn = 16, /*!< GPIO Port A Interrupt */ + GPB_IRQn = 17, /*!< GPIO Port B Interrupt */ + GPC_IRQn = 18, /*!< GPIO Port C Interrupt */ + GPD_IRQn = 19, /*!< GPIO Port D Interrupt */ + GPE_IRQn = 20, /*!< GPIO Port E Interrupt */ + GPF_IRQn = 21, /*!< GPIO Port F Interrupt */ + QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */ + SPI0_IRQn = 23, /*!< SPI0 Interrupt */ + BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */ + EPWM0_P0_IRQn = 25, /*!< EPWM0P0 Interrupt */ + EPWM0_P1_IRQn = 26, /*!< EPWM0P1 Interrupt */ + EPWM0_P2_IRQn = 27, /*!< EPWM0P2 Interrupt */ + BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */ + EPWM1_P0_IRQn = 29, /*!< EPWM1P0 Interrupt */ + EPWM1_P1_IRQn = 30, /*!< EPWM1P1 Interrupt */ + EPWM1_P2_IRQn = 31, /*!< EPWM1P2 Interrupt */ + TMR0_IRQn = 32, /*!< Timer 0 Interrupt */ + TMR1_IRQn = 33, /*!< Timer 1 Interrupt */ + TMR2_IRQn = 34, /*!< Timer 2 Interrupt */ + TMR3_IRQn = 35, /*!< Timer 3 Interrupt */ + UART0_IRQn = 36, /*!< UART 0 Interrupt */ + UART1_IRQn = 37, /*!< UART 1 Interrupt */ + I2C0_IRQn = 38, /*!< I2C 0 Interrupt */ + I2C1_IRQn = 39, /*!< I2C 1 Interrupt */ + PDMA0_IRQn = 40, /*!< Peripheral DMA 0 Interrupt */ + DAC_IRQn = 41, /*!< DAC Interrupt */ + EADC0_IRQn = 42, /*!< EADC Source 0 Interrupt */ + EADC1_IRQn = 43, /*!< EADC Source 1 Interrupt */ + ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */ + EADC2_IRQn = 46, /*!< EADC Source 2 Interrupt */ + EADC3_IRQn = 47, /*!< EADC Source 3 Interrupt */ + UART2_IRQn = 48, /*!< UART2 Interrupt */ + UART3_IRQn = 49, /*!< UART3 Interrupt */ + SPI1_IRQn = 51, /*!< SPI1 Interrupt */ + SPI2_IRQn = 52, /*!< SPI2 Interrupt */ + USBD_IRQn = 53, /*!< USB device Interrupt */ + USBH_IRQn = 54, /*!< USB host Interrupt */ + USBOTG_IRQn = 55, /*!< USB OTG Interrupt */ + CAN0_IRQn = 56, /*!< CAN0 Interrupt */ + SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */ + SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */ + SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */ + SPI3_IRQn = 62, /*!< SPI3 Interrupt */ + SDH0_IRQn = 64, /*!< SDH0 Interrupt */ + I2S0_IRQn = 68, /*!< I2S0 Interrupt */ + CRPT_IRQn = 71, /*!< CRPT Interrupt */ + GPG_IRQn = 72, /*!< GPIO Port G Interrupt */ + EINT6_IRQn = 73, /*!< External Input 6 Interrupt */ + UART4_IRQn = 74, /*!< UART4 Interrupt */ + UART5_IRQn = 75, /*!< UART5 Interrupt */ + USCI0_IRQn = 76, /*!< USCI0 Interrupt */ + USCI1_IRQn = 77, /*!< USCI1 Interrupt */ + BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */ + BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */ + I2C2_IRQn = 82, /*!< I2C2 Interrupt */ + QEI0_IRQn = 84, /*!< QEI0 Interrupt */ + QEI1_IRQn = 85, /*!< QEI1 Interrupt */ + ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */ + ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */ + GPH_IRQn = 88, /*!< GPIO Port H Interrupt */ + EINT7_IRQn = 89, /*!< External Input 7 Interrupt */ + PDMA1_IRQn = 98, /*!< Peripheral DMA 1 Interrupt */ + SCU_IRQn = 99, /*!< SCU Interrupt */ + LCD_IRQn = 100, /*!< LCD interrupt */ + TRNG_IRQn = 101, /*!< TRNG interrupt */ + KS_IRQn = 109, /*!< Key Store interrupt */ + TAMPER_IRQn = 110, /*!< TAMPER interrupt */ + EWDT_IRQn = 111, /*!< Extra Watchdog Timer interrupt */ + EWWDT_IRQn = 112, /*!< Extra Window Watchdog Timer interrupt */ + NS_ISP_IRQn = 113, /*!< Non-secure FMC ISP interrupt */ + TMR4_IRQn = 114, /*!< Timer 4 Interrupt */ + TMR5_IRQn = 115, /*!< Timer 5 Interrupt */ + + +} IRQn_Type; + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) +#pragma push +#pragma anon_unions +#elif defined (__ICCARM__) +#pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wc11-extensions" +#pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined (__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning 586 +#elif defined (__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + + +/* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */ +#define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */ +#define __SAU_PRESENT 1U /* SAU present */ +#define __SAUREGION_PRESENT 1U /* SAU present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define USE_ASSERT 0U /* Define to use Assert function or not */ + +/**@}*/ /* end of group CMSIS */ + +#include "core_cm23.h" /* Processor and core peripherals */ +#include "system_M2354.h" /* System Header */ +#include "partition_M2354.h" + +/** + * Initialize the system clock + * + * @brief Setup the micro controller system + * Initialize the PLL and update the SystemFrequency variable + */ +extern void SystemInit(void); + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + + +#include "acmp_reg.h" +#include "bpwm_reg.h" +#include "can_reg.h" +#include "clk_reg.h" +#include "crc_reg.h" +#include "dac_reg.h" +#include "eadc_reg.h" +#include "ebi_reg.h" +#include "ecap_reg.h" +#include "fmc_reg.h" +#include "gpio_reg.h" +#include "hdiv_reg.h" +#include "i2c_reg.h" +#include "i2s_reg.h" +#include "pdma_reg.h" +#include "epwm_reg.h" +#include "qei_reg.h" +#include "rtc_reg.h" +#include "sc_reg.h" +#include "scu_reg.h" +#include "sdh_reg.h" +#include "qspi_reg.h" +#include "spi_reg.h" +#include "sys_reg.h" +#include "timer_reg.h" +#include "trng_reg.h" +#include "uart_reg.h" +#include "ui2c_reg.h" +#include "usbh_reg.h" +#include "usbd_reg.h" +#include "otg_reg.h" +#include "crpt_reg.h" +#include "uspi_reg.h" +#include "uuart_reg.h" +#include "wdt_reg.h" +#include "wwdt_reg.h" +#include "keystore_reg.h" +#include "tamper_reg.h" +#include "lcd_reg.h" +#include "ewdt_reg.h" +#include "ewwdt_reg.h" + + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/** @addtogroup PERIPHERAL_BASE Peripheral Memory Base + Memory Mapped Structure for Series Peripheral + @{ + */ + + +/* Peripheral and SRAM base address */ +#define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ +#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ +#define NS_OFFSET (0x10000000UL) + +/* Peripheral memory map */ +#define AHBPERIPH_BASE PERIPH_BASE +#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000UL) + +/*!< AHB peripherals */ +#define SYS_BASE (AHBPERIPH_BASE + 0x00000UL) +#define CLK_BASE (AHBPERIPH_BASE + 0x00200UL) +#define INT_BASE (AHBPERIPH_BASE + 0x00300UL) +#define GPIO_BASE (AHBPERIPH_BASE + 0x04000UL) +#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL) +#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL) +#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL) +#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL) +#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL) +#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL) +#define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL) +#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL) +#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL) +#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL) +#define PDMA0_BASE (AHBPERIPH_BASE + 0x08000UL) +#define PDMA1_BASE (AHBPERIPH_BASE + 0x18000UL) +#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL) +#define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL) +#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL) +#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL) +#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL) +#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL) +#define CRPT_BASE (AHBPERIPH_BASE + 0x32000UL) +#define SCU_BASE (AHBPERIPH_BASE + 0x2F000UL) +#define FVC_BASE (AHBPERIPH_BASE + 0x2F500UL) +#define DPM_BASE (AHBPERIPH_BASE + 0x2F600UL) +#define PLM_BASE (AHBPERIPH_BASE + 0x2F700UL) + +#define BTF_BASE (AHBPERIPH_BASE + 0x2F800UL) + +/*!< APB peripherals */ +#define WDT_BASE (APBPERIPH_BASE + 0x00000UL) +#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL) +#define RTC_BASE (APBPERIPH_BASE + 0x01000UL) +#define EADC_BASE (APBPERIPH_BASE + 0x03000UL) +#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL) +#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL) +#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL) +#define I2S0_BASE (APBPERIPH_BASE + 0x08000UL) +#define OTG_BASE (APBPERIPH_BASE + 0x0D000UL) +#define TMR01_BASE (APBPERIPH_BASE + 0x10000UL) +#define TMR23_BASE (APBPERIPH_BASE + 0x11000UL) +#define TMR45_BASE (APBPERIPH_BASE + 0x12000UL) +#define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL) +#define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL) +#define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL) +#define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL) +#define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL) +#define SPI0_BASE (APBPERIPH_BASE + 0x21000UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x22000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x23000UL) +#define SPI3_BASE (APBPERIPH_BASE + 0x24000UL) +#define UART0_BASE (APBPERIPH_BASE + 0x30000UL) +#define UART0_BASE (APBPERIPH_BASE + 0x30000UL) +#define UART1_BASE (APBPERIPH_BASE + 0x31000UL) +#define UART2_BASE (APBPERIPH_BASE + 0x32000UL) +#define UART3_BASE (APBPERIPH_BASE + 0x33000UL) +#define UART4_BASE (APBPERIPH_BASE + 0x34000UL) +#define UART5_BASE (APBPERIPH_BASE + 0x35000UL) +#define I2C0_BASE (APBPERIPH_BASE + 0x40000UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x41000UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x42000UL) +#define SC0_BASE (APBPERIPH_BASE + 0x50000UL) +#define SC1_BASE (APBPERIPH_BASE + 0x51000UL) +#define SC2_BASE (APBPERIPH_BASE + 0x52000UL) +#define CAN0_BASE (APBPERIPH_BASE + 0x60000UL) +#define QEI0_BASE (APBPERIPH_BASE + 0x70000UL) +#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL) +#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL) +#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL) +#define TRNG_BASE (APBPERIPH_BASE + 0x79000UL) +#define USBD_BASE (APBPERIPH_BASE + 0x80000UL) +#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL) +#define USCI1_BASE (APBPERIPH_BASE + 0x91000UL) + +#define EWDT_BASE (APBPERIPH_BASE + 0x02000UL) +#define EWWDT_BASE (APBPERIPH_BASE + 0x02100UL) + + +#define KS_BASE (AHBPERIPH_BASE + 0x35000UL) +#define TAMPER_BASE (AHBPERIPH_BASE + 0xBD000UL) +#define LCD_BASE (AHBPERIPH_BASE + 0xBB000UL) + + + +/**@}*/ /* PERIPHERAL */ + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ + +/** @addtogroup PMODULE Peripheral Pointer + The Declaration of Peripheral Pointer + @{ + */ + +/** @addtogroup PMODULE_S Secure Peripheral Pointer + The Declaration of Secure Peripheral Pointer + @{ +*/ + +#define PA_S ((GPIO_T *) GPIOA_BASE) /*!< GPIO PORTA Pointer */ +#define PB_S ((GPIO_T *) GPIOB_BASE) /*!< GPIO PORTB Pointer */ +#define PC_S ((GPIO_T *) GPIOC_BASE) /*!< GPIO PORTC Pointer */ +#define PD_S ((GPIO_T *) GPIOD_BASE) /*!< GPIO PORTD Pointer */ +#define PE_S ((GPIO_T *) GPIOE_BASE) /*!< GPIO PORTE Pointer */ +#define PF_S ((GPIO_T *) GPIOF_BASE) /*!< GPIO PORTF Pointer */ +#define PG_S ((GPIO_T *) GPIOG_BASE) /*!< GPIO PORTG Pointer */ +#define PH_S ((GPIO_T *) GPIOH_BASE) /*!< GPIO PORTH Pointer */ + +#define UART0_S ((UART_T *) UART0_BASE) /*!< UART0 Pointer */ +#define UART1_S ((UART_T *) UART1_BASE) /*!< UART1 Pointer */ +#define UART2_S ((UART_T *) UART2_BASE) /*!< UART2 Pointer */ +#define UART3_S ((UART_T *) UART3_BASE) /*!< UART3 Pointer */ +#define UART4_S ((UART_T *) UART4_BASE) /*!< UART4 Pointer */ +#define UART5_S ((UART_T *) UART5_BASE) /*!< UART5 Pointer */ + + +#define TIMER0_S ((TIMER_T *) TMR01_BASE) /*!< TIMER0 Pointer */ +#define TIMER1_S ((TIMER_T *) (TMR01_BASE + 0x100UL)) /*!< TIMER1 Pointer */ +#define TIMER2_S ((TIMER_T *) TMR23_BASE) /*!< TIMER2 Pointer */ +#define TIMER3_S ((TIMER_T *) (TMR23_BASE + 0x100UL)) /*!< TIMER3 Pointer */ +#define TIMER4_S ((TIMER_T *) TMR45_BASE) /*!< TIMER4 Pointer */ +#define TIMER5_S ((TIMER_T *) (TMR45_BASE + 0x100UL)) /*!< TIMER5 Pointer */ + +#define WDT_S ((WDT_T *) WDT_BASE) /*!< Watch Dog Timer Pointer */ + +#define WWDT_S ((WWDT_T *) WWDT_BASE) /*!< Window Watch Dog Timer Pointer */ + +#define QSPI0_S ((QSPI_T *) QSPI0_BASE) /*!< QSPI0 Pointer */ +#define SPI0_S ((SPI_T *) SPI0_BASE) /*!< SPI0 Pointer */ +#define SPI1_S ((SPI_T *) SPI1_BASE) /*!< SPI1 Pointer */ +#define SPI2_S ((SPI_T *) SPI2_BASE) /*!< SPI2 Pointer */ +#define SPI3_S ((SPI_T *) SPI3_BASE) /*!< SPI3 Pointer */ + +#define I2S0_S ((I2S_T *) I2S0_BASE) /*!< I2S0 Pointer */ + +#define I2C0_S ((I2C_T *) I2C0_BASE) /*!< I2C0 Pointer */ +#define I2C1_S ((I2C_T *) I2C1_BASE) /*!< I2C1 Pointer */ +#define I2C2_S ((I2C_T *) I2C2_BASE) /*!< I2C1 Pointer */ + +#define QEI0_S ((QEI_T *) QEI0_BASE) /*!< QEI0 Pointer */ +#define QEI1_S ((QEI_T *) QEI1_BASE) /*!< QEI1 Pointer */ + +#define RTC_S ((RTC_T *) RTC_BASE) /*!< RTC Pointer */ + +#define ACMP01_S ((ACMP_T *) ACMP01_BASE) /*!< ACMP01 Pointer */ + +#define CLK_S ((CLK_T *) CLK_BASE) /*!< System Clock Controller Pointer */ + +#define DAC0_S ((DAC_T *) DAC0_BASE) /*!< DAC0 Pointer */ +#define DAC1_S ((DAC_T *) DAC1_BASE) /*!< DAC1 Pointer */ + +#define EADC_S ((EADC_T *) EADC_BASE) /*!< EADC Pointer */ + +#define SYS_S ((SYS_T *) SYS_BASE) /*!< System Global Controller Pointer */ + +#define SYSINT_S ((SYS_INT_T *) INT_BASE) /*!< Interrupt Source Controller Pointer */ + +#define FMC_S ((FMC_T *) FMC_BASE) /*!< Flash Memory Controller */ + +#define SDH0_S ((SDH_T *) SDH0_BASE) + +#define CRPT_S ((CRPT_T *) CRPT_BASE) /*!< Crypto Accelerator Pointer */ +#define TRNG_S ((TRNG_T *)TRNG_BASE) /*!< True Random Number Pointer */ + +#define BPWM0_S ((BPWM_T *) BPWM0_BASE) /*!< BPWM0 Pointer */ +#define BPWM1_S ((BPWM_T *) BPWM1_BASE) /*!< BPWM1 Pointer */ + +#define EPWM0_S ((EPWM_T *) EPWM0_BASE) /*!< EPWM0 Pointer */ +#define EPWM1_S ((EPWM_T *) EPWM1_BASE) /*!< EPWM1 Pointer */ + +#define SC0_S ((SC_T *) SC0_BASE) /*!< SC0 Pointer */ +#define SC1_S ((SC_T *) SC1_BASE) /*!< SC1 Pointer */ +#define SC2_S ((SC_T *) SC2_BASE) /*!< SC2 Pointer */ + +#define EBI_S ((EBI_T *) EBI_BASE) /*!< EBI Pointer */ + +#define CRC_S ((CRC_T *) CRC_BASE) /*!< CRC Pointer */ + +#define USBD_S ((USBD_T *) USBD_BASE) /*!< USB Device Pointer */ +#define USBH_S ((USBH_T *) USBH_BASE) /*!< USBH Pointer */ +#define OTG_S ((OTG_T *) OTG_BASE) /*!< OTG Pointer */ + +#define PDMA0_S ((PDMA_T *) PDMA0_BASE) /*!< PDMA0 Pointer */ +#define PDMA1_S ((PDMA_T *) PDMA1_BASE) /*!< PDMA1 Pointer */ + +#define UI2C0_S ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Pointer */ +#define UI2C1_S ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Pointer */ + +#define USPI0_S ((USPI_T *) USCI0_BASE) /*!< USPI0 Pointer */ +#define USPI1_S ((USPI_T *) USCI1_BASE) /*!< USPI1 Pointer */ + +#define UUART0_S ((UUART_T *) USCI0_BASE) /*!< UUART0 Pointer */ +#define UUART1_S ((UUART_T *) USCI1_BASE) /*!< UUART1 Pointer */ + +#define SCU_S ((SCU_T *) SCU_BASE) /*!< SCU Pointer */ +#define ECAP0_S ((ECAP_T *) ECAP0_BASE) /*!< ECAP0 Pointer */ +#define ECAP1_S ((ECAP_T *) ECAP1_BASE) /*!< ECAP1 Pointer */ + +#define CAN0_S ((CAN_T *)CAN0_BASE) /*!< CAN0 Pointer */ + +#define KS_S ((KS_T *)KS_BASE) /*!< Key Store Pointer */ +#define TAMPER_S ((TAMPER_T *)TAMPER_BASE) /*!< TAMPER Pointer */ +#define LCD_S ((LCD_T *)LCD_BASE) /*!< LCD Pointer */ + +#define EWDT_S ((EWDT_T *) EWDT_BASE) /*!< Extra Watch Dog Timer Pointer */ + +#define EWWDT_S ((EWWDT_T *) EWWDT_BASE) /*!< Extra Window Watch Dog Timer Pointer*/ + +#define FVC_S ((FVC_T *) FVC_BASE) +#define DPM_S ((DPM_T *) DPM_BASE) +#define PLM_S ((PLM_T *) PLM_BASE) + + + +/**@}*/ /* end of group PMODULE_S */ + +/** @addtogroup PMODULE_NS Non-secure Peripheral Pointer + The Declaration of Non-secure Peripheral Pointer + @{ +*/ + + +#define PA_NS ((GPIO_T *) (GPIOA_BASE+NS_OFFSET)) /*!< GPIO PORTA Pointer */ +#define PB_NS ((GPIO_T *) (GPIOB_BASE+NS_OFFSET)) /*!< GPIO PORTB Pointer */ +#define PC_NS ((GPIO_T *) (GPIOC_BASE+NS_OFFSET)) /*!< GPIO PORTC Pointer */ +#define PD_NS ((GPIO_T *) (GPIOD_BASE+NS_OFFSET)) /*!< GPIO PORTD Pointer */ +#define PE_NS ((GPIO_T *) (GPIOE_BASE+NS_OFFSET)) /*!< GPIO PORTE Pointer */ +#define PF_NS ((GPIO_T *) (GPIOF_BASE+NS_OFFSET)) /*!< GPIO PORTF Pointer */ +#define PG_NS ((GPIO_T *) (GPIOG_BASE+NS_OFFSET)) /*!< GPIO PORTG Pointer */ +#define PH_NS ((GPIO_T *) (GPIOH_BASE+NS_OFFSET)) /*!< GPIO PORTH Pointer */ +#define UART0_NS ((UART_T *) (UART0_BASE+NS_OFFSET)) /*!< UART0 Pointer */ +#define UART1_NS ((UART_T *) (UART1_BASE+NS_OFFSET)) /*!< UART1 Pointer */ +#define UART2_NS ((UART_T *) (UART2_BASE+NS_OFFSET)) /*!< UART2 Pointer */ +#define UART3_NS ((UART_T *) (UART3_BASE+NS_OFFSET)) /*!< UART3 Pointer */ +#define UART4_NS ((UART_T *) (UART4_BASE+NS_OFFSET)) /*!< UART4 Pointer */ +#define UART5_NS ((UART_T *) (UART5_BASE+NS_OFFSET)) /*!< UART5 Pointer */ +#define TIMER2_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET)) /*!< TIMER2 Pointer */ +#define TIMER3_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET+0x100UL)) /*!< TIMER3 Pointer */ +#define TIMER4_NS ((TIMER_T *) (TMR45_BASE+NS_OFFSET)) /*!< TIMER4 Pointer */ +#define TIMER5_NS ((TIMER_T *) (TMR45_BASE+NS_OFFSET+0x100UL)) /*!< TIMER5 Pointer */ +#define QSPI0_NS ((QSPI_T *) (QSPI0_BASE+NS_OFFSET)) /*!< QSPI0 Pointer */ +#define SPI0_NS ((SPI_T *) (SPI0_BASE+NS_OFFSET)) /*!< SPI0 Pointer */ +#define SPI1_NS ((SPI_T *) (SPI1_BASE+NS_OFFSET)) /*!< SPI1 Pointer */ +#define SPI2_NS ((SPI_T *) (SPI2_BASE+NS_OFFSET)) /*!< SPI2 Pointer */ +#define SPI3_NS ((SPI_T *) (SPI3_BASE+NS_OFFSET)) /*!< SPI3 Pointer */ +#define I2S0_NS ((I2S_T *) (I2S0_BASE+NS_OFFSET)) /*!< I2S0 Pointer */ +#define I2C0_NS ((I2C_T *) (I2C0_BASE+NS_OFFSET)) /*!< I2C0 Pointer */ +#define I2C1_NS ((I2C_T *) (I2C1_BASE+NS_OFFSET)) /*!< I2C1 Pointer */ +#define I2C2_NS ((I2C_T *) (I2C2_BASE+NS_OFFSET)) /*!< I2C1 Pointer */ +#define QEI0_NS ((QEI_T *) (QEI0_BASE+NS_OFFSET)) /*!< QEI0 Pointer */ +#define QEI1_NS ((QEI_T *) (QEI1_BASE+NS_OFFSET)) /*!< QEI1 Pointer */ +#define ACMP01_NS ((ACMP_T *) (ACMP01_BASE+NS_OFFSET)) /*!< ACMP01 Pointer */ +#define DAC0_NS ((DAC_T *) (DAC0_BASE+NS_OFFSET)) /*!< DAC0 Pointer */ +#define DAC1_NS ((DAC_T *) (DAC1_BASE+NS_OFFSET)) /*!< DAC1 Pointer */ +#define EADC_NS ((EADC_T *) (EADC_BASE+NS_OFFSET)) /*!< EADC Pointer */ +#define SDH0_NS ((SDH_T *) (SDH0_BASE +NS_OFFSET)) +#define CRPT_NS ((CRPT_T *) (CRPT_BASE +NS_OFFSET)) +#define TRNG_NS ((TRNG_T *) (TRNG_BASE +NS_OFFSET)) /*!< Random Number Generator Pointer */ +#define BPWM0_NS ((BPWM_T *) (BPWM0_BASE+NS_OFFSET)) /*!< BPWM0 Pointer */ +#define BPWM1_NS ((BPWM_T *) (BPWM1_BASE+NS_OFFSET)) /*!< BPWM1 Pointer */ +#define EPWM0_NS ((EPWM_T *) (EPWM0_BASE+NS_OFFSET)) /*!< EPWM0 Pointer */ +#define EPWM1_NS ((EPWM_T *) (EPWM1_BASE+NS_OFFSET)) /*!< EPWM1 Pointer */ +#define SC0_NS ((SC_T *) (SC0_BASE +NS_OFFSET)) /*!< SC0 Pointer */ +#define SC1_NS ((SC_T *) (SC1_BASE +NS_OFFSET)) /*!< SC1 Pointer */ +#define SC2_NS ((SC_T *) (SC2_BASE +NS_OFFSET)) /*!< SC2 Pointer */ +#define EBI_NS ((EBI_T *) (EBI_BASE +NS_OFFSET)) /*!< EBI Pointer */ +#define CRC_NS ((CRC_T *) (CRC_BASE +NS_OFFSET)) /*!< CRC Pointer */ +#define USBD_NS ((USBD_T *) (USBD_BASE +NS_OFFSET)) /*!< USB Device Pointer */ +#define USBH_NS ((USBH_T *) (USBH_BASE +NS_OFFSET)) /*!< USBH Pointer */ +#define OTG_NS ((OTG_T *) (OTG_BASE +NS_OFFSET)) /*!< OTG Pointer */ +#define PDMA1_NS ((PDMA_T *) (PDMA1_BASE +NS_OFFSET)) /*!< PDMA1 Pointer */ +#define UI2C0_NS ((UI2C_T *) (USCI0_BASE +NS_OFFSET)) /*!< UI2C0 Pointer */ +#define UI2C1_NS ((UI2C_T *) (USCI1_BASE +NS_OFFSET)) /*!< UI2C1 Pointer */ +#define USPI0_NS ((USPI_T *) (USCI0_BASE +NS_OFFSET)) /*!< USPI0 Pointer */ +#define USPI1_NS ((USPI_T *) (USCI1_BASE +NS_OFFSET)) /*!< USPI1 Pointer */ +#define UUART0_NS ((UUART_T *) (USCI0_BASE+NS_OFFSET)) /*!< UUART0 Pointer */ +#define UUART1_NS ((UUART_T *) (USCI1_BASE+NS_OFFSET)) /*!< UUART1 Pointer */ +#define SCU_NS ((SCU_T *) (SCU_BASE +NS_OFFSET)) /*!< SCU Pointer */ +#define ECAP0_NS ((ECAP_T *) (ECAP0_BASE+NS_OFFSET)) /*!< ECAP0 Pointer */ +#define ECAP1_NS ((ECAP_T *) (ECAP1_BASE+NS_OFFSET)) /*!< ECAP1 Pointer */ +#define CAN0_NS ((CAN_T *) (CAN0_BASE +NS_OFFSET)) /*!< CAN0 Pointer */ + +#define EWDT_NS ((EWDT_T *) (EWDT_BASE+NS_OFFSET)) /*!< Extra Watch Dog Timer Pointer */ + +#define EWWDT_NS ((EWWDT_T *) (EWWDT_BASE+NS_OFFSET)) /*!< Extra Window Watch Dog Timer Pointer*/ + + +#define LCD_NS ((LCD_T *)(LCD_BASE+NS_OFFSET)) /*!< LCD Pointer */ +#define DPM_NS ((DPM_T *)(DPM_BASE+NS_OFFSET)) +#define FMC_NS ((FMC_T *)(FMC_BASE+NS_OFFSET)) /*!< Flash Memory Controller */ +#define SYS_NS ((SYS_T *)(SYS_BASE+NS_OFFSET)) +#define CLK_NS ((CLK_T *)(CLK_BASE+NS_OFFSET)) + + +/**@}*/ /* end of group PMODULE_NS */ + +/** @addtogroup PMODULE_SNS Peripheral Pointer + The Declaration of Peripheral Pointer + @{ +*/ + +/* Always Secure Modules */ +#define SYS SYS_S +#define CLK CLK_S +#define FMC FMC_S +#define SCU SCU_S +#define FVC FVC_S +#define PLM PLM_S +#define DPM DPM_S +#define PDMA0 PDMA0_S +#define WDT WDT_S +#define WWDT WWDT_S +#define TIMER0 TIMER0_S +#define TIMER1 TIMER1_S +#define RTC RTC_S +#define KS KS_S +#define TAMPER TAMPER_S + +#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT9 ) +# define USBH USBH_NS +#else +# define USBH USBH_S +#endif + +#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT13) +# define SDH0 SDH0_NS +#else +# define SDH0 SDH0_S +#endif + +#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT16) +# define EBI EBI_NS +#else +# define EBI EBI_S +#endif + + +#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT24) +# define PDMA1 PDMA1_NS +#else +# define PDMA1 PDMA1_S +#endif + +#if defined (SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & BIT17) +# define CRC CRC_NS +#else +# define CRC CRC_S +#endif + +#if defined (SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & BIT18) +# define CRPT CRPT_NS +#else +# define CRPT CRPT_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT2 ) +# define EWDT EWDT_NS +# define EWWDT EWWDT_NS +#else +# define EWDT EWDT_S +# define EWWDT EWWDT_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 ) +# define EADC EADC_NS +#else +# define EADC EADC_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 ) +# define EADC EADC_NS +#else +# define EADC EADC_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 ) +# define EADC EADC_NS +#else +# define EADC EADC_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 ) +# define EADC EADC_NS +#else +# define EADC EADC_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT5 ) +# define ACMP01 ACMP01_NS +#else +# define ACMP01 ACMP01_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT7 ) +# define DAC0 DAC0_NS +# define DAC1 DAC1_NS +#else +# define DAC0 DAC0_S +# define DAC1 DAC1_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT8 ) +# define I2S0 I2S0_NS +#else +# define I2S0 I2S0_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT13) +# define OTG OTG_NS +#else +# define OTG OTG_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT17) +# define TIMER2 TIMER2_NS +# define TIMER3 TIMER3_NS +#else +# define TIMER2 TIMER2_S +# define TIMER3 TIMER3_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT18) +# define TIMER4 TIMER4_NS +# define TIMER5 TIMER5_NS +#else +# define TIMER4 TIMER4_S +# define TIMER5 TIMER5_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT24) +# define EPWM0 EPWM0_NS +#else +# define EPWM0 EPWM0_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT24) +# define EPWM0 EPWM0_NS +#else +# define EPWM0 EPWM0_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT24) +# define EPWM0 EPWM0_NS +#else +# define EPWM0 EPWM0_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT25) +# define EPWM1 EPWM1_NS +#else +# define EPWM1 EPWM1_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT25) +# define EPWM1 EPWM1_NS +#else +# define EPWM1 EPWM1_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT25) +# define EPWM1 EPWM1_NS +#else +# define EPWM1 EPWM1_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT26) +# define BPWM0 BPWM0_NS +#else +# define BPWM0 BPWM0_S +#endif + +#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT27) +# define BPWM1 BPWM1_NS +#else +# define BPWM1 BPWM1_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT0 ) +# define QSPI0 QSPI0_NS +#else +# define QSPI0 QSPI0_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT1 ) +# define SPI0 SPI0_NS +#else +# define SPI0 SPI0_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT2 ) +# define SPI1 SPI1_NS +#else +# define SPI1 SPI1_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT3 ) +# define SPI2 SPI2_NS +#else +# define SPI2 SPI2_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT4 ) +# define SPI3 SPI3_NS +#else +# define SPI3 SPI3_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT16) +# define UART0 UART0_NS +#else +# define UART0 UART0_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT17) +# define UART1 UART1_NS +#else +# define UART1 UART1_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT18) +# define UART2 UART2_NS +#else +# define UART2 UART2_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT19) +# define UART3 UART3_NS +#else +# define UART3 UART3_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT20) +# define UART4 UART4_NS +#else +# define UART4 UART4_S +#endif + +#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT21) +# define UART5 UART5_NS +#else +# define UART5 UART5_S +#endif + +#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT0 ) +# define I2C0 I2C0_NS +#else +# define I2C0 I2C0_S +#endif + +#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT1 ) +# define I2C1 I2C1_NS +#else +# define I2C1 I2C1_S +#endif + +#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT2 ) +# define I2C2 I2C2_NS +#else +# define I2C2 I2C2_S +#endif + +#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT16) +# define SC0 SC0_NS +#else +# define SC0 SC0_S +#endif + +#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT17) +# define SC1 SC1_NS +#else +# define SC1 SC1_S +#endif + +#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT18) +# define SC2 SC2_NS +#else +# define SC2 SC2_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT0 ) +# define CAN0 CAN0_NS +#else +# define CAN0 CAN0_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT16) +# define QEI0 QEI0_NS +#else +# define QEI0 QEI0_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT17) +# define QEI1 QEI1_NS +#else +# define QEI1 QEI1_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT20) +# define ECAP0 ECAP0_NS +#else +# define ECAP0 ECAP0_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT21) +# define ECAP1 ECAP1_NS +#else +# define ECAP1 ECAP1_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT25) +# define TRNG TRNG_NS +#else +# define TRNG TRNG_S +#endif + +#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT27) +# define LCD LCD_NS +#else +# define LCD LCD_S +#endif + +#if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT0 ) +# define USBD USBD_NS +#else +# define USBD USBD_S +#endif + +#if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT16) +# define USCI0 USCI0_NS +# define UI2C0 UI2C0_NS +# define USPI0 USPI0_NS +# define UUART0 UUART0_NS + +#else +# define USCI0 USCI0_S +# define UI2C0 UI2C0_S +# define USPI0 USPI0_S +# define UUART0 UUART0_S + +#endif + +#if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT17) +# define USCI1 USCI1_NS +# define USPI1 USPI1_NS +# define UI2C1 UI2C1_NS +# define UUART1 UUART1_NS + +#else +# define USCI1 USCI1_S +# define USPI1 USPI1_S +# define UI2C1 UI2C1_S +# define UUART1 UUART1_S +#endif + +#define PA ( (__PC() & NS_OFFSET) ? PA_NS : PA_S) +#define PB ( (__PC() & NS_OFFSET) ? PB_NS : PB_S) +#define PC ( (__PC() & NS_OFFSET) ? PC_NS : PC_S) +#define PD ( (__PC() & NS_OFFSET) ? PD_NS : PD_S) +#define PE ( (__PC() & NS_OFFSET) ? PE_NS : PE_S) +#define PF ( (__PC() & NS_OFFSET) ? PF_NS : PF_S) +#define PG ( (__PC() & NS_OFFSET) ? PG_NS : PG_S) +#define PH ( (__PC() & NS_OFFSET) ? PH_NS : PH_S) + +/**@}*/ /* end of group PMODULE_SNS */ + +/**@}*/ /* end of group PMODULE */ + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined (__CC_ARM) +#pragma pop +#elif defined (__ICCARM__) +/* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) +#pragma clang diagnostic pop +#elif defined (__GNUC__) +/* anonymous unions are enabled by default */ +#elif defined (__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined (__TASKING__) +#pragma warning restore +#elif defined (__CSMC__) +/* anonymous unions are enabled by default */ +#else +#warning Not supported compiler type +#endif + +#ifdef __cplusplus +} +#endif + + + +/******************************************************************************/ +/* Peripheral header files */ +/******************************************************************************/ +#include "m2354_sys.h" +#include "m2354_clk.h" +#include "m2354_dac.h" +#include "m2354_eadc.h" +#include "m2354_ebi.h" +#include "m2354_ecap.h" +#include "m2354_fmc.h" +#include "m2354_gpio.h" +#include "m2354_i2c.h" +#include "m2354_i2s.h" +#include "m2354_bpwm.h" +#include "m2354_epwm.h" +#include "m2354_qspi.h" +#include "m2354_spi.h" +#include "m2354_timer.h" +#include "m2354_timer_pwm.h" +#include "m2354_wdt.h" +#include "m2354_wwdt.h" +#include "m2354_rtc.h" +#include "m2354_uart.h" +#include "m2354_acmp.h" +#include "m2354_crc.h" +#include "m2354_usbd.h" +#include "m2354_otg.h" +#include "m2354_pdma.h" +#include "m2354_ebi.h" +#include "m2354_keystore.h" +#include "m2354_crypto.h" +#include "m2354_sc.h" +#include "m2354_scuart.h" +#include "m2354_usci_spi.h" +#include "m2354_usci_uart.h" +#include "m2354_usci_i2c.h" +#include "m2354_sdh.h" +#include "m2354_qei.h" +#include "m2354_can.h" +#include "m2354_scu.h" +#include "m2354_tamper.h" +#include "m2354_rng.h" +#include "m2354_dpm.h" +#include "m2354_fvc.h" +#include "m2354_ewwdt.h" +#include "m2354_ewdt.h" +#include "m2354_plm.h" +#include "m2354_lcd.h" + +#endif /* __M2354_H__ */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/NuMicro.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/NuMicro.h new file mode 100644 index 0000000000..a1130033e0 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/NuMicro.h @@ -0,0 +1,17 @@ +/**************************************************************************//** + * @file NuMicro.h + * @version V1.00 + * @brief NuMicro peripheral access layer header file. + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __NUMICRO_H__ +#define __NUMICRO_H__ + +#include "M2354.h" + +#endif /* __NUMICRO_H__ */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/acmp_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/acmp_reg.h new file mode 100644 index 0000000000..d54afb6545 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/acmp_reg.h @@ -0,0 +1,244 @@ +/**************************************************************************//** + * @file acmp_reg.h + * @version V1.00 + * @brief ACMP register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ACMP_REG_H__ +#define __ACMP_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Analog Comparator Controller -------------------------*/ +/** + @addtogroup ACMP Analog Comparator Controller(ACMP) + Memory Mapped Structure for ACMP Controller + @{ +*/ + +typedef struct +{ + + +/** + * @var ACMP_T::CTL + * Offset: 0x00 Analog Comparator 0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPEN |Comparator Enable Bit + * | | |0 = Comparator 0 Disabled. + * | | |1 = Comparator 0 Enabled. + * |[1] |ACMPIE |Comparator Interrupt Enable Bit + * | | |0 = Comparator 0 interrupt Disabled. + * | | |1 = Comparator 0 interrupt Enabled. + * | | |If WKEN (ACMP_CTL0[16]) is set to 1, the wake-up interrupt function will be enabled as well. + * |[2] |HYSEN |Comparator Hysteresis Enable Bit + * | | |0 = Comparator 0 hysteresis Disabled. + * | | |1 = Comparator 0 hysteresis Enabled. + * | | |Note: If HYSEN = 0, user can adjust HYS by HYSSEL. + * | | |Note: If HYSEN = 1, HYSSEL is invalid. The Hysteresis is fixed to 30mV. + * |[3] |ACMPOINV |Comparator Output Inverse + * | | |0 = Comparator 0 output inverse Disabled. + * | | |1 = Comparator 0 output inverse Enabled. + * |[5:4] |NEGSEL |Comparator Negative Input Selection + * | | |00 = ACMP0_N pin. + * | | |01 = Internal comparator reference voltage (CRV). + * | | |10 = Band-gap voltage. + * | | |11 = DAC output. + * |[7:6] |POSSEL |Comparator Positive Input Selection + * | | |00 = Input from ACMP0_P0. + * | | |01 = Input from ACMP0_P1. + * | | |10 = Input from ACMP0_P2. + * | | |11 = Input from ACMP0_P3. + * |[9:8] |INTPOL |Interrupt Condition Polarity Selection + * | | |ACMPIF0 will be set to 1 when comparator output edge condition is detected. + * | | |00 = Rising edge or falling edge. + * | | |01 = Rising edge. + * | | |10 = Falling edge. + * | | |11 = Reserved. + * |[12] |OUTSEL |Comparator Output Select + * | | |0 = Comparator 0 output to ACMP0_O pin is unfiltered comparator output. + * | | |1 = Comparator 0 output to ACMP0_O pin is from filter output. + * |[15:13] |FILTSEL |Comparator Output Filter Count Selection + * | | |000 = Filter function is Disabled. + * | | |001 = ACMP0 output is sampled 1 consecutive PCLK. + * | | |010 = ACMP0 output is sampled 2 consecutive PCLKs. + * | | |011 = ACMP0 output is sampled 4 consecutive PCLKs. + * | | |100 = ACMP0 output is sampled 8 consecutive PCLKs. + * | | |101 = ACMP0 output is sampled 16 consecutive PCLKs. + * | | |110 = ACMP0 output is sampled 32 consecutive PCLKs. + * | | |111 = ACMP0 output is sampled 64 consecutive PCLKs. + * |[16] |WKEN |Power-down Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[17] |WLATEN |Window Latch Mode Enable Bit + * | | |0 = Window Latch Mode Disabled. + * | | |1 = Window Latch Mode Enabled. + * |[18] |WCMPSEL |Window Compare Mode Selection + * | | |0 = Window Compare Mode Disabled. + * | | |1 = Window Compare Mode is Selected. + * |[25:24] |HYSSEL |Hysteresis Mode Selection + * | | |00 = Hysteresis is 0mV. + * | | |01 = Hysteresis is 10mV. + * | | |10 = Hysteresis is 20mV. + * | | |11 = Hysteresis is 30mV. + * |[29:28] |MODESEL |Propagation Delay Mode Selection + * | | |00 = Max propagation delay is 4.5uS, operation current is 1.2uA. + * | | |01 = Max propagation delay is 2uS, operation current is 3uA. + * | | |10 = Max propagation delay is 600nS, operation current is 10uA. + * | | |11 = Max propagation delay is 200nS, operation current is 75uA. + * @var ACMP_T::STATUS + * Offset: 0x08 Analog Comparator Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACMPIF0 |Comparator 0 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[9:8]) is detected on comparator 0 output + * | | |This will generate an interrupt if ACMPIE (ACMP_CTL0[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |ACMPIF1 |Comparator 1 Interrupt Flag + * | | |This bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[9:8]) is detected on comparator 1 output + * | | |This will cause an interrupt if ACMPIE (ACMP_CTL1[1]) is set to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |ACMPO0 |Comparator 0 Output + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 0 is disabled, i.e + * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[5] |ACMPO1 |Comparator 1 Output + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 1 is disabled, i.e + * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[8] |WKIF0 |Comparator 0 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP0 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[9] |WKIF1 |Comparator 1 Power-down Wake-up Interrupt Flag + * | | |This bit will be set to 1 when ACMP1 wake-up interrupt event occurs. + * | | |0 = No power-down wake-up occurred. + * | | |1 = Power-down wake-up occurred. + * | | |Note: Write 1 to clear this bit to 0. + * |[12] |ACMPS0 |Comparator 0 Status + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 0 is disabled, i.e + * | | |ACMPEN (ACMP_CTL0[0]) is cleared to 0. + * |[13] |ACMPS1 |Comparator 1 Status + * | | |Synchronized to the PCLK to allow reading by software + * | | |Cleared when the comparator 1 is disabled, i.e + * | | |ACMPEN (ACMP_CTL1[0]) is cleared to 0. + * |[16] |ACMPWO |Comparator Window Output + * | | |This bit shows the output status of window compare mode + * | | |0 = The positive input voltage is outside the window. + * | | |1 = The positive input voltage is in the window. + * @var ACMP_T::VREF + * Offset: 0x0C Analog Comparator Reference Voltage Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CRVCTL |Comparator Reference Voltage Setting + * | | |CRV = CRV source voltage * (1/6+CRVCTL/24). + * |[6] |CRVSSEL |CRV Source Voltage Selection + * | | |0 = VDDA is selected as CRV source voltage. + * | | |1 = The reference voltage defined by SYS_VREFCTL register is selected as CRV source voltage. + */ + + __IO uint32_t CTL[2]; /*!< [0x0000~0x0004] Analog Comparator 0~1 Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] Analog Comparator Status Register */ + __IO uint32_t VREF; /*!< [0x000c] Analog Comparator Reference Voltage Control Register */ + +} ACMP_T; + +/** + @addtogroup ACMP_CONST ACMP Bit Field Definition + Constant Definitions for ACMP Controller + @{ +*/ + +#define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP_T::CTL: ACMPEN Position */ +#define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP_T::CTL: ACMPEN Mask */ + +#define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP_T::CTL: ACMPIE Position */ +#define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP_T::CTL: ACMPIE Mask */ + +#define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP_T::CTL: HYSEN Position */ +#define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP_T::CTL: HYSEN Mask */ + +#define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP_T::CTL: ACMPOINV Position */ +#define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP_T::CTL: ACMPOINV Mask */ + +#define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP_T::CTL: NEGSEL Position */ +#define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP_T::CTL: NEGSEL Mask */ + +#define ACMP_CTL_POSSEL_Pos (6) /*!< ACMP_T::CTL: POSSEL Position */ +#define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP_T::CTL: POSSEL Mask */ + +#define ACMP_CTL_INTPOL_Pos (8) /*!< ACMP_T::CTL: INTPOL Position */ +#define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) /*!< ACMP_T::CTL: INTPOL Mask */ + +#define ACMP_CTL_OUTSEL_Pos (12) /*!< ACMP_T::CTL: OUTSEL Position */ +#define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) /*!< ACMP_T::CTL: OUTSEL Mask */ + +#define ACMP_CTL_FILTSEL_Pos (13) /*!< ACMP_T::CTL: FILTSEL Position */ +#define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) /*!< ACMP_T::CTL: FILTSEL Mask */ + +#define ACMP_CTL_WKEN_Pos (16) /*!< ACMP_T::CTL: WKEN Position */ +#define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) /*!< ACMP_T::CTL: WKEN Mask */ + +#define ACMP_CTL_WLATEN_Pos (17) /*!< ACMP_T::CTL: WLATEN Position */ +#define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) /*!< ACMP_T::CTL: WLATEN Mask */ + +#define ACMP_CTL_WCMPSEL_Pos (18) /*!< ACMP_T::CTL: WCMPSEL Position */ +#define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) /*!< ACMP_T::CTL: WCMPSEL Mask */ + +#define ACMP_CTL_HYSSEL_Pos (24) /*!< ACMP_T::CTL: HYSSEL Position */ +#define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) /*!< ACMP_T::CTL: HYSSEL Mask */ + +#define ACMP_CTL_MODESEL_Pos (28) /*!< ACMP_T::CTL: MODESEL Position */ +#define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) /*!< ACMP_T::CTL: MODESEL Mask */ + +#define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP_T::STATUS: ACMPIF0 Position */ +#define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP_T::STATUS: ACMPIF0 Mask */ + +#define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP_T::STATUS: ACMPIF1 Position */ +#define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP_T::STATUS: ACMPIF1 Mask */ + +#define ACMP_STATUS_ACMPO0_Pos (4) /*!< ACMP_T::STATUS: ACMPO0 Position */ +#define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP_T::STATUS: ACMPO0 Mask */ + +#define ACMP_STATUS_ACMPO1_Pos (5) /*!< ACMP_T::STATUS: ACMPO1 Position */ +#define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP_T::STATUS: ACMPO1 Mask */ + +#define ACMP_STATUS_WKIF0_Pos (8) /*!< ACMP_T::STATUS: WKIF0 Position */ +#define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) /*!< ACMP_T::STATUS: WKIF0 Mask */ + +#define ACMP_STATUS_WKIF1_Pos (9) /*!< ACMP_T::STATUS: WKIF1 Position */ +#define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) /*!< ACMP_T::STATUS: WKIF1 Mask */ + +#define ACMP_STATUS_ACMPS0_Pos (12) /*!< ACMP_T::STATUS: ACMPS0 Position */ +#define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) /*!< ACMP_T::STATUS: ACMPS0 Mask */ + +#define ACMP_STATUS_ACMPS1_Pos (13) /*!< ACMP_T::STATUS: ACMPS1 Position */ +#define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) /*!< ACMP_T::STATUS: ACMPS1 Mask */ + +#define ACMP_STATUS_ACMPWO_Pos (16) /*!< ACMP_T::STATUS: ACMPWO Position */ +#define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) /*!< ACMP_T::STATUS: ACMPWO Mask */ + +#define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP_T::VREF: CRVCTL Position */ +#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP_T::VREF: CRVCTL Mask */ + +#define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP_T::VREF: CRVSSEL Position */ +#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP_T::VREF: CRVSSEL Mask */ + +/**@}*/ /* ACMP_CONST */ +/**@}*/ /* end of ACMP register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __ACMP_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/bpwm_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/bpwm_reg.h new file mode 100644 index 0000000000..041d09a9b6 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/bpwm_reg.h @@ -0,0 +1,1800 @@ +/**************************************************************************//** + * @file bpwm_reg.h + * @version V1.00 + * @brief BPWM register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BPWM_REG_H__ +#define __BPWM_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Basic Pulse Width Modulation Controller -------------------------*/ +/** + @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM) + Memory Mapped Structure for BPWM Controller + @{ +*/ + +typedef struct +{ + /** + * @var BCAPDAT_T::RCAPDAT + * Offset: 0x20C BPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the BPWM counter value will be saved in this register. + * @var BCAPDAT_T::FCAPDAT + * Offset: 0x210 BPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the BPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */ +} BCAPDAT_T; + + +typedef struct +{ + /** + * @var BPWM_T::CTL0 + * Offset: 0x00 BPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[1] |CTRLD1 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[2] |CTRLD2 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[3] |CTRLD3 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[4] |CTRLD4 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[5] |CTRLD5 |Center Re-load + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the center point of a period + * |[16] |IMMLDEN0 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bit(S) + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = PERIOD will load to PBUF at the end point of each period + * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. + * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. + * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt Disable. + * | | |1 = ICE debug mode counter halt Enable. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects BPWM output. + * | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement Disabled. + * | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * @var BPWM_T::CTL1 + * Offset: 0x04 BPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0 + * | | |Each bit n controls corresponding BPWM channel n. + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * @var BPWM_T::CLKSRC + * Offset: 0x10 BPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select + * | | |000 = BPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var BPWM_T::CLKPSC + * Offset: 0x14 BPWM Clock Prescale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |BPWM Counter Clock Prescale + * | | |The clock of BPWM counter is decided by clock prescaler + * | | |Each BPWM pair share one BPWM counter clock prescaler + * | | |The clock of BPWM counter is divided by (CLKPSC+ 1) + * @var BPWM_T::CNTEN + * Offset: 0x20 BPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |BPWM Counter 0 Enable Bit + * | | |0 = BPWM Counter and clock prescaler stop running. + * | | |1 = BPWM Counter and clock prescaler start running. + * @var BPWM_T::CNTCLR + * Offset: 0x24 BPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0 + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit BPWM counter to 0000H. + * @var BPWM_T::PERIOD + * Offset: 0x30 BPWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |BPWM Period Register + * | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |BPWM period time = (PERIOD+1) * BPWM_CLK period. + * | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |BPWM period time = 2 * PERIOD * BPWM_CLK period. + * @var BPWM_T::CMPDAT[6] + * Offset: 0x50 BPWM Comparator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPDAT |BPWM Comparator Register + * | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC. + * | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. + * @var BPWM_T::CNT + * Offset: 0x90 BPWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |BPWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |BPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is Down count. + * | | |1 = Counter is UP count. + * @var BPWM_T::WGCTL0 + * Offset: 0xB0 BPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[3:2] |ZPCTL1 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[5:4] |ZPCTL2 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[7:6] |ZPCTL3 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[9:8] |ZPCTL4 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[11:10] |ZPCTL5 |BPWM Zero Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM zero point output Low. + * | | |10 = BPWM zero point output High. + * | | |11 = BPWM zero point output Toggle. + * | | |BPWM can control output level when BPWM counter count to zero. + * |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM period (center) point output Low. + * | | |10 = BPWM period (center) point output High. + * | | |11 = BPWM period (center) point output Toggle. + * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). + * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. + * @var BPWM_T::WGCTL1 + * Offset: 0xB4 BPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare up point output Low. + * | | |10 = BPWM compare up point output High. + * | | |11 = BPWM compare up point output Toggle. + * | | |BPWM can control output level when BPWM counter up count to CMPDAT. + * |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |00 = Do nothing. + * | | |01 = BPWM compare down point output Low. + * | | |10 = BPWM compare down point output High. + * | | |11 = BPWM compare down point output Toggle. + * | | |BPWM can control output level when BPWM counter down count to CMPDAT. + * @var BPWM_T::MSKEN + * Offset: 0xB8 BPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[1] |MSKEN1 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[2] |MSKEN2 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[3] |MSKEN3 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[4] |MSKEN4 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * |[5] |MSKEN5 |BPWM Mask Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |The BPWM output signal will be masked when this bit is enabled + * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. + * | | |0 = BPWM output signal is non-masked. + * | | |1 = BPWM output signal is masked and output MSKDATn data. + * @var BPWM_T::MSK + * Offset: 0xBC BPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[1] |MSKDAT1 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[2] |MSKDAT2 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[3] |MSKDAT3 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[4] |MSKDAT4 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * |[5] |MSKDAT5 |BPWM Mask Data Bit + * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Output logic low to BPWMn. + * | | |1 = Output logic high to BPWMn. + * @var BPWM_T::POLCTL + * Offset: 0xD4 BPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[1] |PINV1 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[2] |PINV2 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[3] |PINV3 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[4] |PINV4 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * |[5] |PINV5 |BPWM PIN Polar Inverse Control + * | | |The register controls polarity state of BPWM output + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM output polar inverse Disabled. + * | | |1 = BPWM output polar inverse Enabled. + * @var BPWM_T::POEN + * Offset: 0xD8 BPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[1] |POEN1 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[2] |POEN2 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[3] |POEN3 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[4] |POEN4 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * |[5] |POEN5 |BPWM Pin Output Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM pin at tri-state. + * | | |1 = BPWM pin in output mode. + * @var BPWM_T::INTEN + * Offset: 0xE0 BPWM Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: When up-down counter type period point means center point. + * |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * @var BPWM_T::INTSTS + * Offset: 0xE8 BPWM Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. + * |[8] |PIF0 |BPWM Period Point Interrupt Flag 0 + * | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero. + * |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. + * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * @var BPWM_T::EADCTS0 + * Offset: 0xF8 BPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit + * |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select + * | | |0000 = BPWM_CH0 zero point. + * | | |0001 = BPWM_CH0 period point. + * | | |0010 = BPWM_CH0 zero or period point. + * | | |0011 = BPWM_CH0 up-count CMPDAT point. + * | | |0100 = BPWM_CH0 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH1 up-count CMPDAT point. + * | | |1001 = BPWM_CH1 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit + * |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved + * |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit + * |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select + * | | |0000 = BPWM_CH2 zero point. + * | | |0001 = BPWM_CH2 period point. + * | | |0010 = BPWM_CH2 zero or period point. + * | | |0011 = BPWM_CH2 up-count CMPDAT point. + * | | |0100 = BPWM_CH2 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH3 up-count CMPDAT point. + * | | |1001 = BPWM_CH3 down-count CMPDAT point. + * | | |Others reserved. + * |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit + * @var BPWM_T::EADCTS1 + * Offset: 0xFC BPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit + * |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select + * | | |0000 = BPWM_CH4 zero point. + * | | |0001 = BPWM_CH4 period point. + * | | |0010 = BPWM_CH4 zero or period point. + * | | |0011 = BPWM_CH4 up-count CMPDAT point. + * | | |0100 = BPWM_CH4 down-count CMPDAT point. + * | | |0101 = Reserved. + * | | |0110 = Reserved. + * | | |0111 = Reserved. + * | | |1000 = BPWM_CH5 up-count CMPDAT point. + * | | |1001 = BPWM_CH5 down-count CMPDAT point. + * | | |Others reserved + * |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit + * @var BPWM_T::SSCTL + * Offset: 0x110 BPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit + * | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). + * | | |0 = BPWM synchronous start function Disabled. + * | | |1 = BPWM synchronous start function Enabled. + * |[9:8] |SSRC |BPWM Synchronous Start Source Select + * | | |00 = Synchronous start source come from PWM0. + * | | |01 = Synchronous start source come from PWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var BPWM_T::SSTRG + * Offset: 0x114 BPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only) + * | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. + * @var BPWM_T::STATUS + * Offset: 0x120 BPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[16] |EADCTRG0 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[17] |EADCTRG1 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[18] |EADCTRG2 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[19] |EADCTRG3 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[20] |EADCTRG4 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[21] |EADCTRG5 |EADC Start of Conversion Status + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * @var BPWM_T::CAPINEN + * Offset: 0x200 BPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = BPWM Channel capture input path Disabled + * | | |The input of BPWM channel capture function is always regarded as 0. + * | | |1 = BPWM Channel capture input path Enabled + * | | |The input of BPWM channel capture function comes from correlative multifunction pin. + * @var BPWM_T::CAPCTL + * Offset: 0x204 BPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var BPWM_T::CAPSTS + * Offset: 0x208 BPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. + * |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. + * @var BPWM_T::CAPIEN + * Offset: 0x250 BPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits + * | | |Each bit n controls the corresponding BPWM channel n. + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * @var BPWM_T::CAPIF + * Offset: 0x254 BPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * @var BPWM_T::PBUF + * Offset: 0x304 BPWM PERIOD Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |BPWM Period Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var BPWM_T::CMPBUF[6] + * Offset: 0x31C BPWM CMPDAT 0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */ + __I uint32_t RESERVED0[2]; + __IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */ + __IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */ + __I uint32_t RESERVED1[2]; + __IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */ + __I uint32_t RESERVED2[2]; + __IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */ + __I uint32_t RESERVED3[7]; + __IO uint32_t CMPDAT[6]; /*!< [0x0050~0x0064] BPWM Comparator Register 0~5 */ + __I uint32_t RESERVED4[10]; + __I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */ + __I uint32_t RESERVED5[7]; + __IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */ + __I uint32_t RESERVED6[5]; + __IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */ + __I uint32_t RESERVED7[1]; + __IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */ + __I uint32_t RESERVED8[1]; + __IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */ + __I uint32_t RESERVED9[3]; + __IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */ + __I uint32_t RESERVED10[4]; + __IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */ + __I uint32_t RESERVED11[2]; + __IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */ + __I uint32_t RESERVED12[55]; + __IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */ + BCAPDAT_T CAPDAT[6]; /*!< [0x020c~0x0238] BPWM Rising and Falling Capture Data Register 0~5 */ + __I uint32_t RESERVED13[5]; + __IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */ + __I uint32_t RESERVED14[43]; + __I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */ + __I uint32_t RESERVED15[5]; + __I uint32_t CMPBUF[6]; /*!< [0x031c~0x0330] BPWM CMPDAT 0~5 Buffer */ + +} BPWM_T; + +/** + @addtogroup BPWM_CONST BPWM Bit Field Definition + Constant Definitions for BPWM Controller + @{ +*/ + +#define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */ +#define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */ + +#define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */ +#define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */ + +#define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */ +#define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */ + +#define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */ +#define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */ + +#define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */ +#define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */ + +#define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */ +#define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */ + +#define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */ +#define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */ + +#define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */ +#define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */ + +#define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */ +#define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */ + +#define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */ +#define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */ + +#define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */ +#define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */ + +#define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */ +#define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */ + +#define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */ +#define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */ + +#define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */ +#define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */ + +#define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */ +#define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */ + +#define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */ +#define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */ +#define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */ + +#define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */ +#define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */ + +#define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */ +#define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */ +#define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */ + +#define BPWM_CMPDAT0_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */ +#define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */ + +#define BPWM_CMPDAT1_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT1: CMPDAT Position */ +#define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) /*!< BPWM_T::CMPDAT1: CMPDAT Mask */ + +#define BPWM_CMPDAT2_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT2: CMPDAT Position */ +#define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) /*!< BPWM_T::CMPDAT2: CMPDAT Mask */ + +#define BPWM_CMPDAT3_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT3: CMPDAT Position */ +#define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) /*!< BPWM_T::CMPDAT3: CMPDAT Mask */ + +#define BPWM_CMPDAT4_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT4: CMPDAT Position */ +#define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) /*!< BPWM_T::CMPDAT4: CMPDAT Mask */ + +#define BPWM_CMPDAT5_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT5: CMPDAT Position */ +#define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) /*!< BPWM_T::CMPDAT5: CMPDAT Mask */ + +#define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */ +#define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */ + +#define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */ +#define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */ + +#define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */ +#define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */ +#define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */ +#define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */ +#define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */ +#define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */ +#define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define BPWM_WGCTL0_ZPCTLn_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTLn Position */ +#define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) /*!< BPWM_T::WGCTL0: ZPCTLn Mask */ + +#define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */ +#define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */ +#define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */ +#define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */ +#define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */ +#define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */ +#define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define BPWM_WGCTL0_PRDPCTLn_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTLn Position */ +#define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) /*!< BPWM_T::WGCTL0: PRDPCTLn Mask */ + +#define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */ +#define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */ +#define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */ +#define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */ +#define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */ +#define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */ +#define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define BPWM_WGCTL1_CMPUCTLn_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTLn Position */ +#define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPUCTLn Mask */ + +#define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */ +#define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */ +#define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */ +#define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */ +#define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */ +#define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */ +#define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define BPWM_WGCTL1_CMPDCTLn_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTLn Position */ +#define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPDCTLn Mask */ + +#define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */ +#define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */ + +#define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */ +#define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */ + +#define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */ +#define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */ + +#define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */ +#define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */ + +#define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */ +#define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */ + +#define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */ +#define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */ + +#define BPWM_MSKEN_MSKENn_Pos (0) /*!< BPWM_T::MSKEN: MSKENn Position */ +#define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) /*!< BPWM_T::MSKEN: MSKENn Mask */ + +#define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */ +#define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */ + +#define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */ +#define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */ + +#define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */ +#define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */ + +#define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */ +#define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */ + +#define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */ +#define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */ + +#define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */ +#define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */ + +#define BPWM_MSK_MSKDATn_Pos (0) /*!< BPWM_T::MSK: MSKDATn Position */ +#define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) /*!< BPWM_T::MSK: MSKDATn Mask */ + +#define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */ +#define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */ + +#define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */ +#define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */ + +#define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */ +#define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */ + +#define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */ +#define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */ + +#define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */ +#define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */ + +#define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */ +#define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */ + +#define BPWM_POLCTL_PINVn_Pos (0) /*!< BPWM_T::POLCTL: PINVn Position */ +#define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) /*!< BPWM_T::POLCTL: PINVn Mask */ + +#define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */ +#define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */ + +#define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */ +#define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */ + +#define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */ +#define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */ + +#define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */ +#define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */ + +#define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */ +#define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */ + +#define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */ +#define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */ + +#define BPWM_POEN_POENn_Pos (0) /*!< BPWM_T::POEN: POENn Position */ +#define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) /*!< BPWM_T::POEN: POENn Mask */ + +#define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */ +#define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */ + +#define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */ +#define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */ +#define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */ + +#define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */ +#define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */ + +#define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */ +#define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */ + +#define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */ +#define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */ + +#define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */ +#define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */ + +#define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */ +#define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */ + +#define BPWM_INTEN_CMPUIENn_Pos (16) /*!< BPWM_T::INTEN: CMPUIENn Position */ +#define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM_T::INTEN: CMPUIENn Mask */ + +#define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */ +#define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */ + +#define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */ +#define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */ + +#define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */ +#define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */ + +#define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */ +#define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */ + +#define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */ +#define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */ + +#define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */ +#define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */ + +#define BPWM_INTEN_CMPDIENn_Pos (24) /*!< BPWM_T::INTEN: CMPDIENn Position */ +#define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM_T::INTEN: CMPDIENn Mask */ + +#define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */ +#define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */ + +#define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */ +#define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */ +#define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */ + +#define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */ +#define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */ + +#define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */ +#define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */ + +#define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */ +#define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */ + +#define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */ +#define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */ + +#define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */ +#define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */ + +#define BPWM_INTSTS_CMPUIFn_Pos (16) /*!< BPWM_T::INTSTS: CMPUIFn Position */ +#define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) /*!< BPWM_T::INTSTS: CMPUIFn Mask */ + +#define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */ +#define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */ + +#define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */ +#define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */ + +#define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */ +#define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */ + +#define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */ +#define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */ + +#define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */ +#define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */ + +#define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */ +#define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */ + +#define BPWM_INTSTS_CMPDIFn_Pos (24) /*!< BPWM_T::INTSTS: CMPDIFn Position */ +#define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) /*!< BPWM_T::INTSTS: CMPDIFn Mask */ + +#define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */ +#define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */ +#define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */ + +#define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */ +#define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */ +#define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */ + +#define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */ +#define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */ +#define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */ + +#define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */ +#define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */ +#define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */ + +#define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */ +#define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */ +#define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */ + +#define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */ +#define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */ +#define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */ + +#define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */ +#define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */ + +#define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */ +#define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */ + +#define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */ +#define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */ + +#define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */ +#define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */ + +#define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */ +#define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */ + +#define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */ +#define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */ + +#define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */ +#define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */ + +#define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */ +#define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */ + +#define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */ +#define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */ + +#define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */ +#define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */ + +#define BPWM_STATUS_EADCTRGn_Pos (16) /*!< BPWM_T::STATUS: EADCTRGn Position */ +#define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) /*!< BPWM_T::STATUS: EADCTRGn Mask */ + +#define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */ +#define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */ +#define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */ +#define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */ +#define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */ +#define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */ +#define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define BPWM_CAPINEN_CAPINENn_Pos (0) /*!< BPWM_T::CAPINEN: CAPINENn Position */ +#define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) /*!< BPWM_T::CAPINEN: CAPINENn Mask */ + +#define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */ +#define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */ + +#define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */ +#define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */ + +#define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */ +#define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */ + +#define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */ +#define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */ + +#define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */ +#define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */ + +#define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */ +#define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */ + +#define BPWM_CAPCTL_CAPENn_Pos (0) /*!< BPWM_T::CAPCTL: CAPENn Position */ +#define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) /*!< BPWM_T::CAPCTL: CAPENn Mask */ + +#define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */ +#define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */ + +#define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */ +#define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */ + +#define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */ +#define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */ + +#define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */ +#define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */ + +#define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */ +#define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */ + +#define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */ +#define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */ + +#define BPWM_CAPCTL_CAPINVn_Pos (8) /*!< BPWM_T::CAPCTL: CAPINVn Position */ +#define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) /*!< BPWM_T::CAPCTL: CAPINVn Mask */ + +#define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */ +#define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */ +#define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */ +#define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */ +#define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */ +#define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */ +#define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define BPWM_CAPCTL_RCRLDENn_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDENn Position */ +#define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) /*!< BPWM_T::CAPCTL: RCRLDENn Mask */ + +#define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */ +#define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */ +#define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */ +#define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */ +#define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */ +#define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */ +#define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define BPWM_CAPCTL_FCRLDENn_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDENn Position */ +#define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) /*!< BPWM_T::CAPCTL: FCRLDENn Mask */ + +#define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */ +#define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */ + +#define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */ +#define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */ + +#define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */ +#define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */ + +#define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */ +#define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */ + +#define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */ +#define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */ + +#define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */ +#define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */ + +#define BPWM_CAPSTS_CRIFOVn_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOVn Position */ +#define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) /*!< BPWM_T::CAPSTS: CRIFOVn Mask */ + +#define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */ +#define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */ + +#define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */ +#define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */ + +#define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */ +#define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */ + +#define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */ +#define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */ + +#define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */ +#define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */ + +#define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */ +#define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */ + +#define BPWM_CAPSTS_CFIFOVn_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOVn Position */ +#define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) /*!< BPWM_T::CAPSTS: CFIFOVn Mask */ + +#define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */ +#define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */ +#define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */ +#define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */ +#define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */ +#define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */ +#define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */ +#define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */ +#define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */ +#define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */ +#define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */ +#define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */ +#define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */ +#define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */ + +#define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */ +#define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */ + +#define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */ +#define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */ + +#define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */ +#define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */ + +#define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */ +#define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */ + +#define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */ +#define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */ + +#define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */ +#define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */ + +#define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */ +#define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */ + +#define BPWM_CAPIF_CAPRIFn_Pos (0) /*!< BPWM_T::CAPIF: CAPRIFn Position */ +#define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) /*!< BPWM_T::CAPIF: CAPRIFn Mask */ + +#define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */ +#define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */ + +#define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */ +#define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */ + +#define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */ +#define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */ + +#define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */ +#define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */ + +#define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */ +#define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */ + +#define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */ +#define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */ + +#define BPWM_CAPIF_CAPFIFn_Pos (8) /*!< BPWM_T::CAPIF: CAPFIFn Position */ +#define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) /*!< BPWM_T::CAPIF: CAPFIFn Mask */ + +#define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */ +#define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */ + +#define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */ +#define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */ + +#define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */ +#define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */ + +#define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */ +#define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */ + +#define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */ +#define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */ + +#define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */ +#define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */ + +#define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */ +#define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */ + +/**@}*/ /* BPWM_CONST */ +/**@}*/ /* end of BPWM register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __BPWM_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/can_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/can_reg.h new file mode 100644 index 0000000000..a93edb74cf --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/can_reg.h @@ -0,0 +1,790 @@ +/**************************************************************************//** + * @file can_reg.h + * @version V1.00 + * @brief CAN register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CAN_REG_H__ +#define __CAN_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Controller Area Network Controller -------------------------*/ +/** + @addtogroup CAN Controller Area Network Controller(CAN) + Memory Mapped Structure for CAN Controller + @{ +*/ + + +typedef struct +{ + + + + /** + * @var CAN_IF_T::CREQ + * Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |MessageNumber|Message Number + * | | |0x01-0x20: Valid Message Number, the Message Object in the Message + * | | |RAM is selected for data transfer. + * | | |0x00: Not a valid Message Number, interpreted as 0x20. + * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F. + * |[15] |Busy |Busy Flag + * | | |0 = Read/write action has finished. + * | | |1 = Writing to the IFn Command Request Register is in progress. + * | | |This bit can only be read by the software. + * @var CAN_IF_T::CMASK + * Offset: 0x24, 0x84 IFn Command Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DAT_B |Access Data Bytes [7:4] + * | | |Write Operation: + * | | |0 = Data Bytes [7:4] unchanged. + * | | |1 = Transfer Data Bytes [7:4] to Message Object. + * | | |Read Operation: + * | | |0 = Data Bytes [7:4] unchanged. + * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register. + * |[1] |DAT_A |Access Data Bytes [3:0] + * | | |Write Operation: + * | | |0 = Data Bytes [3:0] unchanged. + * | | |1 = Transfer Data Bytes [3:0] to Message Object. + * | | |Read Operation: + * | | |0 = Data Bytes [3:0] unchanged. + * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register. + * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation + * | | |0 = TxRqst bit unchanged. + * | | |1 = Set TxRqst bit. + * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored. + * | | |Access New Data Bit when Read Operation. + * | | |0 = NewDat bit remains unchanged. + * | | |1 = Clear NewDat bit in the Message Object. + * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. + * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits. + * |[3] |ClrIntPnd |Clear Interrupt Pending Bit + * | | |Write Operation: + * | | |When writing to a Message Object, this bit is ignored. + * | | |Read Operation: + * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged. + * | | |1 = Clear IntPnd bit in the Message Object. + * |[4] |Control |Control Access Control Bits + * | | |Write Operation: + * | | |0 = Control Bits unchanged. + * | | |1 = Transfer Control Bits to Message Object. + * | | |Read Operation: + * | | |0 = Control Bits unchanged. + * | | |1 = Transfer Control Bits to IFn Message Buffer Register. + * |[5] |Arb |Access Arbitration Bits + * | | |Write Operation: + * | | |0 = Arbitration bits unchanged. + * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object. + * | | |Read Operation: + * | | |0 = Arbitration bits unchanged. + * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register. + * |[6] |Mask |Access Mask Bits + * | | |Write Operation: + * | | |0 = Mask bits unchanged. + * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object. + * | | |Read Operation: + * | | |0 = Mask bits unchanged. + * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register. + * |[7] |WR_RD |Write / Read Mode + * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers. + * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register. + * @var CAN_IF_T::MASK1 + * Offset: 0x28, 0x88 IFn Mask 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |Msk[15:0] |Identifier Mask 15-0 + * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. + * | | |1 = The corresponding identifier bit is used for acceptance filtering. + * @var CAN_IF_T::MASK2 + * Offset: 0x2C, 0x8C IFn Mask 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |Msk[28:16]|Identifier Mask 28-16 + * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. + * | | |1 = The corresponding identifier bit is used for acceptance filtering. + * |[14] |MDir |Mask Message Direction + * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering. + * | | |1 = The message direction bit (Dir) is used for acceptance filtering. + * |[15] |MXtd |Mask Extended Identifier + * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering. + * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering. + * | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]). + * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered. + * @var CAN_IF_T::ARB1 + * Offset: 0x30, 0x90 IFn Arbitration 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ID[15:0] |Message Identifier 15-0 + * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame"). + * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame") + * @var CAN_IF_T::ARB2 + * Offset: 0x34, 0x94 IFn Arbitration 2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |ID[28:16] |Message Identifier 28-16 + * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame"). + * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame") + * |[13] |Dir |Message Direction + * | | |0 = Direction is receive. + * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted. + * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object. + * | | |1 = Direction is transmit. + * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame. + * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one). + * |[14] |Xtd |Extended Identifier + * | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object. + * | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object. + * |[15] |MsgVal |Message Valid + * | | |0 = The Message Object is ignored by the Message Handler. + * | | |1 = The Message Object is configured and should be considered by the Message Handler. + * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). + * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required. + * @var CAN_IF_T::MCON + * Offset: 0x38, 0x98 IFn Message Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DLC |Data Length Code + * | | |0-8: Data Frame has 0-8 data bytes. + * | | |9-15: Data Frame has 8 data bytes + * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. + * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. + * | | |Data 0: 1st data byte of a CAN Data Frame + * | | |Data 1: 2nd data byte of a CAN Data Frame + * | | |Data 2: 3rd data byte of a CAN Data Frame + * | | |Data 3: 4th data byte of a CAN Data Frame + * | | |Data 4: 5th data byte of a CAN Data Frame + * | | |Data 5: 6th data byte of a CAN Data Frame + * | | |Data 6: 7th data byte of a CAN Data Frame + * | | |Data 7 : 8th data byte of a CAN Data Frame + * | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last. + * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. + * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values. + * |[7] |EoB |End Of Buffer + * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer. + * | | |1 = Single Message Object or last Message Object of a FIFO Buffer. + * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. + * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one. + * |[8] |TxRqst |Transmit Request + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * |[9] |RmtEn |Remote Enable Control + * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged. + * | | |1 = At the reception of a Remote Frame, TxRqst is set. + * |[10] |RxIE |Receive Interrupt Enable Control + * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame. + * | | |1 = IntPnd will be set after a successful reception of a frame. + * |[11] |TxIE |Transmit Interrupt Enable Control + * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame. + * | | |1 = IntPnd will be set after a successful transmission of a frame. + * |[12] |UMask |Use Acceptance Mask + * | | |0 = Mask ignored. + * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering. + * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one. + * |[13] |IntPnd |Interrupt Pending + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt. + * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority. + * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive). + * | | |0 = No message lost since last time this bit was reset by the CPU. + * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message. + * |[15] |NewDat |New Data + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_IF_T::DAT_A1 + * Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data0 |Data Byte 0 + * | | |1st data byte of a CAN Data Frame + * |[15:8] |Data1 |Data Byte 1 + * | | |2nd data byte of a CAN Data Frame + * @var CAN_IF_T::DAT_A2 + * Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data2 |Data Byte 2 + * | | |3rd data byte of CAN Data Frame + * |[15:8] |Data3 |Data Byte 3 + * | | |4th data byte of CAN Data Frame + * @var CAN_IF_T::DAT_B1 + * Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data4 |Data Byte 4 + * | | |5th data byte of CAN Data Frame + * |[15:8] |Data5 |Data Byte 5 + * | | |6th data byte of CAN Data Frame + * @var CAN_IF_T::DAT_B2 + * Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |Data6 |Data Byte 6 + * | | |7th data byte of CAN Data Frame. + * |[15:8] |Data7 |Data Byte 7 + * | | |8th data byte of CAN Data Frame. + */ + + __IO uint32_t CREQ; /* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers */ + __IO uint32_t CMASK; /* Offset: 0x24, 0x84 IFn Command Mask Register */ + __IO uint32_t MASK1; /* Offset: 0x28, 0x88 IFn Mask 1 Register */ + __IO uint32_t MASK2; /* Offset: 0x2C, 0x8C IFn Mask 2 Register */ + __IO uint32_t ARB1; /* Offset: 0x30, 0x90 IFn Arbitration 1 Register */ + __IO uint32_t ARB2; /* Offset: 0x34, 0x94 IFn Arbitration 2 Register */ + __IO uint32_t MCON; /* Offset: 0x38, 0x98 IFn Message Control Register */ + __IO uint32_t DAT_A1; /* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) */ + __IO uint32_t DAT_A2; /* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) */ + __IO uint32_t DAT_B1; /* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) */ + __IO uint32_t DAT_B2; /* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) */ + __I uint32_t RESERVE0[13]; + +} CAN_IF_T; + + + + +typedef struct +{ + + + + /** + * @var CAN_T::CON + * Offset: 0x00 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |Init |Init Initialization + * | | |0 = Normal Operation. + * | | |1 = Initialization is started. + * |[1] |IE |Module Interrupt Enable Control + * | | |0 = Disabled. + * | | |1 = Enabled. + * |[2] |SIE |Status Change Interrupt Enable Control + * | | |0 = Disabled - No Status Change Interrupt will be generated. + * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected. + * |[3] |EIE |Error Interrupt Enable Control + * | | |0 = Disabled - No Error Status Interrupt will be generated. + * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt. + * |[5] |DAR |Automatic Re-Transmission Disable Control + * | | |0 = Automatic Retransmission of disturbed messages enabled. + * | | |1 = Automatic Retransmission disabled. + * |[6] |CCE |Configuration Change Enable Control + * | | |0 = No write access to the Bit Timing Register. + * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1). + * |[7] |Test |Test Mode Enable Control + * | | |0 = Normal Operation. + * | | |1 = Test Mode. + * @var CAN_T::STATUS + * Offset: 0x04 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus) + * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. + * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. + * | | |The unused code '7' may be written by the CPU to check for updates. + * | | |The following table describes the error code. + * |[3] |TxOK |Transmitted A Message Successfully + * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted. + * | | |This bit is never reset by the CAN Core. + * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted. + * |[4] |RxOK |Received A Message Successfully + * | | |0 = No message has been successfully received since this bit was last reset by the CPU. + * | | |This bit is never reset by the CAN Core. + * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering). + * |[5] |EPass |Error Passive (Read Only) + * | | |0 = The CAN Core is error active. + * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification. + * |[6] |EWarn |Error Warning Status (Read Only) + * | | |0 = Both error counters are below the error warning limit of 96. + * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96. + * |[7] |BOff |Bus-Off Status (Read Only) + * | | |0 = The CAN module is not in bus-off state. + * | | |1 = The CAN module is in bus-off state. + * @var CAN_T::ERR + * Offset: 0x08 Error Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TEC |Transmit Error Counter + * | | |Actual state of the Transmit Error Counter. Values between 0 and 255. + * |[14:8] |REC |Receive Error Counter + * | | |Actual state of the Receive Error Counter. Values between 0 and 127. + * |[15] |RP |Receive Error Passive + * | | |0 = The Receive Error Counter is below the error passive level. + * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification. + * @var CAN_T::BTIME + * Offset: 0x0C Bit Timing Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |BRP |Baud Rate Prescaler + * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. + * | | |The bit time is built up from a multiple of this quanta. + * | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ]. + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[7:6] |SJW |(Re)Synchronization Jump Width + * | | |0x0-0x3: Valid programmed values are [0 ... 3]. + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * |[11:8] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg + * | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15]. + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used. + * |[14:12] |TSeg2 |Time Segment After Sample Point + * | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7]. + * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. + * @var CAN_T::IIDR + * Offset: 0x10 Interrupt Identifier Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt) + * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. + * | | |An interrupt remains pending until the application software has cleared it. + * | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active. + * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset. + * | | |The Status Interrupt has the highest priority. + * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number. + * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]). + * | | |The Status Interrupt is cleared by reading the Status Register. + * @var CAN_T::TEST + * Offset: 0x14 Test Register (Register Map Note 1) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |Res |Reserved + * | | |There are reserved bits. + * | | |These bits are always read as '0' and must always be written with '0'. + * |[2] |Basic |Basic Mode + * | | |0 = Basic Mode disabled. + * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. + * |[3] |Silent |Silent Mode + * | | |0 = Normal operation. + * | | |1 = The module is in Silent Mode. + * |[4] |LBack |Loop Back Mode Enable Control + * | | |0 = Loop Back Mode is disabled. + * | | |1 = Loop Back Mode is enabled. + * |[6:5] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin + * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core. + * | | |01 = Sample Point can be monitored at CAN_TX pin. + * | | |10 = CAN_TX pin drives a dominant ('0') value. + * | | |11 = CAN_TX pin drives a recessive ('1') value. + * |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only) + * | | |0 = The CAN bus is dominant (CAN_RX = '0'). + * | | |1 = The CAN bus is recessive (CAN_RX = '1'). + * @var CAN_T::BRPE + * Offset: 0x18 Baud Rate Prescaler Extension Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension + * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. + * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used. + * @var CAN_T::IF + * Offset: 0x20~0xFC CAN Interface Registers + * --------------------------------------------------------------------------------------------------- + * CAN interface structure. Refer to \ref CAN_IF_T for detail information. + * + * @var CAN_T::TXREQ1 + * Offset: 0x100 Transmission Request Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects) + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * | | |These bits are read only. + * @var CAN_T::TXREQ2 + * Offset: 0x104 Transmission Request Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects) + * | | |0 = This Message Object is not waiting for transmission. + * | | |1 = The transmission of this Message Object is requested and is not yet done. + * | | |These bits are read only. + * @var CAN_T::NDAT1 + * Offset: 0x120 New Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects) + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_T::NDAT2 + * Offset: 0x124 New Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects) + * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. + * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. + * @var CAN_T::IPND1 + * Offset: 0x140 Interrupt Pending Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects) + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt. + * @var CAN_T::IPND2 + * Offset: 0x144 Interrupt Pending Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects) + * | | |0 = This message object is not the source of an interrupt. + * | | |1 = This message object is the source of an interrupt. + * @var CAN_T::MVLD1 + * Offset: 0x160 Message Valid Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only) + * | | |0 = This Message Object is ignored by the Message Handler. + * | | |1 = This Message Object is configured and should be considered by the Message Handler. + * | | |Ex. + * | | |CAN_MVLD1[0] means Message object No.1 is valid or not. + * | | |If CAN_MVLD1[0] is set, message object No.1 is configured. + * @var CAN_T::MVLD2 + * Offset: 0x164 Message Valid Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only) + * | | |0 = This Message Object is ignored by the Message Handler. + * | | |1 = This Message Object is configured and should be considered by the Message Handler. + * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not. + * | | |If CAN_MVLD2[15] is set, message object No.32 is configured. + * @var CAN_T::WU_EN + * Offset: 0x168 Wake-up Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WAKUP_EN |Wake-Up Enable Control + * | | |0 = The wake-up function Disabled. + * | | |1 = The wake-up function Enabled. + * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin. + * @var CAN_T::WU_STATUS + * Offset: 0x16C Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WAKUP_STS |Wake-Up Status + * | | |0 = No wake-up event occurred. + * | | |1 = Wake-up event occurred. + * | | |Note: This bit can be cleared by writing '0'. + */ + + __IO uint32_t CON; /* Offset: 0x00 Control Register */ + __IO uint32_t STATUS; /* Offset: 0x04 Status Register */ + __I uint32_t ERR; /* Offset: 0x08 Error Counter Register */ + __IO uint32_t BTIME; /* Offset: 0x0C Bit Timing Register */ + __I uint32_t IIDR; /* Offset: 0x10 Interrupt Identifier Register */ + __IO uint32_t TEST; /* Offset: 0x14 Test Register (Register Map Note 1) */ + __IO uint32_t BRPE; /* Offset: 0x18 Baud Rate Prescaler Extension Register */ + __I uint32_t RESERVE0[1]; + __IO CAN_IF_T IF[2]; /* Offset: 0x20~0xFC CAN Interface Registers */ + __I uint32_t RESERVE1[8]; + __I uint32_t TXREQ1; /* Offset: 0x100 Transmission Request Register 1 */ + __I uint32_t TXREQ2; /* Offset: 0x104 Transmission Request Register 2 */ + __I uint32_t RESERVE3[6]; + __I uint32_t NDAT1; /* Offset: 0x120 New Data Register 1 */ + __I uint32_t NDAT2; /* Offset: 0x124 New Data Register 2 */ + __I uint32_t RESERVE4[6]; + __I uint32_t IPND1; /* Offset: 0x140 Interrupt Pending Register 1 */ + __I uint32_t IPND2; /* Offset: 0x144 Interrupt Pending Register 2 */ + __I uint32_t RESERVE5[6]; + __I uint32_t MVLD1; /* Offset: 0x160 Message Valid Register 1 */ + __I uint32_t MVLD2; /* Offset: 0x164 Message Valid Register 2 */ + __IO uint32_t WU_EN; /* Offset: 0x168 Wake-up Enable Register */ + __IO uint32_t WU_STATUS; /* Offset: 0x16C Wake-up Status Register */ + +} CAN_T; + + + +/** + @addtogroup CAN_CONST CAN Bit Field Definition + Constant Definitions for CAN Controller + @{ +*/ +/* CAN CON Bit Field Definitions */ +#define CAN_CON_TEST_Pos 7 /*!< CAN_T::CON: TEST Position */ +#define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: TEST Mask */ + +#define CAN_CON_CCE_Pos 6 /*!< CAN_T::CON: CCE Position */ +#define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */ + +#define CAN_CON_DAR_Pos 5 /*!< CAN_T::CON: DAR Position */ +#define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */ + +#define CAN_CON_EIE_Pos 3 /*!< CAN_T::CON: EIE Position */ +#define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */ + +#define CAN_CON_SIE_Pos 2 /*!< CAN_T::CON: SIE Position */ +#define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */ + +#define CAN_CON_IE_Pos 1 /*!< CAN_T::CON: IE Position */ +#define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */ + +#define CAN_CON_INIT_Pos 0 /*!< CAN_T::CON: INIT Position */ +#define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: INIT Mask */ + +/* CAN STATUS Bit Field Definitions */ +#define CAN_STATUS_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */ +#define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */ + +#define CAN_STATUS_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */ +#define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */ + +#define CAN_STATUS_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */ +#define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */ + +#define CAN_STATUS_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */ +#define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */ + +#define CAN_STATUS_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */ +#define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */ + +#define CAN_STATUS_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */ +#define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */ + +/* CAN ERR Bit Field Definitions */ +#define CAN_ERR_RP_Pos 15 /*!< CAN_T::ERR: RP Position */ +#define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */ + +#define CAN_ERR_REC_Pos 8 /*!< CAN_T::ERR: REC Position */ +#define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */ + +#define CAN_ERR_TEC_Pos 0 /*!< CAN_T::ERR: TEC Position */ +#define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */ + +/* CAN BTIME Bit Field Definitions */ +#define CAN_BTIME_TSEG2_Pos 12 /*!< CAN_T::BTIME: TSEG2 Position */ +#define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSEG2 Mask */ + +#define CAN_BTIME_TSEG1_Pos 8 /*!< CAN_T::BTIME: TSEG1 Position */ +#define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSEG1 Mask */ + +#define CAN_BTIME_SJW_Pos 6 /*!< CAN_T::BTIME: SJW Position */ +#define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */ + +#define CAN_BTIME_BRP_Pos 0 /*!< CAN_T::BTIME: BRP Position */ +#define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */ + +/* CAN IIDR Bit Field Definitions */ +#define CAN_IIDR_INTID_Pos 0 /*!< CAN_T::IIDR: INTID Position */ +#define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: INTID Mask */ + +/* CAN TEST Bit Field Definitions */ +#define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */ +#define CAN_TEST_RX_Msk (0x1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */ + +#define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */ +#define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */ + +#define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */ +#define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */ + +#define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */ +#define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */ + +#define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */ +#define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */ + +/* CAN BPRE Bit Field Definitions */ +#define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */ +#define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */ + +/* CAN IFn_CREQ Bit Field Definitions */ +#define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_IF_T::CREQ: BUSY Position */ +#define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: BUSY Mask */ + +#define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_IF_T::CREQ: MSGNUM Position */ +#define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MSGNUM Mask */ + +/* CAN IFn_CMASK Bit Field Definitions */ +#define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_IF_T::CMASK: WRRD Position */ +#define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WRRD Mask */ + +#define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_IF_T::CMASK: MASK Position */ +#define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: MASK Mask */ + +#define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_IF_T::CMASK: ARB Position */ +#define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: ARB Mask */ + +#define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_IF_T::CMASK: CONTROL Position */ +#define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: CONTROL Mask */ + +#define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_IF_T::CMASK: CLRINTPND Position */ +#define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: CLRINTPND Mask */ + +#define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */ +#define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask */ + +#define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_IF_T::CMASK: DATAA Position */ +#define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DATAA Mask */ + +#define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_IF_T::CMASK: DATAB Position */ +#define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DATAB Mask */ + +/* CAN IFn_MASK1 Bit Field Definitions */ +#define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_IF_T::MASK1: MSK Position */ +#define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_IF_T::MASK1: MSK Mask */ + +/* CAN IFn_MASK2 Bit Field Definitions */ +#define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN_IF_T::MASK2: MXTD Position */ +#define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXTD Mask */ + +#define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN_IF_T::MASK2: MDIR Position */ +#define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDIR Mask */ + +#define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN_IF_T::MASK2: MSK Position */ +#define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN_IF_T::MASK2: MSK Mask */ + +/* CAN IFn_ARB1 Bit Field Definitions */ +#define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_IF_T::ARB1: ID Position */ +#define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */ + +/* CAN IFn_ARB2 Bit Field Definitions */ +#define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN_IF_T::ARB2: MSGVAL Position */ +#define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MSGVAL Mask */ + +#define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN_IF_T::ARB2: XTD Position */ +#define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: XTD Mask */ + +#define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN_IF_T::ARB2: DIR Position */ +#define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: DIR Mask */ + +#define CAN_IF_ARB2_ID_Pos 0 /*!< CAN_IF_T::ARB2: ID Position */ +#define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */ + +/* CAN IFn_MCON Bit Field Definitions */ +#define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN_IF_T::MCON: NEWDAT Position */ +#define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NEWDAT Mask */ + +#define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN_IF_T::MCON: MSGLST Position */ +#define CAN_IF_MCON_MSGLST_Msk (0x1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN_IF_T::MCON: MSGLST Mask */ + +#define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN_IF_T::MCON: INTPND Position */ +#define CAN_IF_MCON_INTPND_Msk (0x1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN_IF_T::MCON: INTPND Mask */ + +#define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN_IF_T::MCON: UMASK Position */ +#define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMASK Mask */ + +#define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN_IF_T::MCON: TXIE Position */ +#define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TXIE Mask */ + +#define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN_IF_T::MCON: RXIE Position */ +#define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RXIE Mask */ + +#define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN_IF_T::MCON: RMTEN Position */ +#define CAN_IF_MCON_RMTEN_Msk (0x1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN_IF_T::MCON: RMTEN Mask */ + +#define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN_IF_T::MCON: TXRQST Position */ +#define CAN_IF_MCON_TXRQST_Msk (0x1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN_IF_T::MCON: TXRQST Mask */ + +#define CAN_IF_MCON_EOB_Pos 7 /*!< CAN_IF_T::MCON: EOB Position */ +#define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EOB Mask */ + +#define CAN_IF_MCON_DLC_Pos 0 /*!< CAN_IF_T::MCON: DLC Position */ +#define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */ + +/* CAN IFn_DATA_A1 Bit Field Definitions */ +#define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN_IF_T::DATAA1: DATA1 Position */ +#define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DATAA1: DATA1 Mask */ + +#define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN_IF_T::DATAA1: DATA0 Position */ +#define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DATAA1: DATA0 Mask */ + +/* CAN IFn_DATA_A2 Bit Field Definitions */ +#define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN_IF_T::DATAA1: DATA3 Position */ +#define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DATAA1: DATA3 Mask */ + +#define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN_IF_T::DATAA1: DATA2 Position */ +#define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DATAA1: DATA2 Mask */ + +/* CAN IFn_DATA_B1 Bit Field Definitions */ +#define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN_IF_T::DATAB1: DATA5 Position */ +#define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DATAB1: DATA5 Mask */ + +#define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN_IF_T::DATAB1: DATA4 Position */ +#define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DATAB1: DATA4 Mask */ + +/* CAN IFn_DATA_B2 Bit Field Definitions */ +#define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN_IF_T::DATAB2: DATA7 Position */ +#define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DATAB2: DATA7 Mask */ + +#define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN_IF_T::DATAB2: DATA6 Position */ +#define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DATAB2: DATA6 Mask */ + +/* CAN IFn_TXRQST1 Bit Field Definitions */ +#define CAN_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::TXRQST1: TXRQST Position */ +#define CAN_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_TXRQST1_TXRQST_Pos) /*!< CAN_T::TXRQST1: TXRQST Mask */ + +/* CAN IFn_TXRQST2 Bit Field Definitions */ +#define CAN_TXRQST2_TXRQST_Pos 0 /*!< CAN_T::TXRQST2: TXRQST Position */ +#define CAN_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_TXRQST2_TXRQST_Pos) /*!< CAN_T::TXRQST2: TXRQST Mask */ + +/* CAN IFn_NDAT1 Bit Field Definitions */ +#define CAN_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::NDAT1: NEWDATA Position */ +#define CAN_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_NDAT1_NEWDATA_Pos) /*!< CAN_T::NDAT1: NEWDATA Mask */ + +/* CAN IFn_NDAT2 Bit Field Definitions */ +#define CAN_NDAT2_NEWDATA_Pos 0 /*!< CAN_T::NDAT2: NEWDATA Position */ +#define CAN_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_NDAT2_NEWDATA_Pos) /*!< CAN_T::NDAT2: NEWDATA Mask */ + +/* CAN IFn_IPND1 Bit Field Definitions */ +#define CAN_IPND1_INTPND_Pos 0 /*!< CAN_T::IPND1: INTPND Position */ +#define CAN_IPND1_INTPND_Msk (0xFFFFul << CAN_IPND1_INTPND_Pos) /*!< CAN_T::IPND1: INTPND Mask */ + +/* CAN IFn_IPND2 Bit Field Definitions */ +#define CAN_IPND2_INTPND_Pos 0 /*!< CAN_T::IPND2: INTPND Position */ +#define CAN_IPND2_INTPND_Msk (0xFFFFul << CAN_IPND2_INTPND_Pos) /*!< CAN_T::IPND2: INTPND Mask */ + +/* CAN IFn_MVLD1 Bit Field Definitions */ +#define CAN_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::MVLD1: MSGVAL Position */ +#define CAN_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_MVLD1_MSGVAL_Pos) /*!< CAN_T::MVLD1: MSGVAL Mask */ + +/* CAN IFn_MVLD2 Bit Field Definitions */ +#define CAN_MVLD2_MSGVAL_Pos 0 /*!< CAN_T::MVLD2: MSGVAL Position */ +#define CAN_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_MVLD2_MSGVAL_Pos) /*!< CAN_T::MVLD2: MSGVAL Mask */ + +/* CAN WUEN Bit Field Definitions */ +#define CAN_WU_EN_WAKUP_EN_Pos 0 /*!< CAN_T::WU_EN: WAKUP_EN Position */ +#define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */ + +/* CAN WUSTATUS Bit Field Definitions */ +#define CAN_WU_STATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WU_STATUS: WAKUP_STS Position */ +#define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */ + + +/**@}*/ /* CAN_CONST */ +/**@}*/ /* end of CAN register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __CAN_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/clk_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/clk_reg.h new file mode 100644 index 0000000000..7dbd310587 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/clk_reg.h @@ -0,0 +1,1815 @@ +/**************************************************************************//** + * @file clk_reg.h + * @version V1.00 + * @brief CLK register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CLK_REG_H__ +#define __CLK_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- System Clock Controller -------------------------*/ +/** + @addtogroup CLK System Clock Controller(CLK) + Memory Mapped Structure for CLK Controller + @{ +*/ + +typedef struct +{ + + /** + * @var CLK_T::PWRCTL + * Offset: 0x00 System Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTEN |HXT Enable Bit (Write Protect) + * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled. + * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: HXT cannot be disabled and HXTEN will always read as 1 if HCLK clock source is selected from HXT or PLL (clock source from HXT). + * |[1] |LXTEN |LXT Enable Bit (Write Protect) + * | | |0 = 32.768 kHz external low speed crystal (extLXT) Disabled. + * | | |1 = 32.768 kHz external low speed crystal (extLXT) Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: LXT cannot be disabled and LXTEN will always read as 1 if HCLK clock source is selected from LXT when the LXT clock source is selected as extLXT by setting C32KS(RTC_LXTCTL[7]) to 1. + * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) + * | | |The HCLK default clock source is from HIRC and this bit default value is 1. + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: HIRC cannot be disabled and HIRCEN will always read as 1 if HCLK clock source is selected from HIRC or PLL (clock source from HIRC). + * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) + * | | |0 = 32 kHz internal low speed RC oscillator (LIRC) Disabled. + * | | |1 = 32 kHz internal low speed RC oscillator (LIRC) Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: LIRC cannot be disabled and LIRCEN will always read as 1 if HCLK clock source is selected from LIRC. + * | | |Note3: If CWDTEN(CONFIG[31,4:3]) is set to 111, LIRC clock can be enabled or disabled by setting LIRCEN(CLK_PWRCTL[3]). + * | | |If CWDTEN(CONFIG0[31,4:3]) is not set to 111, LIRC cannot be disabled in normal mode and LIRCEN will always read as 1 + * | | |In Power-down mode, LIRC clock is controlled by LIRCEN(CLK_PWRCTL[3]) and CWDTPDEN (CONFIG0[30]) setting. + * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) + * | | |0 = Power-down mode wake-up interrupt Disabled. + * | | |1 = Power-down mode wake-up interrupt Enabled. + * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high, after resume from Power-down mode. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status + * | | |Set by Power-down wake-up event, it indicates that resume from Power-down mode. + * | | |The flag is set if the EINT7~0, GPIO, UART0~5, USBH, USBD, OTG, CAN0, BOD, ACMP, WDT, EWDT, SDH0, TIMER, I2C0~2, USCI0~1, RTC, TAMPER and CLKD wake-up occurred. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. + * |[7] |PDEN |System Power-down Enable (Write Protect) + * | | |When this bit is set to 1, Power-down mode is enabled and the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. + * | | |When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. + * | | |In Power-down mode, HXT, HIRC, HIRC48, PLL and system clock will be disabled and ignored the clock source selection. + * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT, LIRC or MIRC. + * | | |0 = Chip operating normally or chip in idle mode because of WFI command. + * | | |1 = Chip waits CPU sleep command WFI and then enters Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect) + * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally. + * | | |If gain control is enabled, crystal will consume more power than gain control off. + * | | |00 = HXT frequency is lower than from 8 MHz. + * | | |01 = HXT frequency is from 8 MHz to 12 MHz. + * | | |10 = HXT frequency is from 12 MHz to 16 MHz. + * | | |11 = HXT frequency is higher than 16 MHz. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) + * | | |0 = Select INV type. + * | | |1 = Select GM type. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |HXTTBEN |HXT Crystal TURBO Mode (Write Protect) + * | | |0 = HXT Crystal TURBO mode disabled. + * | | |1 = HXT Crystal TURBO mode enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[18] |HIRC48EN |HIRC48 Enable Bit (Write Protect) + * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48) Disabled. + * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48) Enabled. + * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: HIRC48 cannot be disabled and HIRC48EN will always read as 1 if HCLK clock source is selected from HIRC48. + * |[20] |MIRC1P2MEN|MIRC1P2M Enable Bit (Write Protect) + * | | |0 = 1.2 MHz internal medium speed RC oscillator (MIRC1P2M) Disabled. + * | | |1 = 1.2 MHz internal medium speed RC oscillator (MIRC1P2M) Enabled. + * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: This clock source only for LCD use. + * |[21] |MIRCEN |MIRC Enable Bit (Write Protect) + * | | |0 = 4 MHz internal medium speed RC oscillator (MIRC) Disabled. + * | | |1 = 4 MHz internal medium speed RC oscillator (MIRC) Enabled. + * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: MIRC cannot be disabled and MIRC will always read as 1 if HCLK clock source is selected from MIRC. + * @var CLK_T::AHBCLK + * Offset: 0x04 AHB Devices Clock Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMA0CKEN |PDMA0 Controller Clock Enable Bit (Secure) + * | | |0 = PDMA0 peripheral clock Disabled. + * | | |1 = PDMA0 peripheral clock Enabled. + * |[1] |PDMA1CKEN |PDMA1 Controller Clock Enable Bit + * | | |0 = PDMA1 peripheral clock Disabled. + * | | |1 = PDMA1 peripheral clock Enabled. + * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit + * | | |0 = Flash ISP peripheral clock Disabled. + * | | |1 = Flash ISP peripheral clock Enabled. + * |[3] |EBICKEN |EBI Controller Clock Enable Bit + * | | |0 = EBI peripheral clock Disabled. + * | | |1 = EBI peripheral clock Enabled. + * |[4] |EXSTCKEN |External System Tick Clock Enable Bit + * | | |0 = External System tick clock Disabled. + * | | |1 = External System tick clock Enabled. + * |[6] |SDH0CKEN |SDHOST0 Controller Clock Enable Bit + * | | |0 = SDHOST0 peripheral clock Disabled. + * | | |1 = SDHOST0 peripheral clock Enabled. + * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit + * | | |0 = CRC peripheral clock Disabled. + * | | |1 = CRC peripheral clock Enabled. + * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit + * | | |0 = Cryptographic Accelerator clock Disabled. + * | | |1 = Cryptographic Accelerator clock Enabled. + * |[13] |KSCKEN |Key Store Clock Enable Bit + * | | |0 = Key store clock Disabled. + * | | |1 = Key store clock Enabled. + * |[14] |TRACECKEN |Trace Clock Enable Bit + * | | |0 = Trace clock Disabled. + * | | |1 = Trace clock Enabled. + * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode + * | | |0 = FMC clock Disabled when chip is under IDLE mode. + * | | |1 = FMC clock Enabled when chip is under IDLE mode. + * |[16] |USBHCKEN |USB HOST 1.1 Controller Clock Enable Bit + * | | |0 = USB HOST 1.1 peripheral clock Disabled. + * | | |1 = USB HOST 1.1 peripheral clock Enabled. + * |[20] |SRAM0CKEN |SRAM Bank0 Controller Clock Enable Bit + * | | |0 = SRAM bank0 clock Disabled. + * | | |1 = SRAM bank0 clock Enabled. + * |[21] |SRAM1CKEN |SRAM Bank1 Controller Clock Enable Bit + * | | |0 = SRAM bank1 clock Disabled. + * | | |1 = SRAM bank1 clock Enabled. + * |[22] |SRAM2CKEN |SRAM Bank2 Controller Clock Enable Bit + * | | |0 = SRAM bank2 clock Disabled. + * | | |1 = SRAM bank2 clock Enabled. + * |[24] |GPACKEN |GPIOA Clock Enable Bit + * | | |0 = GPIOA port clock Disabled. + * | | |1 = GPIOA port clock Enabled. + * |[25] |GPBCKEN |GPIOB Clock Enable Bit + * | | |0 = GPIOB port clock Disabled. + * | | |1 = GPIOB port clock Enabled. + * |[26] |GPCCKEN |GPIOC Clock Enable Bit + * | | |0 = GPIOC port clock Disabled. + * | | |1 = GPIOC port clock Enabled. + * |[27] |GPDCKEN |GPIOD Clock Enable Bit + * | | |0 = GPIOD port clock Disabled. + * | | |1 = GPIOD port clock Enabled. + * |[28] |GPECKEN |GPIOE Clock Enable Bit + * | | |0 = GPIOE port clock Disabled. + * | | |1 = GPIOE port clock Enabled. + * |[29] |GPFCKEN |GPIOF Clock Enable Bit + * | | |0 = GPIOF port clock Disabled. + * | | |1 = GPIOF port clock Enabled. + * |[30] |GPGCKEN |GPIOG Clock Enable Bit + * | | |0 = GPIOG port clock Disabled. + * | | |1 = GPIOG port clock Enabled. + * |[31] |GPHCKEN |GPIOH Clock Enable Bit + * | | |0 = GPIOH port clock Disabled. + * | | |1 = GPIOH port clock Enabled. + * @var CLK_T::APBCLK0 + * Offset: 0x08 APB Devices Clock Enable Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) + * | | |0 = Watchdog timer and Windows watchdog timer clock Disabled. + * | | |1 = Watchdog timer and Windows watchdog timer clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit + * | | |This bit is used to control the RTC APB clock only. + * | | |The RTC peripheral clock source is selected from RTCCKSEL(RTC_LXTCTL[7]). + * | | |It can be selected to 32.768 kHz external low speed crystal (LXT) or 32 kHz internal low speed RC oscillator (LIRC). + * | | |0 = RTC clock Disabled. + * | | |1 = RTC clock Enabled. + * |[2] |TMR0CKEN |Timer0 Clock Enable Bit + * | | |0 = Timer0 clock Disabled. + * | | |1 = Timer0 clock Enabled. + * |[3] |TMR1CKEN |Timer1 Clock Enable Bit + * | | |0 = Timer1 clock Disabled. + * | | |1 = Timer1 clock Enabled. + * |[4] |TMR2CKEN |Timer2 Clock Enable Bit + * | | |0 = Timer2 clock Disabled. + * | | |1 = Timer2 clock Enabled. + * |[5] |TMR3CKEN |Timer3 Clock Enable Bit + * | | |0 = Timer3 clock Disabled. + * | | |1 = Timer3 clock Enabled. + * |[6] |CLKOCKEN |CLKO Clock Enable Bit + * | | |0 = CLKO clock Disabled. + * | | |1 = CLKO clock Enabled. + * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit + * | | |0 = Analog comparator 0/1 clock Disabled. + * | | |1 = Analog comparator 0/1 clock Enabled. + * |[8] |I2C0CKEN |I2C0 Clock Enable Bit + * | | |0 = I2C0 clock Disabled. + * | | |1 = I2C0 clock Enabled. + * |[9] |I2C1CKEN |I2C1 Clock Enable Bit + * | | |0 = I2C1 clock Disabled. + * | | |1 = I2C1 clock Enabled. + * |[10] |I2C2CKEN |I2C2 Clock Enable Bit + * | | |0 = I2C2 clock Disabled. + * | | |1 = I2C2 clock Enabled. + * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit + * | | |0 = QSPI0 clock Disabled. + * | | |1 = QSPI0 clock Enabled. + * |[13] |SPI0CKEN |SPI0 Clock Enable Bit + * | | |0 = SPI0 clock Disabled. + * | | |1 = SPI0 clock Enabled. + * |[14] |SPI1CKEN |SPI1 Clock Enable Bit + * | | |0 = SPI1 clock Disabled. + * | | |1 = SPI1 clock Enabled. + * |[15] |SPI2CKEN |SPI2 Clock Enable Bit + * | | |0 = SPI2 clock Disabled. + * | | |1 = SPI2 clock Enabled. + * |[16] |UART0CKEN |UART0 Clock Enable Bit + * | | |0 = UART0 clock Disabled. + * | | |1 = UART0 clock Enabled. + * |[17] |UART1CKEN |UART1 Clock Enable Bit + * | | |0 = UART1 clock Disabled. + * | | |1 = UART1 clock Enabled. + * |[18] |UART2CKEN |UART2 Clock Enable Bit + * | | |0 = UART2 clock Disabled. + * | | |1 = UART2 clock Enabled. + * |[19] |UART3CKEN |UART3 Clock Enable Bit + * | | |0 = UART3 clock Disabled. + * | | |1 = UART3 clock Enabled. + * |[20] |UART4CKEN |UART4 Clock Enable Bit + * | | |0 = UART4 clock Disabled. + * | | |1 = UART4 clock Enabled. + * |[21] |UART5CKEN |UART5 Clock Enable Bit + * | | |0 = UART5 clock Disabled. + * | | |1 = UART5 clock Enabled. + * |[24] |CAN0CKEN |CAN0 Clock Enable Bit + * | | |0 = CAN0 clock Disabled. + * | | |1 = CAN0 clock Enabled. + * |[26] |OTGCKEN |USB OTG Clock Enable Bit + * | | |0 = USB OTG clock Disabled. + * | | |1 = USB OTG clock Enabled. + * |[27] |USBDCKEN |USB Device Clock Enable Bit + * | | |0 = USB Device clock Disabled. + * | | |1 = USB Device clock Enabled. + * |[28] |EADCCKEN |Enhanced Analog-digital-converter (EADC) Clock Enable Bit + * | | |0 = EADC clock Disabled. + * | | |1 = EADC clock Enabled. + * |[29] |I2S0CKEN |I2S0 Clock Enable Bit + * | | |0 = I2S0 Clock Disabled. + * | | |1 = I2S0 Clock Enabled. + * |[31] |EWDTCKEN |Extra Watchdog Timer Clock Enable Bit (Write Protect) + * | | |0 = Extra Watchdog timer and Extra Windows watchdog timer clock Disabled. + * | | |1 = Extra Watchdog timer and Extra Windows watchdog timer clock Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::APBCLK1 + * Offset: 0x0C APB Devices Clock Enable Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0CKEN |Smart Card 0 (SC0) Clock Enable Bit + * | | |0 = SC0 clock Disabled. + * | | |1 = SC0 clock Enabled. + * |[1] |SC1CKEN |Smart Card 1 (SC1) Clock Enable Bit + * | | |0 = SC1 clock Disabled. + * | | |1 = SC1 clock Enabled. + * |[2] |SC2CKEN |Smart Card 2 (SC2) Clock Enable Bit + * | | |0 = SC2 clock Disabled. + * | | |1 = SC2 clock Enabled. + * |[4] |TMR4CKEN |Timer4 Clock Enable Bit + * | | |0 = Timer4 clock Disabled. + * | | |1 = Timer4 clock Enabled. + * |[5] |TMR5CKEN |Timer5 Clock Enable Bit + * | | |0 = Timer5 clock Disabled. + * | | |1 = Timer5 clock Enabled. + * |[6] |SPI3CKEN |SPI3 Clock Enable Bit + * | | |0 = SPI3 clock Disabled. + * | | |1 = SPI3 clock Enabled. + * |[8] |USCI0CKEN |USCI0 Clock Enable Bit + * | | |0 = USCI0 clock Disabled. + * | | |1 = USCI0 clock Enabled. + * |[9] |USCI1CKEN |USCI1 Clock Enable Bit + * | | |0 = USCI1 clock Disabled. + * | | |1 = USCI1 clock Enabled. + * |[12] |DACCKEN |DAC Clock Enable Bit + * | | |0 = DAC clock Disabled. + * | | |1 = DAC clock Enabled. + * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit + * | | |0 = EPWM0 clock Disabled. + * | | |1 = EPWM0 clock Enabled. + * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit + * | | |0 = EPWM1 clock Disabled. + * | | |1 = EPWM1 clock Enabled. + * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit + * | | |0 = BPWM0 clock Disabled. + * | | |1 = BPWM0 clock Enabled. + * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit + * | | |0 = BPWM1 clock Disabled. + * | | |1 = BPWM1 clock Enabled. + * |[22] |QEI0CKEN |QEI0 Clock Enable Bit + * | | |0 = QEI0 clock Disabled. + * | | |1 = QEI0 clock Enabled. + * |[23] |QEI1CKEN |QEI1 Clock Enable Bit + * | | |0 = QEI1 clock Disabled. + * | | |1 = QEI1 clock Enabled. + * |[25] |TRNGCKEN |TRNG Clock Enable Bit + * | | |0 = TRNG clock Disabled. + * | | |1 = TRNG clock Enabled. + * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit + * | | |0 = ECAP0 clock Disabled. + * | | |1 = ECAP0 clock Enabled. + * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit + * | | |0 = ECAP1 clock Disabled. + * | | |1 = ECAP1 clock Enabled. + * |[28] |LCDCPCKEN |LCD Charge Pump Clock Enable Bit + * | | |0 = LCD charge pump clock Disabled. + * | | |1 = LCD charge pump clock Enabled. + * @var CLK_T::CLKSEL0 + * Offset: 0x10 Clock Source Select Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) + * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. + * | | |000 = Clock source from HXT. + * | | |001 = Clock source from LXT. + * | | |010 = Clock source from PLL. + * | | |011 = Clock source from LIRC. + * | | |100 = Reserved. + * | | |101 = Clock source from HIRC48. + * | | |110 = Clock source from MIRC. + * | | |111 = Clock source from HIRC. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[5:3] |STCLKSEL |SysTick Clock Source Selection (Write Protect) + * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. + * | | |000 = Clock source from HXT. + * | | |001 = Clock source from LXT. + * | | |010 = Clock source from HXT/2. + * | | |011 = Clock source from HCLK/2. + * | | |111 = Clock source from HIRC/2. + * | | |Others = Reserved. + * | | |Note1: if SysTick clock source is not from HCLK (i.e SYST_CTRL[2] = 0), + * | | |SysTick need to enable EXSTCKEN(CLK_AHBCLK[4]) and clock frequency must less than or equal to HCLK/2. + * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[8] |USBSEL |USB Clock Source Selection (Write Protect) + * | | |0 = Clock source from HIRC48. + * | | |1 = Clock source from PLL. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[21:20] |SDH0SEL |SDHOST0 Peripheral Clock Source Selection (Write Protect) + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from HIRC clock. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::CLKSEL1 + * Offset: 0x14 Clock Source Select Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) + * | | |00 = Reserved. + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[2] |LCDSEL |LCD Clock Source Selection + * | | |0 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |1 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * |[3] |LCDCPSEL |LCD Charge Pump Clock Source Selection + * | | |0 = Clock source from 1.2 MHz internal medium speed RC oscillator (MIRC1P2M). + * | | |1 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). + * |[5:4] |EWDTSEL |Extra Watchdog Timer Clock Source Selection (Write Protect) + * | | |00 = Reserved. + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[7:6] |EWWDTSEL |Extra Window Watchdog Timer Clock Source Selection (Write Protect) + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM0 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM1 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM2 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK1. + * | | |011 = Clock source from external clock TM3 pin. + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |Others = Reserved. + * |[29:28] |CLKOSEL |Clock Output Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |10 = Clock source from HCLK. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection (Write Protect) + * | | |10 = Clock source from HCLK/2048. + * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::CLKSEL2 + * Offset: 0x18 Clock Source Select Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EPWM0SEL |EPWM0 Clock Source Selection (Read Only) + * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. + * | | |1 = Clock source from PCLK0. + * |[1] |EPWM1SEL |EPWM1 Clock Source Selection (Read Only) + * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. + * | | |1 = Clock source from PCLK1. + * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |SPI0SEL |SPI0 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[7:6] |SPI1SEL |SPI1 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[8] |BPWM0SEL |BPWM0 Clock Source Selection (Read Only) + * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. + * | | |1 = Clock source from PCLK0. + * |[9] |BPWM1SEL |BPWM1 Clock Source Selection (Read Only) + * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. + * | | |1 = Clock source from PCLK1. + * |[11:10] |SPI2SEL |SPI2 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[13:12] |SPI3SEL |SPI3 Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[18:16] |UART0SEL |UART0 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from PCLK0. + * | | |Others = Reserved. + * |[22:20] |UART1SEL |UART1 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from PCLK1. + * | | |Others = Reserved. + * |[26:24] |UART2SEL |UART2 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from PCLK0. + * | | |Others = Reserved. + * |[32:28] |UART3SEL |UART3 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from PCLK1. + * | | |Others = Reserved. + * @var CLK_T::CLKSEL3 + * Offset: 0x1C Clock Source Select Control Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SC0SEL |Smart Card 0 (SC0) Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[3:2] |SC1SEL |Smart Card 1 (SC1) Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK1. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[5:4] |SC2SEL |Smart Card 2 (SC2) Clock Source Selection + * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |01 = Clock source from PLL. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[10:8] |TMR4SEL |TIMER4 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM4 pin. + * | | |100 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |110 = Reserved. + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[14:12] |TMR5SEL |TIMER5 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |010 = Clock source from PCLK0. + * | | |011 = Clock source from external clock TM5 pin. + * | | |100 = Clock source from 4 MHz internal medium speed RC oscillator (MIRC). + * | | |101 = Clock source from 32 kHz internal low speed RC oscillator (LIRC). + * | | |110 = Reserved. + * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * |[17:16] |I2S0SEL |I2S0 Clock Source Selection + * | | |00 = Clock source from HXT clock. + * | | |01 = Clock source from PLL clock. + * | | |10 = Clock source from PCLK0. + * | | |11 = Clock source from HIRC clock. + * |[27:24] |UART4SEL |UART4 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from PCLK0. + * | | |Others = Reserved. + * |[28:30] |UART5SEL |UART5 Clock Source Selection + * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). + * | | |001 = Clock source from PLL. + * | | |010 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). + * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). + * | | |100 = Clock source from PCLK1. + * | | |Others = Reserved. + * @var CLK_T::CLKDIV0 + * Offset: 0x20 Clock Divider Number Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |HCLKDIV |HCLK Clock Divide Number from HCLK Clock Source + * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). + * |[7:4] |USBDIV |USB Clock Divide Number from USB Clock Source + * | | |USB clock frequency = (USB clock source frequency) / (USBDIV + 1). + * |[11:8] |UART0DIV |UART0 Clock Divide Number from UART0 Clock Source + * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). + * |[15:12] |UART1DIV |UART1 Clock Divide Number from UART1 Clock Source + * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). + * |[23:16] |EADCDIV |EADC Clock Divide Number from EADC Clock Source + * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). + * |[31:24] |SDH0DIV |SDHOST0 Clock Divide Number from SDHOST0 Clock Source + * | | |SDHOST0 clock frequency = (SDHOST0 clock source frequency) / (SDH0DIV + 1). + * @var CLK_T::CLKDIV1 + * Offset: 0x24 Clock Divider Number Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SC0DIV |Smart Card 0 (SC0) Clock Divide Number from SC0 Clock Source + * | | |SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1). + * |[15:8] |SC1DIV |Smart Card 1 (SC1) Clock Divide Number from SC1 Clock Source + * | | |SC1 clock frequency = (SC1 clock source frequency) / (SC1DIV + 1). + * |[23:16] |SC2DIV |Smart Card 2 (SC2) Clock Divide Number from SC2 Clock Source + * | | |SC2 clock frequency = (SC2 clock source frequency) / (SC2DIV + 1). + * @var CLK_T::CLKDIV4 + * Offset: 0x30 Clock Divider Number Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |UART2DIV |UART2 Clock Divide Number from UART2 Clock Source + * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). + * |[7:4] |UART3DIV |UART3 Clock Divide Number from UART3 Clock Source + * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). + * |[11:8] |UART4DIV |UART4 Clock Divide Number from UART4 Clock Source + * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). + * |[15:12] |UART5DIV |UART5 Clock Divide Number from UART5 Clock Source + * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). + * @var CLK_T::PLLCTL + * Offset: 0x40 PLL Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) + * | | |Refer to the PLL formulas. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) + * | | |Refer to the PLL formulas. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) + * | | |Refer to the PLL formulas. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[16] |PD |Power-down Mode (Write Protect) + * | | |0 = PLL is enable (in normal mode). + * | | |1 = PLL is disable (in Power-down mode) (default). + * | | |Note1: If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17] |BP |PLL Bypass Control (Write Protect) + * | | |0 = PLL is in normal mode (default). + * | | |1 = PLL clock output is same as PLL input clock FIN. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) + * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT). + * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) + * | | |0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12 MHz). + * | | |1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12 MHz). + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::STATUS + * Offset: 0x50 Clock Status Monitor Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. + * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) + * | | |LXT clock source can be selected as extLXT or LIRC32 by setting C32KS(RTC_LXTCTL[7]). + * | | |If C32KS is set to 0 the LXT stable flag is set when extLXT clock source is stable. + * | | |If C32KS is set to 1 the LXT stable flag is set when LIRC32 clock source is stable. + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. + * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) + * | | |0 = Internal PLL clock is not stable or disabled. + * | | |1 = Internal PLL clock is stable and enabled. + * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) + * | | |0 = 32 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. + * | | |1 = 32 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. + * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) + * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. + * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. + * |[5] |MIRCSTB |MIRC Clock Source Stable Flag (Read Only) + * | | |0 = 4 MHz internal medium speed RC oscillator (MIRC) clock is not stable or disabled. + * | | |1 = 4 MHz internal medium speed RC oscillator (MIRC) clock is stable and enabled. + * |[6] |HIRC48STB |HIRC48 Clock Source Stable Flag (Read Only) + * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48) clock is not stable or disabled. + * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48) clock is stable and enabled. + * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) + * | | |This bit is updated when software switches system clock source. + * | | |If switch target clock is stable, this bit will be set to 0. + * | | |If switch target clock is not stable, this bit will be set to 1. + * | | |0 = Clock switching success. + * | | |1 = Clock switching failure. + * | | |Note: This bit is read only. + * | | |After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. + * |[8] |EXTLXTSTB |EXTLXT Clock Source Stable Flag (Read Only) + * | | |0 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is not stable or disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (extLXT) clock is stable and enabled. + * |[9] |LIRC32STB |LIRC32 Clock Source Stable Flag (Read Only) + * | | |0 = 32 kHz internal low speed RC oscillator (LIRC32) clock is not stable or disabled. + * | | |1 = 32 kHz internal low speed RC oscillator (LIRC32) clock is stable and enabled. + * @var CLK_T::CLKOCTL + * Offset: 0x60 Clock Output Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |FREQSEL |Clock Output Frequency Selection + * | | |The formula of output frequency is Fout = Fin/2^(N+1). + * | | |Fin is the input clock frequency. + * | | |Fout is the frequency of divider output clock. + * | | |N is the 4-bit value of FREQSEL[3:0]. + * |[4] |CLKOEN |Clock Output Enable Bit + * | | |0 = Clock Output function Disabled. + * | | |1 = Clock Output function Enabled. + * |[5] |DIV1EN |Clock Output Divide One Enable Bit + * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. + * | | |1 = Clock Output will output clock with source frequency. + * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit + * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. + * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. + * @var CLK_T::CLKDCTL + * Offset: 0x70 Clock Fail Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. + * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. + * |[6] |HXTFDSEL |HXT Clock Fail Detector Selection + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector after HXT stable. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector bypass HXT stable. + * | | |Note: When HXT Clock Fail Detector Selection is set, detector will keep detect whether HXT is stable or not, prevent HXT fail before stable. + * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. + * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. + * |[16] |HXTFQDEN |HXT Clock Frequency Monitor Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor Enabled. + * |[17] |HXTFQIEN |HXT Clock Frequency Monitor Interrupt Enable Bit + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Disabled. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency monitor fail interrupt Enabled. + * @var CLK_T::CLKDSTS + * Offset: 0x74 Clock Fail Detector Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag (Write Protect) + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag (Write Protect) + * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. + * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |HXTFQIF |HXT Clock Frequency Monitor Interrupt Flag (Write Protect) + * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. + * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::CDUPB + * Offset: 0x78 Clock Frequency Detector Upper Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |UPERBD |HXT Clock Frequency Detector Upper Boundary + * | | |The bits define the high value of frequency monitor window. + * | | |When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1. + * @var CLK_T::CDLOWB + * Offset: 0x7C Clock Frequency Detector Lower Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |LOWERBD |HXT Clock Frequency Detector Lower Boundary + * | | |The bits define the low value of frequency monitor window. + * | | |When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1. + * @var CLK_T::PMUCTL + * Offset: 0x90 Power Manager Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) + * | | |These bits control chip Power-down mode grade selection when CPU execute WFI/WFE instruction. + * | | |000 = Power-down mode is selected (PD). + * | | |001 = Low leakage Power-down mode is selected (LLPD). + * | | |010 = Fast wake-up Power-down (FWPD). + * | | |011 = Ultra low leakage Power-down mode is selected (ULLPD). + * | | |100 = Standby Power-down mode is selected (SPD). + * | | |101 = Reserved. + * | | |110 = Deep Power-down mode is selected (DPD). + * | | |111 = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[4] |VDROPEN |Standby Power Down Mode Regulator Output Voltage Drop Enable Bit (Write Protect) + * | | |If this bit be asserted, regulator output voltage drop to 0.9V when SPD mode. + * | | |0 = Regulator voltage auto drop function Disabled. + * | | |1 = Regulator voltage auto drop function Enabled. (default) + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |WRBUSY |Write Busy Flag (Read Only) + * | | |If CLK_PMUCTL be written, this bit be asserted automatic by hardware, and be de-asserted when write procedure finish. + * | | |0 = CLK_PMUCTL write ready. + * | | |1 = CLK_PMUCTL write ignore. + * |[8] |WKTMREN |Wake-up Timer Enable Bit (Write Protect) + * | | |0 = Wake-up timer Disable in Deep Power-down mode or Standby Power-down mode. + * | | |1 = Wake-up timer Enabled in Deep Power-down mode or Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) + * | | |These bits control wake-up timer time-out interval when chip under Deep Power-down mode or Standby Power-down mode. + * | | |000 = Time-out interval is 410 LIRC clocks (12.8ms). + * | | |001 = Time-out interval is 819 LIRC clocks (25.6ms). + * | | |010 = Time-out interval is 1638 LIRC clocks (51.2ms). + * | | |011 = Time-out interval is 3277 LIRC clocks (102.4ms). + * | | |100 = Time-out interval is 13107 LIRC clocks (409.6ms). + * | | |101 = Time-out interval is 26214 LIRC clocks (819.2ms). + * | | |110 = Time-out interval is 52429 LIRC clocks (1638.4ms). + * | | |111 = Time-out interval is 209715 LIRC clocks (6553.6ms). + * |[17:16] |WKPINEN0 |Wake-up Pin 0 Enable (Write Protect) + * | | |This is control register for GPC.0 to wake-up pin. + * | | |00 = Wake-up pin Disable in Deep Power-down mode. + * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. + * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. + * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect) + * | | |0 = ACMP wake-up disable in Standby Power-down mode. + * | | |1 = ACMP wake-up enabled in Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[19] |TAMPERWK |Tamper Standby Power-down Mode Wake-up Enable Bit (Write Protect) + * | | |0 = Tamper wake-up disable at Standby Power-down mode. + * | | |1 = Tamper wake-up enabled at Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect) + * | | |This is a protected register. Please refer to open lock sequence to program it. + * | | |0 = RTC wake-up Disable in Deep Power-down mode or Standby Power-down mode. + * | | |1 = RTC wake-up Enabled in Deep Power-down mode or Standby Power-down mode. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[25:24] |WKPINEN1 |Wake-up Pin 1 Enable (Write Protect) + * | | |This is control register for GPB.0 to wake-up pin. + * | | |00 = Wake-up pin Disable in Deep Power-down mode. + * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. + * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. + * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[27:26] |WKPINEN2 |Wake-up Pin 2 Enable (Write Protect) + * | | |This is control register for GPB.2 to wake-up pin. + * | | |00 = Wake-up pin Disable in Deep Power-down mode. + * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. + * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. + * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[29:28] |WKPINEN3 |Wake-up Pin 3 Enable (Write Protect) + * | | |This is control register for GPB.12 to wake-up pin. + * | | |00 = Wake-up pin Disable in Deep Power-down mode. + * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. + * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. + * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[31:30] |WKPINEN4 |Wake-up Pin 4 Enable (Write Protect) + * | | |This is control register for GPF.6 to wake-up pin. + * | | |00 = Wake-up pin Disable in Deep Power-down mode. + * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode. + * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode. + * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var CLK_T::PMUSTS + * Offset: 0x94 Power Manager Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINWK0 |Pin 0 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPC.0). + * | | |This flag is cleared when DPD mode is entered. + * |[1] |TMRWK |Timer Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out. + * | | |This flag is cleared when DPD or SPD mode is entered. + * |[2] |RTCWK |RTC Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened. + * | | |This flag is cleared when DPD or SPD mode is entered. + * |[3] |PINWK1 |Pin 1 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPB.0). + * | | |This flag is cleared when DPD mode is entered. + * |[4] |PINWK2 |Pin 2 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPB.2). + * | | |This flag is cleared when DPD mode is entered. + * |[5] |PINWK3 |Pin 3 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPB.12). + * | | |This flag is cleared when DPD mode is entered. + * |[6] |PINWK4 |Pin 4 Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPF.6). + * | | |This flag is cleared when DPD mode is entered. + * |[8] |GPAWK |GPA Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPA group pins. + * | | |This flag is cleared when SPD mode is entered. + * |[9] |GPBWK |GPB Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPB group pins. + * | | |This flag is cleared when SPD mode is entered. + * |[10] |GPCWK |GPC Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPC group pins. + * | | |This flag is cleared when SPD mode is entered. + * |[11] |GPDWK |GPD Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPD group pins. + * | | |This flag is cleared when SPD mode is entered. + * |[12] |LVRWK |LVR Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a LVR happened. + * | | |This flag is cleared when SPD mode is entered. + * |[13] |BODWK |BOD Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a BOD happened. + * | | |This flag is cleared when SPD mode is entered. + * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only) + * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a ACMP transition. + * | | |This flag is cleared when SPD mode is entered. + * |[15] |TAMPERWK |Tamper Wake-up Flag (Read Only) + * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a Tamper event occurred. + * | | |This flag is cleared when SPD mode is entered. + * |[31] |CLRWK |Clear Wake-up Flag + * | | |0 = No clear. + * | | |1 = Clear all wake-up flag. + * | | |Note: This bit is auto cleared by hardware. + * @var CLK_T::SWKDBCTL + * Offset: 0x9C Standby Power-down Wake-up De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection + * | | |0000 = Sample wake-up input once per 1 clocks. + * | | |0001 = Sample wake-up input once per 2 clocks. + * | | |0010 = Sample wake-up input once per 4 clocks. + * | | |0011 = Sample wake-up input once per 8 clocks. + * | | |0100 = Sample wake-up input once per 16 clocks. + * | | |0101 = Sample wake-up input once per 32 clocks. + * | | |0110 = Sample wake-up input once per 64 clocks. + * | | |0111 = Sample wake-up input once per 128 clocks. + * | | |1000 = Sample wake-up input once per 256 clocks. + * | | |1001 = Sample wake-up input once per 2*256 clocks. + * | | |1010 = Sample wake-up input once per 4*256 clocks. + * | | |1011 = Sample wake-up input once per 8*256 clocks. + * | | |1100 = Sample wake-up input once per 16*256 clocks. + * | | |1101 = Sample wake-up input once per 32*256 clocks. + * | | |1110 = Sample wake-up input once per 64*256 clocks. + * | | |1111 = Sample wake-up input once per 128*256 clocks. + * | | |Note: De-bounce counter clock source is the 32 kHz internal low speed RC oscillator (LIRC). + * @var CLK_T::PASWKCTL + * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPA group pin wake-up function disabled. + * | | |1 = GPA group pin wake-up function Enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPA group pin rising edge wake-up function Disabled. + * | | |1 = GPA group pin rising edge wake-up function Enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPA group pin falling edge wake-up function Disabled. + * | | |1 = GPA group pin falling edge wake-up function Enabled. + * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select + * | | |0000 = GPA.0 wake-up function enabled. + * | | |0001 = GPA.1 wake-up function enabled. + * | | |0010 = GPA.2 wake-up function enabled. + * | | |0011 = GPA.3 wake-up function enabled. + * | | |0100 = GPA.4 wake-up function enabled. + * | | |0101 = GPA.5 wake-up function enabled. + * | | |0110 = GPA.6 wake-up function enabled. + * | | |0111 = GPA.7 wake-up function enabled. + * | | |1000 = GPA.8 wake-up function enabled. + * | | |1001 = GPA.9 wake-up function enabled. + * | | |1010 = GPA.10 wake-up function enabled. + * | | |1011 = GPA.11 wake-up function enabled. + * | | |1100 = GPA.12 wake-up function enabled. + * | | |1101 = GPA.13 wake-up function enabled. + * | | |1110 = GPA.14 wake-up function enabled. + * | | |1111 = GPA.15 wake-up function enabled. + * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. + * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator (LIRC). + * | | |0 = Standby power-down wake-up pin De-bounce function Disable. + * | | |1 = Standby power-down wake-up pin De-bounce function Enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PBSWKCTL + * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPB group pin wake-up function Disabled. + * | | |1 = GPB group pin wake-up function Enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPB group pin rising edge wake-up function Disabled. + * | | |1 = GPB group pin rising edge wake-up function Enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPB group pin falling edge wake-up function Disabled. + * | | |1 = GPB group pin falling edge wake-up function Enabled. + * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select + * | | |0000 = GPB.0 wake-up function enabled. + * | | |0001 = GPB.1 wake-up function enabled. + * | | |0010 = GPB.2 wake-up function enabled. + * | | |0011 = GPB.3 wake-up function enabled. + * | | |0100 = GPB.4 wake-up function enabled. + * | | |0101 = GPB.5 wake-up function enabled. + * | | |0110 = GPB.6 wake-up function enabled. + * | | |0111 = GPB.7 wake-up function enabled. + * | | |1000 = GPB.8 wake-up function enabled. + * | | |1001 = GPB.9 wake-up function enabled. + * | | |1010 = GPB.10 wake-up function enabled. + * | | |1011 = GPB.11 wake-up function enabled. + * | | |1100 = GPB.12 wake-up function enabled. + * | | |1101 = GPB.13 wake-up function enabled. + * | | |1110 = GPB.14 wake-up function enabled. + * | | |1111 = GPB.15 wake-up function enabled. + * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. + * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator (LIRC). + * | | |0 = Standby power-down wake-up pin De-bounce function Disable. + * | | |1 = Standby power-down wake-up pin De-bounce function Enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PCSWKCTL + * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPC group pin wake-up function Disabled. + * | | |1 = GPC group pin wake-up function Enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPC group pin rising edge wake-up function Disabled. + * | | |1 = GPC group pin rising edge wake-up function Enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPC group pin falling edge wake-up function Disabled. + * | | |1 = GPC group pin falling edge wake-up function Enabled. + * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select + * | | |0000 = GPC.0 wake-up function enabled. + * | | |0001 = GPC.1 wake-up function enabled. + * | | |0010 = GPC.2 wake-up function enabled. + * | | |0011 = GPC.3 wake-up function enabled. + * | | |0100 = GPC.4 wake-up function enabled. + * | | |0101 = GPC.5 wake-up function enabled. + * | | |0110 = GPC.6 wake-up function enabled. + * | | |0111 = GPC.7 wake-up function enabled. + * | | |1000 = GPC.8 wake-up function enabled. + * | | |1001 = GPC.9 wake-up function enabled. + * | | |1010 = GPC.10 wake-up function enabled. + * | | |1011 = GPC.11 wake-up function enabled. + * | | |1100 = GPC.12 wake-up function enabled. + * | | |1101 = GPC.13 wake-up function enabled. + * | | |1110 = Reserved. + * | | |1111 = Reserved. + * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. + * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). + * | | |0 = Standby power-down wake-up pin De-bounce function Disable. + * | | |1 = Standby power-down wake-up pin De-bounce function Enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::PDSWKCTL + * Offset: 0xAC GPD Standby Power-down Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit + * | | |0 = GPD group pin wake-up function Disabled. + * | | |1 = GPD group pin wake-up function Enabled. + * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit + * | | |0 = GPD group pin rising edge wake-up function Disabled. + * | | |1 = GPD group pin rising edge wake-up function Enabled. + * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit + * | | |0 = GPD group pin falling edge wake-up function Disabled. + * | | |1 = GPD group pin falling edge wake-up function Enabled. + * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select + * | | |0000 = GPD.0 wake-up function enabled. + * | | |0001 = GPD.1 wake-up function enabled. + * | | |0010 = GPD.2 wake-up function enabled. + * | | |0011 = GPD.3 wake-up function enabled. + * | | |0100 = GPD.4 wake-up function enabled. + * | | |0101 = GPD.5 wake-up function enabled. + * | | |0110 = GPD.6 wake-up function enabled. + * | | |0111 = GPD.7 wake-up function enabled. + * | | |1000 = GPD.8 wake-up function enabled. + * | | |1001 = GPD.9 wake-up function enabled. + * | | |1010 = GPD.10 wake-up function enabled. + * | | |1011 = GPD.11 wake-up function enabled. + * | | |1100 = GPD.12 wake-up function enabled. + * | | |1101 = Reserved. + * | | |1110 = GPD.14 wake-up function enabled. + * | | |1111 = Reserved. + * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit + * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup. + * | | |The de-bounce clock source is the 32 kHz internal low speed RC oscillator (LIRC). + * | | |0 = Standby power-down wake-up pin De-bounce function Disable. + * | | |1 = Standby power-down wake-up pin De-bounce function Enable. + * | | |The de-bounce function is valid only for edge triggered. + * @var CLK_T::IOPDCTL + * Offset: 0xB0 GPIO Standby Power-down Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IOHR |GPIO Hold Release + * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status. + * | | |After chip was waked up from standby Power-down mode, the I/O still keeps hold status until user sets this bit to release I/O hold status. + * | | |Note: This bit is auto cleared by hardware. + * @var CLK_T::HXTFSEL + * Offset: 0xB4 HXT Filter Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HXTFSEL |HXT Filter Select + * | | |0 = HXT frequency is > 12MHz. + * | | |1 = HXT frequency is <= 12MHz. + * | | |Note: This bit is auto cleared by hardware. + */ + + + __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ + __IO uint32_t AHBCLK; /*!< [0x0004] AHB Devices Clock Enable Control Register */ + __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ + __IO uint32_t APBCLK1; /*!< [0x000C] APB Devices Clock Enable Control Register 1 */ + __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ + __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ + __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ + __IO uint32_t CLKSEL3; /*!< [0x001C] Clock Source Select Control Register 3 */ + __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ + __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ + __I uint32_t RESERVE0[2]; + __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ + __I uint32_t RESERVE7[1]; + __I uint32_t RESERVE1[2]; + __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ + __I uint32_t RESERVE2[3]; + __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ + __I uint32_t RESERVE3[3]; + __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ + __I uint32_t RESERVE4[3]; + __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ + __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ + __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Detector Upper Boundary Register */ + __IO uint32_t CDLOWB; /*!< [0x007C] Clock Frequency Detector Low Boundary Register */ + __I uint32_t RESERVE5[4]; + __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ + __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ + __I uint32_t RESERVE6[1]; + __IO uint32_t SWKDBCTL; /*!< [0x009C] Standby Power-down Wake-up De-bounce Control Register */ + __IO uint32_t PASWKCTL; /*!< [0x00A0] GPA Standby Power-down Wake-up Control Register */ + __IO uint32_t PBSWKCTL; /*!< [0x00A4] GPB Standby Power-down Wake-up Control Register */ + __IO uint32_t PCSWKCTL; /*!< [0x00A8] GPC Standby Power-down Wake-up Control Register */ + __IO uint32_t PDSWKCTL; /*!< [0x00AC] GPD Standby Power-down Wake-up Control Register */ + __IO uint32_t IOPDCTL; /*!< [0x00B0] GPIO Standby Power-down Control Register */ + __IO uint32_t HXTFSEL; /*!< [0x00B4] HXT Filter Select Control Register */ + +} CLK_T; + +/** + @addtogroup CLK_CONST CLK Bit Field Definition + Constant Definitions for CLK Controller + @{ +*/ + +#define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ +#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ + +#define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ +#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ + +#define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ +#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ + +#define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ +#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ + +#define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ +#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ + +#define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ +#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ + +#define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ +#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ + +#define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */ +#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ + +#define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ +#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ + +#define CLK_PWRCTL_HXTTBEN_Pos (13) /*!< CLK_T::PWRCTL: HXTTBEN Position */ +#define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) /*!< CLK_T::PWRCTL: HXTTBEN Mask */ + +#define CLK_PWRCTL_HIRC48EN_Pos (18) /*!< CLK_T::PWRCTL: HIRC48EN Position */ +#define CLK_PWRCTL_HIRC48EN_Msk (0x1ul << CLK_PWRCTL_HIRC48EN_Pos) /*!< CLK_T::PWRCTL: HIRC48EN Mask */ + +#define CLK_PWRCTL_MIRC1P2MEN_Pos (20) /*!< CLK_T::PWRCTL: MIRC1P2MEN Position */ +#define CLK_PWRCTL_MIRC1P2MEN_Msk (0x1ul << CLK_PWRCTL_MIRC1P2MEN_Pos) /*!< CLK_T::PWRCTL: MIRC1P2MEN Mask */ + +#define CLK_PWRCTL_MIRCEN_Pos (21) /*!< CLK_T::PWRCTL: MIRCEN Position */ +#define CLK_PWRCTL_MIRCEN_Msk (0x1ul << CLK_PWRCTL_MIRCEN_Pos) /*!< CLK_T::PWRCTL: MIRCEN Mask */ + +#define CLK_AHBCLK_PDMA0CKEN_Pos (0) /*!< CLK_T::AHBCLK: PDMA0CKEN Position */ +#define CLK_AHBCLK_PDMA0CKEN_Msk (0x1ul << CLK_AHBCLK_PDMA0CKEN_Pos) /*!< CLK_T::AHBCLK: PDMA0CKEN Mask */ + +#define CLK_AHBCLK_PDMA1CKEN_Pos (1) /*!< CLK_T::AHBCLK: PDMA1CKEN Position */ +#define CLK_AHBCLK_PDMA1CKEN_Msk (0x1ul << CLK_AHBCLK_PDMA1CKEN_Pos) /*!< CLK_T::AHBCLK: PDMA1CKEN Mask */ + +#define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK: ISPCKEN Position */ +#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK_T::AHBCLK: ISPCKEN Mask */ + +#define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK: EBICKEN Position */ +#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK_T::AHBCLK: EBICKEN Mask */ + +#define CLK_AHBCLK_EXSTCKEN_Pos (4) /*!< CLK_T::AHBCLK: EXSTCKEN Position */ +#define CLK_AHBCLK_EXSTCKEN_Msk (0x1ul << CLK_AHBCLK_EXSTCKEN_Pos) /*!< CLK_T::AHBCLK: EXSTCKEN Mask */ + +#define CLK_AHBCLK_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK: SDH0CKEN Position */ +#define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK: SDH0CKEN Mask */ + +#define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK: CRCCKEN Position */ +#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK_T::AHBCLK: CRCCKEN Mask */ + +#define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK: CRPTCKEN Position */ +#define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK: CRPTCKEN Mask */ + +#define CLK_AHBCLK_KSCKEN_Pos (13) /*!< CLK_T::AHBCLK: KSCKEN Position */ +#define CLK_AHBCLK_KSCKEN_Msk (0x1ul << CLK_AHBCLK_KSCKEN_Pos) /*!< CLK_T::AHBCLK: KSCKEN Mask */ + +#define CLK_AHBCLK_TRACECKEN_Pos (14) /*!< CLK_T::AHBCLK: TRACECKEN Position */ +#define CLK_AHBCLK_TRACECKEN_Msk (0x1ul << CLK_AHBCLK_TRACECKEN_Pos) /*!< CLK_T::AHBCLK: TRACECKEN Mask */ + +#define CLK_AHBCLK_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK: FMCIDLE Position */ +#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) /*!< CLK_T::AHBCLK: FMCIDLE Mask */ + +#define CLK_AHBCLK_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK: USBHCKEN Position */ +#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK_T::AHBCLK: USBHCKEN Mask */ + +#define CLK_AHBCLK_SRAM0CKEN_Pos (20) /*!< CLK_T::AHBCLK: SRAM0CKEN Position */ +#define CLK_AHBCLK_SRAM0CKEN_Msk (0x1ul << CLK_AHBCLK_SRAM0CKEN_Pos) /*!< CLK_T::AHBCLK: SRAM0CKEN Mask */ + +#define CLK_AHBCLK_SRAM1CKEN_Pos (21) /*!< CLK_T::AHBCLK: SRAM1CKEN Position */ +#define CLK_AHBCLK_SRAM1CKEN_Msk (0x1ul << CLK_AHBCLK_SRAM1CKEN_Pos) /*!< CLK_T::AHBCLK: SRAM1CKEN Mask */ + +#define CLK_AHBCLK_SRAM2CKEN_Pos (22) /*!< CLK_T::AHBCLK: SRAM2CKEN Position */ +#define CLK_AHBCLK_SRAM2CKEN_Msk (0x1ul << CLK_AHBCLK_SRAM2CKEN_Pos) /*!< CLK_T::AHBCLK: SRAM2CKEN Mask */ + +#define CLK_AHBCLK_GPACKEN_Pos (24) /*!< CLK_T::AHBCLK: GPACKEN Position */ +#define CLK_AHBCLK_GPACKEN_Msk (0x1ul << CLK_AHBCLK_GPACKEN_Pos) /*!< CLK_T::AHBCLK: GPACKEN Mask */ + +#define CLK_AHBCLK_GPBCKEN_Pos (25) /*!< CLK_T::AHBCLK: GPBCKEN Position */ +#define CLK_AHBCLK_GPBCKEN_Msk (0x1ul << CLK_AHBCLK_GPBCKEN_Pos) /*!< CLK_T::AHBCLK: GPBCKEN Mask */ + +#define CLK_AHBCLK_GPCCKEN_Pos (26) /*!< CLK_T::AHBCLK: GPCCKEN Position */ +#define CLK_AHBCLK_GPCCKEN_Msk (0x1ul << CLK_AHBCLK_GPCCKEN_Pos) /*!< CLK_T::AHBCLK: GPCCKEN Mask */ + +#define CLK_AHBCLK_GPDCKEN_Pos (27) /*!< CLK_T::AHBCLK: GPDCKEN Position */ +#define CLK_AHBCLK_GPDCKEN_Msk (0x1ul << CLK_AHBCLK_GPDCKEN_Pos) /*!< CLK_T::AHBCLK: GPDCKEN Mask */ + +#define CLK_AHBCLK_GPECKEN_Pos (28) /*!< CLK_T::AHBCLK: GPECKEN Position */ +#define CLK_AHBCLK_GPECKEN_Msk (0x1ul << CLK_AHBCLK_GPECKEN_Pos) /*!< CLK_T::AHBCLK: GPECKEN Mask */ + +#define CLK_AHBCLK_GPFCKEN_Pos (29) /*!< CLK_T::AHBCLK: GPFCKEN Position */ +#define CLK_AHBCLK_GPFCKEN_Msk (0x1ul << CLK_AHBCLK_GPFCKEN_Pos) /*!< CLK_T::AHBCLK: GPFCKEN Mask */ + +#define CLK_AHBCLK_GPGCKEN_Pos (30) /*!< CLK_T::AHBCLK: GPGCKEN Position */ +#define CLK_AHBCLK_GPGCKEN_Msk (0x1ul << CLK_AHBCLK_GPGCKEN_Pos) /*!< CLK_T::AHBCLK: GPGCKEN Mask */ + +#define CLK_AHBCLK_GPHCKEN_Pos (31) /*!< CLK_T::AHBCLK: GPHCKEN Position */ +#define CLK_AHBCLK_GPHCKEN_Msk (0x1ul << CLK_AHBCLK_GPHCKEN_Pos) /*!< CLK_T::AHBCLK: GPHCKEN Mask */ + +#define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ +#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ + +#define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ +#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ + +#define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ +#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ + +#define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ +#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ + +#define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ +#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ + +#define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ +#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ + +#define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ +#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ + +#define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ +#define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ + +#define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ +#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ + +#define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ +#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ + +#define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ +#define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ + +#define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ +#define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ + +#define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ +#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ + +#define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ +#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ + +#define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ +#define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ + +#define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ +#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ + +#define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ +#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ + +#define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ +#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ + +#define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ +#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ + +#define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ +#define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ + +#define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ +#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ + +#define CLK_APBCLK0_TAMPERCKEN_Pos (22) /*!< CLK_T::APBCLK0: TAMPERCKEN Position */ +#define CLK_APBCLK0_TAMPERCKEN_Msk (0x1ul << CLK_APBCLK0_TAMPERCKEN_Pos) /*!< CLK_T::APBCLK0: TAMPERCKEN Mask */ + +#define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */ +#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */ + +#define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ +#define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ + +#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ +#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ + +#define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ +#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ + +#define CLK_APBCLK0_EADCCKEN_Pos (28) /*!< CLK_T::APBCLK0: EADCCKEN Position */ +#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) /*!< CLK_T::APBCLK0: EADCCKEN Mask */ + +#define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */ +#define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */ + +#define CLK_APBCLK0_EWDTCKEN_Pos (31) /*!< CLK_T::APBCLK0: EWDTCKEN Position */ +#define CLK_APBCLK0_EWDTCKEN_Msk (0x1ul << CLK_APBCLK0_EWDTCKEN_Pos) /*!< CLK_T::APBCLK0: EWDTCKEN Mask */ + +#define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ +#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ + +#define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */ +#define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ + +#define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */ +#define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */ + +#define CLK_APBCLK1_TMR4CKEN_Pos (4) /*!< CLK_T::APBCLK1: TMR4CKEN Position */ +#define CLK_APBCLK1_TMR4CKEN_Msk (0x1ul << CLK_APBCLK1_TMR4CKEN_Pos) /*!< CLK_T::APBCLK1: TMR4CKEN Mask */ + +#define CLK_APBCLK1_TMR5CKEN_Pos (5) /*!< CLK_T::APBCLK1: TMR5CKEN Position */ +#define CLK_APBCLK1_TMR5CKEN_Msk (0x1ul << CLK_APBCLK1_TMR5CKEN_Pos) /*!< CLK_T::APBCLK1: TMR5CKEN Mask */ + +#define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ +#define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ + +#define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ +#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ + +#define CLK_APBCLK1_USCI1CKEN_Pos (9) /*!< CLK_T::APBCLK1: USCI1CKEN Position */ +#define CLK_APBCLK1_USCI1CKEN_Msk (0x1ul << CLK_APBCLK1_USCI1CKEN_Pos) /*!< CLK_T::APBCLK1: USCI1CKEN Mask */ + +#define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ +#define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ + +#define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ +#define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ + +#define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ +#define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ + +#define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ +#define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ + +#define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ +#define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ + +#define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: QEI0CKEN Position */ +#define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK_T::APBCLK1: QEI0CKEN Mask */ + +#define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: QEI1CKEN Position */ +#define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK_T::APBCLK1: QEI1CKEN Mask */ + +#define CLK_APBCLK1_LCDCKEN_Pos (24) /*!< CLK_T::APBCLK1: LCDCKEN Position */ +#define CLK_APBCLK1_LCDCKEN_Msk (0x1ul << CLK_APBCLK1_LCDCKEN_Pos) /*!< CLK_T::APBCLK1: LCKCKEN Mask */ + +#define CLK_APBCLK1_TRNGCKEN_Pos (25) /*!< CLK_T::APBCLK1: TRNGCKEN Position */ +#define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos) /*!< CLK_T::APBCLK1: TRNGCKEN Mask */ + +#define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ +#define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ + +#define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ +#define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ + +#define CLK_APBCLK1_LCDCPCKEN_Pos (28) /*!< CLK_T::APBCLK1: LCDCPCKEN Position */ +#define CLK_APBCLK1_LCDCPCKEN_Msk (0x1ul << CLK_APBCLK1_LCDCPCKEN_Pos) /*!< CLK_T::APBCLK1: LCDCPCKEN Mask */ + +#define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ +#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ + +#define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ +#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ + +#define CLK_CLKSEL0_USBSEL_Pos (8) /*!< CLK_T::CLKSEL0: USBSEL Position */ +#define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) /*!< CLK_T::CLKSEL0: USBSEL Mask */ + +#define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */ +#define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */ + +#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ +#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ + +#define CLK_CLKSEL1_LCDSEL_Pos (2) /*!< CLK_T::CLKSEL1: LCDSEL Position */ +#define CLK_CLKSEL1_LCDSEL_Msk (0x1ul << CLK_CLKSEL1_LCDSEL_Pos) /*!< CLK_T::CLKSEL1: LCDSEL Mask */ + +#define CLK_CLKSEL1_LCDCPSEL_Pos (3) /*!< CLK_T::CLKSEL1: LCDCPSEL Position */ +#define CLK_CLKSEL1_LCDCPSEL_Msk (0x1ul << CLK_CLKSEL1_LCDCPSEL_Pos) /*!< CLK_T::CLKSEL1: LCDCPSEL Mask */ + +#define CLK_CLKSEL1_EWDTSEL_Pos (4) /*!< CLK_T::CLKSEL1: EWDTSEL Position */ +#define CLK_CLKSEL1_EWDTSEL_Msk (0x3ul << CLK_CLKSEL1_EWDTSEL_Pos) /*!< CLK_T::CLKSEL1: EWDTSEL Mask */ + +#define CLK_CLKSEL1_EWWDTSEL_Pos (6) /*!< CLK_T::CLKSEL1: EWWDTSEL Position */ +#define CLK_CLKSEL1_EWWDTSEL_Msk (0x3ul << CLK_CLKSEL1_EWWDTSEL_Pos) /*!< CLK_T::CLKSEL1: EWWDTSEL Mask */ + +#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ +#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ + +#define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ +#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ + +#define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ +#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ + +#define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ +#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ + +#define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ +#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ + +#define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ +#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ + +#define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ +#define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ + +#define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ +#define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ + +#define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ +#define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ + +#define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ +#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ + +#define CLK_CLKSEL2_SPI1SEL_Pos (6) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ +#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ + +#define CLK_CLKSEL2_SPI2SEL_Pos (10) /*!< CLK_T::CLKSEL2: SPI2SEL Position */ +#define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) /*!< CLK_T::CLKSEL2: SPI2SEL Mask */ + +#define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ +#define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ + +#define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ +#define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ + +#define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */ +#define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */ + +#define CLK_CLKSEL2_UART0SEL_Pos (16) /*!< CLK_T::CLKSEL2: UART0SEL Position */ +#define CLK_CLKSEL2_UART0SEL_Msk (0x7ul << CLK_CLKSEL2_UART0SEL_Pos) /*!< CLK_T::CLKSEL2: UART0SEL Mask */ + +#define CLK_CLKSEL2_UART1SEL_Pos (20) /*!< CLK_T::CLKSEL2: UART1SEL Position */ +#define CLK_CLKSEL2_UART1SEL_Msk (0x7ul << CLK_CLKSEL2_UART1SEL_Pos) /*!< CLK_T::CLKSEL2: UART1SEL Mask */ + +#define CLK_CLKSEL2_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL2: UART2SEL Position */ +#define CLK_CLKSEL2_UART2SEL_Msk (0x7ul << CLK_CLKSEL2_UART2SEL_Pos) /*!< CLK_T::CLKSEL2: UART2SEL Mask */ + +#define CLK_CLKSEL2_UART3SEL_Pos (28) /*!< CLK_T::CLKSEL2: UART3SEL Position */ +#define CLK_CLKSEL2_UART3SEL_Msk (0x7ul << CLK_CLKSEL2_UART3SEL_Pos) /*!< CLK_T::CLKSEL2: UART3SEL Mask */ + +#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ +#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ + +#define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */ +#define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */ + +#define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */ +#define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */ + +#define CLK_CLKSEL3_TMR4SEL_Pos (8) /*!< CLK_T::CLKSEL3: TMR4SEL Position */ +#define CLK_CLKSEL3_TMR4SEL_Msk (0x7ul << CLK_CLKSEL3_TMR4SEL_Pos) /*!< CLK_T::CLKSEL3: TMR4SEL Mask */ + +#define CLK_CLKSEL3_TMR5SEL_Pos (12) /*!< CLK_T::CLKSEL3: TMR5SEL Position */ +#define CLK_CLKSEL3_TMR5SEL_Msk (0x7ul << CLK_CLKSEL3_TMR5SEL_Pos) /*!< CLK_T::CLKSEL3: TMR5SEL Mask */ + +#define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */ +#define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */ + +#define CLK_CLKSEL3_UART4SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART4SEL Position */ +#define CLK_CLKSEL3_UART4SEL_Msk (0x7ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */ + +#define CLK_CLKSEL3_UART5SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART5SEL Position */ +#define CLK_CLKSEL3_UART5SEL_Msk (0x7ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */ + +#define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ +#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ + +#define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ +#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ + +#define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ +#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ + +#define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ +#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ + +#define CLK_CLKDIV0_EADCDIV_Pos (16) /*!< CLK_T::CLKDIV0: EADCDIV Position */ +#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLK_T::CLKDIV0: EADCDIV Mask */ + +#define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */ +#define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */ + +#define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ +#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ + +#define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */ +#define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ + +#define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ +#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ + +#define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ +#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ + +#define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ +#define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ + +#define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ +#define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ + +#define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ +#define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ + +#define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ +#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ + +#define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ +#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ + +#define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ +#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ + +#define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ +#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ + +#define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ +#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ + +#define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ +#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ + +#define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ +#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ + +#define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ +#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ + +#define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ +#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ + +#define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ +#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ + +#define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ +#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ + +#define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ +#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ + +#define CLK_STATUS_MIRCSTB_Pos (5) /*!< CLK_T::STATUS: MIRCSTB Position */ +#define CLK_STATUS_MIRCSTB_Msk (0x1ul << CLK_STATUS_MIRCSTB_Pos) /*!< CLK_T::STATUS: MIRCSTB Mask */ + +#define CLK_STATUS_HIRC48STB_Pos (6) /*!< CLK_T::STATUS: HIRC48STB Position */ +#define CLK_STATUS_HIRC48STB_Msk (0x1ul << CLK_STATUS_HIRC48STB_Pos) /*!< CLK_T::STATUS: HIRC48STB Mask */ + +#define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ +#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ + +#define CLK_STATUS_EXTLXTSTB_Pos (8) /*!< CLK_T::STATUS: EXTLXTSTB Position */ +#define CLK_STATUS_EXTLXTSTB_Msk (0x1ul << CLK_STATUS_EXTLXTSTB_Pos) /*!< CLK_T::STATUS: EXTLXTSTB Mask */ + +#define CLK_STATUS_LIRC32STB_Pos (9) /*!< CLK_T::STATUS: LIRC32STB Position */ +#define CLK_STATUS_LIRC32STB_Msk (0x1ul << CLK_STATUS_LIRC32STB_Pos) /*!< CLK_T::STATUS: LIRC32STB Mask */ + +#define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ +#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ + +#define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ +#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ + +#define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ +#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ + +#define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ +#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ + +#define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ +#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ + +#define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ +#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ + +#define CLK_CLKDCTL_HXTFDSEL_Pos (6) /*!< CLK_T::CLKDCTL: HXTFDSEL Position */ +#define CLK_CLKDCTL_HXTFDSEL_Msk (0x1ul << CLK_CLKDCTL_HXTFDSEL_Pos) /*!< CLK_T::CLKDCTL: HXTFDSEL Mask */ + +#define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ +#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ + +#define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ +#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ + +#define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ +#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ + +#define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ +#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ + +#define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ +#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ + +#define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ +#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ + +#define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ +#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ + +#define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ +#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ + +#define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ +#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ + +#define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ +#define CLK_PMUCTL_PDMSEL_Msk (0x7ul<< CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ + +#define CLK_PMUCTL_VDROPEN_Pos (4) /*!< CLK_T::PMUCTL: VDROPEN Position */ +#define CLK_PMUCTL_VDROPEN_Msk (0x1ul<< CLK_PMUCTL_VDROPEN_Pos) /*!< CLK_T::PMUCTL: VDROPEN Mask */ + +#define CLK_PMUCTL_WRBUSY_Pos (7) /*!< CLK_T::PMUCTL: WRBUSY Position */ +#define CLK_PMUCTL_WRBUSY_Msk (0x1ul<< CLK_PMUCTL_WRBUSY_Pos) /*!< CLK_T::PMUCTL: WRBUSY Mask */ + +#define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ +#define CLK_PMUCTL_WKTMREN_Msk (0x1ul<< CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ + +#define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ +#define CLK_PMUCTL_WKTMRIS_Msk (0x7ul<< CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ + +#define CLK_PMUCTL_WKPINEN_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN Position */ +#define CLK_PMUCTL_WKPINEN_Msk (0x3ul<< CLK_PMUCTL_WKPINEN_Pos) /*!< CLK_T::PMUCTL: WKPINEN Mask */ + +#define CLK_PMUCTL_WKPINEN0_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN0 Position */ +#define CLK_PMUCTL_WKPINEN0_Msk (0x3ul<< CLK_PMUCTL_WKPINEN0_Pos) /*!< CLK_T::PMUCTL: WKPINEN0 Mask */ + +#define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */ +#define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul<< CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */ + +#define CLK_PMUCTL_TAMPERWK_Pos (19) /*!< CLK_T::PMUCTL: TAMPERWK Position */ +#define CLK_PMUCTL_TAMPERWK_Msk (0x1ul<< CLK_PMUCTL_TAMPERWK_Pos) /*!< CLK_T::PMUCTL: TAMPERWK Mask */ + +#define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ +#define CLK_PMUCTL_RTCWKEN_Msk (0x1ul<< CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ + +#define CLK_PMUCTL_WKPINEN1_Pos (24) /*!< CLK_T::PMUCTL: WKPINEN1 Position */ +#define CLK_PMUCTL_WKPINEN1_Msk (0x3ul << CLK_PMUCTL_WKPINEN1_Pos) /*!< CLK_T::PMUCTL: WKPINEN1 Mask */ + +#define CLK_PMUCTL_WKPINEN2_Pos (26) /*!< CLK_T::PMUCTL: WKPINEN2 Position */ +#define CLK_PMUCTL_WKPINEN2_Msk (0x3ul << CLK_PMUCTL_WKPINEN2_Pos) /*!< CLK_T::PMUCTL: WKPINEN2 Mask */ + +#define CLK_PMUCTL_WKPINEN3_Pos (28) /*!< CLK_T::PMUCTL: WKPINEN3 Position */ +#define CLK_PMUCTL_WKPINEN3_Msk (0x3ul << CLK_PMUCTL_WKPINEN3_Pos) /*!< CLK_T::PMUCTL: WKPINEN3 Mask */ + +#define CLK_PMUCTL_WKPINEN4_Pos (30) /*!< CLK_T::PMUCTL: WKPINEN4 Position */ +#define CLK_PMUCTL_WKPINEN4_Msk (0x3ul << CLK_PMUCTL_WKPINEN4_Pos) /*!< CLK_T::PMUCTL: WKPINEN4 Mask */ + +#define CLK_PMUSTS_PINWK0_Pos (0) /*!< CLK_T::PMUSTS: PINWK0 Position */ +#define CLK_PMUSTS_PINWK0_Msk (0x1ul << CLK_PMUSTS_PINWK0_Pos) /*!< CLK_T::PMUSTS: PINWK0 Mask */ + +#define CLK_PMUSTS_PINWK_Pos (0) /*!< CLK_T::PMUSTS: PINWK Position */ +#define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) /*!< CLK_T::PMUSTS: PINWK Mask */ + +#define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ +#define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ + +#define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ +#define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ + +#define CLK_PMUSTS_PINWK1_Pos (3) /*!< CLK_T::PMUSTS: PINWK1 Position */ +#define CLK_PMUSTS_PINWK1_Msk (0x1ul << CLK_PMUSTS_PINWK1_Pos) /*!< CLK_T::PMUSTS: PINWK1 Mask */ + +#define CLK_PMUSTS_PINWK2_Pos (4) /*!< CLK_T::PMUSTS: PINWK2 Position */ +#define CLK_PMUSTS_PINWK2_Msk (0x1ul << CLK_PMUSTS_PINWK2_Pos) /*!< CLK_T::PMUSTS: PINWK2 Mask */ + +#define CLK_PMUSTS_PINWK3_Pos (5) /*!< CLK_T::PMUSTS: PINWK3 Position */ +#define CLK_PMUSTS_PINWK3_Msk (0x1ul << CLK_PMUSTS_PINWK3_Pos) /*!< CLK_T::PMUSTS: PINWK3 Mask */ + +#define CLK_PMUSTS_PINWK4_Pos (6) /*!< CLK_T::PMUSTS: PINWK4 Position */ +#define CLK_PMUSTS_PINWK4_Msk (0x1ul << CLK_PMUSTS_PINWK4_Pos) /*!< CLK_T::PMUSTS: PINWK4 Mask */ + +#define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */ +#define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */ + +#define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */ +#define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */ + +#define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */ +#define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */ + +#define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */ +#define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */ + +#define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ +#define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ + +#define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ +#define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ + +#define CLK_PMUSTS_ACMPWK_Pos (14) /*!< CLK_T::PMUSTS: ACMPWK Position */ +#define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) /*!< CLK_T::PMUSTS: ACMPWK Mask */ + +#define CLK_PMUSTS_TAMPERWK_Pos (15) /*!< CLK_T::PMUSTS: TAMPERWK Position */ +#define CLK_PMUSTS_TAMPERWK_Msk (0x1ul << CLK_PMUSTS_TAMPERWK_Pos) /*!< CLK_T::PMUSTS: TAMPERWK Mask */ + +#define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ +#define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ + +#define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xFul<< CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */ + +#define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */ +#define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */ + +#define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */ +#define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */ + +#define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */ +#define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */ + +#define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */ +#define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */ + +#define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */ +#define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */ + +#define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */ +#define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */ + +#define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */ +#define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */ + +#define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */ +#define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */ + +#define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */ +#define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */ + +#define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */ +#define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */ + +#define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */ +#define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */ + +#define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */ +#define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */ + +#define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */ +#define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */ + +#define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */ +#define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */ + +#define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */ +#define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */ + +#define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */ +#define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */ + +#define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */ +#define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */ + +#define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */ +#define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */ + +#define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */ +#define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */ + +#define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */ +#define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */ + +#define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ +#define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ + +#define CLK_HXTFSEL_HXTFSEL_Pos (0) /*!< CLK_T::HXTFSEL: HXTFSEL Position */ +#define CLK_HXTFSEL_HXTFSEL_Msk (0x1ul << CLK_HXTFSEL_HXTFSEL_Pos) /*!< CLK_T::HXTFSEL: HXTFSEL Mask */ + + +/**@}*/ /* CLK_CONST */ +/**@}*/ /* end of CLK register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __CLK_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/crc_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/crc_reg.h new file mode 100644 index 0000000000..a539ab4eb6 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/crc_reg.h @@ -0,0 +1,153 @@ +/**************************************************************************//** + * @file crc_reg.h + * @version V1.00 + * @brief CRC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_REG_H__ +#define __CRC_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Cyclic Redundancy Check Controller -------------------------*/ +/** + @addtogroup CRC Cyclic Redundancy Check Controller(CRC) + Memory Mapped Structure for CRC Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var CRC_T::CTL + * Offset: 0x00 CRC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRCEN |CRC Channel Generator Enable Bit + * | | |Set this bit 1 to enable CRC generator for CRC operation. + * | | |0 = No effect. + * | | |1 = CRC operation generator is active. + * |[1] |CHKSINIT |Checksum Initialization + * | | |Set this bit will auto reload SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value. + * | | |0 = No effect. + * | | |1 = Reload SEED value to CHECKSUM register as CRC operation initial checksum value. + * | | |The others contents of CRC_CTL register will not be cleared. + * | | |Note1: This bit will be cleared automatically + * | | |Note2: Setting this bit will reload the seed value from CRC_SEED register as checksum initial value. + * |[24] |DATREV |Write Data Bit Order Reverse Enable Bit + * | | |This bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]) in CRC_DAT register. + * | | |0 = Bit order reversed for CRC_DATA write data in Disabled. + * | | |1 = Bit order reversed for CRC_DATA write data in Enabled (per byte). + * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB. + * |[25] |CHKSREV |Checksum Bit Order Reverse Enable Bit + * | | |This bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]). + * | | |0 = Bit order reverse for CRC CHECKSUMCRC checksum Disabled. + * | | |1 = Bit order reverse for CRC CHECKSUMCRC checksum Enabled. + * | | |Note: If the checksum result is 0xDD7B0F2E, the bit order reverse result for CRC checksum is 0x74F0DEBB. + * |[26] |DATFMT |Write Data 1's Complement Enable Bit + * | | |This bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0]). + * | | |0 = 1's complement for CRC_DATA writes data in Disabled. + * | | |1 = 1's complement for CRC_DATA writes data in Enabled. + * |[27] |CHKSFMT |Checksum 1's Complement Enable Bit + * | | |This bit is used to enable the 1's complement function for checksum result in CHECKSUM (CRC_CHECKSUM[31:0]) register. + * | | |0 = 1's complement for CRC CHECKSUM Disabled. + * | | |1 = 1's complement for CRC CHECKSUMCRC Enabled. + * |[29:28] |DATLEN |CPU Write Data Length + * | | |This field indicates the valid write data length of DATA (CRC_DAT[31:0]). + * | | |00 = Data length is 8-bit mode. + * | | |01 = Data length is 16-bit mode. + * | | |1x = Data length is 32-bit mode. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0] + * |[31:30] |CRCMODE |CRC Polynomial Mode + * | | |This field indicates the CRC operation polynomial mode. + * | | |00 = CRC-CCITT Polynomial mode. + * | | |01 = CRC-8 Polynomial mode. + * | | |10 = CRC-16 Polynomial mode. + * | | |11 = CRC-32 Polynomial mode. + * @var CRC_T::DAT + * Offset: 0x04 CRC Write Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATA |CRC Write Data Bits + * | | |User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation. + * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]. + * @var CRC_T::SEED + * Offset: 0x08 CRC Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |CRC Seed Value + * | | |This field indicates the CRC seed value. + * | | |Note1: This field SEED value will be reloaded to as checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) register) after perform CRC engine reset, CHKSINIT (CRC_CTL[1]) to 1. + * | | |Note2: The valid bits of CRC_SEED[31:0] is correlated to CRCMODE (CRC_CTL[31:30]). + * @var CRC_T::CHECKSUM + * Offset: 0x0C CRC Checksum Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CHECKSUM |CRC Checksum Results + * | | |This field indicates the CRC checksum result. + * | | |Note: The valid bits of CRC_CHECKSUM[31:0] is correlated to CRCMODE (CRC_CTL[31:30]). + */ + __IO uint32_t CTL; /*!< [0x0000] CRC Control Register */ + __IO uint32_t DAT; /*!< [0x0004] CRC Write Data Register */ + __IO uint32_t SEED; /*!< [0x0008] CRC Seed Register */ + __I uint32_t CHECKSUM; /*!< [0x000c] CRC Checksum Register */ + +} CRC_T; + +/** + @addtogroup CRC_CONST CRC Bit Field Definition + Constant Definitions for CRC Controller + @{ +*/ + +#define CRC_CTL_CRCEN_Pos (0) /*!< CRC_T::CTL: CRCEN Position */ +#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC_T::CTL: CRCEN Mask */ + +#define CRC_CTL_CHKSINIT_Pos (1) /*!< CRC_T::CTL: CHKSINIT Position */ +#define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) /*!< CRC_T::CTL: CHKSINIT Mask */ + +#define CRC_CTL_DATREV_Pos (24) /*!< CRC_T::CTL: DATREV Position */ +#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC_T::CTL: DATREV Mask */ + +#define CRC_CTL_CHKSREV_Pos (25) /*!< CRC_T::CTL: CHKSREV Position */ +#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC_T::CTL: CHKSREV Mask */ + +#define CRC_CTL_DATFMT_Pos (26) /*!< CRC_T::CTL: DATFMT Position */ +#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC_T::CTL: DATFMT Mask */ + +#define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC_T::CTL: CHKSFMT Position */ +#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC_T::CTL: CHKSFMT Mask */ + +#define CRC_CTL_DATLEN_Pos (28) /*!< CRC_T::CTL: DATLEN Position */ +#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC_T::CTL: DATLEN Mask */ + +#define CRC_CTL_CRCMODE_Pos (30) /*!< CRC_T::CTL: CRCMODE Position */ +#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC_T::CTL: CRCMODE Mask */ + +#define CRC_DAT_DATA_Pos (0) /*!< CRC_T::DAT: DATA Position */ +#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC_T::DAT: DATA Mask */ + +#define CRC_SEED_SEED_Pos (0) /*!< CRC_T::SEED: SEED Position */ +#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC_T::SEED: SEED Mask */ + +#define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC_T::CHECKSUM: CHECKSUM Position */ +#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CHECKSUM Mask */ + +/**@}*/ /* CRC_CONST */ +/**@}*/ /* end of CRC register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __CLK_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/crpt_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/crpt_reg.h new file mode 100644 index 0000000000..5862f2a1cd --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/crpt_reg.h @@ -0,0 +1,2083 @@ + /**************************************************************************//** + * @file crpt_reg.h + * @version V1.00 + * @brief CRPT register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRPT_REG_H__ +#define __CRPT_REG_H__ + + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Cryptographic Accelerator -------------------------*/ +/** + @addtogroup CRPT Cryptographic Accelerator(CRPT) + Memory Mapped Structure for CRPT Controller + @{ +*/ + +typedef struct +{ + + +/** + * @var CRPT_T::INTEN + * Offset: 0x00 Crypto Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIEN |AES Interrupt Enable Bit + * | | |0 = AES interrupt Disabled. + * | | |1 = AES interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. + * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. + * |[1] |AESEIEN |AES Error Flag Enable Bit + * | | |0 = AES error interrupt flag Disabled. + * | | |1 = AES error interrupt flag Enabled. + * |[16] |PRNGIEN |PRNG Interrupt Enable Bit + * | | |0 = PRNG interrupt Disabled. + * | | |1 = PRNG interrupt Enabled. + * |[17] |PRNGEIEN |PRNG Error Flag Enable Bit + * | | |0 = PRNG error interrupt flag Disabled. + * | | |1 = PRNG error interrupt flag Enabled. + * |[22] |ECCIEN |ECC Interrupt Enable Bit + * | | |0 = ECC interrupt Disabled. + * | | |1 = ECC interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine + * | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation. + * |[23] |ECCEIEN |ECC Error Interrupt Enable Bit + * | | |0 = ECC error interrupt flag Disabled. + * | | |1 = ECC error interrupt flag Enabled. + * |[24] |HMACIEN |SHA/HMAC Interrupt Enable Bit + * | | |0 = SHA/HMAC interrupt Disabled. + * | | |1 = SHA/HMAC interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when amount of data set in HMAC_DMA_CNT is fed into the SHA/HMAC engine + * | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation. + * |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Bit + * | | |0 = SHA/HMAC error interrupt flag Disabled. + * | | |1 = HMAC error interrupt flag Enabled. + * |[30] |RSAIEN |RSA Interrupt Enable Bit + * | | |0 = RSA interrupt Disabled. + * | | |1 = RSA interrupt Enabled. + * | | |Note: In DMA mode, an interrupt will be triggered when amount of data set in RSA_DMA_CNT is fed into the RSA engine. + * |[31] |RSAEIEN |RSA Error Interrupt Enable Bit + * | | |0 = RSA error interrupt flag Disabled. + * | | |1 = RSA error interrupt flag Enabled. + * @var CRPT_T::INTSTS + * Offset: 0x04 Crypto Interrupt Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |AESIF |AES Finish Interrupt Flag + * | | |0 = No AES interrupt. + * | | |1 = AES encryption/decryption done interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[1] |AESEIF |AES Error Flag + * | | |0 = No AES error. + * | | |1 = AES encryption/decryption error interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[16] |PRNGIF |PRNG Finish Interrupt Flag + * | | |0 = No PRNG interrupt. + * | | |1 = PRNG key generation done interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[17] |PRNGEIF |PRNGError Flag + * | | |0 = No PRNG error. + * | | |1 = PRNG key generation error interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[22] |ECCIF |ECC Finish Interrupt Flag + * | | |0 = No ECC interrupt. + * | | |1 = ECC operation done interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[23] |ECCEIF |ECC Error Flag + * | | |This register includes operating and setting error + * | | |The detail flag is shown in CRPT_ECC_STS register. + * | | |0 = No ECC error. + * | | |1 = ECC error interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag + * | | |0 = No SHA/HMAC interrupt. + * | | |1 = SHA/HMAC operation done interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[25] |HMACEIF |SHA/HMAC Error Flag + * | | |This register includes operating and setting error + * | | |The detail flag is shown in CRPT_HMAC_STS register. + * | | |0 = No SHA/HMAC error. + * | | |1 = SHA/HMAC error interrupt. + * | | |Note:This bit is cleared by writing 1, and it has no effect by writing 0. + * |[30] |RSAIF |RSA Finish Interrupt Flag + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No RSA interrupt. + * | | |1 = RSA operation done interrupt. + * |[31] |RSAEIF |RSA Error Interrupt Flag + * | | |This register includes operating and setting error + * | | |The detail flag is shown in CRPT_RSA_STS register. + * | | |This bit is cleared by writing 1, and it has no effect by writing 0. + * | | |0 = No RSA error. + * | | |1 = RSA error interrupt. + * @var CRPT_T::PRNG_CTL + * Offset: 0x08 PRNG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |Start PRNG Engine + * | | |0 = Stop PRNG engine. + * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx, which will be cleared when the new key is generated. + * |[1] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * |[5:2] |KEYSZ |PRNG Generate Key Size + * | | |0000 = 128 bits. + * | | |0001 = 163 bits. + * | | |0010 = 192 bits. + * | | |0011 = 224 bits. + * | | |0100 = 233 bits. + * | | |0101 = 255 bits. + * | | |0110 = 256 bits. + * | | |0111 = 283 bits (only for KS). + * | | |1000 = 384 bits (only for KS). + * | | |1001 = 409 bits (only for KS). + * | | |1010 = 512 bits (only for KS). + * | | |1011 = 521 bits (only for KS). + * | | |1100 = 571 bits (only for KS). + * | | |1101 = Reserved. + * | | |1110 = Reserved. + * | | |1111 = Reserved. + * | | |Note: 283~571 bits only generate for Key Store. + * |[6] |SEEDSEL |Seed Select + * | | |This bit can be set to 1 only after SEEDRDY (TRNG_CTL[9]) bit become to 1. + * | | |0 = Select the seed which is from PRNG. + * | | |1 = Select the seed which is from TRNG. (not from CRPT_PRNG_SEED) + * |[7] |SEEDSRC |Seed Source (Read Only) + * | | |0 = Seed is from PRNG. + * | | |1 = Seed is from TRNG. (not from CRPT_PRNG_SEED) + * | | |Note: This bit is cleared to u20180u2019 when SEEDSEL is 0. + * |[8] |BUSY |PRNG Busy (Read Only) + * | | |0 = PRNG engine is idle. + * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx. + * @var CRPT_T::PRNG_SEED + * Offset: 0x0C Seed for PRNG + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed for PRNG (Write Only) + * | | |The bits store the seed for PRNG engine. + * | | |Note: In TRNG+PRNG mode, the seed is from TRNGengine, and it will not store in this register. + * @var CRPT_T::PRNG_KEY + * Offset: 0x10-0x2C PRNG Generated Key + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Store PRNG Generated Key (Read Only) + * | | |The bits store the key that is generated by PRNG. + * @var CRPT_T::PRNG_STS + * Offset: 0x30 PRNG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |PRNG Busy Flag + * | | |0 = PRNG engine is idle. + * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx. + * |[16] |KCTLERR |PRNG Key Control Register Error Flag + * | | |0 = No error. + * | | |1 = PRNG key control error + * | | |When PRNG execute ECDSA or ECDH, but PRNG seed not from TRNG or key is not written to the SRAM of key store (WSDST,CRPT_PRNG_KSCTL[23:22] is not equal to u201900u2019). + * |[17] |KSERR |PRNG Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access key store fail. + * @var CRPT_T::AES_FDBCK + * Offset: 0x50-0x5C AES Engine Output Feedback Data After Cryptographic Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |AES Feedback Information + * | | |The feedback value is 128 bits in size. + * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AES_IVx for the next block in DMA cascade mode. + * | | |The AES engine outputs feedback information for IV in the next block operation + * | | |Software can use this feedback information to implement more than four DMA channels + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_AES_IVx in the same channel operation, and then continue the operation with the original setting. + * @var CRPT_T::AES_GCM_IVCNT + * Offset: 0x80-0x84 AES GCM IV Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES GCM IV Byte Count + * | | |The bit length of IV is 64 bits for AES GCM mode + * | | |The CRPT_AES_GCM_IVCNT keeps the low weightbyte count of initial vector (i.e., len(IV)[34:3])of AES GCM mode and can be read and written. + * @var CRPT_T::AES_GCM_ACNT + * Offset: 0x88-0x8C AES GCM A Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES GCM aByte Count + * | | |The bit length of A is 64 bits for AES GCM mode + * | | |The CRPT_AES_GCM_ACNT keeps the low weightbyte count of theadditional authenticated data (i.e., len(A)[34:3])of AES GCM mode and can be read and written. + * @var CRPT_T::AES_GCM_PCNT + * Offset: 0x90-0x94 AES GCM P Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES GCM PByte Count + * | | |The bit length of Por Cis 39 bits for AES GCM mode + * | | |The CRPT_AES_GCM_PCNT0 keeps the low weightbyte count of theplaintextor ciphertext (i.e., len(P)[34:3] or len(C)[34:3])of AES GCM mode and can be read and written. + * |[60:32] |CNT |AES GCM P Byte Count + * | | |The bit length of Por C is 39 bits for AES GCM mode + * | | |The CRPT_AES_GCM_PCNT1 keeps the high weightbyte count of theplaintext or ciphertext (i.e., len(P)[38:35] or len(C)[38:35])of AES GCM mode and can be read and written. + * | | |The bit length of Por C is 64 bits for AES CCM mode + * | | |The CRPT_AES_GCM_PCNT1 keeps the high weightbyte count of theplaintext or ciphertext (i.e., len(P)[63:35] or len(C)[63:35])of AES CCM mode and can be read and written. + * @var CRPT_T::AES_FBADDR + * Offset: 0xA0 AES DMA Feedback Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FBADDR |AES DMA Feedback Address + * | | |In DMA cascade mode, software can update DMA feedbackaddress register for automatically reading and writing feedback vaules via DMA.The FBADDR keeps the feedback address of the feedback data for the next cascade operation + * | | |Based on the feedback address, the AES accelerator can read thefeedback dataof the last cascade opeation from SRAM memory space and write thefeedback dataof the current cascade opeation to SRAM memory space + * | | |The start of feedback address should be located at word boundary + * | | |In other words, bit 1 and 0 of FBADDR are ignored. + * | | |FBADDR can be read and written. + * | | |In DMA mode, software can update the next CRPT_AES_FBADDR before triggering START. + * @var CRPT_T::AES_CTL + * Offset: 0x100 AES Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |AES Engine Start + * | | |0 = No effect. + * | | |1 = Start AES engine. BUSY flag will be set. + * | | |Note: This bit is always 0 when it read back. + * |[1] |STOP |AES Engine Stop + * | | |0 = No effect. + * | | |1 = Stop AES engine. + * | | |Note: This bit is always 0 when it read back. + * |[3:2] |KEYSZ |AES Key Size + * | | |This bit defines three different key size for AES operation. + * | | |2u2019b00 = 128 bits key. + * | | |2u2019b01 = 192 bits key. + * | | |2u2019b10 = 256 bits key. + * | | |2u2019b11 = Reserved. + * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. + * | | |Note:When SM4EN=1, the key size of AESmust be 128. + * |[5] |DMALAST |AES Last Block + * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. + * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. + * | | |This bit is always 0 when it read back. Must be written again once START is triggered. + * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |AES Engine DMA Enable Bit + * | | |0 = AES DMA engine Disabled. + * | | |The AES engine operates in Non-DMA mode. The data need to be written in CRPT_AES_DATIN. + * | | |1 = AES_DMA engine Enabled. + * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[15:8] |OPMODE |AES Engine Operation Modes + * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). + * | | |0x02 = CFB (Cipher Feedback Mode). + * | | |0x03 = OFB (Output Feedback Mode). + * | | |0x04 = CTR (Counter Mode). + * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode). + * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode). + * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode). + * | | |0x20 = GCM (Galois/Counter Mode). + * | | |0x21 = GHASH (Galois Hash Function). + * | | |0x22 = CCM (Counter with CBC-MAC Mode). + * |[16] |ENCRYPTO |AES Encryption/Decryption + * | | |0 = AES engine executes decryption operation. + * | | |1 = AES engine executes encryption operation. + * |[17] |SM4EN |SM4 Engine Enable + * | | |0 = Enable AES engine. + * | | |1 =Enable SM4 engine. + * |[20] |FBIN |Feedback Input to AES Via DMA Automatically + * | | |0 = Disable DMA automatical feedback input fucntion. + * | | |1 =Enable DMA automatical feedback input fucntion.when DMAEN = 1. + * |[21] |FBOUT |Feedback Output From AES Via DMA Automatically + * | | |0 = Disable DMA automatical feedback output fucntion. + * | | |1 =Enable DMA automatical feedback output fucntion when DMAEN = 1. + * |[22] |OUTSWAP |AES Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 =The order that CPU reads data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |AES Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 =The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[24] |KOUTSWAP |AES Engine Output Key, Initial Vector and Feedback Swap + * | | |0 = Keep the original order. + * | | |1 =The order that CPU readskey, initial vector and feeback from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[25] |KINSWAP |AES Engine Input Key and Initial Vector Swap + * | | |0 = Keep the original order. + * | | |1 =The order that CPU feeds key and initial vector to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[30:26] |KEYUNPRT |Unprotect Key + * | | |Writing 0 to CRPT_AES_CTL[31] and u201C10110u201D to CRPT_AES_CTL[30:26] is to unprotect theAES key. + * | | |The KEYUNPRT can be read and written + * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. + * |[31] |KEYPRT |Protect Key + * | | |Read as a flag to reflect KEYPRT. + * | | |0 = No effect. + * | | |1 = Protect the content of the AES key from reading + * | | |The return value for reading CRPT_AES_KEYx is not the content of the registers CRPT_AES_KEYx + * | | |Once it is set, it can be cleared by asserting KEYUNPRT + * | | |And the key content would be cleared as well. + * @var CRPT_T::AES_STS + * Offset: 0x104 AES Engine Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |AES Engine Busy + * | | |0 = The AES engine is idle or finished. + * | | |1 = The AES engine is under processing. + * |[8] |INBUFEMPTY|AES Input Buffer Empty + * | | |0 = There are some data in input buffer waiting for the AES engine to process. + * | | |1 = AES input buffer is empty + * | | |Software needs to feed data to the AES engine + * | | |Otherwise, the AES engine will be pending to wait for input data. + * |[9] |INBUFFULL |AES Input Buffer Full Flag + * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine. + * | | |1 = AES input buffer is full + * | | |Software cannot feed data to the AES engine + * | | |Otherwise, the flag INBUFERR will be set to 1. + * |[10] |INBUFERR |AES Input Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during feeding data to the AES engine. + * |[12] |CNTERR |CRPT_AES_CNT Setting Error + * | | |0 = No error in CRPT_AES_CNT setting. + * | | |1 = CRPT_AES_CNT is 0 or not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode if DMAEN (CRPT_AES_CTL[7]) is enabled. + * |[16] |OUTBUFEMPTY|AES Out Buffer Empty + * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer. + * | | |1 = AES output buffer is empty + * | | |Software cannot get data from CRPT_AES_DATOUT + * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty. + * |[17] |OUTBUFFULL|AES Out Buffer Full Flag + * | | |0 = AES output buffer is not full. + * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT + * | | |Otherwise, the AES engine will be pending since the output buffer is full. + * |[18] |OUTBUFERR |AES Out Buffer Error Flag + * | | |0 = No error. + * | | |1 = Error happens during getting the result from AES engine. + * |[20] |BUSERR |AES DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and AES engine. + * |[21] |KSERR |AES Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop AES engine. + * @var CRPT_T::AES_DATIN + * Offset: 0x108 AES Engine Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |AES Engine Input Port + * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0. + * @var CRPT_T::AES_DATOUT + * Offset: 0x10C AES Engine Data Output Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATOUT |AES Engine Output Port + * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS + * | | |Get data as OUTBUFEMPTY is 0. + * @var CRPT_T::AES_KEY + * Offset: 0x110-0x12C AES Key Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |CRPT_AES_KEYx + * | | |The KEY keeps the security key for AES operation. + * | | |x = 0, 1..7. + * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. + * | | |{CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 128-bit security key for AES operation. + * | | |{CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 192-bit security key for AES operation. + * | | |{CRPT_AES_KEY7, CRPT_AES_KEY6, CRPT_AES_KEY5, CRPT_AES_KEY4, CRPT_AES_KEY3, CRPT_AES_KEY2, CRPT_AES_KEY1, CRPT_AES_KEY0} stores the 256-bit security key for AES operation. + * @var CRPT_T::AES_IV + * Offset: 0x130-0x13C AES Initial Vector Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |IV |AES Initial Vectors + * | | |x = 0, 1..3. + * | | |Four initial vectors (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) are for AES operating in CBC, CFB, and OFB mode + * | | |Four registers (CRPT_AES_IV0, CRPT_AES_IV1, CRPT_AES_IV2, and CRPT_AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode. + * @var CRPT_T::AES_SADDR + * Offset: 0x140 AES DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |AES DMA Source Address + * | | |The AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO + * | | |The SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written + * | | |Writing to SADDR while the AES accelerator is operating doesnu2019t affect the current AES operation + * | | |But the value of SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AES_SADDR before triggering START. + * | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same. + * @var CRPT_T::AES_DADDR + * Offset: 0x144 AES DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |AES DMA Destination Address + * | | |The AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO + * | | |The DADDR keeps the destination address of the data buffer where the engine output text will be stored + * | | |Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished + * | | |The start of destination address should be located at word boundary + * | | |In other words, bit 1 and 0 of DADDR are ignored. + * | | |DADDR can be read and written + * | | |Writing to DADDR while the AES accelerator is operating doesnu2019t affect the current AES operation + * | | |But the value of DADDR will be updated later on + * | | |Consequently, software can prepare the destination address for the next AES operation. + * | | |In DMA mode, software can update the next CRPT_AES_DADDR before triggering START. + * | | |The value of CRPT_AES_SADDR and CRPT_AES_DADDR can be the same. + * @var CRPT_T::AES_CNT + * Offset: 0x148 AES Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |AES Byte Count + * | | |The CRPT_AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode + * | | |The CRPT_AES_CNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_AES_CNT can be read and written + * | | |Writing to CRPT_AES_CNT while the AES accelerator is operating doesnu2019t affect the current AES operation + * | | |But the value of CRPT_AES_CNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next AES operation. + * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes + * | | |Operations that are qual or less than one block will output unexpected result. + * | | |In Non-DMA ECB, CBC, CFB, OFB, CTR, CCM and GCM mode, CRPT_AES_CNT must be set as byte count for the last block of data before feeding in the last block of data + * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. + * | | |In AES GCM mode without DMA cascade fucntion, the value of CRPT_AES_CNT is equal to the total value of{CRPT_AES_GCM_IVCNT1, CRPT_AES_GCM_IVCNT0}, {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0}. + * | | |In AES GCM mode with DMA cascade fucntion,the value of CRPT_AES_CNT represents the byte count of source text in this cascade function + * | | |Thus, the value of CRPT_AES_CNT is less than or equal to the total value of {CRPT_AES_GCM_IVCNT1, CRPT_AES_GCM_IVCNT0}, {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0} and must be block alignment. + * | | |In AES CCM mode without DMA cascade fucntion, the value of CRPT_AES_CNT is equal to the total value of {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0}. + * | | |In AES CCM mode with DMA cascade fucntion,the value of CRPT_AES_CNT represents the byte count of source text in this cascade function + * | | |Thus, the value of CRPT_AES_CNT is less than or equal to the total value of {CRPT_AES_GCM_ACNT1, CRPT_AES_GCM_ACNT0} and {CRPT_AES_GCM_PCNT1, CRPT_AES_GCM_PCNT0} and must be block alignment, except for the last block of plaintext or ciphertext. + * @var CRPT_T::HMAC_CTL + * Offset: 0x300 SHA/HMAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |SHA/HMAC Engine Start + * | | |0 = No effect. + * | | |1 = Start SHA/HMAC engine. BUSY flag will be set. + * | | |Note: This bit is always 0 when it read back. + * |[1] |STOP |SHA/HMAC Engine Stop + * | | |0 = No effect. + * | | |1 = Stop SHA/HMAC engine. + * | | |Note: This bit is always 0 when it read back. + * |[4] |DMAFIRST |SHA/HMAC First Blockin Cascadefunction + * | | |This bit must be set as feeding in first byte of data. + * |[5] |DMALAST |SHA/HMAC Last Block + * | | |This bit must be set as feeding in last byte of data. + * |[6] |DMACSCAD |SHA/HMAC Engine DMA with Cascade Mode + * | | |0 = DMA cascade function Disabled. + * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. + * |[7] |DMAEN |SHA/HMAC Engine DMA Enable Bit + * | | |0 = SHA/HMAC DMA engine Disabled. + * | | |SHA/HMAC engine operates in Non-DMA mode. The data need to be written in CRPT_HMAC_DATIN. + * | | |1 = SHA/HMAC DMA engine Enabled. + * | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. + * |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes + * | | |0x0xx: SHA1-160 + * | | |0x100: SHA2-256 + * | | |0x101: SHA2-224 + * | | |0x110: SHA2-512 + * | | |0x111: SHA2-384 + * | | |Note: These bits can be read and written. But writing tothem wouldnu2019t take effect as BUSY is 1.. + * | | |Note:When SM3EN=1, SHA/HMAC only execute SM3-256. + * |[11] |HMACEN |HMAC_SHA Engine Operating Mode + * | | |0 = Execute SHA function. + * | | |1 = Execute HMAC function. + * |[13] |SM3EN |SM3 Engine Enable Bit + * | | |0 = Execute other function. + * | | |1 = Execute SM3 function. + * |[20] |FBIN |Feedback Input to SHA/HMAC Via DMA Automatically + * | | |0 = Disable DMA automatical feedback input fucntion.. + * | | |1 = Enable DMA automatical feedback input fucntion when DMAEN = 1. + * |[21] |FBOUT |Feedback Output From SHA/HMAC Via DMA Automatically + * | | |0 = Disable DMA automatical feedback output fucntion.. + * | | |1 = Enable DMA automatical feedback output fucntion when DMAEN = 1. + * |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * |[23] |INSWAP |SHA/HMAC Engine Input Data Swap + * | | |0 = Keep the original order. + * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. + * @var CRPT_T::HMAC_STS + * Offset: 0x304 SHA/HMAC Status Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |SHA/HMAC Engine Busy + * | | |0 = SHA/HMAC engine is idle or finished. + * | | |1 = SHA/HMAC engine is busy. + * |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag + * | | |0 = SHA/HMAC DMA engine is idle or finished. + * | | |1 = SHA/HMAC DMA engine is busy. + * |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag + * | | |0 = Show the SHA/HMAC engine access normal. + * | | |1 = Show the SHA/HMAC engine access error. + * |[9] |KSERR |HMAC Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop HMAC engine. + * |[16] |DATINREQ |SHA/HMAC Non-dMA Mode Data Input Request + * | | |0 = No effect. + * | | |1 = Request SHA/HMAC Non-DMA mode data input. + * @var CRPT_T::HMAC_DGST + * Offset: 0x308-0x344 SHA/HMAC Output Feedback Data + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DGST |SHA/HMACOutput Feedback Data Output Register + * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. + * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. + * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. + * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. + * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. + * @var CRPT_T::HMAC_KEYCNT + * Offset: 0x348 SHA/HMAC Key Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEYCNT |SHA/HMAC Key Byte Count + * | | |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates + * | | |The register is 32-bit and the maximum byte count is 4G bytes + * | | |It can be read and written. + * | | |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesnu2019t affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_KEYCNT will be updated later on + * | | |Consequently, software can prepare the key count for the next SHA/HMAC operation. + * @var CRPT_T::HMAC_SADDR + * Offset: 0x34C SHA/HMAC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |SHA/HMAC DMA Source Address + * | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO + * | | |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored + * | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from SRAM memory space and do SHA/HMAC operation + * | | |The start of source address should be located at word boundary + * | | |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored. + * | | |CRPT_HMAC_SADDR can be read and written + * | | |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesnu2019t affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_SADDR will be updated later on + * | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation. + * | | |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START. + * | | |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value. + * @var CRPT_T::HMAC_DMACNT + * Offset: 0x350 SHA/HMAC Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DMACNT |SHA/HMAC Operation Byte Count + * | | |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode + * | | |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes. + * | | |CRPT_HMAC_DMACNT can be read and written + * | | |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesnu2019t affect the current SHA/HMAC operation + * | | |But the value of CRPT_HMAC_DMACNT will be updated later on + * | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation. + * | | |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data. + * @var CRPT_T::HMAC_DATIN + * Offset: 0x354 SHA/HMAC Engine Non-dMA Mode Data Input Port Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DATIN |SHA/HMAC Engine Input Port + * | | |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS + * | | |Feed data as DATINREQ is 1. + * @var CRPT_T::HMAC_FDBCK + * Offset: 0x358-0x42C SHA/HMAC Output Feedback Data After SHA/HMAC Operation + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FDBCK |SHA/HMAC Feedback Information + * | | |The feedback value is 1728 bits in size for SHA1/2. + * | | |The SHA/HMAC engine uses the data from CRPT_HMAC_FDBCKx as the data inputted to CRPT_HMAC_FDBCKx for the next block in DMA cascade mode. + * | | |The SHA/HMAC engine outputs feedback information for initial setting in the next block operation + * | | |Software can store that feedback value temporarily + * | | |After switching back, fill the stored feedback value to CRPT_HMAC_FDBCKx in the same operation, and then continue the operation with the original setting. + * @var CRPT_T::HMAC_FBADDR + * Offset: 0x4FC SHA/HMAC DMA Feedback Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FBADDR |SHA/HMAC DMA Feedback Address + * | | |In DMA cascade mode, software can update DMA feedbackaddress register for automatically reading and writing feedback vaules via DMA.The FBADDR keeps the feedback address of the feedback data for the next cascade operation + * | | |Based on the feedback address, the SHA/HMAC accelerator can read thefeedback dataof the last cascade opeation from SRAM memory space and write thefeedback dataof the current cascade opeation to SRAM memory space + * | | |The start of feedback address should be located at word boundary + * | | |In other words, bit 1 and 0 of FBADDR are ignored. + * | | |FBADDR can be read and written. + * | | |In DMA mode, software can update the next CRPT_HMAC_FBADDR before triggering START. + * @var CRPT_T::ECC_CTL + * Offset: 0x800 ECC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |ECC Accelerator Start + * | | |0 = No effect. + * | | |1 = Start ECC accelerator. BUSY flag will be set. + * | | |This bit is always 0 when it read back. + * | | |ECC accelerator will ignore this START signal when BUSY flag is 1. + * |[1] |STOP |ECC Accelerator Stop + * | | |0 = No effect. + * | | |1 = Abort ECC accelerator and make it into idle state. + * | | |This bit is always 0 when it read back. + * | | |Remember to clear ECC interrupt flag after stopping ECC accelerator. + * |[3] |PFA2C |Primg Field Adder with 2Cycles + * | | |0 = cost1 cycle . + * | | |1 = cost 2 cycles. + * |[4] |ECDSAS |Generate S in ECDSA Signature Generation + * | | |0 = No effect. + * | | |1 = Formula for generating S. + * | | |POINTX1 = ((POINTX2 * POINTY1 + POINTY2 ) / POINTX1) % CURVEN. + * |[5] |ECDSAR |Generate R in ECDSA Signature Generation + * | | |0 = No effect. + * | | |1 = Formula for generating R. + * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). + * |[7] |DMAEN |ECC Accelerator DMA Enable Bit + * | | |0 = ECC DMA engine Disabled. + * | | |1 = ECC DMA engine Enabled. + * | | |Only when START and DMAEN are 1, ECC DMA engine will be active + * |[8] |FSEL |Field Selection + * | | |0 = Binary Field (GF(2m )). + * | | |1 = Prime Field (GF(p)). + * |[10:9] |ECCOP |Point Operation for BF and PF + * | | |00 = Point multiplication :. + * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). + * | | |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]). + * | | |10 = Point addition :. + * | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +. + * | | |(POINTX2, POINTY2) + * | | |11 = Point doubling :. + * | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1). + * | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11 + * |[12:11] |MODOP |Modulus Operation for PF + * | | |00 = Division :. + * | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN. + * | | |01 = Multiplication :. + * | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN. + * | | |10 = Addition :. + * | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN. + * | | |11 = Subtraction :. + * | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN. + * | | |MODOP is active only when ECCOP = 01. + * |[13] |CSEL |Curve Selection + * | | |0 = NISTsuggested curve. + * | | |1 = Montgomery curve. + * |[14] |SCAP |Side-channel Attack Protection + * | | |0 = Full speed without side-channel protection. + * | | |1 = Less speed with side-channel protection. + * |[15] |SBM |Secure-boot Mode + * | | |0 = (POINTX1,POINTY1)from user data. + * | | |1 = (POINTX1,POINTY1)from secure boot key. + * |[16] |LDP1 |The Control Signal of RegisterPOINTX1and POINTY1for the xand Y Coordinate of the First Point + * | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user. + * | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user. + * |[17] |LDP2 |The Control Signal of Register POINTX2and POINTY2for the xand Y Coordinate of the Second Point + * | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user. + * | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user. + * |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve + * | | |0 = The register for CURVEA is not modified by DMA or user. + * | | |1 = The register for CURVEA is modified by DMA or user. + * |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve + * | | |0 = The register for CURVEB is not modified by DMA or user. + * | | |1 = The register for CURVEB is modified by DMA or user. + * |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve + * | | |0 = The register for CURVEN is not modified by DMA or user. + * | | |1 = The register for CURVEN is modified by DMA or user. + * |[21] |LDK |The Control Signal of Register for SCALARK + * | | |0 = The register for SCALARK is not modified by DMA or user. + * | | |1 = The register for SCALARK is modified by DMA or user. + * |[31:22] |CURVEM |The key length of elliptic curve. + * @var CRPT_T::ECC_STS + * Offset: 0x804 ECC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |ECC Accelerator Busy Flag + * | | |0 = The ECC accelerator is idle or finished. + * | | |1 = The ECC accelerator is under processing and protects all registers. + * | | |Remember to clear ECC interrupt flag after ECC accelerator finished + * |[1] |DMABUSY |ECC DMA Busy Flag + * | | |0 = ECC DMA is idle or finished. + * | | |1 = ECC DMA is busy. + * |[16] |BUSERR |ECC DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and ECC accelerator.. + * |[17] |KSERR |ECC Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop ECC engine. + * @var CRPT_T::ECC_X1 + * Offset: 0x808-0x84C ECC the X-coordinate Word of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX1 |ECC the X-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 + * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 + * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 + * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 + * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 + * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 + * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 + * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 + * @var CRPT_T::ECC_Y1 + * Offset: 0x850-0x894 ECC the Y-coordinate Word of the First Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point + * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 + * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 + * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 + * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 + * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 + * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 + * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 + * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 + * @var CRPT_T::ECC_X2 + * Offset: 0x898-0x8DC ECC the X-coordinate Word of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTX2 |ECC the X-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 + * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 + * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 + * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 + * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 + * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 + * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 + * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 + * @var CRPT_T::ECC_Y2 + * Offset: 0x8E0-0x924 ECC the Y-coordinate Word of the Second Point + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point + * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 + * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 + * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 + * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 + * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 + * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 + * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 + * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 + * @var CRPT_T::ECC_A + * Offset: 0x928-0x96C ECC the Parameter CURVEA Word of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 + * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 + * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 + * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 + * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 + * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 + * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 + * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 + * @var CRPT_T::ECC_B + * Offset: 0x970-0x9B4 ECC the Parameter CURVEB Word of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve + * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). + * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 + * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 + * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 + * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 + * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 + * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 + * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 + * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 + * @var CRPT_T::ECC_N + * Offset: 0x9B8-0x9FC ECC the Parameter CURVEN Word of Elliptic Curve + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve + * | | |In GF(p), CURVEN is the prime p. + * | | |In GF(2m), CURVEN is the irreducible polynomial. + * | | |For B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08 + * | | |For B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12 + * | | |For B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17 + * | | |For P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05 + * | | |For P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06 + * | | |For P-256, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07 + * | | |For P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11 + * | | |For P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16 + * @var CRPT_T::ECC_K + * Offset: 0xA00-0xA44 ECC the Scalar SCALARK Word of Point Multiplication + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication + * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. + * | | |For B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08 + * | | |For B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12 + * | | |For B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17 + * | | |For P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05 + * | | |For P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06 + * | | |For P-256, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07 + * | | |For P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11 + * | | |For P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16 + * @var CRPT_T::ECC_SADDR + * Offset: 0xA48 ECC DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR |ECC DMA Source Address + * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and ECC accelerator. + * | | |The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, + * | | |the ECC accelerator can read the DATA and PARAMETER from SRAM memory space and do ECC operation. + * | | |The start of source address should be located at word boundary. That is, bit 1 and 0 of SADDR are ignored. + * | | |SADDR can be read and written. In DMA mode, software must update the CRYPTO_ECC_SADDR before triggering START. + * @var CRPT_T::ECC_DADDR + * Offset: 0xA4C ECC DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |ECC DMA Destination Address + * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory and ECC accelerator + * | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored + * | | |Based on the destination address, the ECC accelerator can write the result data back to SRAM memory space after the ECC operation is finished + * | | |The start of destination address should be located at word boundary + * | | |That is, bit 1 and 0 of DADDR are ignored + * | | |DADDR can be read and written + * | | |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START + * @var CRPT_T::ECC_STARTREG + * Offset: 0xA50 ECC Starting Address of Updated Registers + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |STARTREG |ECC Starting Address of Updated Registers + * | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine + * | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG, for example, to update input data from register CRPT_ECC POINTX1 + * | | |Thus, the value of STARTREG is 0x808. + * @var CRPT_T::ECC_WORDCNT + * Offset: 0xA54 ECC DMA Word Count + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |WORDCNT |ECC DMA Word Count + * | | |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode + * | | |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144words + * | | |CRPT_ECC_WORDCNT can be read and written + * @var CRPT_T::RSA_CTL + * Offset: 0xB00 RSA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |RSA Accelerator Start + * | | |0 = No effect. + * | | |1 = Start RSAaccelerator. BUSY flag will be set. + * | | |This bit is always 0 when it read back. + * | | |RSAaccelerator will ignore this START signal when BUSY flag is 1. + * |[1] |STOP |RSA Accelerator Stop + * | | |0 = No effect. + * | | |1 = Abort RSA accelerator and make it into initialstate. + * | | |This bit is always 0 when it read back. + * | | |Remember to clear RSA interrupt flag after stopping RSA accelerator. + * |[2] |CRT |CRT Enable Control + * | | |0 = CRT Disabled. + * | | |1 = CRT Enabled. + * | | |CRT is only used in decryption with key length 2048, 3072,4096 bits. + * |[3] |CRTBYP |CRT BypassEnable Control + * | | |0 = CRT Bypass Disabled. + * | | |1 = CRT Bypass Enabled. + * | | |CRT bypass is only used in CRT decryption with the same key. + * | | |Note: If users want to decrypt repeatedly with the same key, they can execute CRT bypass mode after the first time CRT decryption(means the second time to the latest time), but they canu2019t set CRTBYP to 1 in non-CRT mode. + * |[5:4] |KEYLENG |The Key Length of RSA Operation + * | | |00 = 1024bits. + * | | |01 = 2048bits. + * | | |10 = 3072bits. + * | | |11 = 4096bits. + * |[8] |SCAP |Side Channel Attack Protection Enable Control + * | | |0 = Side Channel Attack Protection Disabled. + * | | |1 = Side Channel Attack Protection Enabled. + * @var CRPT_T::RSA_STS + * Offset: 0xB04 RSA Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |RSA Accelerator Busy Flag + * | | |0 = The RSA accelerator is idle or finished. + * | | |1 = The RSA accelerator is under processing and protects all registers. + * | | |Remember to clear RSA interrupt flag after RSA accelerator finished + * |[1] |DMABUSY |RSA DMA Busy Flag + * | | |0 = RSA DMA is idle or finished. + * | | |1 = RSA DMA is busy. + * |[16] |BUSERR |RSA DMA Access Bus Error Flag + * | | |0 = No error. + * | | |1 = Bus error will stop DMA operation and RSA accelerator. + * |[17] |CTLERR |RSA Control Register Error Flag + * | | |0 = No error. + * | | |1 = RSA control error. RSA will not start in the unsupported situation. + * | | |Note: If user use the control error condition, but donu2019t set START(CRPT_RSA_CTL[0]) to 1, CTLERR still be set to 1. + * |[18] |KSERR |RSA Engine Access Key Store Error Flag + * | | |0 = No error. + * | | |1 = Access error will stop RSA engine. + * @var CRPT_T::RSA_SADDR + * Offset: 0xB08-0xB18 RSA DMA Source Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SADDR0 |RSA DMA Source Address Register0 + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator. + * | | |This register is stored the address of RSA the Base of Exponentiation (M,N,E,p,q). + * @var CRPT_T::RSA_DADDR + * Offset: 0xB1C RSA DMA Destination Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DADDR |RSA DMA Destination Address Register + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator. + * | | |This register is stored the address of RSA DMA Destination Address Register (Ans). + * @var CRPT_T::RSA_MADDR + * Offset: 0xB20-0xB38 RSA DMA Middle Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MADDR |RSA DMA Middle Address Register + * | | |The RSA accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory space and RSA accelarator. + * | | |This register is stored the address of RSA CRT the Temporary Value (Cp -> Mp -> Sp, Cq -> Mq -> Sq, Dp, Dq, Rp, Rq, E'). + * @var CRPT_T::PRNG_KSCTL + * Offset: 0xF00 PRNG Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Write Key Number + * | | |The key number is sent to key store + * | | |Note: Only for destination Is OTP of Key Store. + * |[16] |TRUST |Write Key Trust Selection Bit + * | | |0 = Set written key as the non-secure key. + * | | |1 = Set written key as the secure key. + * |[18] |PRIV |Privilege Key Selection Bit + * | | |0 = Set key as the non-privilege key. + * | | |1 = Set key as the privilege key. + * |[19] |ECDH |ECDH Control Bit + * | | |0 =reserved. + * | | |1 = key is written to key store and used in ECDH. + * | | |Note:When ECDH was set to u20181u2019, 1 + * | | |PRNG seed must from TRNG and key is must written to the SRAM of key store (WSDST, CRPT_PRNG_KSCTL[23:22] must set to u201800u2019) + * | | |Otherwise, KCTLERRwill become u20181u2019(CRPT_PRNG_KSSTS[16]) + * | | |2 + * | | |Key must in the interval [1, n-1] (the parameter n is from ECC) + * | | |The value of n canu2019t be 0 or 1, otherwise, PRNG will always keep busy. + * |[20] |ECDSA |ECDSA Control Bit + * | | |0 =reserved. + * | | |1 = key is written to key store and used in ECDSA. + * | | |Note:When ECDSA was set to u20181u2019, 1 + * | | |PRNG seed must from TRNGand key is must written to the SRAM of key store (WSDST, CRPT_PRNG_KSCTL[23:22] must set to u201800u2019) + * | | |Otherwise, KCTLERRwill become u20181u2019(CRPT_PRNG_KSSTS[16]) + * | | |2.Key must in the interval [1, n-1] (the parameter n is from ECC) + * | | |The value of n canu2019t be 0 or 1, otherwise, PRNG will always keep busy. + * |[21] |WDST |Write Key Destination + * | | |0 = key is written to registers CRPT_PRNG_KEYx. + * | | |1 = key is written to key store. + * |[23:22] |WSDST |Write Key Store Destination + * | | |00 = key is written to the SRAM of key store. + * | | |10 = key is written to the OTP of key store. + * | | |Others = reserved. + * |[26:24] |OWNER |Write Key Owner Selection Bits + * | | |000 = Only for AES used. + * | | |001 = Only for HMAC engine used. + * | | |100 = Only for ECC engine used. + * | | |101 = Only for CPU engine use. + * | | |Others = reserved. + * @var CRPT_T::PRNG_KSSTS + * Offset: 0xF04 PRNG Key Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Key Number + * | | |The key number is generated by key store + * |[16] |KCTLERR |PRNG Key Control Register Error Flag + * | | |0 = No error. + * | | |1 = PRNG key control error + * | | |When PRNG execute ECDSA or ECDH, but PRNG seed not from TRNG or key is not written to the SRAM of key store (WSDST,CRPT_PRNG_KSCTL[23:22] is not equal to u201900u2019). + * @var CRPT_T::AES_KSCTL + * Offset: 0xF10 AES Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Read Key Number + * | | |The key number is sent to key store + * |[5] |RSRC |Read Key Destination + * | | |0 = key is read from registers CRPT_AESx_KEYx. + * | | |1 = key is read from key store. + * |[7:6] |RSSRC |Read Key Store Destination + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * @var CRPT_T::HMAC_KSCTL + * Offset: 0xF30 HMAC Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Read Key Number + * | | |The key number is sent to key store + * |[5] |RSRC |Read Key Destination + * | | |0 = key is read from HMAC registers. + * | | |1 = key is read from key store. + * |[7:6] |RSSRC |Read Key Store Destination + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * @var CRPT_T::ECC_KSCTL + * Offset: 0xF40 ECC Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUMK |Read Key Number K + * | | |The key number of CRPT_ECC_K is sent to key store when RSRCK =1. + * |[5] |RSRCK |Read Key Destinationfor Key Number K + * | | |0 = key is read from ECC registers. + * | | |1 = key is read from key store. + * |[7:6] |RSSRCK |Read Key Store Destinationfor Key Number K + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * |[14] |ECDH |ECDH Control Bit + * | | |0 =reserved. + * | | |1 = Set ECC opereration is in ECDH + * | | |When this bit and RSRCK are equal to 0x1, ECC will read ECDH private key to CRPT_ECC_K from key store. + * |[16] |TRUST |Write Key Trust Selection Bit + * | | |0 = Set ECDH written key as the non-secure key. + * | | |1 = Set ECDH written key as the secure key. + * |[18] |PRIV |Write Key Privilege Selection Bit + * | | |0 = Set ECDH written key as the non-privilege key. + * | | |1 = Set ECDHwritten key as the privilege key. + * |[20] |XY |ECDH Output Select Bit + * | | |0 =The ECDH written key is from X-coordinate Value. + * | | |1 = The ECDH written key is from Y-coordinate Value. + * |[21] |WDST |Write Key Destination + * | | |0 = The ECDH writtenkey is in registers CRPT_ECC_X1 and CRPT_ECC_Y. + * | | |1 = The ECDH writtenkey is written to key store. + * |[23:22] |WSDST |Write Key Store Destination + * | | |00 = The ECDH writtenkey is written to the SRAM of key store. + * | | |10 = The ECDH writtenkey is written to the OTP of key store. + * | | |Others = reserved. + * |[26:24] |OWNER |Write Key Owner Selection Bits + * | | |000 = The ECDH written key is only for AES used. + * | | |001 = The ECDH written key is only for HMAC engine used. + * | | |100 = The ECDH written key is only for ECC engine used. + * | | |101 = The ECDH written key is only for CPU engine use. + * | | |Others = reserved. + * @var CRPT_T::ECC_KSSTS + * Offset: 0xF44 ECC Key Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Key Number + * | | |The key number is generated by key store after ECDH. + * @var CRPT_T::ECC_KSXY + * Offset: 0xF48 ECC XY Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUMX |Read Key Number X + * | | |The key number of CRPT_ECC_X1 is sent to key store when RSRCXY =1. + * |[5] |RSRCXY |Read Key Source for Key Number xand Y + * | | |0 = key is read from ECC registers. + * | | |1 = key is read from key store. + * |[7:6] |RSSRCX |Read Key Store Source for Key Number X + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * |[12:8] |NUMY |Read Key Number Y + * | | |The key number of CRPT_ECC_Y1 is sent to key store when RSRCXY =1. + * |[15:14] |RSSRCY |Read Key Store Source for Key Number Y + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * @var CRPT_T::RSA_KSCTL + * Offset: 0xF50 RSA Key Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM |Read Key Number + * | | |The key number is sent to key store + * |[5] |RSRC |Read Key Destination + * | | |0 = key is read from RSA engine. + * | | |1 = key is read from key store. + * |[7:6] |RSSRC |Read Key Store Destination + * | | |00 = key is read from the SRAM of key store. + * | | |10 = key is read from the OTP of key store. + * | | |Others = reserved. + * |[12:8] |BKNUM |Read Exponent Blind Key Number + * | | |The key number is sent to key store, and its destination always be the SRAM of key store + * | | |CPU canu2019t read the exponent blind key. + * | | |Note:Use this key number, only when executing SCA protection but no-CRT mode. + * @var CRPT_T::RSA_KSSTS + * Offset: 0xF54-0xF58 RSA Key Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |NUM0 |Key Number0 + * | | |The key number is generated by key store, RSA can get complete p by key number in Key Store while operating. + * |[12:8] |NUM1 |Key Number1 + * | | |The key number is generated by key store, RSA can get complete q by key number in Key Store while operating. + * |[20:16] |NUM2 |Key Number2 + * | | |The key number is generated by key store, RSA can get or store Cp by key number in Key Store while operating. + * |[28:24] |NUM3 |Key Number3 + * | | |The key number is generated by key store, RSA can get or store Cq by key number in Key Store while operating. + * |[36:32] |NUM4 |Key Number4 + * | | |The key number is generated by key store, RSA can get or store Dp by key number in Key Store while operating. + * |[44:40] |NUM5 |Key Number5 + * | | |The key number is generated by key store, RSA can get or store Dq by key number in Key Store while operating. + * |[52:48] |NUM6 |Key Number6 + * | | |The key number is generated by key store, RSA can get or store Rp by key number in Key Store while operating. + * |[60:56] |NUM7 |Key Number7 + * | | |The key number is generated by key store, RSA can get or store Rq by key number in Key Store while operating. + */ + __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */ + __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */ + __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */ + __I uint32_t PRNG_KEY[8]; /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7 */ + __I uint32_t PRNG_STS; /*!< [0x0030] PRNG Status Register */ + __I uint32_t RESERVE0[7]; + __I uint32_t AES_FDBCK[4]; /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation */ + __I uint32_t RESERVE1[8]; + __IO uint32_t AES_GCM_IVCNT[2]; /*!< [0x0080] ~ [0x0084] AES GCM IV Byte Count Register 0 */ + __IO uint32_t AES_GCM_ACNT[2]; /*!< [0x0088] ~ [0x008c] AES GCM A Byte Count Register 0 */ + __IO uint32_t AES_GCM_PCNT[2]; /*!< [0x0090] ~ [0x0094] AES GCM P Byte Count Register 0 */ + __I uint32_t RESERVE2[2]; + __IO uint32_t AES_FBADDR; /*!< [0x00a0] AES DMA Feedback Address Register */ + __I uint32_t RESERVE3[23]; + __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */ + __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */ + __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */ + __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */ + __IO uint32_t AES_KEY[8]; /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0 */ + __IO uint32_t AES_IV[4]; /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0 */ + __IO uint32_t AES_SADDR; /*!< [0x0140] AES DMA Source Address Register */ + __IO uint32_t AES_DADDR; /*!< [0x0144] AES DMA Destination Address Register */ + __IO uint32_t AES_CNT; /*!< [0x0148] AES Byte Count Register */ + __I uint32_t RESERVE4[109]; + __IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */ + __I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */ + __I uint32_t HMAC_DGST[16]; /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15 */ + __IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */ + __IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */ + __IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */ + __IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-dMA Mode Data Input Port Register */ + __IO uint32_t HMAC_FDBCK[54]; /*!< [0x0358] ~ [0x042c] SHA/HMAC Output Feedback Data 0After SHA/HMAC Operation */ + __I uint32_t RESERVE5[51]; + __IO uint32_t HMAC_FBADDR; /*!< [0x04fc] SHA/HMAC DMA Feedback Address Register */ + __I uint32_t RESERVE6[192]; + __IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */ + __I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */ + __IO uint32_t ECC_X1[18]; /*!< [0x0808] ~ [0x084c] ECC the X-coordinate Word0 of the First Point */ + __IO uint32_t ECC_Y1[18]; /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point */ + __IO uint32_t ECC_X2[18]; /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point */ + __IO uint32_t ECC_Y2[18]; /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point */ + __IO uint32_t ECC_A[18]; /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve */ + __IO uint32_t ECC_B[18]; /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve */ + __IO uint32_t ECC_N[18]; /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve */ + __O uint32_t ECC_K[18]; /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */ + __IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */ + __IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */ + __IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */ + __IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */ + __I uint32_t RESERVE7[42]; + __IO uint32_t RSA_CTL; /*!< [0x0b00] RSA Control Register */ + __I uint32_t RSA_STS; /*!< [0x0b04] RSA Status Register */ + __IO uint32_t RSA_SADDR[5]; /*!< [0x0b08] ~ [0x0b18] RSA DMA Source Address Register0 */ + __IO uint32_t RSA_DADDR; /*!< [0x0b1c] RSA DMA Destination Address Register */ + __IO uint32_t RSA_MADDR[7]; /*!< [0x0b20] ~ [0x0b38] RSA DMA Middle Address Register0 */ + __I uint32_t RESERVE8[241]; + __O uint32_t PRNG_KSCTL; /*!< [0x0f00] PRNG Key Control Register */ + __I uint32_t PRNG_KSSTS; /*!< [0x0f04] PRNG Key Status Register */ + __I uint32_t RESERVE9[2]; + __O uint32_t AES_KSCTL; /*!< [0x0f10] AES Key Control Register */ + __I uint32_t RESERVE10[7]; + __O uint32_t HMAC_KSCTL; /*!< [0x0f30] HMAC Key Control Register */ + __I uint32_t RESERVE11[3]; + __O uint32_t ECC_KSCTL; /*!< [0x0f40] ECC Key Control Register */ + __I uint32_t ECC_KSSTS; /*!< [0x0f44] ECC Key Status Register */ + __O uint32_t ECC_KSXY; /*!< [0x0f48] ECC XY Number Register */ + __I uint32_t RESERVE12[1]; + __O uint32_t RSA_KSCTL; /*!< [0x0f50] RSA Key Control Register */ + __IO uint32_t RSA_KSSTS[2]; /*!< [0x0f54] ~ [0x0f58] RSA Key Status Register 0 */ + __I uint32_t RESERVE13[40]; + +} CRPT_T; + +/** + @addtogroup CRPT_CONST CRYPTO Bit Field Definition + Constant Definitions for CRYPTO Controller + @{ +*/ + +#define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */ +#define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */ + +#define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */ +#define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */ + +#define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */ +#define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */ + +#define CRPT_INTEN_PRNGEIEN_Pos (17) /*!< CRPT_T::INTEN: PRNGEIEN Position */ +#define CRPT_INTEN_PRNGEIEN_Msk (0x1ul << CRPT_INTEN_PRNGEIEN_Pos) /*!< CRPT_T::INTEN: PRNGEIEN Mask */ + +#define CRPT_INTEN_ECCIEN_Pos (22) /*!< CRPT_T::INTEN: ECCIEN Position */ +#define CRPT_INTEN_ECCIEN_Msk (0x1ul << CRPT_INTEN_ECCIEN_Pos) /*!< CRPT_T::INTEN: ECCIEN Mask */ + +#define CRPT_INTEN_ECCEIEN_Pos (23) /*!< CRPT_T::INTEN: ECCEIEN Position */ +#define CRPT_INTEN_ECCEIEN_Msk (0x1ul << CRPT_INTEN_ECCEIEN_Pos) /*!< CRPT_T::INTEN: ECCEIEN Mask */ + +#define CRPT_INTEN_HMACIEN_Pos (24) /*!< CRPT_T::INTEN: HMACIEN Position */ +#define CRPT_INTEN_HMACIEN_Msk (0x1ul << CRPT_INTEN_HMACIEN_Pos) /*!< CRPT_T::INTEN: HMACIEN Mask */ + +#define CRPT_INTEN_HMACEIEN_Pos (25) /*!< CRPT_T::INTEN: HMACEIEN Position */ +#define CRPT_INTEN_HMACEIEN_Msk (0x1ul << CRPT_INTEN_HMACEIEN_Pos) /*!< CRPT_T::INTEN: HMACEIEN Mask */ + +#define CRPT_INTEN_RSAIEN_Pos (30) /*!< CRPT_T::INTEN: RSAIEN Position */ +#define CRPT_INTEN_RSAIEN_Msk (0x1ul << CRPT_INTEN_RSAIEN_Pos) /*!< CRPT_T::INTEN: RSAIEN Mask */ + +#define CRPT_INTEN_RSAEIEN_Pos (31) /*!< CRPT_T::INTEN: RSAEIEN Position */ +#define CRPT_INTEN_RSAEIEN_Msk (0x1ul << CRPT_INTEN_RSAEIEN_Pos) /*!< CRPT_T::INTEN: RSAEIEN Mask */ + +#define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */ +#define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */ + +#define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */ +#define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */ + +#define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */ +#define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */ + +#define CRPT_INTSTS_PRNGEIF_Pos (17) /*!< CRPT_T::INTSTS: PRNGEIF Position */ +#define CRPT_INTSTS_PRNGEIF_Msk (0x1ul << CRPT_INTSTS_PRNGEIF_Pos) /*!< CRPT_T::INTSTS: PRNGEIF Mask */ + +#define CRPT_INTSTS_ECCIF_Pos (22) /*!< CRPT_T::INTSTS: ECCIF Position */ +#define CRPT_INTSTS_ECCIF_Msk (0x1ul << CRPT_INTSTS_ECCIF_Pos) /*!< CRPT_T::INTSTS: ECCIF Mask */ + +#define CRPT_INTSTS_ECCEIF_Pos (23) /*!< CRPT_T::INTSTS: ECCEIF Position */ +#define CRPT_INTSTS_ECCEIF_Msk (0x1ul << CRPT_INTSTS_ECCEIF_Pos) /*!< CRPT_T::INTSTS: ECCEIF Mask */ + +#define CRPT_INTSTS_HMACIF_Pos (24) /*!< CRPT_T::INTSTS: HMACIF Position */ +#define CRPT_INTSTS_HMACIF_Msk (0x1ul << CRPT_INTSTS_HMACIF_Pos) /*!< CRPT_T::INTSTS: HMACIF Mask */ + +#define CRPT_INTSTS_HMACEIF_Pos (25) /*!< CRPT_T::INTSTS: HMACEIF Position */ +#define CRPT_INTSTS_HMACEIF_Msk (0x1ul << CRPT_INTSTS_HMACEIF_Pos) /*!< CRPT_T::INTSTS: HMACEIF Mask */ + +#define CRPT_INTSTS_RSAIF_Pos (30) /*!< CRPT_T::INTSTS: RSAIF Position */ +#define CRPT_INTSTS_RSAIF_Msk (0x1ul << CRPT_INTSTS_RSAIF_Pos) /*!< CRPT_T::INTSTS: RSAIF Mask */ + +#define CRPT_INTSTS_RSAEIF_Pos (31) /*!< CRPT_T::INTSTS: RSAEIF Position */ +#define CRPT_INTSTS_RSAEIF_Msk (0x1ul << CRPT_INTSTS_RSAEIF_Pos) /*!< CRPT_T::INTSTS: RSAEIF Mask */ + +#define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */ +#define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */ + +#define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */ +#define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */ + +#define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */ +#define CRPT_PRNG_CTL_KEYSZ_Msk (0xful << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */ + +#define CRPT_PRNG_CTL_SEEDSEL_Pos (6) /*!< CRPT_T::PRNG_CTL: SEEDSEL Position */ +#define CRPT_PRNG_CTL_SEEDSEL_Msk (0x1ul << CRPT_PRNG_CTL_SEEDSEL_Pos) /*!< CRPT_T::PRNG_CTL: SEEDSEL Mask */ + +#define CRPT_PRNG_CTL_SEEDSRC_Pos (7) /*!< CRPT_T::PRNG_CTL: SEEDSRC Position */ +#define CRPT_PRNG_CTL_SEEDSRC_Msk (0x1ul << CRPT_PRNG_CTL_SEEDSRC_Pos) /*!< CRPT_T::PRNG_CTL: SEEDSRC Mask */ + +#define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */ +#define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */ + +#define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */ +#define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */ + +#define CRPT_PRNG_KEY0_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY0: KEY Position */ +#define CRPT_PRNG_KEY0_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY0_KEY_Pos) /*!< CRPT_T::PRNG_KEY0: KEY Mask */ + +#define CRPT_PRNG_KEY1_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY1: KEY Position */ +#define CRPT_PRNG_KEY1_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY1_KEY_Pos) /*!< CRPT_T::PRNG_KEY1: KEY Mask */ + +#define CRPT_PRNG_KEY2_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY2: KEY Position */ +#define CRPT_PRNG_KEY2_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY2_KEY_Pos) /*!< CRPT_T::PRNG_KEY2: KEY Mask */ + +#define CRPT_PRNG_KEY3_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY3: KEY Position */ +#define CRPT_PRNG_KEY3_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY3_KEY_Pos) /*!< CRPT_T::PRNG_KEY3: KEY Mask */ + +#define CRPT_PRNG_KEY4_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY4: KEY Position */ +#define CRPT_PRNG_KEY4_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY4_KEY_Pos) /*!< CRPT_T::PRNG_KEY4: KEY Mask */ + +#define CRPT_PRNG_KEY5_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY5: KEY Position */ +#define CRPT_PRNG_KEY5_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY5_KEY_Pos) /*!< CRPT_T::PRNG_KEY5: KEY Mask */ + +#define CRPT_PRNG_KEY6_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY6: KEY Position */ +#define CRPT_PRNG_KEY6_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY6_KEY_Pos) /*!< CRPT_T::PRNG_KEY6: KEY Mask */ + +#define CRPT_PRNG_KEY7_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY7: KEY Position */ +#define CRPT_PRNG_KEY7_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY7_KEY_Pos) /*!< CRPT_T::PRNG_KEY7: KEY Mask */ + +#define CRPT_PRNG_STS_BUSY_Pos (0) /*!< CRPT_T::PRNG_STS: BUSY Position */ +#define CRPT_PRNG_STS_BUSY_Msk (0x1ul << CRPT_PRNG_STS_BUSY_Pos) /*!< CRPT_T::PRNG_STS: BUSY Mask */ + +#define CRPT_PRNG_STS_KCTLERR_Pos (16) /*!< CRPT_T::PRNG_STS: KCTLERR Position */ +#define CRPT_PRNG_STS_KCTLERR_Msk (0x1ul << CRPT_PRNG_STS_KCTLERR_Pos) /*!< CRPT_T::PRNG_STS: KCTLERR Mask */ + +#define CRPT_PRNG_STS_KSERR_Pos (17) /*!< CRPT_T::PRNG_STS: KSERR Position */ +#define CRPT_PRNG_STS_KSERR_Msk (0x1ul << CRPT_PRNG_STS_KSERR_Pos) /*!< CRPT_T::PRNG_STS: KSERR Mask */ + +#define CRPT_AES_FDBCK0_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK0: FDBCK Position */ +#define CRPT_AES_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK0_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK0: FDBCK Mask */ + +#define CRPT_AES_FDBCK1_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK1: FDBCK Position */ +#define CRPT_AES_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK1_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK1: FDBCK Mask */ + +#define CRPT_AES_FDBCK2_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK2: FDBCK Position */ +#define CRPT_AES_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK2_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK2: FDBCK Mask */ + +#define CRPT_AES_FDBCK3_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK3: FDBCK Position */ +#define CRPT_AES_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK3_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK3: FDBCK Mask */ + +#define CRPT_AES_GCM_IVCNT0_CNT_Pos (0) /*!< CRPT_T::AES_GCM_IVCNT0: CNT Position */ +#define CRPT_AES_GCM_IVCNT0_CNT_Msk (0xfffffffful << CRPT_AES_GCM_IVCNT0_CNT_Pos) /*!< CRPT_T::AES_GCM_IVCNT0: CNT Mask */ + +#define CRPT_AES_GCM_IVCNT1_CNT_Pos (0) /*!< CRPT_T::AES_GCM_IVCNT1: CNT Position */ +#define CRPT_AES_GCM_IVCNT1_CNT_Msk (0x1ffffffful << CRPT_AES_GCM_IVCNT1_CNT_Pos) /*!< CRPT_T::AES_GCM_IVCNT1: CNT Mask */ + +#define CRPT_AES_GCM_ACNT0_CNT_Pos (0) /*!< CRPT_T::AES_GCM_ACNT0: CNT Position */ +#define CRPT_AES_GCM_ACNT0_CNT_Msk (0xfffffffful << CRPT_AES_GCM_ACNT0_CNT_Pos) /*!< CRPT_T::AES_GCM_ACNT0: CNT Mask */ + +#define CRPT_AES_GCM_ACNT1_CNT_Pos (0) /*!< CRPT_T::AES_GCM_ACNT1: CNT Position */ +#define CRPT_AES_GCM_ACNT1_CNT_Msk (0x1ffffffful << CRPT_AES_GCM_ACNT1_CNT_Pos) /*!< CRPT_T::AES_GCM_ACNT1: CNT Mask */ + +#define CRPT_AES_GCM_PCNT0_CNT_Pos (0) /*!< CRPT_T::AES_GCM_PCNT0: CNT Position */ +#define CRPT_AES_GCM_PCNT0_CNT_Msk (0xfffffffful << CRPT_AES_GCM_PCNT0_CNT_Pos) /*!< CRPT_T::AES_GCM_PCNT0: CNT Mask */ + +#define CRPT_AES_GCM_PCNT1_CNT_Pos (0) /*!< CRPT_T::AES_GCM_PCNT1: CNT Position */ +#define CRPT_AES_GCM_PCNT1_CNT_Msk (0x1ffffffful << CRPT_AES_GCM_PCNT1_CNT_Pos) /*!< CRPT_T::AES_GCM_PCNT1: CNT Mask */ + +#define CRPT_AES_FBADDR_FBADDR_Pos (0) /*!< CRPT_T::AES_FBADDR: FBADDR Position */ +#define CRPT_AES_FBADDR_FBADDR_Msk (0xfffffffful << CRPT_AES_FBADDR_FBADDR_Pos) /*!< CRPT_T::AES_FBADDR: FBADDR Mask */ + +#define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */ +#define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */ + +#define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */ +#define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */ + +#define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */ +#define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */ + +#define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */ +#define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */ + +#define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */ +#define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */ + +#define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */ +#define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */ + +#define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */ +#define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */ + +#define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRYPTO Position */ +#define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRYPTO Mask */ + +#define CRPT_AES_CTL_SM4EN_Pos (17) /*!< CRPT_T::AES_CTL: SM4EN Position */ +#define CRPT_AES_CTL_SM4EN_Msk (0x1ul << CRPT_AES_CTL_SM4EN_Pos) /*!< CRPT_T::AES_CTL: SM4EN Mask */ + +#define CRPT_AES_CTL_FBIN_Pos (20) /*!< CRPT_T::AES_CTL: FBIN Position */ +#define CRPT_AES_CTL_FBIN_Msk (0x1ul << CRPT_AES_CTL_FBIN_Pos) /*!< CRPT_T::AES_CTL: FBIN Mask */ + +#define CRPT_AES_CTL_FBOUT_Pos (21) /*!< CRPT_T::AES_CTL: FBOUT Position */ +#define CRPT_AES_CTL_FBOUT_Msk (0x1ul << CRPT_AES_CTL_FBOUT_Pos) /*!< CRPT_T::AES_CTL: FBOUT Mask */ + +#define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */ +#define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */ + +#define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */ +#define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */ + +#define CRPT_AES_CTL_KOUTSWAP_Pos (24) /*!< CRPT_T::AES_CTL: KOUTSWAP Position */ +#define CRPT_AES_CTL_KOUTSWAP_Msk (0x1ul << CRPT_AES_CTL_KOUTSWAP_Pos) /*!< CRPT_T::AES_CTL: KOUTSWAP Mask */ + +#define CRPT_AES_CTL_KINSWAP_Pos (25) /*!< CRPT_T::AES_CTL: KINSWAP Position */ +#define CRPT_AES_CTL_KINSWAP_Msk (0x1ul << CRPT_AES_CTL_KINSWAP_Pos) /*!< CRPT_T::AES_CTL: KINSWAP Mask */ + +#define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */ +#define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */ + +#define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */ +#define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */ + +#define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */ +#define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */ + +#define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */ +#define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */ + +#define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */ +#define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */ + +#define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */ +#define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */ + +#define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */ +#define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */ + +#define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position*/ +#define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */ + +#define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */ +#define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */ + +#define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */ +#define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */ + +#define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */ +#define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */ + +#define CRPT_AES_STS_KSERR_Pos (21) /*!< CRPT_T::AES_STS: KSERR Position */ +#define CRPT_AES_STS_KSERR_Msk (0x1ul << CRPT_AES_STS_KSERR_Pos) /*!< CRPT_T::AES_STS: KSERR Mask */ + +#define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */ +#define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */ + +#define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */ +#define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */ + +#define CRPT_AES_KEY0_KEY_Pos (0) /*!< CRPT_T::AES_KEY0: KEY Position */ +#define CRPT_AES_KEY0_KEY_Msk (0xfffffffful << CRPT_AES_KEY0_KEY_Pos) /*!< CRPT_T::AES_KEY0: KEY Mask */ + +#define CRPT_AES_KEY1_KEY_Pos (0) /*!< CRPT_T::AES_KEY1: KEY Position */ +#define CRPT_AES_KEY1_KEY_Msk (0xfffffffful << CRPT_AES_KEY1_KEY_Pos) /*!< CRPT_T::AES_KEY1: KEY Mask */ + +#define CRPT_AES_KEY2_KEY_Pos (0) /*!< CRPT_T::AES_KEY2: KEY Position */ +#define CRPT_AES_KEY2_KEY_Msk (0xfffffffful << CRPT_AES_KEY2_KEY_Pos) /*!< CRPT_T::AES_KEY2: KEY Mask */ + +#define CRPT_AES_KEY3_KEY_Pos (0) /*!< CRPT_T::AES_KEY3: KEY Position */ +#define CRPT_AES_KEY3_KEY_Msk (0xfffffffful << CRPT_AES_KEY3_KEY_Pos) /*!< CRPT_T::AES_KEY3: KEY Mask */ + +#define CRPT_AES_KEY4_KEY_Pos (0) /*!< CRPT_T::AES_KEY4: KEY Position */ +#define CRPT_AES_KEY4_KEY_Msk (0xfffffffful << CRPT_AES_KEY4_KEY_Pos) /*!< CRPT_T::AES_KEY4: KEY Mask */ + +#define CRPT_AES_KEY5_KEY_Pos (0) /*!< CRPT_T::AES_KEY5: KEY Position */ +#define CRPT_AES_KEY5_KEY_Msk (0xfffffffful << CRPT_AES_KEY5_KEY_Pos) /*!< CRPT_T::AES_KEY5: KEY Mask */ + +#define CRPT_AES_KEY6_KEY_Pos (0) /*!< CRPT_T::AES_KEY6: KEY Position */ +#define CRPT_AES_KEY6_KEY_Msk (0xfffffffful << CRPT_AES_KEY6_KEY_Pos) /*!< CRPT_T::AES_KEY6: KEY Mask */ + +#define CRPT_AES_KEY7_KEY_Pos (0) /*!< CRPT_T::AES_KEY7: KEY Position */ +#define CRPT_AES_KEY7_KEY_Msk (0xfffffffful << CRPT_AES_KEY7_KEY_Pos) /*!< CRPT_T::AES_KEY7: KEY Mask */ + +#define CRPT_AES_IV0_IV_Pos (0) /*!< CRPT_T::AES_IV0: IV Position */ +#define CRPT_AES_IV0_IV_Msk (0xfffffffful << CRPT_AES_IV0_IV_Pos) /*!< CRPT_T::AES_IV0: IV Mask */ + +#define CRPT_AES_IV1_IV_Pos (0) /*!< CRPT_T::AES_IV1: IV Position */ +#define CRPT_AES_IV1_IV_Msk (0xfffffffful << CRPT_AES_IV1_IV_Pos) /*!< CRPT_T::AES_IV1: IV Mask */ + +#define CRPT_AES_IV2_IV_Pos (0) /*!< CRPT_T::AES_IV2: IV Position */ +#define CRPT_AES_IV2_IV_Msk (0xfffffffful << CRPT_AES_IV2_IV_Pos) /*!< CRPT_T::AES_IV2: IV Mask */ + +#define CRPT_AES_IV3_IV_Pos (0) /*!< CRPT_T::AES_IV3: IV Position */ +#define CRPT_AES_IV3_IV_Msk (0xfffffffful << CRPT_AES_IV3_IV_Pos) /*!< CRPT_T::AES_IV3: IV Mask */ + +#define CRPT_AES_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES_SADDR: SADDR Position */ +#define CRPT_AES_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES_SADDR_SADDR_Pos) /*!< CRPT_T::AES_SADDR: SADDR Mask */ + +#define CRPT_AES_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES_DADDR: DADDR Position */ +#define CRPT_AES_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES_DADDR_DADDR_Pos) /*!< CRPT_T::AES_DADDR: DADDR Mask */ + +#define CRPT_AES_CNT_CNT_Pos (0) /*!< CRPT_T::AES_CNT: CNT Position */ +#define CRPT_AES_CNT_CNT_Msk (0xfffffffful << CRPT_AES_CNT_CNT_Pos) /*!< CRPT_T::AES_CNT: CNT Mask */ + +#define CRPT_HMAC_CTL_START_Pos (0) /*!< CRPT_T::HMAC_CTL: START Position */ +#define CRPT_HMAC_CTL_START_Msk (0x1ul << CRPT_HMAC_CTL_START_Pos) /*!< CRPT_T::HMAC_CTL: START Mask */ + +#define CRPT_HMAC_CTL_STOP_Pos (1) /*!< CRPT_T::HMAC_CTL: STOP Position */ +#define CRPT_HMAC_CTL_STOP_Msk (0x1ul << CRPT_HMAC_CTL_STOP_Pos) /*!< CRPT_T::HMAC_CTL: STOP Mask */ + +#define CRPT_HMAC_CTL_DMAFIRST_Pos (4) /*!< CRPT_T::HMAC_CTL: DMAFIRST Position */ +#define CRPT_HMAC_CTL_DMAFIRST_Msk (0x1ul << CRPT_HMAC_CTL_DMAFIRST_Pos) /*!< CRPT_T::HMAC_CTL: DMAFIRST Mask */ + +#define CRPT_HMAC_CTL_DMALAST_Pos (5) /*!< CRPT_T::HMAC_CTL: DMALAST Position */ +#define CRPT_HMAC_CTL_DMALAST_Msk (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos) /*!< CRPT_T::HMAC_CTL: DMALAST Mask */ + +#define CRPT_HMAC_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::HMAC_CTL: DMACSCAD Position */ +#define CRPT_HMAC_CTL_DMACSCAD_Msk (0x1ul << CRPT_HMAC_CTL_DMACSCAD_Pos) /*!< CRPT_T::HMAC_CTL: DMACSCAD Mask */ + +#define CRPT_HMAC_CTL_DMAEN_Pos (7) /*!< CRPT_T::HMAC_CTL: DMAEN Position */ +#define CRPT_HMAC_CTL_DMAEN_Msk (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos) /*!< CRPT_T::HMAC_CTL: DMAEN Mask */ + +#define CRPT_HMAC_CTL_OPMODE_Pos (8) /*!< CRPT_T::HMAC_CTL: OPMODE Position */ +#define CRPT_HMAC_CTL_OPMODE_Msk (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos) /*!< CRPT_T::HMAC_CTL: OPMODE Mask */ + +#define CRPT_HMAC_CTL_HMACEN_Pos (11) /*!< CRPT_T::HMAC_CTL: HMACEN Position */ +#define CRPT_HMAC_CTL_HMACEN_Msk (0x1ul << CRPT_HMAC_CTL_HMACEN_Pos) /*!< CRPT_T::HMAC_CTL: HMACEN Mask */ + +#define CRPT_HMAC_CTL_SM3EN_Pos (13) /*!< CRPT_T::HMAC_CTL: SM3EN Position */ +#define CRPT_HMAC_CTL_SM3EN_Msk (0x1ul << CRPT_HMAC_CTL_SM3EN_Pos) /*!< CRPT_T::HMAC_CTL: SM3EN Mask */ + +#define CRPT_HMAC_CTL_FBIN_Pos (20) /*!< CRPT_T::HMAC_CTL: FBIN Position */ +#define CRPT_HMAC_CTL_FBIN_Msk (0x1ul << CRPT_HMAC_CTL_FBIN_Pos) /*!< CRPT_T::HMAC_CTL: FBIN Mask */ + +#define CRPT_HMAC_CTL_FBOUT_Pos (21) /*!< CRPT_T::HMAC_CTL: FBOUT Position */ +#define CRPT_HMAC_CTL_FBOUT_Msk (0x1ul << CRPT_HMAC_CTL_FBOUT_Pos) /*!< CRPT_T::HMAC_CTL: FBOUT Mask */ + +#define CRPT_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::HMAC_CTL: OUTSWAP Position */ +#define CRPT_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos) /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask */ + +#define CRPT_HMAC_CTL_INSWAP_Pos (23) /*!< CRPT_T::HMAC_CTL: INSWAP Position */ +#define CRPT_HMAC_CTL_INSWAP_Msk (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos) /*!< CRPT_T::HMAC_CTL: INSWAP Mask */ + +#define CRPT_HMAC_STS_BUSY_Pos (0) /*!< CRPT_T::HMAC_STS: BUSY Position */ +#define CRPT_HMAC_STS_BUSY_Msk (0x1ul << CRPT_HMAC_STS_BUSY_Pos) /*!< CRPT_T::HMAC_STS: BUSY Mask */ + +#define CRPT_HMAC_STS_DMABUSY_Pos (1) /*!< CRPT_T::HMAC_STS: DMABUSY Position */ +#define CRPT_HMAC_STS_DMABUSY_Msk (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos) /*!< CRPT_T::HMAC_STS: DMABUSY Mask */ + +#define CRPT_HMAC_STS_DMAERR_Pos (8) /*!< CRPT_T::HMAC_STS: DMAERR Position */ +#define CRPT_HMAC_STS_DMAERR_Msk (0x1ul << CRPT_HMAC_STS_DMAERR_Pos) /*!< CRPT_T::HMAC_STS: DMAERR Mask */ + +#define CRPT_HMAC_STS_KSERR_Pos (9) /*!< CRPT_T::HMAC_STS: KSERR Position */ +#define CRPT_HMAC_STS_KSERR_Msk (0x1ul << CRPT_HMAC_STS_KSERR_Pos) /*!< CRPT_T::HMAC_STS: KSERR Mask */ + +#define CRPT_HMAC_STS_DATINREQ_Pos (16) /*!< CRPT_T::HMAC_STS: DATINREQ Position */ +#define CRPT_HMAC_STS_DATINREQ_Msk (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos) /*!< CRPT_T::HMAC_STS: DATINREQ Mask */ + +#define CRPT_HMAC_DGST0_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST0: DGST Position */ +#define CRPT_HMAC_DGST0_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST0_DGST_Pos) /*!< CRPT_T::HMAC_DGST0: DGST Mask */ + +#define CRPT_HMAC_DGST1_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST1: DGST Position */ +#define CRPT_HMAC_DGST1_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST1_DGST_Pos) /*!< CRPT_T::HMAC_DGST1: DGST Mask */ + +#define CRPT_HMAC_DGST2_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST2: DGST Position */ +#define CRPT_HMAC_DGST2_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST2_DGST_Pos) /*!< CRPT_T::HMAC_DGST2: DGST Mask */ + +#define CRPT_HMAC_DGST3_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST3: DGST Position */ +#define CRPT_HMAC_DGST3_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST3_DGST_Pos) /*!< CRPT_T::HMAC_DGST3: DGST Mask */ + +#define CRPT_HMAC_DGST4_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST4: DGST Position */ +#define CRPT_HMAC_DGST4_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST4_DGST_Pos) /*!< CRPT_T::HMAC_DGST4: DGST Mask */ + +#define CRPT_HMAC_DGST5_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST5: DGST Position */ +#define CRPT_HMAC_DGST5_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST5_DGST_Pos) /*!< CRPT_T::HMAC_DGST5: DGST Mask */ + +#define CRPT_HMAC_DGST6_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST6: DGST Position */ +#define CRPT_HMAC_DGST6_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST6_DGST_Pos) /*!< CRPT_T::HMAC_DGST6: DGST Mask */ + +#define CRPT_HMAC_DGST7_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST7: DGST Position */ +#define CRPT_HMAC_DGST7_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST7_DGST_Pos) /*!< CRPT_T::HMAC_DGST7: DGST Mask */ + +#define CRPT_HMAC_DGST8_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST8: DGST Position */ +#define CRPT_HMAC_DGST8_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST8_DGST_Pos) /*!< CRPT_T::HMAC_DGST8: DGST Mask */ + +#define CRPT_HMAC_DGST9_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST9: DGST Position */ +#define CRPT_HMAC_DGST9_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST9_DGST_Pos) /*!< CRPT_T::HMAC_DGST9: DGST Mask */ + +#define CRPT_HMAC_DGST10_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST10: DGST Position */ +#define CRPT_HMAC_DGST10_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST10_DGST_Pos) /*!< CRPT_T::HMAC_DGST10: DGST Mask */ + +#define CRPT_HMAC_DGST11_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST11: DGST Position */ +#define CRPT_HMAC_DGST11_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST11_DGST_Pos) /*!< CRPT_T::HMAC_DGST11: DGST Mask */ + +#define CRPT_HMAC_DGST12_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST12: DGST Position */ +#define CRPT_HMAC_DGST12_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST12_DGST_Pos) /*!< CRPT_T::HMAC_DGST12: DGST Mask */ + +#define CRPT_HMAC_DGST13_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST13: DGST Position */ +#define CRPT_HMAC_DGST13_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST13_DGST_Pos) /*!< CRPT_T::HMAC_DGST13: DGST Mask */ + +#define CRPT_HMAC_DGST14_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST14: DGST Position */ +#define CRPT_HMAC_DGST14_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST14_DGST_Pos) /*!< CRPT_T::HMAC_DGST14: DGST Mask */ + +#define CRPT_HMAC_DGST15_DGST_Pos (0) /*!< CRPT_T::HMAC_DGST15: DGST Position */ +#define CRPT_HMAC_DGST15_DGST_Msk (0xfffffffful << CRPT_HMAC_DGST15_DGST_Pos) /*!< CRPT_T::HMAC_DGST15: DGST Mask */ + +#define CRPT_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */ +#define CRPT_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask */ + +#define CRPT_HMAC_SADDR_SADDR_Pos (0) /*!< CRPT_T::HMAC_SADDR: SADDR Position */ +#define CRPT_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos) /*!< CRPT_T::HMAC_SADDR: SADDR Mask */ + +#define CRPT_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */ +#define CRPT_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos) /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask */ + +#define CRPT_HMAC_DATIN_DATIN_Pos (0) /*!< CRPT_T::HMAC_DATIN: DATIN Position */ +#define CRPT_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos) /*!< CRPT_T::HMAC_DATIN: DATIN Mask */ + +#define CRPT_HMAC_FDBCK0_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK0: FDBCK Position */ +#define CRPT_HMAC_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK0_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK0: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK1_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK1: FDBCK Position */ +#define CRPT_HMAC_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK1_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK1: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK2_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK2: FDBCK Position */ +#define CRPT_HMAC_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK2_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK2: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK3_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK3: FDBCK Position */ +#define CRPT_HMAC_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK3_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK3: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK4_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK4: FDBCK Position */ +#define CRPT_HMAC_FDBCK4_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK4_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK4: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK5_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK5: FDBCK Position */ +#define CRPT_HMAC_FDBCK5_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK5_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK5: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK6_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK6: FDBCK Position */ +#define CRPT_HMAC_FDBCK6_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK6_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK6: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK7_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK7: FDBCK Position */ +#define CRPT_HMAC_FDBCK7_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK7_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK7: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK8_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK8: FDBCK Position */ +#define CRPT_HMAC_FDBCK8_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK8_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK8: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK9_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK9: FDBCK Position */ +#define CRPT_HMAC_FDBCK9_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK9_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK9: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK10_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK10: FDBCK Position */ +#define CRPT_HMAC_FDBCK10_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK10_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK10: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK11_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK11: FDBCK Position */ +#define CRPT_HMAC_FDBCK11_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK11_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK11: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK12_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK12: FDBCK Position */ +#define CRPT_HMAC_FDBCK12_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK12_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK12: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK13_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK13: FDBCK Position */ +#define CRPT_HMAC_FDBCK13_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK13_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK13: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK14_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK14: FDBCK Position */ +#define CRPT_HMAC_FDBCK14_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK14_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK14: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK15_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK15: FDBCK Position */ +#define CRPT_HMAC_FDBCK15_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK15_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK15: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK16_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK16: FDBCK Position */ +#define CRPT_HMAC_FDBCK16_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK16_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK16: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK17_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK17: FDBCK Position */ +#define CRPT_HMAC_FDBCK17_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK17_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK17: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK18_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK18: FDBCK Position */ +#define CRPT_HMAC_FDBCK18_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK18_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK18: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK19_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK19: FDBCK Position */ +#define CRPT_HMAC_FDBCK19_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK19_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK19: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK20_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK20: FDBCK Position */ +#define CRPT_HMAC_FDBCK20_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK20_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK20: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK21_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK21: FDBCK Position */ +#define CRPT_HMAC_FDBCK21_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK21_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK21: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK22_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK22: FDBCK Position */ +#define CRPT_HMAC_FDBCK22_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK22_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK22: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK23_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK23: FDBCK Position */ +#define CRPT_HMAC_FDBCK23_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK23_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK23: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK24_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK24: FDBCK Position */ +#define CRPT_HMAC_FDBCK24_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK24_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK24: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK25_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK25: FDBCK Position */ +#define CRPT_HMAC_FDBCK25_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK25_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK25: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK26_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK26: FDBCK Position */ +#define CRPT_HMAC_FDBCK26_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK26_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK26: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK27_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK27: FDBCK Position */ +#define CRPT_HMAC_FDBCK27_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK27_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK27: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK28_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK28: FDBCK Position */ +#define CRPT_HMAC_FDBCK28_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK28_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK28: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK29_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK29: FDBCK Position */ +#define CRPT_HMAC_FDBCK29_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK29_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK29: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK30_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK30: FDBCK Position */ +#define CRPT_HMAC_FDBCK30_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK30_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK30: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK31_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK31: FDBCK Position */ +#define CRPT_HMAC_FDBCK31_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK31_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK31: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK32_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK32: FDBCK Position */ +#define CRPT_HMAC_FDBCK32_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK32_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK32: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK33_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK33: FDBCK Position */ +#define CRPT_HMAC_FDBCK33_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK33_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK33: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK34_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK34: FDBCK Position */ +#define CRPT_HMAC_FDBCK34_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK34_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK34: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK35_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK35: FDBCK Position */ +#define CRPT_HMAC_FDBCK35_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK35_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK35: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK36_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK36: FDBCK Position */ +#define CRPT_HMAC_FDBCK36_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK36_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK36: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK37_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK37: FDBCK Position */ +#define CRPT_HMAC_FDBCK37_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK37_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK37: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK38_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK38: FDBCK Position */ +#define CRPT_HMAC_FDBCK38_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK38_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK38: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK39_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK39: FDBCK Position */ +#define CRPT_HMAC_FDBCK39_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK39_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK39: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK40_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK40: FDBCK Position */ +#define CRPT_HMAC_FDBCK40_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK40_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK40: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK41_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK41: FDBCK Position */ +#define CRPT_HMAC_FDBCK41_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK41_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK41: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK42_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK42: FDBCK Position */ +#define CRPT_HMAC_FDBCK42_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK42_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK42: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK43_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK43: FDBCK Position */ +#define CRPT_HMAC_FDBCK43_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK43_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK43: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK44_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK44: FDBCK Position */ +#define CRPT_HMAC_FDBCK44_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK44_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK44: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK45_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK45: FDBCK Position */ +#define CRPT_HMAC_FDBCK45_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK45_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK45: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK46_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK46: FDBCK Position */ +#define CRPT_HMAC_FDBCK46_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK46_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK46: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK47_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK47: FDBCK Position */ +#define CRPT_HMAC_FDBCK47_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK47_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK47: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK48_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK48: FDBCK Position */ +#define CRPT_HMAC_FDBCK48_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK48_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK48: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK49_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK49: FDBCK Position */ +#define CRPT_HMAC_FDBCK49_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK49_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK49: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK50_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK50: FDBCK Position */ +#define CRPT_HMAC_FDBCK50_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK50_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK50: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK51_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK51: FDBCK Position */ +#define CRPT_HMAC_FDBCK51_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK51_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK51: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK52_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK52: FDBCK Position */ +#define CRPT_HMAC_FDBCK52_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK52_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK52: FDBCK Mask */ + +#define CRPT_HMAC_FDBCK53_FDBCK_Pos (0) /*!< CRPT_T::HMAC_FDBCK53: FDBCK Position */ +#define CRPT_HMAC_FDBCK53_FDBCK_Msk (0xfffffffful << CRPT_HMAC_FDBCK53_FDBCK_Pos) /*!< CRPT_T::HMAC_FDBCK53: FDBCK Mask */ + +#define CRPT_HMAC_FBADDR_FBADDR_Pos (0) /*!< CRPT_T::HMAC_FBADDR: FBADDR Position */ +#define CRPT_HMAC_FBADDR_FBADDR_Msk (0xfffffffful << CRPT_HMAC_FBADDR_FBADDR_Pos) /*!< CRPT_T::HMAC_FBADDR: FBADDR Mask */ + +#define CRPT_ECC_CTL_START_Pos (0) /*!< CRPT_T::ECC_CTL: START Position */ +#define CRPT_ECC_CTL_START_Msk (0x1ul << CRPT_ECC_CTL_START_Pos) /*!< CRPT_T::ECC_CTL: START Mask */ + +#define CRPT_ECC_CTL_STOP_Pos (1) /*!< CRPT_T::ECC_CTL: STOP Position */ +#define CRPT_ECC_CTL_STOP_Msk (0x1ul << CRPT_ECC_CTL_STOP_Pos) /*!< CRPT_T::ECC_CTL: STOP Mask */ + +#define CRPT_ECC_CTL_PFA2C_Pos (3) /*!< CRPT_T::ECC_CTL: PFA2C Position */ +#define CRPT_ECC_CTL_PFA2C_Msk (0x1ul << CRPT_ECC_CTL_PFA2C_Pos) /*!< CRPT_T::ECC_CTL: PFA2C Mask */ + +#define CRPT_ECC_CTL_ECDSAS_Pos (4) /*!< CRPT_T::ECC_CTL: ECDSAS Position */ +#define CRPT_ECC_CTL_ECDSAS_Msk (0x1ul << CRPT_ECC_CTL_ECDSAS_Pos) /*!< CRPT_T::ECC_CTL: ECDSAS Mask */ + +#define CRPT_ECC_CTL_ECDSAR_Pos (5) /*!< CRPT_T::ECC_CTL: ECDSAR Position */ +#define CRPT_ECC_CTL_ECDSAR_Msk (0x1ul << CRPT_ECC_CTL_ECDSAR_Pos) /*!< CRPT_T::ECC_CTL: ECDSAR Mask */ + +#define CRPT_ECC_CTL_DMAEN_Pos (7) /*!< CRPT_T::ECC_CTL: DMAEN Position */ +#define CRPT_ECC_CTL_DMAEN_Msk (0x1ul << CRPT_ECC_CTL_DMAEN_Pos) /*!< CRPT_T::ECC_CTL: DMAEN Mask */ + +#define CRPT_ECC_CTL_FSEL_Pos (8) /*!< CRPT_T::ECC_CTL: FSEL Position */ +#define CRPT_ECC_CTL_FSEL_Msk (0x1ul << CRPT_ECC_CTL_FSEL_Pos) /*!< CRPT_T::ECC_CTL: FSEL Mask */ + +#define CRPT_ECC_CTL_ECCOP_Pos (9) /*!< CRPT_T::ECC_CTL: ECCOP Position */ +#define CRPT_ECC_CTL_ECCOP_Msk (0x3ul << CRPT_ECC_CTL_ECCOP_Pos) /*!< CRPT_T::ECC_CTL: ECCOP Mask */ + +#define CRPT_ECC_CTL_MODOP_Pos (11) /*!< CRPT_T::ECC_CTL: MODOP Position */ +#define CRPT_ECC_CTL_MODOP_Msk (0x3ul << CRPT_ECC_CTL_MODOP_Pos) /*!< CRPT_T::ECC_CTL: MODOP Mask */ + +#define CRPT_ECC_CTL_CSEL_Pos (13) /*!< CRPT_T::ECC_CTL: CSEL Position */ +#define CRPT_ECC_CTL_CSEL_Msk (0x1ul << CRPT_ECC_CTL_CSEL_Pos) /*!< CRPT_T::ECC_CTL: CSEL Mask */ + +#define CRPT_ECC_CTL_SCAP_Pos (14) /*!< CRPT_T::ECC_CTL: SCAP Position */ +#define CRPT_ECC_CTL_SCAP_Msk (0x1ul << CRPT_ECC_CTL_SCAP_Pos) /*!< CRPT_T::ECC_CTL: SCAP Mask */ + +#define CRPT_ECC_CTL_SBM_Pos (15) /*!< CRPT_T::ECC_CTL: SBM Position */ +#define CRPT_ECC_CTL_SBM_Msk (0x1ul << CRPT_ECC_CTL_SBM_Pos) /*!< CRPT_T::ECC_CTL: SBM Mask */ + +#define CRPT_ECC_CTL_LDP1_Pos (16) /*!< CRPT_T::ECC_CTL: LDP1 Position */ +#define CRPT_ECC_CTL_LDP1_Msk (0x1ul << CRPT_ECC_CTL_LDP1_Pos) /*!< CRPT_T::ECC_CTL: LDP1 Mask */ + +#define CRPT_ECC_CTL_LDP2_Pos (17) /*!< CRPT_T::ECC_CTL: LDP2 Position */ +#define CRPT_ECC_CTL_LDP2_Msk (0x1ul << CRPT_ECC_CTL_LDP2_Pos) /*!< CRPT_T::ECC_CTL: LDP2 Mask */ + +#define CRPT_ECC_CTL_LDA_Pos (18) /*!< CRPT_T::ECC_CTL: LDA Position */ +#define CRPT_ECC_CTL_LDA_Msk (0x1ul << CRPT_ECC_CTL_LDA_Pos) /*!< CRPT_T::ECC_CTL: LDA Mask */ + +#define CRPT_ECC_CTL_LDB_Pos (19) /*!< CRPT_T::ECC_CTL: LDB Position */ +#define CRPT_ECC_CTL_LDB_Msk (0x1ul << CRPT_ECC_CTL_LDB_Pos) /*!< CRPT_T::ECC_CTL: LDB Mask */ + +#define CRPT_ECC_CTL_LDN_Pos (20) /*!< CRPT_T::ECC_CTL: LDN Position */ +#define CRPT_ECC_CTL_LDN_Msk (0x1ul << CRPT_ECC_CTL_LDN_Pos) /*!< CRPT_T::ECC_CTL: LDN Mask */ + +#define CRPT_ECC_CTL_LDK_Pos (21) /*!< CRPT_T::ECC_CTL: LDK Position */ +#define CRPT_ECC_CTL_LDK_Msk (0x1ul << CRPT_ECC_CTL_LDK_Pos) /*!< CRPT_T::ECC_CTL: LDK Mask */ + +#define CRPT_ECC_CTL_CURVEM_Pos (22) /*!< CRPT_T::ECC_CTL: CURVEM Position */ +#define CRPT_ECC_CTL_CURVEM_Msk (0x3fful << CRPT_ECC_CTL_CURVEM_Pos) /*!< CRPT_T::ECC_CTL: CURVEM Mask */ + +#define CRPT_ECC_STS_BUSY_Pos (0) /*!< CRPT_T::ECC_STS: BUSY Position */ +#define CRPT_ECC_STS_BUSY_Msk (0x1ul << CRPT_ECC_STS_BUSY_Pos) /*!< CRPT_T::ECC_STS: BUSY Mask */ + +#define CRPT_ECC_STS_DMABUSY_Pos (1) /*!< CRPT_T::ECC_STS: DMABUSY Position */ +#define CRPT_ECC_STS_DMABUSY_Msk (0x1ul << CRPT_ECC_STS_DMABUSY_Pos) /*!< CRPT_T::ECC_STS: DMABUSY Mask */ + +#define CRPT_ECC_STS_BUSERR_Pos (16) /*!< CRPT_T::ECC_STS: BUSERR Position */ +#define CRPT_ECC_STS_BUSERR_Msk (0x1ul << CRPT_ECC_STS_BUSERR_Pos) /*!< CRPT_T::ECC_STS: BUSERR Mask */ + +#define CRPT_ECC_STS_KSERR_Pos (17) /*!< CRPT_T::ECC_STS: KSERR Position */ +#define CRPT_ECC_STS_KSERR_Msk (0x1ul << CRPT_ECC_STS_KSERR_Pos) /*!< CRPT_T::ECC_STS: KSERR Mask */ + +#define CRPT_ECC_X1_Pos (0) /*!< CRPT_T::ECC_X1: POINTX Position */ +#define CRPT_ECC_X1_Msk (0xfffffffful << CRPT_ECC_X1_Pos) /*!< CRPT_T::ECC_X1: POINTX Mask */ + + +#define CRPT_ECC_X2_Pos (0) /*!< CRPT_T::ECC_X2: POINTX2 Position */ +#define CRPT_ECC_X2TX_Msk (0xfffffffful << CRPT_ECC_X2_Pos) /*!< CRPT_T::ECC_X2: POINTX2 Mask */ + + +#define CRPT_ECC_Y2_Pos (0) /*!< CRPT_T::ECC_Y2: POINTY2 Position */ +#define CRPT_ECC_Y2_Msk (0xfffffffful << CRPT_ECC_Y2_Pos) /*!< CRPT_T::ECC_Y2: POINTY2 Mask */ + +#define CRPT_ECC_A_Pos (0) /*!< CRPT_T::ECC_A: CURVEA Position */ +#define CRPT_ECC_A_Msk (0xfffffffful << CRPT_ECC_A_Pos) /*!< CRPT_T::ECC_A: CURVEA Mask */ + +#define CRPT_ECC_B_Pos (0) /*!< CRPT_T::ECC_B: CURVEB Position */ +#define CRPT_ECC_B_Msk (0xfffffffful << CRPT_ECC_B_Pos) /*!< CRPT_T::ECC_B: CURVEB Mask */ + +#define CRPT_ECC_N_Pos (0) /*!< CRPT_T::ECC_N: SCALARK Position */ +#define CRPT_ECC_N_Msk (0xfffffffful << CRPT_ECC_N_Pos) /*!< CRPT_T::ECC_N: SCALARK Mask */ + +#define CRPT_ECC_DADDR_DADDR_Pos (0) /*!< CRPT_T::ECC_DADDR: DADDR Position */ +#define CRPT_ECC_DADDR_DADDR_Msk (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos) /*!< CRPT_T::ECC_DADDR: DADDR Mask */ + +#define CRPT_ECC_STARTREG_STARTREG_Pos (0) /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/ +#define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask */ + +#define CRPT_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position*/ +#define CRPT_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask */ + +#define CRPT_RSA_CTL_START_Pos (0) /*!< CRPT_T::RSA_CTL: START Position */ +#define CRPT_RSA_CTL_START_Msk (0x1ul << CRPT_RSA_CTL_START_Pos) /*!< CRPT_T::RSA_CTL: START Mask */ + +#define CRPT_RSA_CTL_STOP_Pos (1) /*!< CRPT_T::RSA_CTL: STOP Position */ +#define CRPT_RSA_CTL_STOP_Msk (0x1ul << CRPT_RSA_CTL_STOP_Pos) /*!< CRPT_T::RSA_CTL: STOP Mask */ + +#define CRPT_RSA_CTL_CRT_Pos (2) /*!< CRPT_T::RSA_CTL: CRT Position */ +#define CRPT_RSA_CTL_CRT_Msk (0x1ul << CRPT_RSA_CTL_CRT_Pos) /*!< CRPT_T::RSA_CTL: CRT Mask */ + +#define CRPT_RSA_CTL_CRTBYP_Pos (3) /*!< CRPT_T::RSA_CTL: CRTBYP Position */ +#define CRPT_RSA_CTL_CRTBYP_Msk (0x1ul << CRPT_RSA_CTL_CRTBYP_Pos) /*!< CRPT_T::RSA_CTL: CRTBYP Mask */ + +#define CRPT_RSA_CTL_KEYLENG_Pos (4) /*!< CRPT_T::RSA_CTL: KEYLENG Position */ +#define CRPT_RSA_CTL_KEYLENG_Msk (0x3ul << CRPT_RSA_CTL_KEYLENG_Pos) /*!< CRPT_T::RSA_CTL: KEYLENG Mask */ + +#define CRPT_RSA_CTL_SCAP_Pos (8) /*!< CRPT_T::RSA_CTL: SCAP Position */ +#define CRPT_RSA_CTL_SCAP_Msk (0x1ul << CRPT_RSA_CTL_SCAP_Pos) /*!< CRPT_T::RSA_CTL: SCAP Mask */ + +#define CRPT_RSA_STS_BUSY_Pos (0) /*!< CRPT_T::RSA_STS: BUSY Position */ +#define CRPT_RSA_STS_BUSY_Msk (0x1ul << CRPT_RSA_STS_BUSY_Pos) /*!< CRPT_T::RSA_STS: BUSY Mask */ + +#define CRPT_RSA_STS_DMABUSY_Pos (1) /*!< CRPT_T::RSA_STS: DMABUSY Position */ +#define CRPT_RSA_STS_DMABUSY_Msk (0x1ul << CRPT_RSA_STS_DMABUSY_Pos) /*!< CRPT_T::RSA_STS: DMABUSY Mask */ + +#define CRPT_RSA_STS_BUSERR_Pos (16) /*!< CRPT_T::RSA_STS: BUSERR Position */ +#define CRPT_RSA_STS_BUSERR_Msk (0x1ul << CRPT_RSA_STS_BUSERR_Pos) /*!< CRPT_T::RSA_STS: BUSERR Mask */ + +#define CRPT_RSA_STS_CTLERR_Pos (17) /*!< CRPT_T::RSA_STS: CTLERR Position */ +#define CRPT_RSA_STS_CTLERR_Msk (0x1ul << CRPT_RSA_STS_CTLERR_Pos) /*!< CRPT_T::RSA_STS: CTLERR Mask */ + +#define CRPT_RSA_STS_KSERR_Pos (18) /*!< CRPT_T::RSA_STS: KSERR Position */ +#define CRPT_RSA_STS_KSERR_Msk (0x1ul << CRPT_RSA_STS_KSERR_Pos) /*!< CRPT_T::RSA_STS: KSERR Mask */ + +#define CRPT_RSA_SADDR_Pos (0) /*!< CRPT_T::RSA_SADDR: SADDR Position */ +#define CRPT_RSA_SADDR_Msk (0xfffffffful << CRPT_RSA_SADDR_Pos) /*!< CRPT_T::RSA_SADDR: SADDR Mask */ + +#define CRPT_RSA_DADDR_Pos (0) /*!< CRPT_T::RSA_DADDR: DADDR Position */ +#define CRPT_RSA_DADDR_Msk (0xfffffffful << CRPT_RSA_DADDR_Pos) /*!< CRPT_T::RSA_DADDR: DADDR Mask */ + +#define CRPT_RSA_MADDR_Pos (0) /*!< CRPT_T::RSA_MADDR: MADDR Position */ +#define CRPT_RSA_MADDR_Msk (0xfffffffful << CRPT_RSA_MADDR_Pos) /*!< CRPT_T::RSA_MADDR: MADDR Mask */ + +#define CRPT_PRNG_KSCTL_NUM_Pos (0) /*!< CRPT_T::PRNG_KSCTL: NUM Position */ +#define CRPT_PRNG_KSCTL_NUM_Msk (0x1ful << CRPT_PRNG_KSCTL_NUM_Pos) /*!< CRPT_T::PRNG_KSCTL: NUM Mask */ + +#define CRPT_PRNG_KSCTL_TRUST_Pos (16) /*!< CRPT_T::PRNG_KSCTL: TRUST Position */ +#define CRPT_PRNG_KSCTL_TRUST_Msk (0x1ul << CRPT_PRNG_KSCTL_TRUST_Pos) /*!< CRPT_T::PRNG_KSCTL: TRUST Mask */ + +#define CRPT_PRNG_KSCTL_PRIV_Pos (18) /*!< CRPT_T::PRNG_KSCTL: PRIV Position */ +#define CRPT_PRNG_KSCTL_PRIV_Msk (0x1ul << CRPT_PRNG_KSCTL_PRIV_Pos) /*!< CRPT_T::PRNG_KSCTL: PRIV Mask */ + +#define CRPT_PRNG_KSCTL_ECDH_Pos (19) /*!< CRPT_T::PRNG_KSCTL: ECDH Position */ +#define CRPT_PRNG_KSCTL_ECDH_Msk (0x1ul << CRPT_PRNG_KSCTL_ECDH_Pos) /*!< CRPT_T::PRNG_KSCTL: ECDH Mask */ + +#define CRPT_PRNG_KSCTL_ECDSA_Pos (20) /*!< CRPT_T::PRNG_KSCTL: ECDSA Position */ +#define CRPT_PRNG_KSCTL_ECDSA_Msk (0x1ul << CRPT_PRNG_KSCTL_ECDSA_Pos) /*!< CRPT_T::PRNG_KSCTL: ECDSA Mask */ + +#define CRPT_PRNG_KSCTL_WDST_Pos (21) /*!< CRPT_T::PRNG_KSCTL: WDST Position */ +#define CRPT_PRNG_KSCTL_WDST_Msk (0x1ul << CRPT_PRNG_KSCTL_WDST_Pos) /*!< CRPT_T::PRNG_KSCTL: WDST Mask */ + +#define CRPT_PRNG_KSCTL_WSDST_Pos (22) /*!< CRPT_T::PRNG_KSCTL: WSDST Position */ +#define CRPT_PRNG_KSCTL_WSDST_Msk (0x3ul << CRPT_PRNG_KSCTL_WSDST_Pos) /*!< CRPT_T::PRNG_KSCTL: WSDST Mask */ + +#define CRPT_PRNG_KSCTL_OWNER_Pos (24) /*!< CRPT_T::PRNG_KSCTL: OWNER Position */ +#define CRPT_PRNG_KSCTL_OWNER_Msk (0x7ul << CRPT_PRNG_KSCTL_OWNER_Pos) /*!< CRPT_T::PRNG_KSCTL: OWNER Mask */ + +#define CRPT_PRNG_KSSTS_NUM_Pos (0) /*!< CRPT_T::PRNG_KSSTS: NUM Position */ +#define CRPT_PRNG_KSSTS_NUM_Msk (0x1ful << CRPT_PRNG_KSSTS_NUM_Pos) /*!< CRPT_T::PRNG_KSSTS: NUM Mask */ + +#define CRPT_PRNG_KSSTS_KCTLERR_Pos (16) /*!< CRPT_T::PRNG_KSSTS: KCTLERR Position */ +#define CRPT_PRNG_KSSTS_KCTLERR_Msk (0x1ul << CRPT_PRNG_KSSTS_KCTLERR_Pos) /*!< CRPT_T::PRNG_KSSTS: KCTLERR Mask */ + +#define CRPT_AES_KSCTL_NUM_Pos (0) /*!< CRPT_T::AES_KSCTL: NUM Position */ +#define CRPT_AES_KSCTL_NUM_Msk (0x1ful << CRPT_AES_KSCTL_NUM_Pos) /*!< CRPT_T::AES_KSCTL: NUM Mask */ + +#define CRPT_AES_KSCTL_RSRC_Pos (5) /*!< CRPT_T::AES_KSCTL: RSRC Position */ +#define CRPT_AES_KSCTL_RSRC_Msk (0x1ul << CRPT_AES_KSCTL_RSRC_Pos) /*!< CRPT_T::AES_KSCTL: RSRC Mask */ + +#define CRPT_AES_KSCTL_RSSRC_Pos (6) /*!< CRPT_T::AES_KSCTL: RSSRC Position */ +#define CRPT_AES_KSCTL_RSSRC_Msk (0x3ul << CRPT_AES_KSCTL_RSSRC_Pos) /*!< CRPT_T::AES_KSCTL: RSSRC Mask */ + +#define CRPT_HMAC_KSCTL_NUM_Pos (0) /*!< CRPT_T::HMAC_KSCTL: NUM Position */ +#define CRPT_HMAC_KSCTL_NUM_Msk (0x1ful << CRPT_HMAC_KSCTL_NUM_Pos) /*!< CRPT_T::HMAC_KSCTL: NUM Mask */ + +#define CRPT_HMAC_KSCTL_RSRC_Pos (5) /*!< CRPT_T::HMAC_KSCTL: RSRC Position */ +#define CRPT_HMAC_KSCTL_RSRC_Msk (0x1ul << CRPT_HMAC_KSCTL_RSRC_Pos) /*!< CRPT_T::HMAC_KSCTL: RSRC Mask */ + +#define CRPT_HMAC_KSCTL_RSSRC_Pos (6) /*!< CRPT_T::HMAC_KSCTL: RSSRC Position */ +#define CRPT_HMAC_KSCTL_RSSRC_Msk (0x3ul << CRPT_HMAC_KSCTL_RSSRC_Pos) /*!< CRPT_T::HMAC_KSCTL: RSSRC Mask */ + +#define CRPT_ECC_KSCTL_NUMK_Pos (0) /*!< CRPT_T::ECC_KSCTL: NUMK Position */ +#define CRPT_ECC_KSCTL_NUMK_Msk (0x1ful << CRPT_ECC_KSCTL_NUMK_Pos) /*!< CRPT_T::ECC_KSCTL: NUMK Mask */ + +#define CRPT_ECC_KSCTL_RSRCK_Pos (5) /*!< CRPT_T::ECC_KSCTL: RSRCK Position */ +#define CRPT_ECC_KSCTL_RSRCK_Msk (0x1ul << CRPT_ECC_KSCTL_RSRCK_Pos) /*!< CRPT_T::ECC_KSCTL: RSRCK Mask */ + +#define CRPT_ECC_KSCTL_RSSRCK_Pos (6) /*!< CRPT_T::ECC_KSCTL: RSSRCK Position */ +#define CRPT_ECC_KSCTL_RSSRCK_Msk (0x3ul << CRPT_ECC_KSCTL_RSSRCK_Pos) /*!< CRPT_T::ECC_KSCTL: RSSRCK Mask */ + +#define CRPT_ECC_KSCTL_ECDH_Pos (14) /*!< CRPT_T::ECC_KSCTL: ECDH Position */ +#define CRPT_ECC_KSCTL_ECDH_Msk (0x1ul << CRPT_ECC_KSCTL_ECDH_Pos) /*!< CRPT_T::ECC_KSCTL: ECDH Mask */ + +#define CRPT_ECC_KSCTL_TRUST_Pos (16) /*!< CRPT_T::ECC_KSCTL: TRUST Position */ +#define CRPT_ECC_KSCTL_TRUST_Msk (0x1ul << CRPT_ECC_KSCTL_TRUST_Pos) /*!< CRPT_T::ECC_KSCTL: TRUST Mask */ + +#define CRPT_ECC_KSCTL_PRIV_Pos (18) /*!< CRPT_T::ECC_KSCTL: PRIV Position */ +#define CRPT_ECC_KSCTL_PRIV_Msk (0x1ul << CRPT_ECC_KSCTL_PRIV_Pos) /*!< CRPT_T::ECC_KSCTL: PRIV Mask */ + +#define CRPT_ECC_KSCTL_XY_Pos (20) /*!< CRPT_T::ECC_KSCTL: XY Position */ +#define CRPT_ECC_KSCTL_XY_Msk (0x1ul << CRPT_ECC_KSCTL_XY_Pos) /*!< CRPT_T::ECC_KSCTL: XY Mask */ + +#define CRPT_ECC_KSCTL_WDST_Pos (21) /*!< CRPT_T::ECC_KSCTL: WDST Position */ +#define CRPT_ECC_KSCTL_WDST_Msk (0x1ul << CRPT_ECC_KSCTL_WDST_Pos) /*!< CRPT_T::ECC_KSCTL: WDST Mask */ + +#define CRPT_ECC_KSCTL_WSDST_Pos (22) /*!< CRPT_T::ECC_KSCTL: WSDST Position */ +#define CRPT_ECC_KSCTL_WSDST_Msk (0x3ul << CRPT_ECC_KSCTL_WSDST_Pos) /*!< CRPT_T::ECC_KSCTL: WSDST Mask */ + +#define CRPT_ECC_KSCTL_OWNER_Pos (24) /*!< CRPT_T::ECC_KSCTL: OWNER Position */ +#define CRPT_ECC_KSCTL_OWNER_Msk (0x7ul << CRPT_ECC_KSCTL_OWNER_Pos) /*!< CRPT_T::ECC_KSCTL: OWNER Mask */ + +#define CRPT_ECC_KSSTS_NUM_Pos (0) /*!< CRPT_T::ECC_KSSTS: NUM Position */ +#define CRPT_ECC_KSSTS_NUM_Msk (0x1ful << CRPT_ECC_KSSTS_NUM_Pos) /*!< CRPT_T::ECC_KSSTS: NUM Mask */ + +#define CRPT_ECC_KSXY_NUMX_Pos (0) /*!< CRPT_T::ECC_KSXY: NUMX Position */ +#define CRPT_ECC_KSXY_NUMX_Msk (0x1ful << CRPT_ECC_KSXY_NUMX_Pos) /*!< CRPT_T::ECC_KSXY: NUMX Mask */ + +#define CRPT_ECC_KSXY_RSRCXY_Pos (5) /*!< CRPT_T::ECC_KSXY: RSRCXY Position */ +#define CRPT_ECC_KSXY_RSRCXY_Msk (0x1ul << CRPT_ECC_KSXY_RSRCXY_Pos) /*!< CRPT_T::ECC_KSXY: RSRCXY Mask */ + +#define CRPT_ECC_KSXY_RSSRCX_Pos (6) /*!< CRPT_T::ECC_KSXY: RSSRCX Position */ +#define CRPT_ECC_KSXY_RSSRCX_Msk (0x3ul << CRPT_ECC_KSXY_RSSRCX_Pos) /*!< CRPT_T::ECC_KSXY: RSSRCX Mask */ + +#define CRPT_ECC_KSXY_NUMY_Pos (8) /*!< CRPT_T::ECC_KSXY: NUMY Position */ +#define CRPT_ECC_KSXY_NUMY_Msk (0x1ful << CRPT_ECC_KSXY_NUMY_Pos) /*!< CRPT_T::ECC_KSXY: NUMY Mask */ + +#define CRPT_ECC_KSXY_RSSRCY_Pos (14) /*!< CRPT_T::ECC_KSXY: RSSRCY Position */ +#define CRPT_ECC_KSXY_RSSRCY_Msk (0x3ul << CRPT_ECC_KSXY_RSSRCY_Pos) /*!< CRPT_T::ECC_KSXY: RSSRCY Mask */ + +#define CRPT_RSA_KSCTL_NUM_Pos (0) /*!< CRPT_T::RSA_KSCTL: NUM Position */ +#define CRPT_RSA_KSCTL_NUM_Msk (0x1ful << CRPT_RSA_KSCTL_NUM_Pos) /*!< CRPT_T::RSA_KSCTL: NUM Mask */ + +#define CRPT_RSA_KSCTL_RSRC_Pos (5) /*!< CRPT_T::RSA_KSCTL: RSRC Position */ +#define CRPT_RSA_KSCTL_RSRC_Msk (0x1ul << CRPT_RSA_KSCTL_RSRC_Pos) /*!< CRPT_T::RSA_KSCTL: RSRC Mask */ + +#define CRPT_RSA_KSCTL_RSSRC_Pos (6) /*!< CRPT_T::RSA_KSCTL: RSSRC Position */ +#define CRPT_RSA_KSCTL_RSSRC_Msk (0x3ul << CRPT_RSA_KSCTL_RSSRC_Pos) /*!< CRPT_T::RSA_KSCTL: RSSRC Mask */ + +#define CRPT_RSA_KSCTL_BKNUM_Pos (8) /*!< CRPT_T::RSA_KSCTL: BKNUM Position */ +#define CRPT_RSA_KSCTL_BKNUM_Msk (0x1ful << CRPT_RSA_KSCTL_BKNUM_Pos) /*!< CRPT_T::RSA_KSCTL: BKNUM Mask */ + +#define CRPT_RSA_KSSTS0_NUM0_Pos (0) /*!< CRPT_T::RSA_KSSTS0: NUM0 Position */ +#define CRPT_RSA_KSSTS0_NUM0_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM0_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM0 Mask */ + +#define CRPT_RSA_KSSTS0_NUM1_Pos (8) /*!< CRPT_T::RSA_KSSTS0: NUM1 Position */ +#define CRPT_RSA_KSSTS0_NUM1_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM1_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM1 Mask */ + +#define CRPT_RSA_KSSTS0_NUM2_Pos (16) /*!< CRPT_T::RSA_KSSTS0: NUM2 Position */ +#define CRPT_RSA_KSSTS0_NUM2_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM2_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM2 Mask */ + +#define CRPT_RSA_KSSTS0_NUM3_Pos (24) /*!< CRPT_T::RSA_KSSTS0: NUM3 Position */ +#define CRPT_RSA_KSSTS0_NUM3_Msk (0x1ful << CRPT_RSA_KSSTS0_NUM3_Pos) /*!< CRPT_T::RSA_KSSTS0: NUM3 Mask */ + +#define CRPT_RSA_KSSTS1_NUM4_Pos (0) /*!< CRPT_T::RSA_KSSTS1: NUM4 Position */ +#define CRPT_RSA_KSSTS1_NUM4_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM4_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM4 Mask */ + +#define CRPT_RSA_KSSTS1_NUM5_Pos (8) /*!< CRPT_T::RSA_KSSTS1: NUM5 Position */ +#define CRPT_RSA_KSSTS1_NUM5_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM5_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM5 Mask */ + +#define CRPT_RSA_KSSTS1_NUM6_Pos (16) /*!< CRPT_T::RSA_KSSTS1: NUM6 Position */ +#define CRPT_RSA_KSSTS1_NUM6_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM6_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM6 Mask */ + +#define CRPT_RSA_KSSTS1_NUM7_Pos (24) /*!< CRPT_T::RSA_KSSTS1: NUM7 Position */ +#define CRPT_RSA_KSSTS1_NUM7_Msk (0x1ful << CRPT_RSA_KSSTS1_NUM7_Pos) /*!< CRPT_T::RSA_KSSTS1: NUM7 Mask */ + +#define CRPT_VERSION_MINOR_Pos (0) /*!< CRPT_T::VERSION: MINOR Position */ +#define CRPT_VERSION_MINOR_Msk (0xfffful << CRPT_VERSION_MINOR_Pos) /*!< CRPT_T::VERSION: MINOR Mask */ + +#define CRPT_VERSION_SUB_Pos (16) /*!< CRPT_T::VERSION: SUB Position */ +#define CRPT_VERSION_SUB_Msk (0xfful << CRPT_VERSION_SUB_Pos) /*!< CRPT_T::VERSION: SUB Mask */ + +#define CRPT_VERSION_MAJOR_Pos (24) /*!< CRPT_T::VERSION: MAJOR Position */ +#define CRPT_VERSION_MAJOR_Msk (0xfful << CRPT_VERSION_MAJOR_Pos) /*!< CRPT_T::VERSION: MAJOR Mask */ + +/**@}*/ /* CRPT_CONST */ +/**@}*/ /* end of CRYPTO register group */ + + +/**@}*/ /* end of REGISTER group */ + +#endif /* __CRPT_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/dac_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/dac_reg.h new file mode 100644 index 0000000000..1a3c2f280e --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/dac_reg.h @@ -0,0 +1,208 @@ +/**************************************************************************//** + * @file dac_reg.h + * @version V1.00 + * @brief DAC register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __DAC_REG_H__ +#define __DAC_REG_H__ + + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Digital to Analog Converter -------------------------*/ +/** + @addtogroup DAC Digital to Analog Converter(DAC) + Memory Mapped Structure for DAC Controller + @{ +*/ + + +typedef struct +{ + + + + /** + * @var DAC_T::CTL + * Offset: 0x00 DAC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DACEN |DAC Enable Bit + * | | |0 = DAC is Disabled. + * | | |1 = DAC is Enabled. + * |[1] |DACIEN |DAC Interrupt Enable Bit + * | | |0 = Interrupt is Disabled. + * | | |1 = Interrupt is Enabled. + * |[2] |DMAEN |DMA Mode Enable Bit + * | | |0 = DMA mode Disabled. + * | | |1 = DMA mode Enabled. + * |[3] |DMAURIEN |DMA Under-run Interrupt Enable Bit + * | | |0 = DMA under-run interrupt Disabled. + * | | |1 = DMA under-run interrupt Enabled. + * |[4] |TRGEN |Trigger Mode Enable Bit + * | | |0 = DAC event trigger mode Disabled. + * | | |1 = DAC event trigger mode Enabled. + * |[7:5] |TRGSEL |Trigger Source Selection + * | | |000 = Software trigger. + * | | |001 = External pin DAC0_ST trigger. + * | | |010 = Timer 0 trigger. + * | | |011 = Timer 1 trigger. + * | | |100 = Timer 2 trigger. + * | | |101 = Timer 3 trigger. + * | | |110 = EPWM0 trigger. + * | | |111 = EPWM1 trigger. + * |[8] |BYPASS |Bypass Buffer Mode + * | | |0 = Output voltage buffer Enabled. + * | | |1 = Output voltage buffer Disabled. + * |[10] |LALIGN |DAC Data Left-aligned Enabled Control + * | | |0 = Right alignment. + * | | |1 = Left alignment. + * |[13:12] |ETRGSEL |External Pin Trigger Selection + * | | |00 = Low level trigger. + * | | |01 = High level trigger. + * | | |10 = Falling edge trigger. + * | | |11 = Rising edge trigger. + * |[15:14] |BWSEL |DAC Data Bit-width Selection + * | | |00 = data is 12 bits. + * | | |01 = data is 8 bits. + * | | |Others = reserved. + * |[16] |GRPEN |DAC Group Mode Enable Bit + * | | |0 = DAC0 and DAC1 are not grouped. + * | | |1 = DAC0 and DAC1 are grouped. + * @var DAC_T::SWTRG + * Offset: 0x04 DAC Software Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWTRG |Software Trigger + * | | |0 = Software trigger Disabled. + * | | |1 = Software trigger Enabled. + * | | |User writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically; Reading this bit will always get 0. + * @var DAC_T::DAT + * Offset: 0x08 DAC Data Holding Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DACDAT |DAC 12-bit Holding Data + * | | |These bits are written by user software which specifies 12-bit conversion data for DAC output. + * | | |The unused bits (DACDAT[3:0] in left-alignment mode and DACDAT[15:12] in right alignment mode) are ignored by DAC controller hardware. + * | | |12 bit left alignment: user has to load data into DACDAT[15:4] bits. + * | | |12 bit right alignment: user has to load data into DACDAT[11:0] bits. + * @var DAC_T::DATOUT + * Offset: 0x0C DAC Data Output Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DATOUT |DAC 12-bit Output Data + * | | |These bits are current digital data for DAC output conversion. + * | | |It is loaded from DAC_DAT register and user cannot write it directly. + * @var DAC_T::STATUS + * Offset: 0x10 DAC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FINISH |DAC Conversion Complete Finish Flag + * | | |0 = DAC is in conversion state. + * | | |1 = DAC conversion finish. + * | | |This bit set to 1 when conversion time counter counts to SETTLET. + * | | |It is cleared to 0 when DAC starts a new conversion. + * | | |User writes 1 to clear this bit to 0. + * |[1] |DMAUDR |DMA Under-run Interrupt Flag + * | | |0 = No DMA under-run error condition occurred. + * | | |1 = DMA under-run error condition occurred. + * | | |User writes 1 to clear this bit. + * |[8] |BUSY |DAC Busy Flag (Read Only) + * | | |0 = DAC is ready for next conversion. + * | | |1 = DAC is busy in conversion. + * | | |This is read only bit. + * @var DAC_T::TCTL + * Offset: 0x14 DAC Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |SETTLET |DAC Output Settling Time + * | | |User software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed. + * | | |For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET value must be greater than 0x40. + */ + __IO uint32_t CTL; /*!< [0x0000] DAC Control Register */ + __IO uint32_t SWTRG; /*!< [0x0004] DAC Software Trigger Control Register */ + __IO uint32_t DAT; /*!< [0x0008] DAC Data Holding Register */ + __I uint32_t DATOUT; /*!< [0x000c] DAC Data Output Register */ + __IO uint32_t STATUS; /*!< [0x0010] DAC Status Register */ + __IO uint32_t TCTL; /*!< [0x0014] DAC Timing Control Register */ + +} DAC_T; + +/** + @addtogroup DAC_CONST DAC Bit Field Definition + Constant Definitions for DAC Controller + @{ +*/ + +#define DAC_CTL_DACEN_Pos (0) /*!< DAC_T::CTL: DACEN Position */ +#define DAC_CTL_DACEN_Msk (0x1ul << DAC_CTL_DACEN_Pos) /*!< DAC_T::CTL: DACEN Mask */ + +#define DAC_CTL_DACIEN_Pos (1) /*!< DAC_T::CTL: DACIEN Position */ +#define DAC_CTL_DACIEN_Msk (0x1ul << DAC_CTL_DACIEN_Pos) /*!< DAC_T::CTL: DACIEN Mask */ + +#define DAC_CTL_DMAEN_Pos (2) /*!< DAC_T::CTL: DMAEN Position */ +#define DAC_CTL_DMAEN_Msk (0x1ul << DAC_CTL_DMAEN_Pos) /*!< DAC_T::CTL: DMAEN Mask */ + +#define DAC_CTL_DMAURIEN_Pos (3) /*!< DAC_T::CTL: DMAURIEN Position */ +#define DAC_CTL_DMAURIEN_Msk (0x1ul << DAC_CTL_DMAURIEN_Pos) /*!< DAC_T::CTL: DMAURIEN Mask */ + +#define DAC_CTL_TRGEN_Pos (4) /*!< DAC_T::CTL: TRGEN Position */ +#define DAC_CTL_TRGEN_Msk (0x1ul << DAC_CTL_TRGEN_Pos) /*!< DAC_T::CTL: TRGEN Mask */ + +#define DAC_CTL_TRGSEL_Pos (5) /*!< DAC_T::CTL: TRGSEL Position */ +#define DAC_CTL_TRGSEL_Msk (0x7ul << DAC_CTL_TRGSEL_Pos) /*!< DAC_T::CTL: TRGSEL Mask */ + +#define DAC_CTL_BYPASS_Pos (8) /*!< DAC_T::CTL: BYPASS Position */ +#define DAC_CTL_BYPASS_Msk (0x1ul << DAC_CTL_BYPASS_Pos) /*!< DAC_T::CTL: BYPASS Mask */ + +#define DAC_CTL_LALIGN_Pos (10) /*!< DAC_T::CTL: LALIGN Position */ +#define DAC_CTL_LALIGN_Msk (0x1ul << DAC_CTL_LALIGN_Pos) /*!< DAC_T::CTL: LALIGN Mask */ + +#define DAC_CTL_ETRGSEL_Pos (12) /*!< DAC_T::CTL: ETRGSEL Position */ +#define DAC_CTL_ETRGSEL_Msk (0x3ul << DAC_CTL_ETRGSEL_Pos) /*!< DAC_T::CTL: ETRGSEL Mask */ + +#define DAC_CTL_BWSEL_Pos (14) /*!< DAC_T::CTL: BWSEL Position */ +#define DAC_CTL_BWSEL_Msk (0x3ul << DAC_CTL_BWSEL_Pos) /*!< DAC_T::CTL: BWSEL Mask */ + +#define DAC_CTL_GRPEN_Pos (16) /*!< DAC_T::CTL: GRPEN Position */ +#define DAC_CTL_GRPEN_Msk (0x1ul << DAC_CTL_GRPEN_Pos) /*!< DAC_T::CTL: GRPEN Mask */ + +#define DAC_SWTRG_SWTRG_Pos (0) /*!< DAC_T::SWTRG: SWTRG Position */ +#define DAC_SWTRG_SWTRG_Msk (0x1ul << DAC_SWTRG_SWTRG_Pos) /*!< DAC_T::SWTRG: SWTRG Mask */ + +#define DAC_DAT_DACDAT_Pos (0) /*!< DAC_T::DAT: DACDAT Position */ +#define DAC_DAT_DACDAT_Msk (0xfffful << DAC_DAT_DACDAT_Pos) /*!< DAC_T::DAT: DACDAT Mask */ + +#define DAC_DATOUT_DATOUT_Pos (0) /*!< DAC_T::DATOUT: DATOUT Position */ +#define DAC_DATOUT_DATOUT_Msk (0xffful << DAC_DATOUT_DATOUT_Pos) /*!< DAC_T::DATOUT: DATOUT Mask */ + +#define DAC_STATUS_FINISH_Pos (0) /*!< DAC_T::STATUS: FINISH Position */ +#define DAC_STATUS_FINISH_Msk (0x1ul << DAC_STATUS_FINISH_Pos) /*!< DAC_T::STATUS: FINISH Mask */ + +#define DAC_STATUS_DMAUDR_Pos (1) /*!< DAC_T::STATUS: DMAUDR Position */ +#define DAC_STATUS_DMAUDR_Msk (0x1ul << DAC_STATUS_DMAUDR_Pos) /*!< DAC_T::STATUS: DMAUDR Mask */ + +#define DAC_STATUS_BUSY_Pos (8) /*!< DAC_T::STATUS: BUSY Position */ +#define DAC_STATUS_BUSY_Msk (0x1ul << DAC_STATUS_BUSY_Pos) /*!< DAC_T::STATUS: BUSY Mask */ + +#define DAC_TCTL_SETTLET_Pos (0) /*!< DAC_T::TCTL: SETTLET Position */ +#define DAC_TCTL_SETTLET_Msk (0x3fful << DAC_TCTL_SETTLET_Pos) /*!< DAC_T::TCTL: SETTLET Mask */ + +/**@}*/ /* DAC_CONST */ +/**@}*/ /* end of DAC register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __DAC_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/eadc_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/eadc_reg.h new file mode 100644 index 0000000000..9fe02f500c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/eadc_reg.h @@ -0,0 +1,1707 @@ +/**************************************************************************//** + * @file eadc_reg.h + * @version V1.00 + * @brief EADC register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EADC_REG_H__ +#define __EADC_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Enhanced Analog to Digital Converter -------------------------*/ +/** + @addtogroup EADC Enhanced Analog to Digital Converter(EADC) + Memory Mapped Structure for EADC Controller + @{ +*/ + + +typedef struct +{ + + + /** + * @var EADC_T::DAT[19] + * Offset: 0x00 ADC Data Register 0~18 for Sample Module 0~18 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Result + * | | |This field contains 12 bits conversion result. + * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. + * |[16] |OV |Overrun Flag + * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |0 = Data in RESULT[11:0] is recent conversion result. + * | | |1 = Data in RESULT[11:0] is overwrite. + * | | |Note: It is cleared by hardware after EADC_DAT register is read. + * |[17] |VALID |Valid Flag + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. + * | | |0 = Data in RESULT[11:0] bits is not valid. + * | | |1 = Data in RESULT[11:0] bits is valid. + * @var EADC_T::CURDAT + * Offset: 0x4C ADC PDMA Current Transfer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register + * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support. + * | | |This is a read only register. + * @var EADC_T::CTL + * Offset: 0x50 ADC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCEN |ADC Converter Enable Bit + * | | |0 = Disabled EADC. + * | | |1 = Enabled EADC. + * | | |Note: Before starting ADC conversion function, this bit should be set to 1 + * | | |Clear it to 0 to disable ADC converter analog circuit power consumption. + * |[1] |ADCRST |ADC Converter Control Circuits Reset + * | | |0 = No effect. + * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value. + * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. + * |[2] |ADCIEN0 |Specific Sample Module ADC ADINT0 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. + * | | |0 = Specific sample module ADC ADINT0 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT0 interrupt function Enabled. + * |[3] |ADCIEN1 |Specific Sample Module ADC ADINT1 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. + * | | |0 = Specific sample module ADC ADINT1 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT1 interrupt function Enabled. + * |[4] |ADCIEN2 |Specific Sample Module ADC ADINT2 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. + * | | |0 = Specific sample module ADC ADINT2 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT2 interrupt function Enabled. + * |[5] |ADCIEN3 |Specific Sample Module ADC ADINT3 Interrupt Enable Bit + * | | |The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion + * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. + * | | |0 = Specific sample module ADC ADINT3 interrupt function Disabled. + * | | |1 = Specific sample module ADC ADINT3 interrupt function Enabled. + * |[7:6] |RESSEL |Resolution Selection + * | | |00 = 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]). + * | | |01 = 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]). + * | | |10 = 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]). + * | | |11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]). + * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit + * | | |0 = Single-end analog input mode. + * | | |1 = Differential analog input mode. + * |[9] |DMOF |ADC Differential Input Mode Output Format + * | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format. + * | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format. + * @var EADC_T::SWTRG + * Offset: 0x54 ADC Sample Module Software Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SWTRG |ADC Sample Module 0~18 Software Force to Start ADC Conversion + * | | |0 = No effect. + * | | |1 = Cause an ADC conversion when the priority is given to sample module. + * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion + * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + * @var EADC_T::PENDSTS + * Offset: 0x58 ADC Start of Conversion Pending Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |STPF |ADC Sample Module 0~18 Start of Conversion Pending Flag + * | | |Read: + * | | |0 = There is no pending conversion for sample module. + * | | |1 = Sample module ADC start of conversion is pending. + * | | |Write: + * | | |1 = clear pending flag and cancel the conversion for sample module. + * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0 + * @var EADC_T::OVSTS + * Offset: 0x5C ADC Sample Module Start of Conversion Overrun Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[18:0] |SPOVF |ADC SAMPLE0~18 Overrun Flag + * | | |0 = No sample module event overrun. + * | | |1 = Indicates a new sample module event is generated while an old one event is pending. + * | | |Note: This bit is cleared by writing 1 to it. + * @var EADC_T::SCTL[19] + * Offset: 0x80 ADC Sample Module 0~18 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CHSEL |ADC Sample Module Channel Selection + * | | |00H = EADC_CH0 (slow channel). + * | | |01H = EADC_CH1 (slow channel). + * | | |02H = EADC_CH2 (slow channel). + * | | |03H = EADC_CH3 (slow channel). + * | | |04H = EADC_CH4 (slow channel). + * | | |05H = EADC_CH5 (slow channel). + * | | |06H = EADC_CH6 (slow channel). + * | | |07H = EADC_CH7 (slow channel). + * | | |08H = EADC_CH8 (slow channel). + * | | |09H = EADC_CH9 (slow channel). + * | | |0AH = EADC_CH10 (fast channel). + * | | |0BH = EADC_CH11 (fast channel). + * | | |0CH = EADC_CH12 (fast channel). + * | | |0DH = EADC_CH13 (fast channel). + * | | |0EH = EADC_CH14 (fast channel). + * | | |0FH = EADC_CH15 (fast channel). + * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit + * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. + * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit + * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. + * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. + * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection + * | | |Trigger delay clock frequency: + * | | |00 = ADC_CLK/1. + * | | |01 = ADC_CLK/2. + * | | |10 = ADC_CLK/4. + * | | |11 = ADC_CLK/16. + * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time + * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting). + * |[20:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection + * | | |0H = Disable trigger. + * | | |1H = External trigger from EADC0_ST pin input. + * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. + * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. + * | | |4H = Timer0 overflow pulse trigger. + * | | |5H = Timer1 overflow pulse trigger. + * | | |6H = Timer2 overflow pulse trigger. + * | | |7H = Timer3 overflow pulse trigger. + * | | |8H = Timer4 overflow pulse trigger. + * | | |9H = Timer5 overflow pulse trigger. + * | | |AH = EPWM0TG0. + * | | |BH = EPWM0TG1. + * | | |CH = EPWM0TG2. + * | | |DH = EPWM0TG3. + * | | |EH = EPWM0TG4. + * | | |FH = EPWM0TG5. + * | | |10H = EPWM1TG0. + * | | |11H = EPWM1TG1. + * | | |12H = EPWM1TG2. + * | | |13H = EPWM1TG3. + * | | |14H = EPWM1TG4. + * | | |15H = EPWM1TG5. + * | | |16H = BPWM0TG. + * | | |17H = BPWM1TG. + * | | |other = Reserved. + * |[22] |INTPOS |Interrupt Flag Position Select + * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. + * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. + * |[23] |DBMEN |Double Buffer Mode Enable Bit + * | | |0 = Sample has one sample result register. (default). + * | | |1 = Sample has two sample result registers. + * |[31:24] |EXTSMPT |ADC Sampling Time Extend + * | | |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time. + * | | |The range of start delay time is from 0~255 ADC clock. + * @var EADC_T::INTSRC[4] + * Offset: 0xD0 ADC interrupt 0~3 Source Enable Control Register. + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit + * | | |0 = Sample Module 0 interrupt Disabled. + * | | |1 = Sample Module 0 interrupt Enabled. + * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit + * | | |0 = Sample Module 1 interrupt Disabled. + * | | |1 = Sample Module 1 interrupt Enabled. + * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit + * | | |0 = Sample Module 2 interrupt Disabled. + * | | |1 = Sample Module 2 interrupt Enabled. + * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit + * | | |0 = Sample Module 3 interrupt Disabled. + * | | |1 = Sample Module 3 interrupt Enabled. + * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit + * | | |0 = Sample Module 4 interrupt Disabled. + * | | |1 = Sample Module 4 interrupt Enabled. + * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit + * | | |0 = Sample Module 5 interrupt Disabled. + * | | |1 = Sample Module 5 interrupt Enabled. + * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit + * | | |0 = Sample Module 6 interrupt Disabled. + * | | |1 = Sample Module 6 interrupt Enabled. + * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit + * | | |0 = Sample Module 7 interrupt Disabled. + * | | |1 = Sample Module 7 interrupt Enabled. + * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit + * | | |0 = Sample Module 8 interrupt Disabled. + * | | |1 = Sample Module 8 interrupt Enabled. + * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit + * | | |0 = Sample Module 9 interrupt Disabled. + * | | |1 = Sample Module 9 interrupt Enabled. + * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit + * | | |0 = Sample Module 10 interrupt Disabled. + * | | |1 = Sample Module 10 interrupt Enabled. + * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit + * | | |0 = Sample Module 11 interrupt Disabled. + * | | |1 = Sample Module 11 interrupt Enabled. + * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit + * | | |0 = Sample Module 12 interrupt Disabled. + * | | |1 = Sample Module 12 interrupt Enabled. + * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit + * | | |0 = Sample Module 13 interrupt Disabled. + * | | |1 = Sample Module 13 interrupt Enabled. + * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit + * | | |0 = Sample Module 14 interrupt Disabled. + * | | |1 = Sample Module 14 interrupt Enabled. + * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit + * | | |0 = Sample Module 15 interrupt Disabled. + * | | |1 = Sample Module 15 interrupt Enabled. + * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit + * | | |0 = Sample Module 16 interrupt Disabled. + * | | |1 = Sample Module 16 interrupt Enabled. + * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit + * | | |0 = Sample Module 17 interrupt Disabled. + * | | |1 = Sample Module 17 interrupt Enabled. + * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit + * | | |0 = Sample Module 18 interrupt Disabled. + * | | |1 = Sample Module 18 interrupt Enabled. + * @var EADC_T::CMP[4] + * Offset: 0xE0 ADC Result Compare Register 0~3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADCMPEN |ADC Result Compare Enable Bit + * | | |0 = Compare Disabled. + * | | |1 = Compare Enabled. + * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. + * |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit + * | | |0 = Compare function interrupt Disabled. + * | | |1 = Compare function interrupt Enabled. + * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. + * |[2] |CMPCOND |Compare Condition + * | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. + * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. + * |[7:3] |CMPSPL |Compare Sample Module Selection + * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. + * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. + * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. + * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. + * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. + * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. + * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. + * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. + * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. + * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared. + * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared. + * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared. + * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared. + * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared. + * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared. + * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared. + * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared. + * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared. + * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared. + * |[11:8] |CMPMCNT |Compare Match Count + * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 + * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 + * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. + * |[15] |CMPWEN |Compare Window Mode Enable Bit + * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched + * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched + * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. + * |[27:16] |CMPDAT |Comparison Data + * | | |The 12 bits data is used to compare with conversion result of specified sample module + * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. + * @var EADC_T::STATUS0 + * Offset: 0xF0 ADC Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). + * |[31:16] |OV |EADC_DAT0~15 Overrun Flag + * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). + * @var EADC_T::STATUS1 + * Offset: 0xF4 ADC Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag + * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). + * |[18:16] |OV |EADC_DAT16~18 Overrun Flag + * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). + * @var EADC_T::STATUS2 + * Offset: 0xF8 ADC Status Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADIF0 |ADC ADINT0 Interrupt Flag + * | | |0 = No ADINT0 interrupt pulse received. + * | | |1 = ADINT0 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[1] |ADIF1 |ADC ADINT1 Interrupt Flag + * | | |0 = No ADINT1 interrupt pulse received. + * | | |1 = ADINT1 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[2] |ADIF2 |ADC ADINT2 Interrupt Flag + * | | |0 = No ADINT2 interrupt pulse received. + * | | |1 = ADINT2 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[3] |ADIF3 |ADC ADINT3 Interrupt Flag + * | | |0 = No ADINT3 interrupt pulse received. + * | | |1 = ADINT3 interrupt pulse has been received. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed + * |[4] |ADCMPF0 |ADC Compare 0 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[5] |ADCMPF1 |ADC Compare 1 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |ADCMPF2 |ADC Compare 2 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[7] |ADCMPF3 |ADC Compare 3 Flag + * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. + * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting. + * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting. + * | | |Note: This bit is cleared by writing 1 to it. + * |[8] |ADOVIF0 |ADC ADINT0 Interrupt Flag Overrun + * | | |0 = ADINT0 interrupt flag is not overwritten to 1. + * | | |1 = ADINT0 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[9] |ADOVIF1 |ADC ADINT1 Interrupt Flag Overrun + * | | |0 = ADINT1 interrupt flag is not overwritten to 1. + * | | |1 = ADINT1 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[10] |ADOVIF2 |ADC ADINT2 Interrupt Flag Overrun + * | | |0 = ADINT2 interrupt flag is not overwritten to 1. + * | | |1 = ADINT2 interrupt flag is s overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[11] |ADOVIF3 |ADC ADINT3 Interrupt Flag Overrun + * | | |0 = ADINT3 interrupt flag is not overwritten to 1. + * | | |1 = ADINT3 interrupt flag is overwritten to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[12] |ADCMPO0 |ADC Compare 0 Output Status (Read Only) + * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting. + * |[13] |ADCMPO1 |ADC Compare 1 Output Status (Read Only) + * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting. + * |[14] |ADCMPO2 |ADC Compare 2 Output Status (Read Only) + * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting. + * |[15] |ADCMPO3 |ADC Compare 3 Output Status (Read Only) + * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. + * | | |User can use it to monitor the external analog input pin voltage status. + * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting. + * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting. + * |[20:16] |CHANNEL |Current Conversion Channel (Read Only) + * | | |This filed reflects ADC current conversion channel when BUSY=1. + * | | |It is read only. + * | | |00H = EADC_CH0. + * | | |01H = EADC_CH1. + * | | |02H = EADC_CH2. + * | | |03H = EADC_CH3. + * | | |04H = EADC_CH4. + * | | |05H = EADC_CH5. + * | | |06H = EADC_CH6. + * | | |07H = EADC_CH7. + * | | |08H = EADC_CH8. + * | | |09H = EADC_CH9. + * | | |0AH = EADC_CH10. + * | | |0BH = EADC_CH11. + * | | |0CH = EADC_CH12. + * | | |0DH = EADC_CH13. + * | | |0EH = EADC_CH14. + * | | |0FH = EADC_CH15. + * | | |10H = VBG. + * | | |11H = VTEMP. + * | | |12H = VBAT/4. + * |[23] |BUSY |Busy/Idle (Read Only) + * | | |0 = EADC is in idle state. + * | | |1 = EADC is busy at conversion. + * |[24] |ADOVIF |All ADC Interrupt Flag Overrun Bits Check (Read Only) + * | | |n=0~3. + * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1. + * |[25] |STOVF |for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1. + * |[26] |AVALID |for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1. + * |[27] |AOV |for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only) + * | | |n=0~18. + * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1. + * @var EADC_T::STATUS3 + * Offset: 0xFC ADC Status Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |CURSPL |ADC Current Sample Module + * | | |This register show the current ADC is controlled by which sample module control logic modules. + * | | |If the ADC is Idle, this bit filed will set to 0x1F. + * | | |This is a read only register. + * @var EADC_T::DDAT + * Offset: 0x100-0x10C ADC Double Data Register n for Sample Module n, n=0~3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RESULT |ADC Conversion Results + * | | |This field contains 12 bits conversion results. + * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. + * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. + * |[16] |OV |Overrun Flag + * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result. + * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite. + * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1. + * | | |It is cleared by hardware after EADC_DDAT register is read. + * |[17] |VALID |Valid Flag + * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. + * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. + * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read. + * | | |(n=0~3). + * @var EADC_T::PWRM + * Offset: 0x110 ADC Power Management Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWUPRDY |ADC Power-up Sequence Completed and Ready for Conversion (Read Only) + * | | |0 = ADC is not ready for conversion may be in power down state or in the progress of power up. + * | | |1 = ADC is ready for conversion. + * |[1] |PWUCALEN |Power Up Calibration Function Enable Control + * | | |0 = Disable the function of calibration at power up. + * | | |1 = Enable the function of calibration at power up. + * | | |Note: This bit work together with CALSEL (EADC_CALCTL [3]), see the following + * | | |{PWUCALEN, CALSEL } Description: + * | | |PWUCALEN is 0 and CALSEL is 0: No need to calibrate. + * | | |PWUCALEN is 0 and CALSEL is 1: No need to calibrate. + * | | |PWUCALEN is 1 and CALSEL is 0: Load calibration word when power up. + * | | |PWUCALEN is 1 and CALSEL is 1: Calibrate when power up. + * |[3:2] |PWDMOD |ADC Power-down Mode + * | | |Set this bit fields to select ADC power down mode when system power-down. + * | | |00 = ADC Deep power down mode. + * | | |01 = ADC Power down. + * | | |10 = ADC Standby mode. + * | | |11 = ADC Deep power down mode. + * | | |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in power down and start up + * |[19:8] |LDOSUT |ADC Internal LDO Start-up Time + * | | |Set this bit fields to control LDO start-up time + * | | |The minimum required LDO start-up time is 20us + * | | |LDO start-up time = (1/ADC_CLK) x LDOSUT. + * @var EADC_T::CALCTL + * Offset: 0x114 ADC Calibration Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |CALSTART |Calibration Functional Block Start + * | | |0 = Stops calibration functional block. + * | | |1 = Starts calibration functional block. + * | | |Note: This bit is set by SW and clear by HW after re-calibration finish + * |[2] |CALDONE |Calibration Functional Block Complete (Read Only) + * | | |0 = During a calibration. + * | | |1 = Calibration is completed. + * |[3] |CALSEL |Select Calibration Functional Block + * | | |0 = Load calibration word when calibration functional block is active. + * | | |1 = Execute calibration when calibration functional block is active. + * @var EADC_T::CALDWRD + * Offset: 0x118 ADC Calibration Load Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |CALWORD |Calibration Word Bits + * | | |Write to this register with the previous calibration word before load calibration action. + * | | |Read this register after calibration done. + * | | |Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done. + */ + + __I uint32_t DAT[19]; /*!< [0x0000~0x0048] ADC Data Register n for Sample Module n, n=0~18 */ + __I uint32_t CURDAT; /*!< [0x004c] ADC PDMA Current Transfer Data Register */ + __IO uint32_t CTL; /*!< [0x0050] ADC Control Register */ + __O uint32_t SWTRG; /*!< [0x0054] ADC Sample Module Software Start Register */ + __IO uint32_t PENDSTS; /*!< [0x0058] ADC Start of Conversion Pending Flag Register */ + __IO uint32_t OVSTS; /*!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register */ + __I uint32_t RESERVE0[8]; + __IO uint32_t SCTL[19]; /*!< [0x0080~0x00c8] ADC Sample Module n Control Register, n=0~18 */ + __I uint32_t RESERVE1[1]; + __IO uint32_t INTSRC[4]; /*!< [0x00d0~0x00dc] ADC interrupt n Source Enable Control Register, n=0~3 */ + __IO uint32_t CMP[4]; /*!< [0x00e0~0x00ec] ADC Result Compare Register n, n=0~3 */ + __I uint32_t STATUS0; /*!< [0x00f0] ADC Status Register 0 */ + __I uint32_t STATUS1; /*!< [0x00f4] ADC Status Register 1 */ + __IO uint32_t STATUS2; /*!< [0x00f8] ADC Status Register 2 */ + __I uint32_t STATUS3; /*!< [0x00fc] ADC Status Register 3 */ + __I uint32_t DDAT[4]; /*!< [0x0100~0x010c] ADC Double Data Register n for Sample Module n, n=0~3 */ + __IO uint32_t PWRM; /*!< [0x0110] ADC Power Management Register */ + __IO uint32_t CALCTL; /*!< [0x0114] ADC Calibration Control Register */ + __IO uint32_t CALDWRD; /*!< [0x0118] ADC Calibration Load Word Register */ + __I uint32_t RESERVE2[5]; + __IO uint32_t PDMACTL; /*!< [0x0130] ADC PDMA Control Register */ + +} EADC_T; + +/** + @addtogroup EADC_CONST EADC Bit Field Definition + Constant Definitions for EADC Controller + @{ +*/ + +#define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */ +#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */ + +#define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */ +#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */ + +#define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */ +#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */ + +#define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */ +#define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */ + +#define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */ +#define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */ + +#define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */ +#define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */ + +#define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */ +#define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */ + +#define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */ +#define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */ + +#define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */ +#define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */ + +#define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */ +#define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */ + +#define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */ +#define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */ + +#define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */ +#define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */ + +#define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */ +#define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */ + +#define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */ +#define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */ + +#define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */ +#define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */ + +#define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */ +#define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */ + +#define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */ +#define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */ + +#define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */ +#define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */ + +#define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */ +#define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */ + +#define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */ +#define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */ + +#define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */ +#define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */ + +#define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */ +#define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */ + +#define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */ +#define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */ + +#define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */ +#define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */ + +#define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */ +#define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */ + +#define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */ +#define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */ + +#define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */ +#define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */ + +#define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */ +#define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */ + +#define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */ +#define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */ + +#define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */ +#define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */ + +#define EADC_DAT9_RESULT_Pos (0) /*!< EADC_T::DAT9: RESULT Position */ +#define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /*!< EADC_T::DAT9: RESULT Mask */ + +#define EADC_DAT9_OV_Pos (16) /*!< EADC_T::DAT9: OV Position */ +#define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /*!< EADC_T::DAT9: OV Mask */ + +#define EADC_DAT9_VALID_Pos (17) /*!< EADC_T::DAT9: VALID Position */ +#define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /*!< EADC_T::DAT9: VALID Mask */ + +#define EADC_DAT10_RESULT_Pos (0) /*!< EADC_T::DAT10: RESULT Position */ +#define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /*!< EADC_T::DAT10: RESULT Mask */ + +#define EADC_DAT10_OV_Pos (16) /*!< EADC_T::DAT10: OV Position */ +#define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /*!< EADC_T::DAT10: OV Mask */ + +#define EADC_DAT10_VALID_Pos (17) /*!< EADC_T::DAT10: VALID Position */ +#define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /*!< EADC_T::DAT10: VALID Mask */ + +#define EADC_DAT11_RESULT_Pos (0) /*!< EADC_T::DAT11: RESULT Position */ +#define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /*!< EADC_T::DAT11: RESULT Mask */ + +#define EADC_DAT11_OV_Pos (16) /*!< EADC_T::DAT11: OV Position */ +#define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /*!< EADC_T::DAT11: OV Mask */ + +#define EADC_DAT11_VALID_Pos (17) /*!< EADC_T::DAT11: VALID Position */ +#define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /*!< EADC_T::DAT11: VALID Mask */ + +#define EADC_DAT12_RESULT_Pos (0) /*!< EADC_T::DAT12: RESULT Position */ +#define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /*!< EADC_T::DAT12: RESULT Mask */ + +#define EADC_DAT12_OV_Pos (16) /*!< EADC_T::DAT12: OV Position */ +#define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /*!< EADC_T::DAT12: OV Mask */ + +#define EADC_DAT12_VALID_Pos (17) /*!< EADC_T::DAT12: VALID Position */ +#define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /*!< EADC_T::DAT12: VALID Mask */ + +#define EADC_DAT13_RESULT_Pos (0) /*!< EADC_T::DAT13: RESULT Position */ +#define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /*!< EADC_T::DAT13: RESULT Mask */ + +#define EADC_DAT13_OV_Pos (16) /*!< EADC_T::DAT13: OV Position */ +#define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /*!< EADC_T::DAT13: OV Mask */ + +#define EADC_DAT13_VALID_Pos (17) /*!< EADC_T::DAT13: VALID Position */ +#define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /*!< EADC_T::DAT13: VALID Mask */ + +#define EADC_DAT14_RESULT_Pos (0) /*!< EADC_T::DAT14: RESULT Position */ +#define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /*!< EADC_T::DAT14: RESULT Mask */ + +#define EADC_DAT14_OV_Pos (16) /*!< EADC_T::DAT14: OV Position */ +#define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /*!< EADC_T::DAT14: OV Mask */ + +#define EADC_DAT14_VALID_Pos (17) /*!< EADC_T::DAT14: VALID Position */ +#define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /*!< EADC_T::DAT14: VALID Mask */ + +#define EADC_DAT15_RESULT_Pos (0) /*!< EADC_T::DAT15: RESULT Position */ +#define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /*!< EADC_T::DAT15: RESULT Mask */ + +#define EADC_DAT15_OV_Pos (16) /*!< EADC_T::DAT15: OV Position */ +#define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /*!< EADC_T::DAT15: OV Mask */ + +#define EADC_DAT15_VALID_Pos (17) /*!< EADC_T::DAT15: VALID Position */ +#define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /*!< EADC_T::DAT15: VALID Mask */ + +#define EADC_DAT16_RESULT_Pos (0) /*!< EADC_T::DAT16: RESULT Position */ +#define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /*!< EADC_T::DAT16: RESULT Mask */ + +#define EADC_DAT16_OV_Pos (16) /*!< EADC_T::DAT16: OV Position */ +#define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /*!< EADC_T::DAT16: OV Mask */ + +#define EADC_DAT16_VALID_Pos (17) /*!< EADC_T::DAT16: VALID Position */ +#define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /*!< EADC_T::DAT16: VALID Mask */ + +#define EADC_DAT17_RESULT_Pos (0) /*!< EADC_T::DAT17: RESULT Position */ +#define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /*!< EADC_T::DAT17: RESULT Mask */ + +#define EADC_DAT17_OV_Pos (16) /*!< EADC_T::DAT17: OV Position */ +#define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /*!< EADC_T::DAT17: OV Mask */ + +#define EADC_DAT17_VALID_Pos (17) /*!< EADC_T::DAT17: VALID Position */ +#define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /*!< EADC_T::DAT17: VALID Mask */ + +#define EADC_DAT18_RESULT_Pos (0) /*!< EADC_T::DAT18: RESULT Position */ +#define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /*!< EADC_T::DAT18: RESULT Mask */ + +#define EADC_DAT18_OV_Pos (16) /*!< EADC_T::DAT18: OV Position */ +#define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /*!< EADC_T::DAT18: OV Mask */ + +#define EADC_DAT18_VALID_Pos (17) /*!< EADC_T::DAT18: VALID Position */ +#define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /*!< EADC_T::DAT18: VALID Mask */ + +#define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */ +#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */ + +#define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */ +#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */ + +#define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */ +#define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */ + +#define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */ +#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */ + +#define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */ +#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */ + +#define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */ +#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */ + +#define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */ +#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */ + +#define EADC_CTL_RESSEL_Pos (6) /*!< EADC_T::CTL: RESSEL Position */ +#define EADC_CTL_RESSEL_Msk (0x3ul << EADC_CTL_RESSEL_Pos) /*!< EADC_T::CTL: RESSEL Mask */ + +#define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */ +#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */ + +#define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */ +#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */ + +#define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */ +#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */ + +#define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */ +#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */ + +#define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */ +#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */ + +#define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */ +#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */ + +#define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */ +#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */ + +#define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */ +#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */ + +#define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */ +#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */ + +#define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */ +#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */ + +#define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */ +#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */ + +#define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */ +#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */ + +#define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */ +#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */ + +#define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */ +#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */ + +#define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */ +#define EADC_SCTL0_CHSEL_Msk (0xful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */ + +#define EADC_SCTL0_EXTREN_Pos (4) /*!< EADC_T::SCTL0: EXTREN Position */ +#define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */ + +#define EADC_SCTL0_EXTFEN_Pos (5) /*!< EADC_T::SCTL0: EXTFEN Position */ +#define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */ + +#define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */ +#define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */ + +#define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */ +#define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */ + +#define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */ +#define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */ + +#define EADC_SCTL0_INTPOS_Pos (22) /*!< EADC_T::SCTL0: INTPOS Position */ +#define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */ + +#define EADC_SCTL0_DBMEN_Pos (23) /*!< EADC_T::SCTL0: DBMEN Position */ +#define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /*!< EADC_T::SCTL0: DBMEN Mask */ + +#define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0: EXTSMPT Position */ +#define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0: EXTSMPT Mask */ + +#define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */ +#define EADC_SCTL1_CHSEL_Msk (0xful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */ + +#define EADC_SCTL1_EXTREN_Pos (4) /*!< EADC_T::SCTL1: EXTREN Position */ +#define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */ + +#define EADC_SCTL1_EXTFEN_Pos (5) /*!< EADC_T::SCTL1: EXTFEN Position */ +#define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */ + +#define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */ +#define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */ + +#define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */ +#define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */ + +#define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */ +#define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */ + +#define EADC_SCTL1_INTPOS_Pos (22) /*!< EADC_T::SCTL1: INTPOS Position */ +#define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */ + +#define EADC_SCTL1_DBMEN_Pos (23) /*!< EADC_T::SCTL1: DBMEN Position */ +#define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /*!< EADC_T::SCTL1: DBMEN Mask */ + +#define EADC_SCTL1_EXTSMPT_Pos (24) /*!< EADC_T::SCTL1: EXTSMPT Position */ +#define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /*!< EADC_T::SCTL1: EXTSMPT Mask */ + +#define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */ +#define EADC_SCTL2_CHSEL_Msk (0xful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */ + +#define EADC_SCTL2_EXTREN_Pos (4) /*!< EADC_T::SCTL2: EXTREN Position */ +#define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */ + +#define EADC_SCTL2_EXTFEN_Pos (5) /*!< EADC_T::SCTL2: EXTFEN Position */ +#define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */ + +#define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */ +#define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */ + +#define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */ +#define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */ + +#define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */ +#define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */ + +#define EADC_SCTL2_INTPOS_Pos (22) /*!< EADC_T::SCTL2: INTPOS Position */ +#define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */ + +#define EADC_SCTL2_DBMEN_Pos (23) /*!< EADC_T::SCTL2: DBMEN Position */ +#define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /*!< EADC_T::SCTL2: DBMEN Mask */ + +#define EADC_SCTL2_EXTSMPT_Pos (24) /*!< EADC_T::SCTL2: EXTSMPT Position */ +#define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /*!< EADC_T::SCTL2: EXTSMPT Mask */ + +#define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */ +#define EADC_SCTL3_CHSEL_Msk (0xful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */ + +#define EADC_SCTL3_EXTREN_Pos (4) /*!< EADC_T::SCTL3: EXTREN Position */ +#define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */ + +#define EADC_SCTL3_EXTFEN_Pos (5) /*!< EADC_T::SCTL3: EXTFEN Position */ +#define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */ + +#define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */ +#define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */ + +#define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */ +#define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */ + +#define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */ +#define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */ + +#define EADC_SCTL3_INTPOS_Pos (22) /*!< EADC_T::SCTL3: INTPOS Position */ +#define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */ + +#define EADC_SCTL3_DBMEN_Pos (23) /*!< EADC_T::SCTL3: DBMEN Position */ +#define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /*!< EADC_T::SCTL3: DBMEN Mask */ + +#define EADC_SCTL3_EXTSMPT_Pos (24) /*!< EADC_T::SCTL3: EXTSMPT Position */ +#define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /*!< EADC_T::SCTL3: EXTSMPT Mask */ + +#define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */ +#define EADC_SCTL4_CHSEL_Msk (0xful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */ + +#define EADC_SCTL4_EXTREN_Pos (4) /*!< EADC_T::SCTL4: EXTREN Position */ +#define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */ + +#define EADC_SCTL4_EXTFEN_Pos (5) /*!< EADC_T::SCTL4: EXTFEN Position */ +#define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */ + +#define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */ +#define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */ + +#define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */ +#define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */ + +#define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */ +#define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */ + +#define EADC_SCTL4_INTPOS_Pos (22) /*!< EADC_T::SCTL4: INTPOS Position */ +#define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */ + +#define EADC_SCTL4_EXTSMPT_Pos (24) /*!< EADC_T::SCTL4: EXTSMPT Position */ +#define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /*!< EADC_T::SCTL4: EXTSMPT Mask */ + +#define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */ +#define EADC_SCTL5_CHSEL_Msk (0xful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */ + +#define EADC_SCTL5_EXTREN_Pos (4) /*!< EADC_T::SCTL5: EXTREN Position */ +#define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */ + +#define EADC_SCTL5_EXTFEN_Pos (5) /*!< EADC_T::SCTL5: EXTFEN Position */ +#define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */ + +#define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */ +#define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */ + +#define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */ +#define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */ + +#define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */ +#define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */ + +#define EADC_SCTL5_INTPOS_Pos (22) /*!< EADC_T::SCTL5: INTPOS Position */ +#define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */ + +#define EADC_SCTL5_EXTSMPT_Pos (24) /*!< EADC_T::SCTL5: EXTSMPT Position */ +#define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /*!< EADC_T::SCTL5: EXTSMPT Mask */ + +#define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */ +#define EADC_SCTL6_CHSEL_Msk (0xful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */ + +#define EADC_SCTL6_EXTREN_Pos (4) /*!< EADC_T::SCTL6: EXTREN Position */ +#define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */ + +#define EADC_SCTL6_EXTFEN_Pos (5) /*!< EADC_T::SCTL6: EXTFEN Position */ +#define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */ + +#define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */ +#define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */ + +#define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */ +#define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */ + +#define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */ +#define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */ + +#define EADC_SCTL6_INTPOS_Pos (22) /*!< EADC_T::SCTL6: INTPOS Position */ +#define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */ + +#define EADC_SCTL6_EXTSMPT_Pos (24) /*!< EADC_T::SCTL6: EXTSMPT Position */ +#define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /*!< EADC_T::SCTL6: EXTSMPT Mask */ + +#define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */ +#define EADC_SCTL7_CHSEL_Msk (0xful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */ + +#define EADC_SCTL7_EXTREN_Pos (4) /*!< EADC_T::SCTL7: EXTREN Position */ +#define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */ + +#define EADC_SCTL7_EXTFEN_Pos (5) /*!< EADC_T::SCTL7: EXTFEN Position */ +#define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */ + +#define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */ +#define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */ + +#define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */ +#define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */ + +#define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */ +#define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */ + +#define EADC_SCTL7_INTPOS_Pos (22) /*!< EADC_T::SCTL7: INTPOS Position */ +#define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */ + +#define EADC_SCTL7_EXTSMPT_Pos (24) /*!< EADC_T::SCTL7: EXTSMPT Position */ +#define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /*!< EADC_T::SCTL7: EXTSMPT Mask */ + +#define EADC_SCTL8_CHSEL_Pos (0) /*!< EADC_T::SCTL8: CHSEL Position */ +#define EADC_SCTL8_CHSEL_Msk (0xful << EADC_SCTL8_CHSEL_Pos) /*!< EADC_T::SCTL8: CHSEL Mask */ + +#define EADC_SCTL8_EXTREN_Pos (4) /*!< EADC_T::SCTL8: EXTREN Position */ +#define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /*!< EADC_T::SCTL8: EXTREN Mask */ + +#define EADC_SCTL8_EXTFEN_Pos (5) /*!< EADC_T::SCTL8: EXTFEN Position */ +#define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /*!< EADC_T::SCTL8: EXTFEN Mask */ + +#define EADC_SCTL8_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL8: TRGDLYDIV Position */ +#define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /*!< EADC_T::SCTL8: TRGDLYDIV Mask */ + +#define EADC_SCTL8_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL8: TRGDLYCNT Position */ +#define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /*!< EADC_T::SCTL8: TRGDLYCNT Mask */ + +#define EADC_SCTL8_TRGSEL_Pos (16) /*!< EADC_T::SCTL8: TRGSEL Position */ +#define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) /*!< EADC_T::SCTL8: TRGSEL Mask */ + +#define EADC_SCTL8_INTPOS_Pos (22) /*!< EADC_T::SCTL8: INTPOS Position */ +#define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /*!< EADC_T::SCTL8: INTPOS Mask */ + +#define EADC_SCTL8_EXTSMPT_Pos (24) /*!< EADC_T::SCTL8: EXTSMPT Position */ +#define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /*!< EADC_T::SCTL8: EXTSMPT Mask */ + +#define EADC_SCTL9_CHSEL_Pos (0) /*!< EADC_T::SCTL9: CHSEL Position */ +#define EADC_SCTL9_CHSEL_Msk (0xful << EADC_SCTL9_CHSEL_Pos) /*!< EADC_T::SCTL9: CHSEL Mask */ + +#define EADC_SCTL9_EXTREN_Pos (4) /*!< EADC_T::SCTL9: EXTREN Position */ +#define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /*!< EADC_T::SCTL9: EXTREN Mask */ + +#define EADC_SCTL9_EXTFEN_Pos (5) /*!< EADC_T::SCTL9: EXTFEN Position */ +#define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /*!< EADC_T::SCTL9: EXTFEN Mask */ + +#define EADC_SCTL9_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL9: TRGDLYDIV Position */ +#define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /*!< EADC_T::SCTL9: TRGDLYDIV Mask */ + +#define EADC_SCTL9_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL9: TRGDLYCNT Position */ +#define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /*!< EADC_T::SCTL9: TRGDLYCNT Mask */ + +#define EADC_SCTL9_TRGSEL_Pos (16) /*!< EADC_T::SCTL9: TRGSEL Position */ +#define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) /*!< EADC_T::SCTL9: TRGSEL Mask */ + +#define EADC_SCTL9_INTPOS_Pos (22) /*!< EADC_T::SCTL9: INTPOS Position */ +#define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /*!< EADC_T::SCTL9: INTPOS Mask */ + +#define EADC_SCTL9_EXTSMPT_Pos (24) /*!< EADC_T::SCTL9: EXTSMPT Position */ +#define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /*!< EADC_T::SCTL9: EXTSMPT Mask */ + +#define EADC_SCTL10_CHSEL_Pos (0) /*!< EADC_T::SCTL10: CHSEL Position */ +#define EADC_SCTL10_CHSEL_Msk (0xful << EADC_SCTL10_CHSEL_Pos) /*!< EADC_T::SCTL10: CHSEL Mask */ + +#define EADC_SCTL10_EXTREN_Pos (4) /*!< EADC_T::SCTL10: EXTREN Position */ +#define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /*!< EADC_T::SCTL10: EXTREN Mask */ + +#define EADC_SCTL10_EXTFEN_Pos (5) /*!< EADC_T::SCTL10: EXTFEN Position */ +#define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /*!< EADC_T::SCTL10: EXTFEN Mask */ + +#define EADC_SCTL10_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL10: TRGDLYDIV Position */ +#define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /*!< EADC_T::SCTL10: TRGDLYDIV Mask */ + +#define EADC_SCTL10_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL10: TRGDLYCNT Position */ +#define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /*!< EADC_T::SCTL10: TRGDLYCNT Mask */ + +#define EADC_SCTL10_TRGSEL_Pos (16) /*!< EADC_T::SCTL10: TRGSEL Position */ +#define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) /*!< EADC_T::SCTL10: TRGSEL Mask */ + +#define EADC_SCTL10_INTPOS_Pos (22) /*!< EADC_T::SCTL10: INTPOS Position */ +#define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /*!< EADC_T::SCTL10: INTPOS Mask */ + +#define EADC_SCTL10_EXTSMPT_Pos (24) /*!< EADC_T::SCTL10: EXTSMPT Position */ +#define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /*!< EADC_T::SCTL10: EXTSMPT Mask */ + +#define EADC_SCTL11_CHSEL_Pos (0) /*!< EADC_T::SCTL11: CHSEL Position */ +#define EADC_SCTL11_CHSEL_Msk (0xful << EADC_SCTL11_CHSEL_Pos) /*!< EADC_T::SCTL11: CHSEL Mask */ + +#define EADC_SCTL11_EXTREN_Pos (4) /*!< EADC_T::SCTL11: EXTREN Position */ +#define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /*!< EADC_T::SCTL11: EXTREN Mask */ + +#define EADC_SCTL11_EXTFEN_Pos (5) /*!< EADC_T::SCTL11: EXTFEN Position */ +#define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /*!< EADC_T::SCTL11: EXTFEN Mask */ + +#define EADC_SCTL11_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL11: TRGDLYDIV Position */ +#define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /*!< EADC_T::SCTL11: TRGDLYDIV Mask */ + +#define EADC_SCTL11_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL11: TRGDLYCNT Position */ +#define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /*!< EADC_T::SCTL11: TRGDLYCNT Mask */ + +#define EADC_SCTL11_TRGSEL_Pos (16) /*!< EADC_T::SCTL11: TRGSEL Position */ +#define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) /*!< EADC_T::SCTL11: TRGSEL Mask */ + +#define EADC_SCTL11_INTPOS_Pos (22) /*!< EADC_T::SCTL11: INTPOS Position */ +#define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /*!< EADC_T::SCTL11: INTPOS Mask */ + +#define EADC_SCTL11_EXTSMPT_Pos (24) /*!< EADC_T::SCTL11: EXTSMPT Position */ +#define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /*!< EADC_T::SCTL11: EXTSMPT Mask */ + +#define EADC_SCTL12_CHSEL_Pos (0) /*!< EADC_T::SCTL12: CHSEL Position */ +#define EADC_SCTL12_CHSEL_Msk (0xful << EADC_SCTL12_CHSEL_Pos) /*!< EADC_T::SCTL12: CHSEL Mask */ + +#define EADC_SCTL12_EXTREN_Pos (4) /*!< EADC_T::SCTL12: EXTREN Position */ +#define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /*!< EADC_T::SCTL12: EXTREN Mask */ + +#define EADC_SCTL12_EXTFEN_Pos (5) /*!< EADC_T::SCTL12: EXTFEN Position */ +#define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /*!< EADC_T::SCTL12: EXTFEN Mask */ + +#define EADC_SCTL12_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL12: TRGDLYDIV Position */ +#define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /*!< EADC_T::SCTL12: TRGDLYDIV Mask */ + +#define EADC_SCTL12_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL12: TRGDLYCNT Position */ +#define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /*!< EADC_T::SCTL12: TRGDLYCNT Mask */ + +#define EADC_SCTL12_TRGSEL_Pos (16) /*!< EADC_T::SCTL12: TRGSEL Position */ +#define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) /*!< EADC_T::SCTL12: TRGSEL Mask */ + +#define EADC_SCTL12_INTPOS_Pos (22) /*!< EADC_T::SCTL12: INTPOS Position */ +#define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /*!< EADC_T::SCTL12: INTPOS Mask */ + +#define EADC_SCTL12_EXTSMPT_Pos (24) /*!< EADC_T::SCTL12: EXTSMPT Position */ +#define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /*!< EADC_T::SCTL12: EXTSMPT Mask */ + +#define EADC_SCTL13_CHSEL_Pos (0) /*!< EADC_T::SCTL13: CHSEL Position */ +#define EADC_SCTL13_CHSEL_Msk (0xful << EADC_SCTL13_CHSEL_Pos) /*!< EADC_T::SCTL13: CHSEL Mask */ + +#define EADC_SCTL13_EXTREN_Pos (4) /*!< EADC_T::SCTL13: EXTREN Position */ +#define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /*!< EADC_T::SCTL13: EXTREN Mask */ + +#define EADC_SCTL13_EXTFEN_Pos (5) /*!< EADC_T::SCTL13: EXTFEN Position */ +#define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /*!< EADC_T::SCTL13: EXTFEN Mask */ + +#define EADC_SCTL13_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL13: TRGDLYDIV Position */ +#define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /*!< EADC_T::SCTL13: TRGDLYDIV Mask */ + +#define EADC_SCTL13_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL13: TRGDLYCNT Position */ +#define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /*!< EADC_T::SCTL13: TRGDLYCNT Mask */ + +#define EADC_SCTL13_TRGSEL_Pos (16) /*!< EADC_T::SCTL13: TRGSEL Position */ +#define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) /*!< EADC_T::SCTL13: TRGSEL Mask */ + +#define EADC_SCTL13_INTPOS_Pos (22) /*!< EADC_T::SCTL13: INTPOS Position */ +#define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /*!< EADC_T::SCTL13: INTPOS Mask */ + +#define EADC_SCTL13_EXTSMPT_Pos (24) /*!< EADC_T::SCTL13: EXTSMPT Position */ +#define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /*!< EADC_T::SCTL13: EXTSMPT Mask */ + +#define EADC_SCTL14_CHSEL_Pos (0) /*!< EADC_T::SCTL14: CHSEL Position */ +#define EADC_SCTL14_CHSEL_Msk (0xful << EADC_SCTL14_CHSEL_Pos) /*!< EADC_T::SCTL14: CHSEL Mask */ + +#define EADC_SCTL14_EXTREN_Pos (4) /*!< EADC_T::SCTL14: EXTREN Position */ +#define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /*!< EADC_T::SCTL14: EXTREN Mask */ + +#define EADC_SCTL14_EXTFEN_Pos (5) /*!< EADC_T::SCTL14: EXTFEN Position */ +#define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /*!< EADC_T::SCTL14: EXTFEN Mask */ + +#define EADC_SCTL14_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL14: TRGDLYDIV Position */ +#define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /*!< EADC_T::SCTL14: TRGDLYDIV Mask */ + +#define EADC_SCTL14_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL14: TRGDLYCNT Position */ +#define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /*!< EADC_T::SCTL14: TRGDLYCNT Mask */ + +#define EADC_SCTL14_TRGSEL_Pos (16) /*!< EADC_T::SCTL14: TRGSEL Position */ +#define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) /*!< EADC_T::SCTL14: TRGSEL Mask */ + +#define EADC_SCTL14_INTPOS_Pos (22) /*!< EADC_T::SCTL14: INTPOS Position */ +#define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /*!< EADC_T::SCTL14: INTPOS Mask */ + +#define EADC_SCTL14_EXTSMPT_Pos (24) /*!< EADC_T::SCTL14: EXTSMPT Position */ +#define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /*!< EADC_T::SCTL14: EXTSMPT Mask */ + +#define EADC_SCTL15_CHSEL_Pos (0) /*!< EADC_T::SCTL15: CHSEL Position */ +#define EADC_SCTL15_CHSEL_Msk (0xful << EADC_SCTL15_CHSEL_Pos) /*!< EADC_T::SCTL15: CHSEL Mask */ + +#define EADC_SCTL15_EXTREN_Pos (4) /*!< EADC_T::SCTL15: EXTREN Position */ +#define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /*!< EADC_T::SCTL15: EXTREN Mask */ + +#define EADC_SCTL15_EXTFEN_Pos (5) /*!< EADC_T::SCTL15: EXTFEN Position */ +#define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /*!< EADC_T::SCTL15: EXTFEN Mask */ + +#define EADC_SCTL15_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL15: TRGDLYDIV Position */ +#define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /*!< EADC_T::SCTL15: TRGDLYDIV Mask */ + +#define EADC_SCTL15_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL15: TRGDLYCNT Position */ +#define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /*!< EADC_T::SCTL15: TRGDLYCNT Mask */ + +#define EADC_SCTL15_TRGSEL_Pos (16) /*!< EADC_T::SCTL15: TRGSEL Position */ +#define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) /*!< EADC_T::SCTL15: TRGSEL Mask */ + +#define EADC_SCTL15_INTPOS_Pos (22) /*!< EADC_T::SCTL15: INTPOS Position */ +#define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /*!< EADC_T::SCTL15: INTPOS Mask */ + +#define EADC_SCTL15_EXTSMPT_Pos (24) /*!< EADC_T::SCTL15: EXTSMPT Position */ +#define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /*!< EADC_T::SCTL15: EXTSMPT Mask */ + +#define EADC_SCTL16_EXTSMPT_Pos (24) /*!< EADC_T::SCTL16: EXTSMPT Position */ +#define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /*!< EADC_T::SCTL16: EXTSMPT Mask */ + +#define EADC_SCTL17_EXTSMPT_Pos (24) /*!< EADC_T::SCTL17: EXTSMPT Position */ +#define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /*!< EADC_T::SCTL17: EXTSMPT Mask */ + +#define EADC_SCTL18_EXTSMPT_Pos (24) /*!< EADC_T::SCTL18: EXTSMPT Position */ +#define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /*!< EADC_T::SCTL18: EXTSMPT Mask */ + +#define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */ +#define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */ + +#define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */ +#define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */ + +#define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */ +#define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */ + +#define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */ +#define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */ + +#define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */ +#define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */ + +#define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */ +#define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */ + +#define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */ +#define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */ + +#define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */ +#define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */ + +#define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */ +#define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */ + +#define EADC_INTSRC0_SPLIE9_Pos (9) /*!< EADC_T::INTSRC0: SPLIE9 Position */ +#define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /*!< EADC_T::INTSRC0: SPLIE9 Mask */ + +#define EADC_INTSRC0_SPLIE10_Pos (10) /*!< EADC_T::INTSRC0: SPLIE10 Position */ +#define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /*!< EADC_T::INTSRC0: SPLIE10 Mask */ + +#define EADC_INTSRC0_SPLIE11_Pos (11) /*!< EADC_T::INTSRC0: SPLIE11 Position */ +#define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /*!< EADC_T::INTSRC0: SPLIE11 Mask */ + +#define EADC_INTSRC0_SPLIE12_Pos (12) /*!< EADC_T::INTSRC0: SPLIE12 Position */ +#define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /*!< EADC_T::INTSRC0: SPLIE12 Mask */ + +#define EADC_INTSRC0_SPLIE13_Pos (13) /*!< EADC_T::INTSRC0: SPLIE13 Position */ +#define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /*!< EADC_T::INTSRC0: SPLIE13 Mask */ + +#define EADC_INTSRC0_SPLIE14_Pos (14) /*!< EADC_T::INTSRC0: SPLIE14 Position */ +#define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /*!< EADC_T::INTSRC0: SPLIE14 Mask */ + +#define EADC_INTSRC0_SPLIE15_Pos (15) /*!< EADC_T::INTSRC0: SPLIE15 Position */ +#define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /*!< EADC_T::INTSRC0: SPLIE15 Mask */ + +#define EADC_INTSRC0_SPLIE16_Pos (16) /*!< EADC_T::INTSRC0: SPLIE16 Position */ +#define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /*!< EADC_T::INTSRC0: SPLIE16 Mask */ + +#define EADC_INTSRC0_SPLIE17_Pos (17) /*!< EADC_T::INTSRC0: SPLIE17 Position */ +#define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /*!< EADC_T::INTSRC0: SPLIE17 Mask */ + +#define EADC_INTSRC0_SPLIE18_Pos (18) /*!< EADC_T::INTSRC0: SPLIE18 Position */ +#define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /*!< EADC_T::INTSRC0: SPLIE18 Mask */ + +#define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */ +#define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */ + +#define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */ +#define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */ + +#define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */ +#define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */ + +#define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */ +#define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */ + +#define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */ +#define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */ + +#define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */ +#define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */ + +#define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */ +#define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */ + +#define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */ +#define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */ + +#define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */ +#define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */ + +#define EADC_INTSRC1_SPLIE9_Pos (9) /*!< EADC_T::INTSRC1: SPLIE9 Position */ +#define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /*!< EADC_T::INTSRC1: SPLIE9 Mask */ + +#define EADC_INTSRC1_SPLIE10_Pos (10) /*!< EADC_T::INTSRC1: SPLIE10 Position */ +#define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /*!< EADC_T::INTSRC1: SPLIE10 Mask */ + +#define EADC_INTSRC1_SPLIE11_Pos (11) /*!< EADC_T::INTSRC1: SPLIE11 Position */ +#define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /*!< EADC_T::INTSRC1: SPLIE11 Mask */ + +#define EADC_INTSRC1_SPLIE12_Pos (12) /*!< EADC_T::INTSRC1: SPLIE12 Position */ +#define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /*!< EADC_T::INTSRC1: SPLIE12 Mask */ + +#define EADC_INTSRC1_SPLIE13_Pos (13) /*!< EADC_T::INTSRC1: SPLIE13 Position */ +#define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /*!< EADC_T::INTSRC1: SPLIE13 Mask */ + +#define EADC_INTSRC1_SPLIE14_Pos (14) /*!< EADC_T::INTSRC1: SPLIE14 Position */ +#define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /*!< EADC_T::INTSRC1: SPLIE14 Mask */ + +#define EADC_INTSRC1_SPLIE15_Pos (15) /*!< EADC_T::INTSRC1: SPLIE15 Position */ +#define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /*!< EADC_T::INTSRC1: SPLIE15 Mask */ + +#define EADC_INTSRC1_SPLIE16_Pos (16) /*!< EADC_T::INTSRC1: SPLIE16 Position */ +#define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /*!< EADC_T::INTSRC1: SPLIE16 Mask */ + +#define EADC_INTSRC1_SPLIE17_Pos (17) /*!< EADC_T::INTSRC1: SPLIE17 Position */ +#define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /*!< EADC_T::INTSRC1: SPLIE17 Mask */ + +#define EADC_INTSRC1_SPLIE18_Pos (18) /*!< EADC_T::INTSRC1: SPLIE18 Position */ +#define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /*!< EADC_T::INTSRC1: SPLIE18 Mask */ + +#define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */ +#define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */ + +#define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */ +#define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */ + +#define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */ +#define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */ + +#define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */ +#define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */ + +#define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */ +#define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */ + +#define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */ +#define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */ + +#define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */ +#define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */ + +#define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */ +#define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */ + +#define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */ +#define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */ + +#define EADC_INTSRC2_SPLIE9_Pos (9) /*!< EADC_T::INTSRC2: SPLIE9 Position */ +#define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /*!< EADC_T::INTSRC2: SPLIE9 Mask */ + +#define EADC_INTSRC2_SPLIE10_Pos (10) /*!< EADC_T::INTSRC2: SPLIE10 Position */ +#define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /*!< EADC_T::INTSRC2: SPLIE10 Mask */ + +#define EADC_INTSRC2_SPLIE11_Pos (11) /*!< EADC_T::INTSRC2: SPLIE11 Position */ +#define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /*!< EADC_T::INTSRC2: SPLIE11 Mask */ + +#define EADC_INTSRC2_SPLIE12_Pos (12) /*!< EADC_T::INTSRC2: SPLIE12 Position */ +#define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /*!< EADC_T::INTSRC2: SPLIE12 Mask */ + +#define EADC_INTSRC2_SPLIE13_Pos (13) /*!< EADC_T::INTSRC2: SPLIE13 Position */ +#define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /*!< EADC_T::INTSRC2: SPLIE13 Mask */ + +#define EADC_INTSRC2_SPLIE14_Pos (14) /*!< EADC_T::INTSRC2: SPLIE14 Position */ +#define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /*!< EADC_T::INTSRC2: SPLIE14 Mask */ + +#define EADC_INTSRC2_SPLIE15_Pos (15) /*!< EADC_T::INTSRC2: SPLIE15 Position */ +#define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /*!< EADC_T::INTSRC2: SPLIE15 Mask */ + +#define EADC_INTSRC2_SPLIE16_Pos (16) /*!< EADC_T::INTSRC2: SPLIE16 Position */ +#define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /*!< EADC_T::INTSRC2: SPLIE16 Mask */ + +#define EADC_INTSRC2_SPLIE17_Pos (17) /*!< EADC_T::INTSRC2: SPLIE17 Position */ +#define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /*!< EADC_T::INTSRC2: SPLIE17 Mask */ + +#define EADC_INTSRC2_SPLIE18_Pos (18) /*!< EADC_T::INTSRC2: SPLIE18 Position */ +#define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /*!< EADC_T::INTSRC2: SPLIE18 Mask */ + +#define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */ +#define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */ + +#define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */ +#define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */ + +#define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */ +#define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */ + +#define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */ +#define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */ + +#define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */ +#define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */ + +#define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */ +#define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */ + +#define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */ +#define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */ + +#define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */ +#define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */ + +#define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */ +#define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */ + +#define EADC_INTSRC3_SPLIE9_Pos (9) /*!< EADC_T::INTSRC3: SPLIE9 Position */ +#define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /*!< EADC_T::INTSRC3: SPLIE9 Mask */ + +#define EADC_INTSRC3_SPLIE10_Pos (10) /*!< EADC_T::INTSRC3: SPLIE10 Position */ +#define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /*!< EADC_T::INTSRC3: SPLIE10 Mask */ + +#define EADC_INTSRC3_SPLIE11_Pos (11) /*!< EADC_T::INTSRC3: SPLIE11 Position */ +#define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /*!< EADC_T::INTSRC3: SPLIE11 Mask */ + +#define EADC_INTSRC3_SPLIE12_Pos (12) /*!< EADC_T::INTSRC3: SPLIE12 Position */ +#define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /*!< EADC_T::INTSRC3: SPLIE12 Mask */ + +#define EADC_INTSRC3_SPLIE13_Pos (13) /*!< EADC_T::INTSRC3: SPLIE13 Position */ +#define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /*!< EADC_T::INTSRC3: SPLIE13 Mask */ + +#define EADC_INTSRC3_SPLIE14_Pos (14) /*!< EADC_T::INTSRC3: SPLIE14 Position */ +#define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /*!< EADC_T::INTSRC3: SPLIE14 Mask */ + +#define EADC_INTSRC3_SPLIE15_Pos (15) /*!< EADC_T::INTSRC3: SPLIE15 Position */ +#define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /*!< EADC_T::INTSRC3: SPLIE15 Mask */ + +#define EADC_INTSRC3_SPLIE16_Pos (16) /*!< EADC_T::INTSRC3: SPLIE16 Position */ +#define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /*!< EADC_T::INTSRC3: SPLIE16 Mask */ + +#define EADC_INTSRC3_SPLIE17_Pos (17) /*!< EADC_T::INTSRC3: SPLIE17 Position */ +#define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /*!< EADC_T::INTSRC3: SPLIE17 Mask */ + +#define EADC_INTSRC3_SPLIE18_Pos (18) /*!< EADC_T::INTSRC3: SPLIE18 Position */ +#define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /*!< EADC_T::INTSRC3: SPLIE18 Mask */ + +#define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */ +#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */ + +#define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */ +#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */ + +#define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */ +#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */ + +#define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */ +#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */ + +#define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */ +#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */ + +#define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */ +#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */ + +#define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */ +#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */ + +#define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */ +#define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */ + +#define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */ +#define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */ + +#define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */ +#define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */ + +#define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */ +#define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */ + +#define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */ +#define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */ + +#define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */ +#define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */ + +#define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */ +#define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */ + +#define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */ +#define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */ + +#define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */ +#define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */ + +#define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */ +#define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */ + +#define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */ +#define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */ + +#define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */ +#define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */ + +#define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */ +#define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */ + +#define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */ +#define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */ + +#define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */ +#define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */ + +#define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */ +#define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */ + +#define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */ +#define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */ + +#define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */ +#define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */ + +#define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */ +#define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */ + +#define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */ +#define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */ + +#define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */ +#define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */ + +#define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */ +#define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */ + +#define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */ +#define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */ + +#define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */ +#define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */ + +#define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */ +#define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */ + +#define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */ +#define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */ + +#define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */ +#define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */ + +#define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */ +#define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */ + +#define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */ +#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */ + +#define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */ +#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */ + +#define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */ +#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */ + +#define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */ +#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */ + +#define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */ +#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */ + +#define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */ +#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */ + +#define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */ +#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */ + +#define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */ +#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */ + +#define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */ +#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */ + +#define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */ +#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */ + +#define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */ +#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */ + +#define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */ +#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */ + +#define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */ +#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */ + +#define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */ +#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */ + +#define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */ +#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */ + +#define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */ +#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */ + +#define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */ +#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */ + +#define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */ +#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */ + +#define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */ +#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */ + +#define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */ +#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */ + +#define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */ +#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */ + +#define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */ +#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */ + +#define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */ +#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */ + +#define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */ +#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */ + +#define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */ +#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */ + +#define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */ +#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */ + +#define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */ +#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */ + +#define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */ +#define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */ + +#define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */ +#define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */ + +#define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */ +#define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */ + +#define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */ +#define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */ + +#define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */ +#define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */ + +#define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */ +#define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */ + +#define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */ +#define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */ + +#define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */ +#define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */ + +#define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */ +#define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */ + +#define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */ +#define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */ + +#define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */ +#define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */ + +#define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */ +#define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */ + +#define EADC_PWRM_PWUPRDY_Pos (0) /*!< EADC_T::PWRM: PWUPRDY Position */ +#define EADC_PWRM_PWUPRDY_Msk (0x1ul << EADC_PWRM_PWUPRDY_Pos) /*!< EADC_T::PWRM: PWUPRDY Mask */ + +#define EADC_PWRM_PWUCALEN_Pos (1) /*!< EADC_T::PWRM: PWUCALEN Position */ +#define EADC_PWRM_PWUCALEN_Msk (0x1ul << EADC_PWRM_PWUCALEN_Pos) /*!< EADC_T::PWRM: PWUCALEN Mask */ + +#define EADC_PWRM_PWDMOD_Pos (2) /*!< EADC_T::PWRM: PWDMOD Position */ +#define EADC_PWRM_PWDMOD_Msk (0x3ul << EADC_PWRM_PWDMOD_Pos) /*!< EADC_T::PWRM: PWDMOD Mask */ + +#define EADC_PWRM_LDOSUT_Pos (8) /*!< EADC_T::PWRM: LDOSUT Position */ +#define EADC_PWRM_LDOSUT_Msk (0xffful << EADC_PWRM_LDOSUT_Pos) /*!< EADC_T::PWRM: LDOSUT Mask */ + +#define EADC_CALCTL_CALSTART_Pos (1) /*!< EADC_T::CALCTL: CALSTART Position */ +#define EADC_CALCTL_CALSTART_Msk (0x1ul << EADC_CALCTL_CALSTART_Pos) /*!< EADC_T::CALCTL: CALSTART Mask */ + +#define EADC_CALCTL_CALDONE_Pos (2) /*!< EADC_T::CALCTL: CALDONE Position */ +#define EADC_CALCTL_CALDONE_Msk (0x1ul << EADC_CALCTL_CALDONE_Pos) /*!< EADC_T::CALCTL: CALDONE Mask */ + +#define EADC_CALCTL_CALSEL_Pos (3) /*!< EADC_T::CALCTL: CALSEL Position */ +#define EADC_CALCTL_CALSEL_Msk (0x1ul << EADC_CALCTL_CALSEL_Pos) /*!< EADC_T::CALCTL: CALSEL Mask */ + +#define EADC_CALDWRD_CALWORD_Pos (0) /*!< EADC_T::CALDWRD: CALWORD Position */ +#define EADC_CALDWRD_CALWORD_Msk (0x7ful << EADC_CALDWRD_CALWORD_Pos) /*!< EADC_T::CALDWRD: CALWORD Mask */ + +#define EADC_PDMACTL_PDMATEN_Pos (0) /*!< EADC_T::PDMACTL: PDMATEN Position */ +#define EADC_PDMACTL_PDMATEN_Msk (0x7fffful << EADC_PDMACTL_PDMATEN_Pos) /*!< EADC_T::PDMACTL: PDMATEN Mask */ + + +/**@}*/ /* EADC_CONST */ +/**@}*/ /* end of EADC register group */ +/**@}*/ /* end of REGISTER group */ + + + +#endif /* __EADC_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ebi_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ebi_reg.h new file mode 100644 index 0000000000..a407ec2260 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ebi_reg.h @@ -0,0 +1,163 @@ +/**************************************************************************//** + * @file ebi_reg.h + * @version V1.00 + * @brief EBI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EBI_REG_H__ +#define __EBI_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- External Bus Interface Controller -------------------------*/ +/** + @addtogroup EBI External Bus Interface Controller(EBI) + Memory Mapped Structure for EBI Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var EBI_T::CTL0 + * Offset: 0x00 External Bus Interface Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |EBI Enable Bit + * | | |This bit is the functional enable bit for EBI. + * | | |0 = EBI function Disabled. + * | | |1 = EBI function Enabled. + * |[1] |DW16 |EBI Data Width 16-bit Select + * | | |This bit defines if the EBI data width is 8-bit or 16-bit. + * | | |0 = EBI data width is 8-bit. + * | | |1 = EBI data width is 16-bit. + * |[2] |CSPOLINV |Chip Select Pin Polar Inverse + * | | |This bit defines the active level of EBI chip select pin (EBI_nCS). + * | | |0 = Chip select pin (EBI_nCS) is active low. + * | | |1 = Chip select pin (EBI_nCS) is active high. + * |[3] |ADSEPEN |EBI Address/Data Bus Separating Mode Enable Bit + * | | |0 = Address/Data Bus Separating Mode Disabled. + * | | |1 = Address/Data Bus Separating Mode Enabled. + * |[4] |CACCESS |Continuous Data Access Mode + * | | |When continuous access mode enabled, the tASU, tALE and tLHD cycles are bypass for continuous data transfer request. + * | | |0 = Continuous data access mode Disabled. + * | | |1 = Continuous data access mode Enabled. + * |[10:8] |MCLKDIV |External Output Clock Divider + * | | |The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow: + * | | |000 = HCLK/1. + * | | |001 = HCLK/2. + * | | |010 = HCLK/4. + * | | |011 = HCLK/8. + * | | |100 = HCLK/16. + * | | |101 = HCLK/32. + * | | |110 = HCLK/64. + * | | |111 = HCLK/128. + * |[18:16] |TALE |Extend Time of ALE + * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. + * | | |tALE = (TALE+1)*EBI_MCLK. + * | | |Note: This field only available in EBI_CTL0 register + * |[24] |WBUFEN |EBI Write Buffer Enable Bit + * | | |0 = EBI write buffer Disabled. + * | | |1 = EBI write buffer Enabled. + * | | |Note: This bit only available in EBI_CTL0 register + * @var EBI_T::TCTL0 + * Offset: 0x04 External Bus Interface Timing Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:3] |TACC |EBI Data Access Time + * | | |TACC define data access time (tACC). + * | | |tACC = (TACC+1) * EBI_MCLK. + * |[10:8] |TAHD |EBI Data Access Hold Time + * | | |TAHD define data access hold time (tAHD). + * | | |tAHD = (TAHD+1) * EBI_MCLK. + * |[15:12] |W2X |Idle Cycle After Write + * | | |This field defines the number of W2X idle cycle. + * | | |W2X idle cycle = (W2X * EBI_MCLK). + * | | |When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state. + * |[22] |RAHDOFF |Access Hold Time Disable Control When Read + * | | |0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled. + * |[23] |WAHDOFF |Access Hold Time Disable Control When Write + * | | |0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled. + * | | |1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled. + * |[27:24] |R2R |Idle Cycle Between Read-to-read + * | | |This field defines the number of R2R idle cycle. + * | | |R2R idle cycle = (R2R * EBI_MCLK). + * | | |When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state. + */ + __IO uint32_t CTL0; /*!< [0x0000] External Bus Interface Bank0 Control Register */ + __IO uint32_t TCTL0; /*!< [0x0004] External Bus Interface Bank0 Timing Control Register */ + __I uint32_t RESERVE0[2]; + __IO uint32_t CTL1; /*!< [0x0010] External Bus Interface Bank1 Control Register */ + __IO uint32_t TCTL1; /*!< [0x0014] External Bus Interface Bank1 Timing Control Register */ + __I uint32_t RESERVE1[2]; + __IO uint32_t CTL2; /*!< [0x0020] External Bus Interface Bank2 Control Register */ + __IO uint32_t TCTL2; /*!< [0x0024] External Bus Interface Bank2 Timing Control Register */ + +} EBI_T; + +/** + @addtogroup EBI_CONST EBI Bit Field Definition + Constant Definitions for EBI Controller + @{ +*/ + +#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */ +#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL0: EN Mask */ + +#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */ +#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */ + +#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */ +#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */ + +#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */ +#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */ + +#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */ +#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */ + +#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */ +#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */ + +#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */ +#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */ + +#define EBI_CTL_WBUFEN_Pos (24) /*!< EBI_T::CTL0: WBUFEN Position */ +#define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) /*!< EBI_T::CTL0: WBUFEN Mask */ + +#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */ +#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */ + +#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */ +#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */ + +#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */ +#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */ + +#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */ +#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */ + +#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */ +#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */ + +#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */ +#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */ + +/**@}*/ /* EBI_CONST */ +/**@}*/ /* end of EBI register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __EBI_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ecap_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ecap_reg.h new file mode 100644 index 0000000000..ffc4b95007 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ecap_reg.h @@ -0,0 +1,388 @@ +/**************************************************************************//** + * @file ecap_reg.h + * @version V1.00 + * @brief ECAP register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __ECAP_REG_H__ +#define __ECAP_REG_H__ + +/** + @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Enhanced Input Capture Timer -------------------------*/ +/** + @addtogroup ECAP Enhanced Input Capture Timer(ECAP) + Memory Mapped Structure for ECAP Controller + @{ +*/ + +typedef struct +{ + + /** + * @var ECAP_T::CNT + * Offset: 0x00 Input Capture Counter (24-bit up counter) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Input Capture Timer/Counter + * | | |The input Capture Timer/Counter is a 24-bit up-counting counter + * | | |The clock source for the counter is from the clock divider + * @var ECAP_T::HLD0 + * Offset: 0x04 Input Capture Hold Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD1 + * Offset: 0x08 Input Capture Hold Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::HLD2 + * Offset: 0x0C Input Capture Hold Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |HOLD |Input Capture Counter Hold Register + * | | |When an active input capture channel detects a valid edge signal change, the ECAPCNT value is latched into the corresponding holding register + * | | |Each input channel has its own holding register named by ECAP_HLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively. + * @var ECAP_T::CNTCMP + * Offset: 0x10 Input Capture Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNTCMP |Input Capture Counter Compare Register + * | | |If the compare function is enabled (CMPEN = 1), this register (ECAP_CNTCMP) is used to compare with the capture counter (ECAP_CNT). + * | | |If the reload control is enabled (RLDEN[n] = 1, n=0~3), an overflow event or capture events will trigger the hardware to load the value of this register (ECAP_CNTCMP) into ECAP_CNT. + * @var ECAP_T::CTL0 + * Offset: 0x14 Input Capture Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection + * | | |To determine the sampling frequency of the Noise Filter clock + * | | |000 = CAP_CLK. + * | | |001 = CAP_CLK/2. + * | | |010 = CAP_CLK/4. + * | | |011 = CAP_CLK/16. + * | | |100 = CAP_CLK/32. + * | | |101 = CAP_CLK/64. + * |[3] |CAPNFDIS |Input Capture Noise Filter Disable Control + * | | |0 = Noise filter of Input Capture Enabled. + * | | |1 = Noise filter of Input Capture Disabled (Bypass). + * |[4] |IC0EN |Port Pin IC0 Input to Input Capture Unit Enable Control + * | | |0 = IC0 input to Input Capture Unit Disabled. + * | | |1 = IC0 input to Input Capture Unit Enabled. + * |[5] |IC1EN |Port Pin IC1 Input to Input Capture Unit Enable Control + * | | |0 = IC1 input to Input Capture Unit Disabled. + * | | |1 = IC1 input to Input Capture Unit Enabled. + * |[6] |IC2EN |Port Pin IC2 Input to Input Capture Unit Enable Control + * | | |0 = IC2 input to Input Capture Unit Disabled. + * | | |1 = IC2 input to Input Capture Unit Enabled. + * |[9:8] |CAPSEL0 |CAP0 Input Source Selection + * | | |00 = CAP0 input is from port pin ICAP0. + * | | |01 = Reserved. + * | | |10 = CAP0 input is from signal CHA of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[11:10] |CAPSEL1 |CAP1 Input Source Selection + * | | |00 = CAP1 input is from port pin ICAP1. + * | | |01 = Reserved. + * | | |10 = CAP1 input is from signal CHB of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[13:12] |CAPSEL2 |CAP2 Input Source Selection + * | | |00 = CAP2 input is from port pin ICAP2. + * | | |01 = Reserved. + * | | |10 = CAP2 input is from signal CHX of QEI controller unit n. + * | | |11 = Reserved. + * | | |Note: Input capture unit n matches QEIn, where n = 0~1. + * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control + * | | |0 = The flag CAPTF0 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF0 can trigger Input Capture interrupt Enabled. + * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control + * | | |0 = The flag CAPTF1 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF1 can trigger Input Capture interrupt Enabled. + * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control + * | | |0 = The flag CAPTF2 can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPTF2 can trigger Input Capture interrupt Enabled. + * |[20] |OVIEN |CAPOVF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPOVF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPOVF can trigger Input Capture interrupt Enabled. + * |[21] |CMPIEN |CAPCMPF Trigger Input Capture Interrupt Enable Control + * | | |0 = The flag CAPCMPF can trigger Input Capture interrupt Disabled. + * | | |1 = The flag CAPCMPF can trigger Input Capture interrupt Enabled. + * |[24] |CNTEN |Input Capture Counter Start Counting Control + * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with the clock from the . + * | | |0 = ECAP_CNT stop counting. + * | | |1 = ECAP_CNT starts up-counting. + * |[25] |CMPCLREN |Input Capture Counter Cleared by Compare-match Control + * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAPCMPF = 1) occurs. + * | | |0 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Compare-match event (CAPCMPF) can clear capture counter (ECAP_CNT) Enabled. + * |[28] |CMPEN |Compare Function Enable Control + * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CAPCMPF will be set. + * | | |0 = The compare function Disabled. + * | | |1 = The compare function Enabled. + * |[29] |CAPEN |Input Capture Timer/Counter Enable Control + * | | |0 = Input Capture function Disabled. + * | | |1 = Input Capture function Enabled. + * @var ECAP_T::CTL1 + * Offset: 0x18 Input Capture Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |EDGESEL0 |Channel 0 Captured Edge Selection + * | | |Input capture0 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[3:2] |EDGESEL1 |Channel 1 Captured Edge Selection + * | | |Input capture1 can detect falling edge change only, rising edge change only or both edge change + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[5:4] |EDGESEL2 |Channel 2 Captured Edge Selection + * | | |Input capture2 can detect falling edge change only, rising edge change only or both edge changes + * | | |00 = Detect rising edge only. + * | | |01 = Detect falling edge only. + * | | |1x = Detect both rising and falling edge. + * |[8] |CAP0RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE0 Enable Bit + * | | |0 = The reload triggered by Event CAPTE0 Disabled. + * | | |1 = The reload triggered by Event CAPTE0 Enabled. + * |[9] |CAP1RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE1 Enable Bit + * | | |0 = The reload triggered by Event CAPTE1 Disabled. + * | | |1 = The reload triggered by Event CAPTE1 Enabled. + * |[10] |CAP2RLDEN |Capture Counteru2019s Reload Function Triggered by Event CAPTE2 Enable Bit + * | | |0 = The reload triggered by Event CAPTE2 Disabled. + * | | |1 = The reload triggered by Event CAPTE2 Enabled. + * |[11] |OVRLDEN |Capture Counteru2019s Reload Function Triggered by Overflow Enable Bit + * | | |0 = The reload triggered by CAPOV Disabled. + * | | |1 = The reload triggered by CAPOV Enabled. + * |[14:12] |CLKSEL |Capture Timer Clock Divide Selection + * | | |The capture timer clock has a pre-divider with eight divided options controlled by CLKSEL[2:0]. + * | | |000 = CAP_CLK/1. + * | | |001 = CAP_CLK/4. + * | | |010 = CAP_CLK/16. + * | | |011 = CAP_CLK/32. + * | | |100 = CAP_CLK/64. + * | | |101 = CAP_CLK/96. + * | | |110 = CAP_CLK/112. + * | | |111 = CAP_CLK/128. + * |[17:16] |CNTSRCSEL |Capture Timer/Counter Clock Source Selection + * | | |Select the capture timer/counter clock source. + * | | |00 = CAP_CLK (default). + * | | |01 = CAP0. + * | | |10 = CAP1. + * | | |11 = CAP2. + * |[20] |CAP0CLREN |Capture Counter Cleared by Capture Event0 Control + * | | |0 = Event CAPTE0 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE0 can clear capture counter (ECAP_CNT) Enabled. + * |[21] |CAP1CLREN |Capture Counter Cleared by Capture Event1 Control + * | | |0 = Event CAPTE1 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE1 can clear capture counter (ECAP_CNT) Enabled. + * |[22] |CAP2CLREN |Capture Counter Cleared by Capture Event2 Control + * | | |0 = Event CAPTE2 can clear capture counter (ECAP_CNT) Disabled. + * | | |1 = Event CAPTE2 can clear capture counter (ECAP_CNT) Enabled. + * @var ECAP_T::STATUS + * Offset: 0x1C Input Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPTF0 |Input Capture Channel 0 Triggered Flag + * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPTF0 to high. + * | | |0 = No valid edge change has been detected at CAP0 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP0 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[1] |CAPTF1 |Input Capture Channel 1 Triggered Flag + * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPTF1 to high. + * | | |0 = No valid edge change has been detected at CAP1 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP1 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[2] |CAPTF2 |Input Capture Channel 2 Triggered Flag + * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPTF2 to high. + * | | |0 = No valid edge change has been detected at CAP2 input since last clear. + * | | |1 = At least a valid edge change has been detected at CAP2 input since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[4] |CAPCMPF |Input Capture Compare-match Flag + * | | |If the input capture compare function is enabled, the flag is set by hardware when capture counter (ECAP_CNT) up counts and reaches the ECAP_CNTCMP value. + * | | |0 = ECAP_CNT has not matched ECAP_CNTCMP value since last clear. + * | | |1 = ECAP_CNT has matched ECAP_CNTCMP value at least once since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[5] |CAPOVF |Input Capture Counter Overflow Flag + * | | |Flag is set by hardware when counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero. + * | | |0 = No overflow event has occurred since last clear. + * | | |1 = Overflow event(s) has/have occurred since last clear. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[6] |CAP0 |Value of Input Channel 0, CAP0 (Read Only) + * | | |Reflecting the value of input channel 0, CAP0 + * | | |(The bit is read only and write is ignored) + * |[7] |CAP1 |Value of Input Channel 1, CAP1 (Read Only) + * | | |Reflecting the value of input channel 1, CAP1 + * | | |(The bit is read only and write is ignored) + * |[8] |CAP2 |Value of Input Channel 2, CAP2 (Read Only) + * | | |Reflecting the value of input channel 2, CAP2. + * | | |(The bit is read only and write is ignored) + */ + __IO uint32_t CNT; /*!< [0x0000] Input Capture Counter */ + __IO uint32_t HLD0; /*!< [0x0004] Input Capture Hold Register 0 */ + __IO uint32_t HLD1; /*!< [0x0008] Input Capture Hold Register 1 */ + __IO uint32_t HLD2; /*!< [0x000c] Input Capture Hold Register 2 */ + __IO uint32_t CNTCMP; /*!< [0x0010] Input Capture Compare Register */ + __IO uint32_t CTL0; /*!< [0x0014] Input Capture Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0018] Input Capture Control Register 1 */ + __IO uint32_t STATUS; /*!< [0x001c] Input Capture Status Register */ + +} ECAP_T; + +/** + @addtogroup ECAP_CONST ECAP Bit Field Definition + Constant Definitions for ECAP Controller + @{ +*/ + +#define ECAP_CNT_CNT_Pos (0) /*!< ECAP_T::CNT: CNT Position */ +#define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) /*!< ECAP_T::CNT: CNT Mask */ + +#define ECAP_HLD0_HOLD_Pos (0) /*!< ECAP_T::HLD0: HOLD Position */ +#define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) /*!< ECAP_T::HLD0: HOLD Mask */ + +#define ECAP_HLD1_HOLD_Pos (0) /*!< ECAP_T::HLD1: HOLD Position */ +#define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) /*!< ECAP_T::HLD1: HOLD Mask */ + +#define ECAP_HLD2_HOLD_Pos (0) /*!< ECAP_T::HLD2: HOLD Position */ +#define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) /*!< ECAP_T::HLD2: HOLD Mask */ + +#define ECAP_CNTCMP_CNTCMP_Pos (0) /*!< ECAP_T::CNTCMP: CNTCMP Position */ +#define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) /*!< ECAP_T::CNTCMP: CNTCMP Mask */ + +#define ECAP_CTL0_NFCLKSEL_Pos (0) /*!< ECAP_T::CTL0: NFCLKSEL Position */ +#define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) /*!< ECAP_T::CTL0: NFCLKSEL Mask */ + +#define ECAP_CTL0_CAPNFDIS_Pos (3) /*!< ECAP_T::CTL0: CAPNFDIS Position */ +#define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) /*!< ECAP_T::CTL0: CAPNFDIS Mask */ + +#define ECAP_CTL0_IC0EN_Pos (4) /*!< ECAP_T::CTL0: IC0EN Position */ +#define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) /*!< ECAP_T::CTL0: IC0EN Mask */ + +#define ECAP_CTL0_IC1EN_Pos (5) /*!< ECAP_T::CTL0: IC1EN Position */ +#define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) /*!< ECAP_T::CTL0: IC1EN Mask */ + +#define ECAP_CTL0_IC2EN_Pos (6) /*!< ECAP_T::CTL0: IC2EN Position */ +#define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) /*!< ECAP_T::CTL0: IC2EN Mask */ + +#define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP_T::CTL0: CAPSEL0 Position */ +#define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP_T::CTL0: CAPSEL0 Mask */ + +#define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP_T::CTL0: CAPSEL1 Position */ +#define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP_T::CTL0: CAPSEL1 Mask */ + +#define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP_T::CTL0: CAPSEL2 Position */ +#define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP_T::CTL0: CAPSEL2 Mask */ + +#define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP_T::CTL0: CAPIEN0 Position */ +#define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP_T::CTL0: CAPIEN0 Mask */ + +#define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP_T::CTL0: CAPIEN1 Position */ +#define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP_T::CTL0: CAPIEN1 Mask */ + +#define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP_T::CTL0: CAPIEN2 Position */ +#define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP_T::CTL0: CAPIEN2 Mask */ + +#define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP_T::CTL0: OVIEN Position */ +#define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP_T::CTL0: OVIEN Mask */ + +#define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP_T::CTL0: CMPIEN Position */ +#define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP_T::CTL0: CMPIEN Mask */ + +#define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP_T::CTL0: CNTEN Position */ +#define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP_T::CTL0: CNTEN Mask */ + +#define ECAP_CTL0_CMPCLREN_Pos (25) /*!< ECAP_T::CTL0: CMPCLREN Position */ +#define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) /*!< ECAP_T::CTL0: CMPCLREN Mask */ + +#define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP_T::CTL0: CMPEN Position */ +#define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP_T::CTL0: CMPEN Mask */ + +#define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP_T::CTL0: CAPEN Position */ +#define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP_T::CTL0: CAPEN Mask */ + +#define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP_T::CTL1: EDGESEL0 Position */ +#define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP_T::CTL1: EDGESEL0 Mask */ + +#define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP_T::CTL1: EDGESEL1 Position */ +#define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP_T::CTL1: EDGESEL1 Mask */ + +#define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP_T::CTL1: EDGESEL2 Position */ +#define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP_T::CTL1: EDGESEL2 Mask */ + +#define ECAP_CTL1_CAP0RLDEN_Pos (8) /*!< ECAP_T::CTL1: CAP0RLDEN Position */ +#define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) /*!< ECAP_T::CTL1: CAP0RLDEN Mask */ + +#define ECAP_CTL1_CAP1RLDEN_Pos (9) /*!< ECAP_T::CTL1: CAP1RLDEN Position */ +#define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) /*!< ECAP_T::CTL1: CAP1RLDEN Mask */ + +#define ECAP_CTL1_CAP2RLDEN_Pos (10) /*!< ECAP_T::CTL1: CAP2RLDEN Position */ +#define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) /*!< ECAP_T::CTL1: CAP2RLDEN Mask */ + +#define ECAP_CTL1_OVRLDEN_Pos (11) /*!< ECAP_T::CTL1: OVRLDEN Position */ +#define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) /*!< ECAP_T::CTL1: OVRLDEN Mask */ + +#define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP_T::CTL1: CLKSEL Position */ +#define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP_T::CTL1: CLKSEL Mask */ + +#define ECAP_CTL1_CNTSRCSEL_Pos (16) /*!< ECAP_T::CTL1: CNTSRCSEL Position */ +#define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) /*!< ECAP_T::CTL1: CNTSRCSEL Mask */ + +#define ECAP_CTL1_CAP0CLREN_Pos (20) /*!< ECAP_T::CTL1: CAP0CLREN Position */ +#define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) /*!< ECAP_T::CTL1: CAP0CLREN Mask */ + +#define ECAP_CTL1_CAP1CLREN_Pos (21) /*!< ECAP_T::CTL1: CAP1CLREN Position */ +#define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) /*!< ECAP_T::CTL1: CAP1CLREN Mask */ + +#define ECAP_CTL1_CAP2CLREN_Pos (22) /*!< ECAP_T::CTL1: CAP2CLREN Position */ +#define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) /*!< ECAP_T::CTL1: CAP2CLREN Mask */ + +#define ECAP_STATUS_CAPTF0_Pos (0) /*!< ECAP_T::STATUS: CAPTF0 Position */ +#define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) /*!< ECAP_T::STATUS: CAPTF0 Mask */ + +#define ECAP_STATUS_CAPTF1_Pos (1) /*!< ECAP_T::STATUS: CAPTF1 Position */ +#define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) /*!< ECAP_T::STATUS: CAPTF1 Mask */ + +#define ECAP_STATUS_CAPTF2_Pos (2) /*!< ECAP_T::STATUS: CAPTF2 Position */ +#define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) /*!< ECAP_T::STATUS: CAPTF2 Mask */ + +#define ECAP_STATUS_CAPCMPF_Pos (4) /*!< ECAP_T::STATUS: CAPCMPF Position */ +#define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) /*!< ECAP_T::STATUS: CAPCMPF Mask */ + +#define ECAP_STATUS_CAPOVF_Pos (5) /*!< ECAP_T::STATUS: CAPOVF Position */ +#define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) /*!< ECAP_T::STATUS: CAPOVF Mask */ + +#define ECAP_STATUS_CAP0_Pos (8) /*!< ECAP_T::STATUS: CAP0 Position */ +#define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) /*!< ECAP_T::STATUS: CAP0 Mask */ + +#define ECAP_STATUS_CAP1_Pos (9) /*!< ECAP_T::STATUS: CAP1 Position */ +#define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) /*!< ECAP_T::STATUS: CAP1 Mask */ + +#define ECAP_STATUS_CAP2_Pos (10) /*!< ECAP_T::STATUS: CAP2 Position */ +#define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) /*!< ECAP_T::STATUS: CAP2 Mask */ + +/**@}*/ /* ECAP_CONST */ +/**@}*/ /* end of ECAP register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __ECAP_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/epwm_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/epwm_reg.h new file mode 100644 index 0000000000..27b26d5d21 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/epwm_reg.h @@ -0,0 +1,4001 @@ +/**************************************************************************//** + * @file epwm_reg.h + * @version V1.00 + * @brief EPWM register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EPWM_REG_H__ +#define __EPWM_REG_H__ + +/** + @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Enhanced Pulse Width Modulation Controller -------------------------*/ +/** + @addtogroup EPWM Enhanced Pulse Width Modulation Controller(EPWM) + Memory Mapped Structure for EPWM Controller + @{ +*/ + +typedef struct +{ + /** + * @var ECAPDAT_T::RCAPDAT + * Offset: 0x20C EPWM Rising Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only) + * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. + * @var ECAPDAT_T::FCAPDAT + * Offset: 0x210 EPWM Falling Capture Data Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only) + * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. + */ + __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */ + __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */ +} ECAPDAT_T; + +typedef struct +{ + + + /** + * @var EPWM_T::CTL0 + * Offset: 0x00 EPWM Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTRLD0 |Center Re-load + * | | |In up-down counter type, PERIOD0 register will load to PBUF0 register at the end point of each period. + * | | |CMPDAT0 register will load to CMPBUF0 register at the center point of a period. + * |[1] |CTRLD1 |Center Re-load + * | | |In up-down counter type, PERIOD1 register will load to PBUF1 register at the end point of each period. + * | | |CMPDAT1 register will load to CMPBUF1 register at the center point of a period. + * |[2] |CTRLD2 |Center Re-load + * | | |In up-down counter type, PERIOD2 register will load to PBUF2 register at the end point of each period. + * | | |CMPDAT2 register will load to CMPBUF2 register at the center point of a period. + * |[3] |CTRLD3 |Center Re-load + * | | |In up-down counter type, PERIOD3 register will load to PBUF3 register at the end point of each period. + * | | |CMPDAT3 register will load to CMPBUF3 register at the center point of a period. + * |[4] |CTRLD4 |Center Re-load + * | | |In up-down counter type, PERIOD4 register will load to PBUF4 register at the end point of each period. + * | | |CMPDAT4 register will load to CMPBUF4 register at the center point of a period. + * |[5] |CTRLD5 |Center Re-load + * | | |In up-down counter type, PERIOD5 register will load to PBUF5 register at the end point of each period. + * | | |CMPDAT5 register will load to CMPBUF5 register at the center point of a period. + * |[8] |WINLDEN0 |Window Load Enable Bits + * | | |0 = PERIOD0 register will load to PBUF0 register at the end point of each period. + * | | |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit. + * | | |1 = PERIOD0 register will load to PBUF0 and CMPDAT0 registers will load to CMPBUF0 register at the end point of each period when valid reload window is set. + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. + * |[9] |WINLDEN1 |Window Load Enable Bits + * | | |0 = PERIOD1 register will load to PBUF1 register at the end point of each period. + * | | |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit. + * | | |1 = PERIOD1 register will load to PBUF1 and CMPDAT1 registers will load to CMPBUF1 register at the end point of each period when valid reload window is set. + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. + * |[10] |WINLDEN2 |Window Load Enable Bits + * | | |0 = PERIOD2 register will load to PBUF2 register at the end point of each period. + * | | |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit. + * | | |1 = PERIOD2 register will load to PBUF2 and CMPDAT2 registers will load to CMPBUF2 register at the end point of each period when valid reload window is set. + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. + * |[11] |WINLDEN3 |Window Load Enable Bits + * | | |0 = PERIOD3 register will load to PBUF3 register at the end point of each period. + * | | |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit. + * | | |1 = PERIOD3 register will load to PBUF3 and CMPDAT3 registers will load to CMPBUF3 register at the end point of each period when valid reload window is set. + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. + * |[12] |WINLDEN4 |Window Load Enable Bits + * | | |0 = PERIOD4 register will load to PBUF4 register at the end point of each period. + * | | |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit. + * | | |1 = PERIOD4 register will load to PBUF4 and CMPDAT4 registers will load to CMPBUF4 register at the end point of each period when valid reload window is set. + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. + * |[13] |WINLDEN5 |Window Load Enable Bits + * | | |0 = PERIOD5 register will load to PBUF5 register at the end point of each period. + * | | |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit. + * | | |1 = PERIOD5 register will load to PBUF5 and CMPDAT5 registers will load to CMPBUF5 register at the end point of each period when valid reload window is set. + * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. + * |[16] |IMMLDEN0 |Immediately Load Enable Bits + * | | |0 = PERIOD0 register will load to PBUF0 register at the end point of each period. + * | | |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit. + * | | |1 = PERIOD0/CMPDAT0 registers will load to PBUF0 and CMPBUF0 register immediately when software update PERIOD0/CMPDAT0 register. + * | | |Note: If IMMLDEN0 bit is enabled, WINLDEN0 bit and CTRLD0 bits will be invalid. + * |[17] |IMMLDEN1 |Immediately Load Enable Bits + * | | |0 = PERIOD1 register will load to PBUF1 register at the end point of each period. + * | | |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit. + * | | |1 = PERIOD1/CMPDAT1 registers will load to PBUF1 and CMPBUF1 register immediately when software update PERIOD1/CMPDAT1 register. + * | | |Note: If IMMLDEN1 bit is enabled, WINLDEN1 bit and CTRLD1 bits will be invalid. + * |[18] |IMMLDEN2 |Immediately Load Enable Bits + * | | |0 = PERIOD2 register will load to PBUF2 register at the end point of each period. + * | | |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit. + * | | |1 = PERIOD2/CMPDAT2 registers will load to PBUF2 and CMPBUF2 register immediately when software update PERIOD2/CMPDAT2 register. + * | | |Note: If IMMLDEN2 bit is enabled, WINLDEN2 bit and CTRLD2 bits will be invalid. + * |[19] |IMMLDEN3 |Immediately Load Enable Bits + * | | |0 = PERIOD3 register will load to PBUF3 register at the end point of each period. + * | | |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit. + * | | |1 = PERIOD3/CMPDAT3 registers will load to PBUF3 and CMPBUF3 register immediately when software update PERIOD3/CMPDAT3 register. + * | | |Note: If IMMLDEN3 bit is enabled, WINLDEN3 bit and CTRLD3 bits will be invalid. + * |[20] |IMMLDEN4 |Immediately Load Enable Bits + * | | |0 = PERIOD4 register will load to PBUF4 register at the end point of each period. + * | | |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit. + * | | |1 = PERIOD4/CMPDAT4 registers will load to PBUF4 and CMPBUF4 register immediately when software update PERIOD4/CMPDAT4 register. + * | | |Note: If IMMLDEN4 bit is enabled, WINLDEN4 bit and CTRLD4 bits will be invalid. + * |[21] |IMMLDEN5 |Immediately Load Enable Bits + * | | |0 = PERIOD5 register will load to PBUF5 register at the end point of each period. + * | | |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit. + * | | |1 = PERIOD5/CMPDAT5 registers will load to PBUF5 and CMPBUF5 register immediately when software update PERIOD5/CMPDAT5 register. + * | | |Note: If IMMLDEN5 bit is enabled, WINLDEN5 bit and CTRLD5 bits will be invalid. + * |[24] |GROUPEN |Group Function Enable Bit + * | | |0 = The output waveform of each EPWM channel are independent. + * | | |1 = Unify the EPWMx_CH2 and EPWMx_CH4 to output the same waveform as EPWMx_CH0 and unify the EPWMx_CH3 and EPWMx_CH5 to output the same waveform as EPWMx_CH1. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt disable. + * | | |1 = ICE debug mode counter halt enable. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) + * | | |0 = ICE debug mode acknowledgement effects EPWM output. + * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgement disabled. + * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::CTL1 + * Offset: 0x04 EPWM Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type + * | | |00 = Up counter type (supports in capture mode). + * | | |01 = Down count type (supports in capture mode). + * | | |10 = Up-down counter type. + * | | |11 = Reserved. + * |[16] |CNTMODE0 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[17] |CNTMODE1 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[18] |CNTMODE2 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[19] |CNTMODE3 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[20] |CNTMODE4 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[21] |CNTMODE5 |EPWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[24] |OUTMODE0 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[25] |OUTMODE2 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * |[26] |OUTMODE4 |EPWM Output Mode + * | | |Each bit n controls the output mode of corresponding EPWM channel n. + * | | |0 = EPWM independent mode. + * | | |1 = EPWM complementary mode. + * | | |Note: When operating in group function, these bits must all set to the same mode. + * @var EPWM_T::SYNC + * Offset: 0x08 EPWM Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PHSEN0 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[1] |PHSEN2 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[2] |PHSEN4 |SYNC Phase Enable Bits + * | | |0 = EPWM counter disable to load PHS value. + * | | |1 = EPWM counter enable to load PHS value. + * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection + * | | |00 = Synchronize source from SYNC_IN or SWSYNC. + * | | |01 = Counter equal to 0. + * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. + * | | |11 = SYNC_OUT will not be generated. + * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits + * | | |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled. + * | | |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled. + * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count + * | | |The register bits control the counter number of edge detector. + * |[23] |SINPINV |SYNC Input Pin Inverse + * | | |0 = The state of pin EPWM0_SYNC_IN is passed to the negative edge detector. + * | | |1 = The inverse state of pin EPWM0_SYNC_IN is passed to the negative edge detector. + * |[24] |PHSDIR0 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[25] |PHSDIR2 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * |[26] |PHSDIR4 |EPWM Phase Direction Control + * | | |0 = Control EPWM counter count decrement after synchronizing. + * | | |1 = Control EPWM counter count increment after synchronizing. + * @var EPWM_T::SWSYNC + * Offset: 0x0C EPWM Software Control Synchronization Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SWSYNC0 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * |[1] |SWSYNC2 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * |[2] |SWSYNC4 |Software SYNC Function + * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. + * @var EPWM_T::CLKSRC + * Offset: 0x10 EPWM Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select + * | | |000 = EPWMx_CLK, x denotes 0 or 1. + * | | |001 = TIMER0 overflow. + * | | |010 = TIMER1 overflow. + * | | |011 = TIMER2 overflow. + * | | |100 = TIMER3 overflow. + * | | |Others = Reserved. + * @var EPWM_T::CLKPSC[3] + * Offset: 0x14 EPWM Clock Prescale Register 0/1, 2/3, 4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |EPWM Counter Clock Prescale + * | | |The clock of EPWM counter is decided by clock prescaler + * | | |Each EPWM pair share one EPWM counter clock prescaler + * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) + * @var EPWM_T::CNTEN + * Offset: 0x20 EPWM Counter Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN0 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[1] |CNTEN1 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[2] |CNTEN2 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[3] |CNTEN3 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[4] |CNTEN4 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * |[5] |CNTEN5 |EPWM Counter Enable Bits + * | | |0 = EPWM Counter and clock prescaler Stop Running. + * | | |1 = EPWM Counter and clock prescaler Start Running. + * @var EPWM_T::CNTCLR + * Offset: 0x24 EPWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = Clear 16-bit EPWM counter to 0000H. + * @var EPWM_T::LOAD + * Offset: 0x28 EPWM Load Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LOAD0 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDEN0(EPWM_CTL0[13:8]) = 1. + * |[1] |LOAD1 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDEN1(EPWM_CTL0[13:8]) = 1. + * |[2] |LOAD2 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDEN2(EPWM_CTL0[13:8]) = 1. + * |[3] |LOAD3 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDEN3(EPWM_CTL0[13:8]) = 1. + * |[4] |LOAD4 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDEN4(EPWM_CTL0[13:8]) = 1. + * |[5] |LOAD5 |Re-load EPWM Comparator Register (CMPDAT) Control Bit + * | | |This bit is software write, hardware clear when current EPWM period end. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set load window of window loading mode. + * | | |Read Operation: + * | | |0 = No load window is set. + * | | |1 = Load window is set. + * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. + * @var EPWM_T::PERIOD[6] + * Offset: 0x30 EPWM Period Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |EPWM Period Register + * | | |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |EPWM period time = (PERIOD+1) * EPWM_CLK period. + * | | |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |EPWM period time = 2 * PERIOD * EPWM_CLK period. + * @var EPWM_T::CMPDAT[6] + * Offset: 0x50 EPWM Comparator Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |EPWM Comparator Register + * | | |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC. + * | | |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point. + * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::DTCTL[3] + * Offset: 0x70 EPWM Dead-Time Control Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following formula: + * | | |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect) + * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled + * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. + * | | |0 = Dead-time insertion Disabled on the pin pair. + * | | |1 = Dead-time insertion Enabled on the pin pair. + * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from EPWM_CLK. + * | | |1 = Dead-time clock source from prescaler output. + * | | |Note: This register is write protected. Refer toREGWRPROT register. + * @var EPWM_T::PHS[3] + * Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PHS |EPWM Synchronous Start Phase Bits + * | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. + * @var EPWM_T::CNT[6] + * Offset: 0x90 EPWM Counter Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |EPWM Data Register (Read Only) + * | | |User can monitor CNTR to know the current value in 16-bit period counter. + * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) + * | | |0 = Counter is Down count. + * | | |1 = Counter is UP count. + * @var EPWM_T::WGCTL0 + * Offset: 0xB0 EPWM Generation Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |ZPCTL0 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[3:2] |ZPCTL1 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[5:4] |ZPCTL2 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[7:6] |ZPCTL3 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[9:8] |ZPCTL4 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[11:10] |ZPCTL5 |EPWM Zero Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM zero point output Low. + * | | |10 = EPWM zero point output High. + * | | |11 = EPWM zero point output Toggle. + * | | |EPWM can control output level when EPWM counter count to zero. + * |[17:16] |PRDPCTL0 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIOD0+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[19:18] |PRDPCTL1 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIOD1+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[21:20] |PRDPCTL2 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIOD2+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[23:22] |PRDPCTL3 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIOD3+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[25:24] |PRDPCTL4 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIOD4+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * |[27:26] |PRDPCTL5 |EPWM Period (Center) Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM period (center) point output Low. + * | | |10 = EPWM period (center) point output High. + * | | |11 = EPWM period (center) point output Toggle. + * | | |EPWM can control output level when EPWM counter count to (PERIOD5+1). + * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. + * @var EPWM_T::WGCTL1 + * Offset: 0xB4 EPWM Generation Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare up point output Low. + * | | |10 = EPWM compare up point output High. + * | | |11 = EPWM compare up point output Toggle. + * | | |EPWM can control output level when EPWM counter up count to CMPDAT. + * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. + * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control + * | | |00 = Do nothing. + * | | |01 = EPWM compare down point output Low. + * | | |10 = EPWM compare down point output High. + * | | |11 = EPWM compare down point output Toggle. + * | | |EPWM can control output level when EPWM counter down count to CMPDAT. + * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. + * @var EPWM_T::MSKEN + * Offset: 0xB8 EPWM Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled. + * | | |The corresponding EPWM channel 0 will output MSKDAT0 (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDAT0 data. + * |[1] |MSKEN1 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled. + * | | |The corresponding EPWM channel 1 will output MSKDAT1 (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDAT1 data. + * |[2] |MSKEN2 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled. + * | | |The corresponding EPWM channel 2 will output MSKDAT2 (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDAT2 data. + * |[3] |MSKEN3 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled. + * | | |The corresponding EPWM channel 3 will output MSKDAT3 (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDAT3 data. + * |[4] |MSKEN4 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled. + * | | |The corresponding EPWM channel 4 will output MSKDAT4 (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDAT4 data. + * |[5] |MSKEN5 |EPWM Mask Enable Bits + * | | |The EPWM output signal will be masked when this bit is enabled. + * | | |The corresponding EPWM channel 5 will output MSKDAT5 (EPWM_MSK[5:0]) data. + * | | |0 = EPWM output signal is non-masked. + * | | |1 = EPWM output signal is masked and output MSKDAT5 data. + * @var EPWM_T::MSK + * Offset: 0xBC EPWM Mask Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWM_CH0 output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM_CH0. + * | | |1 = Output logic high to EPWM_CH0. + * |[1] |MSKDAT1 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWM_CH1 output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM_CH1. + * | | |1 = Output logic high to EPWM_CH1. + * |[2] |MSKDAT2 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWM_CH2 output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM_CH2. + * | | |1 = Output logic high to EPWM_CH2. + * |[3] |MSKDAT3 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWM_CH3 output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM_CH3. + * | | |1 = Output logic high to EPWM_CH3. + * |[4] |MSKDAT4 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWM_CH4 output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM_CH4. + * | | |1 = Output logic high to EPWM_CH4. + * |[5] |MSKDAT5 |EPWM Mask Data Bit + * | | |This data bit control the state of EPWM_CH5 output pin, if corresponding mask function is enabled. + * | | |0 = Output logic low to EPWM_CH5. + * | | |1 = Output logic high to EPWM_CH5. + * @var EPWM_T::BNF + * Offset: 0xC0 EPWM Brake Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 0 Disabled. + * | | |1 = Noise filter of EPWM Brake 0 Enabled. + * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count + * | | |The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT. + * |[7] |BRK0PINV |Brake 0 Pin Inverse + * | | |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector. + * | | |1 = The inversed state of pin EPWMx_BRAKE0 is passed to the negative edge detector. + * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit + * | | |0 = Noise filter of EPWM Brake 1 Disabled. + * | | |1 = Noise filter of EPWM Brake 1 Enabled. + * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection + * | | |000 = Filter clock = HCLK. + * | | |001 = Filter clock = HCLK/2. + * | | |010 = Filter clock = HCLK/4. + * | | |011 = Filter clock = HCLK/8. + * | | |100 = Filter clock = HCLK/16. + * | | |101 = Filter clock = HCLK/32. + * | | |110 = Filter clock = HCLK/64. + * | | |111 = Filter clock = HCLK/128. + * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count + * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. + * |[15] |BRK1PINV |Brake 1 Pin Inverse + * | | |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector. + * | | |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector. + * |[16] |BK0SRC |Brake 0 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |For EPWM1 setting: + * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0. + * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0. + * |[24] |BK1SRC |Brake 1 Pin Source Select + * | | |For EPWM0 setting: + * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |For EPWM1 setting: + * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1. + * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1. + * @var EPWM_T::FAILBRK + * Offset: 0xC4 EPWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by CSS detection Disabled. + * | | |1 = Brake Function triggered by CSS detection Enabled. + * |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by BOD Disabled. + * | | |1 = Brake Function triggered by BOD Enabled. + * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. + * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit + * | | |0 = Brake Function triggered by Core lockup detection Disabled. + * | | |1 = Brake Function triggered by Core lockup detection Enabled. + * @var EPWM_T::BRKCTL[3] + * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as edge-detect brake source Disabled. + * | | |1 = ACMP0_O as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as edge-detect brake source Disabled. + * | | |1 = ACMP1_O as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as edge-detect brake source Disabled. + * | | |1 = System Fail condition as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP0_O as level-detect brake source Disabled. + * | | |1 = ACMP0_O as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = ACMP1_O as level-detect brake source Disabled. + * | | |1 = ACMP1_O as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) + * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled. + * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System Fail condition as level-detect brake source Disabled. + * | | |1 = System Fail condition as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect even channels output. + * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM even channel output low level when EPWMx brake event happened. + * | | |11 = EPWM even channel output high level when EPWMx brake event happened. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect) + * | | |00 = EPWMx brake event will not affect odd channels output. + * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened. + * | | |10 = EPWM odd channel output low level when EPWMx brake event happened. + * | | |11 = EPWM odd channel output high level when EPWMx brake event happened. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[20] |EADCEBEN |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect) + * | | |0 = EADCRM as edge-detect brake source Disabled. + * | | |1 = EADCRM as edge-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[28] |EADCLBEN |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect) + * | | |0 = EADCRM as level-detect brake source Disabled. + * | | |1 = EADCRM as level-detect brake source Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::POLCTL + * Offset: 0xD4 EPWM Pin Polar Inverse Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |EPWM_CH0 PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM_CH0 output. + * | | |0 = EPWM_CH0 output polar inverse Disabled. + * | | |1 = EPWM_CH0 output polar inverse Enabled. + * |[1] |PINV1 |EPWM_CH1 PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM_CH1 output. + * | | |0 = EPWM_CH1 output polar inverse Disabled. + * | | |1 = EPWM_CH1 output polar inverse Enabled. + * |[2] |PINV2 |EPWM_CH2 PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM_CH2 output. + * | | |0 = EPWM_CH2 output polar inverse Disabled. + * | | |1 = EPWM_CH2 output polar inverse Enabled. + * |[3] |PINV3 |EPWM_CH3 PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM_CH3 output. + * | | |0 = EPWM_CH3 output polar inverse Disabled. + * | | |1 = EPWM_CH3 output polar inverse Enabled. + * |[4] |PINV4 |EPWM_CH4 PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM_CH4 output. + * | | |0 = EPWM_CH4 output polar inverse Disabled. + * | | |1 = EPWM_CH4 output polar inverse Enabled. + * |[5] |PINV5 |EPWM_CH5 PIN Polar Inverse Control + * | | |The register controls polarity state of EPWM_CH5 output. + * | | |0 = EPWM_CH5 output polar inverse Disabled. + * | | |1 = EPWM_CH5 output polar inverse Enabled. + * @var EPWM_T::POEN + * Offset: 0xD8 EPWM Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |EPWM_CH0 Pin Output Enable Bits + * | | |0 = EPWM_CH0 pin at tri-state. + * | | |1 = EPWM_CH0 pin in output mode. + * |[1] |POEN1 |EPWM_CH1 Pin Output Enable Bits + * | | |0 = EPWM_CH1 pin at tri-state. + * | | |1 = EPWM_CH1 pin in output mode. + * |[2] |POEN2 |EPWM_CH2 Pin Output Enable Bits + * | | |0 = EPWM_CH2 pin at tri-state. + * | | |1 = EPWM_CH2 pin in output mode. + * |[3] |POEN3 |EPWM_CH3 Pin Output Enable Bits + * | | |0 = EPWM_CH3 pin at tri-state. + * | | |1 = EPWM_CH3 pin in output mode. + * |[4] |POEN4 |EPWM_CH4 Pin Output Enable Bits + * | | |0 = EPWM_CH4 pin at tri-state. + * | | |1 = EPWM_CH4 pin in output mode. + * |[5] |POEN5 |EPWM_CH5 Pin Output Enable Bits + * | | |0 = EPWM_CH5 pin at tri-state. + * | | |1 = EPWM_CH5 pin in output mode. + * @var EPWM_T::SWBRK + * Offset: 0xDC EPWM Software Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF0 to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF2 to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF4 to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIF0 to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIF2 to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger level brake, and set BRKLIF4 to 1 in EPWM_INTSTS1 register. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::INTEN0 + * Offset: 0xE0 EPWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: Odd channels will read always 0 at complementary mode. + * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note1: When up-down counter type period point means center point. + * | | |Note2: Odd channels will read always 0 at complementary mode. + * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. + * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. + * @var EPWM_T::INTEN1 + * Offset: 0xE4 EPWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled. + * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled. + * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) + * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled. + * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * @var EPWM_T::INTSTS0 + * Offset: 0xE8 EPWM Interrupt Flag Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. + * |[8] |PIF0 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD0, software can write 1 to clear this bit to zero + * |[9] |PIF1 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD1, software can write 1 to clear this bit to zero + * |[10] |PIF2 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD2, software can write 1 to clear this bit to zero + * |[11] |PIF3 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD4, software can write 1 to clear this bit to zero + * |[12] |PIF4 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD5, software can write 1 to clear this bit to zero + * |[13] |PIF5 |EPWM Period Point Interrupt Flag + * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. + * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. + * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. + * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag + * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it. + * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. + * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. + * @var EPWM_T::INTSTS1 + * Offset: 0xEC EPWM Interrupt Flag Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel0 edge-detect brake event do not happened. + * | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel1 edge-detect brake event do not happened. + * | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel2 edge-detect brake event do not happened. + * | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel3 edge-detect brake event do not happened. + * | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel4 edge-detect brake event do not happened. + * | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel5 edge-detect brake event do not happened. + * | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel0 level-detect brake event do not happened. + * | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel1 level-detect brake event do not happened. + * | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel2 level-detect brake event do not happened. + * | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel3 level-detect brake event do not happened. + * | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel4 level-detect brake event do not happened. + * | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect) + * | | |0 = EPWM channel5 level-detect brake event do not happened. + * | | |1 = When EPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. + * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. + * |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel0 edge-detect brake state is released. + * | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear. + * |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel1 edge-detect brake state is released. + * | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear. + * |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel2 edge-detect brake state is released. + * | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear. + * |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel3 edge-detect brake state is released. + * | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear. + * |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel4 edge-detect brake state is released. + * | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear. + * |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only) + * | | |0 = EPWM channel5 edge-detect brake state is released. + * | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear. + * |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel0 level-detect brake state is released. + * | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel1 level-detect brake state is released. + * | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel2 level-detect brake state is released. + * | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel3 level-detect brake state is released. + * | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel4 level-detect brake state is released. + * | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only) + * | | |0 = EPWM channel5 level-detect brake state is released. + * | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state. + * | | |Note: This bit is read only and auto cleared by hardware + * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished + * | | |The EPWM waveform will start output from next full EPWM period. + * @var EPWM_T::DACTRGEN + * Offset: 0xF4 EPWM Trigger DAC Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits + * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. + * | | |0 = EPWM period point trigger DAC function Disabled. + * | | |1 = EPWM period point trigger DAC function Enabled. + * |[16] |CUTRGE0 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[17] |CUTRGE1 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[18] |CUTRGE2 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[19] |CUTRGE3 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[20] |CUTRGE4 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[21] |CUTRGE5 |EPWM Compare Up Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Up point trigger DAC function Disabled. + * | | |1 = EPWM Compare Up point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. + * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. + * |[24] |CDTRGE0 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[25] |CDTRGE1 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[26] |CDTRGE2 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[27] |CDTRGE3 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[28] |CDTRGE4 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * |[29] |CDTRGE5 |EPWM Compare Down Count Point Trigger DAC Enable Bits + * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. + * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. + * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. + * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. + * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. + * @var EPWM_T::EADCTS0 + * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select + * | | |0000 = EPWM_CH0 zero point. + * | | |0001 = EPWM_CH0 period point. + * | | |0010 = EPWM_CH0 zero or period point. + * | | |0011 = EPWM_CH0 up-count CMPDAT point. + * | | |0100 = EPWM_CH0 down-count CMPDAT point. + * | | |0101 = EPWM_CH1 zero point. + * | | |0110 = EPWM_CH1 period point. + * | | |0111 = EPWM_CH1 zero or period point. + * | | |1000 = EPWM_CH1 up-count CMPDAT point. + * | | |1001 = EPWM_CH1 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC enable bit + * |[11:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select + * | | |0000 = EPWM_CH0 zero point. + * | | |0001 = EPWM_CH0 period point. + * | | |0010 = EPWM_CH0 zero or period point. + * | | |0011 = EPWM_CH0 up-count CMPDAT point. + * | | |0100 = EPWM_CH0 down-count CMPDAT point. + * | | |0101 = EPWM_CH1 zero point. + * | | |0110 = EPWM_CH1 period point. + * | | |0111 = EPWM_CH1 zero or period point. + * | | |1000 = EPWM_CH1 up-count CMPDAT point. + * | | |1001 = EPWM_CH1 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC enable bit + * |[19:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select + * | | |0000 = EPWM_CH2 zero point. + * | | |0001 = EPWM_CH2 period point. + * | | |0010 = EPWM_CH2 zero or period point. + * | | |0011 = EPWM_CH2 up-count CMPDAT point. + * | | |0100 = EPWM_CH2 down-count CMPDAT point. + * | | |0101 = EPWM_CH3 zero point. + * | | |0110 = EPWM_CH3 period point. + * | | |0111 = EPWM_CH3 zero or period point. + * | | |1000 = EPWM_CH3 up-count CMPDAT point. + * | | |1001 = EPWM_CH3 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC enable bit + * |[27:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select + * | | |0000 = EPWM_CH2 zero point. + * | | |0001 = EPWM_CH2 period point. + * | | |0010 = EPWM_CH2 zero or period point. + * | | |0011 = EPWM_CH2 up-count CMPDAT point. + * | | |0100 = EPWM_CH2 down-count CMPDAT point. + * | | |0101 = EPWM_CH3 zero point. + * | | |0110 = EPWM_CH3 period point. + * | | |0111 = EPWM_CH3 zero or period point. + * | | |1000 = EPWM_CH3 up-count CMPDAT point. + * | | |1001 = EPWM_CH3 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC enable bit + * @var EPWM_T::EADCTS1 + * Offset: 0xFC EPWM Trigger EADC Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select + * | | |0000 = EPWM_CH4 zero point. + * | | |0001 = EPWM_CH4 period point. + * | | |0010 = EPWM_CH4 zero or period point. + * | | |0011 = EPWM_CH4 up-count CMPDAT point. + * | | |0100 = EPWM_CH4 down-count CMPDAT point. + * | | |0101 = EPWM_CH5 zero point. + * | | |0110 = EPWM_CH5 period point. + * | | |0111 = EPWM_CH5 zero or period point. + * | | |1000 = EPWM_CH5 up-count CMPDAT point. + * | | |1001 = EPWM_CH5 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC enable bit + * |[11:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select + * | | |0000 = EPWM_CH4 zero point. + * | | |0001 = EPWM_CH4 period point. + * | | |0010 = EPWM_CH4 zero or period point. + * | | |0011 = EPWM_CH4 up-count CMPDAT point. + * | | |0100 = EPWM_CH4 down-count CMPDAT point. + * | | |0101 = EPWM_CH5 zero point. + * | | |0110 = EPWM_CH5 period point. + * | | |0111 = EPWM_CH5 zero or period point. + * | | |1000 = EPWM_CH5 up-count CMPDAT point. + * | | |1001 = EPWM_CH5 down-count CMPDAT point. + * | | |1010 = EPWM_CH0 up-count free CMPDAT point. + * | | |1011 = EPWM_CH0 down-count free CMPDAT point. + * | | |1100 = EPWM_CH2 up-count free CMPDAT point. + * | | |1101 = EPWM_CH2 down-count free CMPDAT point. + * | | |1110 = EPWM_CH4 up-count free CMPDAT point. + * | | |1111 = EPWM_CH4 down-count free CMPDAT point. + * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC enable bit + * @var EPWM_T::FTCMPDAT[3] + * Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMP |EPWM Free Trigger Compare Register + * | | |FTCMP use to compare with even CNTR to trigger EADC + * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. + * @var EPWM_T::SSCTL + * Offset: 0x110 EPWM Synchronous Start Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits + * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). + * | | |0 = EPWM synchronous start function Disabled. + * | | |1 = EPWM synchronous start function Enabled. + * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits + * | | |00 = Synchronous start source come from EPWM0. + * | | |01 = Synchronous start source come from EPWM1. + * | | |10 = Synchronous start source come from BPWM0. + * | | |11 = Synchronous start source come from BPWM1. + * @var EPWM_T::SSTRG + * Offset: 0x114 EPWM Synchronous Start Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only) + * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time. + * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. + * @var EPWM_T::LEBCTL + * Offset: 0x118 EPWM Leading Edge Blanking Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit + * | | |0 = EPWM Leading Edge Blanking Disabled. + * | | |1 = EPWM Leading Edge Blanking Enabled. + * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled. + * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled. + * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit + * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled. + * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled. + * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type + * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting. + * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting. + * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting. + * | | |3 = Reserved. + * @var EPWM_T::LEBCNT + * Offset: 0x11C EPWM Leading Edge Blanking Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter + * | | |This counter value decides leading edge blanking window size. + * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK. + * @var EPWM_T::STATUS + * Offset: 0x120 EPWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag + * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. + * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. + * |[8] |SYNCINF0 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[9] |SYNCINF2 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[10] |SYNCINF4 |Input Synchronization Latched Flag + * | | |0 = Indicates no SYNC_IN event has occurred. + * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. + * |[16] |EADCTRGF0 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[17] |EADCTRGF1 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[18] |EADCTRGF2 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[19] |EADCTRGF3 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[20] |EADCTRGF4 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[21] |EADCTRGF5 |EADC Start of Conversion Flag + * | | |0 = Indicates no EADC start of conversion trigger event has occurred. + * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. + * |[24] |DACTRGF |DAC Start of Conversion Flag + * | | |0 = Indicates no DAC start of conversion trigger event has occurred. + * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit + * @var EPWM_T::IFA[6] + * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter + * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. + * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. + * |[24] |STPMOD |EPWM_CHn Interrupt Flag Accumulator Stop Mode Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator stop mode disable. + * | | |1 = EPWM_CHn interrupt flag accumulator stop mode enable. + * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select + * | | |00 = CNT equal to Zero in channel n. + * | | |01 = CNT equal to PERIOD in channel n. + * | | |10 = CNT equal to CMPU in channel n. + * | | |11 = CNT equal to CMPD in channel n. + * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits + * | | |0 = EPWM_CHn interrupt flag accumulator disable. + * | | |1 = EPWM_CHn interrupt flag accumulator enable. + * @var EPWM_T::AINTSTS + * Offset: 0x150 EPWM Accumulator Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag + * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. + * @var EPWM_T::AINTEN + * Offset: 0x154 EPWM Accumulator Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits + * | | |0 = Interrupt Flag accumulator interrupt Disabled. + * | | |1 = Interrupt Flag accumulator interrupt Enabled. + * @var EPWM_T::APDMACTL + * Offset: 0x158 EPWM Accumulator PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APDMAEN0 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[1] |APDMAEN1 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[2] |APDMAEN2 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[3] |APDMAEN3 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[4] |APDMAEN4 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * |[5] |APDMAEN5 |Channel N Accumulator PDMA Enable Bits + * | | |0 = Channel n PDMA function Disabled. + * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. + * @var EPWM_T::CAPINEN + * Offset: 0x200 EPWM Capture Input Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPINEN0 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[1] |CAPINEN1 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[2] |CAPINEN2 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[3] |CAPINEN3 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[4] |CAPINEN4 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * |[5] |CAPINEN5 |Capture Input Enable Bits + * | | |0 = EPWM Channel capture input path Disabled + * | | |The input of EPWM channel capture function is always regarded as 0. + * | | |1 = EPWM Channel capture input path Enabled + * | | |The input of EPWM channel capture function comes from correlative multifunction pin. + * @var EPWM_T::CAPCTL + * Offset: 0x204 EPWM Capture Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPEN0 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[1] |CAPEN1 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[2] |CAPEN2 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[3] |CAPEN3 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[4] |CAPEN4 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[5] |CAPEN5 |Capture Function Enable Bits + * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. + * | | |1 = Capture function Enabled + * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). + * |[8] |CAPINV0 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[9] |CAPINV1 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[10] |CAPINV2 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[11] |CAPINV3 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[12] |CAPINV4 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[13] |CAPINV5 |Capture Inverter Enable Bits + * | | |0 = Capture source inverter Disabled. + * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. + * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits + * | | |0 = Rising capture reload counter Disabled. + * | | |1 = Rising capture reload counter Enabled. + * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits + * | | |0 = Falling capture reload counter Disabled. + * | | |1 = Falling capture reload counter Enabled. + * @var EPWM_T::CAPSTS + * Offset: 0x208 EPWM Capture Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. + * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) + * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. + * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. + * @var EPWM_T::PDMACTL + * Offset: 0x23C EPWM PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable + * | | |0 = Channel 0/1 PDMA function Disabled. + * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory. + * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT0/1 register. + * | | |10 = EPWM_FCAPDAT0/1 register. + * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1 registers. + * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to = 0x3. + * | | |0 = EPWM_FCAPDAT0/1 register is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT0/1 register is the first captured data to memory. + * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer + * | | |0 = Channel0. + * | | |1 = Channel1. + * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable + * | | |0 = Channel 2/3 PDMA function Disabled. + * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory. + * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT2/3 register. + * | | |10 = EPWM_FCAPDAT2/3 register. + * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3 registers. + * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 register is the first captured data transferred to memory through PDMA when CAPMOD2_3 bits are set to =0x3. + * | | |0 = EPWM_FCAPDAT2/3 register is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT2/3 register is the first captured data to memory. + * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer + * | | |0 = Channel2. + * | | |1 = Channel3. + * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable + * | | |0 = Channel 4/5 PDMA function Disabled. + * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory. + * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer + * | | |00 = Reserved. + * | | |01 = EPWM_RCAPDAT4/5 register. + * | | |10 = EPWM_FCAPDAT4/5 register. + * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5 registers. + * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order + * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits =are set to 0x3. + * | | |0 = EPWM_FCAPDAT4/5 register is the first captured data to memory. + * | | |1 = EPWM_RCAPDAT4/5 register is the first captured data to memory. + * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer + * | | |0 = Channel4. + * | | |1 = Channel5. + * @var EPWM_T::PDMACAP[3] + * Offset: 0x240 EPWM Capture Channel 01 PDMA Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only) + * | | |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. + * @var EPWM_T::CAPIEN + * Offset: 0x250 EPWM Capture Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN0 bit must be disabled. + * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN1 bit must be disabled. + * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN2 bit must be disabled. + * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN3 bit must be disabled. + * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN4 bit must be disabled. + * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits + * | | |0 = Capture rising edge latch interrupt Disabled. + * | | |1 = Capture rising edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN5 bit must be disabled. + * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN0 bit must be disabled. + * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN1 bit must be disabled. + * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN2 bit must be disabled. + * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN3 bit must be disabled. + * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN4 bit must be disabled. + * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits + * | | |0 = Capture falling edge latch interrupt Disabled. + * | | |1 = Capture falling edge latch interrupt Enabled. + * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN5 bit must be disabled. + * @var EPWM_T::CAPIF + * Offset: 0x254 EPWM Capture Interrupt Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF0 bit will cleared by hardware after PDMA transfer data. + * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF1 bit will cleared by hardware after PDMA transfer data. + * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF2 bit will cleared by hardware after PDMA transfer data. + * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF3 bit will cleared by hardware after PDMA transfer data. + * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF4 bit will cleared by hardware after PDMA transfer data. + * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture rising latch condition happened. + * | | |1 = Capture rising latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF5 bit will cleared by hardware after PDMA transfer data. + * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF0 bit will cleared by hardware after PDMA transfer data. + * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF1 bit will cleared by hardware after PDMA transfer data. + * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF2 bit will cleared by hardware after PDMA transfer data. + * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF3 bit will cleared by hardware after PDMA transfer data. + * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF4 bit will cleared by hardware after PDMA transfer data. + * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag + * | | |This bit is writing 1 to clear. + * | | |0 = No capture falling latch condition happened. + * | | |1 = Capture falling latch condition happened, this flag will be set to high. + * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. + * @var EPWM_T::PBUF[6] + * Offset: 0x304 EPWM PERIOD0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) + * | | |Used as PERIOD active register. + * @var EPWM_T::CMPBUF[6] + * Offset: 0x31C EPWM CMPDAT0~5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) + * | | |Used as CMP active register. + * @var EPWM_T::CPSCBUF[3] + * Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer + * | | |Use as EPWM counter clock prescale active register. + * @var EPWM_T::FTCBUF[3] + * Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only) + * | | |Used as FTCMPDAT active register. + * @var EPWM_T::FTCI + * Offset: 0x34C EPWM FTCMPDAT Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. + * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator + * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. + */ + __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */ + __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */ + __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */ + __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */ + __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */ + __IO uint32_t CLKPSC[3]; /*!< [0x0014~0x001c] EPWM Clock Prescale Register 0_1,2_3,4_5 */ + __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */ + __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */ + __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t PERIOD[6]; /*!< [0x0030~0x0044] EPWM Period Register 0~5 */ + __I uint32_t RESERVE1[2]; + __IO uint32_t CMPDAT[6]; /*!< [0x0050~0x0064] EPWM Comparator Register 0~5 */ + __I uint32_t RESERVE2[2]; + __IO uint32_t DTCTL[3]; /*!< [0x0070~0x0078] EPWM Dead-Time Control Register 0_1,2_3,4_5 */ + __I uint32_t RESERVE3[1]; + __IO uint32_t PHS[3]; /*!< [0x0080~0x0088] EPWM Counter Phase Register 0_1,2_3,4_5 */ + __I uint32_t RESERVE4[1]; + __I uint32_t CNT[6]; /*!< [0x0090~0x00A4 EPWM Counter Register 0~5 */ + __I uint32_t RESERVE5[2]; + __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */ + __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */ + __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */ + __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */ + __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */ + __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */ + __IO uint32_t BRKCTL[3]; /*!< [0x00c8~0x00d0] EPWM Brake Edge Detect Control Register 0_1,2_3,4_5 */ + __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */ + __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */ + __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */ + __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */ + __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */ + __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */ + __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */ + __I uint32_t RESERVE6[1]; + __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */ + __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */ + __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */ + __IO uint32_t FTCMPDAT[3]; /*!< [0x0100~0x108] EPWM Free Trigger Compare Register 0_1,2_3,4_5 */ + __I uint32_t RESERVE7[1]; + __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */ + __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */ + __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */ + __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */ + __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */ + __I uint32_t RESERVE8[3]; + __IO uint32_t IFA[6]; /*!< [0x0130~0x144] EPWM Interrupt Flag Accumulator Register 0~5 */ + __I uint32_t RESERVE9[2]; + __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */ + __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */ + __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */ + __I uint32_t RESERVE10[1]; + __IO uint32_t FDEN; /*!< [0x0160] EPWM Fault Detect Enable Register */ + __IO uint32_t FDCTL[6]; /*!< [0x0164~0x178] EPWM Fault Detect Control Register 0~5 */ + __IO uint32_t FDIEN; /*!< [0x017C] EPWM Fault Detect Interrupt Enable Register */ + __IO uint32_t FDSTS; /*!< [0x0180] EPWM Fault Detect Interrupt Flag Register */ + __IO uint32_t EADCPSCCTL; /*!< [0x0184] EPWM Trigger EADC Prescale Control Register */ + __IO uint32_t EADCPSC0; /*!< [0x0188] EPWM Trigger EADC Prescale Register 0 */ + __IO uint32_t EADCPSC1; /*!< [0x018C] EPWM Trigger EADC Prescale Register 1 */ + __IO uint32_t EADCPSCNT0; /*!< [0x0190] EPWM Trigger EADC Prescale Counter Register 0 */ + __IO uint32_t EADCPSCNT1; /*!< [0x0194] EPWM Trigger EADC Prescale Counter Register 1 */ + __I uint32_t RESERVE11[26]; + __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */ + __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */ + __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */ + ECAPDAT_T CAPDAT[6]; /*!< [0x020c~0x0238] EPWM Rising and Falling Capture Data Register 0~5 */ + __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */ + __I uint32_t PDMACAP[3]; /*!< [0x0240~0x248] EPWM Capture Channel 0_1,2_3,4_5 PDMA Register */ + __I uint32_t RESERVE12[1]; + __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */ + __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */ + __I uint32_t RESERVE13[43]; + __I uint32_t PBUF[6]; /*!< [0x0304~0x0318 EPWM PERIOD0~5 Buffer */ + __I uint32_t CMPBUF[6]; /*!< [0x031C~0x0330 EPWM CMPDAT0~5 Buffer */ + __I uint32_t CPSCBUF[3]; /*!< [0x0334~0x33c] EPWM CLKPSC0_1,2_3,4_5 Buffer */ + __I uint32_t FTCBUF[3]; /*!< [0x0340~0x348] EPWM FTCMPDAT0_1,2_3,4_5 Buffer */ + __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */ + +} EPWM_T; + +/** + @addtogroup EPWM_CONST EPWM Bit Field Definition + Constant Definitions for EPWM Controller + @{ +*/ + +#define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */ +#define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */ + +#define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */ +#define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */ + +#define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */ +#define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */ + +#define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */ +#define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */ + +#define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */ +#define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */ + +#define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */ +#define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */ + +#define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */ +#define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */ + +#define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */ +#define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */ + +#define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */ +#define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */ + +#define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */ +#define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */ + +#define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */ +#define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */ + +#define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */ +#define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */ + +#define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */ +#define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */ + +#define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */ +#define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */ + +#define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */ +#define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */ + +#define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */ +#define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */ + +#define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */ +#define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */ + +#define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */ +#define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */ + +#define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */ +#define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */ + +#define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */ +#define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */ + +#define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */ +#define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */ + +#define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */ +#define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */ + +#define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */ +#define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */ + +#define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */ +#define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */ + +#define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */ +#define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */ + +#define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */ +#define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */ + +#define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */ +#define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */ + +#define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */ +#define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */ + +#define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */ +#define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */ + +#define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */ +#define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */ + +#define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */ +#define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */ + +#define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */ +#define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */ + +#define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */ +#define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */ + +#define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */ +#define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */ + +#define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */ +#define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */ + +#define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */ +#define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */ + +#define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */ +#define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */ + +#define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */ +#define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */ + +#define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */ +#define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */ + +#define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */ +#define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */ + +#define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */ +#define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */ + +#define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */ +#define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */ + +#define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */ +#define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */ + +#define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */ +#define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */ + +#define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */ +#define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */ + +#define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */ +#define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */ + +#define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */ +#define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */ + +#define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */ +#define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */ + +#define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */ +#define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */ + +#define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */ +#define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */ + +#define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */ +#define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */ + +#define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */ +#define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */ + +#define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */ +#define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */ + +#define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */ +#define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */ + +#define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */ +#define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */ + +#define EPWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0_1: CLKPSC Position */ +#define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask */ + +#define EPWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2_3: CLKPSC Position */ +#define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask */ + +#define EPWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4_5: CLKPSC Position */ +#define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask */ + +#define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */ +#define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */ + +#define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */ +#define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */ + +#define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */ +#define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */ + +#define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */ +#define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */ + +#define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */ +#define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */ + +#define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */ +#define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */ + +#define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */ +#define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */ + +#define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */ +#define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */ + +#define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */ +#define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */ + +#define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */ +#define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */ + +#define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */ +#define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */ + +#define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */ +#define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */ + +#define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */ +#define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */ + +#define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */ +#define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */ + +#define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */ +#define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */ + +#define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */ +#define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */ + +#define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */ +#define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */ + +#define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */ +#define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */ + +#define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */ +#define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */ + +#define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */ +#define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */ + +#define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */ +#define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */ + +#define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */ +#define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */ + +#define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */ +#define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */ + +#define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */ +#define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */ + +#define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */ +#define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */ + +#define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */ +#define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */ + +#define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */ +#define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */ + +#define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */ +#define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */ + +#define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */ +#define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */ + +#define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */ +#define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */ + +#define EPWM_DTCTL0_1_DTCNT_Pos (0) /*!< EPWM_T::DTCTL0_1: DTCNT Position */ +#define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) /*!< EPWM_T::DTCTL0_1: DTCNT Mask */ + +#define EPWM_DTCTL0_1_DTEN_Pos (16) /*!< EPWM_T::DTCTL0_1: DTEN Position */ +#define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) /*!< EPWM_T::DTCTL0_1: DTEN Mask */ + +#define EPWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL0_1: DTCKSEL Position */ +#define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask */ + +#define EPWM_DTCTL2_3_DTCNT_Pos (0) /*!< EPWM_T::DTCTL2_3: DTCNT Position */ +#define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) /*!< EPWM_T::DTCTL2_3: DTCNT Mask */ + +#define EPWM_DTCTL2_3_DTEN_Pos (16) /*!< EPWM_T::DTCTL2_3: DTEN Position */ +#define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) /*!< EPWM_T::DTCTL2_3: DTEN Mask */ + +#define EPWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL2_3: DTCKSEL Position */ +#define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask */ + +#define EPWM_DTCTL4_5_DTCNT_Pos (0) /*!< EPWM_T::DTCTL4_5: DTCNT Position */ +#define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) /*!< EPWM_T::DTCTL4_5: DTCNT Mask */ + +#define EPWM_DTCTL4_5_DTEN_Pos (16) /*!< EPWM_T::DTCTL4_5: DTEN Position */ +#define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) /*!< EPWM_T::DTCTL4_5: DTEN Mask */ + +#define EPWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL4_5: DTCKSEL Position */ +#define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask */ + +#define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */ +#define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */ + +#define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */ +#define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */ + +#define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */ +#define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */ + +#define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */ +#define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */ + +#define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */ +#define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */ + +#define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */ +#define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */ + +#define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */ +#define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */ + +#define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */ +#define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */ + +#define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */ +#define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */ + +#define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */ +#define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */ + +#define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */ +#define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */ + +#define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */ +#define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */ + +#define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */ +#define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */ + +#define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */ +#define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */ + +#define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */ +#define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */ + +#define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */ +#define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */ + +#define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */ +#define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */ + +#define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */ +#define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */ + +#define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */ +#define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */ + +#define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */ +#define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */ + +#define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */ +#define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */ + +#define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */ +#define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */ + +#define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */ +#define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */ + +#define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */ +#define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */ + +#define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */ +#define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */ + +#define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */ +#define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */ + +#define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */ +#define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */ + +#define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */ +#define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */ + +#define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */ +#define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */ + +#define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */ +#define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */ + +#define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */ +#define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */ + +#define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */ +#define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */ + +#define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */ +#define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */ + +#define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */ +#define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */ + +#define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */ +#define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */ + +#define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */ +#define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */ + +#define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */ +#define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */ + +#define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */ +#define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */ + +#define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */ +#define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */ + +#define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */ +#define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */ + +#define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */ +#define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */ + +#define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */ +#define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */ + +#define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */ +#define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */ + +#define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */ +#define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */ + +#define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */ +#define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */ + +#define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */ +#define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */ + +#define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */ +#define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */ + +#define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */ +#define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */ + +#define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */ +#define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */ + +#define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */ +#define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */ + +#define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */ +#define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */ + +#define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */ +#define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */ + +#define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */ +#define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */ + +#define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */ +#define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */ + +#define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */ +#define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */ + +#define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */ +#define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */ + +#define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */ +#define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */ + +#define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */ +#define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */ + +#define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */ +#define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */ + +#define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */ +#define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */ + +#define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */ +#define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */ + +#define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */ +#define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */ + +#define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */ +#define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */ + +#define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */ +#define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */ + +#define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */ +#define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */ + +#define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */ +#define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */ +#define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */ +#define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */ +#define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */ + +#define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */ +#define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */ +#define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */ + +#define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */ +#define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */ +#define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */ + +#define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */ +#define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */ + +#define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */ +#define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */ +#define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */ + +#define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */ +#define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */ + +#define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position */ +#define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask */ + +#define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position */ +#define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */ +#define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */ +#define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */ +#define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */ +#define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */ + +#define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */ +#define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */ +#define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */ + +#define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */ +#define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */ +#define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */ + +#define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */ +#define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */ + +#define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */ +#define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */ +#define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */ + +#define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */ +#define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */ + +#define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position */ +#define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask */ + +#define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position */ +#define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */ +#define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */ +#define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */ +#define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */ +#define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */ + +#define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */ +#define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */ +#define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */ + +#define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */ +#define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */ +#define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */ + +#define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */ +#define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */ + +#define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */ +#define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */ +#define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */ + +#define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */ +#define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */ + +#define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position */ +#define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask */ + +#define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position */ +#define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask */ + +#define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */ +#define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */ + +#define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */ +#define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */ + +#define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */ +#define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */ + +#define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */ +#define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */ + +#define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */ +#define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */ + +#define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */ +#define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */ + +#define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */ +#define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */ + +#define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */ +#define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */ + +#define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */ +#define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */ + +#define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */ +#define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */ + +#define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */ +#define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */ + +#define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */ +#define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */ + +#define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */ +#define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */ + +#define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */ +#define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */ + +#define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */ +#define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */ + +#define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */ +#define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */ + +#define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */ +#define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */ + +#define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */ +#define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */ + +#define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */ +#define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */ + +#define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */ +#define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */ + +#define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */ +#define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */ + +#define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */ +#define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */ + +#define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */ +#define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */ + +#define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */ +#define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */ + +#define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */ +#define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */ + +#define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */ +#define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */ + +#define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */ +#define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */ + +#define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */ +#define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */ + +#define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */ +#define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */ + +#define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */ +#define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */ + +#define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */ +#define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */ + +#define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */ +#define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */ + +#define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */ +#define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */ + +#define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */ +#define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */ + +#define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */ +#define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */ + +#define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */ +#define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */ + +#define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */ +#define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */ + +#define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */ +#define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */ + +#define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */ +#define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */ + +#define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */ +#define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */ + +#define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */ +#define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */ + +#define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */ +#define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */ + +#define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */ +#define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */ +#define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */ +#define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */ + +#define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */ +#define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */ + +#define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */ +#define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */ + +#define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */ +#define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */ + +#define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */ +#define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */ + +#define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */ +#define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */ + +#define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */ +#define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */ + +#define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */ +#define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */ + +#define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */ +#define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */ + +#define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */ +#define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */ + +#define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */ +#define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */ + +#define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */ +#define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */ + +#define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */ +#define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */ + +#define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */ +#define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */ + +#define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */ +#define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */ + +#define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */ +#define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */ + +#define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */ +#define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */ + +#define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */ +#define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */ + +#define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */ +#define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */ + +#define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */ +#define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */ + +#define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */ +#define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */ + +#define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */ +#define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */ + +#define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */ +#define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */ + +#define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */ +#define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */ + +#define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */ +#define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */ + +#define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */ +#define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */ + +#define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */ +#define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */ + +#define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */ +#define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */ + +#define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */ +#define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */ + +#define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */ +#define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */ + +#define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */ +#define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */ + +#define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */ +#define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */ + +#define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */ +#define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */ + +#define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */ +#define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */ + +#define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */ +#define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */ + +#define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */ +#define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */ + +#define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */ +#define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */ + +#define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */ +#define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */ + +#define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */ +#define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */ + +#define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */ +#define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */ + +#define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */ +#define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */ + +#define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */ +#define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */ + +#define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */ +#define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */ + +#define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */ +#define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */ + +#define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */ +#define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */ + +#define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */ +#define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */ + +#define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */ +#define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */ + +#define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */ +#define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */ + +#define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */ +#define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */ + +#define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */ +#define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */ + +#define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */ +#define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */ + +#define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */ +#define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */ + +#define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */ +#define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */ + +#define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */ +#define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */ + +#define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */ +#define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */ + +#define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */ +#define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */ + +#define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */ +#define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */ + +#define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */ +#define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */ + +#define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */ +#define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */ + +#define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */ +#define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */ + +#define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */ +#define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */ + +#define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */ +#define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */ + +#define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */ +#define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */ + +#define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */ +#define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */ + +#define EPWM_DACTRGEN_CUTRGE0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGE0 Position */ +#define EPWM_DACTRGEN_CUTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask */ + +#define EPWM_DACTRGEN_CUTRGE1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGE1 Position */ +#define EPWM_DACTRGEN_CUTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask */ + +#define EPWM_DACTRGEN_CUTRGE2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGE2 Position */ +#define EPWM_DACTRGEN_CUTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask */ + +#define EPWM_DACTRGEN_CUTRGE3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGE3 Position */ +#define EPWM_DACTRGEN_CUTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask */ + +#define EPWM_DACTRGEN_CUTRGE4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGE4 Position */ +#define EPWM_DACTRGEN_CUTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask */ + +#define EPWM_DACTRGEN_CUTRGE5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGE5 Position */ +#define EPWM_DACTRGEN_CUTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask */ + +#define EPWM_DACTRGEN_CDTRGE0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGE0 Position */ +#define EPWM_DACTRGEN_CDTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask */ + +#define EPWM_DACTRGEN_CDTRGE1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGE1 Position */ +#define EPWM_DACTRGEN_CDTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask */ + +#define EPWM_DACTRGEN_CDTRGE2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGE2 Position */ +#define EPWM_DACTRGEN_CDTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask */ + +#define EPWM_DACTRGEN_CDTRGE3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGE3 Position */ +#define EPWM_DACTRGEN_CDTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask */ + +#define EPWM_DACTRGEN_CDTRGE4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGE4 Position */ +#define EPWM_DACTRGEN_CDTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask */ + +#define EPWM_DACTRGEN_CDTRGE5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGE5 Position */ +#define EPWM_DACTRGEN_CDTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask */ + +#define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */ +#define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */ + +#define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */ +#define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */ + +#define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */ +#define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */ + +#define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */ +#define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */ + +#define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */ +#define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */ + +#define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */ +#define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */ + +#define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */ +#define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */ + +#define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */ +#define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */ + +#define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */ +#define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */ + +#define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */ +#define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */ + +#define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */ +#define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */ + +#define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */ +#define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */ + +#define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */ +#define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */ + +#define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */ +#define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */ + +#define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */ +#define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */ + +#define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */ +#define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */ + +#define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */ +#define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */ + +#define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */ +#define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */ + +#define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */ +#define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */ + +#define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */ +#define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */ + +#define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */ +#define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */ + +#define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */ +#define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */ + +#define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */ +#define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */ + +#define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */ +#define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */ + +#define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */ +#define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */ + +#define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */ +#define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */ + +#define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */ +#define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */ + +#define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */ +#define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */ + +#define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */ +#define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */ + +#define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */ +#define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */ + +#define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */ +#define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */ + +#define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */ +#define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */ + +#define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */ +#define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */ + +#define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */ +#define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */ + +#define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */ +#define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */ + +#define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */ +#define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */ + +#define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */ +#define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */ + +#define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */ +#define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */ + +#define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */ +#define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */ + +#define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */ +#define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */ + +#define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */ +#define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */ + +#define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */ +#define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */ + +#define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */ +#define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */ + +#define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */ +#define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */ + +#define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */ +#define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */ + +#define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */ +#define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */ + +#define EPWM_IFA0_STPMOD_Pos (24) /*!< EPWM_T::IFA0: STPMOD Position */ +#define EPWM_IFA0_STPMOD_Msk (0x1ul << EPWM_IFA0_STPMOD_Pos) /*!< EPWM_T::IFA0: STPMOD Mask */ + +#define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */ +#define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */ + +#define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */ +#define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */ + +#define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */ +#define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */ + +#define EPWM_IFA1_STPMOD_Pos (24) /*!< EPWM_T::IFA1: STPMOD Position */ +#define EPWM_IFA1_STPMOD_Msk (0x1ul << EPWM_IFA1_STPMOD_Pos) /*!< EPWM_T::IFA1: STPMOD Mask */ + +#define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */ +#define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */ + +#define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */ +#define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */ + +#define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */ +#define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */ + +#define EPWM_IFA2_STPMOD_Pos (24) /*!< EPWM_T::IFA2: STPMOD Position */ +#define EPWM_IFA2_STPMOD_Msk (0x1ul << EPWM_IFA2_STPMOD_Pos) /*!< EPWM_T::IFA2: STPMOD Mask */ + +#define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */ +#define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */ + +#define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */ +#define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */ + +#define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */ +#define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */ + +#define EPWM_IFA3_STPMOD_Pos (24) /*!< EPWM_T::IFA3: STPMOD Position */ +#define EPWM_IFA3_STPMOD_Msk (0x1ul << EPWM_IFA3_STPMOD_Pos) /*!< EPWM_T::IFA3: STPMOD Mask */ + +#define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */ +#define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */ + +#define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */ +#define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */ + +#define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */ +#define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */ + +#define EPWM_IFA4_STPMOD_Pos (24) /*!< EPWM_T::IFA4: STPMOD Position */ +#define EPWM_IFA4_STPMOD_Msk (0x1ul << EPWM_IFA4_STPMOD_Pos) /*!< EPWM_T::IFA4: STPMOD Mask */ + +#define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */ +#define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */ + +#define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */ +#define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */ + +#define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */ +#define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */ + +#define EPWM_IFA5_STPMOD_Pos (24) /*!< EPWM_T::IFA5: STPMOD Position */ +#define EPWM_IFA5_STPMOD_Msk (0x1ul << EPWM_IFA5_STPMOD_Pos) /*!< EPWM_T::IFA5: STPMOD Mask */ + +#define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */ +#define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */ + +#define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */ +#define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */ + +#define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */ +#define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */ + +#define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */ +#define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */ + +#define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */ +#define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */ + +#define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */ +#define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */ + +#define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */ +#define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */ + +#define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */ +#define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */ + +#define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */ +#define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */ + +#define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */ +#define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */ + +#define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */ +#define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */ + +#define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */ +#define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */ + +#define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */ +#define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */ + +#define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */ +#define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */ + +#define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */ +#define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */ + +#define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */ +#define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */ + +#define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */ +#define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */ + +#define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */ +#define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */ + +#define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */ +#define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */ + +#define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */ +#define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */ + +#define EPWM_FDEN_FDEN0_Pos (0) /*!< EPWM_T::FDEN: FDEN0 Position */ +#define EPWM_FDEN_FDEN0_Msk (0x1ul << EPWM_FDEN_FDEN0_Pos) /*!< EPWM_T::FDEN: FDEN0 Mask */ + +#define EPWM_FDEN_FDEN1_Pos (1) /*!< EPWM_T::FDEN: FDEN1 Position */ +#define EPWM_FDEN_FDEN1_Msk (0x1ul << EPWM_FDEN_FDEN1_Pos) /*!< EPWM_T::FDEN: FDEN1 Mask */ + +#define EPWM_FDEN_FDEN2_Pos (2) /*!< EPWM_T::FDEN: FDEN2 Position */ +#define EPWM_FDEN_FDEN2_Msk (0x1ul << EPWM_FDEN_FDEN2_Pos) /*!< EPWM_T::FDEN: FDEN2 Mask */ + +#define EPWM_FDEN_FDEN3_Pos (3) /*!< EPWM_T::FDEN: FDEN3 Position */ +#define EPWM_FDEN_FDEN3_Msk (0x1ul << EPWM_FDEN_FDEN3_Pos) /*!< EPWM_T::FDEN: FDEN3 Mask */ + +#define EPWM_FDEN_FDEN4_Pos (4) /*!< EPWM_T::FDEN: FDEN4 Position */ +#define EPWM_FDEN_FDEN4_Msk (0x1ul << EPWM_FDEN_FDEN4_Pos) /*!< EPWM_T::FDEN: FDEN4 Mask */ + +#define EPWM_FDEN_FDEN5_Pos (5) /*!< EPWM_T::FDEN: FDEN5 Position */ +#define EPWM_FDEN_FDEN5_Msk (0x1ul << EPWM_FDEN_FDEN5_Pos) /*!< EPWM_T::FDEN: FDEN5 Mask */ + +#define EPWM_FDEN_FDODIS0_Pos (8) /*!< EPWM_T::FDEN: FDODIS0 Position */ +#define EPWM_FDEN_FDODIS0_Msk (0x1ul << EPWM_FDEN_FDODIS0_Pos) /*!< EPWM_T::FDEN: FDODIS0 Mask */ + +#define EPWM_FDEN_FDODIS1_Pos (9) /*!< EPWM_T::FDEN: FDODIS1 Position */ +#define EPWM_FDEN_FDODIS1_Msk (0x1ul << EPWM_FDEN_FDODIS1_Pos) /*!< EPWM_T::FDEN: FDODIS1 Mask */ + +#define EPWM_FDEN_FDODIS2_Pos (10) /*!< EPWM_T::FDEN: FDODIS2 Position */ +#define EPWM_FDEN_FDODIS2_Msk (0x1ul << EPWM_FDEN_FDODIS2_Pos) /*!< EPWM_T::FDEN: FDODIS2 Mask */ + +#define EPWM_FDEN_FDODIS3_Pos (11) /*!< EPWM_T::FDEN: FDODIS3 Position */ +#define EPWM_FDEN_FDODIS3_Msk (0x1ul << EPWM_FDEN_FDODIS3_Pos) /*!< EPWM_T::FDEN: FDODIS3 Mask */ + +#define EPWM_FDEN_FDODIS4_Pos (12) /*!< EPWM_T::FDEN: FDODIS4 Position */ +#define EPWM_FDEN_FDODIS4_Msk (0x1ul << EPWM_FDEN_FDODIS4_Pos) /*!< EPWM_T::FDEN: FDODIS4 Mask */ + +#define EPWM_FDEN_FDODIS5_Pos (13) /*!< EPWM_T::FDEN: FDODIS5 Position */ +#define EPWM_FDEN_FDODIS5_Msk (0x1ul << EPWM_FDEN_FDODIS5_Pos) /*!< EPWM_T::FDEN: FDODIS5 Mask */ + +#define EPWM_FDEN_FDCKS0_Pos (16) /*!< EPWM_T::FDEN: FDCKS0 Position */ +#define EPWM_FDEN_FDCKS0_Msk (0x1ul << EPWM_FDEN_FDCKS0_Pos) /*!< EPWM_T::FDEN: FDCKS0 Mask */ + +#define EPWM_FDEN_FDCKS1_Pos (17) /*!< EPWM_T::FDEN: FDCKS1 Position */ +#define EPWM_FDEN_FDCKS1_Msk (0x1ul << EPWM_FDEN_FDCKS1_Pos) /*!< EPWM_T::FDEN: FDCKS1 Mask */ + +#define EPWM_FDEN_FDCKS2_Pos (18) /*!< EPWM_T::FDEN: FDCKS2 Position */ +#define EPWM_FDEN_FDCKS2_Msk (0x1ul << EPWM_FDEN_FDCKS2_Pos) /*!< EPWM_T::FDEN: FDCKS2 Mask */ + +#define EPWM_FDEN_FDCKS3_Pos (19) /*!< EPWM_T::FDEN: FDCKS3 Position */ +#define EPWM_FDEN_FDCKS3_Msk (0x1ul << EPWM_FDEN_FDCKS3_Pos) /*!< EPWM_T::FDEN: FDCKS3 Mask */ + +#define EPWM_FDEN_FDCKS4_Pos (20) /*!< EPWM_T::FDEN: FDCKS4 Position */ +#define EPWM_FDEN_FDCKS4_Msk (0x1ul << EPWM_FDEN_FDCKS4_Pos) /*!< EPWM_T::FDEN: FDCKS4 Mask */ + +#define EPWM_FDEN_FDCKS5_Pos (21) /*!< EPWM_T::FDEN: FDCKS5 Position */ +#define EPWM_FDEN_FDCKS5_Msk (0x1ul << EPWM_FDEN_FDCKS5_Pos) /*!< EPWM_T::FDEN: FDCKS5 Mask */ + +#define EPWM_FDCTL0_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL0: TRMSKCNT Position */ +#define EPWM_FDCTL0_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL0_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL0: TRMSKCNT Mask */ + +#define EPWM_FDCTL0_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL0: FDMSKEN Position */ +#define EPWM_FDCTL0_FDMSKEN_Msk (0x1ul << EPWM_FDCTL0_FDMSKEN_Pos) /*!< EPWM_T::FDCTL0: FDMSKEN Mask */ + +#define EPWM_FDCTL0_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL0: DGSMPCYC Position */ +#define EPWM_FDCTL0_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL0_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL0: DGSMPCYC Mask */ + +#define EPWM_FDCTL0_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL0: FDCKSEL Position */ +#define EPWM_FDCTL0_FDCKSEL_Msk (0x3ul << EPWM_FDCTL0_FDCKSEL_Pos) /*!< EPWM_T::FDCTL0: FDCKSEL Mask */ + +#define EPWM_FDCTL0_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL0: FDDGEN Position */ +#define EPWM_FDCTL0_FDDGEN_Msk (0x1ul << EPWM_FDCTL0_FDDGEN_Pos) /*!< EPWM_T::FDCTL0: FDDGEN Mask */ + +#define EPWM_FDCTL1_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL1: TRMSKCNT Position */ +#define EPWM_FDCTL1_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL1_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL1: TRMSKCNT Mask */ + +#define EPWM_FDCTL1_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL1: FDMSKEN Position */ +#define EPWM_FDCTL1_FDMSKEN_Msk (0x1ul << EPWM_FDCTL1_FDMSKEN_Pos) /*!< EPWM_T::FDCTL1: FDMSKEN Mask */ + +#define EPWM_FDCTL1_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL1: DGSMPCYC Position */ +#define EPWM_FDCTL1_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL1_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL1: DGSMPCYC Mask */ + +#define EPWM_FDCTL1_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL1: FDCKSEL Position */ +#define EPWM_FDCTL1_FDCKSEL_Msk (0x3ul << EPWM_FDCTL1_FDCKSEL_Pos) /*!< EPWM_T::FDCTL1: FDCKSEL Mask */ + +#define EPWM_FDCTL1_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL1: FDDGEN Position */ +#define EPWM_FDCTL1_FDDGEN_Msk (0x1ul << EPWM_FDCTL1_FDDGEN_Pos) /*!< EPWM_T::FDCTL1: FDDGEN Mask */ + +#define EPWM_FDCTL2_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL2: TRMSKCNT Position */ +#define EPWM_FDCTL2_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL2_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL2: TRMSKCNT Mask */ + +#define EPWM_FDCTL2_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL2: FDMSKEN Position */ +#define EPWM_FDCTL2_FDMSKEN_Msk (0x1ul << EPWM_FDCTL2_FDMSKEN_Pos) /*!< EPWM_T::FDCTL2: FDMSKEN Mask */ + +#define EPWM_FDCTL2_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL2: DGSMPCYC Position */ +#define EPWM_FDCTL2_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL2_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL2: DGSMPCYC Mask */ + +#define EPWM_FDCTL2_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL2: FDCKSEL Position */ +#define EPWM_FDCTL2_FDCKSEL_Msk (0x3ul << EPWM_FDCTL2_FDCKSEL_Pos) /*!< EPWM_T::FDCTL2: FDCKSEL Mask */ + +#define EPWM_FDCTL2_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL2: FDDGEN Position */ +#define EPWM_FDCTL2_FDDGEN_Msk (0x1ul << EPWM_FDCTL2_FDDGEN_Pos) /*!< EPWM_T::FDCTL2: FDDGEN Mask */ + +#define EPWM_FDCTL3_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL3: TRMSKCNT Position */ +#define EPWM_FDCTL3_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL3_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL3: TRMSKCNT Mask */ + +#define EPWM_FDCTL3_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL3: FDMSKEN Position */ +#define EPWM_FDCTL3_FDMSKEN_Msk (0x1ul << EPWM_FDCTL3_FDMSKEN_Pos) /*!< EPWM_T::FDCTL3: FDMSKEN Mask */ + +#define EPWM_FDCTL3_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL3: DGSMPCYC Position */ +#define EPWM_FDCTL3_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL3_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL3: DGSMPCYC Mask */ + +#define EPWM_FDCTL3_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL3: FDCKSEL Position */ +#define EPWM_FDCTL3_FDCKSEL_Msk (0x3ul << EPWM_FDCTL3_FDCKSEL_Pos) /*!< EPWM_T::FDCTL3: FDCKSEL Mask */ + +#define EPWM_FDCTL3_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL3: FDDGEN Position */ +#define EPWM_FDCTL3_FDDGEN_Msk (0x1ul << EPWM_FDCTL3_FDDGEN_Pos) /*!< EPWM_T::FDCTL3: FDDGEN Mask */ + +#define EPWM_FDCTL4_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL4: TRMSKCNT Position */ +#define EPWM_FDCTL4_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL4_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL4: TRMSKCNT Mask */ + +#define EPWM_FDCTL4_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL4: FDMSKEN Position */ +#define EPWM_FDCTL4_FDMSKEN_Msk (0x1ul << EPWM_FDCTL4_FDMSKEN_Pos) /*!< EPWM_T::FDCTL4: FDMSKEN Mask */ + +#define EPWM_FDCTL4_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL4: DGSMPCYC Position */ +#define EPWM_FDCTL4_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL4_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL4: DGSMPCYC Mask */ + +#define EPWM_FDCTL4_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL4: FDCKSEL Position */ +#define EPWM_FDCTL4_FDCKSEL_Msk (0x3ul << EPWM_FDCTL4_FDCKSEL_Pos) /*!< EPWM_T::FDCTL4: FDCKSEL Mask */ + +#define EPWM_FDCTL4_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL4: FDDGEN Position */ +#define EPWM_FDCTL4_FDDGEN_Msk (0x1ul << EPWM_FDCTL4_FDDGEN_Pos) /*!< EPWM_T::FDCTL4: FDDGEN Mask */ + +#define EPWM_FDCTL5_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL5: TRMSKCNT Position */ +#define EPWM_FDCTL5_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL5_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL5: TRMSKCNT Mask */ + +#define EPWM_FDCTL5_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL5: FDMSKEN Position */ +#define EPWM_FDCTL5_FDMSKEN_Msk (0x1ul << EPWM_FDCTL5_FDMSKEN_Pos) /*!< EPWM_T::FDCTL5: FDMSKEN Mask */ + +#define EPWM_FDCTL5_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL5: DGSMPCYC Position */ +#define EPWM_FDCTL5_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL5_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL5: DGSMPCYC Mask */ + +#define EPWM_FDCTL5_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL5: FDCKSEL Position */ +#define EPWM_FDCTL5_FDCKSEL_Msk (0x3ul << EPWM_FDCTL5_FDCKSEL_Pos) /*!< EPWM_T::FDCTL5: FDCKSEL Mask */ + +#define EPWM_FDCTL5_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL5: FDDGEN Position */ +#define EPWM_FDCTL5_FDDGEN_Msk (0x1ul << EPWM_FDCTL5_FDDGEN_Pos) /*!< EPWM_T::FDCTL5: FDDGEN Mask */ + +#define EPWM_FDIEN_FDIEN0_Pos (0) /*!< EPWM_T::FDIEN: FDIEN0 Position */ +#define EPWM_FDIEN_FDIEN0_Msk (0x1ul << EPWM_FDIEN_FDIEN0_Pos) /*!< EPWM_T::FDIEN: FDIEN0 Mask */ + +#define EPWM_FDIEN_FDIEN1_Pos (1) /*!< EPWM_T::FDIEN: FDIEN1 Position */ +#define EPWM_FDIEN_FDIEN1_Msk (0x1ul << EPWM_FDIEN_FDIEN1_Pos) /*!< EPWM_T::FDIEN: FDIEN1 Mask */ + +#define EPWM_FDIEN_FDIEN2_Pos (2) /*!< EPWM_T::FDIEN: FDIEN2 Position */ +#define EPWM_FDIEN_FDIEN2_Msk (0x1ul << EPWM_FDIEN_FDIEN2_Pos) /*!< EPWM_T::FDIEN: FDIEN2 Mask */ + +#define EPWM_FDIEN_FDIEN3_Pos (3) /*!< EPWM_T::FDIEN: FDIEN3 Position */ +#define EPWM_FDIEN_FDIEN3_Msk (0x1ul << EPWM_FDIEN_FDIEN3_Pos) /*!< EPWM_T::FDIEN: FDIEN3 Mask */ + +#define EPWM_FDIEN_FDIEN4_Pos (4) /*!< EPWM_T::FDIEN: FDIEN4 Position */ +#define EPWM_FDIEN_FDIEN4_Msk (0x1ul << EPWM_FDIEN_FDIEN4_Pos) /*!< EPWM_T::FDIEN: FDIEN4 Mask */ + +#define EPWM_FDIEN_FDIEN5_Pos (5) /*!< EPWM_T::FDIEN: FDIEN5 Position */ +#define EPWM_FDIEN_FDIEN5_Msk (0x1ul << EPWM_FDIEN_FDIEN5_Pos) /*!< EPWM_T::FDIEN: FDIEN5 Mask */ + +#define EPWM_FDSTS_FDIF0_Pos (0) /*!< EPWM_T::FDSTS: FDIF0 Position */ +#define EPWM_FDSTS_FDIF0_Msk (0x1ul << EPWM_FDSTS_FDIF0_Pos) /*!< EPWM_T::FDSTS: FDIF0 Mask */ + +#define EPWM_FDSTS_FDIF1_Pos (1) /*!< EPWM_T::FDSTS: FDIF1 Position */ +#define EPWM_FDSTS_FDIF1_Msk (0x1ul << EPWM_FDSTS_FDIF1_Pos) /*!< EPWM_T::FDSTS: FDIF1 Mask */ + +#define EPWM_FDSTS_FDIF2_Pos (2) /*!< EPWM_T::FDSTS: FDIF2 Position */ +#define EPWM_FDSTS_FDIF2_Msk (0x1ul << EPWM_FDSTS_FDIF2_Pos) /*!< EPWM_T::FDSTS: FDIF2 Mask */ + +#define EPWM_FDSTS_FDIF3_Pos (3) /*!< EPWM_T::FDSTS: FDIF3 Position */ +#define EPWM_FDSTS_FDIF3_Msk (0x1ul << EPWM_FDSTS_FDIF3_Pos) /*!< EPWM_T::FDSTS: FDIF3 Mask */ + +#define EPWM_FDSTS_FDIF4_Pos (4) /*!< EPWM_T::FDSTS: FDIF4 Position */ +#define EPWM_FDSTS_FDIF4_Msk (0x1ul << EPWM_FDSTS_FDIF4_Pos) /*!< EPWM_T::FDSTS: FDIF4 Mask */ + +#define EPWM_FDSTS_FDIF5_Pos (5) /*!< EPWM_T::FDSTS: FDIF5 Position */ +#define EPWM_FDSTS_FDIF5_Msk (0x1ul << EPWM_FDSTS_FDIF5_Pos) /*!< EPWM_T::FDSTS: FDIF5 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN0_Pos (0) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Position */ +#define EPWM_EADCPSCCTL_PSCEN0_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN0_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN1_Pos (1) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Position */ +#define EPWM_EADCPSCCTL_PSCEN1_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN1_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN2_Pos (2) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Position */ +#define EPWM_EADCPSCCTL_PSCEN2_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN2_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN3_Pos (3) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Position */ +#define EPWM_EADCPSCCTL_PSCEN3_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN3_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN4_Pos (4) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Position */ +#define EPWM_EADCPSCCTL_PSCEN4_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN4_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Mask */ + +#define EPWM_EADCPSCCTL_PSCEN5_Pos (5) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Position */ +#define EPWM_EADCPSCCTL_PSCEN5_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN5_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Mask */ + +#define EPWM_EADCPSC0_EADCPSC0_Pos (0) /*!< EPWM_T::EADCPSC0: EADCPSC0 Position */ +#define EPWM_EADCPSC0_EADCPSC0_Msk (0xful << EPWM_EADCPSC0_EADCPSC0_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC0 Mask */ + +#define EPWM_EADCPSC0_EADCPSC1_Pos (8) /*!< EPWM_T::EADCPSC0: EADCPSC1 Position */ +#define EPWM_EADCPSC0_EADCPSC1_Msk (0xful << EPWM_EADCPSC0_EADCPSC1_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC1 Mask */ + +#define EPWM_EADCPSC0_EADCPSC2_Pos (16) /*!< EPWM_T::EADCPSC0: EADCPSC2 Position */ +#define EPWM_EADCPSC0_EADCPSC2_Msk (0xful << EPWM_EADCPSC0_EADCPSC2_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC2 Mask */ + +#define EPWM_EADCPSC0_EADCPSC3_Pos (24) /*!< EPWM_T::EADCPSC0: EADCPSC3 Position */ +#define EPWM_EADCPSC0_EADCPSC3_Msk (0xful << EPWM_EADCPSC0_EADCPSC3_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC3 Mask */ + +#define EPWM_EADCPSC1_EADCPSC4_Pos (0) /*!< EPWM_T::EADCPSC1: EADCPSC4 Position */ +#define EPWM_EADCPSC1_EADCPSC4_Msk (0xful << EPWM_EADCPSC1_EADCPSC4_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC4 Mask */ + +#define EPWM_EADCPSC1_EADCPSC5_Pos (8) /*!< EPWM_T::EADCPSC1: EADCPSC5 Position */ +#define EPWM_EADCPSC1_EADCPSC5_Msk (0xful << EPWM_EADCPSC1_EADCPSC5_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC5 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT0_Pos (0) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Position */ +#define EPWM_EADCPSCNT0_PSCNT0_Msk (0xful << EPWM_EADCPSCNT0_PSCNT0_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT1_Pos (8) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Position */ +#define EPWM_EADCPSCNT0_PSCNT1_Msk (0xful << EPWM_EADCPSCNT0_PSCNT1_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT2_Pos (16) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Position */ +#define EPWM_EADCPSCNT0_PSCNT2_Msk (0xful << EPWM_EADCPSCNT0_PSCNT2_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Mask */ + +#define EPWM_EADCPSCNT0_PSCNT3_Pos (24) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Position */ +#define EPWM_EADCPSCNT0_PSCNT3_Msk (0xful << EPWM_EADCPSCNT0_PSCNT3_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Mask */ + +#define EPWM_EADCPSCNT1_PSCNT4_Pos (0) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Position */ +#define EPWM_EADCPSCNT1_PSCNT4_Msk (0xful << EPWM_EADCPSCNT1_PSCNT4_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Mask */ + +#define EPWM_EADCPSCNT1_PSCNT5_Pos (8) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Position */ +#define EPWM_EADCPSCNT1_PSCNT5_Msk (0xful << EPWM_EADCPSCNT1_PSCNT5_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Mask */ + +#define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */ +#define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */ + +#define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */ +#define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */ + +#define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */ +#define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */ + +#define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */ +#define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */ + +#define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */ +#define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */ + +#define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */ +#define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */ + +#define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */ +#define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */ + +#define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */ +#define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */ + +#define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */ +#define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */ + +#define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */ +#define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */ + +#define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */ +#define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */ + +#define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */ +#define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */ + +#define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */ +#define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */ + +#define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */ +#define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */ + +#define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */ +#define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */ + +#define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */ +#define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */ + +#define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */ +#define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */ + +#define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */ +#define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */ + +#define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */ +#define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */ + +#define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */ +#define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */ + +#define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */ +#define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */ + +#define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */ +#define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */ + +#define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */ +#define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */ + +#define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */ +#define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */ + +#define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */ +#define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */ + +#define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */ +#define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */ + +#define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */ +#define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */ + +#define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */ +#define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */ + +#define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */ +#define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */ + +#define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */ +#define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */ + +#define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */ +#define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */ + +#define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */ +#define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */ + +#define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */ +#define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */ + +#define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */ +#define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */ + +#define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */ +#define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */ + +#define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */ +#define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */ + +#define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */ +#define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */ + +#define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */ +#define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */ + +#define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */ +#define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */ + +#define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */ +#define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */ + +#define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */ +#define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */ + +#define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */ +#define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */ + +#define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */ +#define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */ + +#define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */ +#define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */ + +#define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */ +#define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */ + +#define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */ +#define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */ + +#define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */ +#define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */ + +#define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */ +#define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */ + +#define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */ +#define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */ + +#define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */ +#define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */ + +#define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */ +#define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */ + +#define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */ +#define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */ + +#define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */ +#define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */ + +#define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */ +#define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */ + +#define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */ +#define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */ + +#define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */ +#define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */ + +#define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */ +#define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */ + +#define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */ +#define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */ + +#define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */ +#define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */ + +#define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */ +#define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */ + +#define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */ +#define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */ + +#define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */ +#define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */ + +#define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */ +#define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */ + +#define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */ +#define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */ + +#define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */ +#define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */ + +#define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */ +#define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */ + +#define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */ +#define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */ + +#define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */ +#define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */ + +#define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */ +#define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */ + +#define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */ +#define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */ + +#define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */ +#define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */ + +#define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */ +#define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */ + +#define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */ +#define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */ + +#define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */ +#define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */ + +#define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */ +#define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */ + +#define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */ +#define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */ + +#define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */ +#define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */ + +#define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */ +#define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */ + +#define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */ +#define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */ + +#define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */ +#define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */ + +#define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */ +#define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */ + +#define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */ +#define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */ + +#define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */ +#define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */ + +#define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */ +#define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */ + +#define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */ +#define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */ + +#define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */ +#define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */ + +#define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */ +#define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */ + +#define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */ +#define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */ + +#define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */ +#define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */ + +#define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */ +#define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */ + +#define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */ +#define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */ + +#define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */ +#define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */ + +#define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */ +#define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */ + +#define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */ +#define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */ + +#define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */ +#define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */ + +#define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */ +#define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */ + +#define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */ +#define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */ + +#define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */ +#define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */ + +#define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */ +#define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */ + +#define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */ +#define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */ + +#define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */ +#define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */ + +#define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */ +#define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */ + +#define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */ +#define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */ + +#define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */ +#define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */ + +#define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */ +#define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */ + +#define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position */ +#define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask */ + +#define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position */ +#define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask */ + +#define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position */ +#define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask */ + +#define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */ +#define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */ + +#define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */ +#define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */ + +#define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */ +#define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */ + +#define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */ +#define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */ + +#define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */ +#define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */ + +#define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */ +#define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */ + +#define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */ +#define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */ + +#define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */ +#define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */ + +#define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */ +#define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */ + +/**@}*/ /* EPWM_CONST */ +/**@}*/ /* end of EPWM register group */ +/**@}*/ /* end of REGISTER group */ + + + +#endif /* __EPWM_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ewdt_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ewdt_reg.h new file mode 100644 index 0000000000..090ed241bb --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ewdt_reg.h @@ -0,0 +1,178 @@ +/**************************************************************************//** + * @file ewdt_reg.h + * @version V1.00 + * @brief EWDT register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EWDT_REG_H__ +#define __EWDT_REG_H__ + +/** + @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Extra Watch Dog Timer Controller -------------------------*/ +/** + @addtogroup EWDT Extra Watch Dog Timer Controller(EWDT) + Memory Mapped Structure for EWDT Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var EWDT_T::CTL + * Offset: 0x00 EWDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RSTEN |EWDT Time-out Reset Enable Control (Write Protect) + * | | |Setting this bit will enable the EWDT time-out reset system function If the EWDT up counter value has not been cleared after the specific EWDT reset delay period expires. + * | | |0 = EWDT time-out reset system function Disabled. + * | | |1 = EWDT time-out reset system function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |RSTF |EWDT Time-out Reset Flag + * | | |This bit indicates the system has been reset by EWDT time-out reset system event or not. + * | | |0 = EWDT time-out reset system event did not occur. + * | | |1 = EWDT time-out reset system event has been occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |IF |EWDT Time-out Interrupt Flag + * | | |This bit will set to 1 while EWDT up counter value reaches the selected EWDT time-out interval + * | | |0 = EWDT time-out interrupt event interrupt did not occur. + * | | |1 = EWDT time-out interrupt interrupt event occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[4] |WKEN |EWDT Time-out Wake-up Function Control (Write Protect) + * | | |If this bit is set to 1, while EWDT time-out interrupt flag IF (EWDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (EWDT_CTL[6]) is enabled, the EWDT time-out interrupt signal will generate a event to trigger CPU wake-up trigger event to chip. + * | | |0 = Trigger Wake-up trigger event function Disabled if EWDT time-out interrupt signal generated. + * | | |1 = Trigger Wake-up trigger event function Enabled if EWDT time-out interrupt signal generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: Chip can be woken-up by while EWDT time-out interrupt signal generated only if EWDT clock source is selected to LIRC or LXT (32 kHz). + * |[5] |WKF |EWDT Time-out Wake-up Flag (Write Protect) + * | | |This bit indicates the EWDT time-out event has triggered interrupt chip wake-up or not.flag status of EWDT + * | | |0 = WDT does not cause chip wake-up. + * | | |1 = Chip wake-up from Idle or Power-down mode if when WDT time-out interrupt signal is generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect) + * | | |If this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and the WDT time-out interrupt signal is generated and inform to CPU. + * | | |0 = WDT time-out interrupt Disabled. + * | | |1 = WDT time-out interrupt Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |WDTEN |WDT Enable Control (Write Protect) + * | | |0 = Set WDT counter stop Disabled, and (This action will reset the internal up counter value will be reset also). + * | | |1 = Set WDT counter start Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enable/disable command is completed or not. + * | | |Note32: If CWDTEN[2:0] (combined by with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0. + * | | |Note3: This bit disabled needs 2 * WDT_CLK. + * |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) + * | | |These three bits select the time-out interval period after for the WDT starts counting. + * | | |000 = 2^4 * WDT_CLK. + * | | |001 = 2^6 * WDT_CLK. + * | | |010 = 2^8 * WDT_CLK. + * | | |011 = 2^10 * WDT_CLK. + * | | |100 = 2^12 * WDT_CLK. + * | | |101 = 2^14 * WDT_CLK. + * | | |110 = 2^16 * WDT_CLK. + * | | |111 = 2^18 * WDT_CLK. + * | | |111 = 2^20 * WDT_CLK. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[30] |SYNC |WDT Enable Control SYNC SYNC Flag Indicator (Read Only) + * | | |If use to synchronization, software er can check execute enable/disable this flag after enable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is become completed or not active or not.. + * | | |SYNC delay is + * | | |0 = Set WDTEN bit is WDT enable control synccompletedhronizing is completion. + * | | |1 = Set WDTEN bit WDT enable control is synchronizing and not become active yet.. + * | | |Note: Perform enable or disable WDTEN bit + * | | |This bit enabled needs 2 * WDT_CLK period to become active. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgment affects WDT counting. + * | | |WDT up counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgment Disabled. + * | | |WDT up counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var EWDT_T::ALTCTL + * Offset: 0x04 EWDT Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RSTDSEL |WDT Reset Delay Period Selection (Write Protect) + * | | |When WDT time-out event happened, user has a time named WDT Reset Delay Period to clear execute WDT counter by setting RSTCNT (WDT_CTL[0]) reset to prevent WDT time-out reset system occurred happened + * | | |User can select a suitable setting of RSTDSEL for different application program WDT Reset Delay Period. + * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. + * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. + * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. + * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This register will be reset to 0 if WDT time-out reset system event occurred happened. + * @var EWDT_T::RSTCNT + * Offset: 0x08 EWDT Reset Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RSTCNT |WDT Reset Counter Register + * | | |Writing 0x00005AA5 to this register field will reset the internal 18-bit WDT up counter value to 0. + * | | |Note: This WDT_RSTCNT is not write protected, but this RSTCNT (WDT_CTL[0]) is write protected. + * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. + */ + __IO uint32_t CTL; /*!< [0x0000] EWDT Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0004] EWDT Alternative Control Register */ + __O uint32_t RSTCNT; /*!< [0x0008] EWDT Reset Counter Register */ + +} EWDT_T; + +/** + @addtogroup EWDT_CONST WDT Bit Field Definition + Constant Definitions for EWDT Controller + @{ +*/ + +#define EWDT_CTL_RSTEN_Pos (1) /*!< EWDT_T::CTL: RSTEN Position */ +#define EWDT_CTL_RSTEN_Msk (0x1ul << EWDT_CTL_RSTEN_Pos) /*!< EWDT_T::CTL: RSTEN Mask */ + +#define EWDT_CTL_RSTF_Pos (2) /*!< EWDT_T::CTL: RSTF Position */ +#define EWDT_CTL_RSTF_Msk (0x1ul << EWDT_CTL_RSTF_Pos) /*!< EWDT_T::CTL: RSTF Mask */ + +#define EWDT_CTL_IF_Pos (3) /*!< EWDT_T::CTL: IF Position */ +#define EWDT_CTL_IF_Msk (0x1ul << EWDT_CTL_IF_Pos) /*!< EWDT_T::CTL: IF Mask */ + +#define EWDT_CTL_WKEN_Pos (4) /*!< EWDT_T::CTL: WKEN Position */ +#define EWDT_CTL_WKEN_Msk (0x1ul << EWDT_CTL_WKEN_Pos) /*!< EWDT_T::CTL: WKEN Mask */ + +#define EWDT_CTL_WKF_Pos (5) /*!< EWDT_T::CTL: WKF Position */ +#define EWDT_CTL_WKF_Msk (0x1ul << EWDT_CTL_WKF_Pos) /*!< EWDT_T::CTL: WKF Mask */ + +#define EWDT_CTL_INTEN_Pos (6) /*!< EWDT_T::CTL: INTEN Position */ +#define EWDT_CTL_INTEN_Msk (0x1ul << EWDT_CTL_INTEN_Pos) /*!< EWDT_T::CTL: INTEN Mask */ + +#define EWDT_CTL_WDTEN_Pos (7) /*!< EWDT_T::CTL: WDTEN Position */ +#define EWDT_CTL_WDTEN_Msk (0x1ul << EWDT_CTL_WDTEN_Pos) /*!< EWDT_T::CTL: WDTEN Mask */ + +#define EWDT_CTL_TOUTSEL_Pos (8) /*!< EWDT_T::CTL: TOUTSEL Position */ +#define EWDT_CTL_TOUTSEL_Msk (0xful << EWDT_CTL_TOUTSEL_Pos) /*!< EWDT_T::CTL: TOUTSEL Mask */ + +#define EWDT_CTL_SYNC_Pos (30) /*!< EWDT_T::CTL: SYNC Position */ +#define EWDT_CTL_SYNC_Msk (0x1ul << EWDT_CTL_SYNC_Pos) /*!< EWDT_T::CTL: SYNC Mask */ + +#define EWDT_CTL_ICEDEBUG_Pos (31) /*!< EWDT_T::CTL: ICEDEBUG Position */ +#define EWDT_CTL_ICEDEBUG_Msk (0x1ul << EWDT_CTL_ICEDEBUG_Pos) /*!< EWDT_T::CTL: ICEDEBUG Mask */ + +#define EWDT_ALTCTL_RSTDSEL_Pos (0) /*!< EWDT_T::ALTCTL: RSTDSEL Position */ +#define EWDT_ALTCTL_RSTDSEL_Msk (0x3ul << EWDT_ALTCTL_RSTDSEL_Pos) /*!< EWDT_T::ALTCTL: RSTDSEL Mask */ + +#define EWDT_RSTCNT_RSTCNT_Pos (0) /*!< EWDT_T::RSTCNT: RSTCNT Position */ +#define EWDT_RSTCNT_RSTCNT_Msk (0xfffffffful << EWDT_RSTCNT_RSTCNT_Pos) /*!< EWDT_T::RSTCNT: RSTCNT Mask */ + + +/**@}*/ /* EWDT_CONST */ +/**@}*/ /* end of EWDT register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __EWDT_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ewwdt_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ewwdt_reg.h new file mode 100644 index 0000000000..ce0d94e664 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ewwdt_reg.h @@ -0,0 +1,148 @@ +/**************************************************************************//** + * @file ewwdt_reg.h + * @version V1.00 + * @brief EWWDT register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EWWDT_REG_H__ +#define __EWWDT_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Extra Window Watchdog Timer -------------------------*/ +/** + @addtogroup EWWDT Extra Window Watchdog Timer(EWWDT) + Memory Mapped Structure for EWWDT Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var EWWDT_T::RLDCNT + * Offset: 0x00 WWDT Reload Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RLDCNT |WWDT Reload Counter Register + * | | |Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. + * | | |Note1: User can only write execute WWDT_RLDCNT register to the reload WWDT counter value command when current current WWDT counter value CNTDAT (WWDT_CNT[5:0]) is between 10 and CMPDAT (WWDT_CTL[21:16]) + * | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current current CNTDATWWDT counter value is larger than CMPDAT, WWDT reset signal system event will be generated immediately. + * | | |Note2: Execute WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also. + * @var EWWDT_T::CTL + * Offset: 0x04 WWDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTEN |WWDT Enable Control Bit + * | | |Set this bit to enable start WWDT counter counting. + * | | |0 = WWDT counter is stopped. + * | | |1 = WWDT counter is starting counting. + * |[1] |INTEN |WWDT Interrupt Enable Control Bit + * | | |If this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU. + * | | |0 = WWDT counter compare match interrupt Disabled. + * | | |1 = WWDT counter compare match interrupt Enabled. + * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection + * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK. + * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK. + * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK. + * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK. + * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK. + * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK. + * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK. + * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK. + * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK. + * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK. + * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK. + * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. + * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. + * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. + * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. + * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK. + * |[21:16] |CMPDAT |WWDT Window Compare Register Value + * | | |Set this register field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated.. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT CNTDAT (WWDT_CNT[5:]) is counter value between 10 and CMPDAT + * | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current WWDT counter value CNTDAT is larger than CMPDAT, WWDT reset system event signal will be generated immediately. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control + * | | |0 = ICE debug mode acknowledgment effects WWDT counter counting. + * | | |WWDT down counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgment Disabled. + * | | |WWDT down counter will keep going counting no matter CPU is held by ICE or not. + * @var EWWDT_T::STATUS + * Offset: 0x08 WWDT Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag + * | | |This bit indicates the that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16])interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). + * | | |0 = No effect. + * | | |1 = WWDT WWDT CNTDAT counter value matches the CMPDAT. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WWDTRF |WWDT Timer-out Reset System Flag + * | | |If this bit is set to 1, it This bit indicates the that system has been reset by WWDT counter time-out reset system event.or not. + * | | |0 = WWDT time-out reset system event did not occur. + * | | |1 = WWDT time-out reset system event occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var EWWDT_T::CNT + * Offset: 0x0C WWDT Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CNTDAT |WWDT Counter Value + * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. + */ + __O uint32_t RLDCNT; /*!< [0x0000] EWWDT Reload Counter Register */ + __IO uint32_t CTL; /*!< [0x0004] EWWDT Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] EWWDT Status Register */ + __I uint32_t CNT; /*!< [0x000c] EWWDT Counter Value Register */ + +} EWWDT_T; + + +/** + @addtogroup WWDT_CONST WWDT Bit Field Definition + Constant Definitions for WWDT Controller + @{ +*/ + +#define EWWDT_RLDCNT_RLDCNT_Pos (0) /*!< EWWDT_T::RLDCNT: RLDCNT Position */ +#define EWWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << EWWDT_RLDCNT_RLDCNT_Pos) /*!< EWWDT_T::RLDCNT: RLDCNT Mask */ + +#define EWWDT_CTL_WWDTEN_Pos (0) /*!< EWWDT_T::CTL: WWDTEN Position */ +#define EWWDT_CTL_WWDTEN_Msk (0x1ul << EWWDT_CTL_WWDTEN_Pos) /*!< EWWDT_T::CTL: WWDTEN Mask */ + +#define EWWDT_CTL_INTEN_Pos (1) /*!< EWWDT_T::CTL: INTEN Position */ +#define EWWDT_CTL_INTEN_Msk (0x1ul << EWWDT_CTL_INTEN_Pos) /*!< EWWDT_T::CTL: INTEN Mask */ + +#define EWWDT_CTL_PSCSEL_Pos (8) /*!< EWWDT_T::CTL: PSCSEL Position */ +#define EWWDT_CTL_PSCSEL_Msk (0xful << EWWDT_CTL_PSCSEL_Pos) /*!< EWWDT_T::CTL: PSCSEL Mask */ + +#define EWWDT_CTL_CMPDAT_Pos (16) /*!< EWWDT_T::CTL: CMPDAT Position */ +#define EWWDT_CTL_CMPDAT_Msk (0x3ful << EWWDT_CTL_CMPDAT_Pos) /*!< EWWDT_T::CTL: CMPDAT Mask */ + +#define EWWDT_CTL_ICEDEBUG_Pos (31) /*!< EWWDT_T::CTL: ICEDEBUG Position */ +#define EWWDT_CTL_ICEDEBUG_Msk (0x1ul << EWWDT_CTL_ICEDEBUG_Pos) /*!< EWWDT_T::CTL: ICEDEBUG Mask */ + +#define EWWDT_STATUS_WWDTIF_Pos (0) /*!< EWWDT_T::STATUS: WWDTIF Position */ +#define EWWDT_STATUS_WWDTIF_Msk (0x1ul << EWWDT_STATUS_WWDTIF_Pos) /*!< EWWDT_T::STATUS: WWDTIF Mask */ + +#define EWWDT_STATUS_WWDTRF_Pos (1) /*!< EWWDT_T::STATUS: WWDTRF Position */ +#define EWWDT_STATUS_WWDTRF_Msk (0x1ul << EWWDT_STATUS_WWDTRF_Pos) /*!< EWWDT_T::STATUS: WWDTRF Mask */ + +#define EWWDT_CNT_CNTDAT_Pos (0) /*!< EWWDT_T::CNT: CNTDAT Position */ +#define EWWDT_CNT_CNTDAT_Msk (0x3ful << EWWDT_CNT_CNTDAT_Pos) /*!< EWWDT_T::CNT: CNTDAT Mask */ + +/**@}*/ /* EWWDT_CONST */ +/**@}*/ /* end of EWWDT register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __EWWDT_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/fmc_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/fmc_reg.h new file mode 100644 index 0000000000..d5a8e64fa1 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/fmc_reg.h @@ -0,0 +1,634 @@ +/**************************************************************************//** + * @file fmc_reg.h + * @version V1.00 + * @brief FMC register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __FMC_REG_H__ +#define __FMC_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Flash Memory Controller -------------------------*/ +/** + @addtogroup FMC Flash Memory Controller(FMC) + Memory Mapped Structure for FMC Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var FMC_T::ISPCTL + * Offset: 0x00 ISP Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPEN |ISP Enable Bit (Write Protect) + * | | |ISP function enable bit. Set this bit to enable ISP function. + * | | |0 = ISP function Disabled. + * | | |1 = ISP function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |BS |Boot Select (Write Protect) + * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively + * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from + * | | |This bit is initiated with the inverse value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened + * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1. + * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |APUEN |APROM Update Enable Bit (Write Protect) + * | | |0 = APROM cannot be updated when the chip runs in APROM. + * | | |1 = APROM can be updated when the chip runs in APROM. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect) + * | | |0 = CONFIG cannot be updated. + * | | |1 = CONFIG can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect) + * | | |LDROM update enable bit. + * | | |0 = LDROM cannot be updated. + * | | |1 = LDROM can be updated. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |This bit needs to be cleared by writing 1 to it. + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) Page Erase command at LOCK mode with ICE connection + * | | |(5) Erase or Program command at brown-out detected + * | | |(6) Destination address is illegal, such as over an available range. + * | | |(7) Invalid ISP commands + * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1 + * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1 + * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1 + * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0 + * | | |(12) Read any content of boot loader with ICE connection + * | | |(13) The address of block erase and bank erase is not in APROM + * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command + * | | |(15) The wrong setting of page erase ISP CMD in XOM + * | | |(16) Violate XOM setting one time protection + * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page + * | | |(18) Mass erase when MERASE (CFG0[13]) is disable + * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |BL |Boot Loader Booting (Write Protect) + * | | |This bit is initiated with the inverses value of MBS (CONFIG0[5]) + * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded + * | | |This bit is used to check chip boot from Boot Loader or not + * | | |User should keep original value of this bit when updating FMC_ISPCTL register. + * | | |0 = Booting from APROM or LDROM. + * | | |1 = Booting from Boot Loader. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[24] |INTEN |Interrupt Enable (Write Protect) + * | | |0 = ISP INT Disabled. + * | | |1 = ISP INT Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. Before use INT, user need to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time. + * @var FMC_T::ISPADDR + * Offset: 0x04 ISP Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPADDR |ISP Address + * | | |The NuMicro M2355 series is equipped with embedded flash + * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation + * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. + * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 KBytes alignment is necessary for CRC32 checksum calculation. + * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte) + * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte). + * @var FMC_T::ISPDAT + * Offset: 0x08 ISP Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT |ISP Data + * | | |Write data to this register before ISP program operation. + * | | |Read data from this register after ISP read operation. + * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff + * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 2 KBytes alignment + * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result + * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect + * | | |For XOM page erase function, , ISPDAT = 0x0055_aa03. + * @var FMC_T::ISPCMD + * Offset: 0x0C ISP Command Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |CMD |ISP Command + * | | |ISP command table is shown below: + * | | |0x00= FLASH Read. + * | | |0x04= Read Unique ID. + * | | |0x08= Read Flash All-One Result. + * | | |0x0B= Read Company ID. + * | | |0x0C= Read Device ID. + * | | |0x0D= Read Checksum. + * | | |0x21= FLASH 32-bit Program. + * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP. + * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1. + * | | |0x25= FLASH Block Erase Erase four pages alignment of APROM in BANK0 or BANK1.. + * | | |0x27= FLASH Multi-Word Program. + * | | |0x28= Run Flash All-One Verification. + * | | |0x2D= Run Checksum Calculation. + * | | |0x2E= Vector Remap. + * | | |0x40= FLASH 64-bit Read. + * | | |0x61= FLASH 64-bit Program. + * | | |The other commands are invalid. + * @var FMC_T::ISPTRG + * Offset: 0x10 ISP Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPGO |ISP Start Trigger (Write Protect) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished + * | | |When ISPGO=1, the operation of accessing value from address FMC_BA+0x00 to FMC_BA+0x68 would halt CPU still ISPGO =0 + * | | |If user want to monitor whether ISP finish or not,user can access FMC_MPSTS[0] MPBUSY. + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::ISPSTS + * Offset: 0x40 ISP Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ISPBUSY |ISP Busy Flag (Read Only) + * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP operation is finished. + * | | |1 = ISP is progressed. + * |[2] |CBS |Boot Selection of CONFIG (Read Only) + * | | |This bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. + * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1. + * | | |0 = LDROM with IAP mode. + * | | |1 = APROM with IAP mode. + * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only) + * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened + * | | |0 = Booting from Boot Loader. + * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting) + * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only) + * | | |This bit is set if flash access cycle auto-tuning function is disabled + * | | |The auto-tuning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready. + * | | |0 = Flash access cycle auto-tuning is Enabled. + * | | |1 = Flash access cycle auto-tuning is Disabled. + * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only) + * | | |This bit is set if data is mismatched at ISP programming verification + * | | |This bit is clear by performing ISP flash erase or ISP read CID operation + * | | |0 = Flash Program is success. + * | | |1 = Flash Program is fail. Program data is different with data in the flash memory + * |[6] |ISPFF |ISP Fail Flag (Write Protect) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] if this bit is set. + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) Page Erase command at LOCK mode with ICE connection + * | | |(5) Erase or Program command at brown-out detected + * | | |(6) Destination address is illegal, such as over an available range. + * | | |(7) Invalid ISP commands + * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1 + * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1 + * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1 + * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0. + * | | |(12) Read any content of boot loader with ICE connection + * | | |(13) The address of block erase and bank erase is not in APROM + * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command + * | | |(15) The wrong setting of page erase ISP CMD in XOM + * | | |(16) Violate XOM setting one time protection + * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page + * | | |(18) Mass erase when MERASE (CFG0[13]) is disable + * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |ALLONE |Flash All-one Verification Flag + * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after Run Flash All-One Verification complete; this bit also can be clear by writing 1 + * | | |0 = All of flash bits are 1 after Run Flash All-One Verification complete. + * | | |1 = Flash bits are not all 1 after Run Flash All-One Verification complete. + * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only) + * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF} + * |[24] |INTFLAG |Interrupt Flag + * | | |0 = ISP is not finish. + * | | |1 = ISP done or ISPFF set. + * @var FMC_T::CYCCTL + * Offset: 0x4C Flash Access Cycle Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect) + * | | |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1). + * | | |When auto-tuning function disabled, user needs to check the speed of HCLK and set the cycle >0. + * | | |0000 = CPU access with zero wait cycle ; Flash access cycle is 1. The HCLK working frequency range is <27MHz; Cache is disabled by hardware. + * | | |0001 = CPU access with one wait cycle if cache miss; Flash access cycle is 1. The HCLK working frequency range range is<27MHz. + * | | |0010 = CPU access with two wait cycles if cache miss; Flash access cycle is 2. The optimized HCLK working frequency range is 25~52 MHz. + * | | |0011 = CPU access with three wait cycles if cache miss; Flash access cycle is 3. The optimized HCLK working frequency range is 49~79MHz. + * | | |Others = Reserved. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |FADIS |Flash Access Cycle Auto-tuning Disabled Control (Write Protect) + * | | |Set this bit to disable flash access cycle auto-tuning function + * | | |0 = Flash access cycle auto-tuning is enabled. + * | | |1 = Flash access cycle auto-tuning is disabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var FMC_T::MPDAT0 + * Offset: 0x80 ISP Data0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT0 |ISP Data 0 + * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data + * @var FMC_T::MPDAT1 + * Offset: 0x84 ISP Data1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT1 |ISP Data 1 + * | | |This register is the second 32-bit data for 64-bit/multi-word programming. + * @var FMC_T::MPDAT2 + * Offset: 0x88 ISP Data2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT2 |ISP Data 2 + * | | |This register is the third 32-bit data for multi-word programming. + * @var FMC_T::MPDAT3 + * Offset: 0x8C ISP Data3 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ISPDAT3 |ISP Data 3 + * | | |This register is the fourth 32-bit data for multi-word programming. + * @var FMC_T::MPSTS + * Offset: 0xC0 ISP Multi-Program Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only) + * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. + * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). + * | | |0 = ISP Multi-Word program operation is finished. + * | | |1 = ISP Multi-Word program operation is progressed. + * |[1] |PPGO |ISP Multi-program Status (Read Only) + * | | |0 = ISP multi-word program operation is not active. + * | | |1 = ISP multi-word program operation is in progress. + * |[2] |ISPFF |ISP Fail Flag (Read Only) + * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] + * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: + * | | |(1) APROM writes to itself if APUEN is set to 0. + * | | |(2) LDROM writes to itself if LDUEN is set to 0. + * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. + * | | |(4) Page Erase command at LOCK mode with ICE connection + * | | |(5) Erase or Program command at brown-out detected + * | | |(6) Destination address is illegal, such as over an available range. + * | | |(7) Invalid ISP commands + * |[4] |D0 |ISP DATA 0 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete. + * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete. + * |[5] |D1 |ISP DATA 1 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete. + * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete. + * |[6] |D2 |ISP DATA 2 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete. + * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete. + * |[7] |D3 |ISP DATA 3 Flag (Read Only) + * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete. + * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete. + * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete. + * @var FMC_T::MPADDR + * Offset: 0xC4 ISP Multi-Program Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |MPADDR |ISP Multi-word Program Address + * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. + * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete. + * @var FMC_T::XOMR0STS + * Offset: 0xD0 XOM Region 0 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SIZE |XOM Region 0 Size (Page-aligned) + * | | |SIZE is the page number of XOM Region 0. + * |[31:8] |BASE |XOM Region 0 Base Address (Page-aligned) + * | | |BASE is the base address of XOM Region 0. + * @var FMC_T::XOMR1STS + * Offset: 0xD4 XOM Region 1 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SIZE |XOM Region 1 Size (Page-aligned) + * | | |SIZE is the page number of XOM Region 1. + * |[31:8] |BASE |XOM Region 1 Base Address (Page-aligned) + * | | |BASE is the base address of XOM Region 1. + * @var FMC_T::XOMR2STS + * Offset: 0xD8 XOM Region 2 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SIZE |XOM Region 2 Size (Page-aligned) + * | | |SIZE is the page number of XOM Region 2. + * |[31:8] |BASE |XOM Region 2 Base Address (Page-aligned) + * | | |BASE is the base address of XOM Region 2. + * @var FMC_T::XOMR3STS + * Offset: 0xDC XOM Region 3 Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |SIZE |XOM Region 3 Size (Page-aligned) + * | | |SIZE is the page number of XOM Region 3. + * |[31:8] |BASE |XOM Region 3 Base Address (Page-aligned) + * | | |BASE is the base address of XOM Region 3. + * @var FMC_T::XOMSTS + * Offset: 0xE0 XOM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |XOMR0ON |XOM Region 0 On + * | | |XOM Region 0 active status. + * | | |0 = No active. + * | | |1 = XOM region 0 is active. + * |[1] |XOMR1ON |XOM Region 1 On + * | | |XOM Region 1 active status. + * | | |0 = No active. + * | | |1 = XOM region 1 is active. + * |[2] |XOMR2ON |XOM Region 2 On + * | | |XOM Region 2 active status. + * | | |0 = No active. + * | | |1 = XOM region 2 is active. + * |[3] |XOMR3ON |XOM Region 3 On + * | | |XOM Region 3 active status. + * | | |0 = No active. + * | | |1 = XOM region 3 is active. + * |[4] |XOMPEF |XOM Page Erase Function Fail + * | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again. + * | | |0 = Success. + * | | |1 = Fail. + */ + __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ + __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ + __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ + __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */ + __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ + __I uint32_t RESERVE0[11]; + __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ + __I uint32_t RESERVE1[2]; + __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */ + __I uint32_t RESERVE2[12]; + __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */ + __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */ + __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */ + __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */ + __I uint32_t RESERVE3[12]; + __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */ + __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */ + __I uint32_t RESERVE4[2]; + __I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */ + __I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */ + __I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */ + __I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */ + __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */ + __I uint32_t RESERVE5[7]; + __IO uint32_t DFCTL; /*!< [0x0100] Data Flash Function Control Register */ + __I uint32_t RESERVE6; + __IO uint32_t DFSTS; /*!< [0x0108] Data Flash Status Register */ + __O uint32_t SCRKEY; /*!< [0x010c] Data Flash Scrambling Key Register */ + +} FMC_T; + +/** + @addtogroup FMC_CONST FMC Bit Field Definition + Constant Definitions for FMC Controller + @{ +*/ + +#define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */ +#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */ + +#define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */ +#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */ + +#define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */ +#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */ + +#define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */ +#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */ + +#define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */ +#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */ + +#define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */ +#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */ + +#define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */ +#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */ + +#define FMC_ISPCTL_INTEN_Pos (24) /*!< FMC_T::ISPCTL: INTEN Position */ +#define FMC_ISPCTL_INTEN_Msk (0x1ul << FMC_ISPCTL_INTEN_Pos) /*!< FMC_T::ISPCTL: INTEN Mask */ + +#define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */ +#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */ + +#define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */ +#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ + +#define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */ +#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */ + +#define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */ +#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ + +#define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */ +#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */ + +#define FMC_ISPSTS_CBS_Pos (2) /*!< FMC_T::ISPSTS: CBS Position */ +#define FMC_ISPSTS_CBS_Msk (0x1ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */ + +#define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */ +#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */ + +#define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */ +#define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */ + +#define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */ +#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */ + +#define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */ +#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */ + +#define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */ +#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */ + +#define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */ +#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */ + +#define FMC_ISPSTS_INTFLAG_Pos (24) /*!< FMC_T::ISPSTS: INTFLAG Position */ +#define FMC_ISPSTS_INTFLAG_Msk (0x1ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Mask */ + +#define FMC_ISPSTS_ISPCERR_Pos (28) /*!< FMC_T::ISPSTS: ISPCERR Position */ +#define FMC_ISPSTS_ISPCERR_Msk (0x1ul << FMC_ISPSTS_ISPCERR_Pos) /*!< FMC_T::ISPSTS: ISPCERR Mask */ + +#define FMC_ISPSTS_MIRBOUND_Pos (29) /*!< FMC_T::ISPSTS: MIRBOUND Position */ +#define FMC_ISPSTS_MIRBOUND_Msk (0x1ul << FMC_ISPSTS_MIRBOUND_Pos) /*!< FMC_T::ISPSTS: MIRBOUND Mask */ + +#define FMC_ISPSTS_FBS_Pos (30) /*!< FMC_T::ISPSTS: FBS Position */ +#define FMC_ISPSTS_FBS_Msk (0x1ul << FMC_ISPSTS_FBS_Pos) /*!< FMC_T::ISPSTS: FBS Mask */ + +#define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */ +#define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */ + +#define FMC_CYCCTL_FADIS_Pos (8) /*!< FMC_T::CYCCTL: FADIS Position */ +#define FMC_CYCCTL_FADIS_Msk (0x1ul << FMC_CYCCTL_FADIS_Pos) /*!< FMC_T::CYCCTL: FADIS Mask */ + +#define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */ +#define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */ + +#define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */ +#define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */ + +#define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */ +#define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */ + +#define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */ +#define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */ + +#define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */ +#define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */ + +#define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */ +#define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */ + +#define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */ +#define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */ + +#define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */ +#define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */ + +#define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */ +#define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */ + +#define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */ +#define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */ + +#define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */ +#define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */ + +#define FMC_KPKEYSTS_SBKPBUSY_Pos (8) /*!< FMC_T::KPKEYSTS: SBKPBUSY Position */ +#define FMC_KPKEYSTS_SBKPBUSY_Msk (0x1ul << FMC_KPKEYSTS_SBKPBUSY_Pos) /*!< FMC_T::KPKEYSTS: SBKPBUSY Mask */ + +#define FMC_KPKEYSTS_SBKPFLAG_Pos (9) /*!< FMC_T::KPKEYSTS: SBKPFLAG Position */ +#define FMC_KPKEYSTS_SBKPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SBKPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SBKPFLAG Mask */ + +#define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */ +#define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */ + +#define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */ +#define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */ + +#define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */ +#define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */ + +#define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */ +#define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */ + +#define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */ +#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */ + +#define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */ +#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */ + +#define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */ +#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */ + +#define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */ +#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */ + +#define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */ +#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */ + +#define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */ +#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */ + +#define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */ +#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */ + +#define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */ +#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */ + +#define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */ +#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */ + +#define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */ +#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */ + +#define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */ +#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */ + +#define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */ +#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */ + +#define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */ +#define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */ + +#define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */ +#define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */ + +#define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */ +#define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */ + +#define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */ +#define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */ + +#define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */ +#define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */ + +#define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */ +#define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOMR2STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */ + +#define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */ +#define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */ + +#define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */ +#define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */ + +#define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */ +#define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */ + +#define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */ +#define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */ + +#define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */ +#define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */ + +#define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */ +#define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */ + +#define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */ +#define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */ + +#define FMC_DFCTL_SCRAMEN_Pos (0) /*!< FMC_T::DFCTL: SCRAMEN Position */ +#define FMC_DFCTL_SCRAMEN_Msk (0x1ul << FMC_DFCTL_SCRAMEN_Pos) /*!< FMC_T::DFCTL: SCRAMEN Mask */ + +#define FMC_DFCTL_SILENTEN_Pos (1) /*!< FMC_T::DFCTL: SILENTEN Position */ +#define FMC_DFCTL_SILENTEN_Msk (0x1ul << FMC_DFCTL_SILENTEN_Pos) /*!< FMC_T::DFCTL: SILENTEN Mask */ + +#define FMC_DFSTS_TMPCLRDONE_Pos (0) /*!< FMC_T::DFSTS: TMPCLRDONE Position */ +#define FMC_DFSTS_TMPCLRDONE_Msk (0x1ul << FMC_DFSTS_TMPCLRDONE_Pos) /*!< FMC_T::DFSTS: TMPCLRDONE Mask */ + +#define FMC_DFSTS_TMPCLRBUSY_Pos (1) /*!< FMC_T::DFSTS: TMPCLRBUSY Position */ +#define FMC_DFSTS_TMPCLRBUSY_Msk (0x1ul << FMC_DFSTS_TMPCLRBUSY_Pos) /*!< FMC_T::DFSTS: TMPCLRBUSY Mask */ + +#define FMC_SCRKEY_SCRKEY_Pos (0) /*!< FMC_T::SCRKEY: SCRKEY Position */ +#define FMC_SCRKEY_SCRKEY_Msk (0xfffffffful << FMC_SCRKEY_SCRKEY_Pos) /*!< FMC_T::SCRKEY: SCRKEY Mask */ + +/**@}*/ /* FMC_CONST */ +/**@}*/ /* end of FMC register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __FMC_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/gpio_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/gpio_reg.h new file mode 100644 index 0000000000..0fbe522598 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/gpio_reg.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file gpio_reg.h + * @version V1.00 + * @brief GPIO register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __GPIO_REG_H__ +#define __GPIO_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- General Purpose Input/Output Controller -------------------------*/ +/** + @addtogroup GPIO General Purpose Input/Output Controller(GPIO) + Memory Mapped Structure for GPIO Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var GPIO_T::MODE + * Offset: 0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0 PA-H I/O Mode Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|MODEn |Port A-H I/O Pin[n] Mode Control + * | | |Determine each I/O mode of Px.n pins. + * | | |00 = Px.n is in Input mode. + * | | |01 = Px.n is in Push-pull Output mode. + * | | |10 = Px.n is in Open-drain Output mode. + * | | |11 = Px.n is in Quasi-bidirectional mode. + * | | |Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]). + * | | |If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on. + * | | |If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be input mode after chip powered on. + * | | |Note 2: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::DINOFF + * Offset: 0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4 PA-H Digital Input Path Disable Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n+16] |DINOFFn |Port A-H Pin[n] Digital Input Path Disable Control + * | | |Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. + * | | |If input is analog signal, users can disable Px.n digital input path to avoid input current leakage. + * | | |0 = Px.n digital input path Enabled. + * | | |1 = Px.n digital input path Disabled (digital input tied to low). + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::DOUT + * Offset: 0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8 PA-H Data Output Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DOUTn |Port A-H Pin[n] Output Value + * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode. + * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::DATMSK + * Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC PA-H Data Output Write Mask + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DATMSKn |Port A-H Pin[n] Data Output Write Mask + * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. + * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected. + * | | |If the write signal is masked, writing data to the protect bit is ignored. + * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. + * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected. + * | | |Note 1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit. + * | | |Note 2: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::PIN + * Offset: 0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0 PA-H Pin Value + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |PINn |Port A-H Pin[n] Pin Value + * | | |Each bit of the register reflects the actual status of the respective Px.n pin. + * | | |0 = The corresponding pin status is low. + * | | |1 = The corresponding pin status is high. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::DBEN + * Offset: 0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4 PA-H De-Bounce Enable Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |DBENn |Port A-H Pin[n] Input Signal De-bounce Enable Bit + * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. + * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. + * | | |The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]). + * | | |0 = Px.n de-bounce function Disabled. + * | | |1 = Px.n de-bounce function Enabled. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::INTTYPE + * Offset: 0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8 PA-H Interrupt Trigger Type Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |TYPEn |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control + * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. + * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. + * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. + * | | |0 = Edge trigger interrupt. + * | | |1 = Level trigger interrupt. + * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]). + * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. + * | | |The de-bounce function is valid only for edge triggered interrupt. + * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::INTEN + * Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC PA-H Interrupt Enable Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |FLIENn |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit + * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. + * | | |If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low. + * | | |0 = Px.n level low or high to low interrupt Disabled. + * | | |1 = Px.n level low or high to low interrupt Enabled. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * |[n+16] |RHIENn |Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit + * | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. + * | | |Set bit to 1 also enable the pin wake-up function. + * | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : + * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. + * | | |If the interrupt is edge trigger (TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high. + * | | |0 = Px.n level high or low to high interrupt Disabled. + * | | |1 = Px.n level high or low to high interrupt Enabled. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::INTSRC + * Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0 PA-H Interrupt Source Flag + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |INTSRCn |Port A-H Pin[n] Interrupt Source Flag + * | | |Write Operation : + * | | |0 = No action. + * | | |1 = Clear the corresponding pending interrupt. + * | | |Read Operation : + * | | |0 = No interrupt at Px.n. + * | | |1 = Px.n generates an interrupt. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::SMTEN + * Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4 PA-H Input Schmitt Trigger Enable + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[n] |SMTENn |Port A-H Pin[n] Input Schmitt Trigger Enable Bit + * | | |0 = Px.n input Schmitt trigger function Disabled. + * | | |1 = Px.n input Schmitt trigger function Enabled. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::SLEWCTL + * Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8 PA-H High Slew Rate Control + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|HSRENn |Port A-H Pin[n] High Slew Rate Control + * | | |00 = Px.n output with normal slew rate mode (maximum 40 MHz at 2.7V). + * | | |01 = Px.n output with high slew rate mode (maximum 80 MHz at 2.7V). + * | | |10 = Px.n output with fast slew rate mode (maximum 100 MHz at 2.7V. + * | | |11 = Reserved. + * | | |Note: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::PUSEL + * Offset: 0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0 PA-H Pull-up and Pull-down Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2n+1:2n]|PUSELn |Port A-H Pin[n] Pull-up and Pull-down Enable Register + * | | |Determine each I/O Pull-up/pull-down of Px.n pins. + * | | |00 = Px.n pull-up and pull-down disabled. + * | | |01 = Px.n pull-up enabled. + * | | |10 = Px.n pull-down enabled. + * | | |11 = Px.n pull-up and pull-down disabled. + * | | |Note 1: + * | | |Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state and open-drain mode. + * | | |The independent pull-down control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state mode. + * | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode. + * | | |Note 2: The PC.14/ PC.15/ PD.13/ PD.15/ PF.12~15/ PG.0/ PG.1/ PG.5~8/ PH.0~3/ PH.12~15 pin is ignored. + * @var GPIO_T::DBCTL + * Offset: 0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4 PA-H Interrupt De-bounce Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DBCLKSEL |De-bounce Sampling Cycle Selection + * | | |0000 = Sample interrupt input once per 1 clocks. + * | | |0001 = Sample interrupt input once per 2 clocks. + * | | |0010 = Sample interrupt input once per 4 clocks. + * | | |0011 = Sample interrupt input once per 8 clocks. + * | | |0100 = Sample interrupt input once per 16 clocks. + * | | |0101 = Sample interrupt input once per 32 clocks. + * | | |0110 = Sample interrupt input once per 64 clocks. + * | | |0111 = Sample interrupt input once per 128 clocks. + * | | |1000 = Sample interrupt input once per 256 clocks. + * | | |1001 = Sample interrupt input once per 2*256 clocks. + * | | |1010 = Sample interrupt input once per 4*256 clocks. + * | | |1011 = Sample interrupt input once per 8*256 clocks. + * | | |1100 = Sample interrupt input once per 16*256 clocks. + * | | |1101 = Sample interrupt input once per 32*256 clocks. + * | | |1110 = Sample interrupt input once per 64*256 clocks. + * | | |1111 = Sample interrupt input once per 128*256 clocks. + * |[4] |DBCLKSRC |De-bounce Counter Clock Source Selection + * | | |0 = De-bounce counter clock source is the HCLK. + * | | |1 = De-bounce counter clock source is the 32 kHz internal low speed RC oscillator (LIRC). + * |[5] |ICLKON |Interrupt Clock on Mode + * | | |0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1. + * | | |1 = All I/O pins edge detection circuit is always active after reset. + * | | |Note: It is recommended to disable this bit to save system power if no special application concern. + */ + + + __IO uint32_t MODE; /*!< [0x00/0x40/0x80/0xC0/0x100/0x140/0x180/0x1C0] Port A-H I/O Mode Control */ + __IO uint32_t DINOFF; /*!< [0x04/0x44/0x84/0xC4/0x104/0x144/0x184/0x1C4] Port A-H Digital Input Path Disable Control */ + __IO uint32_t DOUT; /*!< [0x08/0x48/0x88/0xC8/0x108/0x148/0x188/0x1C8] Port A-H Data Output Value */ + __IO uint32_t DATMSK; /*!< [0x0C/0x4C/0x8C/0xCC/0x10C/0x14C/0x18C/0x1CC] Port A-H Data Output Write Mask */ + __I uint32_t PIN; /*!< [0x10/0x50/0x90/0xD0/0x110/0x150/0x190/0x1D0] Port A-H Pin Value */ + __IO uint32_t DBEN; /*!< [0x14/0x54/0x94/0xD4/0x114/0x154/0x194/0x1D4] Port A-H De-Bounce Enable Control */ + __IO uint32_t INTTYPE; /*!< [0x18/0x58/0x98/0xD8/0x118/0x158/0x198/0x1D8] Port A-H Interrupt Trigger Type Control */ + __IO uint32_t INTEN; /*!< [0x1C/0x5C/0x9C/0xDC/0x11C/0x15C/0x19C/0x1DC] Port A-H Interrupt Enable Control */ + __IO uint32_t INTSRC; /*!< [0x20/0x60/0xA0/0xE0/0x120/0x160/0x1A0/0x1E0] Port A-H Interrupt Source Flag */ + __IO uint32_t SMTEN; /*!< [0x24/0x64/0xA4/0xE4/0x124/0x164/0x1A4/0x1E4] Port A-H Input Schmitt Trigger Enable */ + __IO uint32_t SLEWCTL; /*!< [0x28/0x68/0xA8/0xE8/0x128/0x168/0x1A8/0x1E8] Port A-H High Slew Rate Control */ + __I uint32_t RESERVE0[1]; + __IO uint32_t PUSEL; /*!< [0x30/0x70/0xB0/0xF0/0x130/0x170/0x1B0/0x1F0] Port A-H Pull-up and Pull-down Selection Register */ + __IO uint32_t DBCTL; /*!< [0x34/0x74/0xB4/0xF4/0x134/0x174/0x1B4/0x1F4] Port A-H Interrupt De-bounce Control */ + +} GPIO_T; + + + +/** + @addtogroup GPIO_CONST GPIO Bit Field Definition + Constant Definitions for GPIO Controller + @{ +*/ + +#define GPIO_MODE_MODE0_Pos (0) /*!< GPIO_T::MODE: MODE0 Position */ +#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO_T::MODE: MODE0 Mask */ + +#define GPIO_MODE_MODE1_Pos (2) /*!< GPIO_T::MODE: MODE1 Position */ +#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO_T::MODE: MODE1 Mask */ + +#define GPIO_MODE_MODE2_Pos (4) /*!< GPIO_T::MODE: MODE2 Position */ +#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO_T::MODE: MODE2 Mask */ + +#define GPIO_MODE_MODE3_Pos (6) /*!< GPIO_T::MODE: MODE3 Position */ +#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO_T::MODE: MODE3 Mask */ + +#define GPIO_MODE_MODE4_Pos (8) /*!< GPIO_T::MODE: MODE4 Position */ +#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO_T::MODE: MODE4 Mask */ + +#define GPIO_MODE_MODE5_Pos (10) /*!< GPIO_T::MODE: MODE5 Position */ +#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO_T::MODE: MODE5 Mask */ + +#define GPIO_MODE_MODE6_Pos (12) /*!< GPIO_T::MODE: MODE6 Position */ +#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO_T::MODE: MODE6 Mask */ + +#define GPIO_MODE_MODE7_Pos (14) /*!< GPIO_T::MODE: MODE7 Position */ +#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO_T::MODE: MODE7 Mask */ + +#define GPIO_MODE_MODE8_Pos (16) /*!< GPIO_T::MODE: MODE8 Position */ +#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO_T::MODE: MODE8 Mask */ + +#define GPIO_MODE_MODE9_Pos (18) /*!< GPIO_T::MODE: MODE9 Position */ +#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO_T::MODE: MODE9 Mask */ + +#define GPIO_MODE_MODE10_Pos (20) /*!< GPIO_T::MODE: MODE10 Position */ +#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO_T::MODE: MODE10 Mask */ + +#define GPIO_MODE_MODE11_Pos (22) /*!< GPIO_T::MODE: MODE11 Position */ +#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO_T::MODE: MODE11 Mask */ + +#define GPIO_MODE_MODE12_Pos (24) /*!< GPIO_T::MODE: MODE12 Position */ +#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO_T::MODE: MODE12 Mask */ + +#define GPIO_MODE_MODE13_Pos (26) /*!< GPIO_T::MODE: MODE13 Position */ +#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO_T::MODE: MODE13 Mask */ + +#define GPIO_MODE_MODE14_Pos (28) /*!< GPIO_T::MODE: MODE14 Position */ +#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO_T::MODE: MODE14 Mask */ + +#define GPIO_MODE_MODE15_Pos (30) /*!< GPIO_T::MODE: MODE15 Position */ +#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO_T::MODE: MODE15 Mask */ + +#define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO_T::DINOFF: DINOFF0 Position */ +#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO_T::DINOFF: DINOFF0 Mask */ + +#define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO_T::DINOFF: DINOFF1 Position */ +#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO_T::DINOFF: DINOFF1 Mask */ + +#define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO_T::DINOFF: DINOFF2 Position */ +#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO_T::DINOFF: DINOFF2 Mask */ + +#define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO_T::DINOFF: DINOFF3 Position */ +#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO_T::DINOFF: DINOFF3 Mask */ + +#define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO_T::DINOFF: DINOFF4 Position */ +#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO_T::DINOFF: DINOFF4 Mask */ + +#define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO_T::DINOFF: DINOFF5 Position */ +#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO_T::DINOFF: DINOFF5 Mask */ + +#define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO_T::DINOFF: DINOFF6 Position */ +#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO_T::DINOFF: DINOFF6 Mask */ + +#define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO_T::DINOFF: DINOFF7 Position */ +#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO_T::DINOFF: DINOFF7 Mask */ + +#define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO_T::DINOFF: DINOFF8 Position */ +#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO_T::DINOFF: DINOFF8 Mask */ + +#define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO_T::DINOFF: DINOFF9 Position */ +#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO_T::DINOFF: DINOFF9 Mask */ + +#define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO_T::DINOFF: DINOFF10 Position */ +#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO_T::DINOFF: DINOFF10 Mask */ + +#define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO_T::DINOFF: DINOFF11 Position */ +#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO_T::DINOFF: DINOFF11 Mask */ + +#define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO_T::DINOFF: DINOFF12 Position */ +#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO_T::DINOFF: DINOFF12 Mask */ + +#define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO_T::DINOFF: DINOFF13 Position */ +#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO_T::DINOFF: DINOFF13 Mask */ + +#define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO_T::DINOFF: DINOFF14 Position */ +#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO_T::DINOFF: DINOFF14 Mask */ + +#define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO_T::DINOFF: DINOFF15 Position */ +#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO_T::DINOFF: DINOFF15 Mask */ + +#define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO_T::DOUT: DOUT0 Position */ +#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO_T::DOUT: DOUT0 Mask */ + +#define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO_T::DOUT: DOUT1 Position */ +#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO_T::DOUT: DOUT1 Mask */ + +#define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO_T::DOUT: DOUT2 Position */ +#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO_T::DOUT: DOUT2 Mask */ + +#define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO_T::DOUT: DOUT3 Position */ +#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO_T::DOUT: DOUT3 Mask */ + +#define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO_T::DOUT: DOUT4 Position */ +#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO_T::DOUT: DOUT4 Mask */ + +#define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO_T::DOUT: DOUT5 Position */ +#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO_T::DOUT: DOUT5 Mask */ + +#define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO_T::DOUT: DOUT6 Position */ +#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO_T::DOUT: DOUT6 Mask */ + +#define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO_T::DOUT: DOUT7 Position */ +#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO_T::DOUT: DOUT7 Mask */ + +#define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO_T::DOUT: DOUT8 Position */ +#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO_T::DOUT: DOUT8 Mask */ + +#define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO_T::DOUT: DOUT9 Position */ +#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO_T::DOUT: DOUT9 Mask */ + +#define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO_T::DOUT: DOUT10 Position */ +#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO_T::DOUT: DOUT10 Mask */ + +#define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO_T::DOUT: DOUT11 Position */ +#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO_T::DOUT: DOUT11 Mask */ + +#define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO_T::DOUT: DOUT12 Position */ +#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO_T::DOUT: DOUT12 Mask */ + +#define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO_T::DOUT: DOUT13 Position */ +#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO_T::DOUT: DOUT13 Mask */ + +#define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO_T::DOUT: DOUT14 Position */ +#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO_T::DOUT: DOUT14 Mask */ + +#define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO_T::DOUT: DOUT15 Position */ +#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO_T::DOUT: DOUT15 Mask */ + +#define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO_T::DATMSK: DATMSK0 Position */ +#define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO_T::DATMSK: DATMSK0 Mask */ + +#define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO_T::DATMSK: DATMSK1 Position */ +#define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO_T::DATMSK: DATMSK1 Mask */ + +#define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO_T::DATMSK: DATMSK2 Position */ +#define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO_T::DATMSK: DATMSK2 Mask */ + +#define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO_T::DATMSK: DATMSK3 Position */ +#define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO_T::DATMSK: DATMSK3 Mask */ + +#define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO_T::DATMSK: DATMSK4 Position */ +#define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO_T::DATMSK: DATMSK4 Mask */ + +#define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO_T::DATMSK: DATMSK5 Position */ +#define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO_T::DATMSK: DATMSK5 Mask */ + +#define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO_T::DATMSK: DATMSK6 Position */ +#define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO_T::DATMSK: DATMSK6 Mask */ + +#define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO_T::DATMSK: DATMSK7 Position */ +#define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO_T::DATMSK: DATMSK7 Mask */ + +#define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO_T::DATMSK: DATMSK8 Position */ +#define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO_T::DATMSK: DATMSK8 Mask */ + +#define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO_T::DATMSK: DATMSK9 Position */ +#define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO_T::DATMSK: DATMSK9 Mask */ + +#define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO_T::DATMSK: DATMSK10 Position */ +#define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO_T::DATMSK: DATMSK10 Mask */ + +#define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO_T::DATMSK: DATMSK11 Position */ +#define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO_T::DATMSK: DATMSK11 Mask */ + +#define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO_T::DATMSK: DATMSK12 Position */ +#define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO_T::DATMSK: DATMSK12 Mask */ + +#define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO_T::DATMSK: DATMSK13 Position */ +#define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO_T::DATMSK: DATMSK13 Mask */ + +#define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO_T::DATMSK: DATMSK14 Position */ +#define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO_T::DATMSK: DATMSK14 Mask */ + +#define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO_T::DATMSK: DATMSK15 Position */ +#define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO_T::DATMSK: DATMSK15 Mask */ + +#define GPIO_PIN_PIN0_Pos (0) /*!< GPIO_T::PIN: PIN0 Position */ +#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO_T::PIN: PIN0 Mask */ + +#define GPIO_PIN_PIN1_Pos (1) /*!< GPIO_T::PIN: PIN1 Position */ +#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO_T::PIN: PIN1 Mask */ + +#define GPIO_PIN_PIN2_Pos (2) /*!< GPIO_T::PIN: PIN2 Position */ +#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO_T::PIN: PIN2 Mask */ + +#define GPIO_PIN_PIN3_Pos (3) /*!< GPIO_T::PIN: PIN3 Position */ +#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO_T::PIN: PIN3 Mask */ + +#define GPIO_PIN_PIN4_Pos (4) /*!< GPIO_T::PIN: PIN4 Position */ +#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO_T::PIN: PIN4 Mask */ + +#define GPIO_PIN_PIN5_Pos (5) /*!< GPIO_T::PIN: PIN5 Position */ +#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO_T::PIN: PIN5 Mask */ + +#define GPIO_PIN_PIN6_Pos (6) /*!< GPIO_T::PIN: PIN6 Position */ +#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO_T::PIN: PIN6 Mask */ + +#define GPIO_PIN_PIN7_Pos (7) /*!< GPIO_T::PIN: PIN7 Position */ +#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO_T::PIN: PIN7 Mask */ + +#define GPIO_PIN_PIN8_Pos (8) /*!< GPIO_T::PIN: PIN8 Position */ +#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO_T::PIN: PIN8 Mask */ + +#define GPIO_PIN_PIN9_Pos (9) /*!< GPIO_T::PIN: PIN9 Position */ +#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO_T::PIN: PIN9 Mask */ + +#define GPIO_PIN_PIN10_Pos (10) /*!< GPIO_T::PIN: PIN10 Position */ +#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO_T::PIN: PIN10 Mask */ + +#define GPIO_PIN_PIN11_Pos (11) /*!< GPIO_T::PIN: PIN11 Position */ +#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO_T::PIN: PIN11 Mask */ + +#define GPIO_PIN_PIN12_Pos (12) /*!< GPIO_T::PIN: PIN12 Position */ +#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO_T::PIN: PIN12 Mask */ + +#define GPIO_PIN_PIN13_Pos (13) /*!< GPIO_T::PIN: PIN13 Position */ +#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO_T::PIN: PIN13 Mask */ + +#define GPIO_PIN_PIN14_Pos (14) /*!< GPIO_T::PIN: PIN14 Position */ +#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO_T::PIN: PIN14 Mask */ + +#define GPIO_PIN_PIN15_Pos (15) /*!< GPIO_T::PIN: PIN15 Position */ +#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO_T::PIN: PIN15 Mask */ + +#define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO_T::DBEN: DBEN0 Position */ +#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO_T::DBEN: DBEN0 Mask */ + +#define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO_T::DBEN: DBEN1 Position */ +#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO_T::DBEN: DBEN1 Mask */ + +#define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO_T::DBEN: DBEN2 Position */ +#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO_T::DBEN: DBEN2 Mask */ + +#define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO_T::DBEN: DBEN3 Position */ +#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO_T::DBEN: DBEN3 Mask */ + +#define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO_T::DBEN: DBEN4 Position */ +#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO_T::DBEN: DBEN4 Mask */ + +#define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO_T::DBEN: DBEN5 Position */ +#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO_T::DBEN: DBEN5 Mask */ + +#define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO_T::DBEN: DBEN6 Position */ +#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO_T::DBEN: DBEN6 Mask */ + +#define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO_T::DBEN: DBEN7 Position */ +#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO_T::DBEN: DBEN7 Mask */ + +#define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO_T::DBEN: DBEN8 Position */ +#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO_T::DBEN: DBEN8 Mask */ + +#define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO_T::DBEN: DBEN9 Position */ +#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO_T::DBEN: DBEN9 Mask */ + +#define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO_T::DBEN: DBEN10 Position */ +#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO_T::DBEN: DBEN10 Mask */ + +#define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO_T::DBEN: DBEN11 Position */ +#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO_T::DBEN: DBEN11 Mask */ + +#define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO_T::DBEN: DBEN12 Position */ +#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO_T::DBEN: DBEN12 Mask */ + +#define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO_T::DBEN: DBEN13 Position */ +#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO_T::DBEN: DBEN13 Mask */ + +#define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO_T::DBEN: DBEN14 Position */ +#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO_T::DBEN: DBEN14 Mask */ + +#define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO_T::DBEN: DBEN15 Position */ +#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO_T::DBEN: DBEN15 Mask */ + +#define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO_T::INTTYPE: TYPE0 Position */ +#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO_T::INTTYPE: TYPE0 Mask */ + +#define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO_T::INTTYPE: TYPE1 Position */ +#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO_T::INTTYPE: TYPE1 Mask */ + +#define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO_T::INTTYPE: TYPE2 Position */ +#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO_T::INTTYPE: TYPE2 Mask */ + +#define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO_T::INTTYPE: TYPE3 Position */ +#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO_T::INTTYPE: TYPE3 Mask */ + +#define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO_T::INTTYPE: TYPE4 Position */ +#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO_T::INTTYPE: TYPE4 Mask */ + +#define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO_T::INTTYPE: TYPE5 Position */ +#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO_T::INTTYPE: TYPE5 Mask */ + +#define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO_T::INTTYPE: TYPE6 Position */ +#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO_T::INTTYPE: TYPE6 Mask */ + +#define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO_T::INTTYPE: TYPE7 Position */ +#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO_T::INTTYPE: TYPE7 Mask */ + +#define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO_T::INTTYPE: TYPE8 Position */ +#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO_T::INTTYPE: TYPE8 Mask */ + +#define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO_T::INTTYPE: TYPE9 Position */ +#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO_T::INTTYPE: TYPE9 Mask */ + +#define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO_T::INTTYPE: TYPE10 Position */ +#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO_T::INTTYPE: TYPE10 Mask */ + +#define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO_T::INTTYPE: TYPE11 Position */ +#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO_T::INTTYPE: TYPE11 Mask */ + +#define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO_T::INTTYPE: TYPE12 Position */ +#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO_T::INTTYPE: TYPE12 Mask */ + +#define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO_T::INTTYPE: TYPE13 Position */ +#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO_T::INTTYPE: TYPE13 Mask */ + +#define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO_T::INTTYPE: TYPE14 Position */ +#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO_T::INTTYPE: TYPE14 Mask */ + +#define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO_T::INTTYPE: TYPE15 Position */ +#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO_T::INTTYPE: TYPE15 Mask */ + +#define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO_T::INTEN: FLIEN0 Position */ +#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO_T::INTEN: FLIEN0 Mask */ + +#define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO_T::INTEN: FLIEN1 Position */ +#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO_T::INTEN: FLIEN1 Mask */ + +#define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO_T::INTEN: FLIEN2 Position */ +#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO_T::INTEN: FLIEN2 Mask */ + +#define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO_T::INTEN: FLIEN3 Position */ +#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO_T::INTEN: FLIEN3 Mask */ + +#define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO_T::INTEN: FLIEN4 Position */ +#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO_T::INTEN: FLIEN4 Mask */ + +#define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO_T::INTEN: FLIEN5 Position */ +#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO_T::INTEN: FLIEN5 Mask */ + +#define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO_T::INTEN: FLIEN6 Position */ +#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO_T::INTEN: FLIEN6 Mask */ + +#define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO_T::INTEN: FLIEN7 Position */ +#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO_T::INTEN: FLIEN7 Mask */ + +#define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO_T::INTEN: FLIEN8 Position */ +#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO_T::INTEN: FLIEN8 Mask */ + +#define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO_T::INTEN: FLIEN9 Position */ +#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO_T::INTEN: FLIEN9 Mask */ + +#define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO_T::INTEN: FLIEN10 Position */ +#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO_T::INTEN: FLIEN10 Mask */ + +#define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO_T::INTEN: FLIEN11 Position */ +#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO_T::INTEN: FLIEN11 Mask */ + +#define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO_T::INTEN: FLIEN12 Position */ +#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO_T::INTEN: FLIEN12 Mask */ + +#define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO_T::INTEN: FLIEN13 Position */ +#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO_T::INTEN: FLIEN13 Mask */ + +#define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO_T::INTEN: FLIEN14 Position */ +#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO_T::INTEN: FLIEN14 Mask */ + +#define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO_T::INTEN: FLIEN15 Position */ +#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO_T::INTEN: FLIEN15 Mask */ + +#define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO_T::INTEN: RHIEN0 Position */ +#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO_T::INTEN: RHIEN0 Mask */ + +#define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO_T::INTEN: RHIEN1 Position */ +#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO_T::INTEN: RHIEN1 Mask */ + +#define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO_T::INTEN: RHIEN2 Position */ +#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO_T::INTEN: RHIEN2 Mask */ + +#define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO_T::INTEN: RHIEN3 Position */ +#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO_T::INTEN: RHIEN3 Mask */ + +#define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO_T::INTEN: RHIEN4 Position */ +#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO_T::INTEN: RHIEN4 Mask */ + +#define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO_T::INTEN: RHIEN5 Position */ +#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO_T::INTEN: RHIEN5 Mask */ + +#define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO_T::INTEN: RHIEN6 Position */ +#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO_T::INTEN: RHIEN6 Mask */ + +#define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO_T::INTEN: RHIEN7 Position */ +#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO_T::INTEN: RHIEN7 Mask */ + +#define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO_T::INTEN: RHIEN8 Position */ +#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO_T::INTEN: RHIEN8 Mask */ + +#define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO_T::INTEN: RHIEN9 Position */ +#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO_T::INTEN: RHIEN9 Mask */ + +#define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO_T::INTEN: RHIEN10 Position */ +#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO_T::INTEN: RHIEN10 Mask */ + +#define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO_T::INTEN: RHIEN11 Position */ +#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO_T::INTEN: RHIEN11 Mask */ + +#define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO_T::INTEN: RHIEN12 Position */ +#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO_T::INTEN: RHIEN12 Mask */ + +#define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO_T::INTEN: RHIEN13 Position */ +#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO_T::INTEN: RHIEN13 Mask */ + +#define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO_T::INTEN: RHIEN14 Position */ +#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO_T::INTEN: RHIEN14 Mask */ + +#define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO_T::INTEN: RHIEN15 Position */ +#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO_T::INTEN: RHIEN15 Mask */ + +#define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO_T::INTSRC: INTSRC0 Position */ +#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO_T::INTSRC: INTSRC0 Mask */ + +#define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO_T::INTSRC: INTSRC1 Position */ +#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO_T::INTSRC: INTSRC1 Mask */ + +#define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO_T::INTSRC: INTSRC2 Position */ +#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO_T::INTSRC: INTSRC2 Mask */ + +#define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO_T::INTSRC: INTSRC3 Position */ +#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO_T::INTSRC: INTSRC3 Mask */ + +#define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO_T::INTSRC: INTSRC4 Position */ +#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO_T::INTSRC: INTSRC4 Mask */ + +#define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO_T::INTSRC: INTSRC5 Position */ +#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO_T::INTSRC: INTSRC5 Mask */ + +#define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO_T::INTSRC: INTSRC6 Position */ +#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO_T::INTSRC: INTSRC6 Mask */ + +#define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO_T::INTSRC: INTSRC7 Position */ +#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO_T::INTSRC: INTSRC7 Mask */ + +#define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO_T::INTSRC: INTSRC8 Position */ +#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO_T::INTSRC: INTSRC8 Mask */ + +#define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO_T::INTSRC: INTSRC9 Position */ +#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO_T::INTSRC: INTSRC9 Mask */ + +#define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO_T::INTSRC: INTSRC10 Position */ +#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO_T::INTSRC: INTSRC10 Mask */ + +#define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO_T::INTSRC: INTSRC11 Position */ +#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO_T::INTSRC: INTSRC11 Mask */ + +#define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO_T::INTSRC: INTSRC12 Position */ +#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO_T::INTSRC: INTSRC12 Mask */ + +#define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO_T::INTSRC: INTSRC13 Position */ +#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO_T::INTSRC: INTSRC13 Mask */ + +#define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO_T::INTSRC: INTSRC14 Position */ +#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO_T::INTSRC: INTSRC14 Mask */ + +#define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO_T::INTSRC: INTSRC15 Position */ +#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO_T::INTSRC: INTSRC15 Mask */ + +#define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO_T::SMTEN: SMTEN0 Position */ +#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO_T::SMTEN: SMTEN0 Mask */ + +#define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO_T::SMTEN: SMTEN1 Position */ +#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO_T::SMTEN: SMTEN1 Mask */ + +#define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO_T::SMTEN: SMTEN2 Position */ +#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO_T::SMTEN: SMTEN2 Mask */ + +#define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO_T::SMTEN: SMTEN3 Position */ +#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO_T::SMTEN: SMTEN3 Mask */ + +#define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO_T::SMTEN: SMTEN4 Position */ +#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO_T::SMTEN: SMTEN4 Mask */ + +#define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO_T::SMTEN: SMTEN5 Position */ +#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO_T::SMTEN: SMTEN5 Mask */ + +#define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO_T::SMTEN: SMTEN6 Position */ +#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO_T::SMTEN: SMTEN6 Mask */ + +#define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO_T::SMTEN: SMTEN7 Position */ +#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO_T::SMTEN: SMTEN7 Mask */ + +#define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO_T::SMTEN: SMTEN8 Position */ +#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO_T::SMTEN: SMTEN8 Mask */ + +#define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO_T::SMTEN: SMTEN9 Position */ +#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO_T::SMTEN: SMTEN9 Mask */ + +#define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO_T::SMTEN: SMTEN10 Position */ +#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO_T::SMTEN: SMTEN10 Mask */ + +#define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO_T::SMTEN: SMTEN11 Position */ +#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO_T::SMTEN: SMTEN11 Mask */ + +#define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO_T::SMTEN: SMTEN12 Position */ +#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO_T::SMTEN: SMTEN12 Mask */ + +#define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO_T::SMTEN: SMTEN13 Position */ +#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO_T::SMTEN: SMTEN13 Mask */ + +#define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO_T::SMTEN: SMTEN14 Position */ +#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO_T::SMTEN: SMTEN14 Mask */ + +#define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO_T::SMTEN: SMTEN15 Position */ +#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO_T::SMTEN: SMTEN15 Mask */ + +#define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO_T::SLEWCTL: HSREN0 Position */ +#define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO_T::SLEWCTL: HSREN0 Mask */ + +#define GPIO_SLEWCTL_HSREN1_Pos (1) /*!< GPIO_T::SLEWCTL: HSREN1 Position */ +#define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO_T::SLEWCTL: HSREN1 Mask */ + +#define GPIO_SLEWCTL_HSREN2_Pos (2) /*!< GPIO_T::SLEWCTL: HSREN2 Position */ +#define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO_T::SLEWCTL: HSREN2 Mask */ + +#define GPIO_SLEWCTL_HSREN3_Pos (3) /*!< GPIO_T::SLEWCTL: HSREN3 Position */ +#define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO_T::SLEWCTL: HSREN3 Mask */ + +#define GPIO_SLEWCTL_HSREN4_Pos (4) /*!< GPIO_T::SLEWCTL: HSREN4 Position */ +#define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO_T::SLEWCTL: HSREN4 Mask */ + +#define GPIO_SLEWCTL_HSREN5_Pos (5) /*!< GPIO_T::SLEWCTL: HSREN5 Position */ +#define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO_T::SLEWCTL: HSREN5 Mask */ + +#define GPIO_SLEWCTL_HSREN6_Pos (6) /*!< GPIO_T::SLEWCTL: HSREN6 Position */ +#define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO_T::SLEWCTL: HSREN6 Mask */ + +#define GPIO_SLEWCTL_HSREN7_Pos (7) /*!< GPIO_T::SLEWCTL: HSREN7 Position */ +#define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO_T::SLEWCTL: HSREN7 Mask */ + +#define GPIO_SLEWCTL_HSREN8_Pos (8) /*!< GPIO_T::SLEWCTL: HSREN8 Position */ +#define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO_T::SLEWCTL: HSREN8 Mask */ + +#define GPIO_SLEWCTL_HSREN9_Pos (9) /*!< GPIO_T::SLEWCTL: HSREN9 Position */ +#define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO_T::SLEWCTL: HSREN9 Mask */ + +#define GPIO_SLEWCTL_HSREN10_Pos (10) /*!< GPIO_T::SLEWCTL: HSREN10 Position */ +#define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO_T::SLEWCTL: HSREN10 Mask */ + +#define GPIO_SLEWCTL_HSREN11_Pos (11) /*!< GPIO_T::SLEWCTL: HSREN11 Position */ +#define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO_T::SLEWCTL: HSREN11 Mask */ + +#define GPIO_SLEWCTL_HSREN12_Pos (12) /*!< GPIO_T::SLEWCTL: HSREN12 Position */ +#define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO_T::SLEWCTL: HSREN12 Mask */ + +#define GPIO_SLEWCTL_HSREN13_Pos (13) /*!< GPIO_T::SLEWCTL: HSREN13 Position */ +#define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO_T::SLEWCTL: HSREN13 Mask */ + +#define GPIO_SLEWCTL_HSREN14_Pos (14) /*!< GPIO_T::SLEWCTL: HSREN14 Position */ +#define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO_T::SLEWCTL: HSREN14 Mask */ + +#define GPIO_SLEWCTL_HSREN15_Pos (15) /*!< GPIO_T::SLEWCTL: HSREN15 Position */ +#define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO_T::SLEWCTL: HSREN15 Mask */ + +#define GPIO_PUSEL_PUSEL0_Pos (0) /*!< GPIO_T::PUSEL: PUSEL0 Position */ +#define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) /*!< GPIO_T::PUSEL: PUSEL0 Mask */ + +#define GPIO_PUSEL_PUSEL1_Pos (2) /*!< GPIO_T::PUSEL: PUSEL1 Position */ +#define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) /*!< GPIO_T::PUSEL: PUSEL1 Mask */ + +#define GPIO_PUSEL_PUSEL2_Pos (4) /*!< GPIO_T::PUSEL: PUSEL2 Position */ +#define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) /*!< GPIO_T::PUSEL: PUSEL2 Mask */ + +#define GPIO_PUSEL_PUSEL3_Pos (6) /*!< GPIO_T::PUSEL: PUSEL3 Position */ +#define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) /*!< GPIO_T::PUSEL: PUSEL3 Mask */ + +#define GPIO_PUSEL_PUSEL4_Pos (8) /*!< GPIO_T::PUSEL: PUSEL4 Position */ +#define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) /*!< GPIO_T::PUSEL: PUSEL4 Mask */ + +#define GPIO_PUSEL_PUSEL5_Pos (10) /*!< GPIO_T::PUSEL: PUSEL5 Position */ +#define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) /*!< GPIO_T::PUSEL: PUSEL5 Mask */ + +#define GPIO_PUSEL_PUSEL6_Pos (12) /*!< GPIO_T::PUSEL: PUSEL6 Position */ +#define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) /*!< GPIO_T::PUSEL: PUSEL6 Mask */ + +#define GPIO_PUSEL_PUSEL7_Pos (14) /*!< GPIO_T::PUSEL: PUSEL7 Position */ +#define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) /*!< GPIO_T::PUSEL: PUSEL7 Mask */ + +#define GPIO_PUSEL_PUSEL8_Pos (16) /*!< GPIO_T::PUSEL: PUSEL8 Position */ +#define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) /*!< GPIO_T::PUSEL: PUSEL8 Mask */ + +#define GPIO_PUSEL_PUSEL9_Pos (18) /*!< GPIO_T::PUSEL: PUSEL9 Position */ +#define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) /*!< GPIO_T::PUSEL: PUSEL9 Mask */ + +#define GPIO_PUSEL_PUSEL10_Pos (20) /*!< GPIO_T::PUSEL: PUSEL10 Position */ +#define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) /*!< GPIO_T::PUSEL: PUSEL10 Mask */ + +#define GPIO_PUSEL_PUSEL11_Pos (22) /*!< GPIO_T::PUSEL: PUSEL11 Position */ +#define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) /*!< GPIO_T::PUSEL: PUSEL11 Mask */ + +#define GPIO_PUSEL_PUSEL12_Pos (24) /*!< GPIO_T::PUSEL: PUSEL12 Position */ +#define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) /*!< GPIO_T::PUSEL: PUSEL12 Mask */ + +#define GPIO_PUSEL_PUSEL13_Pos (26) /*!< GPIO_T::PUSEL: PUSEL13 Position */ +#define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) /*!< GPIO_T::PUSEL: PUSEL13 Mask */ + +#define GPIO_PUSEL_PUSEL14_Pos (28) /*!< GPIO_T::PUSEL: PUSEL14 Position */ +#define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) /*!< GPIO_T::PUSEL: PUSEL14 Mask */ + +#define GPIO_PUSEL_PUSEL15_Pos (30) /*!< GPIO_T::PUSEL: PUSEL15 Position */ +#define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) /*!< GPIO_T::PUSEL: PUSEL15 Mask */ + +#define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO_T::DBCTL: DBCLKSEL Position */ +#define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO_T::DBCTL: DBCLKSEL Mask */ + +#define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO_T::DBCTL: DBCLKSRC Position */ +#define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO_T::DBCTL: DBCLKSRC Mask */ + +#define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO_T::DBCTL: ICLKON Position */ +#define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO_T::DBCTL: ICLKON Mask */ + + +/**@}*/ /* GPIO_CONST */ +/**@}*/ /* end of GPIO register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __GPIO_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/hdiv_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/hdiv_reg.h new file mode 100644 index 0000000000..e0f411b23a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/hdiv_reg.h @@ -0,0 +1,114 @@ +/**************************************************************************//** + * @file hdiv_reg.h + * @version V1.00 + * @brief HDIV register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __HDIV_REG_H__ +#define __HDIV_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Hardware Divider --------------------------------*/ +/** + @addtogroup HDIV Hardware Divider(HDIV) + Memory Mapped Structure for HDIV Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var HDIV_T::DIVIDEND + * Offset: 0x00 Dividend Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DIVIDEND |Dividend Source + * | | |This register is given the dividend of divider before calculation starting. + * @var HDIV_T::DIVISOR + * Offset: 0x04 Divisor Source Resister + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |DIVISOR |Divisor Source + * | | |This register is given the divisor of divider before calculation starts. + * | | |Note: When this register is written, hardware divider will start calculate. + * @var HDIV_T::DIVQUO + * Offset: 0x08 Quotient Result Resister + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |QUOTIENT |Quotient Result + * | | |This register holds the quotient result of divider after calculation complete. + * @var HDIV_T::DIVREM + * Offset: 0x0C Remainder Result Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |REMAINDER |Remainder Result + * | | |The remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]), which holds the remainder result of divider after calculation complete. + * | | |The remainder of hardware divider with sign extension (REMAINDER[31:16]) to 32-bit integer. + * | | |This register holds the remainder result of divider after calculation complete. + * @var HDIV_T::DIVSTS + * Offset: 0x10 Divider Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FINISH |Division Finish Flag + * | | |0 = Under Calculation. + * | | |1 = Calculation finished. + * | | |The flag will become low when the divider is in calculation. + * | | |The flag will go back to high once the calculation finished. + * |[1] |DIV0 |Divisor Zero Warning + * | | |0 = The divisor is not 0. + * | | |1 = The divisor is 0. + * | | |Note: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written + * | | |This register is read only. + */ + __IO uint32_t DIVIDEND; /*!< [0x0000] Dividend Source Register */ + __IO uint32_t DIVISOR; /*!< [0x0004] Divisor Source Resister */ + __IO uint32_t DIVQUO; /*!< [0x0008] Quotient Result Resister */ + __IO uint32_t DIVREM; /*!< [0x000c] Remainder Result Register */ + __I uint32_t DIVSTS; /*!< [0x0010] Divider Status Register */ + +} HDIV_T; + +/** + @addtogroup HDIV_CONST HDIV Bit Field Definition + Constant Definitions for HDIV Controller + @{ +*/ + +#define HDIV_DIVIDEND_DIVIDEND_Pos (0) /*!< HDIV_T::DIVIDEND: DIVIDEND Position */ +#define HDIV_DIVIDEND_DIVIDEND_Msk (0xfffffffful << HDIV_DIVIDEND_DIVIDEND_Pos) /*!< HDIV_T::DIVIDEND: DIVIDEND Mask */ + +#define HDIV_DIVISOR_DIVISOR_Pos (0) /*!< HDIV_T::DIVISOR: DIVISOR Position */ +#define HDIV_DIVISOR_DIVISOR_Msk (0xfffful << HDIV_DIVISOR_DIVISOR_Pos) /*!< HDIV_T::DIVISOR: DIVISOR Mask */ + +#define HDIV_DIVQUO_QUOTIENT_Pos (0) /*!< HDIV_T::DIVQUO: QUOTIENT Position */ +#define HDIV_DIVQUO_QUOTIENT_Msk (0xfffffffful << HDIV_DIVQUO_QUOTIENT_Pos) /*!< HDIV_T::DIVQUO: QUOTIENT Mask */ + +#define HDIV_DIVREM_REMAINDER_Pos (0) /*!< HDIV_T::DIVREM: REMAINDER Position */ +#define HDIV_DIVREM_REMAINDER_Msk (0xfffffffful << HDIV_DIVREM_REMAINDER_Pos) /*!< HDIV_T::DIVREM: REMAINDER Mask */ + +#define HDIV_DIVSTS_FINISH_Pos (0) /*!< HDIV_T::DIVSTS: FINISH Position */ +#define HDIV_DIVSTS_FINISH_Msk (0x1ul << HDIV_DIVSTS_FINISH_Pos) /*!< HDIV_T::DIVSTS: FINISH Mask */ + +#define HDIV_DIVSTS_DIV0_Pos (1) /*!< HDIV_T::DIVSTS: DIV0 Position */ +#define HDIV_DIVSTS_DIV0_Msk (0x1ul << HDIV_DIVSTS_DIV0_Pos) /*!< HDIV_T::DIVSTS: DIV0 Mask */ + +/**@}*/ /* HDIV_CONST */ +/**@}*/ /* end of HDIV register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __HDIV_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/i2c_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/i2c_reg.h new file mode 100644 index 0000000000..fa8f85d378 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/i2c_reg.h @@ -0,0 +1,717 @@ +/**************************************************************************//** + * @file i2c_reg.h + * @version V1.00 + * @brief I2C register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2C_REG_H__ +#define __I2C_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Inter-IC Bus Controller -------------------------*/ +/** + @addtogroup I2C Inter-IC Bus Controller(I2C) + Memory Mapped Structure for I2C Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var I2C_T::CTL0 + * Offset: 0x00 I2C Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |AA |Assert Acknowledge Control + * | | |When AA =1 prior to address or data is received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line + * |[3] |SI |I2C Interrupt Flag + * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware + * | | |If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested + * | | |SI must be cleared by software + * | | |Clear SI by writing 1 to this bit. + * | | |For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer. + * |[4] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected + * | | |This bit will be cleared by hardware automatically. + * |[5] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[6] |I2CEN |I2C Controller Enable Bit + * | | |Set to enable I2C serial function controller + * | | |When I2CEN=1 the I2C serial function enable + * | | |The multi-function pin function must set to SDA, and SCL of I2C function first. + * | | |0 = I2C controller Disabled. + * | | |1 = I2C controller Enabled. + * |[7] |INTEN |Enable Interrupt + * | | |0 = I2C interrupt Disabled. + * | | |1 = I2C interrupt Enabled. + * @var I2C_T::ADDR0 + * Offset: 0x04 I2C Slave Address Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * @var I2C_T::DAT + * Offset: 0x08 I2C Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |I2C Data + * | | |Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port. + * @var I2C_T::STATUS0 + * Offset: 0x0C I2C Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |STATUS |I2C Status + * | | |The three least significant bits are always 0 + * | | |The five most significant bits contain the status code + * | | |There are 28 possible status codes + * | | |When the content of I2C_STATUS0 is F8H, no serial interrupt is requested + * | | |Others I2C_STATUS0 values correspond to defined I2C states + * | | |When each of these states is entered, a status interrupt is requested (SI = 1) + * | | |A valid status code is present in I2C_STATUS0 one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software + * | | |In addition, states 00H stands for a Bus Error + * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit. + * @var I2C_T::CLKDIV + * Offset: 0x10 I2C Clock Divided Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DIVIDER |I2C Clock Divided + * | | |Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)). + * | | |Note: The minimum value of I2C_CLKDIV is 4. + * @var I2C_T::TOCTL + * Offset: 0x14 I2C Time-out Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIF |Time-out Flag + * | | |This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1. + * | | |Note: Software can write 1 to clear this bit. + * |[1] |TOCDIV4 |Time-out Counter Input Clock Divided by 4 + * | | |When Enabled, The time-out period is extend 4 times. + * | | |0 = Time-out period is extend 4 times Disabled. + * | | |1 = Time-out period is extend 4 times Enabled. + * |[2] |TOCEN |Time-out Counter Enable Bit + * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear + * | | |Setting flag SI to u20181' will reset counter and re-start up counting after SI is cleared. + * | | |0 = Time-out counter Disabled. + * | | |1 = Time-out counter Enabled. + * @var I2C_T::ADDR1 + * Offset: 0x18 I2C Slave Address Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * @var I2C_T::ADDR2 + * Offset: 0x1C I2C Slave Address Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * @var I2C_T::ADDR3 + * Offset: 0x20 I2C Slave Address Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[10:1] |ADDR |I2C Address + * | | |The content of this register is irrelevant when I2C is in Master mode + * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address + * | | |The I2C hardware will react if either of the address is matched. + * @var I2C_T::ADDRMSK0 + * Offset: 0x24 I2C Slave Address Mask Register0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK1 + * Offset: 0x28 I2C Slave Address Mask Register1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK2 + * Offset: 0x2C I2C Slave Address Mask Register2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::ADDRMSK3 + * Offset: 0x30 I2C Slave Address Mask Register3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:1] |ADDRMSK |I2C Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |I2C bus controllers support multiple address recognition with four address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not use address mask. + * @var I2C_T::WKCTL + * Offset: 0x3C I2C Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |I2C Wake-up Enable Bit + * | | |0 = I2C wake-up function Disabled. + * | | |1= I2C wake-up function Enabled. + * |[7] |NHDBUSEN |I2C No Hold BUS Enable Bit + * | | |0 = I2C don't hold bus after wake-up disable. + * | | |1= I2C don't hold bus after wake-up enable. + * | | |Note: I2C controller could response when WKIF event is not clear, it may cause error data transmitted or received + * | | |If data transmitted or received when WKIF event is not clear, user must reset I2C controller and execute the original operation again. + * @var I2C_T::WKSTS + * Offset: 0x40 I2C Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKIF |I2C Wake-up Flag + * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * |[1] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release WKIF. Software can write 1 to clear this bit. + * |[2] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * | | |Note: This bit will be cleared when software can write 1 to WKAKDONE bit. + * @var I2C_T::CTL1 + * Offset: 0x44 I2C Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function disable. + * | | |1 = Transmit PDMA function enable. + * |[1] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function disable. + * | | |1 = Receive PDMA function enable. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the I2C request to PDMA. This bit will be cleared to 0 automatically. + * |[8] |PDMASTR |PDMA Stretch Bit + * | | |0 = I2C send STOP automatically after PDMA transfer done. (only master TX) + * | | |1 = I2C SCL bus is stretched by hardware after PDMA transfer done if the SI is not cleared + * | | |(only master TX) + * |[9] |ADDR10EN |Address 10-bit Function Enable + * | | |0 = Address match 10-bit function is disabled. + * | | |1 = Address match 10-bit function is enabled. + * @var I2C_T::STATUS1 + * Offset: 0x48 I2C Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |I2C Address 0 Match Status Register + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |I2C Address 1 Match Status Register + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[2] |ADMAT2 |I2C Address 2 Match Status Register + * | | |When address 2 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[3] |ADMAT3 |I2C Address 3 Match Status Register + * | | |When address 3 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[8] |ONBUSY |On Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected. + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * | | |Note:This bit is read only. + * @var I2C_T::TMCTL + * Offset: 0x4C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control Register + * | | |This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode. + * | | |The delay setup time is numbers of peripheral clock = STCTL x PCLK. + * | | |Note: Setup time setting should not make SCL output less than three PCLKs. + * |[24:16] |HTCTL |Hold Time Configure Control Register + * | | |This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x PCLK. + * @var I2C_T::BUSCTL + * Offset: 0x50 I2C Bus Management Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ACKMEN |Acknowledge Control by Manual + * | | |In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit. + * | | |0 = Slave byte control Disabled. + * | | |1 = Slave byte control Enabled + * | | |The 9th bit can response the ACK or NACK according the received data by user + * | | |When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse. + * | | |Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition. + * |[1] |PECEN |Packet Error Checking Calculation Enable Bit + * | | |0 = Packet Error Checking Calculation Disabled. + * | | |1 = Packet Error Checking Calculation Enabled. + * | | |Note: When I2C enter power down mode, the bit should be enabled after wake-up if needed PEC calculation. + * |[2] |BMDEN |Bus Management Device Default Address Enable Bit + * | | |0 = Device default address Disable + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed + * | | |1 = Device default address Enabled + * | | |When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed. + * |[3] |BMHEN |Bus Management Host Enable Bit + * | | |0 = Host function Disabled. + * | | |1 = Host function Enabled. + * |[4] |ALERTEN |Bus Management Alert Enable Bit + * | | |Device Mode (BMHEN =0). + * | | |0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled. + * | | |1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled. + * | | |Host Mode (BMHEN =1). + * | | |0 = BM_ALERT pin not supported. + * | | |1 = BM_ALERT pin supported. + * |[5] |SCTLOSTS |Suspend/Control Data Output Status + * | | |0 = The output of SUSCON pin is low. + * | | |1 = The output of SUSCON pin is high. + * |[6] |SCTLOEN |Suspend or Control Pin Output Enable Bit + * | | |0 = The SUSCON pin in input. + * | | |1 = The output enable is active on the SUSCON pin. + * |[7] |BUSEN |BUS Enable Bit + * | | |0 = The system management function is Disabled. + * | | |1 = The system management function is Enable. + * | | |Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition. + * |[8] |PECTXEN |Packet Error Checking Byte Transmission/Reception + * | | |0 = No PEC transfer. + * | | |1 = PEC transmission is requested. + * | | |Note: 1.This bit has no effect in slave mode when ACKMEN =0. + * |[9] |TIDLE |Timer Check in Idle State + * | | |The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle + * | | |This bit is used to define which condition is enabled. + * | | |0 = The BUSTOUT is used to calculate the clock low period in bus active. + * | | |1 = The BUSTOUT is used to calculate the IDLE period in bus Idle. + * | | |Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state. + * |[10] |PECCLR |PEC Clear at Repeat Start + * | | |The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected + * | | |This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation. + * | | |0 = The PEC calculation is cleared by Repeat Start function is Disabled. + * | | |1 = The PEC calculation is cleared by Repeat Start function is Enabled. + * |[11] |ACKM9SI |Acknowledge Manual Enable Extra SI Interrupt + * | | |0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1. + * | | |1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1. + * |[12] |BCDIEN |Packet Error Checking Byte Count Done Interrupt Enable Bit + * | | |0 = Indicates the byte count done interrupt is Disabled. + * | | |1 = Indicates the byte count done interrupt is Enabled. + * | | |Note: This bit is used in PECEN =1. + * |[13] |PECDIEN |Packet Error Checking Byte Transfer Done Interrupt Enable Bit + * | | |0 = Indicates the PEC transfer done interrupt is Disabled. + * | | |1 = Indicates the PEC transfer done interrupt is Enabled. + * | | |Note: This bit is used in PECEN =1. + * @var I2C_T::BUSTCTL + * Offset: 0x54 I2C Bus Management Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSTOEN |Bus Time Out Enable Bit + * | | |0 = Indicates the bus clock low time-out detection is Disabled. + * | | |1 = Indicates the bus clock low time-out detection is Enabled (bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1) + * |[1] |CLKTOEN |Cumulative Clock Low Time Out Enable Bit + * | | |0 = Indicates the cumulative clock low time-out detection is Disabled. + * | | |1 = Indicates the cumulative clock low time-out detection is Enabled. + * | | |For Master, it calculates the period from START to ACK + * | | |For Slave, it calculates the period from START to STOP + * |[2] |BUSTOIEN |Time-out Interrupt Enable Bit + * | | |BUSY =1. + * | | |0 = Indicates the SCLK low time-out interrupt is Disabled. + * | | |1 = Indicates the SCLK low time-out interrupt is Enabled. + * | | |BUSY =0. + * | | |0 = Indicates the bus IDLE time-out interrupt is Disabled. + * | | |1 = Indicates the bus IDLE time-out interrupt is Enabled. + * |[3] |CLKTOIEN |Extended Clock Time Out Interrupt Enable Bit + * | | |0 = Indicates the clock time out interrupt is Disabled. + * | | |1 = Indicates the clock time out interrupt is Enabled. + * |[4] |TORSTEN |Time Out Reset Enable Bit + * | | |0 = Indicates the I2C state machine reset is Disable. + * | | |1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high) + * @var I2C_T::BUSSTS + * Offset: 0x58 I2C Bus Management Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * |[1] |BCDONE |Byte Count Transmission/Receive Done + * | | |0 = Indicates the byte count transmission/ receive is not finished when the PECEN is set. + * | | |1 = Indicates the byte count transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * |[2] |PECERR |PEC Error in Reception + * | | |0 = Indicates the PEC value equal the received PEC data packet. + * | | |1 = Indicates the PEC value doesn't match the receive PEC data packet. + * | | |Note: Software can write 1 to clear this bit. + * |[3] |ALERT |SMBus Alert Status + * | | |Device Mode (BMHEN =0). + * | | |0 = Indicates SMBALERT pin state is low. + * | | |1 = Indicates SMBALERT pin state is high. + * | | |Host Mode (BMHEN =1). + * | | |0 = No SMBALERT event. + * | | |1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1. + * | | |Note: 1 + * | | |The SMBALERT pin is an open-drain pin, the pull-high resistor is must in the system + * | | |2 + * | | |Software can write 1 to clear this bit. + * |[4] |SCTLDIN |Bus Suspend or Control Signal Input Status + * | | |0 = The input status of SUSCON pin is 0. + * | | |1 = The input status of SUSCON pin is 1. + * |[5] |BUSTO |Bus Time-out Status + * | | |0 = Indicates that there is no any time-out or external clock time-out. + * | | |1 = Indicates that a time-out or external clock time-out occurred. + * | | |In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[6] |CLKTO |Clock Low Accumulate Time-out Status + * | | |0 = Indicates that the cumulative clock low is no any time-out. + * | | |1 = Indicates that the cumulative clock low time-out occurred. + * | | |Note: Software can write 1 to clear this bit. + * |[7] |PECDONE |PEC Byte Transmission/Receive Done + * | | |0 = Indicates the PEC transmission/ receive is not finished when the PECEN is set. + * | | |1 = Indicates the PEC transmission/ receive is finished when the PECEN is set. + * | | |Note: Software can write 1 to clear this bit. + * @var I2C_T::PKTSIZE + * Offset: 0x5C I2C Packet Error Checking Byte Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |PLDSIZE |Transfer Byte Number + * | | |The transmission or receive byte number in one transaction when the PECEN is set + * | | |The maximum transaction or receive byte is 256 Bytes. + * | | |Notice: The byte number counting includes address, command code, and data frame. + * @var I2C_T::PKTCRC + * Offset: 0x60 I2C Packet Error Checking Byte Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PECCRC |Packet Error Checking Byte Value + * | | |This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1 + * | | |It is read only. + * @var I2C_T::BUSTOUT + * Offset: 0x64 I2C Bus Management Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |BUSTO |Bus Management Time-out Value + * | | |Indicate the bus time-out value in bus is IDLE or SCLK low. + * | | |Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set. + * @var I2C_T::CLKTOUT + * Offset: 0x68 I2C Bus Management Clock Low Timer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CLKTO |Bus Clock Low Timer + * | | |The field is used to configure the cumulative clock extension time-out. + * | | |Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and clear to 0 first in the BUSEN is set. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2C Control Register 0 */ + __IO uint32_t ADDR0; /*!< [0x0004] I2C Slave Address Register0 */ + __IO uint32_t DAT; /*!< [0x0008] I2C Data Register */ + __I uint32_t STATUS0; /*!< [0x000c] I2C Status Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0010] I2C Clock Divided Register */ + __IO uint32_t TOCTL; /*!< [0x0014] I2C Time-out Control Register */ + __IO uint32_t ADDR1; /*!< [0x0018] I2C Slave Address Register1 */ + __IO uint32_t ADDR2; /*!< [0x001c] I2C Slave Address Register2 */ + __IO uint32_t ADDR3; /*!< [0x0020] I2C Slave Address Register3 */ + __IO uint32_t ADDRMSK0; /*!< [0x0024] I2C Slave Address Mask Register0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0028] I2C Slave Address Mask Register1 */ + __IO uint32_t ADDRMSK2; /*!< [0x002c] I2C Slave Address Mask Register2 */ + __IO uint32_t ADDRMSK3; /*!< [0x0030] I2C Slave Address Mask Register3 */ + __I uint32_t RESERVE0[2]; + __IO uint32_t WKCTL; /*!< [0x003c] I2C Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0040] I2C Wake-up Status Register */ + __IO uint32_t CTL1; /*!< [0x0044] I2C Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0048] I2C Status Register 1 */ + __IO uint32_t TMCTL; /*!< [0x004c] I2C Timing Configure Control Register */ + __IO uint32_t BUSCTL; /*!< [0x0050] I2C Bus Management Control Register */ + __IO uint32_t BUSTCTL; /*!< [0x0054] I2C Bus Management Timer Control Register */ + __IO uint32_t BUSSTS; /*!< [0x0058] I2C Bus Management Status Register */ + __IO uint32_t PKTSIZE; /*!< [0x005c] I2C Packet Error Checking Byte Number Register */ + __I uint32_t PKTCRC; /*!< [0x0060] I2C Packet Error Checking Byte Value Register */ + __IO uint32_t BUSTOUT; /*!< [0x0064] I2C Bus Management Timer Register */ + __IO uint32_t CLKTOUT; /*!< [0x0068] I2C Bus Management Clock Low Timer Register */ + +} I2C_T; + +/** + @addtogroup I2C_CONST I2C Bit Field Definition + Constant Definitions for I2C Controller + @{ +*/ + +#define I2C_CTL0_AA_Pos (2) /*!< I2C_T::CTL0: AA Position */ +#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) /*!< I2C_T::CTL0: AA Mask */ + +#define I2C_CTL0_SI_Pos (3) /*!< I2C_T::CTL0: SI Position */ +#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) /*!< I2C_T::CTL0: SI Mask */ + +#define I2C_CTL0_STO_Pos (4) /*!< I2C_T::CTL0: STO Position */ +#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) /*!< I2C_T::CTL0: STO Mask */ + +#define I2C_CTL0_STA_Pos (5) /*!< I2C_T::CTL0: STA Position */ +#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) /*!< I2C_T::CTL0: STA Mask */ + +#define I2C_CTL0_I2CEN_Pos (6) /*!< I2C_T::CTL0: I2CEN Position */ +#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) /*!< I2C_T::CTL0: I2CEN Mask */ + +#define I2C_CTL0_INTEN_Pos (7) /*!< I2C_T::CTL0: INTEN Position */ +#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) /*!< I2C_T::CTL0: INTEN Mask */ + +#define I2C_ADDR0_GC_Pos (0) /*!< I2C_T::ADDR0: GC Position */ +#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C_T::ADDR0: GC Mask */ + +#define I2C_ADDR0_ADDR_Pos (1) /*!< I2C_T::ADDR0: ADDR Position */ +#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) /*!< I2C_T::ADDR0: ADDR Mask */ + +#define I2C_DAT_DAT_Pos (0) /*!< I2C_T::DAT: DAT Position */ +#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C_T::DAT: DAT Mask */ + +#define I2C_STATUS0_STATUS_Pos (0) /*!< I2C_T::STATUS0: STATUS Position */ +#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS0_STATUS_Pos) /*!< I2C_T::STATUS0: STATUS Mask */ + +#define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C_T::CLKDIV: DIVIDER Position */ +#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C_T::CLKDIV: DIVIDER Mask */ + +#define I2C_TOCTL_TOIF_Pos (0) /*!< I2C_T::TOCTL: TOIF Position */ +#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C_T::TOCTL: TOIF Mask */ + +#define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C_T::TOCTL: TOCDIV4 Position */ +#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C_T::TOCTL: TOCDIV4 Mask */ + +#define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C_T::TOCTL: TOCEN Position */ +#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C_T::TOCTL: TOCEN Mask */ + +#define I2C_ADDR1_GC_Pos (0) /*!< I2C_T::ADDR1: GC Position */ +#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C_T::ADDR1: GC Mask */ + +#define I2C_ADDR1_ADDR_Pos (1) /*!< I2C_T::ADDR1: ADDR Position */ +#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) /*!< I2C_T::ADDR1: ADDR Mask */ + +#define I2C_ADDR2_GC_Pos (0) /*!< I2C_T::ADDR2: GC Position */ +#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C_T::ADDR2: GC Mask */ + +#define I2C_ADDR2_ADDR_Pos (1) /*!< I2C_T::ADDR2: ADDR Position */ +#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) /*!< I2C_T::ADDR2: ADDR Mask */ + +#define I2C_ADDR3_GC_Pos (0) /*!< I2C_T::ADDR3: GC Position */ +#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C_T::ADDR3: GC Mask */ + +#define I2C_ADDR3_ADDR_Pos (1) /*!< I2C_T::ADDR3: ADDR Position */ +#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) /*!< I2C_T::ADDR3: ADDR Mask */ + +#define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK0: ADDRMSK Position */ +#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK1: ADDRMSK Position */ +#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK2: ADDRMSK Position */ +#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK2: ADDRMSK Mask */ + +#define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C_T::ADDRMSK3: ADDRMSK Position */ +#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C_T::ADDRMSK3: ADDRMSK Mask */ + +#define I2C_WKCTL_WKEN_Pos (0) /*!< I2C_T::WKCTL: WKEN Position */ +#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C_T::WKCTL: WKEN Mask */ + +#define I2C_WKCTL_NHDBUSEN_Pos (7) /*!< I2C_T::WKCTL: NHDBUSEN Position */ +#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) /*!< I2C_T::WKCTL: NHDBUSEN Mask */ + +#define I2C_WKSTS_WKIF_Pos (0) /*!< I2C_T::WKSTS: WKIF Position */ +#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C_T::WKSTS: WKIF Mask */ + +#define I2C_WKSTS_WKAKDONE_Pos (1) /*!< I2C_T::WKSTS: WKAKDONE Position */ +#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) /*!< I2C_T::WKSTS: WKAKDONE Mask */ + +#define I2C_WKSTS_WRSTSWK_Pos (2) /*!< I2C_T::WKSTS: WRSTSWK Position */ +#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) /*!< I2C_T::WKSTS: WRSTSWK Mask */ + +#define I2C_CTL1_TXPDMAEN_Pos (0) /*!< I2C_T::CTL1: TXPDMAEN Position */ +#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) /*!< I2C_T::CTL1: TXPDMAEN Mask */ + +#define I2C_CTL1_RXPDMAEN_Pos (1) /*!< I2C_T::CTL1: RXPDMAEN Position */ +#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) /*!< I2C_T::CTL1: RXPDMAEN Mask */ + +#define I2C_CTL1_PDMARST_Pos (2) /*!< I2C_T::CTL1: PDMARST Position */ +#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) /*!< I2C_T::CTL1: PDMARST Mask */ + +#define I2C_CTL1_PDMASTR_Pos (8) /*!< I2C_T::CTL1: PDMASTR Position */ +#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) /*!< I2C_T::CTL1: PDMASTR Mask */ + +#define I2C_CTL1_ADDR10EN_Pos (9) /*!< I2C_T::CTL1: ADDR10EN Position */ +#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) /*!< I2C_T::CTL1: ADDR10EN Mask */ + +#define I2C_STATUS1_ADMAT0_Pos (0) /*!< I2C_T::STATUS1: ADMAT0 Position */ +#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) /*!< I2C_T::STATUS1: ADMAT0 Mask */ + +#define I2C_STATUS1_ADMAT1_Pos (1) /*!< I2C_T::STATUS1: ADMAT1 Position */ +#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) /*!< I2C_T::STATUS1: ADMAT1 Mask */ + +#define I2C_STATUS1_ADMAT2_Pos (2) /*!< I2C_T::STATUS1: ADMAT2 Position */ +#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) /*!< I2C_T::STATUS1: ADMAT2 Mask */ + +#define I2C_STATUS1_ADMAT3_Pos (3) /*!< I2C_T::STATUS1: ADMAT3 Position */ +#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) /*!< I2C_T::STATUS1: ADMAT3 Mask */ + +#define I2C_STATUS1_ONBUSY_Pos (8) /*!< I2C_T::STATUS1: ONBUSY Position */ +#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) /*!< I2C_T::STATUS1: ONBUSY Mask */ + +#define I2C_TMCTL_STCTL_Pos (0) /*!< I2C_T::TMCTL: STCTL Position */ +#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) /*!< I2C_T::TMCTL: STCTL Mask */ + +#define I2C_TMCTL_HTCTL_Pos (16) /*!< I2C_T::TMCTL: HTCTL Position */ +#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) /*!< I2C_T::TMCTL: HTCTL Mask */ + +#define I2C_BUSCTL_ACKMEN_Pos (0) /*!< I2C_T::BUSCTL: ACKMEN Position */ +#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) /*!< I2C_T::BUSCTL: ACKMEN Mask */ + +#define I2C_BUSCTL_PECEN_Pos (1) /*!< I2C_T::BUSCTL: PECEN Position */ +#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) /*!< I2C_T::BUSCTL: PECEN Mask */ + +#define I2C_BUSCTL_BMDEN_Pos (2) /*!< I2C_T::BUSCTL: BMDEN Position */ +#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) /*!< I2C_T::BUSCTL: BMDEN Mask */ + +#define I2C_BUSCTL_BMHEN_Pos (3) /*!< I2C_T::BUSCTL: BMHEN Position */ +#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) /*!< I2C_T::BUSCTL: BMHEN Mask */ + +#define I2C_BUSCTL_ALERTEN_Pos (4) /*!< I2C_T::BUSCTL: ALERTEN Position */ +#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) /*!< I2C_T::BUSCTL: ALERTEN Mask */ + +#define I2C_BUSCTL_SCTLOSTS_Pos (5) /*!< I2C_T::BUSCTL: SCTLOSTS Position */ +#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) /*!< I2C_T::BUSCTL: SCTLOSTS Mask */ + +#define I2C_BUSCTL_SCTLOEN_Pos (6) /*!< I2C_T::BUSCTL: SCTLOEN Position */ +#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) /*!< I2C_T::BUSCTL: SCTLOEN Mask */ + +#define I2C_BUSCTL_BUSEN_Pos (7) /*!< I2C_T::BUSCTL: BUSEN Position */ +#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) /*!< I2C_T::BUSCTL: BUSEN Mask */ + +#define I2C_BUSCTL_PECTXEN_Pos (8) /*!< I2C_T::BUSCTL: PECTXEN Position */ +#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) /*!< I2C_T::BUSCTL: PECTXEN Mask */ + +#define I2C_BUSCTL_TIDLE_Pos (9) /*!< I2C_T::BUSCTL: TIDLE Position */ +#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) /*!< I2C_T::BUSCTL: TIDLE Mask */ + +#define I2C_BUSCTL_PECCLR_Pos (10) /*!< I2C_T::BUSCTL: PECCLR Position */ +#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) /*!< I2C_T::BUSCTL: PECCLR Mask */ + +#define I2C_BUSCTL_ACKM9SI_Pos (11) /*!< I2C_T::BUSCTL: ACKM9SI Position */ +#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) /*!< I2C_T::BUSCTL: ACKM9SI Mask */ + +#define I2C_BUSCTL_BCDIEN_Pos (12) /*!< I2C_T::BUSCTL: BCDIEN Position */ +#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) /*!< I2C_T::BUSCTL: BCDIEN Mask */ + +#define I2C_BUSCTL_PECDIEN_Pos (13) /*!< I2C_T::BUSCTL: PECDIEN Position */ +#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) /*!< I2C_T::BUSCTL: PECDIEN Mask */ + +#define I2C_BUSTCTL_BUSTOEN_Pos (0) /*!< I2C_T::BUSTCTL: BUSTOEN Position */ +#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOEN Mask */ + +#define I2C_BUSTCTL_CLKTOEN_Pos (1) /*!< I2C_T::BUSTCTL: CLKTOEN Position */ +#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOEN Mask */ + +#define I2C_BUSTCTL_BUSTOIEN_Pos (2) /*!< I2C_T::BUSTCTL: BUSTOIEN Position */ +#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) /*!< I2C_T::BUSTCTL: BUSTOIEN Mask */ + +#define I2C_BUSTCTL_CLKTOIEN_Pos (3) /*!< I2C_T::BUSTCTL: CLKTOIEN Position */ +#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) /*!< I2C_T::BUSTCTL: CLKTOIEN Mask */ + +#define I2C_BUSTCTL_TORSTEN_Pos (4) /*!< I2C_T::BUSTCTL: TORSTEN Position */ +#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) /*!< I2C_T::BUSTCTL: TORSTEN Mask */ + +#define I2C_BUSSTS_BUSY_Pos (0) /*!< I2C_T::BUSSTS: BUSY Position */ +#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) /*!< I2C_T::BUSSTS: BUSY Mask */ + +#define I2C_BUSSTS_BCDONE_Pos (1) /*!< I2C_T::BUSSTS: BCDONE Position */ +#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) /*!< I2C_T::BUSSTS: BCDONE Mask */ + +#define I2C_BUSSTS_PECERR_Pos (2) /*!< I2C_T::BUSSTS: PECERR Position */ +#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) /*!< I2C_T::BUSSTS: PECERR Mask */ + +#define I2C_BUSSTS_ALERT_Pos (3) /*!< I2C_T::BUSSTS: ALERT Position */ +#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) /*!< I2C_T::BUSSTS: ALERT Mask */ + +#define I2C_BUSSTS_SCTLDIN_Pos (4) /*!< I2C_T::BUSSTS: SCTLDIN Position */ +#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) /*!< I2C_T::BUSSTS: SCTLDIN Mask */ + +#define I2C_BUSSTS_BUSTO_Pos (5) /*!< I2C_T::BUSSTS: BUSTO Position */ +#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) /*!< I2C_T::BUSSTS: BUSTO Mask */ + +#define I2C_BUSSTS_CLKTO_Pos (6) /*!< I2C_T::BUSSTS: CLKTO Position */ +#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) /*!< I2C_T::BUSSTS: CLKTO Mask */ + +#define I2C_BUSSTS_PECDONE_Pos (7) /*!< I2C_T::BUSSTS: PECDONE Position */ +#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) /*!< I2C_T::BUSSTS: PECDONE Mask */ + +#define I2C_PKTSIZE_PLDSIZE_Pos (0) /*!< I2C_T::PKTSIZE: PLDSIZE Position */ +#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) /*!< I2C_T::PKTSIZE: PLDSIZE Mask */ + +#define I2C_PKTCRC_PECCRC_Pos (0) /*!< I2C_T::PKTCRC: PECCRC Position */ +#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) /*!< I2C_T::PKTCRC: PECCRC Mask */ + +#define I2C_BUSTOUT_BUSTO_Pos (0) /*!< I2C_T::BUSTOUT: BUSTO Position */ +#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) /*!< I2C_T::BUSTOUT: BUSTO Mask */ + +#define I2C_CLKTOUT_CLKTO_Pos (0) /*!< I2C_T::CLKTOUT: CLKTO Position */ +#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /*!< I2C_T::CLKTOUT: CLKTO Mask */ + +/**@}*/ /* I2C_CONST */ +/**@}*/ /* end of I2C register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __I2C_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/i2s_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/i2s_reg.h new file mode 100644 index 0000000000..f5ef355f7d --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/i2s_reg.h @@ -0,0 +1,701 @@ +/**************************************************************************//** + * @file i2s_reg.h + * @version V1.00 + * @brief I2S register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __I2S_REG_H__ +#define __I2S_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- I2S Interface Controller -------------------------*/ +/** + @addtogroup I2S I2S Interface Controller(I2S) + Memory Mapped Structure for I2S Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var I2S_T::CTL0 + * Offset: 0x00 I2S Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable Control + * | | |0 = I2S controller Disabled. + * | | |1 = I2S controller Enabled. + * |[1] |TXEN |Transmit Enable Control + * | | |0 = Data transmission Disabled. + * | | |1 = Data transmission Enabled. + * |[2] |RXEN |Receive Enable Control + * | | |0 = Data receiving Disabled. + * | | |1 = Data receiving Enabled. + * |[3] |MUTE |Transmit Mute Enable Control + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Send zero on transmit channel. + * |[5:4] |DATWIDTH |Data Width + * | | |This bit field is used to define the bit-width of data word in each audio channel + * | | |00 = The bit-width of data word is 8-bit. + * | | |01 = The bit-width of data word is 16-bit. + * | | |10 = The bit-width of data word is 24-bit. + * | | |11 = The bit-width of data word is 32-bit. + * |[6] |MONO |Monaural Data Control + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * | | |Note: when chip records data, RXLCH (I2S_CTL0[23]) indicates which channel data will be saved if monaural format is selected. + * |[7] |ORDER |Stereo Data Order in FIFO + * | | |In 8-bit/16-bit data width, this bit is used to select whether the even or odd channel data is stored in higher byte + * | | |In 24-bit data width, this is used to select the left/right alignment method of audio data which is stored in data memory consisted of 32-bit FIFO entries. + * | | |0 = Even channel data at high byte in 8-bit/16-bit data width. + * | | |LSB of 24-bit audio data in each channel is aligned to right side in 32-bit FIFO entries. + * | | |1 = Even channel data at low byte. + * | | | MSB of 24-bit audio data in each channel is aligned to left side in 32-bit FIFO entries. + * |[8] |SLAVE |Slave Mode Enable Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * | | |Note: I2S can operate as master or slave + * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send out bit clock to Audio CODEC chip + * | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip. + * |[15] |MCLKEN |Master Clock Enable Control + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[18] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No Effect. + * | | |1 = Clear TX FIFO. + * | | |Note 1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT (I2S_STATUS1[12:8]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed. + * | | |Note 2: This bit is clear by hardware automatically, read it return zero. + * |[19] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No Effect. + * | | |1 = Clear RX FIFO. + * | | |Note 1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS1[20:16]) returns 0 and receive FIFO becomes empty. + * | | |Note 2: This bit is cleared by hardware automatically, read it return zero. + * |[20] |TXPDMAEN |Transmit PDMA Enable Control + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[21] |RXPDMAEN |Receive PDMA Enable Control + * | | |0 = Receiver PDMA function Disabled. + * | | |1 = Receiver PDMA function Enabled. + * |[23] |RXLCH |Receive Left Channel Enable Control + * | | |When monaural format is selected (MONO = 1), I2S will receive channel1 data if RXLCH is set to 0, and receive channel0 data if RXLCH is set to 1. + * | | |0 = Receives channel1 data in MONO mode. + * | | |1 = Receives channel0 data in MONO mode. + * |[26:24] |FORMAT |Data Format Selection + * | | |000 = I2S standard data format. + * | | |001 = I2S with MSB justified. + * | | |010 = I2S with LSB justified. + * | | |011 = Reserved. + * | | |100 = PCM standard data format. + * | | |101 = PCM with MSB justified. + * | | |110 = PCM with LSB justified. + * | | |111 = Reserved. + * |[27] |PCMSYNC |PCM Synchronization Pulse Length Selection + * | | |This bit field is used to select the high pulse length of frame synchronization signal in PCM protocol. + * | | |0 = One BCLK period. + * | | |1 = One channel period. + * | | |Note: This bit is only available in master mode. + * |[29:28] |CHWIDTH |Channel Width + * | | |This bit fields are used to define the length of audio channel + * | | |If CHWIDTH < DATWIDTH, the hardware will set the real channel length as the bit-width of audio data which is defined by DATWIDTH. + * | | |00 = The bit-width of each audio channel is 8-bit. + * | | |01 = The bit-width of each audio channel is 16-bit. + * | | |10 = The bit-width of each audio channel is 24-bit. + * | | |11 = The bit-width of each audio channel is 32-bit. + * |[31:30] |TDMCHNUM |TDM Channel Number + * | | |This bit fields are used to define the TDM channel number in one audio frame while PCM mode (FORMAT[2] = 1). + * | | |00 = 2 channels in audio frame. + * | | |01 = 4 channels in audio frame. + * | | |10 = 6 channels in audio frame. + * | | |11 = 8 channels in audio frame. + * @var I2S_T::CLKDIV + * Offset: 0x04 I2S Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |MCLKDIV |Master Clock Divider + * | | |If chip external crystal frequency is (2 x MCLKDIV) x 256fs then software can program these bits to generate 256fs clock frequency to audio codec chip + * | | |If MCLKDIV is set to 0, MCLK is the same as external clock input. + * | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1. + * | | |F_MCLK = F_I2SCLK/(2 x MCLKDIV) (When MCLKDIV is >= 1 ). + * | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ). + * | | |Note: F_MCLK is the frequency of MCLK, and F_I2SCLK is the frequency of the I2S_CLK. + * |[16:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode + * | | |Software can program these bit fields to generate sampling rate clock frequency. + * | | |F_BCLK= F_I2SCLK / (2 x (BCLKDIV + 1)). + * | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK. + * @var I2S_T::IEN + * Offset: 0x08 I2S Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXUDFIEN |Receive FIFO Underflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: If software reads receive FIFO when it is empty then RXUDIF (I2S_STATUS0[8]) flag is set to 1. + * |[1] |RXOVFIEN |Receive FIFO Overflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIF (I2S_STATUS0[9]) flag is set to 1. + * |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: When data word in receive FIFO is equal or higher than RXTH (I2S_CTL1[19:16]) and the RXTHIF (I2S_STATUS0[10]) bit is set to 1 + * | | |If RXTHIEN bit is enabled, interrupt occur. + * |[8] |TXUDFIEN |Transmit FIFO Underflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occur if this bit is set to 1 and TXUDIF (I2S_STATUS0[16]) flag is set to 1. + * |[9] |TXOVFIEN |Transmit FIFO Overflow Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIF (I2S_STATUS0[17]) flag is set to 1. + * |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH (I2S_CTL1[11:8]). + * |[16] |CH0ZCIEN |Channel0 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel0 zero-cross. + * | | |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[17] |CH1ZCIEN |Channel1 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel1 zero-cross. + * | | |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[18] |CH2ZCIEN |Channel2 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel2 zero-cross. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[19] |CH3ZCIEN |Channel3 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel3 zero-cross. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[20] |CH4ZCIEN |Channel4 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel4 zero-cross. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[21] |CH5ZCIEN |Channel5 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel5 zero-cross. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[22] |CH6ZCIEN |Channel6 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel6 zero-cross. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[23] |CH7ZCIEN |Channel7 Zero-cross Interrupt Enable Control + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note 1: Interrupt occurs if this bit is set to 1 and channel7 zero-cross. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * @var I2S_T::STATUS0 + * Offset: 0x0C I2S Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SINT |I2S Interrupt Flag (Read Only) + * | | |0 = No I2S interrupt. + * | | |1 = I2S interrupt. + * | | |Note: It is wire-OR of I2STXINT and I2SRXINT bits. + * |[1] |I2SRXINT |I2S Receive Interrupt (Read Only) + * | | |0 = No receive interrupt. + * | | |1 = Receive interrupt. + * |[2] |I2STXINT |I2S Transmit Interrupt (Read Only) + * | | |0 = No transmit interrupt. + * | | |1 = Transmit interrupt. + * |[5:3] |DATACH |Transmission Data Channel (Read Only) + * | | |This bit fields are used to indicate which audio channel is current transmit data belong. + * | | |000 = channel0 (means left channel while 2-channel I2S/PCM mode). + * | | |001 = channel1 (means right channel while 2-channel I2S/PCM mode). + * | | |010 = channel2 (available while 4-channel TDM PCM mode). + * | | |011 = channel3 (available while 4-channel TDM PCM mode). + * | | |100 = channel4 (available while 6-channel TDM PCM mode). + * | | |101 = channel5 (available while 6-channel TDM PCM mode). + * | | |110 = channel6 (available while 8-channel TDM PCM mode). + * | | |111 = channel7 (available while 8-channel TDM PCM mode). + * |[8] |RXUDIF |Receive FIFO Underflow Interrupt Flag + * | | |0 = No underflow occur. + * | | |1 = Underflow occur. + * | | |Note 1: When receive FIFO is empty, and software reads the receive FIFO again + * | | |This bit will be set to 1, and it indicates underflow situation occurs. + * | | |Note 2: Write 1 to clear this bit to zero + * |[9] |RXOVIF |Receive FIFO Overflow Interrupt Flag + * | | |0 = No overflow occur. + * | | |1 = Overflow occur. + * | | |Note 1: When receive FIFO is full and receive hardware attempt to write data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote. + * | | |Note 2: Write 1 to clear this bit to 0. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is not higher than threshold level. + * | | |1 = Data word(s) in FIFO is higher than threshold level. + * | | |Note: When data word(s) in receive FIFO is higher than threshold value set in RXTH (I2S_CTL1[19:16]) the RXTHIF bit becomes to 1 + * | | |It keeps at 1 till RXCNT (I2S_STATUS1[20:16]) is not higher than RXTH (I2S_CTL1[19:16]) after software read RXFIFO register. + * |[11] |RXFULL |Receive FIFO Full (Read Only) + * | | |0 = Not full. + * | | |1 = Full. + * | | |Note: This bit reflects data words number in receive FIFO is 16. + * |[12] |RXEMPTY |Receive FIFO Empty (Read Only) + * | | |0 = Not empty. + * | | |1 = Empty. + * | | |Note: This bit reflects data words number in receive FIFO is 0. + * |[16] |TXUDIF |Transmit FIFO Underflow Interrupt Flag + * | | |0 = No underflow. + * | | |1 = Underflow. + * | | |Note 1: This bit will be set to 1 when shift logic hardware read data from transmitting FIFO and the filling data level in transmitting FIFO is not enough for one audio frame. + * | | |Note 2: Write 1 to clear this bit to 0. + * |[17] |TXOVIF |Transmit FIFO Overflow Interrupt Flag + * | | |0 = No overflow. + * | | |1 = Overflow. + * | | |Note 1: Write data to transmit FIFO when it is full and this bit set to 1. + * | | |Note 2: Write 1 to clear this bit to 0. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = Data word(s) in FIFO is higher than threshold level. + * | | |1 = Data word(s) in FIFO is equal or lower than threshold level. + * | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH (I2S_CTL1[11:8]) the TXTHIF bit becomes to 1 + * | | |It keeps at 1 till TXCNT (I2S_STATUS1[12:8]) is higher than TXTH (I2S_CTL1[11:8]) after software write TXFIFO register. + * |[19] |TXFULL |Transmit FIFO Full (Read Only) + * | | |0 = Not full. + * | | |1 = Full. + * | | |Note: This bit reflects data words number in transmit FIFO is 16. + * |[20] |TXEMPTY |Transmit FIFO Empty (Read Only) + * | | |0 = Not empty. + * | | |1 = Empty. + * | | |Note: This bit reflects data words number in transmit FIFO is 0. + * |[21] |TXBUSY |Transmit Busy (Read Only) + * | | |0 = Transmit shift buffer is empty. + * | | |1 = Transmit shift buffer is busy. + * | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out + * | | |And set to 1 when 1st data is load to shift buffer + * @var I2S_T::TXFIFO + * Offset: 0x10 I2S Transmit FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TXFIFO |Transmit FIFO Bits + * | | |I2S contains 16 words (16x32 bit) data buffer for data transmit + * | | |Write data to this register to prepare data for transmit + * | | |The remaining word number is indicated by TXCNT (I2S_STATUS1[12:8]). + * @var I2S_T::RXFIFO + * Offset: 0x14 I2S Receive FIFO Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RXFIFO |Receive FIFO Bits + * | | |I2S contains 16 words (16x32 bit) data buffer for data receive + * | | |Read this register to get data in FIFO + * | | |The remaining data word number is indicated by RXCNT (I2S_STATUS1[20:16]). + * @var I2S_T::CTL1 + * Offset: 0x20 I2S Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCEN |Channel0 Zero-cross Detection Enable Control + * | | |0 = channel0 zero-cross detect Disabled. + * | | |1 = channel0 zero-cross detect Enabled. + * | | |Note 1: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note 2: If this bit is set to 1, when channel0 data sign bit change or next shift data bits are all zero then CH0ZCIF(I2S_STATUS1[0]) flag is set to 1. + * | | |Note 3: If CH0ZCIF Flag is set to 1, the channel0 will be mute. + * |[1] |CH1ZCEN |Channel1 Zero-cross Detect Enable Control + * | | |0 = channel1 zero-cross detect Disabled. + * | | |1 = channel1 zero-cross detect Enabled. + * | | |Note 1: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * | | |Note 2: If this bit is set to 1, when channel1 data sign bit change or next shift data bits are all zero then CH1ZCIF(I2S_STATUS1[1]) flag is set to 1. + * | | |Note 3: If CH1ZCIF Flag is set to 1, the channel1 will be mute. + * |[2] |CH2ZCEN |Channel2 Zero-cross Detect Enable Control + * | | |0 = channel2 zero-cross detect Disabled. + * | | |1 = channel2 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel2 data sign bit change or next shift data bits are all zero then CH2ZCIF(I2S_STATUS1[2]) flag is set to 1. + * | | |Note 3: If CH2ZCIF Flag is set to 1, the channel2 will be mute. + * |[3] |CH3ZCEN |Channel3 Zero-cross Detect Enable Control + * | | |0 = channel3 zero-cross detect Disabled. + * | | |1 = channel3 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel3 data sign bit change or next shift data bits are all zero then CH3ZCIF(I2S_STATUS1[3]) flag is set to 1. + * | | |Note 3: If CH3ZCIF Flag is set to 1, the channel3 will be mute. + * |[4] |CH4ZCEN |Channel4 Zero-cross Detect Enable Control + * | | |0 = channel4 zero-cross detect Disabled. + * | | |1 = channel4 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel4 data sign bit change or next shift data bits are all zero then CH4ZCIF(I2S_STATUS1[4]) flag is set to 1. + * | | |Note 3: If CH4ZCIF Flag is set to 1, the channel4 will be mute. + * |[5] |CH5ZCEN |Channel5 Zero-cross Detect Enable Control + * | | |0 = channel5 zero-cross detect Disabled. + * | | |1 = channel5 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel5 data sign bit change or next shift data bits are all zero then CH5ZCIF(I2S_STATUS1[5]) flag is set to 1. + * | | |Note 3: If CH5ZCIF Flag is set to 1, the channel5 will be mute. + * |[6] |CH6ZCEN |Channel6 Zero-cross Detect Enable Control + * | | |0 = channel6 zero-cross detect Disabled. + * | | |1 = channel6 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel6 data sign bit change or next shift data bits are all zero then CH6ZCIF(I2S_STATUS1[6]) flag is set to 1. + * | | |Note 3: If CH6ZCIF Flag is set to 1, the channel6 will be mute. + * |[7] |CH7ZCEN |Channel7 Zero-cross Detect Enable Control + * | | |0 = channel7 zero-cross detect Disabled. + * | | |1 = channel7 zero-cross detect Enabled. + * | | |Note 1: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * | | |Note 2: If this bit is set to 1, when channel7 data sign bit change or next shift data bits are all zero then CH7ZCIF (I2S_STATUS1[7]) flag is set to 1. + * | | |Note 3: If CH7ZCIF Flag is set to 1, the channel7 will be mute. + * |[11:8] |TXTH |Transmit FIFO Threshold Level + * | | |0000 = 0 data word in transmit FIFO. + * | | |0001 = 1 data word in transmit FIFO. + * | | |0010 = 2 data words in transmit FIFO. + * | | |... + * | | |1110 = 14 data words in transmit FIFO. + * | | |1111 = 15 data words in transmit FIFO. + * | | |Note: If remain data word number in transmit FIFO is the same or less than threshold level then TXTHIF (I2S_STATUS0[18]) flag is set. + * |[19:16] |RXTH |Receive FIFO Threshold Level + * | | |0000 = 1 data word in receive FIFO. + * | | |0001 = 2 data words in receive FIFO. + * | | |0010 = 3 data words in receive FIFO. + * | | |... + * | | |1110 = 15 data words in receive FIFO. + * | | |1111 = 16 data words in receive FIFO. + * | | |Note: When received data word number in receive buffer is greater than threshold level then RXTHIF (I2S_STATUS0[10]) flag is set. + * |[24] |PBWIDTH |Peripheral Bus Data Width Selection + * | | |This bit is used to choice the available data width of APB bus + * | | |It must be set to 1 while PDMA function is enable and it is set to 16-bit transmission mode + * | | |0 = 32 bits data width. + * | | |1 = 16 bits data width. + * | | |Note 1: If PBWIDTH=1, the low 16 bits of 32-bit data bus are available. + * | | |Note 2: If PBWIDTH=1, the transmitting FIFO level will be increased after two FIFO write operations. + * | | |Note 3: If PBWIDTH=1, the receiving FIFO level will be decreased after two FIFO read operations. + * |[25] |PB16ORD |FIFO Read/Write Order in 16-bit Width of Peripheral Bus + * | | |When PBWIDTH = 1, the data FIFO will be increased or decreased by two peripheral bus access + * | | |This bit is used to select the order of FIFO access operations to meet the 32-bit transmitting/receiving FIFO entries. + * | | |0 = Low 16-bit read/write access first. + * | | |1 = High 16-bit read/write access first. + * | | |Note: This bit is available while PBWIDTH = 1. + * @var I2S_T::STATUS1 + * Offset: 0x24 I2S Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CH0ZCIF |Channel0 Zero-cross Interrupt Flag + * | | |It indicates channel0 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel0. + * | | |1 = Channel0 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Channel0 also means left audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[1] |CH1ZCIF |Channel1 Zero-cross Interrupt Flag + * | | |It indicates channel1 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel1. + * | | |1 = Channel1 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Channel1 also means right audio channel while I2S (FORMAT[2]=0) or 2-channel PCM mode. + * |[2] |CH2ZCIF |Channel2 Zero-cross Interrupt Flag + * | | |It indicates channel2 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel2. + * | | |1 = Channel2 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[3] |CH3ZCIF |Channel3 Zero-cross Interrupt Flag + * | | |It indicates channel3 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel3. + * | | |1 = Channel3 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[4] |CH4ZCIF |Channel4 Zero-cross Interrupt Flag + * | | |It indicates channel4 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel4. + * | | |1 = Channel4 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[5] |CH5ZCIF |Channel5 Zero-cross Interrupt Flag + * | | |It indicates channel5 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel5. + * | | |1 = Channel5 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[6] |CH6ZCIF |Channel6 Zero-cross Interrupt Flag + * | | |It indicates channel6 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel6. + * | | |1 = Channel6 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[7] |CH7ZCIF |Channel7 Zero-cross Interrupt Flag + * | | |It indicates channel7 next sample data sign bit is changed or all data bits are zero. + * | | |0 = No zero-cross in channel7. + * | | |1 = Channel7 zero-cross is detected. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: This bit is available while multi-channel PCM mode and TDMCHNUM (I2S_CTL0[31:30]) = 0x1, 0x2, 0x3. + * |[12:8] |TXCNT |Transmit FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in transmit FIFO. + * | | |00000 = No data. + * | | |00001 = 1 word in transmit FIFO. + * | | |00010 = 2 words in transmit FIFO. + * | | |... + * | | |01110 = 14 words in transmit FIFO. + * | | |01111 = 15 words in transmit FIFO. + * | | |10000 = 16 words in transmit FIFO. + * | | |Others are reserved. + * |[20:16] |RXCNT |Receive FIFO Level (Read Only) + * | | |These bits indicate the number of available entries in receive FIFO. + * | | |00000 = No data. + * | | |00001 = 1 word in receive FIFO. + * | | |00010 = 2 words in receive FIFO. + * | | |... + * | | |01110 = 14 words in receive FIFO. + * | | |01111 = 15 words in receive FIFO. + * | | |10000 = 16 words in receive FIFO. + * | | |Others are reserved. + */ + __IO uint32_t CTL0; /*!< [0x0000] I2S Control Register 0 */ + __IO uint32_t CLKDIV; /*!< [0x0004] I2S Clock Divider Register */ + __IO uint32_t IEN; /*!< [0x0008] I2S Interrupt Enable Register */ + __IO uint32_t STATUS0; /*!< [0x000c] I2S Status Register 0 */ + __O uint32_t TXFIFO; /*!< [0x0010] I2S Transmit FIFO Register */ + __I uint32_t RXFIFO; /*!< [0x0014] I2S Receive FIFO Register */ + __I uint32_t RESERVE0[2]; + __IO uint32_t CTL1; /*!< [0x0020] I2S Control Register 1 */ + __IO uint32_t STATUS1; /*!< [0x0024] I2S Status Register 1 */ + +} I2S_T; + +/** + @addtogroup I2S_CONST I2S Bit Field Definition + Constant Definitions for I2S Controller + @{ +*/ + +#define I2S_CTL0_I2SEN_Pos (0) /*!< I2S_T::CTL0: I2SEN Position */ +#define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) /*!< I2S_T::CTL0: I2SEN Mask */ + +#define I2S_CTL0_TXEN_Pos (1) /*!< I2S_T::CTL0: TXEN Position */ +#define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) /*!< I2S_T::CTL0: TXEN Mask */ + +#define I2S_CTL0_RXEN_Pos (2) /*!< I2S_T::CTL0: RXEN Position */ +#define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) /*!< I2S_T::CTL0: RXEN Mask */ + +#define I2S_CTL0_MUTE_Pos (3) /*!< I2S_T::CTL0: MUTE Position */ +#define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) /*!< I2S_T::CTL0: MUTE Mask */ + +#define I2S_CTL0_DATWIDTH_Pos (4) /*!< I2S_T::CTL0: DATWIDTH Position */ +#define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) /*!< I2S_T::CTL0: DATWIDTH Mask */ + +#define I2S_CTL0_MONO_Pos (6) /*!< I2S_T::CTL0: MONO Position */ +#define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) /*!< I2S_T::CTL0: MONO Mask */ + +#define I2S_CTL0_ORDER_Pos (7) /*!< I2S_T::CTL0: ORDER Position */ +#define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) /*!< I2S_T::CTL0: ORDER Mask */ + +#define I2S_CTL0_SLAVE_Pos (8) /*!< I2S_T::CTL0: SLAVE Position */ +#define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) /*!< I2S_T::CTL0: SLAVE Mask */ + +#define I2S_CTL0_MCLKEN_Pos (15) /*!< I2S_T::CTL0: MCLKEN Position */ +#define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) /*!< I2S_T::CTL0: MCLKEN Mask */ + +#define I2S_CTL0_TXFBCLR_Pos (18) /*!< I2S_T::CTL0: TXFBCLR Position */ +#define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) /*!< I2S_T::CTL0: TXFBCLR Mask */ + +#define I2S_CTL0_RXFBCLR_Pos (19) /*!< I2S_T::CTL0: RXFBCLR Position */ +#define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) /*!< I2S_T::CTL0: RXFBCLR Mask */ + +#define I2S_CTL0_TXPDMAEN_Pos (20) /*!< I2S_T::CTL0: TXPDMAEN Position */ +#define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) /*!< I2S_T::CTL0: TXPDMAEN Mask */ + +#define I2S_CTL0_RXPDMAEN_Pos (21) /*!< I2S_T::CTL0: RXPDMAEN Position */ +#define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) /*!< I2S_T::CTL0: RXPDMAEN Mask */ + +#define I2S_CTL0_RXLCH_Pos (23) /*!< I2S_T::CTL0: RXLCH Position */ +#define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) /*!< I2S_T::CTL0: RXLCH Mask */ + +#define I2S_CTL0_FORMAT_Pos (24) /*!< I2S_T::CTL0: FORMAT Position */ +#define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) /*!< I2S_T::CTL0: FORMAT Mask */ + +#define I2S_CTL0_PCMSYNC_Pos (27) /*!< I2S_T::CTL0: PCMSYNC Position */ +#define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) /*!< I2S_T::CTL0: PCMSYNC Mask */ + +#define I2S_CTL0_CHWIDTH_Pos (28) /*!< I2S_T::CTL0: CHWIDTH Position */ +#define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) /*!< I2S_T::CTL0: CHWIDTH Mask */ + +#define I2S_CTL0_TDMCHNUM_Pos (30) /*!< I2S_T::CTL0: TDMCHNUM Position */ +#define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) /*!< I2S_T::CTL0: TDMCHNUM Mask */ + +#define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S_T::CLKDIV: MCLKDIV Position */ +#define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S_T::CLKDIV: MCLKDIV Mask */ + +#define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S_T::CLKDIV: BCLKDIV Position */ +#define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S_T::CLKDIV: BCLKDIV Mask */ + +#define I2S_IEN_RXUDFIEN_Pos (0) /*!< I2S_T::IEN: RXUDFIEN Position */ +#define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) /*!< I2S_T::IEN: RXUDFIEN Mask */ + +#define I2S_IEN_RXOVFIEN_Pos (1) /*!< I2S_T::IEN: RXOVFIEN Position */ +#define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) /*!< I2S_T::IEN: RXOVFIEN Mask */ + +#define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S_T::IEN: RXTHIEN Position */ +#define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S_T::IEN: RXTHIEN Mask */ + +#define I2S_IEN_TXUDFIEN_Pos (8) /*!< I2S_T::IEN: TXUDFIEN Position */ +#define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) /*!< I2S_T::IEN: TXUDFIEN Mask */ + +#define I2S_IEN_TXOVFIEN_Pos (9) /*!< I2S_T::IEN: TXOVFIEN Position */ +#define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) /*!< I2S_T::IEN: TXOVFIEN Mask */ + +#define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S_T::IEN: TXTHIEN Position */ +#define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S_T::IEN: TXTHIEN Mask */ + +#define I2S_IEN_CH0ZCIEN_Pos (16) /*!< I2S_T::IEN: CH0ZCIEN Position */ +#define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) /*!< I2S_T::IEN: CH0ZCIEN Mask */ + +#define I2S_IEN_CH1ZCIEN_Pos (17) /*!< I2S_T::IEN: CH1ZCIEN Position */ +#define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) /*!< I2S_T::IEN: CH1ZCIEN Mask */ + +#define I2S_IEN_CH2ZCIEN_Pos (18) /*!< I2S_T::IEN: CH2ZCIEN Position */ +#define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) /*!< I2S_T::IEN: CH2ZCIEN Mask */ + +#define I2S_IEN_CH3ZCIEN_Pos (19) /*!< I2S_T::IEN: CH3ZCIEN Position */ +#define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) /*!< I2S_T::IEN: CH3ZCIEN Mask */ + +#define I2S_IEN_CH4ZCIEN_Pos (20) /*!< I2S_T::IEN: CH4ZCIEN Position */ +#define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) /*!< I2S_T::IEN: CH4ZCIEN Mask */ + +#define I2S_IEN_CH5ZCIEN_Pos (21) /*!< I2S_T::IEN: CH5ZCIEN Position */ +#define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) /*!< I2S_T::IEN: CH5ZCIEN Mask */ + +#define I2S_IEN_CH6ZCIEN_Pos (22) /*!< I2S_T::IEN: CH6ZCIEN Position */ +#define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) /*!< I2S_T::IEN: CH6ZCIEN Mask */ + +#define I2S_IEN_CH7ZCIEN_Pos (23) /*!< I2S_T::IEN: CH7ZCIEN Position */ +#define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) /*!< I2S_T::IEN: CH7ZCIEN Mask */ + +#define I2S_STATUS0_I2SINT_Pos (0) /*!< I2S_T::STATUS0: I2SINT Position */ +#define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) /*!< I2S_T::STATUS0: I2SINT Mask */ + +#define I2S_STATUS0_I2SRXINT_Pos (1) /*!< I2S_T::STATUS0: I2SRXINT Position */ +#define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) /*!< I2S_T::STATUS0: I2SRXINT Mask */ + +#define I2S_STATUS0_I2STXINT_Pos (2) /*!< I2S_T::STATUS0: I2STXINT Position */ +#define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) /*!< I2S_T::STATUS0: I2STXINT Mask */ + +#define I2S_STATUS0_DATACH_Pos (3) /*!< I2S_T::STATUS0: DATACH Position */ +#define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) /*!< I2S_T::STATUS0: DATACH Mask */ + +#define I2S_STATUS0_RXUDIF_Pos (8) /*!< I2S_T::STATUS0: RXUDIF Position */ +#define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) /*!< I2S_T::STATUS0: RXUDIF Mask */ + +#define I2S_STATUS0_RXOVIF_Pos (9) /*!< I2S_T::STATUS0: RXOVIF Position */ +#define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) /*!< I2S_T::STATUS0: RXOVIF Mask */ + +#define I2S_STATUS0_RXTHIF_Pos (10) /*!< I2S_T::STATUS0: RXTHIF Position */ +#define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) /*!< I2S_T::STATUS0: RXTHIF Mask */ + +#define I2S_STATUS0_RXFULL_Pos (11) /*!< I2S_T::STATUS0: RXFULL Position */ +#define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) /*!< I2S_T::STATUS0: RXFULL Mask */ + +#define I2S_STATUS0_RXEMPTY_Pos (12) /*!< I2S_T::STATUS0: RXEMPTY Position */ +#define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) /*!< I2S_T::STATUS0: RXEMPTY Mask */ + +#define I2S_STATUS0_TXUDIF_Pos (16) /*!< I2S_T::STATUS0: TXUDIF Position */ +#define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) /*!< I2S_T::STATUS0: TXUDIF Mask */ + +#define I2S_STATUS0_TXOVIF_Pos (17) /*!< I2S_T::STATUS0: TXOVIF Position */ +#define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) /*!< I2S_T::STATUS0: TXOVIF Mask */ + +#define I2S_STATUS0_TXTHIF_Pos (18) /*!< I2S_T::STATUS0: TXTHIF Position */ +#define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) /*!< I2S_T::STATUS0: TXTHIF Mask */ + +#define I2S_STATUS0_TXFULL_Pos (19) /*!< I2S_T::STATUS0: TXFULL Position */ +#define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) /*!< I2S_T::STATUS0: TXFULL Mask */ + +#define I2S_STATUS0_TXEMPTY_Pos (20) /*!< I2S_T::STATUS0: TXEMPTY Position */ +#define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) /*!< I2S_T::STATUS0: TXEMPTY Mask */ + +#define I2S_STATUS0_TXBUSY_Pos (21) /*!< I2S_T::STATUS0: TXBUSY Position */ +#define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) /*!< I2S_T::STATUS0: TXBUSY Mask */ + +#define I2S_TXFIFO_TXFIFO_Pos (0) /*!< I2S_T::TXFIFO: TXFIFO Position */ +#define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) /*!< I2S_T::TXFIFO: TXFIFO Mask */ + +#define I2S_RXFIFO_RXFIFO_Pos (0) /*!< I2S_T::RXFIFO: RXFIFO Position */ +#define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) /*!< I2S_T::RXFIFO: RXFIFO Mask */ + +#define I2S_CTL1_CH0ZCEN_Pos (0) /*!< I2S_T::CTL1: CH0ZCEN Position */ +#define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) /*!< I2S_T::CTL1: CH0ZCEN Mask */ + +#define I2S_CTL1_CH1ZCEN_Pos (1) /*!< I2S_T::CTL1: CH1ZCEN Position */ +#define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) /*!< I2S_T::CTL1: CH1ZCEN Mask */ + +#define I2S_CTL1_CH2ZCEN_Pos (2) /*!< I2S_T::CTL1: CH2ZCEN Position */ +#define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) /*!< I2S_T::CTL1: CH2ZCEN Mask */ + +#define I2S_CTL1_CH3ZCEN_Pos (3) /*!< I2S_T::CTL1: CH3ZCEN Position */ +#define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) /*!< I2S_T::CTL1: CH3ZCEN Mask */ + +#define I2S_CTL1_CH4ZCEN_Pos (4) /*!< I2S_T::CTL1: CH4ZCEN Position */ +#define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) /*!< I2S_T::CTL1: CH4ZCEN Mask */ + +#define I2S_CTL1_CH5ZCEN_Pos (5) /*!< I2S_T::CTL1: CH5ZCEN Position */ +#define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) /*!< I2S_T::CTL1: CH5ZCEN Mask */ + +#define I2S_CTL1_CH6ZCEN_Pos (6) /*!< I2S_T::CTL1: CH6ZCEN Position */ +#define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) /*!< I2S_T::CTL1: CH6ZCEN Mask */ + +#define I2S_CTL1_CH7ZCEN_Pos (7) /*!< I2S_T::CTL1: CH7ZCEN Position */ +#define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) /*!< I2S_T::CTL1: CH7ZCEN Mask */ + +#define I2S_CTL1_TXTH_Pos (8) /*!< I2S_T::CTL1: TXTH Position */ +#define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) /*!< I2S_T::CTL1: TXTH Mask */ + +#define I2S_CTL1_RXTH_Pos (16) /*!< I2S_T::CTL1: RXTH Position */ +#define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) /*!< I2S_T::CTL1: RXTH Mask */ + +#define I2S_CTL1_PBWIDTH_Pos (24) /*!< I2S_T::CTL1: PBWIDTH Position */ +#define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) /*!< I2S_T::CTL1: PBWIDTH Mask */ + +#define I2S_CTL1_PB16ORD_Pos (25) /*!< I2S_T::CTL1: PB16ORD Position */ +#define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) /*!< I2S_T::CTL1: PB16ORD Mask */ + +#define I2S_STATUS1_CH0ZCIF_Pos (0) /*!< I2S_T::STATUS1: CH0ZCIF Position */ +#define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) /*!< I2S_T::STATUS1: CH0ZCIF Mask */ + +#define I2S_STATUS1_CH1ZCIF_Pos (1) /*!< I2S_T::STATUS1: CH1ZCIF Position */ +#define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) /*!< I2S_T::STATUS1: CH1ZCIF Mask */ + +#define I2S_STATUS1_CH2ZCIF_Pos (2) /*!< I2S_T::STATUS1: CH2ZCIF Position */ +#define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) /*!< I2S_T::STATUS1: CH2ZCIF Mask */ + +#define I2S_STATUS1_CH3ZCIF_Pos (3) /*!< I2S_T::STATUS1: CH3ZCIF Position */ +#define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) /*!< I2S_T::STATUS1: CH3ZCIF Mask */ + +#define I2S_STATUS1_CH4ZCIF_Pos (4) /*!< I2S_T::STATUS1: CH4ZCIF Position */ +#define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) /*!< I2S_T::STATUS1: CH4ZCIF Mask */ + +#define I2S_STATUS1_CH5ZCIF_Pos (5) /*!< I2S_T::STATUS1: CH5ZCIF Position */ +#define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) /*!< I2S_T::STATUS1: CH5ZCIF Mask */ + +#define I2S_STATUS1_CH6ZCIF_Pos (6) /*!< I2S_T::STATUS1: CH6ZCIF Position */ +#define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) /*!< I2S_T::STATUS1: CH6ZCIF Mask */ + +#define I2S_STATUS1_CH7ZCIF_Pos (7) /*!< I2S_T::STATUS1: CH7ZCIF Position */ +#define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) /*!< I2S_T::STATUS1: CH7ZCIF Mask */ + +#define I2S_STATUS1_TXCNT_Pos (8) /*!< I2S_T::STATUS1: TXCNT Position */ +#define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) /*!< I2S_T::STATUS1: TXCNT Mask */ + +#define I2S_STATUS1_RXCNT_Pos (16) /*!< I2S_T::STATUS1: RXCNT Position */ +#define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) /*!< I2S_T::STATUS1: RXCNT Mask */ + +/**@}*/ /* I2S_CONST */ +/**@}*/ /* end of I2S register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __I2S_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/keystore_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/keystore_reg.h new file mode 100644 index 0000000000..42b539ce81 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/keystore_reg.h @@ -0,0 +1,384 @@ +/**************************************************************************//** + * @file keystore_reg.h + * @version V1.00 + * @brief Key store register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __KEYSTORE_REG_H__ +#define __KEYSTORE_REG_H__ + + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Key Store -------------------------*/ +/** + @addtogroup KS Key Store(KS) + Memory Mapped Structure for KS Controller + @{ +*/ + +typedef struct +{ + + +/** + * @var KS_T::CTL + * Offset: 0x00 Key Store Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |START |Key Store Start Control Bit + * | | |0 = No operation. + * | | |1 = Start the setted operation. + * |[3:1] |OPMODE |Key Store Operation Mode + * | | |000 = Read operation. + * | | |001 = Create operation. + * | | |010 = Erase one key operation (only for key is in SRAM). + * | | |011 = Erase all keys operation (only for SRAM and Flash). + * | | |100 = Revoke key operation. + * | | |101 = Data Remanence prevention opertation (only for SRAM). + * | | |Others = reserved. + * |[7] |CONT |Read/Write Key Continue Bit + * | | |0 = Read/Write key operation is not continuous to previous operation. + * | | |1 = Read/Write key operation is continuous to previous operation. + * |[8] |INIT |Key Store Initialization + * | | |User should to check BUSY(KS_STS[2]) is 0, and then write 1 to this bit and START(KS_CTL[0[), the Key Store will start to be initialized. + * | | |After KeyStore is initialized, INIT will be cleared. + * | | |Note: Before executing INIT, user must to checks KS(SYS_SRAMPC1) is 00. + * |[10] |SILENT |Silent Access Enable Bit + * | | |0 = Silent Access Disabled. + * | | |1 = Silent Access Enabled. + * |[11] |SCMB |Data Scramble Enable Bit + * | | |0 = Data Scramble Disabled. + * | | |1 = Data Scramble Enabled. + * |[15] |IEN |Key Store Interrupt Enable Bit + * | | |0 = Key Store Interrupt Disabled. + * | | |1 = Key Store Interrupt Enabled. + * @var KS_T::METADATA + * Offset: 0x04 Key Store Metadata Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SEC |Secure Key Selection Bit + * | | |0 = Set key as the non-secure key. + * | | |1 = Set key as the secure key. + * |[1] |PRIV |Privilege Key Selection Bit + * | | |0 = Set key as the non-privilege key. + * | | |1 = Set key as the privilege key. + * |[2] |READABLE |Key Readable Control Bit + * | | |0 = key is un-readable. + * | | |1 = key is readable. + * |[3] |RVK |Key Revoke Control Bit + * | | |0 = Key current selected will not be changed. + * | | |1 = key current selected will be change to revoked state. + * |[4] |BS |Booting State Selection Bit + * | | |0 = Set key used at all state. + * | | |1 = Set key used at boot loader state 1 (BL1 state). + * |[12:8] |SIZE |Key Size Selection Bits + * | | |00000 = 128 bits. + * | | |00001 = 163 bits. + * | | |00010 = 192 bits. + * | | |00011 = 224 bits. + * | | |00100 = 233 bits. + * | | |00101 = 255 bits. + * | | |00110 = 256 bits. + * | | |00111 = 283 bits. + * | | |01000 = 384 bits. + * | | |01001 = 409 bits. + * | | |01010 = 512 bits. + * | | |01011 = 521 bits. + * | | |01100 = 571 bits. + * | | |10000 = 1024 bits. + * | | |10001 = 1536 bits. + * | | |10010 = 2048 bits. + * | | |10011 = 3072 bits. + * | | |10100 = 4096 bits. + * | | |Others = reserved. + * |[18:16] |OWNER |Key Owner Selection Bits + * | | |000 = Only for AES used. + * | | |001 = Only for HMAC engine used. + * | | |010 = Only for RSA engine exponential used (private key). + * | | |011 = Only for RSA engine middle data used. + * | | |100 = Only for ECC engine used. + * | | |101 = Only for CPU engine use. + * | | |Others = reserved. + * |[25:20] |NUMBER |Key Number + * | | |Before read or erase one key operation starts, user should write the key number to be operated + * | | |When create operation is finished, user can read these bits to get its key number. + * |[31:30] |DST |Key Location Selection Bits + * | | |00 = Key is in SRAM. + * | | |01 = Key is in Flash. + * | | |10 = Key is in OTP. + * | | |Others = reserved. + * @var KS_T::STS + * Offset: 0x08 Key Store Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IF |Key Store Finish Interrupt Flag + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No Key Store interrupt. + * | | |1 = Key Store operation done interrupt. + * |[1] |EIF |Key Store Error Flag + * | | |This bit is cleared by writing 1 and it has no effect by writing 0. + * | | |0 = No Key Store error. + * | | |1 = Key Store error interrupt. + * |[2] |BUSY |Key Store Busy Flag (RO) + * | | |0 = KeyStore is idle or finished. + * | | |1 = KeyStore is busy. + * |[3] |SRAMFULL |Key Storage at SRAM Full Status Bit (RO) + * | | |0 = Key Storage at SRAM is not full. + * | | |1 = Key Storage at SRAM is full. + * |[4] |FLASHFULL |Key Storage at Flash Full Status Bit (RO) + * | | |0 = Key Storage at Flash is not full. + * | | |1 = Key Storage at Flash is full. + * |[7] |INITDONE |Key Store Initialization Done Status (RO) + * | | |0 = Key Store is un-initialized. + * | | |1 = Key Store is initialized. + * |[8] |RAMINV |Key Store SRAM Invert Status (RO) + * | | |0 = Key Store key in SRAM is normal. + * | | |1 = Key Store key in SRAM is inverted. + * @var KS_T::REMAIN + * Offset: 0x0C Key Store Remaining Space Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12:0] |RRMNG |Key Store SRAM Remaining Space + * | | |The RRMNG shows the remaining byte count space for SRAM. + * |[27:16] |FRMNG |Key Store Flash Remaining Space + * | | |The FRMNG shows the remaining byte count space for Flash. + * @var KS_T::SCMBKEY + * Offset: 0x10-0x1C Key Store Scramble Key Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SCMBKEY |Key Store Scramble Key + * | | |When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store + * | | |If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function. + * @var KS_T::KEY + * Offset: 0x20-0x3C Key Store Entry Key Word Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |KEY |Key Data + * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. + * @var KS_T::OTPSTS + * Offset: 0x40 Key Store OTP Keys Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |KEY0 |OTP Key 0 Used Status + * | | |0 = OTP key 0 is unused. + * | | |1 = OTP key 0 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[1] |KEY1 |OTP Key 1 Used Status + * | | |0 = OTP key 1 is unused. + * | | |1 = OTP key 1 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[2] |KEY2 |OTP Key 2 Used Status + * | | |0 = OTP key 2 is unused. + * | | |1 = OTP key 2 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[3] |KEY3 |OTP Key 3 Used Status + * | | |0 = OTP key 3 is unused. + * | | |1 = OTP key 3 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[4] |KEY4 |OTP Key 4 Used Status + * | | |0 = OTP key 4 is unused. + * | | |1 = OTP key 4 is used. + * | | |Note: If chip is changed to RMA stage, existing key will be revoked after initialization. + * |[5] |KEY5 |OTP Key 5 Used Status + * | | |0 = OTP key 5 is unused. + * | | |1 = OTP key 5 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[6] |KEY6 |OTP Key 6 Used Status + * | | |0 = OTP key 6 is unused. + * | | |1 = OTP key 6 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * |[7] |KEY7 |OTP Key 7 Used Status + * | | |0 = OTP key 7 is unused. + * | | |1 = OTP key 7 is used. + * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. + * @var KS_T::REMKCNT + * Offset: 0x44 Key Store Remaining Key Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |RRMKCNT |Key Store SRAM Remaining Key Count + * | | |The RRMKCNT shows the remaining key count for SRAM. + * |[21:16] |FRMKCNT |Key Store Flash Remaining Key Count + * | | |The FRMKCNT shows the remaining key count for Flash. + */ + __IO uint32_t CTL; /*!< [0x0000] Key Store Control Register */ + __IO uint32_t METADATA; /*!< [0x0004] Key Store Metadata Register */ + __IO uint32_t STS; /*!< [0x0008] Key Store Status Register */ + __I uint32_t REMAIN; /*!< [0x000c] Key Store Remaining Space Register */ + __IO uint32_t SCMBKEY[4]; /*!< [0x0010 ~ 0x001c] Key Store Scramble Key Word 0 Register */ + __IO uint32_t KEY[8]; /*!< [0x0020 ~ 0x003c] Key Store Entry Key Word 0 Register */ + __I uint32_t OTPSTS; /*!< [0x0040] Key Store OTP Keys Status Register */ + __I uint32_t REMKCNT; /*!< [0x0044] Key Store Remaining Key Count Register */ + +} KS_T; + +/** + @addtogroup KS_CONST KS Bit Field Definition + Constant Definitions for KS Controller + @{ +*/ + +#define KS_CTL_START_Pos (0) /*!< KS_T::CTL: START Position */ +#define KS_CTL_START_Msk (0x1ul << KS_CTL_START_Pos) /*!< KS_T::CTL: START Mask */ + +#define KS_CTL_OPMODE_Pos (1) /*!< KS_T::CTL: OPMODE Position */ +#define KS_CTL_OPMODE_Msk (0x7ul << KS_CTL_OPMODE_Pos) /*!< KS_T::CTL: OPMODE Mask */ + +#define KS_CTL_CONT_Pos (7) /*!< KS_T::CTL: CONT Position */ +#define KS_CTL_CONT_Msk (0x1ul << KS_CTL_CONT_Pos) /*!< KS_T::CTL: CONT Mask */ + +#define KS_CTL_INIT_Pos (8) /*!< KS_T::CTL: INIT Position */ +#define KS_CTL_INIT_Msk (0x1ul << KS_CTL_INIT_Pos) /*!< KS_T::CTL: INIT Mask */ + +#define KS_CTL_SILENT_Pos (10) /*!< KS_T::CTL: SILENT Position */ +#define KS_CTL_SILENT_Msk (0x1ul << KS_CTL_SILENT_Pos) /*!< KS_T::CTL: SILENT Mask */ + +#define KS_CTL_SCMB_Pos (11) /*!< KS_T::CTL: SCMB Position */ +#define KS_CTL_SCMB_Msk (0x1ul << KS_CTL_SCMB_Pos) /*!< KS_T::CTL: SCMB Mask */ + +#define KS_CTL_IEN_Pos (15) /*!< KS_T::CTL: IEN Position */ +#define KS_CTL_IEN_Msk (0x1ul << KS_CTL_IEN_Pos) /*!< KS_T::CTL: IEN Mask */ + +#define KS_METADATA_SEC_Pos (0) /*!< KS_T::METADATA: SEC Position */ +#define KS_METADATA_SEC_Msk (0x1ul << KS_METADATA_SEC_Pos) /*!< KS_T::METADATA: SEC Mask */ + +#define KS_METADATA_PRIV_Pos (1) /*!< KS_T::METADATA: PRIV Position */ +#define KS_METADATA_PRIV_Msk (0x1ul << KS_METADATA_PRIV_Pos) /*!< KS_T::METADATA: PRIV Mask */ + +#define KS_METADATA_READABLE_Pos (2) /*!< KS_T::METADATA: READABLE Position */ +#define KS_METADATA_READABLE_Msk (0x1ul << KS_METADATA_READABLE_Pos) /*!< KS_T::METADATA: READABLE Mask */ + +#define KS_METADATA_RVK_Pos (3) /*!< KS_T::METADATA: RVK Position */ +#define KS_METADATA_RVK_Msk (0x1ul << KS_METADATA_RVK_Pos) /*!< KS_T::METADATA: RVK Mask */ + +#define KS_METADATA_BS_Pos (4) /*!< KS_T::METADATA: BS Position */ +#define KS_METADATA_BS_Msk (0x1ul << KS_METADATA_BS_Pos) /*!< KS_T::METADATA: BS Mask */ + +#define KS_METADATA_SIZE_Pos (8) /*!< KS_T::METADATA: SIZE Position */ +#define KS_METADATA_SIZE_Msk (0x1ful << KS_METADATA_SIZE_Pos) /*!< KS_T::METADATA: SIZE Mask */ + +#define KS_METADATA_OWNER_Pos (16) /*!< KS_T::METADATA: OWNER Position */ +#define KS_METADATA_OWNER_Msk (0x7ul << KS_METADATA_OWNER_Pos) /*!< KS_T::METADATA: OWNER Mask */ + +#define KS_METADATA_NUMBER_Pos (20) /*!< KS_T::METADATA: NUMBER Position */ +#define KS_METADATA_NUMBER_Msk (0x3ful << KS_METADATA_NUMBER_Pos) /*!< KS_T::METADATA: NUMBER Mask */ + +#define KS_METADATA_DST_Pos (30) /*!< KS_T::METADATA: DST Position */ +#define KS_METADATA_DST_Msk (0x3ul << KS_METADATA_DST_Pos) /*!< KS_T::METADATA: DST Mask */ + +#define KS_STS_IF_Pos (0) /*!< KS_T::STS: IF Position */ +#define KS_STS_IF_Msk (0x1ul << KS_STS_IF_Pos) /*!< KS_T::STS: IF Mask */ + +#define KS_STS_EIF_Pos (1) /*!< KS_T::STS: EIF Position */ +#define KS_STS_EIF_Msk (0x1ul << KS_STS_EIF_Pos) /*!< KS_T::STS: EIF Mask */ + +#define KS_STS_BUSY_Pos (2) /*!< KS_T::STS: BUSY Position */ +#define KS_STS_BUSY_Msk (0x1ul << KS_STS_BUSY_Pos) /*!< KS_T::STS: BUSY Mask */ + +#define KS_STS_SRAMFULL_Pos (3) /*!< KS_T::STS: SRAMFULL Position */ +#define KS_STS_SRAMFULL_Msk (0x1ul << KS_STS_SRAMFULL_Pos) /*!< KS_T::STS: SRAMFULL Mask */ + +#define KS_STS_FLASHFULL_Pos (4) /*!< KS_T::STS: FLASHFULL Position */ +#define KS_STS_FLASHFULL_Msk (0x1ul << KS_STS_FLASHFULL_Pos) /*!< KS_T::STS: FLASHFULL Mask */ + +#define KS_STS_INITDONE_Pos (7) /*!< KS_T::STS: INITDONE Position */ +#define KS_STS_INITDONE_Msk (0x1ul << KS_STS_INITDONE_Pos) /*!< KS_T::STS: INITDONE Mask */ + +#define KS_STS_RAMINV_Pos (8) /*!< KS_T::STS: RAMINV Position */ +#define KS_STS_RAMINV_Msk (0x1ul << KS_STS_RAMINV_Pos) /*!< KS_T::STS: RAMINV Mask */ + +#define KS_REMAIN_RRMNG_Pos (0) /*!< KS_T::REMAIN: RRMNG Position */ +#define KS_REMAIN_RRMNG_Msk (0x1ffful << KS_REMAIN_RRMNG_Pos) /*!< KS_T::REMAIN: RRMNG Mask */ + +#define KS_REMAIN_FRMNG_Pos (16) /*!< KS_T::REMAIN: FRMNG Position */ +#define KS_REMAIN_FRMNG_Msk (0xffful << KS_REMAIN_FRMNG_Pos) /*!< KS_T::REMAIN: FRMNG Mask */ + +#define KS_SCMBKEY0_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY0: SCMBKEY Position */ +#define KS_SCMBKEY0_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY0_SCMBKEY_Pos) /*!< KS_T::SCMBKEY0: SCMBKEY Mask */ + +#define KS_SCMBKEY1_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY1: SCMBKEY Position */ +#define KS_SCMBKEY1_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY1_SCMBKEY_Pos) /*!< KS_T::SCMBKEY1: SCMBKEY Mask */ + +#define KS_SCMBKEY2_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY2: SCMBKEY Position */ +#define KS_SCMBKEY2_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY2_SCMBKEY_Pos) /*!< KS_T::SCMBKEY2: SCMBKEY Mask */ + +#define KS_SCMBKEY3_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY3: SCMBKEY Position */ +#define KS_SCMBKEY3_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY3_SCMBKEY_Pos) /*!< KS_T::SCMBKEY3: SCMBKEY Mask */ + +#define KS_KEY0_KEY_Pos (0) /*!< KS_T::KEY0: KEY Position */ +#define KS_KEY0_KEY_Msk (0xfffffffful << KS_KEY0_KEY_Pos) /*!< KS_T::KEY0: KEY Mask */ + +#define KS_KEY1_KEY_Pos (0) /*!< KS_T::KEY1: KEY Position */ +#define KS_KEY1_KEY_Msk (0xfffffffful << KS_KEY1_KEY_Pos) /*!< KS_T::KEY1: KEY Mask */ + +#define KS_KEY2_KEY_Pos (0) /*!< KS_T::KEY2: KEY Position */ +#define KS_KEY2_KEY_Msk (0xfffffffful << KS_KEY2_KEY_Pos) /*!< KS_T::KEY2: KEY Mask */ + +#define KS_KEY3_KEY_Pos (0) /*!< KS_T::KEY3: KEY Position */ +#define KS_KEY3_KEY_Msk (0xfffffffful << KS_KEY3_KEY_Pos) /*!< KS_T::KEY3: KEY Mask */ + +#define KS_KEY4_KEY_Pos (0) /*!< KS_T::KEY4: KEY Position */ +#define KS_KEY4_KEY_Msk (0xfffffffful << KS_KEY4_KEY_Pos) /*!< KS_T::KEY4: KEY Mask */ + +#define KS_KEY5_KEY_Pos (0) /*!< KS_T::KEY5: KEY Position */ +#define KS_KEY5_KEY_Msk (0xfffffffful << KS_KEY5_KEY_Pos) /*!< KS_T::KEY5: KEY Mask */ + +#define KS_KEY6_KEY_Pos (0) /*!< KS_T::KEY6: KEY Position */ +#define KS_KEY6_KEY_Msk (0xfffffffful << KS_KEY6_KEY_Pos) /*!< KS_T::KEY6: KEY Mask */ + +#define KS_KEY7_KEY_Pos (0) /*!< KS_T::KEY7: KEY Position */ +#define KS_KEY7_KEY_Msk (0xfffffffful << KS_KEY7_KEY_Pos) /*!< KS_T::KEY7: KEY Mask */ + +#define KS_OTPSTS_KEY0_Pos (0) /*!< KS_T::OTPSTS: KEY0 Position */ +#define KS_OTPSTS_KEY0_Msk (0x1ul << KS_OTPSTS_KEY0_Pos) /*!< KS_T::OTPSTS: KEY0 Mask */ + +#define KS_OTPSTS_KEY1_Pos (1) /*!< KS_T::OTPSTS: KEY1 Position */ +#define KS_OTPSTS_KEY1_Msk (0x1ul << KS_OTPSTS_KEY1_Pos) /*!< KS_T::OTPSTS: KEY1 Mask */ + +#define KS_OTPSTS_KEY2_Pos (2) /*!< KS_T::OTPSTS: KEY2 Position */ +#define KS_OTPSTS_KEY2_Msk (0x1ul << KS_OTPSTS_KEY2_Pos) /*!< KS_T::OTPSTS: KEY2 Mask */ + +#define KS_OTPSTS_KEY3_Pos (3) /*!< KS_T::OTPSTS: KEY3 Position */ +#define KS_OTPSTS_KEY3_Msk (0x1ul << KS_OTPSTS_KEY3_Pos) /*!< KS_T::OTPSTS: KEY3 Mask */ + +#define KS_OTPSTS_KEY4_Pos (4) /*!< KS_T::OTPSTS: KEY4 Position */ +#define KS_OTPSTS_KEY4_Msk (0x1ul << KS_OTPSTS_KEY4_Pos) /*!< KS_T::OTPSTS: KEY4 Mask */ + +#define KS_OTPSTS_KEY5_Pos (5) /*!< KS_T::OTPSTS: KEY5 Position */ +#define KS_OTPSTS_KEY5_Msk (0x1ul << KS_OTPSTS_KEY5_Pos) /*!< KS_T::OTPSTS: KEY5 Mask */ + +#define KS_OTPSTS_KEY6_Pos (6) /*!< KS_T::OTPSTS: KEY6 Position */ +#define KS_OTPSTS_KEY6_Msk (0x1ul << KS_OTPSTS_KEY6_Pos) /*!< KS_T::OTPSTS: KEY6 Mask */ + +#define KS_OTPSTS_KEY7_Pos (7) /*!< KS_T::OTPSTS: KEY7 Position */ +#define KS_OTPSTS_KEY7_Msk (0x1ul << KS_OTPSTS_KEY7_Pos) /*!< KS_T::OTPSTS: KEY7 Mask */ + +#define KS_REMKCNT_RRMKCNT_Pos (0) /*!< KS_T::REMKCNT: RRMKCNT Position */ +#define KS_REMKCNT_RRMKCNT_Msk (0x3ful << KS_REMKCNT_RRMKCNT_Pos) /*!< KS_T::REMKCNT: RRMKCNT Mask */ + +#define KS_REMKCNT_FRMKCNT_Pos (16) /*!< KS_T::REMKCNT: FRMKCNT Position */ +#define KS_REMKCNT_FRMKCNT_Msk (0x3ful << KS_REMKCNT_FRMKCNT_Pos) /*!< KS_T::REMKCNT: FRMKCNT Mask */ + + +/**@}*/ /* KS_CONST */ +/**@}*/ /* end of KS register group */ + + +/**@}*/ /* end of REGISTER group */ + +#endif /* __KEYSTORE_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/lcd_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/lcd_reg.h new file mode 100644 index 0000000000..665763e1a7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/lcd_reg.h @@ -0,0 +1,1050 @@ +/**************************************************************************//** + * @file lcd_reg.h + * @version V1.00 + * @brief LCD register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __LCD_REG_H__ +#define __LCD_REG_H__ + + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Liquid-Crystal Display -------------------------*/ +/** + @addtogroup LCD Liquid-Crystal Display(LCD) + Memory Mapped Structure for LCD Controller + @{ +*/ + +typedef struct +{ + + +/** + * @var LCD_T::CTL + * Offset: 0x00 LCD Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |EN |LCD Display Enable Bit + * | | |0 = LCD display function Disabled + * | | |1 = LCD display function Enabled + * | | |Note 1: When software writes 1 to this bit, the LCD Controller needs some synchronizing time to completely enable the LCD display function. Before that, the read value of this bit is still 0. + * | | |Note 2: When software writes 0 to this bit, the LCD Controller needs some synchronizing time to completely disable the LCD display function. Before that, the read value of this bit is still 1. + * |[31] |SYNC |LCD Enable/Disable Synchronizing Indicator (Read Only) + * | | |When software writes 0/1 to EN bit (LCD_CTL[0]), the LCD Controller needs some synchronizing time to completely disable/enable the LCD display function. During this time, this bit keeps at 1. + * | | |0 = LCD display function is completely Disabled/Enabled + * | | |1 = LCD display function is not yet completely Disabled/Enabled + * | | |Note 1: The synchronizing time to enable LCD display function is not constant. It is between one and two cycles of LCD_CLK. + * | | |Note 2: The LCD display function cannot be disabled until the end of a frame. So the maximum synchronizing time to disable LCD display function could be as long as one frame time. + * @var LCD_T::PCTL + * Offset: 0x04 LCD Panel Control Registerr + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |BIAS |LCD Bias Level Selection + * | | |This field is used to select the bias level. + * | | |0 = Reserved + * | | |1 = 1/2 Bias + * | | |2 = 1/3 Bias + * | | |3 = 1/4 Bias + * |[4:2] |DUTY |LCD Duty Ratio Selection + * | | |This field is used to select the duty ratio. + * | | |0 = 1/1 Duty + * | | |1 = 1/2 Duty + * | | |2 = 1/3 Duty + * | | |3 = 1/4 Duty + * | | |4 = 1/5 Duty + * | | |5 = 1/6 Duty + * | | |6 = 1/7 Duty + * | | |7 = 1/8 Duty + * |[5] |TYPE |LCD Waveform Type Selection + * | | |This bit is used to select the waveform type. + * | | |0 = Type A + * | | |1 = Type B + * |[6] |INV |LCD Waveform Inverse + * | | |This bit is used to set the inverse LCD waveform. + * | | |0 = COM/SEG waveform is normal + * | | |1 = COM/SEG waveform is inversed + * |[17:8] |FREQDIV |LCD Operating Frequency Divider + * | | |The field is used to divide LCD_CLK to generate the LCD operating frequency. + * | | |LCD Operating Frequency = (LCD_CLK Frequency) / (FRRQDIV + 1). + * | | |Note 1: FREQDIV can be set from 0 to 1023, therefore, the fastest LCD operating frequency is equal to LCD_CLK frequency, + * | | |and the lowest LCD operating frequency is equal to LCD_CLK frequency divided by 1024. + * | | |Note 2: LCD frame rate is + * | | |(LCD Operating Frequency) x (Duty Ratio) x 1/2 for type A waveform, and + * | | |(LCD Operating Frequency) x (Duty Ratio) for type B waveform. + * | | |Example: Assume LCD operating frequency is 1 kHz, duty ratio is 1/4, then the LCD frame rate is + * | | |1 kHz x (1/4) x (1/2) = 128 Hz for type A waveform, and + * | | |1 kHz x (1/4) = 256 Hz for type B waveform. + * |[20:18] |CPVSEL |LCD Operating Voltage (VLCD) Select (For Charge Pump Only) + * | | |This field is used to select the LCD operating voltage. + * | | |0 = 2.6 V + * | | |1 = 2.8 V + * | | |2 = 3.0 V + * | | |3 = 3.2 V + * | | |4 = 3.4 V + * | | |5 = 3.6 V + * | | |Others = (Reserved) + * | | |Note: This field is meaningful only if the VLCD source is the charge pump. Otherwise, this field is ignored. + * |[27:24] |CPVTUNE |LCD Operating Voltage (VLCD) Fine Tuning (For Charge Pump Only) + * | | |This field is used to fine tune the LCD operating voltage. + * | | |0 = No tuning + * | | |1 = increase by 1 unit of voltage + * | | |2 = increase by 2 unit of voltage + * | | |3 = increase by 3 unit of voltage + * | | |4 = increase by 4 unit of voltage + * | | |5 = increase by 5 unit of voltage + * | | |6 = increase by 6 unit of voltage + * | | |7 = increase by 7 unit of voltage + * | | |8 = decrease by 8 units of voltage + * | | |9 = decrease by 7 units of voltage + * | | |10 = decrease by 6 units of voltage + * | | |11 = decrease by 5 units of voltage + * | | |12 = decrease by 4 units of voltage + * | | |13 = decrease by 3 units of voltage + * | | |14 = decrease by 2 units of voltage + * | | |15 = decrease by 1 units of voltage + * | | |Note 1: a unit of voltage is about 0.03 V. + * | | |Note 2: This field is meaningful only if the VLCD source is the charge pump. Otherwise, this field is ignored. + * @var LCD_T::FCTL + * Offset: 0x08 LCD Frame Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLINK |LCD Blinking Enable Bit + * | | |0 = LCD blinking function Disabled + * | | |1 = LCD blinking function Enabled + * |[17:8] |FCV |Frame Counting Value + * | | |This field indicates the maximum value that the frame counter can reach. + * | | |Note 1: The frame counter automatically increases by 1 at the end of every frame. When the counter reaches FCV, it will recounts from 0 at the end of the next frame. + * | | |At this moment, the hardware sets a dedicated flag to 1, and triggers a dedicated interrupt if it is enabled. + * | | |Note 2: For type B waveform, the frame counter increases at the end of odd frames, not even frames. + * |[27:24] |NFTIME |Null Frame Time + * | | |This field is used to configure the length of a null frame. + * | | |One null frame time is (1 / LCD_FREQ) x NFTIME. + * | | |Note: All COM and SEG output voltages are 0 V during a null frame. + * |[31:28] |NFNUM |Number of Frames Inserted By One Null Frame + * | | |This field is used to specify the number of continuous normal frames inserted by one null frame. + * | | |The number of continuous normal frames is (NFNUM + 1) frames. + * @var LCD_T::DCTL + * Offset: 0x0C LCD Driving Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |VSRC |LCD Operating Voltage (VLCD) Source + * | | |0 = VLCD Power + * | | |1 = AVDD Power + * | | |2 = Built-In Charge Pump + * | | |3 = None + * | | |Note: Whenever the LCD controller is disabled, all VLCD sources are automatically cut off. + * |[2] |RESMODE |Resistive Network Driving Mode + * | | |0 = Low-Drive Mode + * | | |1 = High-Drive Mode + * |[3] |BUFEN |Voltage Buffer Enable Bit + * | | |0 = Voltage Buffer Disabled + * | | |1 = Voltage Buffer Enabled + * | | |Note: When RESMODE = 1, the voltage buffers are automatically disabled. The setting of BUFEN bit is ignored. + * |[4] |PSVEN |Power Saving Mode Enable Bit + * | | |0 = Power Saving Mode Disabled + * | | |1 = Power Saving Mode Enabled + * | | |Note: when RESMODE = 0 and BUFEN = 0, the output drivers consumes the least driving current. In this case, the power saving mode is automatically disabled. The setting of PSVEN bit is ignored. + * |[5] |PSVREV |Power Saving Timing Reverse + * | | |When the timing is reversed, the original powe-saving period becomes no-power-saving, and the original no-power-saving period becomes power-saving. + * | | |0 = Timing of power saving is normal + * | | |1 = Timing of power saving is reversed + * |[11:8] |PSVT1 |Power Saving "Enable Time" Setting + * | | |The "Enable Time" of the power saving mode is calculated as "Enable Time" = 15.26 us x (PSVT1 + 1), + * | | |where 15.26 us is the half-cycle time of LCD_CLK, whose frequency is about 32 kHz. + * | | |PSVT1 can be set as 0, 1, 2, ..., 15, so the minimum "Enable Time" is about 15.26 us, and the maximum "Enable Time" is about 15.26 x 16 = 244.14 us. + * | | |Note: In the following two cases, the power saving mode is disabled. The setting of PSVT1 bits is ignored. + * | | |1. PSVEN = 0 + * | | |2. RESMODE = 0 and BUFEN = 0 + * |[15:12] |PSVT2 |Power Saving "On Time" Setting + * | | |The "On Time" of the power saving mode is calculated as "On Time" = 15.26 us x (PSVT2 + 1), + * | | |where 15.26 us is the half-cycle time of LCD_CLK, whose frequency is about 32 kHz. + * | | |PSVT2 can be set as 0, 1, 2, ..., 15, so the minimum "On Time" is about 15.26 us, and the maximum "On Time" is about 15.26 x 16 = 244.14 us. + * | | |Note: In the following two cases, the power saving mode is disabled. The setting of PSVT2 bits is ignored. + * | | |1. PSVEN = 0 + * |[28:16] |CTOTIME |Charging Timer Timeout Time + * | | |This field is used to specify the timeout value for the charging timer. When the charging timer reaches this timeout value, a status bit or an interrupt will occur. + * | | |The timeout is calculated by the following formula: Timeout = 30.52 us x (CTOTIME + 1), where 30.52 us is the cycle time of LCD_CLK, whose frequency is about 32 kHz. + * | | |CTOTIME can be set as 0, 1, 2, ..., 8191, so the minimum timeout is 30.52 us, and the maximum timeout is 30.52 x 8192 = 256 ms. + * @var LCD_T::PKGSEL + * Offset: 0x10 LCD Package Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PKG |Device Package Type Selection + * | | |0 = 128-Pin Package + * | | |1 = 64-Pin Package + * @var LCD_T::STS + * Offset: 0x14 LCD Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FCEF |End of Frame-Counting Flag + * | | |This flag is automatically set by hardware at the end of a frame, and the frame counter value must be equal to FCV (LCD_FCTL[17:8], Frame Counting Value). + * | | |0 = End of Frame-Counting did not occur + * | | |1 = End of Frame-Counting occurred + * | | |Note 1: User can clear this bit by writing 1 to it. + * | | |Note 2: For type B waveform, this flag is set only at the end of an odd frame. + * |[1] |FEF |End of Frame Flag + * | | |This flag is automatically set by hardware at the end of a frame. + * | | |0 = End of Frame did not occur + * | | |1 = End of Frame occurred + * | | |Note 1: User can clear this bit by writing 1 to it. + * | | |Note 2: For type B waveform, this flag is set only at the end of an odd frame. + * |[2] |CTOF |Charging Timeout Flag + * | | |This flag is automatically set by hardware when the charging timer reaches the timeout value. + * | | |0 = Charging Timeout did not occur + * | | |1 = Charging Timeout occurred + * | | |Note: User can clear this bit by writing 1 to it. + * |[28:16] |CTIME |Charging Timer Value (Read Only) + * | | |The field contains the value of the charging timer. It records the charging time of the charge pump. + * | | |The charging timer stops counting when the charge pump stops charging or a timeout occurs. At this moment, the hardware dumps the current charging timer value into this field. + * | | |Charging Time = 30.52 us x (CTIME + 1), where 30.52 us is the cycle time of LCD_CLK, whose frequency is about 32 kHz. + * @var LCD_T::INTEN + * Offset: 0x18 LCD Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FCEIEN |End of Frame-Counting Interrupt Enable Bit + * | | |An interrupt occurs at the end of a frame, and the frame counter value must be equal to FCV (LCD_FCTL[17:8], Frame Counting Value). + * | | |0 = End of Frame-Counting Interrupt Disabled + * | | |1 = End of Frame-Counting Interrupt Enabled + * | | |Note: For type B waveform, the interrupt occurs only at the end of an odd frame. + * |[1] |FEIEN |End of Frame Interrupt Enable Bit + * | | |An interrupt occurs at the end of a frame. + * | | |0 = End of Frame Interrupt Disabled + * | | |1 = End of Frame Interrupt Enabled + * | | |Note: For type B waveform, the interrupt occurs only at the end of an odd frame. + * |[2] |CTOIEN |Charging Timeout Interrupt Enable Bit + * | | |An interrupt occurs when the charging timer reaches the timeout value. + * | | |0 = Charging Timeout Interrupt Disabled + * | | |1 = Charging Timeout Interrupt Enabled + * @var LCD_T::DATA + * Offset: 0x20 LCD Segment Display Data Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x24 LCD Segment Display Data Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x28 LCD Segment Display Data Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x2C LCD Segment Display Data Register 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x30 LCD Segment Display Data Register 4 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x34 LCD Segment Display Data Register 5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x38 LCD Segment Display Data Register 6 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x3C LCD Segment Display Data Register 7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x40 LCD Segment Display Data Register 8 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x44 LCD Segment Display Data Register 9 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + * Offset: 0x48 LCD Segment Display Data Register 10 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DD0 |Display Data of Segments S, where S is (4 x N) + 0, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD0 corresponds to SEG00, SEG04, SEG08, SEG12, SEG16, SEG20, SEG24, SEG28, SEG32, SEG36, and SEG40. + * | | |Note 2: Each bit, DD0[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD0 (= LCD_DATA07[7:0]) = 1001_0110, LCD_DATA07[7:0] corresponds to SEG28 (4 x 7 + 0 = 28), + * | | |the pixel SEG28-COM0 is light (LCD_DATA07[0] = 0), + * | | |the pixel SEG28-COM1 is dark (LCD_DATA07[1] = 1), + * | | |the pixel SEG28-COM2 is dark (LCD_DATA07[2] = 1), + * | | |the pixel SEG28-COM3 is light (LCD_DATA07[3] = 0), + * | | |LCD_DATA07[7:4] are ignored, since COMs from 4 to 7 are not used. + * |[15:8] |DD1 |Display Data of Segments S, where S is (4 x N) + 1, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD1 corresponds to SEG01, SEG05, SEG09, SEG13, SEG17, SEG21, SEG25, SEG29, SEG33, SEG37, and SEG41. + * | | |Note 2: Each bit, DD1[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD1 (= LCD_DATA07[15:8]) = 1001_0110, LCD_DATA07[15:8] corresponds to SEG29 (4 x 7 + 1 = 29), + * | | |the pixel SEG29-COM0 is light (LCD_DATA07[8] = 0), + * | | |the pixel SEG29-COM1 is dark (LCD_DATA07[9] = 1), + * | | |the pixel SEG29-COM2 is dark (LCD_DATA07[10] = 1), + * | | |the pixel SEG29-COM3 is light (LCD_DATA07[11] = 0), + * | | |LCD_DATA07[15:12] are ignored, since COMs from 4 to 7 are not used. + * |[23:16] |DD2 |Display Data of Segments S, where S is (4 x N) + 2, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD2 corresponds to SEG02, SEG06, SEG10, SEG14, SEG18, SEG22, SEG26, SEG30, SEG34, SEG38, and SEG42. + * | | |Note 2: Each bit, DD2[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD2 (= LCD_DATA07[23:16]) = 1001_0110, LCD_DATA07[23:16] corresponds to SEG31 (4 x 7 + 2 = 30), + * | | |the pixel SEG30-COM0 is light (LCD_DATA07[16] = 0), + * | | |the pixel SEG30-COM1 is dark (LCD_DATA07[17] = 1), + * | | |the pixel SEG30-COM2 is dark (LCD_DATA07[18] = 1), + * | | |the pixel SEG30-COM3 is light (LCD_DATA07[19] = 0), + * | | |LCD_DATA07[23:20] are ignored, since COMs from 4 to 7 are not used. + * |[31:24] |DD3 |Display Data of Segments S, where S is (4 x N) + 3, and N is 0, 1, 2, ..., 10 + * | | |Each bit specifies the brightness of each pixel in a segment. + * | | |0 = The pixel is light + * | | |1 = The pixel is dark + * | | |Note 1: DD3 corresponds to SEG03, SEG07, SEG11, SEG15, SEG19, SEG23, SEG27, SEG31, SEG35, SEG39, and SEG43. + * | | |Note 2: Each bit, DD3[n], corresponds to COMn, n= 0 ~ 7. + * | | |[Example] Assume 1/4 Duty, and DD3 (= LCD_DATA07[31:24]) = 1001_0110, LCD_DATA07[31:24] corresponds to SEG31 (4 x 7 + 3 = 31), + * | | |the pixel SEG31-COM0 is light (LCD_DATA07[24] = 0), + * | | |the pixel SEG31-COM1 is dark (LCD_DATA07[25] = 1), + * | | |the pixel SEG31-COM2 is dark (LCD_DATA07[26] = 1), + * | | |the pixel SEG31-COM3 is light (LCD_DATA07[27] = 0), + * | | |LCD_DATA07[31:28] are ignored, since COMs from 4 to 7 are not used. + */ + __IO uint32_t CTL; /*!< [0x0000] LCD Control Register */ + __IO uint32_t PCTL; /*!< [0x0004] LCD Panel Control Register */ + __IO uint32_t FCTL; /*!< [0x0008] LCD Frame Control Register */ + __IO uint32_t DCTL; /*!< [0x000C] LCD Driving Control Register */ + __IO uint32_t PKGSEL; /*!< [0x0010] LCD Package Selection Register */ + __IO uint32_t STS; /*!< [0x0014] LCD Status Register */ + __IO uint32_t INTEN; /*!< [0x0018] LCD Interrupt Enable Register */ + __I uint32_t RESERVED0; /*!< [0x001C] Reserved 0 */ + __IO uint32_t DATA[11]; /*!< [0x0020] ~ [0x0048] LCD Segment Display Data Register 0 ~ 10 */ + +} LCD_T; + +/** + @addtogroup LCD_CONST LCD Bit Field Definition + Constant Definitions for LCD Controller + @{ +*/ + +#define LCD_CTL_EN_Pos (0) /*!< LCD_T::CTL: EN Position */ +#define LCD_CTL_EN_Msk (0x1ul << LCD_CTL_EN_Pos) /*!< LCD_T::CTL: EN Mask */ + +#define LCD_CTL_SYNC_Pos (31) /*!< LCD_T::CTL: SYNC Position */ +#define LCD_CTL_SYNC_Msk (0x1ul << LCD_CTL_SYNC_Pos) /*!< LCD_T::CTL: SYNC Mask */ + +#define LCD_PCTL_BIAS_Pos (0) /*!< LCD_T::PCTL: BIAS Position */ +#define LCD_PCTL_BIAS_Msk (0x3ul << LCD_PCTL_BIAS_Pos) /*!< LCD_T::PCTL: BIAS Mask */ + +#define LCD_PCTL_DUTY_Pos (2) /*!< LCD_T::PCTL: DUTY Position */ +#define LCD_PCTL_DUTY_Msk (0x7ul << LCD_PCTL_DUTY_Pos) /*!< LCD_T::PCTL: DUTY Mask */ + +#define LCD_PCTL_TYPE_Pos (5) /*!< LCD_T::PCTL: TYPE Position */ +#define LCD_PCTL_TYPE_Msk (0x1ul << LCD_PCTL_TYPE_Pos) /*!< LCD_T::PCTL: TYPE Mask */ + +#define LCD_PCTL_INV_Pos (6) /*!< LCD_T::PCTL: INV Position */ +#define LCD_PCTL_INV_Msk (0x1ul << LCD_PCTL_INV_Pos) /*!< LCD_T::PCTL: INV Mask */ + +#define LCD_PCTL_FREQDIV_Pos (8) /*!< LCD_T::PCTL: FREQDIV Position */ +#define LCD_PCTL_FREQDIV_Msk (0x3fful << LCD_PCTL_FREQDIV_Pos) /*!< LCD_T::PCTL: FREQDIV Mask */ + +#define LCD_PCTL_CPVSEL_Pos (18) /*!< LCD_T::PCTL: CPVSEL Position */ +#define LCD_PCTL_CPVSEL_Msk (0x7ul << LCD_PCTL_CPVSEL_Pos) /*!< LCD_T::PCTL: CPVSEL Mask */ + +#define LCD_PCTL_CPVTUNE_Pos (24) /*!< LCD_T::PCTL: CPVTUNE Position */ +#define LCD_PCTL_CPVTUNE_Msk (0xful << LCD_PCTL_CPVTUNE_Pos) /*!< LCD_T::PCTL: CPVTUNE Mask */ + +#define LCD_FCTL_BLINK_Pos (0) /*!< LCD_T::FCTL: BLINK Position */ +#define LCD_FCTL_BLINK_Msk (0x1ul << LCD_FCTL_BLINK_Pos) /*!< LCD_T::FCTL: BLINK Mask */ + +#define LCD_FCTL_FCV_Pos (8) /*!< LCD_T::FCTL: FCV Position */ +#define LCD_FCTL_FCV_Msk (0x3fful << LCD_FCTL_FCV_Pos) /*!< LCD_T::FCTL: FCV Mask */ + +#define LCD_FCTL_NFTIME_Pos (24) /*!< LCD_T::FCTL: NFTIME Position */ +#define LCD_FCTL_NFTIME_Msk (0xful << LCD_FCTL_NFTIME_Pos) /*!< LCD_T::FCTL: NFTIME Mask */ + +#define LCD_FCTL_NFNUM_Pos (28) /*!< LCD_T::FCTL: NFNUM Position */ +#define LCD_FCTL_NFNUM_Msk (0xful << LCD_FCTL_NFNUM_Pos) /*!< LCD_T::FCTL: NFNUM Mask */ + +#define LCD_DCTL_VSRC_Pos (0) /*!< LCD_T::DCTL: VSRC Position */ +#define LCD_DCTL_VSRC_Msk (0x3ul << LCD_DCTL_VSRC_Pos) /*!< LCD_T::DCTL: VSRC Mask */ + +#define LCD_DCTL_RESMODE_Pos (2) /*!< LCD_T::DCTL: RESMODE Position */ +#define LCD_DCTL_RESMODE_Msk (0x1ul << LCD_DCTL_RESMODE_Pos) /*!< LCD_T::DCTL: RESMODE Mask */ + +#define LCD_DCTL_BUFEN_Pos (3) /*!< LCD_T::DCTL: BUFEN Position */ +#define LCD_DCTL_BUFEN_Msk (0x1ul << LCD_DCTL_BUFEN_Pos) /*!< LCD_T::DCTL: BUFEN Mask */ + +#define LCD_DCTL_PSVEN_Pos (4) /*!< LCD_T::DCTL: PSVEN Position */ +#define LCD_DCTL_PSVEN_Msk (0x1ul << LCD_DCTL_PSVEN_Pos) /*!< LCD_T::DCTL: PSVEN Mask */ + +#define LCD_DCTL_PSVREV_Pos (5) /*!< LCD_T::DCTL: PSVREV Position */ +#define LCD_DCTL_PSVREV_Msk (0x1ul << LCD_DCTL_PSVREV_Pos) /*!< LCD_T::DCTL: PSVREV Mask */ + +#define LCD_DCTL_PSVT1_Pos (8) /*!< LCD_T::DCTL: PSVT1 Position */ +#define LCD_DCTL_PSVT1_Msk (0xful << LCD_DCTL_PSVT1_Pos) /*!< LCD_T::DCTL: PSVT1 Mask */ + +#define LCD_DCTL_PSVT2_Pos (12) /*!< LCD_T::DCTL: PSVT2 Position */ +#define LCD_DCTL_PSVT2_Msk (0xful << LCD_DCTL_PSVT2_Pos) /*!< LCD_T::DCTL: PSVT2 Mask */ + +#define LCD_DCTL_CTOTIME_Pos (16) /*!< LCD_T::DCTL: CTOTIME Position */ +#define LCD_DCTL_CTOTIME_Msk (0x1ffful << LCD_DCTL_CTOTIME_Pos) /*!< LCD_T::DCTL: CTOTIME Mask */ + +#define LCD_PKGSEL_PKG_Pos (0) /*!< LCD_T::PKGSEL: PKG Position */ +#define LCD_PKGSEL_PKG_Msk (0x1ul << LCD_PKGSEL_PKG_Pos) /*!< LCD_T::PKGSEL: PKG Mask */ + +#define LCD_STS_FCEF_Pos (0) /*!< LCD_T::STS: FCEF Position */ +#define LCD_STS_FCEF_Msk (0x1ul << LCD_STS_FCEF_Pos) /*!< LCD_T::STS: FCEF Mask */ + +#define LCD_STS_FEF_Pos (1) /*!< LCD_T::STS: FEF Position */ +#define LCD_STS_FEF_Msk (0x1ul << LCD_STS_FEF_Pos) /*!< LCD_T::STS: FEF Mask */ + +#define LCD_STS_CTOF_Pos (2) /*!< LCD_T::STS: CTOF Position */ +#define LCD_STS_CTOF_Msk (0x1ul << LCD_STS_CTOF_Pos) /*!< LCD_T::STS: CTOF Mask */ + +#define LCD_STS_CTIME_Pos (16) /*!< LCD_T::STS: CTIME Position */ +#define LCD_STS_CTIME_Msk (0x1ffful << LCD_STS_CTIME_Pos) /*!< LCD_T::STS: CTIME Mask */ + +#define LCD_INTEN_FCEIEN_Pos (0) /*!< LCD_T::INTEN: FCEIEN Position */ +#define LCD_INTEN_FCEIEN_Msk (0x1ul << LCD_INTEN_FCEIEN_Pos) /*!< LCD_T::INTEN: FCEIEN Mask */ + +#define LCD_INTEN_FEIEN_Pos (1) /*!< LCD_T::INTEN: FEIEN Position */ +#define LCD_INTEN_FEIEN_Msk (0x1ul << LCD_INTEN_FEIEN_Pos) /*!< LCD_T::INTEN: FEIEN Mask */ + +#define LCD_INTEN_CTOIEN_Pos (2) /*!< LCD_T::INTEN: CYOIEN Position */ +#define LCD_INTEN_CTOIEN_Msk (0x1ul << LCD_INTEN_CTOIEN_Pos) /*!< LCD_T::INTEN: CTOIEN Mask */ + +#define LCD_DATA00_DD0_Pos (0) /*!< LCD_T::DATA00: DD0 Position */ +#define LCD_DATA00_DD0_Msk (0xfful << LCD_DATA00_DD0_Pos) /*!< LCD_T::DATA00: DD0 Mask */ + +#define LCD_DATA00_DD1_Pos (8) /*!< LCD_T::DATA00: DD1 Position */ +#define LCD_DATA00_DD1_Msk (0xfful << LCD_DATA00_DD1_Pos) /*!< LCD_T::DATA00: DD1 Mask */ + +#define LCD_DATA00_DD2_Pos (16) /*!< LCD_T::DATA00: DD2 Position */ +#define LCD_DATA00_DD2_Msk (0xfful << LCD_DATA00_DD2_Pos) /*!< LCD_T::DATA00: DD2 Mask */ + +#define LCD_DATA00_DD3_Pos (24) /*!< LCD_T::DATA00: DD3 Position */ +#define LCD_DATA00_DD3_Msk (0xfful << LCD_DATA00_DD3_Pos) /*!< LCD_T::DATA00: DD3 Mask */ + +#define LCD_DATA01_DD0_Pos (0) /*!< LCD_T::DATA01: DD0 Position */ +#define LCD_DATA01_DD0_Msk (0xfful << LCD_DATA01_DD0_Pos) /*!< LCD_T::DATA01: DD0 Mask */ + +#define LCD_DATA01_DD1_Pos (8) /*!< LCD_T::DATA01: DD1 Position */ +#define LCD_DATA01_DD1_Msk (0xfful << LCD_DATA01_DD1_Pos) /*!< LCD_T::DATA01: DD1 Mask */ + +#define LCD_DATA01_DD2_Pos (16) /*!< LCD_T::DATA01: DD2 Position */ +#define LCD_DATA01_DD2_Msk (0xfful << LCD_DATA01_DD2_Pos) /*!< LCD_T::DATA01: DD2 Mask */ + +#define LCD_DATA01_DD3_Pos (24) /*!< LCD_T::DATA01: DD3 Position */ +#define LCD_DATA01_DD3_Msk (0xfful << LCD_DATA01_DD3_Pos) /*!< LCD_T::DATA01: DD3 Mask */ + +#define LCD_DATA02_DD0_Pos (0) /*!< LCD_T::DATA02: DD0 Position */ +#define LCD_DATA02_DD0_Msk (0xfful << LCD_DATA02_DD0_Pos) /*!< LCD_T::DATA02: DD0 Mask */ + +#define LCD_DATA02_DD1_Pos (8) /*!< LCD_T::DATA02: DD1 Position */ +#define LCD_DATA02_DD1_Msk (0xfful << LCD_DATA02_DD1_Pos) /*!< LCD_T::DATA02: DD1 Mask */ + +#define LCD_DATA02_DD2_Pos (16) /*!< LCD_T::DATA02: DD2 Position */ +#define LCD_DATA02_DD2_Msk (0xfful << LCD_DATA02_DD2_Pos) /*!< LCD_T::DATA02: DD2 Mask */ + +#define LCD_DATA02_DD3_Pos (24) /*!< LCD_T::DATA02: DD3 Position */ +#define LCD_DATA02_DD3_Msk (0xfful << LCD_DATA02_DD3_Pos) /*!< LCD_T::DATA02: DD3 Mask */ + +#define LCD_DATA03_DD0_Pos (0) /*!< LCD_T::DATA03: DD0 Position */ +#define LCD_DATA03_DD0_Msk (0xfful << LCD_DATA03_DD0_Pos) /*!< LCD_T::DATA03: DD0 Mask */ + +#define LCD_DATA03_DD1_Pos (8) /*!< LCD_T::DATA03: DD1 Position */ +#define LCD_DATA03_DD1_Msk (0xfful << LCD_DATA03_DD1_Pos) /*!< LCD_T::DATA03: DD1 Mask */ + +#define LCD_DATA03_DD2_Pos (16) /*!< LCD_T::DATA03: DD2 Position */ +#define LCD_DATA03_DD2_Msk (0xfful << LCD_DATA03_DD2_Pos) /*!< LCD_T::DATA03: DD2 Mask */ + +#define LCD_DATA03_DD3_Pos (24) /*!< LCD_T::DATA03: DD3 Position */ +#define LCD_DATA03_DD3_Msk (0xfful << LCD_DATA03_DD3_Pos) /*!< LCD_T::DATA03: DD3 Mask */ + +#define LCD_DATA04_DD0_Pos (0) /*!< LCD_T::DATA04: DD0 Position */ +#define LCD_DATA04_DD0_Msk (0xfful << LCD_DATA04_DD0_Pos) /*!< LCD_T::DATA04: DD0 Mask */ + +#define LCD_DATA04_DD1_Pos (8) /*!< LCD_T::DATA04: DD1 Position */ +#define LCD_DATA04_DD1_Msk (0xfful << LCD_DATA04_DD1_Pos) /*!< LCD_T::DATA04: DD1 Mask */ + +#define LCD_DATA04_DD2_Pos (16) /*!< LCD_T::DATA04: DD2 Position */ +#define LCD_DATA04_DD2_Msk (0xfful << LCD_DATA04_DD2_Pos) /*!< LCD_T::DATA04: DD2 Mask */ + +#define LCD_DATA04_DD3_Pos (24) /*!< LCD_T::DATA04: DD3 Position */ +#define LCD_DATA04_DD3_Msk (0xfful << LCD_DATA04_DD3_Pos) /*!< LCD_T::DATA04: DD3 Mask */ + +#define LCD_DATA05_DD0_Pos (0) /*!< LCD_T::DATA05: DD0 Position */ +#define LCD_DATA05_DD0_Msk (0xfful << LCD_DATA05_DD0_Pos) /*!< LCD_T::DATA05: DD0 Mask */ + +#define LCD_DATA05_DD1_Pos (8) /*!< LCD_T::DATA05: DD1 Position */ +#define LCD_DATA05_DD1_Msk (0xfful << LCD_DATA05_DD1_Pos) /*!< LCD_T::DATA05: DD1 Mask */ + +#define LCD_DATA05_DD2_Pos (16) /*!< LCD_T::DATA05: DD2 Position */ +#define LCD_DATA05_DD2_Msk (0xfful << LCD_DATA05_DD2_Pos) /*!< LCD_T::DATA05: DD2 Mask */ + +#define LCD_DATA05_DD3_Pos (24) /*!< LCD_T::DATA05: DD3 Position */ +#define LCD_DATA05_DD3_Msk (0xfful << LCD_DATA05_DD3_Pos) /*!< LCD_T::DATA05: DD3 Mask */ + +#define LCD_DATA06_DD0_Pos (0) /*!< LCD_T::DATA06: DD0 Position */ +#define LCD_DATA06_DD0_Msk (0xfful << LCD_DATA06_DD0_Pos) /*!< LCD_T::DATA06: DD0 Mask */ + +#define LCD_DATA06_DD1_Pos (8) /*!< LCD_T::DATA06: DD1 Position */ +#define LCD_DATA06_DD1_Msk (0xfful << LCD_DATA06_DD1_Pos) /*!< LCD_T::DATA06: DD1 Mask */ + +#define LCD_DATA06_DD2_Pos (16) /*!< LCD_T::DATA06: DD2 Position */ +#define LCD_DATA06_DD2_Msk (0xfful << LCD_DATA06_DD2_Pos) /*!< LCD_T::DATA06: DD2 Mask */ + +#define LCD_DATA06_DD3_Pos (24) /*!< LCD_T::DATA06: DD3 Position */ +#define LCD_DATA06_DD3_Msk (0xfful << LCD_DATA06_DD3_Pos) /*!< LCD_T::DATA06: DD3 Mask */ + +#define LCD_DATA07_DD0_Pos (0) /*!< LCD_T::DATA07: DD0 Position */ +#define LCD_DATA07_DD0_Msk (0xfful << LCD_DATA07_DD0_Pos) /*!< LCD_T::DATA07: DD0 Mask */ + +#define LCD_DATA07_DD1_Pos (8) /*!< LCD_T::DATA07: DD1 Position */ +#define LCD_DATA07_DD1_Msk (0xfful << LCD_DATA07_DD1_Pos) /*!< LCD_T::DATA07: DD1 Mask */ + +#define LCD_DATA07_DD2_Pos (16) /*!< LCD_T::DATA07: DD2 Position */ +#define LCD_DATA07_DD2_Msk (0xfful << LCD_DATA07_DD2_Pos) /*!< LCD_T::DATA07: DD2 Mask */ + +#define LCD_DATA07_DD3_Pos (24) /*!< LCD_T::DATA07: DD3 Position */ +#define LCD_DATA07_DD3_Msk (0xfful << LCD_DATA07_DD3_Pos) /*!< LCD_T::DATA07: DD3 Mask */ + +#define LCD_DATA08_DD0_Pos (0) /*!< LCD_T::DATA08: DD0 Position */ +#define LCD_DATA08_DD0_Msk (0xfful << LCD_DATA08_DD0_Pos) /*!< LCD_T::DATA08: DD0 Mask */ + +#define LCD_DATA08_DD1_Pos (8) /*!< LCD_T::DATA08: DD1 Position */ +#define LCD_DATA08_DD1_Msk (0xfful << LCD_DATA08_DD1_Pos) /*!< LCD_T::DATA08: DD1 Mask */ + +#define LCD_DATA08_DD2_Pos (16) /*!< LCD_T::DATA08: DD2 Position */ +#define LCD_DATA08_DD2_Msk (0xfful << LCD_DATA08_DD2_Pos) /*!< LCD_T::DATA08: DD2 Mask */ + +#define LCD_DATA08_DD3_Pos (24) /*!< LCD_T::DATA08: DD3 Position */ +#define LCD_DATA08_DD3_Msk (0xfful << LCD_DATA08_DD3_Pos) /*!< LCD_T::DATA08: DD3 Mask */ + +#define LCD_DATA09_DD0_Pos (0) /*!< LCD_T::DATA09: DD0 Position */ +#define LCD_DATA09_DD0_Msk (0xfful << LCD_DATA09_DD0_Pos) /*!< LCD_T::DATA09: DD0 Mask */ + +#define LCD_DATA09_DD1_Pos (8) /*!< LCD_T::DATA09: DD1 Position */ +#define LCD_DATA09_DD1_Msk (0xfful << LCD_DATA09_DD1_Pos) /*!< LCD_T::DATA09: DD1 Mask */ + +#define LCD_DATA09_DD2_Pos (16) /*!< LCD_T::DATA09: DD2 Position */ +#define LCD_DATA09_DD2_Msk (0xfful << LCD_DATA09_DD2_Pos) /*!< LCD_T::DATA09: DD2 Mask */ + +#define LCD_DATA09_DD3_Pos (24) /*!< LCD_T::DATA09: DD3 Position */ +#define LCD_DATA09_DD3_Msk (0xfful << LCD_DATA09_DD3_Pos) /*!< LCD_T::DATA09: DD3 Mask */ + +#define LCD_DATA10_DD0_Pos (0) /*!< LCD_T::DATA10: DD0 Position */ +#define LCD_DATA10_DD0_Msk (0xfful << LCD_DATA10_DD0_Pos) /*!< LCD_T::DATA10: DD0 Mask */ + +#define LCD_DATA10_DD1_Pos (8) /*!< LCD_T::DATA10: DD1 Position */ +#define LCD_DATA10_DD1_Msk (0xfful << LCD_DATA10_DD1_Pos) /*!< LCD_T::DATA10: DD1 Mask */ + +#define LCD_DATA10_DD2_Pos (16) /*!< LCD_T::DATA10: DD2 Position */ +#define LCD_DATA10_DD2_Msk (0xfful << LCD_DATA10_DD2_Pos) /*!< LCD_T::DATA10: DD2 Mask */ + +#define LCD_DATA10_DD3_Pos (24) /*!< LCD_T::DATA10: DD3 Position */ +#define LCD_DATA10_DD3_Msk (0xfful << LCD_DATA10_DD3_Pos) /*!< LCD_T::DATA10: DD3 Mask */ + +/**@}*/ /* LCD_CONST */ +/**@}*/ /* end of LCD register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __LCD_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/otg_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/otg_reg.h new file mode 100644 index 0000000000..064dc967ed --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/otg_reg.h @@ -0,0 +1,394 @@ +/**************************************************************************//** + * @file otg_reg.h + * @version V1.00 + * @brief OTG register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __OTG_REG_H__ +#define __OTG_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- USB On-The-Go Controller -------------------------*/ +/** + @addtogroup OTG USB On-The-Go Controller(OTG) + Memory Mapped Structure for OTG Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var OTG_T::CTL + * Offset: 0x00 OTG Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDROP |Drop VBUS Control + * | | |If user application running on this OTG A-device wants to conserve power, set this bit to drop VBUS + * | | |BUSREQ (OTG_CTL[1]) will be also cleared no matter A-device or B-device. + * | | |0 = Not drop the VBUS. + * | | |1 = Drop the VBUS. + * |[1] |BUSREQ |OTG Bus Request + * | | |If OTG A-device wants to do data transfers via USB bus, setting this bit will drive VBUS high to detect USB device connection + * | | |If user won't use the bus any more, clearing this bit will drop VBUS to save power + * | | |This bit will be cleared when A-device goes to A_wait_vfall state + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. + * | | |If user of an OTG-B Device wants to request VBUS, setting this bit will run SRP protocol + * | | |This bit will be cleared if SRP failure (OTG A-device does not provide VBUS after B-device issues SRP in specified interval, defined in OTG specification) + * | | |This bit will be also cleared if VBUSDROP (OTG_CTL[0]) bit is set or IDSTS (OTG_STATUS[1]) changed. + * | | |0 = Not launch VBUS in OTG A-device or not request SRP in OTG B-device. + * | | |1 = Launch VBUS in OTG A-device or request SRP in OTG B-device. + * |[2] |HNPREQEN |OTG HNP Request Enable Bit + * | | |When USB frame as A-device, set this bit when A-device allows to process HNP protocol -- A-device changes role from Host to Peripheral + * | | |This bit will be cleared when OTG state changes from a_suspend to a_peripheral or goes back to a_idle state + * | | |When USB frame as B-device, set this bit after the OTG A-device successfully sends a SetFeature (b_hnp_enable) command to the OTG B-device to start role change -- B-device changes role from Peripheral to Host + * | | |This bit will be cleared when OTG state changes from b_peripheral to b_wait_acon or goes back to b_idle state. + * | | |0 = HNP request Disabled. + * | | |1 = HNP request Enabled (A-device can change role from Host to Peripheral or B-device can change role from Peripheral to Host). + * | | |Note: Refer to OTG specification to get a_suspend, a_peripheral, a_idle and b_idle state. + * |[4] |OTGEN |OTG Function Enable Bit + * | | |User needs to set this bit to enable OTG function while USB frame configured as OTG device + * | | |When USB frame is not configured as OTG device, this bit must be low. + * | | |0= OTG function Disabled. + * | | |1 = OTG function Enabled. + * |[5] |WKEN |OTG ID Pin Wake-up Enable Bit + * | | |0 = OTG ID pin status change wake-up function Disabled. + * | | |1 = OTG ID pin status change wake-up function Enabled. + * @var OTG_T::PHYCTL + * Offset: 0x04 OTG PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OTGPHYEN |OTG PHY Enable Bit + * | | |When USB frame is configured as OTG device or ID dependent, user needs to set this bit before using OTG function + * | | |If device is not configured as OTG device nor ID dependent , this bit is "don't care". + * | | |0 = OTG PHY Disabled. + * | | |1 = OTG PHY Enabled. + * |[1] |IDDETEN |ID Detection Enable Bit + * | | |0 = Detect ID pin status Disabled. + * | | |1 = Detect ID pin status Enabled. + * |[4] |VBENPOL |Off-chip USB VBUS Power Switch Enable Polarity + * | | |The OTG controller will enable off-chip USB VBUS power switch to provide VBUS power when need + * | | |A USB_VBUS_EN pin is used to control the off-chip USB VBUS power switch. + * | | |The polarity of enabling off-chip USB VBUS power switch (high active or low active) depends on the selected component + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The off-chip USB VBUS power switch enable is active high. + * | | |1 = The off-chip USB VBUS power switch enable is active low. + * |[5] |VBSTSPOL |Off-chip USB VBUS Power Switch Status Polarity + * | | |The polarity of off-chip USB VBUS power switch valid signal depends on the selected component + * | | |A USB_VBUS_ST pin is used to monitor the valid signal of the off-chip USB VBUS power switch + * | | |Set this bit as following according to the polarity of off-chip USB VBUS power switch. + * | | |0 = The polarity of off-chip USB VBUS power switch valid status is high. + * | | |1 = The polarity of off-chip USB VBUS power switch valid status is low. + * @var OTG_T::INTEN + * Offset: 0x08 OTG Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIEN|Role (Host or Peripheral) Changed Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[1] |VBEIEN |VBUS Error Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG specification. + * |[2] |SRPFIEN |SRP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[3] |HNPFIEN |HNP Fail Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[4] |GOIDLEIEN |OTG Device Goes to IDLE State Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * | | |Note: Going to idle state means going to a_idle or b_idle state + * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec. + * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and IDSTS (OTG_STATUS[1]) status is changed from high to low or from low to high, an interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a peripheral, an interrupt will be asserted. + * | | |0 = This device as a peripheral interrupt Disabled. + * | | |1 = This device as a peripheral interrupt Enabled. + * |[7] |HOSTIEN |Act As Host Interrupt Enable Bit + * | | |If this bit is set to 1 and the device is changed as a host, an interrupt will be asserted. + * | | |0 = This device as a host interrupt Disabled. + * | | |1 = This device as a host interrupt Enabled. + * |[8] |BVLDCHGIEN|B-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and BVLD (OTG_STATUS[3]) status is changed from high to low or from low to high, an interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[9] |AVLDCHGIEN|A-device Session Valid Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and AVLD (OTG_STATUS[4]) status is changed from high to low or from low to high, an interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[10] |VBCHGIEN |VBUSVLD Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and VBUSVLD (OTG_STATUS[5]) status is changed from high to low or from low to high, an interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Bit + * | | |If this bit is set to 1 and SESSEND (OTG_STATUS[2]) status is changed from high to low or from low to high, an interrupt will be asserted. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var OTG_T::INTSTS + * Offset: 0x0C OTG Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ROLECHGIF |OTG Role Change Interrupt Status + * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host while USB_ID pin status does not change. + * | | |0 = OTG device role not changed. + * | | |1 = OTG device role changed. + * | | |Note: Write 1 to clear this flag. + * |[1] |VBEIF |VBUS Error Interrupt Status + * | | |This bit will be set when voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A-device starting to drive VBUS high. + * | | |0 = OTG A-device drives VBUS over threshold voltage before this interval expires. + * | | |1 = OTG A-device cannot drive VBUS over threshold voltage before this interval expires. + * | | |Note: Write 1 to clear this flag and recover from the VBUS error state. + * |[2] |SRPFIF |SRP Fail Interrupt Status + * | | |After initiating SRP, an OTG B-device will wait for the OTG A-device to drive VBUS high at least TB_SRP_FAIL minimum, defined in OTG specification + * | | |This flag is set when the OTG B-device does not get VBUS high after this interval. + * | | |0 = OTG B-device gets VBUS high before this interval. + * | | |1 = OTG B-device does not get VBUS high before this interval. + * | | |Note: Write 1 to clear this flag. + * |[3] |HNPFIF |HNP Fail Interrupt Status + * | | |When A-device has granted B-device to be host and USB bus is in SE0 (both USB_D+ and USB_D- low) state, this bit will be set when A-device does not connect after specified interval expires. + * | | |0 = A-device connects to B-device before specified interval expires. + * | | |1 = A-device does not connect to B-device before specified interval expires. + * | | |Note: Write 1 to clear this flag. + * |[4] |GOIDLEIF |OTG Device Goes to IDLE Interrupt Status + * | | |Flag is set if the OTG device transfers from non-idle state to idle state + * | | |The OTG device will be neither a host nor a peripheral. + * | | |0 = OTG device does not go back to idle state (a_idle or b_idle). + * | | |1 = OTG device goes back to idle state(a_idle or b_idle). + * | | |Note 1: Going to idle state means going to a_idle or b_idle state. Please refer to OTG specification. + * | | |Note 2: Write 1 to clear this flag. + * |[5] |IDCHGIF |ID State Change Interrupt Status + * | | |0 = IDSTS (OTG_STATUS[1]) not toggled. + * | | |1 = IDSTS (OTG_STATUS[1]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[6] |PDEVIF |Act As Peripheral Interrupt Status + * | | |0= This device does not act as a peripheral. + * | | |1 = This device acts as a peripheral. + * | | |Note: Write 1 to clear this flag. + * |[7] |HOSTIF |Act As Host Interrupt Status + * | | |0= This device does not act as a host. + * | | |1 = This device acts as a host. + * | | |Note: Write 1 to clear this flag. + * |[8] |BVLDCHGIF |B-device Session Valid State Change Interrupt Status + * | | |0 = BVLD (OTG_STATUS[3]) is not toggled. + * | | |1 = BVLD (OTG_STATUS[3]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[9] |AVLDCHGIF |A-device Session Valid State Change Interrupt Status + * | | |0 = AVLD (OTG_STATUS[4]) not toggled. + * | | |1 = AVLD (OTG_STATUS[4]) from high to low or low to high. + * | | |Note: Write 1 to clear this status. + * |[10] |VBCHGIF |VBUSVLD State Change Interrupt Status + * | | |0 = VBUSVLD (OTG_STATUS[5]) not toggled. + * | | |1 = VBUSVLD (OTG_STATUS[5]) from high to low or from low to high. + * | | |Note: Write 1 to clear this status. + * |[11] |SECHGIF |SESSEND State Change Interrupt Status + * | | |0 = SESSEND (OTG_STATUS[2]) not toggled. + * | | |1 = SESSEND (OTG_STATUS[2]) from high to low or from low to high. + * | | |Note: Write 1 to clear this flag. + * |[13] |SRPDETIF |SRP Detected Interrupt Status + * | | |0 = SRP not detected. + * | | |1 = SRP detected. + * | | |Note: Write 1 to clear this status. + * @var OTG_T::STATUS + * Offset: 0x10 OTG Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |OVERCUR |Over Current Condition + * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A-device drives VBUS high. + * | | |0 = OTG A-device drives VBUS successfully. + * | | |1 = OTG A-device cannot drives VBUS high in this interval. + * |[1] |IDSTS |USB_ID Pin State of Mini-/Micro- Plug + * | | |0 = Mini-A/Micro-A plug is attached. + * | | |1 = Mini-B/Micro-B plug is attached. + * |[2] |SESSEND |Session End Status + * | | |When VBUS voltage is lower than 0.4V, this bit will be set to 1 + * | | |Session end means no meaningful power on VBUS. + * | | |0 = Session is not end. + * | | |1 = Session is end. + * |[3] |BVLD |B-device Session Valid Status + * | | |0 = B-device session is not valid. + * | | |1 = B-device session is valid. + * |[4] |AVLD |A-device Session Valid Status + * | | |0 = A-device session is not valid. + * | | |1 = A-device session is valid. + * |[5] |VBUSVLD |VBUS Valid Status + * | | |When VBUS is larger than 4.7V, this bit will be set to 1. + * | | |0 = VBUS is not valid. + * | | |1 = VBUS is valid. + * |[6] |ASPERI |As Peripheral Status + * | | |When OTG as peripheral, this bit is set. + * | | |0: OTG not as peripheral + * | | |1: OTG as peripheral + * |[7] |ASHOST |As Host Status + * | | |When OTG as Host, this bit is set. + * | | |0: OTG not as Host + * | | |1: OTG as Host + */ + __IO uint32_t CTL; /*!< [0x0000] OTG Control Register */ + __IO uint32_t PHYCTL; /*!< [0x0004] OTG PHY Control Register */ + __IO uint32_t INTEN; /*!< [0x0008] OTG Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x000c] OTG Interrupt Status Register */ + __I uint32_t STATUS; /*!< [0x0010] OTG Status Register */ + +} OTG_T; + +/** + @addtogroup OTG_CONST OTG Bit Field Definition + Constant Definitions for OTG Controller + @{ +*/ + +#define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG_T::CTL: VBUSDROP Position */ +#define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG_T::CTL: VBUSDROP Mask */ + +#define OTG_CTL_BUSREQ_Pos (1) /*!< OTG_T::CTL: BUSREQ Position */ +#define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG_T::CTL: BUSREQ Mask */ + +#define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG_T::CTL: HNPREQEN Position */ +#define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG_T::CTL: HNPREQEN Mask */ + +#define OTG_CTL_OTGEN_Pos (4) /*!< OTG_T::CTL: OTGEN Position */ +#define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG_T::CTL: OTGEN Mask */ + +#define OTG_CTL_WKEN_Pos (5) /*!< OTG_T::CTL: WKEN Position */ +#define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG_T::CTL: WKEN Mask */ + +#define OTG_PHYCTL_OTGPHYEN_Pos (0) /*!< OTG_T::PHYCTL: OTGPHYEN Position */ +#define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG_T::PHYCTL: OTGPHYEN Mask */ + +#define OTG_PHYCTL_IDDETEN_Pos (1) /*!< OTG_T::PHYCTL: IDDETEN Position */ +#define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG_T::PHYCTL: IDDETEN Mask */ + +#define OTG_PHYCTL_VBENPOL_Pos (4) /*!< OTG_T::PHYCTL: VBENPOL Position */ +#define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG_T::PHYCTL: VBENPOL Mask */ + +#define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG_T::PHYCTL: VBSTSPOL Position */ +#define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG_T::PHYCTL: VBSTSPOL Mask */ + +#define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG_T::INTEN: ROLECHGIEN Position */ +#define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG_T::INTEN: ROLECHGIEN Mask */ + +#define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG_T::INTEN: VBEIEN Position */ +#define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG_T::INTEN: VBEIEN Mask */ + +#define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG_T::INTEN: SRPFIEN Position */ +#define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG_T::INTEN: SRPFIEN Mask */ + +#define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG_T::INTEN: HNPFIEN Position */ +#define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG_T::INTEN: HNPFIEN Mask */ + +#define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG_T::INTEN: GOIDLEIEN Position */ +#define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG_T::INTEN: GOIDLEIEN Mask */ + +#define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG_T::INTEN: IDCHGIEN Position */ +#define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG_T::INTEN: IDCHGIEN Mask */ + +#define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG_T::INTEN: PDEVIEN Position */ +#define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG_T::INTEN: PDEVIEN Mask */ + +#define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG_T::INTEN: HOSTIEN Position */ +#define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG_T::INTEN: HOSTIEN Mask */ + +#define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG_T::INTEN: BVLDCHGIEN Position */ +#define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG_T::INTEN: BVLDCHGIEN Mask */ + +#define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG_T::INTEN: AVLDCHGIEN Position */ +#define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG_T::INTEN: AVLDCHGIEN Mask */ + +#define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG_T::INTEN: VBCHGIEN Position */ +#define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG_T::INTEN: VBCHGIEN Mask */ + +#define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG_T::INTEN: SECHGIEN Position */ +#define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG_T::INTEN: SECHGIEN Mask */ + +#define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG_T::INTEN: SRPDETIEN Position */ +#define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG_T::INTEN: SRPDETIEN Mask */ + +#define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG_T::INTSTS: ROLECHGIF Position */ +#define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG_T::INTSTS: ROLECHGIF Mask */ + +#define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG_T::INTSTS: VBEIF Position */ +#define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG_T::INTSTS: VBEIF Mask */ + +#define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG_T::INTSTS: SRPFIF Position */ +#define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG_T::INTSTS: SRPFIF Mask */ + +#define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG_T::INTSTS: HNPFIF Position */ +#define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG_T::INTSTS: HNPFIF Mask */ + +#define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG_T::INTSTS: GOIDLEIF Position */ +#define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG_T::INTSTS: GOIDLEIF Mask */ + +#define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG_T::INTSTS: IDCHGIF Position */ +#define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG_T::INTSTS: IDCHGIF Mask */ + +#define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG_T::INTSTS: PDEVIF Position */ +#define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG_T::INTSTS: PDEVIF Mask */ + +#define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG_T::INTSTS: HOSTIF Position */ +#define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG_T::INTSTS: HOSTIF Mask */ + +#define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG_T::INTSTS: BVLDCHGIF Position */ +#define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG_T::INTSTS: BVLDCHGIF Mask */ + +#define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG_T::INTSTS: AVLDCHGIF Position */ +#define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG_T::INTSTS: AVLDCHGIF Mask */ + +#define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG_T::INTSTS: VBCHGIF Position */ +#define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG_T::INTSTS: VBCHGIF Mask */ + +#define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG_T::INTSTS: SECHGIF Position */ +#define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG_T::INTSTS: SECHGIF Mask */ + +#define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG_T::INTSTS: SRPDETIF Position */ +#define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG_T::INTSTS: SRPDETIF Mask */ + +#define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG_T::STATUS: OVERCUR Position */ +#define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG_T::STATUS: OVERCUR Mask */ + +#define OTG_STATUS_IDSTS_Pos (1) /*!< OTG_T::STATUS: IDSTS Position */ +#define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG_T::STATUS: IDSTS Mask */ + +#define OTG_STATUS_SESSEND_Pos (2) /*!< OTG_T::STATUS: SESSEND Position */ +#define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG_T::STATUS: SESSEND Mask */ + +#define OTG_STATUS_BVLD_Pos (3) /*!< OTG_T::STATUS: BVLD Position */ +#define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG_T::STATUS: BVLD Mask */ + +#define OTG_STATUS_AVLD_Pos (4) /*!< OTG_T::STATUS: AVLD Position */ +#define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG_T::STATUS: AVLD Mask */ + +#define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG_T::STATUS: VBUSVLD Position */ +#define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG_T::STATUS: VBUSVLD Mask */ + +#define OTG_STATUS_ASPERI_Pos (6) /*!< OTG_T::STATUS: ASPERI Position */ +#define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) /*!< OTG_T::STATUS: ASPERI Mask */ + +#define OTG_STATUS_ASHOST_Pos (7) /*!< OTG_T::STATUS: ASHOST Position */ +#define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) /*!< OTG_T::STATUS: ASHOST Mask */ + +/**@}*/ /* OTG_CONST */ +/**@}*/ /* end of OTG register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __OTG_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/pdma_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/pdma_reg.h new file mode 100644 index 0000000000..f47f6267f7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/pdma_reg.h @@ -0,0 +1,814 @@ +/**************************************************************************//** + * @file pdma_reg.h + * @version V1.00 + * @brief PDMA register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_REG_H__ +#define __PDMA_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/ +/** + @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA) + Memory Mapped Structure for PDMA Controller + @{ +*/ + + + +typedef struct +{ + /** + * @var DSCT_T::CTL + * Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70 Descriptor Table Control Register of PDMA Channel 0~7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE |PDMA Operation Mode Selection + * | | |00 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically. + * | | |01 = Basic mode: The descriptor table only has one task + * | | |When this task is finished, the TDIF(PDMA_INTSTS[1]) will be asserted. + * | | |10 = Scatter-Gather mode: When operating in this mode, user must give the first descriptor table address in PDMA_DSCT_FIRST register; PDMA controller will ignore this task, then load the next task to execute. + * | | |11 = Reserved. + * | | |Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete. + * |[2] |TXTYPE |Transfer Type + * | | |0 = Burst transfer type. + * | | |1 = Single transfer type. + * |[6:4] |BURSIZE |Burst Size + * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size. + * | | |000 = 128 Transfers. + * | | |001 = 64 Transfers. + * | | |010 = 32 Transfers. + * | | |011 = 16 Transfers. + * | | |100 = 8 Transfers. + * | | |101 = 4 Transfers. + * | | |110 = 2 Transfers. + * | | |111 = 1 Transfers. + * | | |Note: This field is only useful in burst transfer type. + * |[7] |TBINTDIS |Table Interrupt Disable Bit + * | | |This field can be used to decide whether to enable table interrupt or not + * | | |If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates transfer done interrupt. + * | | |0 = Table interrupt Enabled. + * | | |1 = Table interrupt Disabled. + * | | |Note: If this bit set to 1, the TEMPTYF will not be set. + * |[9:8] |SAINC |Source Address Increment + * | | |This field is used to set the source address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[11:10] |DAINC |Destination Address Increment + * | | |This field is used to set the destination address increment size. + * | | |11 = No increment (fixed address). + * | | |Others = Increment and size is depended on TXWIDTH selection. + * |[13:12] |TXWIDTH |Transfer Width Selection + * | | |This field is used for transfer width. + * | | |00 = One byte (8 bit) is transferred for every operation. + * | | |01 = One half-word (16 bit) is transferred for every operation. + * | | |10 = One word (32-bit) is transferred for every operation. + * | | |11 = Reserved. + * | | |Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection + * | | |For example, if source address is 0x2000_0202, but TXWIDTH is word transfer, the source address is not word alignment + * | | |The source address is aligned when TXWIDTH is byte or half-word transfer. + * |[14] |TXACK |Transfer Acknowledge Selection + * | | |0 = transfer ack when transfer done. + * | | |1 = transfer ack when PDMA get transfer data. + * |[15] |STRIDEEN |Stride Mode Enable Bit + * | | |0 = Stride transfer mode Disabled. + * | | |1 = Stride transfer mode Enabled. + * |[31:16] |TXCNT |Transfer Count + * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field. + * | | |Note: When PDMA finish each transfer data, this field will be decrease immediately. + * @var DSCT_T::SA + * Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74 Source Address Register of PDMA Channel 0~7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SA |PDMA Transfer Source Address Register + * | | |This field indicates a 32-bit source address of PDMA controller. + * | | |Note: The PDMA transfer source address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection. + * @var DSCT_T::DA + * Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78 Destination Address Register of PDMA Channel 0~7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |DA |PDMA Transfer Destination Address Register + * | | |This field indicates a 32-bit destination address of PDMA controller. + * | | |Note: The PDMA transfer destination address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection. + * @var DSCT_T::NEXT + * Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C First Scatter-Gather Descriptor Table Offset of PDMA Channel 0~7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FIRST |PDMA First Descriptor Table Offset + * | | |This field indicates the offset of the first descriptor table address in system memory. + * | | |Write Operation: + * | | |If the system memory based address is 0x2000_0000 (PDMA_SCATBA), and the first descriptor table is start from 0x2000_0100, then this field must fill in 0x0100. + * | | |Read Operation: + * | | |When operating in scatter-gather mode, the last two bits FIRST[1:0] will become reserved. + * | | |Note1: The first descriptor table address must be word boundary. + * | | |Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete. + * |[31:16] |NEXT |PDMA Next Descriptor Table Offset + * | | |This field indicates the offset of next descriptor table address in system memory. + * | | |Note: write operation is useless in this field. + */ + + __IO uint32_t CTL; /*!< [0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70] Descriptor Table Control Register of PDMA Channel 0~7 */ + __IO uint32_t SA; /*!< [0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74] Source Address Register of PDMA Channel 0~7 */ + __IO uint32_t DA; /*!< [0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78] Destination Address Register of PDMA Channel 0~7 */ + __IO uint32_t NEXT; /*!< [0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C]Next Scatter-Gather Descriptor Table Offset */ + +} DSCT_T; + +typedef struct +{ + /** + * @var STRIDE_T::STCR + * Offset: 0x500/0x508/0x510/0x518/0x520/0x528 Stride Transfer Count Register of PDMA Channel 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STC |PDMA Stride Transfer Count + * | | |The 16-bit register defines the stride transfer count of each row. + * @var STRIDE_T::ASOCR + * Offset: 0x504/0x50C/0x514/0x51C/0x524/0x52C Address Stride Offset Register of PDMA Channel 0~5 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SASOL |VDMA Source Address Stride Offset Length + * | | |The 16-bit register defines the source address stride transfer offset count of each row. + * |[31:16] |DASOL |VDMA Destination Address Stride Offset Length + * | | |The 16-bit register defines the destination address stride transfer offset count of each row. + */ + __IO uint32_t STCR; /*!< [0x0500/0x508/0x510/0x518/0x520/0x528] Stride Transfer Count Register of PDMA Channel 0~7 */ + __IO uint32_t ASOCR; /*!< [0x0504/0x50C/0x514/0x51C/0x524/0x52C] Address Stride Offset Register of PDMA Channel 0 */ +} STRIDE_T; + +typedef struct +{ + /** + * @var REPEAT_T::AICTL + * Offset: 0x600 Address Interval Control Register of PDMA Channel n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SAICNT |PDMA Source Address Interval Count + * | | |The 16-bit register defines the source address interval count of each row. + * |[31:16] |DAICNT |PDMA Destination Address Interval Count + * | | |The 16-bit register defines the destination address interval count of each row. + * @var REPEAT_T::RCNT + * Offset: 0x604 Repeat Count Register of PDMA Channe n + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RCNT |PDMA Repeat Count + * | | |The 16-bit register defines the repeat times of block transfer. + */ + __IO uint32_t AICTL; /*!< [0x0600] Address Interval Control Register of PDMA Channel 0 */ + __IO uint32_t RCNT; /*!< [0x0604] Repeat Count Register of PDMA Channel 0 */ +} REPEAT_T; + +typedef struct +{ + + + /** + * @var PDMA_T::CURSCAT + * Offset: 0x80/0x84/0x88/0x8C/0x90/0x94/0x98/0x9C Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CURADDR |PDMA Current Description Address Register (Read Only) + * | | |This field indicates a 32-bit current external description address of PDMA controller. + * | | |Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address. + * @var PDMA_T::CHCTL + * Offset: 0x400 PDMA Channel Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CHENn |PDMA Channel Enable Bit + * | | |Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled. + * | | |0 = PDMA channel [n] Disabled. + * | | |1 = PDMA channel [n] Enabled. + * | | |Note: Set corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit. + * @var PDMA_T::PAUSE + * Offset: 0x404 PDMA Transfer Pause Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PAUSEn |PDMA Transfer Pause Control Register (Write Only) + * | | |User can set PAUSEn bit field to pause the PDMA transfer + * | | |When user sets PAUSEn bit, the PDMA controller will pause the on-going transfer, then clear the channel enable bit CHEN(PDMA_CHCTL [n], n=0,1..7) and clear request active flag + * | | |If re-enable the paused channel again, the remaining transfers will be processed. + * | | |0 = No effect. + * | | |1 = Pause PDMA channel n transfer. + * @var PDMA_T::SWREQ + * Offset: 0x408 PDMA Software Request Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |SWREQn |PDMA Software Request Register (Write Only) + * | | |Set this bit to 1 to generate a software request to PDMA [n]. + * | | |0 = No effect. + * | | |1 = Generate a software request. + * | | |Note1: User can read PDMA_TRGSTS register to know which channel is on active + * | | |Active flag may be triggered by software request or peripheral request. + * | | |Note2: If user does not enable corresponding PDMA channel, the software request will be ignored. + * @var PDMA_T::TRGSTS + * Offset: 0x40C PDMA Channel Request Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |REQSTSn |PDMA Channel Request Status (Read Only) + * | | |This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral + * | | |When PDMA controller finishes channel transfer, this bit will be cleared automatically. + * | | |0 = PDMA Channel n has no request. + * | | |1 = PDMA Channel n has a request. + * | | |Note: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing current transfer. + * @var PDMA_T::PRISET + * Offset: 0x410 PDMA Fixed Priority Setting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FPRISETn |PDMA Fixed Priority Setting Register + * | | |Set this bit to 1 to enable fixed priority level. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set PDMA channel [n] to fixed priority channel. + * | | |Read Operation: + * | | |0 = Corresponding PDMA channel is round-robin priority. + * | | |1 = Corresponding PDMA channel is fixed priority. + * | | |Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register. + * @var PDMA_T::PRICLR + * Offset: 0x414 PDMA Fixed Priority Clear Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FPRICLRn |PDMA Fixed Priority Clear Register (Write Only) + * | | |Set this bit to 1 to clear fixed priority level. + * | | |0 = No effect. + * | | |1 = Clear PDMA channel [n] fixed priority setting. + * | | |Note: User can read PDMA_PRISET register to know the channel priority. + * @var PDMA_T::INTEN + * Offset: 0x418 PDMA Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |INTENn |PDMA Interrupt Enable Register + * | | |This field is used for enabling PDMA channel[n] interrupt. + * | | |0 = PDMA channel n interrupt Disabled. + * | | |1 = PDMA channel n interrupt Enabled. + * @var PDMA_T::INTSTS + * Offset: 0x41C PDMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Flag (Read Only) + * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error. + * | | |0 = No AHB bus ERROR response received. + * | | |1 = AHB bus ERROR response received. + * |[1] |TDIF |Transfer Done Interrupt Flag (Read Only) + * | | |This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer. + * | | |0 = Not finished yet. + * | | |1 = PDMA channel has finished transmission. + * |[2] |ALIGNF |Transfer Alignment Interrupt Flag (Read Only) + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * |[8] |REQTOF0 |Request Time-out Flag for Channel 0 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * |[9] |REQTOF1 |Request Time-out Flag for Channel 1 + * | | |This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits. + * | | |0 = No request time-out. + * | | |1 = Peripheral request time-out. + * @var PDMA_T::ABTSTS + * Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ABTIFn |PDMA Read/Write Target Abort Interrupt Status Flag + * | | |This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits. + * | | |0 = No AHB bus ERROR response received when channel n transfer. + * | | |1 = AHB bus ERROR response received when channel n transfer. + * @var PDMA_T::TDSTS + * Offset: 0x424 PDMA Channel Transfer Done Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TDIFn |Transfer Done Flag Register + * | | |This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits. + * | | |0 = PDMA channel transfer has not finished. + * | | |1 = PDMA channel has finished transmission. + * @var PDMA_T::ALIGN + * Offset: 0x428 PDMA Transfer Alignment Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |ALIGNn |Transfer Alignment Flag Register + * | | |0 = PDMA channel source address and destination address both follow transfer width setting. + * | | |1 = PDMA channel source address or destination address is not follow transfer width setting. + * @var PDMA_T::TACTSTS + * Offset: 0x42C PDMA Transfer Active Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXACTFn |Transfer on Active Flag Register (Read Only) + * | | |This bit indicates which PDMA channel is in active. + * | | |0 = PDMA channel is not finished. + * | | |1 = PDMA channel is active. + * @var PDMA_T::TOUTPSC + * Offset: 0x430 PDMA Time-out Prescaler Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TOUTPSC0 |PDMA Channel 0 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 0 time-out clock source is HCLK/2^8. + * | | |001 = PDMA channel 0 time-out clock source is HCLK/2^9. + * | | |010 = PDMA channel 0 time-out clock source is HCLK/2^10. + * | | |011 = PDMA channel 0 time-out clock source is HCLK/2^11. + * | | |100 = PDMA channel 0 time-out clock source is HCLK/2^12. + * | | |101 = PDMA channel 0 time-out clock source is HCLK/2^13. + * | | |110 = PDMA channel 0 time-out clock source is HCLK/2^14. + * | | |111 = PDMA channel 0 time-out clock source is HCLK/2^15. + * |[6:4] |TOUTPSC1 |PDMA Channel 1 Time-out Clock Source Prescaler Bits + * | | |000 = PDMA channel 1 time-out clock source is HCLK/2^8. + * | | |001 = PDMA channel 1 time-out clock source is HCLK/2^9. + * | | |010 = PDMA channel 1 time-out clock source is HCLK/2^10. + * | | |011 = PDMA channel 1 time-out clock source is HCLK/2^11. + * | | |100 = PDMA channel 1 time-out clock source is HCLK/2^12. + * | | |101 = PDMA channel 1 time-out clock source is HCLK/2^13. + * | | |110 = PDMA channel 1 time-out clock source is HCLK/2^14. + * | | |111 = PDMA channel 1 time-out clock source is HCLK/2^15. + * @var PDMA_T::TOUTEN + * Offset: 0x434 PDMA Time-out Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOUTEN0 |PDMA Channel 0 Time-out Enable Bit + * | | |0 = PDMA Channel 0 time-out function Disable. + * | | |1 = PDMA Channel 0 time-out function Enable. + * |[1] |TOUTEN1 |PDMA Channel 1 Time-out Enable Bit + * | | |0 = PDMA Channel 1 time-out function Disable. + * | | |1 = PDMA Channel 1 time-out function Enable. + * @var PDMA_T::TOUTIEN + * Offset: 0x438 PDMA Time-out Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOUTIEN0 |PDMA Channel 0 Time-out Interrupt Enable Bit + * | | |0 = PDMA Channel 0 time-out interrupt Disable. + * | | |1 = PDMA Channel 0 time-out interrupt Enable. + * |[1] |TOUTIEN1 |PDMA Channel 1 Time-out Interrupt Enable Bit + * | | |0 = PDMA Channel 1 time-out interrupt Disable. + * | | |1 = PDMA Channel 1 time-out interrupt Enable. + * @var PDMA_T::SCATBA + * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |SCATBA |PDMA Scatter-gather Descriptor Table Address Register + * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address + * | | |The next link address equation is + * | | |Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT. + * | | |Note: Only useful in Scatter-Gather mode. + * @var PDMA_T::TOC0_1 + * Offset: 0x440 PDMA Channel 0 and Channel 1 Time-out Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TOC0 |Time-out Counter for Channel 0 + * | | |This controls the period of time-out function for channel 0 + * | | |The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock. + * | | |Time-out period = (Period of time-out clock) * (16-bit TOCn),n = 0,1. + * |[31:16] |TOC1 |Time-out Counter for Channel 1 + * | | |This controls the period of time-out function for channel 1 + * | | |The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock + * | | |The example of time-out period can refer TOC0 bit description. + * @var PDMA_T::CHRST + * Offset: 0x460 PDMA Channel Reset Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CHnRST |Channel N Reset + * | | |0 = corresponding channel n not reset. + * | | |1 = corresponding channel n is reset. + * @var PDMA_T::REQSEL0_3 + * Offset: 0x480 PDMA Channel 0 to Channel 3 Request Source Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC0 |Channel 0 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 0 + * | | |User can configure the peripheral by setting REQSRC0. + * | | |0 = Disable PDMA. + * | | |1 = Reserved. + * | | |2 = Channel connects to USB_TX. + * | | |3 = Channel connects to USB_RX. + * | | |4 = Channel connects to UART0_TX. + * | | |5 = Channel connects to UART0_RX. + * | | |6 = Channel connects to UART1_TX. + * | | |7 = Channel connects to UART1_RX. + * | | |8 = Channel connects to UART2_TX. + * | | |9 = Channel connects to UART2_RX. + * | | |10 = Channel connects to UART3_TX. + * | | |11 = Channel connects to UART3_RX. + * | | |12 = Channel connects to UART4_TX. + * | | |13 = Channel connects to UART4_RX. + * | | |14 = Channel connects to UART5_TX. + * | | |15 = Channel connects to UART5_RX. + * | | |16 = Channel connects to USCI0_TX. + * | | |17 = Channel connects to USCI0_RX. + * | | |18 = Channel connects to USCI1_TX. + * | | |19 = Channel connects to USCI1_RX. + * | | |20 = Channel connects to QSPI0_TX. + * | | |21 = Channel connects to QSPI0_RX. + * | | |22 = Channel connects to SPI0_TX. + * | | |23 = Channel connects to SPI0_RX. + * | | |24 = Channel connects to SPI1_TX. + * | | |25 = Channel connects to SPI1_RX. + * | | |26 = Channel connects to SPI2_TX. + * | | |27 = Channel connects to SPI2_RX. + * | | |28 = Channel connects to SPI3_TX. + * | | |29 = Channel connects to SPI3_RX. + * | | |30 = Channel connects to ADC_RX. + * | | |32 = Channel connects to EPWM0_P1_RX. + * | | |33 = Channel connects to EPWM0_P2_RX. + * | | |34 = Channel connects to EPWM0_P3_RX. + * | | |35 = Channel connects to EPWM1_P1_RX. + * | | |36 = Channel connects to EPWM1_P2_RX. + * | | |37 = Channel connects to EPWM1_P3_RX. + * | | |38 = Channel connects to I2C0_TX. + * | | |39 = Channel connects to I2C0_RX. + * | | |40 = Channel connects to I2C1_TX. + * | | |41 = Channel connects to I2C1_RX. + * | | |42 = Channel connects to I2C2_TX. + * | | |43 = Channel connects to I2C2_RX. + * | | |44 = Channel connects to I2S0_TX. + * | | |45 = Channel connects to I2S0_RX. + * | | |46 = Channel connects to TMR0. + * | | |47 = Channel connects to TMR1. + * | | |48 = Channel connects to TMR2. + * | | |49 = Channel connects to TMR3. + * | | |50 = Channel connects to TMR4. + * | | |51 = Channel connects to TMR5. + * | | |52 = Channel connects to DAC0_TX. + * | | |53 = Channel connects to DAC1_TX. + * | | |54 = Channel connects to EPWM0_CH0_TX. + * | | |55 = Channel connects to EPWM0_CH1_TX. + * | | |56 = Channel connects to EPWM0_CH2_TX. + * | | |57 = Channel connects to EPWM0_CH3_TX. + * | | |58 = Channel connects to EPWM0_CH4_TX. + * | | |59 = Channel connects to EPWM0_CH5_TX. + * | | |60 = Channel connects to EPWM1_CH0_TX. + * | | |61 = Channel connects to EPWM1_CH1_TX. + * | | |62 = Channel connects to EPWM1_CH2_TX. + * | | |63 = Channel connects to EPWM1_CH3_TX. + * | | |64 = Channel connects to EPWM1_CH4_TX. + * | | |65 = Channel connects to EPWM1_CH5_TX. + * | | |Others = Reserved. + * | | |Note 1: A request source cannot assign to two channels at the same time. + * | | |Note 2: This field is useless when transfer between memory and memory. + * |[14:8] |REQSRC1 |Channel 1 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 1 + * | | |User can configure the peripheral setting by REQSRC1. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC2 |Channel 2 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 2 + * | | |User can configure the peripheral setting by REQSRC2. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC3 |Channel 3 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 3 + * | | |User can configure the peripheral setting by REQSRC3. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * @var PDMA_T::REQSEL4_7 + * Offset: 0x484 PDMA Request Source Select Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |REQSRC4 |Channel 4 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 4 + * | | |User can configure the peripheral setting by REQSRC4. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[14:8] |REQSRC5 |Channel 5 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 5 + * | | |User can configure the peripheral setting by REQSRC5. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[22:16] |REQSRC6 |Channel 6 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 6 + * | | |User can configure the peripheral setting by REQSRC6. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + * |[30:24] |REQSRC7 |Channel 7 Request Source Selection + * | | |This filed defines which peripheral is connected to PDMA channel 7 + * | | |User can configure the peripheral setting by REQSRC7. + * | | |Note: The channel configuration is the same as REQSRC0 field + * | | |Please refer to the explanation of REQSRC0. + */ + + DSCT_T DSCT[8]; /*!< [0x0000 ~ 0x007C] DMA Embedded Description Table 0~7 */ + __I uint32_t CURSCAT[8]; /*!< [0x0080~0x009C] Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~7 */ + __I uint32_t RESERVE0[216]; + __IO uint32_t CHCTL; /*!< [0x0400] PDMA Channel Control Register */ + __O uint32_t PAUSE; /*!< [0x0404] PDMA Transfer Pause Control Register */ + __O uint32_t SWREQ; /*!< [0x0408] PDMA Software Request Register */ + __I uint32_t TRGSTS; /*!< [0x040c] PDMA Channel Request Status Register */ + __IO uint32_t PRISET; /*!< [0x0410] PDMA Fixed Priority Setting Register */ + __O uint32_t PRICLR; /*!< [0x0414] PDMA Fixed Priority Clear Register */ + __IO uint32_t INTEN; /*!< [0x0418] PDMA Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x041c] PDMA Interrupt Status Register */ + __IO uint32_t ABTSTS; /*!< [0x0420] PDMA Channel Read/Write Target Abort Flag Register */ + __IO uint32_t TDSTS; /*!< [0x0424] PDMA Channel Transfer Done Flag Register */ + __IO uint32_t ALIGN; /*!< [0x0428] PDMA Transfer Alignment Status Register */ + __I uint32_t TACTSTS; /*!< [0x042c] PDMA Transfer Active Flag Register */ + __IO uint32_t TOUTPSC; /*!< [0x0430] PDMA Time-out Prescaler Register */ + __IO uint32_t TOUTEN; /*!< [0x0434] PDMA Time-out Enable Register */ + __IO uint32_t TOUTIEN; /*!< [0x0438] PDMA Time-out Interrupt Enable Register */ + __IO uint32_t SCATBA; /*!< [0x043c] PDMA Scatter-Gather Descriptor Table Base Address Register */ + __IO uint32_t TOC0_1; /*!< [0x0440] PDMA Channel 0 and Channel 1 Time-out Counter Register */ + __I uint32_t RESERVE1[7]; + __IO uint32_t CHRST; /*!< [0x0460] PDMA Channel Reset Register */ + __I uint32_t RESERVE2[7]; + __IO uint32_t REQSEL0_3; /*!< [0x0480] PDMA Channel 0 to Channel 3 Request Source Select Register */ + __IO uint32_t REQSEL4_7; /*!< [0x0484] PDMA Channel 4 to Channel 7 Request Source Select Register */ + __I uint32_t RESERVE4[30]; + STRIDE_T STRIDE[6]; /*!< [0x0500 ~ 0x052C] Stride function control register of PDMA Channel 0 ~ 5 */ + __IO uint32_t RESERVE5[52]; + REPEAT_T REPEAT[2]; /*!< [0x0600 ~ 0x060C] Repeat Count Function Control Register of PDMA Channel 0 ~ 1 */ +} PDMA_T; + + + + +/** + @addtogroup PDMA_CONST PDMA Bit Field Definition + Constant Definitions for PDMA Controller + @{ +*/ + +#define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA_T::DSCT_CTL: OPMODE Position */ +#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA_T::DSCT_CTL: OPMODE Mask */ + +#define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA_T::DSCT_CTL: TXTYPE Position */ +#define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA_T::DSCT_CTL: TXTYPE Mask */ + +#define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA_T::DSCT_CTL: BURSIZE Position */ +#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA_T::DSCT_CTL: BURSIZE Mask */ + +#define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA_T::DSCT_CTL: TBINTDIS Position */ +#define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA_T::DSCT_CTL: TBINTDIS Mask */ + +#define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA_T::DSCT_CTL: SAINC Position */ +#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA_T::DSCT_CTL: SAINC Mask */ + +#define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA_T::DSCT_CTL: DAINC Position */ +#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA_T::DSCT_CTL: DAINC Mask */ + +#define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA_T::DSCT_CTL: TXWIDTH Position */ +#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA_T::DSCT_CTL: TXWIDTH Mask */ + +#define PDMA_DSCT_CTL_TXACK_Pos (14) /*!< PDMA_T::DSCT_CTL: TXACK Position */ +#define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) /*!< PDMA_T::DSCT_CTL: TXACK Mask */ + +#define PDMA_DSCT_CTL_STRIDEEN_Pos (15) /*!< PDMA_T::DSCT_CTL: STRIDEEN Position */ +#define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) /*!< PDMA_T::DSCT_CTL: STRIDEEN Mask */ + +#define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA_T::DSCT_CTL: TXCNT Position */ +#define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA_T::DSCT_CTL: TXCNT Mask */ + +#define PDMA_DSCT_SA_SA_Pos (0) /*!< PDMA_T::DSCT_SA: SA Position */ +#define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) /*!< PDMA_T::DSCT_SA: SA Mask */ + +#define PDMA_DSCT_DA_DA_Pos (0) /*!< PDMA_T::DSCT_DA: DA Position */ +#define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) /*!< PDMA_T::DSCT_DA: DA Mask */ + +#define PDMA_DSCT_NEXT_NEXT_Pos (0) /*!< PDMA_T::DSCT_NEXT: NEXT Position */ +#define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA_T::DSCT_NEXT: NEXT Mask */ + +#define PDMA_DSCT_NEXT_EXENEXT_Pos (16) /*!< PDMA_T::DSCT_FIRST: NEXT Position */ +#define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) /*!< PDMA_T::DSCT_FIRST: NEXT Mask */ + +#define PDMA_CURSCAT_CURADDR_Pos (0) /*!< PDMA_T::CURSCAT: CURADDR Position */ +#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) /*!< PDMA_T::CURSCAT: CURADDR Mask */ + +#define PDMA_CHCTL_CHENn_Pos (0) /*!< PDMA_T::CHCTL: CHENn Position */ +#define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) /*!< PDMA_T::CHCTL: CHENn Mask */ + +#define PDMA_PAUSE_PAUSEn_Pos (0) /*!< PDMA_T::PAUSE: PAUSEn Position */ +#define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) /*!< PDMA_T::PAUSE: PAUSEn Mask */ + +#define PDMA_SWREQ_SWREQn_Pos (0) /*!< PDMA_T::SWREQ: SWREQn Position */ +#define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) /*!< PDMA_T::SWREQ: SWREQn Mask */ + +#define PDMA_TRGSTS_REQSTSn_Pos (0) /*!< PDMA_T::TRGSTS: REQSTSn Position */ +#define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) /*!< PDMA_T::TRGSTS: REQSTSn Mask */ + +#define PDMA_PRISET_FPRISETn_Pos (0) /*!< PDMA_T::PRISET: FPRISETn Position */ +#define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) /*!< PDMA_T::PRISET: FPRISETn Mask */ + +#define PDMA_PRICLR_FPRICLRn_Pos (0) /*!< PDMA_T::PRICLR: FPRICLRn Position */ +#define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) /*!< PDMA_T::PRICLR: FPRICLRn Mask */ + +#define PDMA_INTEN_INTENn_Pos (0) /*!< PDMA_T::INTEN: INTENn Position */ +#define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) /*!< PDMA_T::INTEN: INTENn Mask */ + +#define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA_T::INTSTS: ABTIF Position */ +#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA_T::INTSTS: ABTIF Mask */ + +#define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA_T::INTSTS: TDIF Position */ +#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA_T::INTSTS: TDIF Mask */ + +#define PDMA_INTSTS_ALIGNF_Pos (2) /*!< PDMA_T::INTSTS: ALIGNF Position */ +#define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) /*!< PDMA_T::INTSTS: ALIGNF Mask */ + +#define PDMA_INTSTS_REQTOF0_Pos (8) /*!< PDMA_T::INTSTS: REQTOF0 Position */ +#define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) /*!< PDMA_T::INTSTS: REQTOF0 Mask */ + +#define PDMA_INTSTS_REQTOF1_Pos (9) /*!< PDMA_T::INTSTS: REQTOF1 Position */ +#define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) /*!< PDMA_T::INTSTS: REQTOF1 Mask */ + +#define PDMA_ABTSTS_ABTIF0_Pos (0) /*!< PDMA_T::ABTSTS: ABTIF0 Position */ +#define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) /*!< PDMA_T::ABTSTS: ABTIF0 Mask */ + +#define PDMA_ABTSTS_ABTIF1_Pos (1) /*!< PDMA_T::ABTSTS: ABTIF1 Position */ +#define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) /*!< PDMA_T::ABTSTS: ABTIF1 Mask */ + +#define PDMA_ABTSTS_ABTIF2_Pos (2) /*!< PDMA_T::ABTSTS: ABTIF2 Position */ +#define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) /*!< PDMA_T::ABTSTS: ABTIF2 Mask */ + +#define PDMA_ABTSTS_ABTIF3_Pos (3) /*!< PDMA_T::ABTSTS: ABTIF3 Position */ +#define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) /*!< PDMA_T::ABTSTS: ABTIF3 Mask */ + +#define PDMA_ABTSTS_ABTIF4_Pos (4) /*!< PDMA_T::ABTSTS: ABTIF4 Position */ +#define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) /*!< PDMA_T::ABTSTS: ABTIF4 Mask */ + +#define PDMA_ABTSTS_ABTIF5_Pos (5) /*!< PDMA_T::ABTSTS: ABTIF5 Position */ +#define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) /*!< PDMA_T::ABTSTS: ABTIF5 Mask */ + +#define PDMA_ABTSTS_ABTIF6_Pos (6) /*!< PDMA_T::ABTSTS: ABTIF6 Position */ +#define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) /*!< PDMA_T::ABTSTS: ABTIF6 Mask */ + +#define PDMA_ABTSTS_ABTIF7_Pos (7) /*!< PDMA_T::ABTSTS: ABTIF7 Position */ +#define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) /*!< PDMA_T::ABTSTS: ABTIF7 Mask */ + +#define PDMA_ABTSTS_ABTIF8_Pos (8) /*!< PDMA_T::ABTSTS: ABTIF8 Position */ +#define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) /*!< PDMA_T::ABTSTS: ABTIF8 Mask */ + +#define PDMA_ABTSTS_ABTIF9_Pos (9) /*!< PDMA_T::ABTSTS: ABTIF9 Position */ +#define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) /*!< PDMA_T::ABTSTS: ABTIF9 Mask */ + +#define PDMA_ABTSTS_ABTIF10_Pos (10) /*!< PDMA_T::ABTSTS: ABTIF10 Position */ +#define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) /*!< PDMA_T::ABTSTS: ABTIF10 Mask */ + +#define PDMA_ABTSTS_ABTIF11_Pos (11) /*!< PDMA_T::ABTSTS: ABTIF11 Position */ +#define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) /*!< PDMA_T::ABTSTS: ABTIF11 Mask */ + +#define PDMA_ABTSTS_ABTIF12_Pos (12) /*!< PDMA_T::ABTSTS: ABTIF12 Position */ +#define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) /*!< PDMA_T::ABTSTS: ABTIF12 Mask */ + +#define PDMA_ABTSTS_ABTIF13_Pos (13) /*!< PDMA_T::ABTSTS: ABTIF13 Position */ +#define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) /*!< PDMA_T::ABTSTS: ABTIF13 Mask */ + +#define PDMA_ABTSTS_ABTIF14_Pos (14) /*!< PDMA_T::ABTSTS: ABTIF14 Position */ +#define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) /*!< PDMA_T::ABTSTS: ABTIF14 Mask */ + +#define PDMA_ABTSTS_ABTIF15_Pos (15) /*!< PDMA_T::ABTSTS: ABTIF15 Position */ +#define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) /*!< PDMA_T::ABTSTS: ABTIF15 Mask */ + +#define PDMA_TDSTS_TDIF0_Pos (0) /*!< PDMA_T::TDSTS: TDIF0 Position */ +#define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) /*!< PDMA_T::TDSTS: TDIF0 Mask */ + +#define PDMA_TDSTS_TDIF1_Pos (1) /*!< PDMA_T::TDSTS: TDIF1 Position */ +#define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) /*!< PDMA_T::TDSTS: TDIF1 Mask */ + +#define PDMA_TDSTS_TDIF2_Pos (2) /*!< PDMA_T::TDSTS: TDIF2 Position */ +#define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) /*!< PDMA_T::TDSTS: TDIF2 Mask */ + +#define PDMA_TDSTS_TDIF3_Pos (3) /*!< PDMA_T::TDSTS: TDIF3 Position */ +#define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) /*!< PDMA_T::TDSTS: TDIF3 Mask */ + +#define PDMA_TDSTS_TDIF4_Pos (4) /*!< PDMA_T::TDSTS: TDIF4 Position */ +#define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) /*!< PDMA_T::TDSTS: TDIF4 Mask */ + +#define PDMA_TDSTS_TDIF5_Pos (5) /*!< PDMA_T::TDSTS: TDIF5 Position */ +#define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) /*!< PDMA_T::TDSTS: TDIF5 Mask */ + +#define PDMA_TDSTS_TDIF6_Pos (6) /*!< PDMA_T::TDSTS: TDIF6 Position */ +#define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) /*!< PDMA_T::TDSTS: TDIF6 Mask */ + +#define PDMA_TDSTS_TDIF7_Pos (7) /*!< PDMA_T::TDSTS: TDIF7 Position */ +#define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) /*!< PDMA_T::TDSTS: TDIF7 Mask */ + +#define PDMA_TDSTS_TDIF8_Pos (8) /*!< PDMA_T::TDSTS: TDIF8 Position */ +#define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) /*!< PDMA_T::TDSTS: TDIF8 Mask */ + +#define PDMA_TDSTS_TDIF9_Pos (9) /*!< PDMA_T::TDSTS: TDIF9 Position */ +#define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) /*!< PDMA_T::TDSTS: TDIF9 Mask */ + +#define PDMA_TDSTS_TDIF10_Pos (10) /*!< PDMA_T::TDSTS: TDIF10 Position */ +#define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) /*!< PDMA_T::TDSTS: TDIF10 Mask */ + +#define PDMA_TDSTS_TDIF11_Pos (11) /*!< PDMA_T::TDSTS: TDIF11 Position */ +#define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) /*!< PDMA_T::TDSTS: TDIF11 Mask */ + +#define PDMA_TDSTS_TDIF12_Pos (12) /*!< PDMA_T::TDSTS: TDIF12 Position */ +#define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) /*!< PDMA_T::TDSTS: TDIF12 Mask */ + +#define PDMA_TDSTS_TDIF13_Pos (13) /*!< PDMA_T::TDSTS: TDIF13 Position */ +#define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) /*!< PDMA_T::TDSTS: TDIF13 Mask */ + +#define PDMA_TDSTS_TDIF14_Pos (14) /*!< PDMA_T::TDSTS: TDIF14 Position */ +#define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) /*!< PDMA_T::TDSTS: TDIF14 Mask */ + +#define PDMA_TDSTS_TDIF15_Pos (15) /*!< PDMA_T::TDSTS: TDIF15 Position */ +#define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) /*!< PDMA_T::TDSTS: TDIF15 Mask */ + +#define PDMA_ALIGN_ALIGNn_Pos (0) /*!< PDMA_T::ALIGN: ALIGNn Position */ +#define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) /*!< PDMA_T::ALIGN: ALIGNn Mask */ + +#define PDMA_TACTSTS_TXACTFn_Pos (0) /*!< PDMA_T::TACTSTS: TXACTFn Position */ +#define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) /*!< PDMA_T::TACTSTS: TXACTFn Mask */ + +#define PDMA_TOUTPSC_TOUTPSC0_Pos (0) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Position */ +#define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC0 Mask */ + +#define PDMA_TOUTPSC_TOUTPSC1_Pos (4) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Position */ +#define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) /*!< PDMA_T::TOUTPSC: TOUTPSC1 Mask */ + +#define PDMA_TOUTEN_TOUTENn_Pos (0) /*!< PDMA_T::TOUTEN: TOUTENn Position */ +#define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) /*!< PDMA_T::TOUTEN: TOUTENn Mask */ + +#define PDMA_TOUTIEN_TOUTIENn_Pos (0) /*!< PDMA_T::TOUTIEN: TOUTIENn Position */ +#define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) /*!< PDMA_T::TOUTIEN: TOUTIENn Mask */ + +#define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA_T::SCATBA: SCATBA Position */ +#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA_T::SCATBA: SCATBA Mask */ + +#define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA_T::TOC0_1: TOC0 Position */ +#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA_T::TOC0_1: TOC0 Mask */ + +#define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA_T::TOC0_1: TOC1 Position */ +#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA_T::TOC0_1: TOC1 Mask */ + +#define PDMA_CHRST_CHnRST_Pos (0) /*!< PDMA_T::CHRST: CHnRST Position */ +#define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) /*!< PDMA_T::CHRST: CHnRST Mask */ + +#define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA_T::REQSEL0_3: REQSRC0 Position */ +#define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC0 Mask */ + +#define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA_T::REQSEL0_3: REQSRC1 Position */ +#define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC1 Mask */ + +#define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA_T::REQSEL0_3: REQSRC2 Position */ +#define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC2 Mask */ + +#define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA_T::REQSEL0_3: REQSRC3 Position */ +#define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA_T::REQSEL0_3: REQSRC3 Mask */ + +#define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA_T::REQSEL4_7: REQSRC4 Position */ +#define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC4 Mask */ + +#define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA_T::REQSEL4_7: REQSRC5 Position */ +#define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC5 Mask */ + +#define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA_T::REQSEL4_7: REQSRC6 Position */ +#define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC6 Mask */ + +#define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA_T::REQSEL4_7: REQSRC7 Position */ +#define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA_T::REQSEL4_7: REQSRC7 Mask */ + +#define PDMA_STCRn_STC_Pos (0) /*!< PDMA_T::STCRn: STC Position */ +#define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) /*!< PDMA_T::STCRn: STC Mask */ + +#define PDMA_ASOCRn_SASOL_Pos (0) /*!< PDMA_T::ASOCRn: SASOL Position */ +#define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::ASOCRn: SASOL Mask */ + +#define PDMA_ASOCRn_DASOL_Pos (16) /*!< PDMA_T::ASOCRn: DASOL Position */ +#define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::ASOCRn: DASOL Mask */ + +#define PDMA_AICTLn_SAICNT_Pos (0) /*!< PDMA_T::AICTLn: SAICNT Position */ +#define PDMA_AICTLn_SAICNT_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) /*!< PDMA_T::AICTLn: SAICNT Mask */ + +#define PDMA_AICTLn_DAICNT_Pos (16) /*!< PDMA_T::AICTLn: DAICNT Position */ +#define PDMA_AICTLn_DAICNT_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) /*!< PDMA_T::AICTLn: DAICNT Mask */ + +#define PDMA_RCNTn_RCNT_Pos (0) /*!< PDMA_T::RCNTn: RCNT Position */ +#define PDMA_RCNTn_RCNT_Msk (0xfffful << PDMA_STCRn_RCNT_Pos) /*!< PDMA_T::RCNTn: RCNT Mask */ + +/**@}*/ /* PDMA_CONST */ +/**@}*/ /* end of PDMA register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __PDMA_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/qei_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/qei_reg.h new file mode 100644 index 0000000000..ce9a92ab3b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/qei_reg.h @@ -0,0 +1,308 @@ +/**************************************************************************//** + * @file qei_reg.h + * @version V1.00 + * @brief QEI register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __QEI_REG_H__ +#define __QEI_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Quadrature Encoder Interface -------------------------*/ +/** + @addtogroup QEI Quadrature Encoder Interface(QEI) + Memory Mapped Structure for QEI Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var QEI_T::CNT + * Offset: 0x00 QEI Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNT |Quadrature Encoder Interface Counter + * | | |A 32-bit up/down counter + * | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[8]) is one or decreased by one if the bit DIRF is zero + * | | |This register performs an integrator which count value is proportional to the encoder position + * | | |The pulse counter may be initialized to a predetermined value by one of three events occurs: + * | | |1. Software is written if QEIEN (QEI_CTL[29]) = 0. + * | | |2. Compare-match event if QEIEN=1 and QEI is in compare-counting mode. + * | | |3. Index signal change if QEIEN=1 and IDXRLDEN (QEI_CTL[27])=1. + * @var QEI_T::CNTHOLD + * Offset: 0x04 QEI Counter Hold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTHOLD |Quadrature Encoder Interface Counter Hold + * | | |When bit HOLDCNT (QEI_CTL[24]) goes from low to high, the CNT(QEI_CNT[31:0]) is copied into CNTHOLD (QEI_CNTHOLD[31:0]) register. + * @var QEI_T::CNTLATCH + * Offset: 0x08 QEI Counter Index Latch Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTLATCH |Quadrature Encoder Interface Counter Index Latch + * | | |When the IDXF (QEI_STATUS[0]) bit is set, the CNT(QEI_CNT[31:0]) is copied into CNTLATCH (QEI_CNTLATCH[31:0]) register. + * @var QEI_T::CNTCMP + * Offset: 0x0C QEI Counter Compare Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTCMP |Quadrature Encoder Interface Counter Compare + * | | |If the QEI controller is in the compare-counting mode CMPEN (QEI_CTL[28]) =1, when the value of CNT(QEI_CNT[31:0]) matches CNTCMP(QEI_CNTCMP[31:0]), CMPF will be set + * | | |This register is software writable. + * @var QEI_T::CNTMAX + * Offset: 0x14 QEI Pre-set Maximum Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |CNTMAX |Quadrature Encoder Interface Preset Maximum Count + * | | |This register value determined by user stores the maximum value which may be the number of the QEI counter for the QEI controller compare-counting mode + * @var QEI_T::CTL + * Offset: 0x18 QEI Controller Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |NFCLKSEL |Noise Filter Clock Pre-divide Selection + * | | |To determine the sampling frequency of the Noise Filter clock . + * | | |000 = QEI_CLK. + * | | |001 = QEI_CLK/2. + * | | |010 = QEI_CLK/4. + * | | |011 = QEI_CLK/16. + * | | |100 = QEI_CLK/32. + * | | |101 = QEI_CLK/64. + * |[3] |NFDIS |QEI Controller Input Noise Filter Disable Bit + * | | |0 = The noise filter of QEI controller Enabled. + * | | |1 = The noise filter of QEI controller Disabled. + * |[4] |CHAEN |QEA Input to QEI Controller Enable Bit + * | | |0 = QEA input to QEI Controller Disabled. + * | | |1 = QEA input to QEI Controller Enabled. + * |[5] |CHBEN |QEB Input to QEI Controller Enable Bit + * | | |0 = QEB input to QEI Controller Disabled. + * | | |1 = QEB input to QEI Controller Enabled. + * |[6] |IDXEN |IDX Input to QEI Controller Enable Bit + * | | |0 = IDX input to QEI Controller Disabled. + * | | |1 = IDX input to QEI Controller Enabled. + * |[9:8] |MODE |QEI Counting Mode Selection + * | | |There are four quadrature encoder pulse counter operation modes. + * | | |00 = X4 Free-counting Mode. + * | | |01 = X2 Free-counting Mode. + * | | |10 = X4 Compare-counting Mode. + * | | |11 = X2 Compare-counting Mode. + * |[12] |CHAINV |Inverse QEA Input Polarity + * | | |0 = Not inverse QEA input polarity. + * | | |1 = QEA input polarity is inverse to QEI controller. + * |[13] |CHBINV |Inverse QEB Input Polarity + * | | |0 = Not inverse QEB input polarity. + * | | |1 = QEB input polarity is inverse to QEI controller. + * |[14] |IDXINV |Inverse IDX Input Polarity + * | | |0 = Not inverse IDX input polarity. + * | | |1 = IDX input polarity is inverse to QEI controller. + * |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Bit + * | | |0 = OVUNF can trigger QEI controller interrupt Disabled. + * | | |1 = OVUNF can trigger QEI controller interrupt Enabled. + * |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Bit + * | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled. + * | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled. + * |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Bit + * | | |0 = CMPF can trigger QEI controller interrupt Disabled. + * | | |1 = CMPF can trigger QEI controller interrupt Enabled. + * |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Bit + * | | |0 = The IDXF can trigger QEI interrupt Disabled. + * | | |1 = The IDXF can trigger QEI interrupt Enabled. + * |[20] |HOLDTMR0 |Hold QEI_CNT by Timer 0 + * | | |0 = TIF (TIMER0_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER0_INTSTS[0]) in timer 0 sets HOLDCNT to 1. + * |[21] |HOLDTMR1 |Hold QEI_CNT by Timer 1 + * | | |0 = TIF(TIMER1_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF (TIMER1_INTSTS[0]) in timer 1 sets HOLDCNT to 1. + * |[22] |HOLDTMR2 |Hold QEI_CNT by Timer 2 + * | | |0 = TIF(TIMER2_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER2_INTSTS[0]) in timer 2 sets HOLDCNT to 1. + * |[23] |HOLDTMR3 |Hold QEI_CNT by Timer 3 + * | | |0 = TIF (TIMER3_INTSTS[0]) has no effect on HOLDCNT. + * | | |1 = A rising edge of bit TIF(TIMER3_INTSTS[0]) in timer 3 sets HOLDCNT to 1. + * |[24] |HOLDCNT |Hold QEI_CNT Control + * | | |When this bit is set from low to high, the CNT(QEI_CNT[31:0]) is copied into QEI_CNTHOLD + * | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TIMERx_INTSTS[0]). + * | | |0 = No operation. + * | | |1 = QEI_CNT content is captured and stored in QEI_CNTHOLD. + * | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value. + * |[25] |IDXLATEN |Index Latch QEI_CNT Enable Bit + * | | |If this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX. + * | | |0 = The index signal latch QEI counter function Disabled. + * | | |1 = The index signal latch QEI counter function Enabled. + * |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Bit + * | | |When this bit is high and a rising edge comes on signal CHX, the QEI_CNT will be reset to zero if the counter is in up-counting type (DIRF = 1); while the QEI_CNT will be reloaded with CNTMAX (QEI_CNTMAX[31:0]) content if the counter is in down-counting type (DIRF = 0). + * | | |0 = Reload function Disabled. + * | | |1 = QEI_CNT re-initialized by Index signal Enabled. + * |[28] |CMPEN |the Compare Function Enable Bit + * | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register CNTCMP( QEI_CNTCMP[31:0]), if CNT(QEI_CNT[31:0]) reaches CNTCMP( QEI_CNTCMP[31:0]), the flag CMPF will be set. + * | | |0 = Compare function Disabled. + * | | |1 = Compare function Enabled. + * |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Bit + * | | |0 = QEI controller function Disabled. + * | | |1 = QEI controller function Enabled. + * @var QEI_T::STATUS + * Offset: 0x2C QEI Controller Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IDXF |IDX Detected Flag + * | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high. + * | | |0 = No rising edge detected on signal CHX. + * | | |1 = A rising edge occurs on signal CHX. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[1] |CMPF |Compare-match Flag + * | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the CNTCMP(QEI_CNTCMP[31:0]). + * | | |0 = QEI counter does not match with CNTCMP(QEI_CNTCMP[31:0]). + * | | |1 = QEI counter counts to the same as CNTCMP(QEI_CNTCMP[31:0]). + * | | |Note: This bit is only cleared by writing 1 to it. + * |[2] |OVUNF |QEI Counter Overflow or Underflow Flag + * | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the CNTMAX (QEI_CNTMAX[31:0]) to zero in compare-counting mode + * | | |Similarly, the flag is set wile QEI counter underflow from zero to 0xFFFF_FFFF or CNTMAX (QEI_CNTMAX[31:0]). + * | | |0 = No overflow or underflow occurs in QEI counter. + * | | |1 = QEI counter occurs counting overflow or underflow. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[3] |DIRCHGF |Direction Change Flag + * | | |Flag is set by hardware while QEI counter counting direction is changed + * | | |Software can clear this bit by writing 1 to it. + * | | |0 = No change in QEI counter counting direction. + * | | |1 = QEI counter counting direction is changed. + * | | |Note: This bit is only cleared by writing 1 to it. + * |[8] |DIRF |QEI Counter Counting Direction Indication + * | | |0 = QEI Counter is in down-counting. + * | | |1 = QEI Counter is in up-counting. + * | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB. + */ + __IO uint32_t CNT; /*!< [0x0000] QEI Counter Register */ + __IO uint32_t CNTHOLD; /*!< [0x0004] QEI Counter Hold Register */ + __IO uint32_t CNTLATCH; /*!< [0x0008] QEI Counter Index Latch Register */ + __IO uint32_t CNTCMP; /*!< [0x000c] QEI Counter Compare Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t CNTMAX; /*!< [0x0014] QEI Pre-set Maximum Count Register */ + __IO uint32_t CTL; /*!< [0x0018] QEI Controller Control Register */ + __I uint32_t RESERVE1[4]; + __IO uint32_t STATUS; /*!< [0x002c] QEI Controller Status Register */ + +} QEI_T; + +/** + @addtogroup QEI_CONST QEI Bit Field Definition + Constant Definitions for QEI Controller + @{ +*/ + +#define QEI_CNT_CNT_Pos (0) /*!< QEI_T::CNT: CNT Position */ +#define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) /*!< QEI_T::CNT: CNT Mask */ + +#define QEI_CNTHOLD_CNTHOLD_Pos (0) /*!< QEI_T::CNTHOLD: CNTHOLD Position */ +#define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) /*!< QEI_T::CNTHOLD: CNTHOLD Mask */ + +#define QEI_CNTLATCH_CNTLATCH_Pos (0) /*!< QEI_T::CNTLATCH: CNTLATCH Position */ +#define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) /*!< QEI_T::CNTLATCH: CNTLATCH Mask */ + +#define QEI_CNTCMP_CNTCMP_Pos (0) /*!< QEI_T::CNTCMP: CNTCMP Position */ +#define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) /*!< QEI_T::CNTCMP: CNTCMP Mask */ + +#define QEI_CNTMAX_CNTMAX_Pos (0) /*!< QEI_T::CNTMAX: CNTMAX Position */ +#define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) /*!< QEI_T::CNTMAX: CNTMAX Mask */ + +#define QEI_CTL_NFCLKSEL_Pos (0) /*!< QEI_T::CTL: NFCLKSEL Position */ +#define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) /*!< QEI_T::CTL: NFCLKSEL Mask */ + +#define QEI_CTL_NFDIS_Pos (3) /*!< QEI_T::CTL: NFDIS Position */ +#define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) /*!< QEI_T::CTL: NFDIS Mask */ + +#define QEI_CTL_CHAEN_Pos (4) /*!< QEI_T::CTL: CHAEN Position */ +#define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) /*!< QEI_T::CTL: CHAEN Mask */ + +#define QEI_CTL_CHBEN_Pos (5) /*!< QEI_T::CTL: CHBEN Position */ +#define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) /*!< QEI_T::CTL: CHBEN Mask */ + +#define QEI_CTL_IDXEN_Pos (6) /*!< QEI_T::CTL: IDXEN Position */ +#define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) /*!< QEI_T::CTL: IDXEN Mask */ + +#define QEI_CTL_MODE_Pos (8) /*!< QEI_T::CTL: MODE Position */ +#define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) /*!< QEI_T::CTL: MODE Mask */ + +#define QEI_CTL_CHAINV_Pos (12) /*!< QEI_T::CTL: CHAINV Position */ +#define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) /*!< QEI_T::CTL: CHAINV Mask */ + +#define QEI_CTL_CHBINV_Pos (13) /*!< QEI_T::CTL: CHBINV Position */ +#define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) /*!< QEI_T::CTL: CHBINV Mask */ + +#define QEI_CTL_IDXINV_Pos (14) /*!< QEI_T::CTL: IDXINV Position */ +#define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) /*!< QEI_T::CTL: IDXINV Mask */ + +#define QEI_CTL_OVUNIEN_Pos (16) /*!< QEI_T::CTL: OVUNIEN Position */ +#define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) /*!< QEI_T::CTL: OVUNIEN Mask */ + +#define QEI_CTL_DIRIEN_Pos (17) /*!< QEI_T::CTL: DIRIEN Position */ +#define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) /*!< QEI_T::CTL: DIRIEN Mask */ + +#define QEI_CTL_CMPIEN_Pos (18) /*!< QEI_T::CTL: CMPIEN Position */ +#define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) /*!< QEI_T::CTL: CMPIEN Mask */ + +#define QEI_CTL_IDXIEN_Pos (19) /*!< QEI_T::CTL: IDXIEN Position */ +#define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) /*!< QEI_T::CTL: IDXIEN Mask */ + +#define QEI_CTL_HOLDTMR0_Pos (20) /*!< QEI_T::CTL: HOLDTMR0 Position */ +#define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) /*!< QEI_T::CTL: HOLDTMR0 Mask */ + +#define QEI_CTL_HOLDTMR1_Pos (21) /*!< QEI_T::CTL: HOLDTMR1 Position */ +#define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) /*!< QEI_T::CTL: HOLDTMR1 Mask */ + +#define QEI_CTL_HOLDTMR2_Pos (22) /*!< QEI_T::CTL: HOLDTMR2 Position */ +#define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) /*!< QEI_T::CTL: HOLDTMR2 Mask */ + +#define QEI_CTL_HOLDTMR3_Pos (23) /*!< QEI_T::CTL: HOLDTMR3 Position */ +#define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) /*!< QEI_T::CTL: HOLDTMR3 Mask */ + +#define QEI_CTL_HOLDCNT_Pos (24) /*!< QEI_T::CTL: HOLDCNT Position */ +#define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) /*!< QEI_T::CTL: HOLDCNT Mask */ + +#define QEI_CTL_IDXLATEN_Pos (25) /*!< QEI_T::CTL: IDXLATEN Position */ +#define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) /*!< QEI_T::CTL: IDXLATEN Mask */ + +#define QEI_CTL_IDXRLDEN_Pos (27) /*!< QEI_T::CTL: IDXRLDEN Position */ +#define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) /*!< QEI_T::CTL: IDXRLDEN Mask */ + +#define QEI_CTL_CMPEN_Pos (28) /*!< QEI_T::CTL: CMPEN Position */ +#define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) /*!< QEI_T::CTL: CMPEN Mask */ + +#define QEI_CTL_QEIEN_Pos (29) /*!< QEI_T::CTL: QEIEN Position */ +#define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) /*!< QEI_T::CTL: QEIEN Mask */ + +#define QEI_STATUS_IDXF_Pos (0) /*!< QEI_T::STATUS: IDXF Position */ +#define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI_T::STATUS: IDXF Mask */ + +#define QEI_STATUS_CMPF_Pos (1) /*!< QEI_T::STATUS: CMPF Position */ +#define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI_T::STATUS: CMPF Mask */ + +#define QEI_STATUS_OVUNF_Pos (2) /*!< QEI_T::STATUS: OVUNF Position */ +#define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI_T::STATUS: OVUNF Mask */ + +#define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI_T::STATUS: DIRCHGF Position */ +#define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI_T::STATUS: DIRCHGF Mask */ + +#define QEI_STATUS_DIRF_Pos (8) /*!< QEI_T::STATUS: DIRF Position */ +#define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI_T::STATUS: DIRF Mask */ + +/**@}*/ /* QEI_CONST */ +/**@}*/ /* end of QEI register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __QEI_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/qspi_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/qspi_reg.h new file mode 100644 index 0000000000..1d9c801ba1 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/qspi_reg.h @@ -0,0 +1,622 @@ +/**************************************************************************//** + * @file qspi_reg.h + * @version V1.00 + * @brief QSPI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __QSPI_REG_H__ +#define __QSPI_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Quad Serial Peripheral Interface Controller -------------------------*/ +/** + @addtogroup QSPI Quad Serial Peripheral Interface Controller(QSPI) + Memory Mapped Structure for QSPI Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var QSPI_T::CTL + * Offset: 0x00 QSPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIEN |QSPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of QSPIx_CTL, QSPIx_CLKDIV, QSPIx_SSCTL and QSPIx_FIFOCTL registers, user shall clear the SPIEN (QSPIx_CTL[0]) and confirm the SPIENSTS (QSPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of QSPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of QSPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of QSPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of QSPI bus clock. + * | | |Note: In TX DTR mode, TXNEG equals to CLKPOL (QSPIx_CTL[3]). + * |[3] |CLKPOL |Clock Polarity + * | | |0 = QSPI bus clock is idle low. + * | | |1 = QSPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a Master transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of QSPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 .... 0.5 QSPICLK clock cycle. + * | | |SUSPITV = 0x1 .... 1.5 QSPICLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE .... 14.5 QSPICLK clock cycle. + * | | |SUSPITV = 0xF .... 15.5 QSPICLK clock cycle. + * | | |Note: In TX DTR mode, SUSPITV equals to 0x0. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |DWIDTH = 0x08 .... 8 bits. + * | | |DWIDTH = 0x09 .... 9 bits. + * | | |..... + * | | |DWIDTH = 0x1F .... 31 bits. + * | | |DWIDTH = 0x00 .... 32 bits. + * | | |Note: For QSPI0~QSPI3, this bit field will decide the depth of TX/RX FIFO configuration in QSPI mode + * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in QSPI0~QSPI3. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the QSPI TX register, is sent first to the QSPI data output pin, and the first bit received from the QSPI data input pin will be put in the LSB position of the RX register (bit 0 of QSPI_RX). + * |[14] |HALFDPX |QSPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for QSPI transfer + * | | |The bit field DATDIR (QSPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = QSPI operates in full-duplex transfer. + * | | |1 = QSPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, QSPI Master will generate QSPI bus clock continuously for receiving data bit from QSPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[16] |TWOBIT |2-bit Transfer Mode Enable Bit + * | | |0 = 2-Bit Transfer mode Disabled. + * | | |1 = 2-Bit Transfer mode Enabled. + * | | |Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd serial transmitted bit data is from the second FIFO buffer data + * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = QSPI unit transfer interrupt Disabled. + * | | |1 = QSPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = QSPI data is input direction. + * | | |1 = QSPI data is output direction. + * |[21] |DUALIOEN |Dual I/O Mode Enable Bit + * | | |0 = Dual I/O mode Disabled. + * | | |1 = Dual I/O mode Enabled. + * |[22] |QUADIOEN |Quad I/O Mode Enable Bit + * | | |0 = Quad I/O mode Disabled. + * | | |1 = Quad I/O mode Enabled. + * |[23] |TXDTREN |Transmit Double Transfer Rate Mode Enable Bit + * | | |0 = TX DTR mode Disabled. + * | | |1 = TX DTR mode Enabled. + * | | |Note: QSPI Master mode supports TXDTR (Transmit Double Transfer Rate) mode, and QSPI Slave mode does not support this mode. + * @var QSPI_T::CLKDIV + * Offset: 0x04 QSPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the QSPI bus clock of QSPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * | | |Note: The time interval must be larger than or equal 5 peripheral clock cycles between releasing QSPI IP software reset and setting this clock divider register. + * @var QSPI_T::SSCTL + * Offset: 0x08 QSPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = Set the QSPIx_SS line to inactive state. + * | | |1 = Set the QSPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the QSPIx_SS line at inactive state. + * | | |1 = QSPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of QSPIx_SS is specified in SSACTPOL (QSPIx_SSCTL[2]). + * | | |Note: Master mode only. + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (QSPIx_SS). + * | | |0 = The slave selection signal QSPIx_SS is active low. + * | | |1 = The slave selection signal QSPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (QSPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * | | |Note: Master mode only. + * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit + * | | |In Slave 3-wire mode, the QSPI controller can work with 3-wire interface including QSPI0_CLK, QSPI0_MISO and QSPI0_MOSI pins. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[5] |SLVTOIEN |Slave Mode Time-out Interrupt Enable Bit + * | | |0 = Slave mode time-out interrupt Disabled. + * | | |1 = Slave mode time-out interrupt Enabled. + * |[6] |SLVTORST |Slave Mode Time-out Reset Control + * | | |0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset. + * | | |1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * |[31:16] |SLVTOCNT |Slave Mode Time-out Period + * | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active + * | | |The clock source of the time-out counter is Slave peripheral clock + * | | |If the value is 0, it indicates the slave mode time-out function is disabled. + * @var QSPI_T::PDMACTL + * Offset: 0x0C QSPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In QSPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the QSPI controller. This bit will be automatically cleared to 0. + * @var QSPI_T::FIFOCTL + * Offset: 0x10 QSPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (QSPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in QSPI Slave mode, this bit can be used to make QSPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The QSPI data out is kept 0 if there is TX underflow event in Slave mode. + * | | |1 = The QSPI data out is kept 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. When TX underflow event occurs, QSPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through QSPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (QSPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error + * | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in QSPI Slave mode. + * | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in QSPI Slave mode + * | | |User can read SLVBENUM (QSPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened. + * | | |Note: Slave mode only. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * | | |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length. + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * | | |For QSPI0~QSPI3, the MSB of this bit field is only meaningful while QSPI mode 8~16 bits of data length. + * @var QSPI_T::STATUS + * Offset: 0x14 QSPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = QSPI controller is in idle state. + * | | |1 = QSPI controller is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. QSPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For QSPI Master mode, QSPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For QSPI Master mode, QSPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d. + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and there is serial clock input into the QSPI core logic when slave select is active. + * | | |e. + * | | |For QSPI Slave mode, the QSPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * | | |Note: By applications, this QSPI busy flag should be used with other status registers in QSPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF + * | | |Therefore the QSPI transfer done events of TX/RX operations can be obtained at correct timing point. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = QSPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (QSPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the QSPI slave select is in inactive status. + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag + * | | |When the slave select is active and the value of SLVTOCNT is not 0, if the bus clock is detected, the slave time-out counter in QSPI controller logic will be started + * | | |When the value of time-out counter is greater than or equal to the value of SLVTOCNT (QSPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted. + * | | |0 = Slave time-out is not active. + * | | |1 = Slave time-out is active. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurs. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurs. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 QSPI peripheral clock periods in Master mode or over 576 QSPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |SPIENSTS |QSPI Enable Status (Read Only) + * | | |0 = The QSPI controller is disabled. + * | | |1 = The QSPI controller is enabled. + * | | |Note: The QSPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the QSPI control logic is disabled, this bit indicates the real status of QSPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var QSPI_T::STATUS2 + * Offset: 0x18 QSPI Status2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX Data + * | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (QSPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in QSPI Slave mode + * | | |This status register will be fixed to 0x0 when SLVBERX (QSPIx_FIFOCTL[10]) is disabled. + * | | |Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (QSPIx_STATUS[6]). + * | | |Note 2: Slave mode only. + * @var QSPI_T::TX + * Offset: 0x20 QSPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (QSPIx_CTL[12:8]) in QSPI mode. + * | | |In QSPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted. + * | | |If DWIDTH is set to 0x00 , the QSPI controller will perform a 32-bit transfer. + * | | |Note: In Master mode, QSPI controller will start to transfer the QSPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var QSPI_T::RX + * Offset: 0x30 QSPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register (Read Only) + * | | |There are 8-level FIFO buffers in this controller. + * | | |The data receive register holds the data received from QSPI data input pin. + * | | |If the RXEMPTY (QSPIx_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. + */ + __IO uint32_t CTL; /*!< [0x0000] QSPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] QSPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] QSPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] QSPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] QSPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] QSPI Status Register */ + __I uint32_t STATUS2; /*!< [0x0018] QSPI Status2 Register */ + __I uint32_t RESERVE0[1]; + __O uint32_t TX; /*!< [0x0020] QSPI Data Transmit Register */ + __I uint32_t RESERVE1[3]; + __I uint32_t RX; /*!< [0x0030] QSPI Data Receive Register */ + +} QSPI_T; + +/** + @addtogroup QSPI_CONST QSPI Bit Field Definition + Constant Definitions for QSPI Controller + @{ +*/ + +#define QSPI_CTL_SPIEN_Pos (0) /*!< QSPI_T::CTL: SPIEN Position */ +#define QSPI_CTL_SPIEN_Msk (0x1ul << QSPI_CTL_SPIEN_Pos) /*!< QSPI_T::CTL: SPIEN Mask */ + +#define QSPI_CTL_RXNEG_Pos (1) /*!< QSPI_T::CTL: RXNEG Position */ +#define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) /*!< QSPI_T::CTL: RXNEG Mask */ + +#define QSPI_CTL_TXNEG_Pos (2) /*!< QSPI_T::CTL: TXNEG Position */ +#define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) /*!< QSPI_T::CTL: TXNEG Mask */ + +#define QSPI_CTL_CLKPOL_Pos (3) /*!< QSPI_T::CTL: CLKPOL Position */ +#define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) /*!< QSPI_T::CTL: CLKPOL Mask */ + +#define QSPI_CTL_SUSPITV_Pos (4) /*!< QSPI_T::CTL: SUSPITV Position */ +#define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) /*!< QSPI_T::CTL: SUSPITV Mask */ + +#define QSPI_CTL_DWIDTH_Pos (8) /*!< QSPI_T::CTL: DWIDTH Position */ +#define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) /*!< QSPI_T::CTL: DWIDTH Mask */ + +#define QSPI_CTL_LSB_Pos (13) /*!< QSPI_T::CTL: LSB Position */ +#define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) /*!< QSPI_T::CTL: LSB Mask */ + +#define QSPI_CTL_HALFDPX_Pos (14) /*!< QSPI_T::CTL: HALFDPX Position */ +#define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) /*!< QSPI_T::CTL: HALFDPX Mask */ + +#define QSPI_CTL_RXONLY_Pos (15) /*!< QSPI_T::CTL: RXONLY Position */ +#define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) /*!< QSPI_T::CTL: RXONLY Mask */ + +#define QSPI_CTL_TWOBIT_Pos (16) /*!< QSPI_T::CTL: TWOBIT Position */ +#define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) /*!< QSPI_T::CTL: TWOBIT Mask */ + +#define QSPI_CTL_UNITIEN_Pos (17) /*!< QSPI_T::CTL: UNITIEN Position */ +#define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) /*!< QSPI_T::CTL: UNITIEN Mask */ + +#define QSPI_CTL_SLAVE_Pos (18) /*!< QSPI_T::CTL: SLAVE Position */ +#define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) /*!< QSPI_T::CTL: SLAVE Mask */ + +#define QSPI_CTL_REORDER_Pos (19) /*!< QSPI_T::CTL: REORDER Position */ +#define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) /*!< QSPI_T::CTL: REORDER Mask */ + +#define QSPI_CTL_DATDIR_Pos (20) /*!< QSPI_T::CTL: DATDIR Position */ +#define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) /*!< QSPI_T::CTL: DATDIR Mask */ + +#define QSPI_CTL_DUALIOEN_Pos (21) /*!< QSPI_T::CTL: DUALIOEN Position */ +#define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) /*!< QSPI_T::CTL: DUALIOEN Mask */ + +#define QSPI_CTL_QUADIOEN_Pos (22) /*!< QSPI_T::CTL: QUADIOEN Position */ +#define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) /*!< QSPI_T::CTL: QUADIOEN Mask */ + +#define QSPI_CTL_TXDTREN_Pos (23) /*!< QSPI_T::CTL: TXDTREN Position */ +#define QSPI_CTL_TXDTREN_Msk (0x1ul << QSPI_CTL_TXDTREN_Pos) /*!< QSPI_T::CTL: TXDTREN Mask */ + +#define QSPI_CLKDIV_DIVIDER_Pos (0) /*!< QSPI_T::CLKDIV: DIVIDER Position */ +#define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) /*!< QSPI_T::CLKDIV: DIVIDER Mask */ + +#define QSPI_SSCTL_SS_Pos (0) /*!< QSPI_T::SSCTL: SS Position */ +#define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) /*!< QSPI_T::SSCTL: SS Mask */ + +#define QSPI_SSCTL_SSACTPOL_Pos (2) /*!< QSPI_T::SSCTL: SSACTPOL Position */ +#define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) /*!< QSPI_T::SSCTL: SSACTPOL Mask */ + +#define QSPI_SSCTL_AUTOSS_Pos (3) /*!< QSPI_T::SSCTL: AUTOSS Position */ +#define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) /*!< QSPI_T::SSCTL: AUTOSS Mask */ + +#define QSPI_SSCTL_SLV3WIRE_Pos (4) /*!< QSPI_T::SSCTL: SLV3WIRE Position */ +#define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) /*!< QSPI_T::SSCTL: SLV3WIRE Mask */ + +#define QSPI_SSCTL_SLVTOIEN_Pos (5) /*!< QSPI_T::SSCTL: SLVTOIEN Position */ +#define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) /*!< QSPI_T::SSCTL: SLVTOIEN Mask */ + +#define QSPI_SSCTL_SLVTORST_Pos (6) /*!< QSPI_T::SSCTL: SLVTORST Position */ +#define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) /*!< QSPI_T::SSCTL: SLVTORST Mask */ + +#define QSPI_SSCTL_SLVBEIEN_Pos (8) /*!< QSPI_T::SSCTL: SLVBEIEN Position */ +#define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) /*!< QSPI_T::SSCTL: SLVBEIEN Mask */ + +#define QSPI_SSCTL_SLVURIEN_Pos (9) /*!< QSPI_T::SSCTL: SLVURIEN Position */ +#define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) /*!< QSPI_T::SSCTL: SLVURIEN Mask */ + +#define QSPI_SSCTL_SSACTIEN_Pos (12) /*!< QSPI_T::SSCTL: SSACTIEN Position */ +#define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) /*!< QSPI_T::SSCTL: SSACTIEN Mask */ + +#define QSPI_SSCTL_SSINAIEN_Pos (13) /*!< QSPI_T::SSCTL: SSINAIEN Position */ +#define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) /*!< QSPI_T::SSCTL: SSINAIEN Mask */ + +#define QSPI_SSCTL_SLVTOCNT_Pos (16) /*!< QSPI_T::SSCTL: SLVTOCNT Position */ +#define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) /*!< QSPI_T::SSCTL: SLVTOCNT Mask */ + +#define QSPI_PDMACTL_TXPDMAEN_Pos (0) /*!< QSPI_T::PDMACTL: TXPDMAEN Position */ +#define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: TXPDMAEN Mask */ + +#define QSPI_PDMACTL_RXPDMAEN_Pos (1) /*!< QSPI_T::PDMACTL: RXPDMAEN Position */ +#define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) /*!< QSPI_T::PDMACTL: RXPDMAEN Mask */ + +#define QSPI_PDMACTL_PDMARST_Pos (2) /*!< QSPI_T::PDMACTL: PDMARST Position */ +#define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) /*!< QSPI_T::PDMACTL: PDMARST Mask */ + +#define QSPI_FIFOCTL_RXRST_Pos (0) /*!< QSPI_T::FIFOCTL: RXRST Position */ +#define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) /*!< QSPI_T::FIFOCTL: RXRST Mask */ + +#define QSPI_FIFOCTL_TXRST_Pos (1) /*!< QSPI_T::FIFOCTL: TXRST Position */ +#define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) /*!< QSPI_T::FIFOCTL: TXRST Mask */ + +#define QSPI_FIFOCTL_RXTHIEN_Pos (2) /*!< QSPI_T::FIFOCTL: RXTHIEN Position */ +#define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTHIEN Mask */ + +#define QSPI_FIFOCTL_TXTHIEN_Pos (3) /*!< QSPI_T::FIFOCTL: TXTHIEN Position */ +#define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) /*!< QSPI_T::FIFOCTL: TXTHIEN Mask */ + +#define QSPI_FIFOCTL_RXTOIEN_Pos (4) /*!< QSPI_T::FIFOCTL: RXTOIEN Position */ +#define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) /*!< QSPI_T::FIFOCTL: RXTOIEN Mask */ + +#define QSPI_FIFOCTL_RXOVIEN_Pos (5) /*!< QSPI_T::FIFOCTL: RXOVIEN Position */ +#define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) /*!< QSPI_T::FIFOCTL: RXOVIEN Mask */ + +#define QSPI_FIFOCTL_TXUFPOL_Pos (6) /*!< QSPI_T::FIFOCTL: TXUFPOL Position */ +#define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) /*!< QSPI_T::FIFOCTL: TXUFPOL Mask */ + +#define QSPI_FIFOCTL_TXUFIEN_Pos (7) /*!< QSPI_T::FIFOCTL: TXUFIEN Position */ +#define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) /*!< QSPI_T::FIFOCTL: TXUFIEN Mask */ + +#define QSPI_FIFOCTL_RXFBCLR_Pos (8) /*!< QSPI_T::FIFOCTL: RXFBCLR Position */ +#define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: RXFBCLR Mask */ + +#define QSPI_FIFOCTL_TXFBCLR_Pos (9) /*!< QSPI_T::FIFOCTL: TXFBCLR Position */ +#define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) /*!< QSPI_T::FIFOCTL: TXFBCLR Mask */ + +#define QSPI_FIFOCTL_SLVBERX_Pos (10) /*!< QSPI_T::FIFOCTL: SLVBERX Position */ +#define QSPI_FIFOCTL_SLVBERX_Msk (0x1ul << QSPI_FIFOCTL_SLVBERX_Pos) /*!< QSPI_T::FIFOCTL: SLVBERX Mask */ + +#define QSPI_FIFOCTL_RXTH_Pos (24) /*!< QSPI_T::FIFOCTL: RXTH Position */ +#define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) /*!< QSPI_T::FIFOCTL: RXTH Mask */ + +#define QSPI_FIFOCTL_TXTH_Pos (28) /*!< QSPI_T::FIFOCTL: TXTH Position */ +#define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) /*!< QSPI_T::FIFOCTL: TXTH Mask */ + +#define QSPI_STATUS_BUSY_Pos (0) /*!< QSPI_T::STATUS: BUSY Position */ +#define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) /*!< QSPI_T::STATUS: BUSY Mask */ + +#define QSPI_STATUS_UNITIF_Pos (1) /*!< QSPI_T::STATUS: UNITIF Position */ +#define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) /*!< QSPI_T::STATUS: UNITIF Mask */ + +#define QSPI_STATUS_SSACTIF_Pos (2) /*!< QSPI_T::STATUS: SSACTIF Position */ +#define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) /*!< QSPI_T::STATUS: SSACTIF Mask */ + +#define QSPI_STATUS_SSINAIF_Pos (3) /*!< QSPI_T::STATUS: SSINAIF Position */ +#define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) /*!< QSPI_T::STATUS: SSINAIF Mask */ + +#define QSPI_STATUS_SSLINE_Pos (4) /*!< QSPI_T::STATUS: SSLINE Position */ +#define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) /*!< QSPI_T::STATUS: SSLINE Mask */ + +#define QSPI_STATUS_SLVTOIF_Pos (5) /*!< QSPI_T::STATUS: SLVTOIF Position */ +#define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) /*!< QSPI_T::STATUS: SLVTOIF Mask */ + +#define QSPI_STATUS_SLVBEIF_Pos (6) /*!< QSPI_T::STATUS: SLVBEIF Position */ +#define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) /*!< QSPI_T::STATUS: SLVBEIF Mask */ + +#define QSPI_STATUS_SLVURIF_Pos (7) /*!< QSPI_T::STATUS: SLVURIF Position */ +#define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) /*!< QSPI_T::STATUS: SLVURIF Mask */ + +#define QSPI_STATUS_RXEMPTY_Pos (8) /*!< QSPI_T::STATUS: RXEMPTY Position */ +#define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) /*!< QSPI_T::STATUS: RXEMPTY Mask */ + +#define QSPI_STATUS_RXFULL_Pos (9) /*!< QSPI_T::STATUS: RXFULL Position */ +#define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) /*!< QSPI_T::STATUS: RXFULL Mask */ + +#define QSPI_STATUS_RXTHIF_Pos (10) /*!< QSPI_T::STATUS: RXTHIF Position */ +#define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) /*!< QSPI_T::STATUS: RXTHIF Mask */ + +#define QSPI_STATUS_RXOVIF_Pos (11) /*!< QSPI_T::STATUS: RXOVIF Position */ +#define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) /*!< QSPI_T::STATUS: RXOVIF Mask */ + +#define QSPI_STATUS_RXTOIF_Pos (12) /*!< QSPI_T::STATUS: RXTOIF Position */ +#define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) /*!< QSPI_T::STATUS: RXTOIF Mask */ + +#define QSPI_STATUS_SPIENSTS_Pos (15) /*!< QSPI_T::STATUS: SPIENSTS Position */ +#define QSPI_STATUS_SPIENSTS_Msk (0x1ul << QSPI_STATUS_SPIENSTS_Pos) /*!< QSPI_T::STATUS: SPIENSTS Mask */ + +#define QSPI_STATUS_TXEMPTY_Pos (16) /*!< QSPI_T::STATUS: TXEMPTY Position */ +#define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) /*!< QSPI_T::STATUS: TXEMPTY Mask */ + +#define QSPI_STATUS_TXFULL_Pos (17) /*!< QSPI_T::STATUS: TXFULL Position */ +#define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) /*!< QSPI_T::STATUS: TXFULL Mask */ + +#define QSPI_STATUS_TXTHIF_Pos (18) /*!< QSPI_T::STATUS: TXTHIF Position */ +#define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) /*!< QSPI_T::STATUS: TXTHIF Mask */ + +#define QSPI_STATUS_TXUFIF_Pos (19) /*!< QSPI_T::STATUS: TXUFIF Position */ +#define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) /*!< QSPI_T::STATUS: TXUFIF Mask */ + +#define QSPI_STATUS_TXRXRST_Pos (23) /*!< QSPI_T::STATUS: TXRXRST Position */ +#define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) /*!< QSPI_T::STATUS: TXRXRST Mask */ + +#define QSPI_STATUS_RXCNT_Pos (24) /*!< QSPI_T::STATUS: RXCNT Position */ +#define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) /*!< QSPI_T::STATUS: RXCNT Mask */ + +#define QSPI_STATUS_TXCNT_Pos (28) /*!< QSPI_T::STATUS: TXCNT Position */ +#define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) /*!< QSPI_T::STATUS: TXCNT Mask */ + +#define QSPI_STATUS2_SLVBENUM_Pos (24) /*!< QSPI_T::STATUS2: SLVBENUM Position */ +#define QSPI_STATUS2_SLVBENUM_Msk (0x3ful << QSPI_STATUS2_SLVBENUM_Pos) /*!< QSPI_T::STATUS2: SLVBENUM Mask */ + +#define QSPI_TX_TX_Pos (0) /*!< QSPI_T::TX: TX Position */ +#define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) /*!< QSPI_T::TX: TX Mask */ + +#define QSPI_RX_RX_Pos (0) /*!< QSPI_T::RX: RX Position */ +#define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) /*!< QSPI_T::RX: RX Mask */ + +/**@}*/ /* QSPI_CONST */ +/**@}*/ /* end of QSPI register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __QSPI_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/rtc_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/rtc_reg.h new file mode 100644 index 0000000000..19f60f9f27 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/rtc_reg.h @@ -0,0 +1,1302 @@ +/**************************************************************************//** + * @file rtc_reg.h + * @version V1.00 + * @brief RTC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_REG_H__ +#define __RTC_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Real Time Clock Controller -------------------------*/ +/** + @addtogroup RTC Real Time Clock Controller(RTC) + Memory Mapped Structure for RTC Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var RTC_T::INIT + * Offset: 0x00 RTC Initiation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INIT_ACTIVE|RTC Active Status (Read Only) + * | | |0 = RTC is at reset state. + * | | |1 = RTC is at normal active state. + * |[31:1] |INIT |RTC Initiation (Write Only) + * | | |When RTC block is powered on, RTC is at reset state. + * | | |User has to write a number (0xa5eb1357) to INIT to make RTC leave reset state. + * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently. + * | | |The INIT is a write-only field and read value will be always 0. + * @var RTC_T::FREQADJ + * Offset: 0x08 RTC Frequency Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |FRACTION |Fraction Part + * | | |Formula: FRACTION = (fraction part of detected value) X 64. + * | | |Note: Digit in FCR must be expressed as hexadecimal number. + * |[12:8] |INTEGER |Integer Part + * | | |00000 = Integer part of detected value is 32752. + * | | |00001 = Integer part of detected value is 32753. + * | | |00010 = Integer part of detected value is 32754. + * | | |00011 = Integer part of detected value is 32755. + * | | |00100 = Integer part of detected value is 32756. + * | | |00101 = Integer part of detected value is 32757. + * | | |00110 = Integer part of detected value is 32758. + * | | |00111 = Integer part of detected value is 32759. + * | | |01000 = Integer part of detected value is 32760. + * | | |01001 = Integer part of detected value is 32761. + * | | |01010 = Integer part of detected value is 32762. + * | | |01011 = Integer part of detected value is 32763. + * | | |01100 = Integer part of detected value is 32764. + * | | |01101 = Integer part of detected value is 32765. + * | | |01110 = Integer part of detected value is 32766. + * | | |01111 = Integer part of detected value is 32767. + * | | |10000 = Integer part of detected value is 32768. + * | | |10001 = Integer part of detected value is 32769. + * | | |10010 = Integer part of detected value is 32770. + * | | |10011 = Integer part of detected value is 32771. + * | | |10100 = Integer part of detected value is 32772. + * | | |10101 = Integer part of detected value is 32773. + * | | |10110 = Integer part of detected value is 32774. + * | | |10111 = Integer part of detected value is 32775. + * | | |11000 = Integer part of detected value is 32776. + * | | |11001 = Integer part of detected value is 32777. + * | | |11010 = Integer part of detected value is 32778. + * | | |11011 = Integer part of detected value is 32779. + * | | |11100 = Integer part of detected value is 32780. + * | | |11101 = Integer part of detected value is 32781. + * | | |11110 = Integer part of detected value is 32782. + * | | |11111 = Integer part of detected value is 32783. + * |[31] |FCRBUSY |Frequency Compensation Register Write Operation Busy (Read Only) + * | | |0 = The new register write operation is acceptable. + * | | |1 = The last write operation is in progress and new register write operation prohibited. + * | | |Note: This bit is only used when DCOMPEN(RTC_CLKFMT[16]) is enabled. + * @var RTC_T::TIME + * Offset: 0x0C RTC Time Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit (0~5) + * |[11:8] |MIN |1-Min Time Digit (0~9) + * |[14:12] |TENMIN |10-Min Time Digit (0~5) + * |[19:16] |HR |1-Hour Time Digit (0~9) + * |[21:20] |TENHR |10-Hour Time Digit (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) + * @var RTC_T::CAL + * Offset: 0x10 RTC Calendar Loading Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit (0~3) + * |[11:8] |MON |1-Month Calendar Digit (0~9) + * |[12] |TENMON |10-Month Calendar Digit (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit (0~9) + * @var RTC_T::CLKFMT + * Offset: 0x14 RTC Time Scale Selection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |24HEN |24-hour / 12-hour Time Scale Selection + * | | |The RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale. + * | | |0 = 12-hour time scale with AM and PM indication selected. + * | | |1 = 24-hour time scale selected. + * |[16] |DCOMPEN |Dynamic Compensation Enable Bit + * | | |0 = Dynamic Compensation Disabled. + * | | |1 = Dynamic Compensation Enabled. + * @var RTC_T::WEEKDAY + * Offset: 0x18 RTC Day of the Week Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |WEEKDAY |Day of the Week Register + * | | |000 = Sunday. + * | | |001 = Monday. + * | | |010 = Tuesday. + * | | |011 = Wednesday. + * | | |100 = Thursday. + * | | |101 = Friday. + * | | |110 = Saturday. + * | | |111 = Reserved. + * @var RTC_T::TALM + * Offset: 0x1C RTC Time Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of Alarm Setting (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5) + * |[11:8] |MIN |1-Min Time Digit of Alarm Setting (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of Alarm Setting (0~5) + * |[19:16] |HR |1-Hour Time Digit of Alarm Setting (0~9) + * |[21:20] |TENHR |10-Hour Time Digit of Alarm Setting (0~2) + * | | |When RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication (If RTC_TIME[21] is 1, it indicates PM time message.) + * @var RTC_T::CALM + * Offset: 0x20 RTC Calendar Alarm Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of Alarm Setting (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3) + * |[11:8] |MON |1-Month Calendar Digit of Alarm Setting (0~9) + * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::LEAPYEAR + * Offset: 0x24 RTC Leap Year Indicator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LEAPYEAR |Leap Year Indication (Read Only) + * | | |0 = This year is not a leap year. + * | | |1 = This year is leap year. + * @var RTC_T::INTEN + * Offset: 0x28 RTC Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIEN |Alarm Interrupt Enable Bit + * | | |Set ALMIEN to 1 can also enable chip wake-up function when RTC alarm interrupt event is generated. + * | | |0 = RTC Alarm interrupt Disabled. + * | | |1 = RTC Alarm interrupt Enabled. + * |[1] |TICKIEN |Time Tick Interrupt Enable Bit + * | | |Set TICKIEN to 1 can also enable chip wake-up function when RTC tick interrupt event is generated. + * | | |0 = RTC Time Tick interrupt Disabled. + * | | |1 = RTC Time Tick interrupt Enabled. + * |[8] |TAMP0IEN |Tamper 0 Interrupt Enable Bit + * | | |Set TAMP0IEN to 1 can also enable chip wake-up function when tamper 0 interrupt event is generated. + * | | |0 = Tamper 0 interrupt Disabled. + * | | |1 = Tamper 0 interrupt Enabled. + * |[9] |TAMP1IEN |Tamper 1 or Pair 0 Interrupt Enable Bit + * | | |Set TAMP1IEN to 1 can also enable chip wake-up function when tamper 1 interrupt event is generated. + * | | |0 = Tamper 1 or Pair 0 interrupt Disabled. + * | | |1 = Tamper 1 or Pair 0 interrupt Enabled. + * |[10] |TAMP2IEN |Tamper 2 Interrupt Enable Bit + * | | |Set TAMP2IEN to 1 can also enable chip wake-up function when tamper 2 interrupt event is generated. + * | | |0 = Tamper 2 interrupt Disabled. + * | | |1 = Tamper 2 interrupt Enabled. + * |[11] |TAMP3IEN |Tamper 3 or Pair 1 Interrupt Enable Bit + * | | |Set TAMP3IEN to 1 can also enable chip wake-up function when tamper 3 interrupt event is generated. + * | | |0 = Tamper 3 or Pair 1 interrupt Disabled. + * | | |1 = Tamper 3 or Pair 1 interrupt Enabled. + * |[12] |TAMP4IEN |Tamper 4 Interrupt Enable Bit + * | | |Set TAMP4IEN to 1 can also enable chip wake-up function when tamper 4 interrupt event is generated. + * | | |0 = Tamper 4 interrupt Disabled. + * | | |1 = Tamper 4 interrupt Enabled. + * |[13] |TAMP5IEN |Tamper 5 or Pair 2 Interrupt Enable Bit + * | | |Set TAMP5IEN to 1 can also enable chip wake-up function when tamper 5 interrupt event is generated. + * | | |0 = Tamper 5 or Pair 2 interrupt Disabled. + * | | |1 = Tamper 5 or Pair 2 interrupt Enabled. + * |[24] |CLKFIEN |LXT Clock Frequency Monitor Fail Interrupt Enable Bit + * | | |0 = LXT Frequency Fail interrupt Disabled. + * | | |1 = LXT Frequency Fail interrupt Enabled. + * |[25] |CLKSTIEN |LXT Clock Frequency Monitor Stop Interrupt Enable Bit + * | | |0 = LXT Frequency Stop interrupt Disabled. + * | | |1 = LXT Frequency Stop interrupt Enabled. + * @var RTC_T::INTSTS + * Offset: 0x2C RTC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ALMIF |RTC Alarm Interrupt Flag + * | | |0 = Alarm condition is not matched. + * | | |1 = Alarm condition is matched. + * | | |Note: Write 1 to clear this bit. + * |[1] |TICKIF |RTC Time Tick Interrupt Flag + * | | |0 = Tick condition does not occur. + * | | |1 = Tick condition occur. + * | | |Note: Write 1 to clear this bit. + * |[8] |TAMP0IF |Tamper 0 Interrupt Flag + * | | |This bit is set when TAMP0_PIN detected level non-equal TAMP0LV (RTC_TAMPCTL[9]). + * | | |0 = No Tamper 0 interrupt flag is generated. + * | | |1 = Tamper 0 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[9] |TAMP1IF |Tamper 1 or Pair 0 Interrupt Flag + * | | |This bit is set when TAMP1_PIN detected level non-equal TAMP1LV (RTC_TAMPCTL[13]) or TAMP0_PIN and TAMP1_PIN disconnected during DYNPR0EN (RTC_TAMPCTL[15]) is activated. + * | | |0 = No Tamper 1 or Pair 0 interrupt flag is generated. + * | | |1 = Tamper 1 or Pair 0 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[10] |TAMP2IF |Tamper 2 Interrupt Flag + * | | |This bit is set when TAMP2_PIN detected level non-equal TAMP2LV (RTC_TAMPCTL[17]). + * | | |0 = No Tamper 2 interrupt flag is generated. + * | | |1 = Tamper 2 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[11] |TAMP3IF |Tamper 3 or Pair 1 Interrupt Flag + * | | |This bit is set when TAMP3_PIN detected level non-equal TAMP3LV (RTC_TAMPCTL[21]) or TAMP2_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) is activated or + * | | |TAMP0_PIN and TAMP3_PIN disconnected during DYNPR1EN (RTC_TAMPCTL[23]) and DYN1ISS (RTC_TAMPCTL[0]) are activated. + * | | |0 = No Tamper 3 or Pair 1 interrupt flag is generated. + * | | |1 = Tamper 3 or Pair 1 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[12] |TAMP4IF |Tamper 4 Interrupt Flag + * | | |This bit is set when TAMP4_PIN detected level non-equal TAMP4LV (RTC_TAMPCTL[25]). + * | | |0 = No Tamper 4 interrupt flag is generated. + * | | |1 = Tamper 4 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[13] |TAMP5IF |Tamper 5 or Pair 2 Interrupt Flag + * | | |This bit is set when TAMP5_PIN detected level non-equal TAMP5LV (RTC_TAMPCTL[29]) or TAMP4_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) is activated or + * | | |TAMP0_PIN and TAMP5_PIN disconnected during DYNPR2EN (RTC_TAMPCTL[31]) and DYN2ISS (RTC_TAMPCTL[1]) are activated. + * | | |0 = No Tamper 5 or Pair 2 interrupt flag is generated. + * | | |1 = Tamper 5 or Pair 2 interrupt flag is generated. + * | | |Note1: Write 1 to clear this bit. + * | | |Note2: This interrupt flag will be generated again when Tamper setting condition is not restoration. + * | | |Note3: Need to clear all TAMPxIF, after that, new RTC_TAMPTIME and RTC_TAMPCAL values are loaded while a tamper event occurred. + * |[24] |CLKFIF |LXT Clock Frequency Monitor Fail Interrupt Flag + * | | |0 = LXT frequency is normal. + * | | |1 = LXT frequency is abnormal. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. + * |[25] |CLKSTIF |LXT Clock Frequency Monitor Stop Interrupt Flag + * | | |0 = LXT frequency is normal. + * | | |1 = LXT frequency is almost stop. + * | | |Note1: Write 1 to clear the bit to 0. + * | | |Note2: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. + * @var RTC_T::TICK + * Offset: 0x30 RTC Time Tick Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TICK |Time Tick Register + * | | |These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. + * | | |000 = Time tick is 1 second. + * | | |001 = Time tick is 1/2 second. + * | | |010 = Time tick is 1/4 second. + * | | |011 = Time tick is 1/8 second. + * | | |100 = Time tick is 1/16 second. + * | | |101 = Time tick is 1/32 second. + * | | |110 = Time tick is 1/64 second. + * | | |111 = Time tick is 1/128 second. + * @var RTC_T::TAMSK + * Offset: 0x34 RTC Time Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9) + * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5) + * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9) + * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5) + * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9) + * | | |Note: MHR function is only for 24-hour time scale mode. + * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2) + * | | |Note: MTENHR function is only for 24-hour time scale mode. + * @var RTC_T::CAMSK + * Offset: 0x38 RTC Calendar Alarm Mask Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9) + * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3) + * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9) + * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1) + * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9) + * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9) + * @var RTC_T::SPRCTL + * Offset: 0x3C RTC Spare Functional Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |SPRRWEN |Spare Register Enable Bit + * | | |0 = Spare register Disabled. + * | | |1 = Spare register Enabled. + * | | |Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed. + * |[5] |SPRCSTS |SPR Clear Flag + * | | |This bit indicates if the RTC_SPR0 ~ RTC_SPR19 content is cleared when specify tamper event is detected. + * | | |0 = Spare register content is not cleared. + * | | |1 = Spare register content is cleared. + * | | |Note 1: Writes 1 to clear this bit. + * | | |Note 2: This bit keep 1 when RTC_INTSTS[13:8] or RTC_INTSTS[25:24] are not equal zero. + * |[16] |LXTFCLR |LXT Clock Fail/Stop to Clear Spare Enable Bit + * | | |0 = LXT Fail/Stop to clear Spare register content Disabled. + * | | |1 = LXT Fail/Stop to clear Spare register content Enabled. + * @var RTC_T::SPR[20] + * Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SPARE |Spare Register + * | | |This field is used to store back-up information defined by user. + * | | |This field will be cleared by hardware automatically in the following conditions, a tamper pin event is detected, + * | | |LXT clock fail/stop event occurs if LXTFCLR(RTC_SPRCTL[16]) is 1, or after Flash mass operation. + * @var RTC_T::LXTCTL + * Offset: 0x100 RTC 32.768 kHz Oscillator Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LIRC32KEN |Enable LIRC32K Source + * | | |0 = LIRC32K Disabled. + * | | |1 = LIRC32K Enabled. + * |[3:1] |GAIN |Oscillator Gain Option + * | | |User can select oscillator gain according to crystal external loading and operating temperature range. + * | | |The larger gain value corresponding to stronger driving capability and higher power consumption. + * | | |000 = L0 mode. + * | | |001 = L1 mode. + * | | |010 = L2 mode. + * | | |011 = L3 mode. + * | | |100 = L4 mode. + * | | |101 = L5 mode. + * | | |110 = L6 mode. + * | | |111 = L7 mode (Default). + * |[6] |C32KSEL |Clock 32K Source Selection + * | | |0 = Clock source from external low speed crystal oscillator (LXT). + * | | |1 = Clock source from internal low speed RC 32K oscillator (LIRC32K). + * |[7] |RTCCKSEL |RTC Clock Source Selection + * | | |0 = Clock source from external low speed crystal oscillator (LXT) or internal low speed RC 32K oscillator (LIRC32K) depended on C32KSEL value. + * | | |1 = Clock source from internal low speed RC oscillator (LIRC). + * |[8] |IOCTLSEL |IO Pin Backup Control Selection + * | | |When low speed 32 kHz oscillator is disabled or TAMPxEN is disabled, + * | | |PF.4 pin (X32KO pin), PF.5 pin (X32KI pin) or PF.6~11 pin (TAMPERx pin) can be used as GPIO function. + * | | |User can program IOCTLSEL to decide PF.4~11 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_GPIOCTL0/1 control register. + * | | |0 = PF.4~11 pin I/O function is controlled by GPIO module. + * | | |1 = PF.4~11 pin I/O function is controlled by VBAT power domain. + * | | |Note: IOCTLSEL will automatically be set by hardware to 1 when system power is off and any writable RTC registers has been written at RTCCKEN(CLK_APBCLK0[1]) enabled. + * @var RTC_T::GPIOCTL0 + * Offset: 0x104 RTC GPIO Control 0 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE0 |IO Operation Mode + * | | |00 = PF.4 is input only mode. + * | | |01 = PF.4 is output push pull mode. + * | | |10 = PF.4 is open drain mode. + * | | |11 = PF.4 is quasi-bidirectional mod. + * |[2] |DOUT0 |IO Output Data + * | | |0 = PF.4 output low. + * | | |1 = PF.4 output high. + * |[3] |DINOFF0 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.4 digital input path Enabled. + * | | |1 = PF.4 digital input path Disabled (digital input tied to low). + * |[5:4] |PUSEL0 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.4 I/O pull-up or pull-down. + * | | |00 = PF.4 pull-up and pull-down Disabled. + * | | |01 = PF.4 pull-up Enabled. + * | | |10 = PF.4 pull-down Enabled. + * | | |11 = PF.4 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE0 is set as input tri-state and open-drain mode. + * |[9:8] |OPMODE1 |IO Operation Mode + * | | |00 = PF.5 is input only mode. + * | | |01 = PF.5 is output push pull mode. + * | | |10 = PF.5 is open drain mode. + * | | |11 = PF.5 is quasi-bidirectional mod. + * |[10] |DOUT1 |IO Output Data + * | | |0 = PF.5 output low. + * | | |1 = PF.5 output high. + * |[11 |DINOFF1 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.5 digital input path Enabled. + * | | |1 = PF.5 digital input path Disabled (digital input tied to low). + * |[13:12] |PUSEL1 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.5 I/O pull-up or pull-down. + * | | |00 = PF.5 pull-up and pull-down Disabled. + * | | |01 = PF.5 pull-up Enabled. + * | | |10 = PF.5 pull-down Enabled. + * | | |11 = PF.5 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE1 is set as input tri-state and open-drain mode. + * |[17:16] |OPMODE2 |IO Operation Mode + * | | |00 = PF.6 is input only mode. + * | | |01 = PF.6 is output push pull mode. + * | | |10 = PF.6 is open drain mode. + * | | |11 = PF.6 is quasi-bidirectional mod. + * |[18] |DOUT2 |IO Output Data + * | | |0 = PF.6 output low. + * | | |1 = PF.6 output high. + * |[19 |DINOFF2 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.6 digital input path Enabled. + * | | |1 = PF.6 digital input path Disabled (digital input tied to low). + * |[21:20] |PUSEL2 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.6 I/O pull-up or pull-down. + * | | |00 = PF.6 pull-up and pull-down Disabled. + * | | |01 = PF.6 pull-up Enabled. + * | | |10 = PF.6 pull-down Enabled. + * | | |11 = PF.6 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE2 is set as input tri-state and open-drain mode. + * |[25:24] |OPMODE3 |IO Operation Mode + * | | |00 = PF.7 is input only mode. + * | | |01 = PF.7 is output push pull mode. + * | | |10 = PF.7 is open drain mode. + * | | |11 = PF.7 is quasi-bidirectional mod. + * |[26] |DOUT3 |IO Output Data + * | | |0 = PF.7 output low. + * | | |1 = PF.7 output high. + * |[27 |DINOFF3 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.7 digital input path Enabled. + * | | |1 = PF.7 digital input path Disabled (digital input tied to low). + * |[29:28] |PUSEL3 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.7 I/O pull-up or pull-down. + * | | |00 = PF.7 pull-up and pull-down Disabled. + * | | |01 = PF.7 pull-up Enabled. + * | | |10 = PF.7 pull-down Enabled. + * | | |11 = PF.7 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE3 is set as input tri-state and open-drain mode. + * @var RTC_T::GPIOCTL1 + * Offset: 0x108 RTC GPIO Control 1 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |OPMODE4 |IO Operation Mode + * | | |00 = PF.8 is input only mode. + * | | |01 = PF.8 is output push pull mode. + * | | |10 = PF.8 is open drain mode. + * | | |11 = PF.8 is quasi-bidirectional mod. + * |[2] |DOUT4 |IO Output Data + * | | |0 = PF.8 output low. + * | | |1 = PF.8 output high. + * |[3] |DINOFF4 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.8 digital input path Enabled. + * | | |1 = PF.8 digital input path Disabled (digital input tied to low). + * |[5:4] |PUSEL4 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.8 I/O pull-up or pull-down. + * | | |00 = PF.8 pull-up and pull-down Disabled. + * | | |01 = PF.8 pull-up Enabled. + * | | |10 = PF.8 pull-down Enabled. + * | | |11 = PF.8 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE4 is set as input tri-state and open-drain mode. + * |[9:8] |OPMODE5 |IO Operation Mode + * | | |00 = PF.9 is input only mode. + * | | |01 = PF.9 is output push pull mode. + * | | |10 = PF.9 is open drain mode. + * | | |11 = PF.9 is quasi-bidirectional mod. + * |[10] |DOUT5 |IO Output Data + * | | |0 = PF.9 output low. + * | | |1 = PF.9 output high. + * |[11 |DINOFF5 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.9 digital input path Enabled. + * | | |1 = PF.9 digital input path Disabled (digital input tied to low). + * |[13:12] |PUSEL5 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.9 I/O pull-up or pull-down. + * | | |00 = PF.9 pull-up and pull-down Disabled. + * | | |01 = PF.9 pull-up Enabled. + * | | |10 = PF.9 pull-down Enabled. + * | | |11 = PF.9 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE5 is set as input tri-state and open-drain mode. + * |[17:16] |OPMODE6 |IO Operation Mode + * | | |00 = PF.10 is input only mode. + * | | |01 = PF.10 is output push pull mode. + * | | |10 = PF.10 is open drain mode. + * | | |11 = PF.10 is quasi-bidirectional mod. + * |[18] |DOUT6 |IO Output Data + * | | |0 = PF.10 output low. + * | | |1 = PF.10 output high. + * |[19 |DINOFF6 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.10 digital input path Enabled. + * | | |1 = PF.10 digital input path Disabled (digital input tied to low). + * |[21:20] |PUSEL6 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.10 I/O pull-up or pull-down. + * | | |00 = PF.10 pull-up and pull-down Disabled. + * | | |01 = PF.10 pull-up Enabled. + * | | |10 = PF.10 pull-down Enabled. + * | | |11 = PF.10 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE6 is set as input tri-state and open-drain mode. + * |[25:24] |OPMODE7 |IO Operation Mode + * | | |00 = PF.11 is input only mode. + * | | |01 = PF.11 is output push pull mode. + * | | |10 = PF.11 is open drain mode. + * | | |11 = PF.11 is quasi-bidirectional mod. + * |[26] |DOUT7 |IO Output Data + * | | |0 = PF.11 output low. + * | | |1 = PF.11 output high. + * |[27 |DINOFF7 |IO Pin Digital Input Path Disable Bit + * | | |0 = PF.11 digital input path Enabled. + * | | |1 = PF.11 digital input path Disabled (digital input tied to low). + * |[29:28] |PUSEL7 |IO Pull-up and Pull-down Enable Bits + * | | |Determine PF.11 I/O pull-up or pull-down. + * | | |00 = PF.11 pull-up and pull-down Disabled. + * | | |01 = PF.11 pull-up Enabled. + * | | |10 = PF.11 pull-down Enabled. + * | | |11 = PF.11 pull-up and pull-down Disabled. + * | | |Note: Basically, the pull-up control and pull-down control has following behavior limitation. + * | | |The independent pull-up/pull-down control register is only valid when OPMODE7 is set as input tri-state and open-drain mode. + * @var RTC_T::DSTCTL + * Offset: 0x110 RTC Daylight Saving Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADDHR |Add 1 Hour + * | | |0 = No effect. + * | | |1 = Indicates RTC hour digit has been added one hour for summer time change. + * |[1] |SUBHR |Subtract 1 Hour + * | | |0 = No effect. + * | | |1 = Indicates RTC hour digit has been subtracted one hour for winter time change. + * |[2] |DSBAK |Daylight Saving Back + * | | |0 = Daylight Saving Change is not performed. + * | | |1 = Daylight Saving Change is performed. + * @var RTC_T::TAMPCTL + * Offset: 0x120 RTC Tamper Pin Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select + * | | |This bit determine Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 2. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit is effective only when DYNPR1EN (RTC_TAMPCTL[23]) and DYNPR0EN (RTC_TAMPCTL[15]) are set. + * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select + * | | |This bit determine Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 4. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit is effective only when DYNPR2EN (RTC_TAMPCTL[31]) and DYNPR0EN (RTC_TAMPCTL[15]) are set. + * |[3] |DYNSRC |Dynamic Reference Pattern + * | | |This fields determine the new reference pattern when current pattern run out in dynamic pair mode. + * | | |0 = The new reference pattern is generated by random number generator when the reference pattern run out. + * | | |1 = The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out. + * | | |Note: After this bit is modified, the SEEDRLD (RTC_TAMPCTL[4]) should be set. + * |[4] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |Setting this bit, the tamper configuration will be reload. + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * | | |Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. + * | | |Note 2: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[7:5] |DYNRATE |Dynamic Change Rate + * | | |This item is choice the dynamic tamper output change rate. + * | | |000 = 2^10 * RTC_CLK. + * | | |001 = 2^11 * RTC_CLK. + * | | |010 = 2^12 * RTC_CLK. + * | | |011 = 2^13 * RTC_CLK. + * | | |100 = 2^14 * RTC_CLK. + * | | |101 = 2^15 * RTC_CLK. + * | | |110 = 2^16 * RTC_CLK. + * | | |111 = 2^17 * RTC_CLK. + * | | |Note: After revising this field, set SEEDRLD (RTC_TAMPCTL[4]) can reload change rate immediately. + * |[8] |TAMP0EN |Tamper0 Detect Enable Bit + * | | |0 = Tamper 0 detect Disabled. + * | | |1 = Tamper 0 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[9] |TAMP0LV |Tamper 0 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit + * | | |0 = Tamper 0 de-bounce Disabled. + * | | |1 = Tamper 0 de-bounce Enabled. + * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit + * | | |0 = Tamper 1 detect Disabled. + * | | |1 = Tamper 1 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[13] |TAMP1LV |Tamper 1 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit + * | | |0 = Tamper 1 de-bounce Disabled. + * | | |1 = Tamper 1 de-bounce Enabled. + * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit + * | | |0 = Tamper 2 detect Disabled. + * | | |1 = Tamper 2 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[17] |TAMP2LV |Tamper 2 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit + * | | |0 = Tamper 2 de-bounce Disabled. + * | | |1 = Tamper 2 de-bounce Enabled. + * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit + * | | |0 = Tamper 3 detect Disabled. + * | | |1 = Tamper 3 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[21] |TAMP3LV |Tamper 3 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit + * | | |0 = Tamper 3 de-bounce Disabled. + * | | |1 = Tamper 3 de-bounce Enabled. + * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[24] |TAMP4EN |Tamper4 Detect Enable Bit + * | | |0 = Tamper 4 detect Disabled. + * | | |1 = Tamper 4 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[25] |TAMP4LV |Tamper 4 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit + * | | |0 = Tamper 4 de-bounce Disabled. + * | | |1 = Tamper 4 de-bounce Enabled. + * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit + * | | |0 = Tamper 5 detect Disabled. + * | | |1 = Tamper 5 detect Enabled. + * | | |Note1: The reference is RTC clock. Tamper detector need sync 2 ~ 3 RTC clock. + * |[29] |TAMP5LV |Tamper 5 Level + * | | |This bit depend on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit + * | | |0 = Tamper 5 de-bounce Disabled. + * | | |1 = Tamper 5 de-bounce Enabled. + * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * @var RTC_T::TAMPSEED + * Offset: 0x128 RTC Tamper Dynamic Seed Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed Value + * @var RTC_T::TAMPTIME + * Offset: 0x130 RTC Tamper Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |SEC |1-Sec Time Digit of TAMPER Time (0~9) + * |[6:4] |TENSEC |10-Sec Time Digit of TAMPER Time (0~5) + * |[11:8] |MIN |1-Min Time Digit of TAMPER Time (0~9) + * |[14:12] |TENMIN |10-Min Time Digit of TAMPER Time (0~5) + * |[19:16] |HR |1-Hour Time Digit of TAMPER Time (0~9) + * |[21:20] |TENHR |10-Hour Time Digit of TAMPER Time (0~2) + * | | |Note: 24-hour time scale only. + * @var RTC_T::TAMPCAL + * Offset: 0x134 RTC Tamper Calendar Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |DAY |1-Day Calendar Digit of TAMPER Calendar (0~9) + * |[5:4] |TENDAY |10-Day Calendar Digit of TAMPER Calendar (0~3) + * |[11:8] |MON |1-Month Calendar Digit of TAMPER Calendar (0~9) + * |[12] |TENMON |10-Month Calendar Digit of TAMPER Calendar (0~1) + * |[19:16] |YEAR |1-Year Calendar Digit of TAMPER Calendar (0~9) + * |[23:20] |TENYEAR |10-Year Calendar Digit of TAMPER Calendar (0~9) + * @var RTC_T::CLKDCTL + * Offset: 0x140 RTC Clock Fail Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LXTFDEN |LXT Clock Fail/Stop Detector Enable Bit + * | | |0 = LXT clock Fail/Stop detector Disabled. + * | | |1 = LXT clock Fail/Stop detector Enabled. + * | | |Note: LXT detector will automatic disable when Fail/Stop Flag rise, resume after Fail/Stop Flag clear. + * |[1] |LXTFSW |LXT Clock Fail Detector Switch LIRC32K Enable Bit + * | | |0 = LXT clock Fail switch LIRC32K Disabled. + * | | |1 = LXT clock Fail detector rise, RTC clock source switch from LIRC32K. + * | | |If LXT clock fail detector flag CLKFIF (RTC_INTSTS[24]) is generated, RTC clock source will switch to LIRC32K automatically. + * |[2] |LXTSTSW |LXT Clock Stop Detector Switch LIRC32K Enable Bit + * | | |0 = LXT clock Stop switch LIRC32K Disabled. + * | | |1 = LXT clock Stop detector rise, RTC clock source switch from LIRC32K. + * | | |If LXT clock stop detector flag CLKSTIF (RTC_INTSTS[25]) is generated, RTC clock source will switch to LIRC32K automatically + * |[16] |SWLIRCF |LXT Clock Detector Fail/Stop Switch LIRC32K Flag (Read Only) + * | | |0 = Indicate RTC clock source from LXT. + * | | |1 = Indicate RTC clock source from LIRC32K. + * |[17] |LXTSLOWF |LXT Slower Than LIRC32K Flag (Read Only) + * | | |0 = LXT frequency faster than LIRC32K. + * | | |1 = LXT frequency is slowly. + * | | |Note: LXTSLOWF is vaild during CLKSTIF (RTC_INTSTS[25]) or CLKFIF (RTC_INTSTS[24]) rising. + * @var RTC_T::CDBR + * Offset: 0x144 RTC Clock Frequency Detector Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |STOPBD |LXT Clock Stop Frequency Detector Stop Boundary + * | | |These bits define the stop value of frequency monitor window. + * | | |When LXT frequency monitor counter lower than STOPBD, the LXT frequency detect Stop interrupt flag will set to 1. + * | | |Note: The boundary is defined as the maximum value of LXT among 256 LIRC32K clock time. + * |[23:16] |FAILBD |LXT Clock Frequency Detector Fail Boundary + * | | |These bits define the fail value of frequency monitor window. + * | | |When LXT frequency monitor counter lower than FAILBD, the LXT frequency detect fail interrupt flag will set to 1. + * | | |Note: The boundary is defined as the maximum value of LXT among 256 LIRC32K clock time. + */ + __IO uint32_t INIT; /*!< [0x0000] RTC Initiation Register */ + __I uint32_t RESERVE0[1]; /* 0x4 */ + __IO uint32_t FREQADJ; /*!< [0x0008] RTC Frequency Compensation Register */ + __IO uint32_t TIME; /*!< [0x000c] RTC Time Loading Register */ + __IO uint32_t CAL; /*!< [0x0010] RTC Calendar Loading Register */ + __IO uint32_t CLKFMT; /*!< [0x0014] RTC Time Scale Selection Register */ + __IO uint32_t WEEKDAY; /*!< [0x0018] RTC Day of the Week Register */ + __IO uint32_t TALM; /*!< [0x001c] RTC Time Alarm Register */ + __IO uint32_t CALM; /*!< [0x0020] RTC Calendar Alarm Register */ + __I uint32_t LEAPYEAR; /*!< [0x0024] RTC Leap Year Indicator Register */ + __IO uint32_t INTEN; /*!< [0x0028] RTC Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x002c] RTC Interrupt Status Register */ + __IO uint32_t TICK; /*!< [0x0030] RTC Time Tick Register */ + __IO uint32_t TAMSK; /*!< [0x0034] RTC Time Alarm Mask Register */ + __IO uint32_t CAMSK; /*!< [0x0038] RTC Calendar Alarm Mask Register */ + __IO uint32_t SPRCTL; /*!< [0x003c] RTC Spare Functional Control Register */ + __IO uint32_t SPR[20]; /*!< [0x0040] ~ [0x008C] RTC Spare Register 0 ~ 19 */ + __I uint32_t RESERVE1[28]; /* 0x90 ~ 0xfc */ + __IO uint32_t LXTCTL; /*!< [0x0100] RTC 32.768 kHz Oscillator Control Register */ + __IO uint32_t GPIOCTL0; /*!< [0x0104] RTC GPIO Control 0 Register */ + __IO uint32_t GPIOCTL1; /*!< [0x0108] RTC GPIO Control 1 Register */ + __I uint32_t RESERVE2[1]; /* 0x10c */ + __IO uint32_t DSTCTL; /*!< [0x0110] RTC Daylight Saving Time Control Register */ + __I uint32_t RESERVE3[3]; /* 0x114 ~ 0x11c */ + __IO uint32_t TAMPCTL; /*!< [0x0120] RTC Tamper Pin Control Register */ + __I uint32_t RESERVE4[1]; /* 0x124 */ + __IO uint32_t TAMPSEED; /*!< [0x0128] RTC Tamper Dynamic Seed Register */ + __I uint32_t RESERVE5[1]; /* 0x12c */ + __I uint32_t TAMPTIME; /*!< [0x0130] RTC Tamper Time Register */ + __I uint32_t TAMPCAL; /*!< [0x0134] RTC Tamper Calendar Register */ + __I uint32_t RESERVE6[2]; /* 0x138 ~ 0x13c */ + __IO uint32_t CLKDCTL; /*!< [0x0140] RTC Clock Fail Detector Control Register */ + __IO uint32_t CDBR; /*!< [0x0144] RTC Clock Frequency Detector Boundary Register */ + +} RTC_T; + +/** + @addtogroup RTC_CONST RTC Bit Field Definition + Constant Definitions for RTC Controller + @{ +*/ + +#define RTC_INIT_ACTIVE_Pos (0) /*!< RTC_T::INIT: ACTIVE Position */ +#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) /*!< RTC_T::INIT: ACTIVE Mask */ + +#define RTC_INIT_INIT_Pos (1) /*!< RTC_T::INIT: INIT Position */ +#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC_T::INIT: INIT Mask */ + +#define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC_T::FREQADJ: FRACTION Position */ +#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC_T::FREQADJ: FRACTION Mask */ + +#define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC_T::FREQADJ: INTEGER Position */ +#define RTC_FREQADJ_INTEGER_Msk (0x1ful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC_T::FREQADJ: INTEGER Mask */ + +#define RTC_FREQADJ_FCRBUSY_Pos (31) /*!< RTC_T::FREQADJ: FCRBUSY Position */ +#define RTC_FREQADJ_FCRBUSY_Msk (0x1ul << RTC_FREQADJ_FCRBUSY_Pos) /*!< RTC_T::FREQADJ: FCRBUSY Mask */ + +#define RTC_TIME_SEC_Pos (0) /*!< RTC_T::TIME: SEC Position */ +#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC_T::TIME: SEC Mask */ + +#define RTC_TIME_TENSEC_Pos (4) /*!< RTC_T::TIME: TENSEC Position */ +#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC_T::TIME: TENSEC Mask */ + +#define RTC_TIME_MIN_Pos (8) /*!< RTC_T::TIME: MIN Position */ +#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC_T::TIME: MIN Mask */ + +#define RTC_TIME_TENMIN_Pos (12) /*!< RTC_T::TIME: TENMIN Position */ +#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC_T::TIME: TENMIN Mask */ + +#define RTC_TIME_HR_Pos (16) /*!< RTC_T::TIME: HR Position */ +#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC_T::TIME: HR Mask */ + +#define RTC_TIME_TENHR_Pos (20) /*!< RTC_T::TIME: TENHR Position */ +#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC_T::TIME: TENHR Mask */ + +#define RTC_CAL_DAY_Pos (0) /*!< RTC_T::CAL: DAY Position */ +#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC_T::CAL: DAY Mask */ + +#define RTC_CAL_TENDAY_Pos (4) /*!< RTC_T::CAL: TENDAY Position */ +#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC_T::CAL: TENDAY Mask */ + +#define RTC_CAL_MON_Pos (8) /*!< RTC_T::CAL: MON Position */ +#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC_T::CAL: MON Mask */ + +#define RTC_CAL_TENMON_Pos (12) /*!< RTC_T::CAL: TENMON Position */ +#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC_T::CAL: TENMON Mask */ + +#define RTC_CAL_YEAR_Pos (16) /*!< RTC_T::CAL: YEAR Position */ +#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC_T::CAL: YEAR Mask */ + +#define RTC_CAL_TENYEAR_Pos (20) /*!< RTC_T::CAL: TENYEAR Position */ +#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC_T::CAL: TENYEAR Mask */ + +#define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC_T::CLKFMT: 24HEN Position */ +#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC_T::CLKFMT: 24HEN Mask */ + +#define RTC_CLKFMT_DCOMPEN_Pos (16) /*!< RTC_T::CLKFMT: DCOMPEN Position */ +#define RTC_CLKFMT_DCOMPEN_Msk (0x1ul << RTC_CLKFMT_DCOMPEN_Pos) /*!< RTC_T::CLKFMT: DCOMPEN Mask */ + +#define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC_T::WEEKDAY: WEEKDAY Position */ +#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC_T::WEEKDAY: WEEKDAY Mask */ + +#define RTC_TALM_SEC_Pos (0) /*!< RTC_T::TALM: SEC Position */ +#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC_T::TALM: SEC Mask */ + +#define RTC_TALM_TENSEC_Pos (4) /*!< RTC_T::TALM: TENSEC Position */ +#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC_T::TALM: TENSEC Mask */ + +#define RTC_TALM_MIN_Pos (8) /*!< RTC_T::TALM: MIN Position */ +#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC_T::TALM: MIN Mask */ + +#define RTC_TALM_TENMIN_Pos (12) /*!< RTC_T::TALM: TENMIN Position */ +#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC_T::TALM: TENMIN Mask */ + +#define RTC_TALM_HR_Pos (16) /*!< RTC_T::TALM: HR Position */ +#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC_T::TALM: HR Mask */ + +#define RTC_TALM_TENHR_Pos (20) /*!< RTC_T::TALM: TENHR Position */ +#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC_T::TALM: TENHR Mask */ + +#define RTC_CALM_DAY_Pos (0) /*!< RTC_T::CALM: DAY Position */ +#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC_T::CALM: DAY Mask */ + +#define RTC_CALM_TENDAY_Pos (4) /*!< RTC_T::CALM: TENDAY Position */ +#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC_T::CALM: TENDAY Mask */ + +#define RTC_CALM_MON_Pos (8) /*!< RTC_T::CALM: MON Position */ +#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC_T::CALM: MON Mask */ + +#define RTC_CALM_TENMON_Pos (12) /*!< RTC_T::CALM: TENMON Position */ +#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC_T::CALM: TENMON Mask */ + +#define RTC_CALM_YEAR_Pos (16) /*!< RTC_T::CALM: YEAR Position */ +#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC_T::CALM: YEAR Mask */ + +#define RTC_CALM_TENYEAR_Pos (20) /*!< RTC_T::CALM: TENYEAR Position */ +#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC_T::CALM: TENYEAR Mask */ + +#define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC_T::LEAPYEAR: LEAPYEAR Position */ +#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC_T::LEAPYEAR: LEAPYEAR Mask */ + +#define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC_T::INTEN: ALMIEN Position */ +#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC_T::INTEN: ALMIEN Mask */ + +#define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC_T::INTEN: TICKIEN Position */ +#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC_T::INTEN: TICKIEN Mask */ + +#define RTC_INTEN_TAMP0IEN_Pos (8) /*!< RTC_T::INTEN: TAMP0IEN Position */ +#define RTC_INTEN_TAMP0IEN_Msk (0x1ul << RTC_INTEN_TAMP0IEN_Pos) /*!< RTC_T::INTEN: TAMP0IEN Mask */ + +#define RTC_INTEN_TAMP1IEN_Pos (9) /*!< RTC_T::INTEN: TAMP1IEN Position */ +#define RTC_INTEN_TAMP1IEN_Msk (0x1ul << RTC_INTEN_TAMP1IEN_Pos) /*!< RTC_T::INTEN: TAMP1IEN Mask */ + +#define RTC_INTEN_TAMP2IEN_Pos (10) /*!< RTC_T::INTEN: TAMP2IEN Position */ +#define RTC_INTEN_TAMP2IEN_Msk (0x1ul << RTC_INTEN_TAMP2IEN_Pos) /*!< RTC_T::INTEN: TAMP2IEN Mask */ + +#define RTC_INTEN_TAMP3IEN_Pos (11) /*!< RTC_T::INTEN: TAMP3IEN Position */ +#define RTC_INTEN_TAMP3IEN_Msk (0x1ul << RTC_INTEN_TAMP3IEN_Pos) /*!< RTC_T::INTEN: TAMP3IEN Mask */ + +#define RTC_INTEN_TAMP4IEN_Pos (12) /*!< RTC_T::INTEN: TAMP4IEN Position */ +#define RTC_INTEN_TAMP4IEN_Msk (0x1ul << RTC_INTEN_TAMP4IEN_Pos) /*!< RTC_T::INTEN: TAMP4IEN Mask */ + +#define RTC_INTEN_TAMP5IEN_Pos (13) /*!< RTC_T::INTEN: TAMP5IEN Position */ +#define RTC_INTEN_TAMP5IEN_Msk (0x1ul << RTC_INTEN_TAMP5IEN_Pos) /*!< RTC_T::INTEN: TAMP5IEN Mask */ + +#define RTC_INTEN_CLKFIEN_Pos (24) /*!< RTC_T::INTEN: CLKFIEN Position */ +#define RTC_INTEN_CLKFIEN_Msk (0x1ul << RTC_INTEN_CLKFIEN_Pos) /*!< RTC_T::INTEN: CLKFIEN Mask */ + +#define RTC_INTEN_CLKSTIEN_Pos (25) /*!< RTC_T::INTEN: CLKSTIEN Position */ +#define RTC_INTEN_CLKSTIEN_Msk (0x1ul << RTC_INTEN_CLKSTIEN_Pos) /*!< RTC_T::INTEN: CLKSTIEN Mask */ + +#define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC_T::INTSTS: ALMIF Position */ +#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC_T::INTSTS: ALMIF Mask */ + +#define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC_T::INTSTS: TICKIF Position */ +#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC_T::INTSTS: TICKIF Mask */ + +#define RTC_INTSTS_TAMP0IF_Pos (8) /*!< RTC_T::INTSTS: TAMP0IF Position */ +#define RTC_INTSTS_TAMP0IF_Msk (0x1ul << RTC_INTSTS_TAMP0IF_Pos) /*!< RTC_T::INTSTS: TAMP0IF Mask */ + +#define RTC_INTSTS_TAMP1IF_Pos (9) /*!< RTC_T::INTSTS: TAMP1IF Position */ +#define RTC_INTSTS_TAMP1IF_Msk (0x1ul << RTC_INTSTS_TAMP1IF_Pos) /*!< RTC_T::INTSTS: TAMP1IF Mask */ + +#define RTC_INTSTS_TAMP2IF_Pos (10) /*!< RTC_T::INTSTS: TAMP2IF Position */ +#define RTC_INTSTS_TAMP2IF_Msk (0x1ul << RTC_INTSTS_TAMP2IF_Pos) /*!< RTC_T::INTSTS: TAMP2IF Mask */ + +#define RTC_INTSTS_TAMP3IF_Pos (11) /*!< RTC_T::INTSTS: TAMP3IF Position */ +#define RTC_INTSTS_TAMP3IF_Msk (0x1ul << RTC_INTSTS_TAMP3IF_Pos) /*!< RTC_T::INTSTS: TAMP3IF Mask */ + +#define RTC_INTSTS_TAMP4IF_Pos (12) /*!< RTC_T::INTSTS: TAMP4IF Position */ +#define RTC_INTSTS_TAMP4IF_Msk (0x1ul << RTC_INTSTS_TAMP4IF_Pos) /*!< RTC_T::INTSTS: TAMP4IF Mask */ + +#define RTC_INTSTS_TAMP5IF_Pos (13) /*!< RTC_T::INTSTS: TAMP5IF Position */ +#define RTC_INTSTS_TAMP5IF_Msk (0x1ul << RTC_INTSTS_TAMP5IF_Pos) /*!< RTC_T::INTSTS: TAMP5IF Mask */ + +#define RTC_INTSTS_CLKFIF_Pos (24) /*!< RTC_T::INTSTS: CLKFIF Position */ +#define RTC_INTSTS_CLKFIF_Msk (0x1ul << RTC_INTSTS_CLKFIF_Pos) /*!< RTC_T::INTSTS: CLKFIF Mask */ + +#define RTC_INTSTS_CLKSTIF_Pos (25) /*!< RTC_T::INTSTS: CLKSTIF Position */ +#define RTC_INTSTS_CLKSTIF_Msk (0x1ul << RTC_INTSTS_CLKSTIF_Pos) /*!< RTC_T::INTSTS: CLKSTIF Mask */ + +#define RTC_TICK_TICK_Pos (0) /*!< RTC_T::TICK: TICK Position */ +#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) /*!< RTC_T::TICK: TICK Mask */ + +#define RTC_TAMSK_MSEC_Pos (0) /*!< RTC_T::TAMSK: MSEC Position */ +#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC_T::TAMSK: MSEC Mask */ + +#define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC_T::TAMSK: MTENSEC Position */ +#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC_T::TAMSK: MTENSEC Mask */ + +#define RTC_TAMSK_MMIN_Pos (2) /*!< RTC_T::TAMSK: MMIN Position */ +#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC_T::TAMSK: MMIN Mask */ + +#define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC_T::TAMSK: MTENMIN Position */ +#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC_T::TAMSK: MTENMIN Mask */ + +#define RTC_TAMSK_MHR_Pos (4) /*!< RTC_T::TAMSK: MHR Position */ +#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC_T::TAMSK: MHR Mask */ + +#define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC_T::TAMSK: MTENHR Position */ +#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC_T::TAMSK: MTENHR Mask */ + +#define RTC_CAMSK_MDAY_Pos (0) /*!< RTC_T::CAMSK: MDAY Position */ +#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC_T::CAMSK: MDAY Mask */ + +#define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC_T::CAMSK: MTENDAY Position */ +#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC_T::CAMSK: MTENDAY Mask */ + +#define RTC_CAMSK_MMON_Pos (2) /*!< RTC_T::CAMSK: MMON Position */ +#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC_T::CAMSK: MMON Mask */ + +#define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC_T::CAMSK: MTENMON Position */ +#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC_T::CAMSK: MTENMON Mask */ + +#define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC_T::CAMSK: MYEAR Position */ +#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC_T::CAMSK: MYEAR Mask */ + +#define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC_T::CAMSK: MTENYEAR Position */ +#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC_T::CAMSK: MTENYEAR Mask */ + +#define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC_T::SPRCTL: SPRRWEN Position */ +#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC_T::SPRCTL: SPRRWEN Mask */ + +#define RTC_SPRCTL_SPRCSTS_Pos (5) /*!< RTC_T::SPRCTL: SPRCSTS Position */ +#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos) /*!< RTC_T::SPRCTL: SPRCSTS Mask */ + +#define RTC_SPRCTL_LXTFCLR_Pos (16) /*!< RTC_T::SPRCTL: LXTFCLR Position */ +#define RTC_SPRCTL_LXTFCLR_Msk (0x1ul << RTC_SPRCTL_LXTFCLR_Pos) /*!< RTC_T::SPRCTL: LXTFCLR Mask */ + +#define RTC_SPR0_SPARE_Pos (0) /*!< RTC_T::SPR0: SPARE Position */ +#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos) /*!< RTC_T::SPR0: SPARE Mask */ + +#define RTC_SPR1_SPARE_Pos (0) /*!< RTC_T::SPR1: SPARE Position */ +#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos) /*!< RTC_T::SPR1: SPARE Mask */ + +#define RTC_SPR2_SPARE_Pos (0) /*!< RTC_T::SPR2: SPARE Position */ +#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos) /*!< RTC_T::SPR2: SPARE Mask */ + +#define RTC_SPR3_SPARE_Pos (0) /*!< RTC_T::SPR3: SPARE Position */ +#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos) /*!< RTC_T::SPR3: SPARE Mask */ + +#define RTC_SPR4_SPARE_Pos (0) /*!< RTC_T::SPR4: SPARE Position */ +#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos) /*!< RTC_T::SPR4: SPARE Mask */ + +#define RTC_SPR5_SPARE_Pos (0) /*!< RTC_T::SPR5: SPARE Position */ +#define RTC_SPR5_SPARE_Msk (0xfffffffful << RTC_SPR5_SPARE_Pos) /*!< RTC_T::SPR5: SPARE Mask */ + +#define RTC_SPR6_SPARE_Pos (0) /*!< RTC_T::SPR6: SPARE Position */ +#define RTC_SPR6_SPARE_Msk (0xfffffffful << RTC_SPR6_SPARE_Pos) /*!< RTC_T::SPR6: SPARE Mask */ + +#define RTC_SPR7_SPARE_Pos (0) /*!< RTC_T::SPR7: SPARE Position */ +#define RTC_SPR7_SPARE_Msk (0xfffffffful << RTC_SPR7_SPARE_Pos) /*!< RTC_T::SPR7: SPARE Mask */ + +#define RTC_SPR8_SPARE_Pos (0) /*!< RTC_T::SPR8: SPARE Position */ +#define RTC_SPR8_SPARE_Msk (0xfffffffful << RTC_SPR8_SPARE_Pos) /*!< RTC_T::SPR8: SPARE Mask */ + +#define RTC_SPR9_SPARE_Pos (0) /*!< RTC_T::SPR9: SPARE Position */ +#define RTC_SPR9_SPARE_Msk (0xfffffffful << RTC_SPR9_SPARE_Pos) /*!< RTC_T::SPR9: SPARE Mask */ + +#define RTC_SPR10_SPARE_Pos (0) /*!< RTC_T::SPR10: SPARE Position */ +#define RTC_SPR10_SPARE_Msk (0xfffffffful << RTC_SPR10_SPARE_Pos) /*!< RTC_T::SPR10: SPARE Mask */ + +#define RTC_SPR11_SPARE_Pos (0) /*!< RTC_T::SPR11: SPARE Position */ +#define RTC_SPR11_SPARE_Msk (0xfffffffful << RTC_SPR11_SPARE_Pos) /*!< RTC_T::SPR11: SPARE Mask */ + +#define RTC_SPR12_SPARE_Pos (0) /*!< RTC_T::SPR12: SPARE Position */ +#define RTC_SPR12_SPARE_Msk (0xfffffffful << RTC_SPR12_SPARE_Pos) /*!< RTC_T::SPR12: SPARE Mask */ + +#define RTC_SPR13_SPARE_Pos (0) /*!< RTC_T::SPR13: SPARE Position */ +#define RTC_SPR13_SPARE_Msk (0xfffffffful << RTC_SPR13_SPARE_Pos) /*!< RTC_T::SPR13: SPARE Mask */ + +#define RTC_SPR14_SPARE_Pos (0) /*!< RTC_T::SPR14: SPARE Position */ +#define RTC_SPR14_SPARE_Msk (0xfffffffful << RTC_SPR14_SPARE_Pos) /*!< RTC_T::SPR14: SPARE Mask */ + +#define RTC_SPR15_SPARE_Pos (0) /*!< RTC_T::SPR15: SPARE Position */ +#define RTC_SPR15_SPARE_Msk (0xfffffffful << RTC_SPR15_SPARE_Pos) /*!< RTC_T::SPR15: SPARE Mask */ + +#define RTC_SPR16_SPARE_Pos (0) /*!< RTC_T::SPR16: SPARE Position */ +#define RTC_SPR16_SPARE_Msk (0xfffffffful << RTC_SPR16_SPARE_Pos) /*!< RTC_T::SPR16: SPARE Mask */ + +#define RTC_SPR17_SPARE_Pos (0) /*!< RTC_T::SPR17: SPARE Position */ +#define RTC_SPR17_SPARE_Msk (0xfffffffful << RTC_SPR17_SPARE_Pos) /*!< RTC_T::SPR17: SPARE Mask */ + +#define RTC_SPR18_SPARE_Pos (0) /*!< RTC_T::SPR18: SPARE Position */ +#define RTC_SPR18_SPARE_Msk (0xfffffffful << RTC_SPR18_SPARE_Pos) /*!< RTC_T::SPR18: SPARE Mask */ + +#define RTC_SPR19_SPARE_Pos (0) /*!< RTC_T::SPR19: SPARE Position */ +#define RTC_SPR19_SPARE_Msk (0xfffffffful << RTC_SPR19_SPARE_Pos) /*!< RTC_T::SPR19: SPARE Mask */ + +#define RTC_LXTCTL_LIRC32KEN_Pos (0) /*!< RTC_T::LXTCTL: LIRC32KEN Position */ +#define RTC_LXTCTL_LIRC32KEN_Msk (0x1ul << RTC_LXTCTL_LIRC32KEN_Pos) /*!< RTC_T::LXTCTL: LIRC32KEN Mask */ + +#define RTC_LXTCTL_GAIN_Pos (1) /*!< RTC_T::LXTCTL: GAIN Position */ +#define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos) /*!< RTC_T::LXTCTL: GAIN Mask */ + +#define RTC_LXTCTL_C32KSEL_Pos (6) /*!< RTC_T::LXTCTL: C32KSEL Position */ +#define RTC_LXTCTL_C32KSEL_Msk (0x1ul << RTC_LXTCTL_C32KSEL_Pos) /*!< RTC_T::LXTCTL: C32KSEL Mask */ + +#define RTC_LXTCTL_RTCCKSEL_Pos (7) /*!< RTC_T::LXTCTL: RTCCKSEL Position */ +#define RTC_LXTCTL_RTCCKSEL_Msk (0x1ul << RTC_LXTCTL_RTCCKSEL_Pos) /*!< RTC_T::LXTCTL: RTCCKSEL Mask */ + +#define RTC_LXTCTL_IOCTLSEL_Pos (8) /*!< RTC_T::LXTCTL: IOCTLSEL Position */ +#define RTC_LXTCTL_IOCTLSEL_Msk (0x1ul << RTC_LXTCTL_IOCTLSEL_Pos) /*!< RTC_T::LXTCTL: IOCTLSEL Mask */ + +#define RTC_GPIOCTL0_OPMODE0_Pos (0) /*!< RTC_T::GPIOCTL0: OPMODE0 Position */ +#define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) /*!< RTC_T::GPIOCTL0: OPMODE0 Mask */ + +#define RTC_GPIOCTL0_DOUT0_Pos (2) /*!< RTC_T::GPIOCTL0: DOUT0 Position */ +#define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) /*!< RTC_T::GPIOCTL0: DOUT0 Mask */ + +#define RTC_GPIOCTL0_DINOFF0_Pos (3) /*!< RTC_T::GPIOCTL0: DINOFF0 Position */ +#define RTC_GPIOCTL0_DINOFF0_Msk (0x1ul << RTC_GPIOCTL0_DINOFF0_Pos) /*!< RTC_T::GPIOCTL0: DINOFF0 Mask */ + +#define RTC_GPIOCTL0_PUSEL0_Pos (4) /*!< RTC_T::GPIOCTL0: PUSEL0 Position */ +#define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) /*!< RTC_T::GPIOCTL0: PUSEL0 Mask */ + +#define RTC_GPIOCTL0_OPMODE1_Pos (8) /*!< RTC_T::GPIOCTL0: OPMODE1 Position */ +#define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) /*!< RTC_T::GPIOCTL0: OPMODE1 Mask */ + +#define RTC_GPIOCTL0_DOUT1_Pos (10) /*!< RTC_T::GPIOCTL0: DOUT1 Position */ +#define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) /*!< RTC_T::GPIOCTL0: DOUT1 Mask */ + +#define RTC_GPIOCTL0_DINOFF1_Pos (11) /*!< RTC_T::GPIOCTL0: DINOFF1 Position */ +#define RTC_GPIOCTL0_DINOFF1_Msk (0x1ul << RTC_GPIOCTL0_DINOFF1_Pos) /*!< RTC_T::GPIOCTL0: DINOFF1 Mask */ + +#define RTC_GPIOCTL0_PUSEL1_Pos (12) /*!< RTC_T::GPIOCTL0: PUSEL1 Position */ +#define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) /*!< RTC_T::GPIOCTL0: PUSEL1 Mask */ + +#define RTC_GPIOCTL0_OPMODE2_Pos (16) /*!< RTC_T::GPIOCTL0: OPMODE2 Position */ +#define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) /*!< RTC_T::GPIOCTL0: OPMODE2 Mask */ + +#define RTC_GPIOCTL0_DOUT2_Pos (18) /*!< RTC_T::GPIOCTL0: DOUT2 Position */ +#define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) /*!< RTC_T::GPIOCTL0: DOUT2 Mask */ + +#define RTC_GPIOCTL0_DINOFF2_Pos (19) /*!< RTC_T::GPIOCTL0: DINOFF2 Position */ +#define RTC_GPIOCTL0_DINOFF2_Msk (0x1ul << RTC_GPIOCTL0_DINOFF2_Pos) /*!< RTC_T::GPIOCTL0: DINOFF2 Mask */ + +#define RTC_GPIOCTL0_PUSEL2_Pos (20) /*!< RTC_T::GPIOCTL0: PUSEL2 Position */ +#define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) /*!< RTC_T::GPIOCTL0: PUSEL2 Mask */ + +#define RTC_GPIOCTL0_OPMODE3_Pos (24) /*!< RTC_T::GPIOCTL0: OPMODE3 Position */ +#define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) /*!< RTC_T::GPIOCTL0: OPMODE3 Mask */ + +#define RTC_GPIOCTL0_DOUT3_Pos (26) /*!< RTC_T::GPIOCTL0: DOUT3 Position */ +#define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) /*!< RTC_T::GPIOCTL0: DOUT3 Mask */ + +#define RTC_GPIOCTL0_DINOFF3_Pos (27) /*!< RTC_T::GPIOCTL0: DINOFF3 Position */ +#define RTC_GPIOCTL0_DINOFF3_Msk (0x1ul << RTC_GPIOCTL0_DINOFF3_Pos) /*!< RTC_T::GPIOCTL0: DINOFF3 Mask */ + +#define RTC_GPIOCTL0_PUSEL3_Pos (28) /*!< RTC_T::GPIOCTL0: PUSEL3 Position */ +#define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) /*!< RTC_T::GPIOCTL0: PUSEL3 Mask */ + +#define RTC_GPIOCTL1_OPMODE4_Pos (0) /*!< RTC_T::GPIOCTL1: OPMODE4 Position */ +#define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) /*!< RTC_T::GPIOCTL1: OPMODE4 Mask */ + +#define RTC_GPIOCTL1_DOUT4_Pos (2) /*!< RTC_T::GPIOCTL1: DOUT4 Position */ +#define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) /*!< RTC_T::GPIOCTL1: DOUT4 Mask */ + +#define RTC_GPIOCTL0_DINOFF4_Pos (3) /*!< RTC_T::GPIOCTL1: DINOFF4 Position */ +#define RTC_GPIOCTL0_DINOFF4_Msk (0x1ul << RTC_GPIOCTL0_DINOFF4_Pos) /*!< RTC_T::GPIOCTL1: DINOFF4 Mask */ + +#define RTC_GPIOCTL1_PUSEL4_Pos (4) /*!< RTC_T::GPIOCTL1: PUSEL4 Position */ +#define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) /*!< RTC_T::GPIOCTL1: PUSEL4 Mask */ + +#define RTC_GPIOCTL1_OPMODE5_Pos (8) /*!< RTC_T::GPIOCTL1: OPMODE5 Position */ +#define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) /*!< RTC_T::GPIOCTL1: OPMODE5 Mask */ + +#define RTC_GPIOCTL1_DOUT5_Pos (10) /*!< RTC_T::GPIOCTL1: DOUT5 Position */ +#define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) /*!< RTC_T::GPIOCTL1: DOUT5 Mask */ + +#define RTC_GPIOCTL0_DINOFF5_Pos (11) /*!< RTC_T::GPIOCTL1: DINOFF5 Position */ +#define RTC_GPIOCTL0_DINOFF5_Msk (0x1ul << RTC_GPIOCTL0_DINOFF5_Pos) /*!< RTC_T::GPIOCTL1: DINOFF5 Mask */ + +#define RTC_GPIOCTL1_PUSEL5_Pos (12) /*!< RTC_T::GPIOCTL1: PUSEL5 Position */ +#define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) /*!< RTC_T::GPIOCTL1: PUSEL5 Mask */ + +#define RTC_GPIOCTL1_OPMODE6_Pos (16) /*!< RTC_T::GPIOCTL1: OPMODE6 Position */ +#define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) /*!< RTC_T::GPIOCTL1: OPMODE6 Mask */ + +#define RTC_GPIOCTL1_DOUT6_Pos (18) /*!< RTC_T::GPIOCTL1: DOUT6 Position */ +#define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) /*!< RTC_T::GPIOCTL1: DOUT6 Mask */ + +#define RTC_GPIOCTL0_DINOFF6_Pos (19) /*!< RTC_T::GPIOCTL1: DINOFF6 Position */ +#define RTC_GPIOCTL0_DINOFF6_Msk (0x1ul << RTC_GPIOCTL0_DINOFF6_Pos) /*!< RTC_T::GPIOCTL1: DINOFF6 Mask */ + +#define RTC_GPIOCTL1_PUSEL6_Pos (20) /*!< RTC_T::GPIOCTL1: PUSEL6 Position */ +#define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) /*!< RTC_T::GPIOCTL1: PUSEL6 Mask */ + +#define RTC_GPIOCTL1_OPMODE7_Pos (24) /*!< RTC_T::GPIOCTL1: OPMODE7 Position */ +#define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) /*!< RTC_T::GPIOCTL1: OPMODE7 Mask */ + +#define RTC_GPIOCTL1_DOUT7_Pos (26) /*!< RTC_T::GPIOCTL1: DOUT7 Position */ +#define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) /*!< RTC_T::GPIOCTL1: DOUT7 Mask */ + +#define RTC_GPIOCTL0_DINOFF7_Pos (27) /*!< RTC_T::GPIOCTL1: DINOFF7 Position */ +#define RTC_GPIOCTL0_DINOFF7_Msk (0x1ul << RTC_GPIOCTL0_DINOFF7_Pos) /*!< RTC_T::GPIOCTL1: DINOFF7 Mask */ + +#define RTC_GPIOCTL1_PUSEL7_Pos (28) /*!< RTC_T::GPIOCTL1: PUSEL7 Position */ +#define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) /*!< RTC_T::GPIOCTL1: PUSEL7 Mask */ + +#define RTC_DSTCTL_ADDHR_Pos (0) /*!< RTC_T::DSTCTL: ADDHR Position */ +#define RTC_DSTCTL_ADDHR_Msk (0x1ul << RTC_DSTCTL_ADDHR_Pos) /*!< RTC_T::DSTCTL: ADDHR Mask */ + +#define RTC_DSTCTL_SUBHR_Pos (1) /*!< RTC_T::DSTCTL: SUBHR Position */ +#define RTC_DSTCTL_SUBHR_Msk (0x1ul << RTC_DSTCTL_SUBHR_Pos) /*!< RTC_T::DSTCTL: SUBHR Mask */ + +#define RTC_DSTCTL_DSBAK_Pos (2) /*!< RTC_T::DSTCTL: DSBAK Position */ +#define RTC_DSTCTL_DSBAK_Msk (0x1ul << RTC_DSTCTL_DSBAK_Pos) /*!< RTC_T::DSTCTL: DSBAK Mask */ + +#define RTC_TAMPCTL_DYN1ISS_Pos (0) /*!< RTC_T::TAMPCTL: DYN1ISS Position */ +#define RTC_TAMPCTL_DYN1ISS_Msk (0x1ul << RTC_TAMPCTL_DYN1ISS_Pos) /*!< RTC_T::TAMPCTL: DYN1ISS Mask */ + +#define RTC_TAMPCTL_DYN2ISS_Pos (1) /*!< RTC_T::TAMPCTL: DYN2ISS Position */ +#define RTC_TAMPCTL_DYN2ISS_Msk (0x1ul << RTC_TAMPCTL_DYN2ISS_Pos) /*!< RTC_T::TAMPCTL: DYN2ISS Mask */ + +#define RTC_TAMPCTL_DYNSRC_Pos (3) /*!< RTC_T::TAMPCTL: DYNSRC Position */ +#define RTC_TAMPCTL_DYNSRC_Msk (0x1ul << RTC_TAMPCTL_DYNSRC_Pos) /*!< RTC_T::TAMPCTL: DYNSRC Mask */ + +#define RTC_TAMPCTL_SEEDRLD_Pos (4) /*!< RTC_T::TAMPCTL: SEEDRLD Position */ +#define RTC_TAMPCTL_SEEDRLD_Msk (0x1ul << RTC_TAMPCTL_SEEDRLD_Pos) /*!< RTC_T::TAMPCTL: SEEDRLD Mask */ + +#define RTC_TAMPCTL_DYNRATE_Pos (5) /*!< RTC_T::TAMPCTL: DYNRATE Position */ +#define RTC_TAMPCTL_DYNRATE_Msk (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< RTC_T::TAMPCTL: DYNRATE Mask */ + +#define RTC_TAMPCTL_TAMP0EN_Pos (8) /*!< RTC_T::TAMPCTL: TAMP0EN Position */ +#define RTC_TAMPCTL_TAMP0EN_Msk (0x1ul << RTC_TAMPCTL_TAMP0EN_Pos) /*!< RTC_T::TAMPCTL: TAMP0EN Mask */ + +#define RTC_TAMPCTL_TAMP0LV_Pos (9) /*!< RTC_T::TAMPCTL: TAMP0LV Position */ +#define RTC_TAMPCTL_TAMP0LV_Msk (0x1ul << RTC_TAMPCTL_TAMP0LV_Pos) /*!< RTC_T::TAMPCTL: TAMP0LV Mask */ + +#define RTC_TAMPCTL_TAMP0DBEN_Pos (10) /*!< RTC_T::TAMPCTL: TAMP0DBEN Position */ +#define RTC_TAMPCTL_TAMP0DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP0DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP0DBEN Mask */ + +#define RTC_TAMPCTL_TAMP1EN_Pos (12) /*!< RTC_T::TAMPCTL: TAMP1EN Position */ +#define RTC_TAMPCTL_TAMP1EN_Msk (0x1ul << RTC_TAMPCTL_TAMP1EN_Pos) /*!< RTC_T::TAMPCTL: TAMP1EN Mask */ + +#define RTC_TAMPCTL_TAMP1LV_Pos (13) /*!< RTC_T::TAMPCTL: TAMP1LV Position */ +#define RTC_TAMPCTL_TAMP1LV_Msk (0x1ul << RTC_TAMPCTL_TAMP1LV_Pos) /*!< RTC_T::TAMPCTL: TAMP1LV Mask */ + +#define RTC_TAMPCTL_TAMP1DBEN_Pos (14) /*!< RTC_T::TAMPCTL: TAMP1DBEN Position */ +#define RTC_TAMPCTL_TAMP1DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP1DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP1DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR0EN_Pos (15) /*!< RTC_T::TAMPCTL: DYNPR0EN Position */ +#define RTC_TAMPCTL_DYNPR0EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR0EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR0EN Mask */ + +#define RTC_TAMPCTL_TAMP2EN_Pos (16) /*!< RTC_T::TAMPCTL: TAMP2EN Position */ +#define RTC_TAMPCTL_TAMP2EN_Msk (0x1ul << RTC_TAMPCTL_TAMP2EN_Pos) /*!< RTC_T::TAMPCTL: TAMP2EN Mask */ + +#define RTC_TAMPCTL_TAMP2LV_Pos (17) /*!< RTC_T::TAMPCTL: TAMP2LV Position */ +#define RTC_TAMPCTL_TAMP2LV_Msk (0x1ul << RTC_TAMPCTL_TAMP2LV_Pos) /*!< RTC_T::TAMPCTL: TAMP2LV Mask */ + +#define RTC_TAMPCTL_TAMP2DBEN_Pos (18) /*!< RTC_T::TAMPCTL: TAMP2DBEN Position */ +#define RTC_TAMPCTL_TAMP2DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP2DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP2DBEN Mask */ + +#define RTC_TAMPCTL_TAMP3EN_Pos (20) /*!< RTC_T::TAMPCTL: TAMP3EN Position */ +#define RTC_TAMPCTL_TAMP3EN_Msk (0x1ul << RTC_TAMPCTL_TAMP3EN_Pos) /*!< RTC_T::TAMPCTL: TAMP3EN Mask */ + +#define RTC_TAMPCTL_TAMP3LV_Pos (21) /*!< RTC_T::TAMPCTL: TAMP3LV Position */ +#define RTC_TAMPCTL_TAMP3LV_Msk (0x1ul << RTC_TAMPCTL_TAMP3LV_Pos) /*!< RTC_T::TAMPCTL: TAMP3LV Mask */ + +#define RTC_TAMPCTL_TAMP3DBEN_Pos (22) /*!< RTC_T::TAMPCTL: TAMP3DBEN Position */ +#define RTC_TAMPCTL_TAMP3DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP3DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP3DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR1EN_Pos (23) /*!< RTC_T::TAMPCTL: DYNPR1EN Position */ +#define RTC_TAMPCTL_DYNPR1EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR1EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR1EN Mask */ + +#define RTC_TAMPCTL_TAMP4EN_Pos (24) /*!< RTC_T::TAMPCTL: TAMP4EN Position */ +#define RTC_TAMPCTL_TAMP4EN_Msk (0x1ul << RTC_TAMPCTL_TAMP4EN_Pos) /*!< RTC_T::TAMPCTL: TAMP4EN Mask */ + +#define RTC_TAMPCTL_TAMP4LV_Pos (25) /*!< RTC_T::TAMPCTL: TAMP4LV Position */ +#define RTC_TAMPCTL_TAMP4LV_Msk (0x1ul << RTC_TAMPCTL_TAMP4LV_Pos) /*!< RTC_T::TAMPCTL: TAMP4LV Mask */ + +#define RTC_TAMPCTL_TAMP4DBEN_Pos (26) /*!< RTC_T::TAMPCTL: TAMP4DBEN Position */ +#define RTC_TAMPCTL_TAMP4DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP4DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP4DBEN Mask */ + +#define RTC_TAMPCTL_TAMP5EN_Pos (28) /*!< RTC_T::TAMPCTL: TAMP5EN Position */ +#define RTC_TAMPCTL_TAMP5EN_Msk (0x1ul << RTC_TAMPCTL_TAMP5EN_Pos) /*!< RTC_T::TAMPCTL: TAMP5EN Mask */ + +#define RTC_TAMPCTL_TAMP5LV_Pos (29) /*!< RTC_T::TAMPCTL: TAMP5LV Position */ +#define RTC_TAMPCTL_TAMP5LV_Msk (0x1ul << RTC_TAMPCTL_TAMP5LV_Pos) /*!< RTC_T::TAMPCTL: TAMP5LV Mask */ + +#define RTC_TAMPCTL_TAMP5DBEN_Pos (30) /*!< RTC_T::TAMPCTL: TAMP5DBEN Position */ +#define RTC_TAMPCTL_TAMP5DBEN_Msk (0x1ul << RTC_TAMPCTL_TAMP5DBEN_Pos) /*!< RTC_T::TAMPCTL: TAMP5DBEN Mask */ + +#define RTC_TAMPCTL_DYNPR2EN_Pos (31) /*!< RTC_T::TAMPCTL: DYNPR2EN Position */ +#define RTC_TAMPCTL_DYNPR2EN_Msk (0x1ul << RTC_TAMPCTL_DYNPR2EN_Pos) /*!< RTC_T::TAMPCTL: DYNPR2EN Mask */ + +#define RTC_TAMPSEED_SEED_Pos (0) /*!< RTC_T::TAMPSEED: SEED Position */ +#define RTC_TAMPSEED_SEED_Msk (0xfffffffful << RTC_TAMPSEED_SEED_Pos) /*!< RTC_T::TAMPSEED: SEED Mask */ + +#define RTC_TAMPTIME_SEC_Pos (0) /*!< RTC_T::TAMPTIME: SEC Position */ +#define RTC_TAMPTIME_SEC_Msk (0xful << RTC_TAMPTIME_SEC_Pos) /*!< RTC_T::TAMPTIME: SEC Mask */ + +#define RTC_TAMPTIME_TENSEC_Pos (4) /*!< RTC_T::TAMPTIME: TENSEC Position */ +#define RTC_TAMPTIME_TENSEC_Msk (0x7ul << RTC_TAMPTIME_TENSEC_Pos) /*!< RTC_T::TAMPTIME: TENSEC Mask */ + +#define RTC_TAMPTIME_MIN_Pos (8) /*!< RTC_T::TAMPTIME: MIN Position */ +#define RTC_TAMPTIME_MIN_Msk (0xful << RTC_TAMPTIME_MIN_Pos) /*!< RTC_T::TAMPTIME: MIN Mask */ + +#define RTC_TAMPTIME_TENMIN_Pos (12) /*!< RTC_T::TAMPTIME: TENMIN Position */ +#define RTC_TAMPTIME_TENMIN_Msk (0x7ul << RTC_TAMPTIME_TENMIN_Pos) /*!< RTC_T::TAMPTIME: TENMIN Mask */ + +#define RTC_TAMPTIME_HR_Pos (16) /*!< RTC_T::TAMPTIME: HR Position */ +#define RTC_TAMPTIME_HR_Msk (0xful << RTC_TAMPTIME_HR_Pos) /*!< RTC_T::TAMPTIME: HR Mask */ + +#define RTC_TAMPTIME_TENHR_Pos (20) /*!< RTC_T::TAMPTIME: TENHR Position */ +#define RTC_TAMPTIME_TENHR_Msk (0x3ul << RTC_TAMPTIME_TENHR_Pos) /*!< RTC_T::TAMPTIME: TENHR Mask */ + +#define RTC_TAMPCAL_DAY_Pos (0) /*!< RTC_T::TAMPCAL: DAY Position */ +#define RTC_TAMPCAL_DAY_Msk (0xful << RTC_TAMPCAL_DAY_Pos) /*!< RTC_T::TAMPCAL: DAY Mask */ + +#define RTC_TAMPCAL_TENDAY_Pos (4) /*!< RTC_T::TAMPCAL: TENDAY Position */ +#define RTC_TAMPCAL_TENDAY_Msk (0x3ul << RTC_TAMPCAL_TENDAY_Pos) /*!< RTC_T::TAMPCAL: TENDAY Mask */ + +#define RTC_TAMPCAL_MON_Pos (8) /*!< RTC_T::TAMPCAL: MON Position */ +#define RTC_TAMPCAL_MON_Msk (0xful << RTC_TAMPCAL_MON_Pos) /*!< RTC_T::TAMPCAL: MON Mask */ + +#define RTC_TAMPCAL_TENMON_Pos (12) /*!< RTC_T::TAMPCAL: TENMON Position */ +#define RTC_TAMPCAL_TENMON_Msk (0x1ul << RTC_TAMPCAL_TENMON_Pos) /*!< RTC_T::TAMPCAL: TENMON Mask */ + +#define RTC_TAMPCAL_YEAR_Pos (16) /*!< RTC_T::TAMPCAL: YEAR Position */ +#define RTC_TAMPCAL_YEAR_Msk (0xful << RTC_TAMPCAL_YEAR_Pos) /*!< RTC_T::TAMPCAL: YEAR Mask */ + +#define RTC_TAMPCAL_TENYEAR_Pos (20) /*!< RTC_T::TAMPCAL: TENYEAR Position */ +#define RTC_TAMPCAL_TENYEAR_Msk (0xful << RTC_TAMPCAL_TENYEAR_Pos) /*!< RTC_T::TAMPCAL: TENYEAR Mask */ + +#define RTC_CLKDCTL_LXTFDEN_Pos (0) /*!< RTC_T::CLKDCTL: LXTFDEN Position */ +#define RTC_CLKDCTL_LXTFDEN_Msk (0x1ul << RTC_CLKDCTL_LXTFDEN_Pos) /*!< RTC_T::CLKDCTL: LXTFDEN Mask */ + +#define RTC_CLKDCTL_LXTFSW_Pos (1) /*!< RTC_T::CLKDCTL: LXTFSW Position */ +#define RTC_CLKDCTL_LXTFSW_Msk (0x1ul << RTC_CLKDCTL_LXTFSW_Pos) /*!< RTC_T::CLKDCTL: LXTFSW Mask */ + +#define RTC_CLKDCTL_LXTSTSW_Pos (2) /*!< RTC_T::CLKDCTL: LXTSTSW Position */ +#define RTC_CLKDCTL_LXTSTSW_Msk (0x1ul << RTC_CLKDCTL_LXTSTSW_Pos) /*!< RTC_T::CLKDCTL: LXTSTSW Mask */ + +#define RTC_CLKDCTL_SWLIRCF_Pos (16) /*!< RTC_T::CLKDCTL: SWLIRCF Position */ +#define RTC_CLKDCTL_SWLIRCF_Msk (0x1ul << RTC_CLKDCTL_SWLIRCF_Pos) /*!< RTC_T::CLKDCTL: SWLIRCF Mask */ + +#define RTC_CLKDCTL_LXTSLOWF_Pos (17) /*!< RTC_T::CLKDCTL: LXTSLOWF Position */ +#define RTC_CLKDCTL_LXTSLOWF_Msk (0x1ul << RTC_CLKDCTL_LXTSLOWF_Pos) /*!< RTC_T::CLKDCTL: LXTSLOWF Mask */ + +#define RTC_CDBR_STOPBD_Pos (0) /*!< RTC_T::CDBR: STOPBD Position */ +#define RTC_CDBR_STOPBD_Msk (0xfful << RTC_CDBR_STOPBD_Pos) /*!< RTC_T::CDBR: STOPBD Mask */ + +#define RTC_CDBR_FAILBD_Pos (16) /*!< RTC_T::CDBR: FAILBD Position */ +#define RTC_CDBR_FAILBD_Msk (0xfful << RTC_CDBR_FAILBD_Pos) /*!< RTC_T::CDBR: FAILBD Mask */ + +/**@}*/ /* RTC_CONST */ +/**@}*/ /* end of RTC register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __RTC_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/sc_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/sc_reg.h new file mode 100644 index 0000000000..d0320f3beb --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/sc_reg.h @@ -0,0 +1,980 @@ +/**************************************************************************//** + * @file sc_reg.h + * @version V1.00 + * @brief SC register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_REG_H__ +#define __SC_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Smart Card Host Interface Controller -------------------------*/ +/** + @addtogroup SC Smart Card Host Interface Controller(SC) + Memory Mapped Structure for SC Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var SC_T::DAT + * Offset: 0x00 SC Receive/Transmit Holding Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Receive/Transmit Holding Buffer + * | | |Write Operation: + * | | |By writing data to DAT, the SC will send out an 8-bit data. + * | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed. + * | | |Read Operation: + * | | |By reading DAT, the SC will return an 8-bit received data. + * @var SC_T::CTL + * Offset: 0x04 SC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SCEN |SC Controller Enable Bit + * | | |Set this bit to 1 to enable SC operation. + * | | |0 = SC will force all transition to IDLE state. + * | | |1 = SC controller is enabled and all function can work correctly. + * | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. + * |[1] |RXOFF |RX Transition Disable Control Bit + * | | |This bit is used for disable Rx transition function. + * | | |0 = The receiver Enabled. + * | | |1 = The receiver Disabled. + * | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[2] |TXOFF |TX Transition Disable Control Bit + * | | |This bit is used for disable Tx transition function. + * | | |0 = The transceiver Enabled. + * | | |1 = The transceiver Disabled. + * |[3] |AUTOCEN |Auto Convention Enable Bit + * | | |This bit is used for enable auto convention function. + * | | |0 = Auto-convention Disabled. + * | | |1 = Auto-convention Enabled. + * | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) state and the first data must be 0x3B or 0x3F + * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F + * | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11. + * | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. + * |[5:4] |CONSEL |Convention Selection + * | | |00 = Direct convention. + * | | |01 = Reserved. + * | | |10 = Reserved. + * | | |11 = Inverse convention. + * | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. + * |[7:6] |RXTRGLV |Rx Buffer Trigger Level + * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set + * | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. + * | | |00 = Rx Buffer Trigger Level with 01 bytes. + * | | |01 = Rx Buffer Trigger Level with 02 bytes. + * | | |10 = Rx Buffer Trigger Level with 03 bytes. + * | | |11 = Reserved. + * |[12:8] |BGT |Block Guard Time (BGT) + * | | |Block guard time means the minimum interval between the leading edges of two consecutive characters between different transfer directions + * | | |This field indicates the counter for the bit length of block guard time + * | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it. + * | | |Note: The real block guard time is BGT + 1. + * |[14:13] |TMRSEL |Timer Channel Selection + * | | |00 = All internal timer function Disabled. + * | | |. + * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled + * | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0]. + * | | |Other configurations are reserve + * |[15] |NSB |Stop Bit Length + * | | |This field indicates the length of stop bit. + * | | |0 = The stop bit length is 2 ETU.(for ISO 7816-3 T=0 mode). + * | | |1= The stop bit length is 1 ETU.(for ISO 7816-3 T=1 mode). + * | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. + * | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. + * |[18:16] |RXRTY |RX Error Retry Count Number + * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred + * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when RXRTYEN enabled + * | | |The change flow is to disable RXRTYEN first and then fill in new retry value. + * |[19] |RXRTYEN |RX Error Retry Enable Bit + * | | |This bit enables receiver retry function when parity error has occurred. + * | | |0 = RX error retry function Disabled. + * | | |1 = RX error retry function Enabled. + * | | |Note: User must fill in the RXRTY value before enabling this bit. + * |[22:20] |TXRTY |TX Error Retry Count Number + * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred. + * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. + * | | |Note2: This field cannot be changed when TXRTYEN enabled + * | | |The change flow is to disable TXRTYEN first and then fill in new retry value. + * |[23] |TXRTYEN |TX Error Retry Enable Bit + * | | |This bit enables transmitter retry function when parity error has occurred. + * | | |0 = TX error retry function Disabled. + * | | |1 = TX error retry function Enabled. + * |[25:24] |CDDBSEL |Card Detect De-bounce Selection + * | | |This field indicates the card detect de-bounce selection. + * | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce sample card removal once per 128 SC module clocks. + * | | |Other configurations are reserved. + * |[26] |CDLV |Card Detect Level Selection + * | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected. + * | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected. + * | | |Note: User must select card detect level before Smart Card controller enabled. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. + * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY. + * | | |1 = Last value is synchronizing. + * @var SC_T::ALTCTL + * Offset: 0x08 SC Alternate Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXRST |TX Software Reset + * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[1] |RXRST |Rx Software Reset + * | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared. + * | | |0 = No effect. + * | | |1 = Reset the Rx internal state machine and pointers. + * | | |Note: This bit will be auto cleared after reset is complete. + * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by deactivation sequence. + * | | |0 = No effect. + * | | |1 = Deactivation sequence generator Enabled. + * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[3] |ACTEN |Activation Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by activation sequence. + * | | |0 = No effect. + * | | |1 = Activation sequence generator Enabled. + * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data + * | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. + * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit + * | | |This bit enables SC controller to initiate the card by warm reset sequence. + * | | |0 = No effect. + * | | |1 = Warm reset sequence generator Enabled. + * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF (SCn_INTSTS[8]) will be set to 1. + * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) + * | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data + * | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform warm reset sequence. + * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit + * | | |This bit enables Timer 0 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed + * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit + * | | |This bit enables Timer 1 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only + * | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit + * | | |This bit enables Timer 2 to start counting + * | | |User can fill 0 to stop it and set 1 to reload and count + * | | |The counter unit is ETU base. + * | | |0 = Stops counting. + * | | |1 = Start counting. + * | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only + * | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. + * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware. + * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. + * |[9:8] |INITSEL |Initial Timing Selection + * | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation. + * | | |The unit of initial timing is SC module clock. + * | | |Activation: refer to SC Activation Sequence in Figure 6.17-4 SC Activation Sequence. + * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5 SC Warm Reset Sequence. + * | | |Deactivation: refer to Deactivation Sequence in Figure 6.17-6 SC Deactivation Sequence. + * | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation at most 128 SC module clock cycles. + * |[11] |ADACEN |Auto Deactivation When Card Removal + * | | |This bit is used for enable hardware auto deactivation when smart card is removed. + * | | |0 = Auto deactivation Disabled. + * | | |1 = Auto deactivation Enabled. + * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence if this bit is set + * | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. + * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit + * | | |This bit enables the receiver block guard time function. + * | | |0 = Receiver block guard time function Disabled. + * | | |1 = Receiver block guard time function Enabled. + * |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer0. + * | | |0 = Timer0 is not active. + * | | |1 = Timer0 is active. + * | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). + * |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer1. + * | | |0 = Timer1 is not active. + * | | |1 = Timer1 is active. + * | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). + * |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only) + * | | |This bit indicates the timer counter status of timer2. + * | | |0 = Timer2 is not active. + * | | |1 = Timer2 is active. + * | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::EGT + * Offset: 0x0C SC Extra Guard Time Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |EGT |Extra Guard Time + * | | |This field indicates the extra guard time value. + * | | |Note: The extra guard time unit is ETU base. + * @var SC_T::RXTOUT + * Offset: 0x10 SC Receive Buffer Time-out Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |RFTM |SC Receiver FIFO Time-out Counter + * | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data + * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SCn_DAT, a receiver time-out flag RXTOIF (SCn_INTSTS[9]) will be set, and hardware will generate an interrupt to CPU when RXTOIEN (SCn_INTEN[9]) is enabled. + * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5. + * | | |Note2: Filling in all 0 to this field indicates to disable this function. + * @var SC_T::ETUCTL + * Offset: 0x14 SC Element Time Unit Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |ETURDIV |ETU Rate Divider + * | | |The field is used for ETU clock rate divider. + * | | |The real ETU is ETURDIV + 1. + * | | |Note: User can configure this field, but this field must be greater than 0x04. + * @var SC_T::INTEN + * Offset: 0x18 SC Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit + * | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. + * | | |0 = Receive data reach trigger level interrupt Disabled. + * | | |1 = Receive data reach trigger level interrupt Enabled. + * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit + * | | |This field is used to enable transmit buffer empty interrupt. + * | | |0 = Transmit buffer empty interrupt Disabled. + * | | |1 = Transmit buffer empty interrupt Enabled. + * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit + * | | |This field is used to enable transfer error interrupt + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt Disabled. + * | | |1 = Transfer error interrupt Enabled. + * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit + * | | |This field is used to enable Timer0 interrupt function. + * | | |0 = Timer0 interrupt Disabled. + * | | |1 = Timer0 interrupt Enabled. + * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit + * | | |This field is used to enable the Timer1 interrupt function. + * | | |0 = Timer1 interrupt Disabled. + * | | |1 = Timer1 interrupt Enabled. + * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit + * | | |This field is used to enable Timer2 interrupt function. + * | | |0 = Timer2 interrupt Disabled. + * | | |1 = Timer2 interrupt Enabled. + * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit + * | | |This field is used to enable block guard time interrupt in receive direction. + * | | |0 = Block guard time interrupt Disabled. + * | | |1 = Block guard time interrupt Enabled. + * | | |Note: This bit is valid only for receive receive direction block guard time. + * |[7] |CDIEN |Card Detect Interrupt Enable Bit + * | | |This field is used to enable card detect interrupt + * | | |The card detect status is CDPINSTS (SCn_STATUS[13]). + * | | |0 = Card detect interrupt Disabled. + * | | |1 = Card detect interrupt Enabled. + * |[8] |INITIEN |Initial End Interrupt Enable Bit + * | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation (DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt. + * | | |0 = Initial end interrupt Disabled. + * | | |1 = Initial end interrupt Enabled. + * |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit + * | | |This field is used to enable receiver buffer time-out interrupt. + * | | |0 = Receiver buffer time-out interrupt Disabled. + * | | |1 = Receiver buffer time-out interrupt Enabled. + * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit + * | | |This field is used to enable auto-convention error interrupt. + * | | |0 = Auto-convention error interrupt Disabled. + * | | |1 = Auto-convention error interrupt Enabled. + * @var SC_T::INTSTS + * Offset: 0x1C SC Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only) + * | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag. + * | | |0 = Number of receive buffer is less than RXTRGLV setting. + * | | |1 = Number of receive buffer data equals the RXTRGLV setting. + * | | |Note: This bit is read only + * | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, this bit will be cleared automatically. + * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only) + * | | |This field is used for transmit buffer empty interrupt status flag. + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * | | |Note: This bit is read only + * | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit will be cleared automatically. + * |[2] |TERRIF |Transfer Error Interrupt Status Flag + * | | |This field is used for transfer error interrupt status flag + * | | |The transfer error states is at SCn_STATUS register which includes receiver break error BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error TXOVERR (SCn_STATUS[30]). + * | | |0 = Transfer error interrupt did not occur. + * | | |1 = Transfer error interrupt occurred. + * | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[3] |TMR0IF |Timer0 Interrupt Status Flag + * | | |This field is used for Timer0 interrupt status flag. + * | | |0 = Timer0 interrupt did not occur. + * | | |1 = Timer0 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[4] |TMR1IF |Timer1 Interrupt Status Flag + * | | |This field is used for Timer1 interrupt status flag. + * | | |0 = Timer1 interrupt did not occur. + * | | |1 = Timer1 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[5] |TMR2IF |Timer2 Interrupt Status Flag + * | | |This field is used for Timer2 interrupt status flag. + * | | |0 = Timer2 interrupt did not occur. + * | | |1 = Timer2 interrupt occurred. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[6] |BGTIF |Block Guard Time Interrupt Status Flag + * | | |This field is used for indicate block guard time interrupt status flag in receive direction. + * | | |0 = Block guard time interrupt did not occur. + * | | |1 = Block guard time interrupt occurred. + * | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only) + * | | |This field is used for card detect interrupt status flag + * | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]). + * | | |0 = Card detect event did not occur. + * | | |1 = Card detect event occurred. + * | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. + * |[8] |INITIF |Initial End Interrupt Status Flag + * | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag. + * | | |0 = Initial sequence is not complete. + * | | |1 = Initial sequence is completed. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only) + * | | |This field is used for indicate receive buffer time-out interrupt status flag. + * | | |0 = Receive buffer time-out interrupt did not occur. + * | | |1 = Receive buffer time-out interrupt occurred. + * | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT register to clear it. + * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag + * | | |This field indicates auto convention sequence error. + * | | |0 = Received TS at ATR state is 0x3B or 0x3F. + * | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F. + * | | |Note: This bit can be cleared by writing 1 to it. + * @var SC_T::STATUS + * Offset: 0x20 SC Transfer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOV |Receive Overflow Error Status Flag + * | | |This bit is set when Rx buffer overflow. + * | | |0 = Rx buffer is not overflow. + * | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only) + * | | |This bit indicates Rx buffer empty or not. + * | | |0 = Rx buffer is not empty. + * | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU. + * |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only) + * | | |This bit indicates Rx buffer full or not. + * | | |0 = Rx buffer count is less than 4. + * | | |1 = Rx buffer count equals to 4. + * |[4] |PEF |Receiver Parity Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. + * | | |0 = Receiver parity error flag did not occur. + * | | |1 = Receiver parity error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[5] |FEF |Receiver Frame Error Status Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = Receiver frame error flag did not occur. + * | | |1 = Receiver frame error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[6] |BEF |Receiver Break Error Status Flag + * | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state (logic 0) is longer than a full word transmission time (that is, the total time of start bit + data bits + parity bit + stop bits). + * | | |0 = Receiver break error flag did not occur. + * | | |1 = Receiver break error flag occurred. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag + * | | |This bit is set when Tx buffer overflow. + * | | |0 = Tx buffer is not overflow. + * | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]). + * | | |Note: This bit can be cleared by writing 1 to it. + * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only) + * | | |This bit indicates TX buffer empty or not. + * | | |0 = Tx buffer is not empty. + * | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter Shift Register. + * | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). + * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only) + * | | |This bit indicates Tx buffer full or not. + * | | |0 = Tx buffer count is less than 4. + * | | |1 = Tx buffer count equals to 4. + * |[11] |CREMOVE |Card Removal Status of SCn_CD Pin + * | | |This bit is set whenever card has been removal. + * | | |0 = No effect. + * | | |1 = Card removed. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set. + * |[12] |CINSERT |Card Insert Status of SCn_CD Pin + * | | |This bit is set whenever card has been inserted. + * | | |0 = No effect. + * | | |1 = Card insert. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set. + * |[13] |CDPINSTS |Card Detect Pin Status (Read Only) + * | | |This bit is the pin status of SCn_CD. + * | | |0 = The SCn_CD pin state at low. + * | | |1 = The SCn_CD pin state at high. + * |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only) + * | | |This field indicates the Rx buffer pointer status + * | | |When SC controller receives one byte from external device, RXPOINT increases one + * | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one. + * |[21] |RXRERR |Receiver Retry Error + * | | |This bit is used for receiver error retry and set by hardware. + * | | |0 = No Rx retry transfer. + * | | |1 = Rx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU. + * | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[22] |RXOVERR |Receiver over Retry Error + * | | |This bit is used for receiver retry counts over than retry number limitation. + * | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1. + * | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set this flag. + * |[23] |RXACT |Receiver in Active Status Flag (Read Only) + * | | |This bit indicates Rx transfer status. + * | | |0 = This bit is cleared automatically when Rx transfer is finished. + * | | |1 = This bit is set by hardware when Rx transfer is in active. + * | | |Note: This bit is read only. + * | | |Note2: + * |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only) + * | | |This field indicates the Tx buffer pointer status + * | | |When CPU writes data into SCn_DAT, TXPOINT increases one + * | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. + * |[29] |TXRERR |Transmitter Retry Error + * | | |This bit is used for indicate transmitter error retry and set by hardware.. + * | | |0 = No Tx retry transfer. + * | | |1 = Tx has any error and retries transfer. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is a flag and cannot generate any interrupt to CPU. + * |[30] |TXOVERR |Transmitter over Retry Error + * | | |This bit is used for transmitter retry counts over than retry number limitation. + * | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1. + * | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[31] |TXACT |Transmit in Active Status Flag (Read Only) + * | | |This bit indicates Tx transmit status. + * | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission has completed. + * | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP bit of the last byte has not been transmitted. + * | | |Note: This bit is read only. + * @var SC_T::PINCTL + * Offset: 0x24 SC Pin Control State Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PWREN |SCn_PWR Pin Signal + * | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level. + * | | |Write this field to drive SCn_PWR pin + * | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. + * | | |Read this field to get SCn_PWR signal status. + * | | |0 = SCn_PWR signal status is low. + * | | |1 = SCn_PWR signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically + * | | |Thus, do not fill in this field when operating in these modes. + * |[1] |RSTEN |SCn_RST Pin Signal + * | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level. + * | | |Write this field to drive SCn_RST pin. + * | | |0 = Drive SCn_RST pin to low. + * | | |1 = Drive SCn_RST pin to high. + * | | |Read this field to get SCn_RST signal status. + * | | |0 = SCn_RST signal status is low. + * | | |1 = SCn_RST signal status is high. + * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically + * | | |Thus, do not fill in this field when operating in these modes. + * |[5] |CSTOPLV |SCn_CLK Pin Stop Level + * | | |This field indicates the SCn_CLK pin status when SC clock in clock stop mode. + * | | |0 = SCn_CLK pin keeps at low when SC clock stopped. + * | | |1 = SCn_CLK pin keeps at high when SC clock stopped. + * |[6] |CLKKEEP |SC Clock Enable Bit + * | | |0 = SC clock generation Disabled. + * | | |1 = SC clock always keeps free running. + * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically + * | | |Thus, do not fill in this field when operating in these modes. + * |[9] |SCDATA |SCn_DATA Pin Signal + * | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit. + * | | |0 = Drive SCn_DATA pin to low. + * | | |1 = Drive SCn_DATA pin to high. + * | | |Read this field to get SCn_DATA signal status. + * | | |0 = SCn_DATA signal status is low. + * | | |1 = SCn_DATA signal status is high. + * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically + * | | |Thus, do not fill in this field when SC is in these modes. + * |[11] |PWRINV |SCn_PWR Pin Inverse + * | | |This bit is used for inverse the SCn_PWR pin. + * | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). + * | | |0 = SCn_PWR pin inverse Disabled + * | | |If PWREN is 1, SCn_PWR pin status is 1; if PWREN is 0, SCn_PWR pin status is 0. + * | | |1 = SCn_PWR pin inverse Enabled + * | | |If PWREN is 1, SCn_PWR pin status is 0; if PWREN is 0, SCn_PWR pin status is 1. + * | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). + * |[16] |DATASTS |SCn_DATA Pin Status (Read Only) + * | | |This bit is the pin status of SCn_DATA. + * | | |0 = The SCn_DATA pin status is low. + * | | |1 = The SCn_DATA pin status is high. + * | | |Note: + * |[17] |PWRSTS |SCn_PWR Pin Status (Read Only) + * | | |This bit is the pin status of SCn_PWR. + * | | |0 = SCn_PWR pin to low. + * | | |1 = SCn_PWR pin to high. + * |[18] |RSTSTS |SCn_RST Pin Status (Read Only) + * | | |This bit is the pin status of SCn_RST. + * | | |0 = SCn_RST pin is low. + * | | |1 = SCn_RST pin is high. + * |[30] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL0 + * Offset: 0x28 SC Internal Timer0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer0 Counter Value + * | | |This field indicates the internal Timer0 counter values. + * | | |Note: Unit of Timer0 counter is ETU base. + * |[27:24] |OPMODE |Timer0 Operation Mode Selection + * | | |This field indicates the internal 24-bit Timer0 operation selection. + * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer0. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL1 + * Offset: 0x2C SC Internal Timer1 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 1 Counter Value + * | | |This field indicates the internal Timer1 counter values. + * | | |Note: Unit of Timer1 counter is ETU base. + * |[27:24] |OPMODE |Timer 1 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer1 operation selection. + * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer1. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::TMRCTL2 + * Offset: 0x30 SC Internal Timer2 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |CNT |Timer 2 Counter Value + * | | |This field indicates the internal Timer2 counter values. + * | | |Note: Unit of Timer2 counter is ETU base. + * |[27:24] |OPMODE |Timer 2 Operation Mode Selection + * | | |This field indicates the internal 8-bit Timer2 operation selection + * | | |Refer to Table 6.17-3 Timer0/Timer1/Timer2 Operation Mode for programming Timer2. + * |[31] |SYNC |SYNC Flag Indicator (Read Only) + * | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. + * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register. + * | | |1 = Last value is synchronizing. + * @var SC_T::UARTCTL + * Offset: 0x34 SC UART Mode Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |UARTEN |UART Mode Enable Bit + * | | |Sets this bit to enable UART mode function. + * | | |0 = Smart Card mode. + * | | |1 = UART mode. + * | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0. + * | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0. + * | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. + * |[5:4] |WLS |Word Length Selection + * | | |This field is used for select UART data length. + * | | |00 = Word length is 8 bits. + * | | |01 = Word length is 7 bits. + * | | |10 = Word length is 6 bits. + * | | |11 = Word length is 5 bits. + * | | |Note: In smart card mode, this WLS must be u201800'. + * |[6] |PBOFF |Parity Bit Disable Control + * | | |Sets this bit is used for disable parity check function. + * | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data. + * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. + * | | |Note: In smart card mode, this field must be u20180' (default setting is with parity bit). + * |[7] |OPE |Odd Parity Enable Bit + * | | |This is used for odd/even parity selection. + * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. + * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. + * | | |Note: This bit has effect only when PBOFF bit is u20180'. + * @var SC_T::ACTCTL + * Offset: 0x4C SC Activation Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |T1EXT |T1 Extend Time of Hardware Activation + * | | |This field provide the configurable cycles to extend the activation time T1 period. + * | | |The cycle scaling factor is 2048. + * | | |Extend cycles = (filled value * 2048) cycles. + * | | |Refer to SC activation sequence in Figure 6.17-4 SC Activation Sequence. + * | | |For example, + * | | |SCLK = 4MHz, each cycle = 0.25us,. + * | | |Filled 20 to this field + * | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms. + * | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 + */ + __IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */ + __IO uint32_t CTL; /*!< [0x0004] SC Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */ + __IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */ + __IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */ + __IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */ + __IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */ + __IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */ + __IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */ + __IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */ + __IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */ + __IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */ + __IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */ + __IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */ + __I uint32_t RESERVE0[5]; + __IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */ + +} SC_T; + +/** + @addtogroup SC_CONST SC Bit Field Definition + Constant Definitions for SC Controller + @{ +*/ + +#define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */ +#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */ + +#define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */ +#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */ + +#define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */ +#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */ + +#define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */ +#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */ + +#define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */ +#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */ + +#define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */ +#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */ + +#define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */ +#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */ + +#define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */ +#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */ + +#define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */ +#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */ + +#define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */ +#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */ + +#define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */ +#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */ + +#define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */ +#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */ + +#define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */ +#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */ + +#define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */ +#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */ + +#define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */ +#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */ + +#define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */ +#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */ + +#define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */ +#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */ + +#define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */ +#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */ + +#define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */ +#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */ + +#define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */ +#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */ + +#define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */ +#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */ + +#define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */ +#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */ + +#define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */ +#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */ + +#define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */ +#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */ + +#define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */ +#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */ + +#define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */ +#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */ + +#define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */ +#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */ + +#define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */ +#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */ + +#define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */ +#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */ + +#define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */ +#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */ + +#define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */ +#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */ + +#define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */ +#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */ + +#define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */ +#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */ + +#define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */ +#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */ + +#define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */ +#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */ + +#define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */ +#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */ + +#define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */ +#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */ + +#define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */ +#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */ + +#define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */ +#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */ + +#define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */ +#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */ + +#define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */ +#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */ + +#define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */ +#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */ + +#define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */ +#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */ + +#define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */ +#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */ + +#define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */ +#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */ + +#define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */ +#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */ + +#define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */ +#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */ + +#define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */ +#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */ + +#define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */ +#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */ + +#define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */ +#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */ + +#define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */ +#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */ + +#define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */ +#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */ + +#define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */ +#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */ + +#define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */ +#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */ + +#define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */ +#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */ + +#define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */ +#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */ + +#define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */ +#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */ + +#define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */ +#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */ + +#define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */ +#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */ + +#define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */ +#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */ + +#define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */ +#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */ + +#define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */ +#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */ + +#define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */ +#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */ + +#define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */ +#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */ + +#define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */ +#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */ + +#define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */ +#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */ + +#define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */ +#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */ + +#define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */ +#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */ + +#define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */ +#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */ + +#define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */ +#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */ + +#define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */ +#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */ + +#define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */ +#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */ + +#define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */ +#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */ + +#define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */ +#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */ + +#define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */ +#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */ + +#define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */ +#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */ + +#define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */ +#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */ + +#define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */ +#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */ + +#define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */ +#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */ + +#define SC_PINCTL_CSTOPLV_Pos (5) /*!< SC_T::PINCTL: CSTOPLV Position */ +#define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos) /*!< SC_T::PINCTL: CSTOPLV Mask */ + +#define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */ +#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */ + +#define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */ +#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */ + +#define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */ +#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */ + +#define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */ +#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */ + +#define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */ +#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */ + +#define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */ +#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */ + +#define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */ +#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */ + +#define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */ +#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */ + +#define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */ +#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */ + +#define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */ +#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */ + +#define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */ +#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */ + +#define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */ +#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */ + +#define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */ +#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */ + +#define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */ +#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */ + +#define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */ +#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */ + +#define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */ +#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */ + +#define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */ +#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */ + +#define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */ +#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */ + +#define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */ +#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */ + +#define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */ +#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */ + +#define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */ +#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */ + +/**@}*/ /* SC_CONST */ +/**@}*/ /* end of SC register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __SC_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/scu_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/scu_reg.h new file mode 100644 index 0000000000..d4d6bfc5da --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/scu_reg.h @@ -0,0 +1,2727 @@ +/**************************************************************************//** + * @file scu_reg.h + * @version V1.00 + * @brief SCU register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SCU_REG_H__ +#define __SCU_REG_H__ + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Booting Flag -------------------------*/ +/** + @addtogroup BTF Booting Flag + Memory Mapped Structure for BTF Controller + @{ +*/ + +typedef struct +{ + + +/** + * @var BTF_T::BTF + * Offset: 0x00 Booting Flag Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BL2 |BL2 Flag + * | | |Indicating the CPU is running at BL2 + */ + __IO uint32_t BTF; /*!< [0x0000] Booting Flag Register */ + +} BTF_T; + +/** + @addtogroup BTF_CONST BTF Bit Field Definition + Constant Definitions for BTF Controller + @{ +*/ + +#define BTF_BTF_BL2_Pos (0) /*!< BTF_T::BTF: BL2 Position */ +#define BTF_BTF_BL2_Msk (0x1ul << BTF_BTF_BL2_Pos) /*!< BTF_T::BTF: BL2 Mask */ + +/**@}*/ /* BTF_CONST */ +/**@}*/ /* end of BTF register group */ + + +/*---------------------- Debug Protection Mechanism -------------------------*/ +/** + @addtogroup DPM Debug Protection Mechanism(DPM) + Memory Mapped Structure for DPM Controller + @{ +*/ + +typedef struct +{ + + +/** + * @var DPM_T::CTL + * Offset: 0x00 Secure DPM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DBGDIS |Set Secure DPM Debug Disable Bit + * | | |When this bit is read as zero, it can be write to one to configure the Secure DPM DBGDIS bit (DBGDISS). + * | | |When write: + * | | |0 = No operation. + * | | |1 = Trigger the process to set DBGDISS configuration bit. + * | | |Note: This bit can be set to 1 but cannot be cleared to 0. + * |[1] |LOCK |Set Secure DPM Debug Lock Bit + * | | |When this bit is read as zero, it can be write to one to configure the Secure DPM LOCK bit (LOCKS). + * | | |When write: + * | | |0 = No operation. + * | | |1 = Trigger the process to set LOCKS configuration bit. + * | | |Note: This bit can be set to 1 but cannot be cleared to 0. + * |[2] |PWCMP |Secure DPM Password Compare Bit + * | | |Set to enter the process of compare Secure DPM password. + * | | |0 = No operation. + * | | |1 = Compare Secure DPM password. + * | | |Note: This bit will be cleared after the comparison process is finished. + * |[3] |PWUPD |Secure DPM Password Update Bit + * | | |Set to enter the process of updating Secure DPM password. + * | | |0 = No operation. + * | | |1 = Update Secure DPM password. + * | | |Note 1: This bit should be set with PWCMP equal to 0. + * | | |Note 2: This bit will be cleared after the update process is finished. + * |[8] |INTEN |DPM Interrupt Enable Bit + * | | |0 = DPM interrupt function Enabled. + * | | |1 = DPM interrupt function Disabled. + * |[12] |DACCWDIS |Secure DPM Debug Write Access Disable Bit + * | | |This bit disables the writability of external debugger to Secure DPM registers for debug authentication. + * | | |0 = External debugger can write Secure DPM registers. + * | | |1 = External debugger cannot write Secure DPM registers. + * |[13] |DACCDIS |Debug Access Disable Bit + * | | |This bit disables the accessibility of external debugger to all DPM registers. + * | | |0 = External debugger can read/write DPM registers. + * | | |1 = External debugger cannot read/write DPM registers. + * |[31:24] |WVCODE |Write Verify Code and Read Verify Code + * | |RVCODE |Read operation: + * | | |0xA5 = The read access for DPM_CTL is correct. + * | | |Others = The read access for DPM_CTL is incorrect. + * | | |Write operation: + * | | |0x5A = The write verify code, 0x5A, is needed to do a valid write to DPM_CTL. + * | | |Others = Invalid write verify code. + * @var DPM_T::STS + * Offset: 0x04 Secure DPM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |DPM Busy Flag (Read Only) + * | | |This bit indicates the DPM is busy. + * | | |0 = DPM is not busy and writing to any register is accepted. + * | | |1 = DPM is busy and other bits in DPM_STS register are not valid and writing to any register is ignored. + * |[1] |INT |DPM Interrupt Flag (Read Only) + * | | |This bit indicates the interrupt is triggered. + * | | |0 = Interrupt is not enabled or no password comparison flag is set. + * | | |1 = Interrupt is enabled and PWCERR flag in either DPM_STS or DPM_NSSTS register is not cleared. + * | | |Note: This bit is cleared automatically when PWCERR flag in both DPM_STS and DPM_NSSTS are zero. + * |[4] |PWCERR |Secure DPM Password Compared Error Flag + * | | |This bit indicates the result of Secure DPM password comparison. + * | | |When read: + * | | |0 = The result of Secure DPM password is correct. + * | | |1 = The result of Seucre DPM password is incorrect. + * | | |Note: This flag is write-one-clear. + * |[5] |PWUOK |Secure DPM Password Updated Flag + * | | |This bit indicates Secure DPM password has been updated successfully. + * | | |When read: + * | | |0 = No successful updating process has happened. + * | | |1 = There is at least one successful updating process since last clearing of this bit. + * | | |Note: This flag is write-one-clear. + * |[6] |PWFMAX |Secure DPM Password Fail Times Maximum Reached Flag (Read Only) + * | | |This bit indicates if the fail times of comparing Secure DPM password reached max times. + * | | |0 = Max time has not reached and Secure DPM password comparison can be triggered. + * | | |1 = Max time reached and Secure DPM password comparison cannot be processed anymore. + * |[10:8] |PWUCNT |Secure DPM Password Updated Times (Read Only) + * | | |This bit indicates how many times of secure password has been updated. + * | | |The max value is 7. If PWUCNT reached the max value, Secure DPM password cannot be updated anymore. + * |[16] |DBGDIS |Secure Debug Disable Flag (Read Only) + * | | |This bit indicates the current value of Secure DPM DBGDIS bit (DBGDISS). + * | | |{PWOK, LOCK, DBGDIS} bits define the current state of DPM. + * | | |x00 = DEFAULT state. + * | | |x1x = LOCKED state. + * | | |001 = CLOSE state. + * | | |101 = OPEN state. + * | | |Others = Unknown. + * |[17] |LOCK |Secure Debug Lock Flag (Read Only) + * | | |This bit indicates the current value of Secure DPM LOCK bit (LOCKS). + * |[18] |PWOK |Secure Password OK Flag (Read Only) + * | | |This bit indicates the Secure DPM password has been checked and is correct. + * | | |0 = The Secure DPM password has not been checked pass, yet. + * | | |1 = The Secure DPM password has been checked pass since last cold reset. + * @var DPM_T::SPW + * Offset: 0x10 Secure DPM Password 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[31:0] to this register to update or compare Secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + * Offset: 0x14 Secure DPM Password 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[63:32] to this register to update or compare Secure DPM password + * | | |It is write-only and always read as 0xFFFFFFFF. + * Offset: 0x18 Secure DPM Password 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[95:64] to this register to update or compare Secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + * Offset: 0x1C Secure DPM Password 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[127:96] to this register to update or compare Secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + * @var DPM_T::NSCTL + * Offset: 0x50 Non-secure DPM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DBGDIS |Set Non-secure DPM Debug Disable Bit + * | | |When this bit is read as zero, it can be write to one to configure the Non-secure DPM DBGDIS bit (DBGDISNS). + * | | |When write: + * | | |0 = No operation. + * | | |1 = Trigger the process to set DBGDISNS configuration bit. + * | | |Note: This bit can be set to 1 but cannot be cleared to 0. + * |[1] |LOCK |Set Non-secure DPM Debug Lock Bit + * | | |When this bit is read as zero, it can be write to one to configure the Non-secure DPM LOCK bit (LOCKNS). + * | | |When write: + * | | |0 = No operation. + * | | |1 = Trigger the process to set LOCKNS configuration bit. + * | | |Note: This bit can be set to 1 but cannot be cleared to 0. + * |[2] |PWCMP |Non-secure DPM Password Compare Bit + * | | |Set to enter the process of compare Non-secure DPM password. + * | | |0 = No operation. + * | | |1 = Compare Non-secure DPM password. + * | | |Note: This bit will be cleared after the comparison process is finished. + * |[3] |PWUPD |Non-secure DPM Password Update Bit + * | | |Set to enter the process of updating Non-secure DPM password. + * | | |0 = No operation. + * | | |1 = Update Non-secure DPM password. + * | | |Note 1: This bit should be set with PWCMP equal to 0. + * | | |Note 2: This bit will be cleared after the update process is finished. + * |[12] |DACCWDIS |Debug Write Access Disable Bit + * | | |This bit disables the writability of external debugger to Non-secure DPM registers for debug authentication. + * | | |0 = External debugger can write Non-secure DPM registers. + * | | |1 = External debugger cannot write Non-secure DPM registers. + * |[31:24] |WVCODE |Write Verify Code and Read Verify Code + * | |RVCODE |Read operation: + * | | |0xA5 = The read access for DPM_NSCTL is correct. + * | | |Others = The read access for DPM_NSCTL is incorrect. + * | | |Write operation: + * | | |0x5A = The write verify code, 0x5A, is needed to do a valid write to DPM_NSCTL. + * | | |Others = Invalid write verify code. + * @var DPM_T::NSSTS + * Offset: 0x54 Non-secure DPM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |DPM Busy Flag (Read Only) + * | | |This bit indicates the DPM is busy. + * | | |0 = DPM is not busy and writing to any register is accepted. + * | | |1 = DPM is busy and other bits in DPM_NSSTS register are not valid and writing to any register is ignored. + * |[4] |PWCERR |Non-secure DPM Password Compared Error Flag + * | | |This bit indicates the result of Non-secure DPM password comparison. + * | | |0 = The result of Non-secure DPM password is correct. + * | | |1 = The result of Non-seucre DPM password is incorrect. + * | | |Note: This flag is write-one-clear. + * |[5] |PWUOK |Non-secure DPM Password Updated Flag + * | | |This bit indicates Non-secure DPM password has been updated correctly. + * | | |When read: + * | | |0 = No successful updating process has happened. + * | | |1 = There is at least one successful updating process since last clearing of this bit. + * | | |Note: This flag is write-one-clear. + * |[6] |PWFMAX |Non-secure DPM Password Fail Times Maximum Reached Flag (Read Only) + * | | |This bit indicates if the fail times of comparing Non-secure DPM password reached max times. + * | | |0 = Max time has not reached and Non-secure DPM password comparison can be triggered. + * | | |1 = Max time reached and Non-secure DPM password comparison cannot be processed anymore. + * |[10:8] |PWUCNT |Non-secure DPM Password Updated Times (Read Only) + * | | |This bit indicates how many times of non-secure password has been updated. + * | | |The max value is 7. If PWUCNT reached the max value, Non-secure DPM password cannot be updated anymore. + * |[16] |DBGDIS |Non-secure Debug Disable Flag (Read Only) + * | | |This bit indicates the current value of of Non-secure DPM DBGDIS bit (DBGDISNS). + * | | |{PWOK, LOCK, DBGDIS} bits define the current state of DPM. + * | | |x00 = DEFAULT state. + * | | |x1x = LOCKED state. + * | | |001 = CLOSE state. + * | | |101 = OPEN state. + * | | |Others = Unknown. + * |[17] |LOCK |Non-secure Debug Lock Flag (Read Only) + * | | |This bit indicates the current value of Non-secure DPM DBGDIS bit (LOCKNS). + * |[18] |PWOK |Non-secure Password OK Flag (Read Only) + * | | |This bit indicates the Non-secure DPM password has been checked and is correct. + * | | |0 = The Non-secure DPM password has not been checked pass, yet. + * | | |1 = The Non-secure DPM password has been checked pass since last cold reset. + * @var DPM_T::NSPW + * Offset: 0x60 Non-secure DPM Password 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[31:0] to this register to update or compare Non-secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + * Offset: 0x64 Non-secure DPM Password 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[63:32] to this register to update or compare Non-secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + * Offset: 0x68 Non-secure DPM Password 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[95:64] to this register to update or compare Non-secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + * Offset: 0x6C Non-secure DPM Password 3 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PW |Password + * | | |Write password[127:96] to this register to update or compare Non-secure DPM password. + * | | |It is write-only and always read as 0xFFFFFFFF. + */ + __IO uint32_t CTL; /*!< [0x0000] Secure DPM Control Register */ + __IO uint32_t STS; /*!< [0x0004] Secure DPM Status Register */ + __I uint32_t RESERVE0[2]; + __O uint32_t SPW[4]; /*!< [0x0010/0x0014/0x0018/0x001c] Secure DPM Password 0/1/2/3 */ + __I uint32_t RESERVE1[12]; + __IO uint32_t NSCTL; /*!< [0x0050] Non-secure DPM Control Register */ + __IO uint32_t NSSTS; /*!< [0x0054] Non-secure DPM Status Register */ + __I uint32_t RESERVE2[2]; + __O uint32_t NSPW[4]; /*!< [0x00600/0x0064/0x0068/0x006c] Non-secure DPM Password 0/1/2/3 */ + + +} DPM_T; + +/** + @addtogroup DPM_CONST DPM Bit Field Definition + Constant Definitions for DPM Controller + @{ +*/ + +#define DPM_CTL_DBGDIS_Pos (0) /*!< DPM_T::CTL: DBGDIS Position */ +#define DPM_CTL_DBGDIS_Msk (0x1ul << DPM_CTL_DBGDIS_Pos) /*!< DPM_T::CTL: DBGDIS Mask */ + +#define DPM_CTL_LOCK_Pos (1) /*!< DPM_T::CTL: LOCK Position */ +#define DPM_CTL_LOCK_Msk (0x1ul << DPM_CTL_LOCK_Pos) /*!< DPM_T::CTL: LOCK Mask */ + +#define DPM_CTL_PWCMP_Pos (2) /*!< DPM_T::CTL: PWCMP Position */ +#define DPM_CTL_PWCMP_Msk (0x1ul << DPM_CTL_PWCMP_Pos) /*!< DPM_T::CTL: PWCMP Mask */ + +#define DPM_CTL_PWUPD_Pos (3) /*!< DPM_T::CTL: PWUPD Position */ +#define DPM_CTL_PWUPD_Msk (0x1ul << DPM_CTL_PWUPD_Pos) /*!< DPM_T::CTL: PWUPD Mask */ + +#define DPM_CTL_INTEN_Pos (8) /*!< DPM_T::CTL: INTEN Position */ +#define DPM_CTL_INTEN_Msk (0x1ul << DPM_CTL_INTEN_Pos) /*!< DPM_T::CTL: INTEN Mask */ + +#define DPM_CTL_DACCWDIS_Pos (12) /*!< DPM_T::CTL: DACCWDIS Position */ +#define DPM_CTL_DACCWDIS_Msk (0x1ul << DPM_CTL_DACCWDIS_Pos) /*!< DPM_T::CTL: DACCWDIS Mask */ + +#define DPM_CTL_DACCDIS_Pos (13) /*!< DPM_T::CTL: DACCDIS Position */ +#define DPM_CTL_DACCDIS_Msk (0x1ul << DPM_CTL_DACCDIS_Pos) /*!< DPM_T::CTL: DACCDIS Mask */ + +#define DPM_CTL_WVCODE_Pos (24) /*!< DPM_T::CTL: WVCODE Position */ +#define DPM_CTL_WVCODE_Msk (0xfful << DPM_CTL_WVCODE_Pos) /*!< DPM_T::CTL: WVCODE Mask */ + +#define DPM_CTL_RVCODE_Pos (24) /*!< DPM_T::CTL: RVCODE Position */ +#define DPM_CTL_RVCODE_Msk (0xfful << DPM_CTL_RVCODE_Pos) /*!< DPM_T::CTL: RVCODE Mask */ + +#define DPM_STS_BUSY_Pos (0) /*!< DPM_T::STS: BUSY Position */ +#define DPM_STS_BUSY_Msk (0x1ul << DPM_STS_BUSY_Pos) /*!< DPM_T::STS: BUSY Mask */ + +#define DPM_STS_INT_Pos (1) /*!< DPM_T::STS: INT Position */ +#define DPM_STS_INT_Msk (0x1ul << DPM_STS_INT_Pos) /*!< DPM_T::STS: INT Mask */ + +#define DPM_STS_PWCERR_Pos (4) /*!< DPM_T::STS: PWCERR Position */ +#define DPM_STS_PWCERR_Msk (0x1ul << DPM_STS_PWCERR_Pos) /*!< DPM_T::STS: PWCERR Mask */ + +#define DPM_STS_PWUOK_Pos (5) /*!< DPM_T::STS: PWUOK Position */ +#define DPM_STS_PWUOK_Msk (0x1ul << DPM_STS_PWUOK_Pos) /*!< DPM_T::STS: PWUOK Mask */ + +#define DPM_STS_PWFMAX_Pos (6) /*!< DPM_T::STS: PWFMAX Position */ +#define DPM_STS_PWFMAX_Msk (0x1ul << DPM_STS_PWFMAX_Pos) /*!< DPM_T::STS: PWFMAX Mask */ + +#define DPM_STS_PWUCNT_Pos (8) /*!< DPM_T::STS: PWUCNT Position */ +#define DPM_STS_PWUCNT_Msk (0x7ul << DPM_STS_PWUCNT_Pos) /*!< DPM_T::STS: PWUCNT Mask */ + +#define DPM_STS_DBGDIS_Pos (16) /*!< DPM_T::STS: DBGDIS Position */ +#define DPM_STS_DBGDIS_Msk (0x1ul << DPM_STS_DBGDIS_Pos) /*!< DPM_T::STS: DBGDIS Mask */ + +#define DPM_STS_LOCK_Pos (17) /*!< DPM_T::STS: LOCK Position */ +#define DPM_STS_LOCK_Msk (0x1ul << DPM_STS_LOCK_Pos) /*!< DPM_T::STS: LOCK Mask */ + +#define DPM_STS_PWOK_Pos (18) /*!< DPM_T::STS: PWOK Position */ +#define DPM_STS_PWOK_Msk (0x1ul << DPM_STS_PWOK_Pos) /*!< DPM_T::STS: PWOK Mask */ + +#define DPM_SPW0_PW_Pos (0) /*!< DPM_T::SPW0: PW Position */ +#define DPM_SPW0_PW_Msk (0xfffffffful << DPM_SPW0_PW_Pos) /*!< DPM_T::SPW0: PW Mask */ + +#define DPM_SPW1_PW_Pos (0) /*!< DPM_T::SPW1: PW Position */ +#define DPM_SPW1_PW_Msk (0xfffffffful << DPM_SPW1_PW_Pos) /*!< DPM_T::SPW1: PW Mask */ + +#define DPM_SPW2_PW_Pos (0) /*!< DPM_T::SPW2: PW Position */ +#define DPM_SPW2_PW_Msk (0xfffffffful << DPM_SPW2_PW_Pos) /*!< DPM_T::SPW2: PW Mask */ + +#define DPM_SPW3_PW_Pos (0) /*!< DPM_T::SPW3: PW Position */ +#define DPM_SPW3_PW_Msk (0xfffffffful << DPM_SPW3_PW_Pos) /*!< DPM_T::SPW3: PW Mask */ + +#define DPM_NSCTL_DBGDIS_Pos (0) /*!< DPM_T::NSCTL: DBGDIS Position */ +#define DPM_NSCTL_DBGDIS_Msk (0x1ul << DPM_NSCTL_DBGDIS_Pos) /*!< DPM_T::NSCTL: DBGDIS Mask */ + +#define DPM_NSCTL_LOCK_Pos (1) /*!< DPM_T::NSCTL: LOCK Position */ +#define DPM_NSCTL_LOCK_Msk (0x1ul << DPM_NSCTL_LOCK_Pos) /*!< DPM_T::NSCTL: LOCK Mask */ + +#define DPM_NSCTL_PWCMP_Pos (2) /*!< DPM_T::NSCTL: PWCMP Position */ +#define DPM_NSCTL_PWCMP_Msk (0x1ul << DPM_NSCTL_PWCMP_Pos) /*!< DPM_T::NSCTL: PWCMP Mask */ + +#define DPM_NSCTL_PWUPD_Pos (3) /*!< DPM_T::NSCTL: PWUPD Position */ +#define DPM_NSCTL_PWUPD_Msk (0x1ul << DPM_NSCTL_PWUPD_Pos) /*!< DPM_T::NSCTL: PWUPD Mask */ + +#define DPM_NSCTL_DACCWDIS_Pos (12) /*!< DPM_T::NSCTL: DACCWDIS Position */ +#define DPM_NSCTL_DACCWDIS_Msk (0x1ul << DPM_NSCTL_DACCWDIS_Pos) /*!< DPM_T::NSCTL: DACCWDIS Mask */ + +#define DPM_NSCTL_WVCODE_Pos (24) /*!< DPM_T::NSCTL: WVCODE Position */ +#define DPM_NSCTL_WVCODE_Msk (0xfful << DPM_NSCTL_WVCODE_Pos) /*!< DPM_T::NSCTL: WVCODE Mask */ + +#define DPM_NSCTL_RVCODE_Pos (24) /*!< DPM_T::NSCTL: RVCODE Position */ +#define DPM_NSCTL_RVCODE_Msk (0xfful << DPM_NSCTL_RVCODE_Pos) /*!< DPM_T::NSCTL: RVCODE Mask */ + +#define DPM_NSSTS_BUSY_Pos (0) /*!< DPM_T::NSSTS: BUSY Position */ +#define DPM_NSSTS_BUSY_Msk (0x1ul << DPM_NSSTS_BUSY_Pos) /*!< DPM_T::NSSTS: BUSY Mask */ + +#define DPM_NSSTS_PWCERR_Pos (4) /*!< DPM_T::NSSTS: PWCERR Position */ +#define DPM_NSSTS_PWCERR_Msk (0x1ul << DPM_NSSTS_PWCERR_Pos) /*!< DPM_T::NSSTS: PWCERR Mask */ + +#define DPM_NSSTS_PWUOK_Pos (5) /*!< DPM_T::NSSTS: PWUOK Position */ +#define DPM_NSSTS_PWUOK_Msk (0x1ul << DPM_NSSTS_PWUOK_Pos) /*!< DPM_T::NSSTS: PWUOK Mask */ + +#define DPM_NSSTS_PWFMAX_Pos (6) /*!< DPM_T::NSSTS: PWFMAX Position */ +#define DPM_NSSTS_PWFMAX_Msk (0x1ul << DPM_NSSTS_PWFMAX_Pos) /*!< DPM_T::NSSTS: PWFMAX Mask */ + +#define DPM_NSSTS_PWUCNT_Pos (8) /*!< DPM_T::NSSTS: PWUCNT Position */ +#define DPM_NSSTS_PWUCNT_Msk (0x7ul << DPM_NSSTS_PWUCNT_Pos) /*!< DPM_T::NSSTS: PWUCNT Mask */ + +#define DPM_NSSTS_DBGDIS_Pos (16) /*!< DPM_T::NSSTS: DBGDIS Position */ +#define DPM_NSSTS_DBGDIS_Msk (0x1ul << DPM_NSSTS_DBGDIS_Pos) /*!< DPM_T::NSSTS: DBGDIS Mask */ + +#define DPM_NSSTS_LOCK_Pos (17) /*!< DPM_T::NSSTS: LOCK Position */ +#define DPM_NSSTS_LOCK_Msk (0x1ul << DPM_NSSTS_LOCK_Pos) /*!< DPM_T::NSSTS: LOCK Mask */ + +#define DPM_NSSTS_PWOK_Pos (18) /*!< DPM_T::NSSTS: PWOK Position */ +#define DPM_NSSTS_PWOK_Msk (0x1ul << DPM_NSSTS_PWOK_Pos) /*!< DPM_T::NSSTS: PWOK Mask */ + +#define DPM_NSPW0_PW_Pos (0) /*!< DPM_T::NSPW0: PW Position */ +#define DPM_NSPW0_PW_Msk (0xfffffffful << DPM_NSPW0_PW_Pos) /*!< DPM_T::NSPW0: PW Mask */ + +#define DPM_NSPW1_PW_Pos (0) /*!< DPM_T::NSPW1: PW Position */ +#define DPM_NSPW1_PW_Msk (0xfffffffful << DPM_NSPW1_PW_Pos) /*!< DPM_T::NSPW1: PW Mask */ + +#define DPM_NSPW2_PW_Pos (0) /*!< DPM_T::NSPW2: PW Position */ +#define DPM_NSPW2_PW_Msk (0xfffffffful << DPM_NSPW2_PW_Pos) /*!< DPM_T::NSPW2: PW Mask */ + +#define DPM_NSPW3_PW_Pos (0) /*!< DPM_T::NSPW3: PW Position */ +#define DPM_NSPW3_PW_Msk (0xfffffffful << DPM_NSPW3_PW_Pos) /*!< DPM_T::NSPW3: PW Mask */ + + +/**@}*/ /* DPM_CONST */ +/**@}*/ /* end of DPM register group */ + + + +/*---------------------- Firmware Version Counter -------------------------*/ +/** + @addtogroup FVC Firmware Version Counter(FVC) + Memory Mapped Structure for FVC Controller + @{ +*/ + +typedef struct +{ + + +/** + * @var FVC_T::CTL + * Offset: 0x00 FVC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INIT |FVC Init Bit + * | | |Set to 1 to enable FVC + * | | |This bit is writable when FVC is at Reset state. + * | | |Note: After set to one, this bit is cleared to zero automatically when FVC is back to Reset state. + * |[1] |MONOEN |Monotonic Enable Bit + * | | |Set to 1 to enable the monotonic mechanism of FVC. + * | | |Note: This bit can be set to one but cannot be cleared to zero. + * |[31:16] |WVCODE |Verification Code + * | | |When write, VERIFY must be 0x7710 + * @var FVC_T::STS + * Offset: 0x04 FVC Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |FVC Busy Bit + * | | |Indicates the FVC is at busy state. + * |[1] |RDY |FVC Ready Bit + * | | |Indicates the FVC is ready after the initial process. + * @var FVC_T::BL2 + * Offset: 0x10 BL2 Firmware Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FW_VERSION|Firmware Version + * | | |Read: Indicate the current firmware version of BL2. + * | | |Write: Update the firmware version of BL2. + * | | |The maximum value is 63. + * | | |Indicating number of 1 in Fuse OTP or number of 0 in Flash + * |[31:16] |WVCODE_RVCODE|Verification Code + * | | |When write, VERIFY must be current firmware version number + * @var FVC_T::BL32 + * Offset: 0x14 BL32 Firmware Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FW_VERSION|Firmware Version + * | | |Read: Indicate the current firmware version of BL32. + * | | |Write: Update the firmware version of BL32. + * | | |The maximum value is 63. + * | | |Indicating number of 1 in Fuse OTP or number of 0 in Flash + * |[31:16] |WVCODE_RVCODE|Verification Code + * | | |When write, VERIFY must be current firmware version number + * @var FVC_T::BL33 + * Offset: 0x20 BL33 Firmware Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FW_VERSION|Firmware Version + * | | |Read: Indicate the current firmware version of BL33. + * | | |Write: Update the firmware version of BL33. + * | | |The maximum value is 255. + * | | |Indicating number of 1 in Fuse OTP or number of 0 in Flash + * |[31:16] |WVCODE_RVCODE|Verification Code + * | | |When write, VERIFY must be current firmware version number + * @var FVC_T::UDF + * Offset: 0x24 User-defined Firmware Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FW_VERSION|Firmware Version + * | | |Read: Indicate the current firmware version of useru2019s firmware. + * | | |Write: Update the firmware version of useru2019s firmware. + * | | |The maximum value is 255. + * | | |Indicating number of 1 in Fuse OTP or number of 0 in Flash + * |[31:16] |WVCODE_RVCODE|Verification Code + * | | |When write, VERIFY must be current firmware version number + */ + __IO uint32_t CTL; /*!< [0x0000] FVC Control Register */ + __I uint32_t STS; /*!< [0x0004] FVC Status Register */ + __I uint32_t RESERVE0[2]; + __IO uint32_t BL2; /*!< [0x0010] BL2 Firmware Control Register */ + __IO uint32_t BL32; /*!< [0x0014] BL32 Firmware Control Register */ + __I uint32_t RESERVE1[2]; + __IO uint32_t BL33; /*!< [0x0020] BL33 Firmware Control Register */ + __IO uint32_t UDF; /*!< [0x0024] User-defined Firmware Control Register */ + +} FVC_T; + +/** + @addtogroup FVC_CONST FVC Bit Field Definition + Constant Definitions for FVC Controller + @{ +*/ + +#define FVC_CTL_INIT_Pos (0) /*!< FVC_T::CTL: INIT Position */ +#define FVC_CTL_INIT_Msk (0x1ul << FVC_CTL_INIT_Pos) /*!< FVC_T::CTL: INIT Mask */ + +#define FVC_CTL_MONOEN_Pos (1) /*!< FVC_T::CTL: MONOEN Position */ +#define FVC_CTL_MONOEN_Msk (0x1ul << FVC_CTL_MONOEN_Pos) /*!< FVC_T::CTL: MONOEN Mask */ + +#define FVC_CTL_WVCODE_Pos (16) /*!< FVC_T::CTL: WVCODE Position */ +#define FVC_CTL_WVCODE_Msk (0xfffful << FVC_CTL_WVCODE_Pos) /*!< FVC_T::CTL: WVCODE Mask */ + +#define FVC_STS_BUSY_Pos (0) /*!< FVC_T::STS: BUSY Position */ +#define FVC_STS_BUSY_Msk (0x1ul << FVC_STS_BUSY_Pos) /*!< FVC_T::STS: BUSY Mask */ + +#define FVC_STS_RDY_Pos (1) /*!< FVC_T::STS: RDY Position */ +#define FVC_STS_RDY_Msk (0x1ul << FVC_STS_RDY_Pos) /*!< FVC_T::STS: RDY Mask */ + +#define FVC_BL2_FW_VERSION_Pos (0) /*!< FVC_T::BL2: FW_VERSION Position */ +#define FVC_BL2_FW_VERSION_Msk (0xfffful << FVC_BL2_FW_VERSION_Pos) /*!< FVC_T::BL2: FW_VERSION Mask */ + +#define FVC_BL2_WVCODE_RVCODE_Pos (16) /*!< FVC_T::BL2: WVCODE_RVCODE Position */ +#define FVC_BL2_WVCODE_RVCODE_Msk (0xfffful << FVC_BL2_WVCODE_RVCODE_Pos) /*!< FVC_T::BL2: WVCODE_RVCODE Mask */ + +#define FVC_BL32_FW_VERSION_Pos (0) /*!< FVC_T::BL32: FW_VERSION Position */ +#define FVC_BL32_FW_VERSION_Msk (0xfffful << FVC_BL32_FW_VERSION_Pos) /*!< FVC_T::BL32: FW_VERSION Mask */ + +#define FVC_BL32_WVCODE_RVCODE_Pos (16) /*!< FVC_T::BL32: WVCODE_RVCODE Position */ +#define FVC_BL32_WVCODE_RVCODE_Msk (0xfffful << FVC_BL32_WVCODE_RVCODE_Pos) /*!< FVC_T::BL32: WVCODE_RVCODE Mask */ + +#define FVC_BL33_FW_VERSION_Pos (0) /*!< FVC_T::BL33: FW_VERSION Position */ +#define FVC_BL33_FW_VERSION_Msk (0xfffful << FVC_BL33_FW_VERSION_Pos) /*!< FVC_T::BL33: FW_VERSION Mask */ + +#define FVC_BL33_WVCODE_RVCODE_Pos (16) /*!< FVC_T::BL33: WVCODE_RVCODE Position */ +#define FVC_BL33_WVCODE_RVCODE_Msk (0xfffful << FVC_BL33_WVCODE_RVCODE_Pos) /*!< FVC_T::BL33: WVCODE_RVCODE Mask */ + +#define FVC_UDF_FW_VERSION_Pos (0) /*!< FVC_T::UDF: FW_VERSION Position */ +#define FVC_UDF_FW_VERSION_Msk (0xfffful << FVC_UDF_FW_VERSION_Pos) /*!< FVC_T::UDF: FW_VERSION Mask */ + +#define FVC_UDF_WVCODE_RVCODE_Pos (16) /*!< FVC_T::UDF: WVCODE_RVCODE Position */ +#define FVC_UDF_WVCODE_RVCODE_Msk (0xfffful << FVC_UDF_WVCODE_RVCODE_Pos) /*!< FVC_T::UDF: WVCODE_RVCODE Mask */ + +/**@}*/ /* FVC_CONST */ +/**@}*/ /* end of FVC register group */ + + +/*---------------------- Product Life-cycle Manager -------------------------*/ +/** + @addtogroup PLM Product Life-cycle Manager(PLM) + Memory Mapped Structure for PLM Controller + @{ +*/ + +typedef struct +{ + + +/** + * @var PLM_T::CTL + * Offset: 0x00 Product Life-cycle Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |STAGE |Life-cycle Stage Update Bits + * | | |Bits to update PLM stage. All bits can be set to one but cannot be cleared to zero. + * | | |001 = progress to OEM stage. + * | | |011 = progress to Deployed stage. + * | | |111 = progress to RMA stage. + * | | |Other value will be ignored. + * |[31:16] |WVCODE |Write Verify Code + * | | |The code is 0x475A for a valid write to this register. + * @var PLM_T::STS + * Offset: 0x04 Product Life-cycle Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |STAGE |Life-cycle Stage (Read Only) + * | | |Indicates the current stage of PLM. + * | | |000 = Vendor Stage. + * | | |001 = OEM Stage. + * | | |011 = Deployed Stage. + * | | |111 = RMA Stage. + * | | |Others = ERROR Stage. + * |[8] |DIRTY |DIRTY Bit (Read Only) + * | | |Indicate the life-cycle stage has been progressed after last cold-reset + * | | |Value of STAGE bits is not Current stage of PLM + * | | |It needs a cold reset to make it work. + */ + __IO uint32_t CTL; /*!< [0x0000] Product Life-cycle Control Register */ + __I uint32_t STS; /*!< [0x0004] Product Life-cycle Status Register */ + +} PLM_T; + +/** + @addtogroup PLM_CONST PLM Bit Field Definition + Constant Definitions for PLM Controller + @{ +*/ + +#define PLM_CTL_STAGE_Pos (0) /*!< PLM_T::CTL: STAGE Position */ +#define PLM_CTL_STAGE_Msk (0x7ul << PLM_CTL_STAGE_Pos) /*!< PLM_T::CTL: STAGE Mask */ + +#define PLM_CTL_WVCODE_Pos (16) /*!< PLM_T::CTL: WVCODE Position */ +#define PLM_CTL_WVCODE_Msk (0xfffful << PLM_CTL_WVCODE_Pos) /*!< PLM_T::CTL: WVCODE Mask */ + +#define PLM_STS_STAGE_Pos (0) /*!< PLM_T::STS: STAGE Position */ +#define PLM_STS_STAGE_Msk (0x7ul << PLM_STS_STAGE_Pos) /*!< PLM_T::STS: STAGE Mask */ + +#define PLM_STS_DIRTY_Pos (8) /*!< PLM_T::STS: DIRTY Position */ +#define PLM_STS_DIRTY_Msk (0x1ul << PLM_STS_DIRTY_Pos) /*!< PLM_T::STS: DIRTY Mask */ + +/**@}*/ /* PLM_CONST */ +/**@}*/ /* end of PLM register group */ + + +/*---------------------- Secure configuration Unit -------------------------*/ +/** + @addtogroup SCU Secure configuration Unit(SCU) + Memory Mapped Structure for SCU Controller + @{ +*/ + +typedef struct +{ + + +/** + * @var SCU_T::PNSSET + * Offset: 0x00 Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x4001_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9] |USBH |Set USBH to Non-secure State + * | | |Write 1 to set USBH to non-secure state. Write 0 has no effect. + * | | |0 = USBH is a secure module (default). + * | | |1 = USBH is a non-secure module. + * |[13] |SDH0 |Set SDH0 to Non-secure State + * | | |Write 1 to set SDH0 to non-secure state. Write 0 has no effect. + * | | |0 = SDH0 is a secure module (default). + * | | |1 = SDH0 is a non-secure module. + * |[16] |EBI |Set EBI to Non-secure State + * | | |Write 1 to set EBI to non-secure state. Write 0 has no effect. + * | | |0 = EBI is a secure module (default). + * | | |1 = EBI is a non-secure module. + * |[24] |PDMA1 |Set PDMA1 to Non-secure State + * | | |Write 1 to set PDMA1 to non-secure state. Write 0 has no effect. + * | | |0 = PDMA1 is a secure module (default). + * | | |1 = PDMA1 is a non-secure module. + * Offset: 0x04 Peripheral Non-secure Attribution Set Register1 (0x4002_0000~0x4003_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[17] |CRC |Set CRC to Non-secure State + * | | |Write 1 to set CRC to non-secure state. Write 0 has no effect. + * | | |0 = CRC is a secure module (default). + * | | |1 = CRC is a non-secure module. + * |[18] |CRPT |Set CRPT to Non-secure State + * | | |0 = CRPT is a secure module (default). + * | | |1 = CRPT is a non-secure module. + * Offset: 0x08 Peripheral Non-secure Attribution Set Register2 (0x4004_0000~0x4005_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2] |EWDT |Set EWDT to Non-secure State + * | | |Write 1 to set EWDT to non-secure state. Write 0 has no effect. + * | | |0 = EWDT is a secure module (default). + * | | |1 = EWDT is a non-secure module. + * |[3] |EADC |Set EADC to Non-secure State + * | | |Write 1 to set EADC to non-secure state. Write 0 has no effect. + * | | |0 = EADC is a secure module (default). + * | | |1 = EADC is a non-secure module. + * |[5] |ACMP01 |Set ACMP01 to Non-secure State + * | | |Write 1 to set ACMP0, ACMP1 to non-secure state. Write 0 has no effect. + * | | |0 = ACMP0, ACMP1 are secure modules (default). + * | | |1 = ACMP0, ACMP1 are non-secure modules. + * |[7] |DAC |Set DAC to Non-secure State + * | | |Write 1 to set DAC to non-secure state. Write 0 has no effect. + * | | |0 = DAC is a secure module (default). + * | | |1 = DAC is a non-secure module. + * |[8] |I2S0 |Set I2S0 to Non-secure State + * | | |Write 1 to set I2S0 to non-secure state. Write 0 has no effect. + * | | |0 = I2S0 is a secure module (default). + * | | |1 = I2S0 is a non-secure module. + * |[13] |OTG |Set OTG to Non-secure State + * | | |Write 1 to set OTG to non-secure state. Write 0 has no effect. + * | | |0 = OTG is a secure module (default). + * | | |1 = OTG is a non-secure module. + * |[17] |TMR23 |Set TMR23 to Non-secure State + * | | |Write 1 to set TMR23 to non-secure state. Write 0 has no effect. + * | | |0 = TMR23 is a secure module (default). + * | | |1 = TMR23 is a non-secure module. + * |[24] |EPWM0 |Set EPWM0 to Non-secure State + * | | |Write 1 to set EPWM0 to non-secure state. Write 0 has no effect. + * | | |0 = EPWM0 is a secure module (default). + * | | |1 = EPWM0 is a non-secure module. + * |[25] |EPWM1 |Set EPWM1 to Non-secure State + * | | |Write 1 to set EPWM1 to non-secure state. Write 0 has no effect. + * | | |0 = EPWM1 is a secure module (default). + * | | |1 = EPWM1 is a non-secure module. + * |[26] |BPWM0 |Set BPWM0 to Non-secure State + * | | |Write 1 to set BPWM0 to non-secure state. Write 0 has no effect. + * | | |0 = BPWM0 is a secure module (default). + * | | |1 = BPWM0 is a non-secure module. + * |[27] |BPWM1 |Set BPWM1 to Non-secure State + * | | |Write 1 to set BPWM1 to non-secure state. Write 0 has no effect. + * | | |0 = BPWM1 is a secure module (default). + * | | |1 = BPWM1 is a non-secure module. + * Offset: 0x0C Peripheral Non-secure Attribution Set Register3 (0x4006_0000~0x4007_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |QSPI0 |Set QSPI0 to Non-secure State + * | | |Write 1 to set QSPI0 to non-secure state. Write 0 has no effect. + * | | |0 = QSPI0 is a secure module (default). + * | | |1 = QSPI0 is a non-secure module. + * |[1] |SPI0 |Set SPI0 to Non-secure State + * | | |Write 1 to set SPI0 to non-secure state. Write 0 has no effect. + * | | |0 = SPI0 is a secure module (default). + * | | |1 = SPI0 is a non-secure module. + * |[2] |SPI1 |Set SPI1 to Non-secure State + * | | |Write 1 to set SPI1 to non-secure state. Write 0 has no effect. + * | | |0 = SPI1 is a secure module (default). + * | | |1 = SPI1 is a non-secure module. + * |[3] |SPI2 |Set SPI2 to Non-secure State + * | | |Write 1 to set SPI2 to non-secure state. Write 0 has no effect. + * | | |0 = SPI2 is a secure module (default). + * | | |1 = SPI2 is a non-secure module. + * |[4] |SPI3 |Set SPI3 to Non-secure State + * | | |Write 1 to set SPI3 to non-secure state. Write 0 has no effect. + * | | |0 = SPI3 is a secure module (default). + * | | |1 = SPI3 is a non-secure module. + * |[16] |UART0 |Set UART0 to Non-secure State + * | | |Write 1 to set UART0 to non-secure state. Write 0 has no effect. + * | | |0 = UART0 is a secure module (default). + * | | |1 = UART0 is a non-secure module. + * |[17] |UART1 |Set UART1 to Non-secure State + * | | |Write 1 to set UART1 to non-secure state. Write 0 has no effect. + * | | |0 = UART1 is a secure module (default). + * | | |1 = UART1 is a non-secure module. + * |[18] |UART2 |Set UART2 to Non-secure State + * | | |Write 1 to set UART2 to non-secure state. Write 0 has no effect. + * | | |0 = UART2 is a secure module (default). + * | | |1 = UART2 is a non-secure module. + * |[19] |UART3 |Set UART3 to Non-secure State + * | | |Write 1 to set UART3 to non-secure state. Write 0 has no effect. + * | | |0 = UART3 is a secure module (default). + * | | |1 = UART3 is a non-secure module. + * |[20] |UART4 |Set UART4 to Non-secure State + * | | |Write 1 to set UART4 to non-secure state. Write 0 has no effect. + * | | |0 = UART4 is a secure module (default). + * | | |1 = UART4 is a non-secure module. + * |[21] |UART5 |Set UART5 to Non-secure State + * | | |Write 1 to set UART5 to non-secure state. Write 0 has no effect. + * | | |0 = UART5 is a secure module (default). + * | | |1 = UART5 is a non-secure module. + * Offset: 0x10 Peripheral Non-secure Attribution Set Register4 (0x4008_0000~0x4009_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2C0 |Set I2C0 to Non-secure State + * | | |Write 1 to set I2C0 to non-secure state. Write 0 has no effect. + * | | |0 = I2C0 is a secure module (default). + * | | |1 = I2C0 is a non-secure module. + * |[1] |I2C1 |Set I2C1 to Non-secure State + * | | |Write 1 to set I2C1 to non-secure state. Write 0 has no effect. + * | | |0 = I2C1 is a secure module (default). + * | | |1 = I2C1 is a non-secure module. + * |[2] |I2C2 |Set I2C2 to Non-secure State + * | | |Write 1 to set I2C2 to non-secure state. Write 0 has no effect. + * | | |0 = I2C2 is a secure module (default). + * | | |1 = I2C2 is a non-secure module. + * |[16] |SC0 |Set SC0 to Non-secure State + * | | |Write 1 to set SC0 to non-secure state. Write 0 has no effect. + * | | |0 = SC0 is a secure module (default). + * | | |1 = SC0 is a non-secure module. + * |[17] |SC1 |Set SC1 to Non-secure State + * | | |Write 1 to set SC1 to non-secure state. Write 0 has no effect. + * | | |0 = SC1 is a secure module (default). + * | | |1 = SC1 is a non-secure module. + * |[18] |SC2 |Set SC2 to Non-secure State + * | | |Write 1 to set SC2 to non-secure state. Write 0 has no effect. + * | | |0 = SC2 is a secure module (default). + * | | |1 = SC2 is a non-secure module. + * Offset: 0x14 Peripheral Non-secure Attribution Set Register5 (0x400A_0000~0x400B_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAN0 |Set CAN0 to Non-secure State + * | | |Write 1 to set CAN0 to non-secure state. Write 0 has no effect. + * | | |0 = CAN0 is a secure module (default). + * | | |1 = CAN0 is a non-secure module. + * |[16] |QEI0 |Set QEI0 to Non-secure State + * | | |Write 1 to set QEI0 to non-secure state. Write 0 has no effect. + * | | |0 = QEI0 is a secure module (default). + * | | |1 = QEI0 is a non-secure module. + * |[17] |QEI1 |Set QEI1 to Non-secure State + * | | |Write 1 to set QEI1 to non-secure state. Write 0 has no effect. + * | | |0 = QEI1 is a secure module (default). + * | | |1 = QEI1 is a non-secure module. + * |[20] |ECAP0 |Set ECAP0 to Non-secure State + * | | |Write 1 to set ECAP0 to non-secure state. Write 0 has no effect. + * | | |0 = ECAP0 is a secure module (default). + * | | |1 = ECAP0 is a non-secure module. + * |[21] |ECAP1 |Set ECAP1 to Non-secure State + * | | |Write 1 to set ECAP1 to non-secure state. Write 0 has no effect. + * | | |0 = ECAP1 is a secure module (default). + * | | |1 = ECAP1 is a non-secure module. + * |[25] |TRNG |Set TRNG to Non-secure State + * | | |Write 1 to set TRNG to non-secure state. Write 0 has no effect. + * | | |0 = TRNG is a secure module (default). + * | | |1 = TRNG is a non-secure module. + * |[27] |LCD |Set LCD to Non-secure State + * | | |Write 1 to set LCD to non-secure state. Write 0 has no effect. + * | | |0 = LCD is a secure module (default). + * | | |1 = LCD is a non-secure module. + * Offset: 0x18 Peripheral Non-secure Attribution Set Register6 (0x400C_0000~0x400D_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBD |Set USBD to Non-secure State + * | | |Write 1 to set USBD to non-secure state. Write 0 has no effect. + * | | |0 = USBD is a secure module (default). + * | | |1 = USBD is a non-secure module. + * |[16] |USCI0 |Set USCI0 to Non-secure State + * | | |Write 1 to set USCI0 to non-secure state. Write 0 has no effect. + * | | |0 = USCI0 is a secure module (default). + * | | |1 = USCI0 is a non-secure module. + * |[17] |USCI1 |Set USCI1 to Non-secure State + * | | |Write 1 to set USCI1 to non-secure state. Write 0 has no effect. + * | | |0 = USCI1 is a secure module (default). + * | | |1 = USCI1 is a non-secure module. + * @var SCU_T::IONSSET + * Offset: 0x20 IO Non-secure Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PA |Set GPIO Port a to Non-scecure State + * | | |Write 1 to set PA to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port A is secure (default). + * | | |1 = GPIO port A is non-secure. + * |[1] |PB |Set GPIO Port B to Non-scecure State + * | | |Write 1 to set PB to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port B is secure (default). + * | | |1 = GPIO port B is non-secure. + * |[2] |PC |Set GPIO Port C to Non-scecure State + * | | |Write 1 to set PC to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port C is secure (default). + * | | |1 = GPIO port C is non-secure. + * |[3] |PD |Set GPIO Port D to Non-scecure State + * | | |Write 1 to set PD to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port D is secure (default). + * | | |1 = GPIO port D is non-secure. + * |[4] |PE |Set GPIO Port E to Non-scecure State + * | | |Write 1 to set PE to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port E is secure (default). + * | | |1 = GPIO port E is non-secure. + * |[5] |PF |Set GPIO Port F to Non-scecure State + * | | |Write 1 to set PF to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port F is secure (default). + * | | |1 = GPIO port F is non-secure. + * |[6] |PG |Set GPIO Port G to Non-scecure State + * | | |Write 1 to set PG to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port G is secure (default). + * | | |1 = GPIO port G is non-secure. + * |[7] |PH |Set GPIO Port H to Non-scecure State + * | | |Write 1 to set PH to non-secure state. Write 0 has no effect. + * | | |0 = GPIO port H is secure (default). + * | | |1 = GPIO port H is non-secure. + * @var SCU_T::SRAMNSSET + * Offset: 0x24 SRAM Non-secure Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |SECn |Set SRAM Section n to Non-scecure State + * | | |Write 1 to set SRAM section n to non-secure state. Write 0 is ignored. + * | | |0 = SRAM Section n is secure (default). + * | | |1 = SRAM Section n is non-secure. + * | | |Size per section is 16 Kbytes. + * | | |Secure SRAM section n is 0x2000_0000+0x4000*n to 0x2000_0000+0x4000*(n+1)-0x1 + * | | |Non-secure SRAM section n is 0x3000_0000+0x4000*n to 0x3000_0000+0x4000*(n+1)-0x1 + * @var SCU_T::FNSADDR + * Offset: 0x28 Flash Non-secure Boundary Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |FNSADDR |Flash Non-secure Boundary Address + * | | |Indicate the base address of Non-secure region set in user configuration + * | | |Refer to FMC section for more details. + * @var SCU_T::SVIOIEN + * Offset: 0x2C Security Violation Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APB0IEN |APB0 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of APB0 Disabled. + * | | |1 = Interrupt triggered from security violation of APB0 Enabled. + * |[1] |APB1IEN |APB1 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of APB1 Disabled. + * | | |1 = Interrupt triggered from security violation of APB1 Enabled. + * |[4] |GPIOIEN |GPIO Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of GPIO Disabled. + * | | |1 = Interrupt triggered from security violation of GPIO Enabled. + * |[5] |EBIIEN |EBI Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of EBI Disabled. + * | | |1 = Interrupt triggered from security violation of EBI Enabled. + * |[6] |USBHIEN |USBH Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of USB host Disabled. + * | | |1 = Interrupt triggered from security violation of USB host Enabled. + * |[7] |CRCIEN |CRC Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of CRC Disabled. + * | | |1 = Interrupt triggered from security violation of CRC Enabled. + * |[8] |SDH0IEN |SDH0 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of SD host 0 Disabled. + * | | |1 = Interrupt triggered from security violation of SD host 0 Enabled. + * |[10] |PDMA0IEN |PDMA0 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of PDMA0 Disabled. + * | | |1 = Interrupt triggered from security violation of PDMA0 Enabled. + * |[11] |PDMA1IEN |PDMA1 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of PDMA1 Disabled. + * | | |1 = Interrupt triggered from security violation of PDMA1 Enabled. + * |[12] |SRAM0IEN |SRAM Bank 0 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of SRAM bank0 Disabled. + * | | |1 = Interrupt triggered from security violation of SRAM bank0 Enabled. + * |[13] |SRAM1IEN |SRAM Bank 1 Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of SRAM bank1 Disabled. + * | | |1 = Interrupt triggered from security violation of SRAM bank1 Enabled. + * |[14] |FMCIEN |FMC Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of FMC Disabled. + * | | |1 = Interrupt triggered from security violation of FMC Enabled. + * |[15] |FLASHIEN |FLASH Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of Flash data Disabled. + * | | |1 = Interrupt triggered from security violation of Flash data Enabled. + * |[16] |SCUIEN |SCU Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of SCU Disabled. + * | | |1 = Interrupt triggered from security violation of SCU Enabled. + * |[17] |SYSIEN |SYS Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of system manager Disabled. + * | | |1 = Interrupt triggered from security violation of system manager Enabled. + * |[18] |CRPTIEN |CRPT Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of crypto Disabled. + * | | |1 = Interrupt triggered from security violation of crypto Enabled. + * |[19] |KSIEN |KS Security Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from security violation of keystore Disabled. + * | | |1 = Interrupt triggered from security violation of keystore Enabled. + * @var SCU_T::SVINTSTS + * Offset: 0x30 Security Violation Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APB0IF |APB0 Security Violation Interrupt Status + * | | |0 = No APB0 violation interrupt event. + * | | |1 = There is APB0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[1] |APB1IF |APB1 Security Violation Interrupt Status + * | | |0 = No APB1 violation interrupt event. + * | | |1 = There is APB1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[4] |GPIOIF |GPIO Security Violation Interrupt Status + * | | |0 = No GPIO violation interrupt event. + * | | |1 = There is GPIO violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[5] |EBIIF |EBI Security Violation Interrupt Status + * | | |0 = No EBI violation interrupt event. + * | | |1 = There is EBI violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[6] |USBHIF |USBH Security Violation Interrupt Status + * | | |0 = No USBH violation interrupt event. + * | | |1 = There is USBH violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[7] |CRCIF |CRC Security Violation Interrupt Status + * | | |0 = No CRC violation interrupt event. + * | | |1 = There is CRC violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[8] |SDH0IF |SDH0 Security Violation Interrupt Status + * | | |0 = No SDH0 violation interrupt event. + * | | |1 = There is SDH0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[10] |PDMA0IF |PDMA0 Security Violation Interrupt Status + * | | |0 = No PDMA0 violation interrupt event. + * | | |1 = There is PDMA0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[11] |PDMA1IF |PDMA1 Security Violation Interrupt Status + * | | |0 = No PDMA1 violation interrupt event. + * | | |1 = There is PDMA1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[12] |SRAM0IF |SRAM0 Security Violation Interrupt Status + * | | |0 = No SRAM0 violation interrupt event. + * | | |1 = There is SRAM0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[13] |SRAM1IF |SRAM Bank 1 Security Violation Interrupt Status + * | | |0 = No SRAM1 violation interrupt event. + * | | |1 = There is SRAM1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[14] |FMCIF |FMC Security Violation Interrupt Status + * | | |0 = No FMC violation interrupt event. + * | | |1 = There is FMC violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[15] |FLASHIF |FLASH Security Violation Interrupt Status + * | | |0 = No FLASH violation interrupt event. + * | | |1 = There is FLASH violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[16] |SCUIF |SCU Security Violation Interrupt Status + * | | |0 = No SCU violation interrupt event. + * | | |1 = There is SCU violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[17] |SYSIF |SYS Security Violation Interrupt Status + * | | |0 = No SYS violation interrupt event. + * | | |1 = There is SYS violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[18] |CRPTIF |CRPT Security Violation Interrupt Status + * | | |0 = No CRPT violation interrupt event. + * | | |1 = There is CRPT violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[19] |KSIF |KS Security Violation Interrupt Status + * | | |0 = No KS violation interrupt event. + * | | |1 = There is KS violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * @var SCU_T::APB0VSRC + * Offset: 0x34 APB0 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::APB0VA + * Offset: 0x38 APB0 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::APB1VSRC + * Offset: 0x3C APB1 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::APB1VA + * Offset: 0x40 APB1 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::GPIOVSRC + * Offset: 0x44 GPIO Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::GPIOVA + * Offset: 0x48 GPIO Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::EBIVSRC + * Offset: 0x4C EBI Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::EBIVA + * Offset: 0x50 EBI Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::USBHVSRC + * Offset: 0x54 USBH Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::USBHVA + * Offset: 0x58 USBH Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::CRCVSRC + * Offset: 0x5C CRC Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::CRCVA + * Offset: 0x60 CRC Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SD0VSRC + * Offset: 0x64 SDH0 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::SD0VA + * Offset: 0x68 SDH0 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::PDMA0VSRC + * Offset: 0x74 PDMA0 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::PDMA0VA + * Offset: 0x78 PDMA0 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::PDMA1VSRC + * Offset: 0x7C PDMA1 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::PDMA1VA + * Offset: 0x80 PDMA1 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SRAM0VSRC + * Offset: 0x84 SRAM0 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::SRAM0VA + * Offset: 0x88 SRAM0 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SRAM1VSRC + * Offset: 0x8C SRAM1 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::SRAM1VA + * Offset: 0x90 SRAM1 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::FMCVSRC + * Offset: 0x94 FMC Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::FMCVA + * Offset: 0x98 FMC Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::FLASHVSRC + * Offset: 0x9C Flash Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::FLASHVA + * Offset: 0xA0 Flash Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SCUVSRC + * Offset: 0xA4 SCU Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::SCUVA + * Offset: 0xA8 SCU Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SYSVSRC + * Offset: 0xAC System(GMISC) Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::SYSVA + * Offset: 0xB0 System(GMISC) Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::CRPTVSRC + * Offset: 0xB4 Crypto Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::CRPTVA + * Offset: 0xB8 Crypto Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::KSVSRC + * Offset: 0xBC KS Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::KSVA + * Offset: 0xC0 KS Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SRAM2VSRC + * Offset: 0xC4 SRAM2 Security Policy Violation Source + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |MASTER |Master Violating Security Policy + * | | |Indicate which master invokes the security violation. + * | | |0x0 = core processor. + * | | |0x3 = PDMA0. + * | | |0x4 = SDH0. + * | | |0x5 = CRYPTO. + * | | |0x6 = USH. + * | | |0xB = PDMA1. + * | | |Others is undefined. + * @var SCU_T::SRAM2VA + * Offset: 0xC8 SRAM2 Violation Address + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |VIOADDR |Violation Address + * | | |Indicate the target address of the access, which invokes the security violation. + * @var SCU_T::SINFAEN + * Offset: 0xF0 Shared Information Access Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SCUSIAEN |SCU Shared Information Access Enable Bit + * | | |0 = Non-secure CPU access SCU Shared information Disabled. + * | | |1 = Non-secure CPU access SCU Shared information Enabled. + * |[1] |SYSSIAEN |SYS Shared Information Access Enable Bit + * | | |0 = Non-secure CPU access SYS Shared information Disabled. + * | | |1 = Non-secure CPU access SYS Shared information Enabled. + * | | |Note:Include clock information. + * |[2] |FMCSIAEN |FMC Shared Information Access Enable Bit + * | | |0 = Non-secure CPU access FMC Shared information Disabled. + * | | |1 = Non-secure CPU access FMC Shared information Enabled. + * @var SCU_T::PNPSET + * Offset: 0x100 Peripheral Non-privileged Attribution Set Register0 (0x4000_0000~0x4001_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYS |Set SYS to Non-privileged State + * | | |0 = SYS is a privileged module (default). + * | | |1 = SYS is a non-privileged module. + * |[8] |PDMA0 |Set PDMA0 to Non-privileged State + * | | |0 = PDMA0 is a privileged module (default). + * | | |1 = PDMA0 is a non-privileged module. + * |[9] |USBH |Set USBH to Non-privileged State + * | | |0 = USBH is a privileged module (default). + * | | |1 = USBH is a non-privileged module. + * |[12] |FMC |Set FMC to Non-privileged State + * | | |0 = FMC is a privileged module (default). + * | | |1 = FMC is a non-privileged module. + * |[13] |SDH0 |Set SDH0 to Non-privileged State + * | | |0 = SDH0 is a privileged module (default). + * | | |1 = SDH0 is a non-privileged module. + * |[16] |EBI |Set EBI to Non-privileged State + * | | |0 = EBI is a privileged module (default). + * | | |1 = EBI is a non-privileged module. + * |[24] |PDMA1 |Set PDMA1 to Non-privileged State + * | | |0 = PDMA1 is a privileged module (default). + * | | |1 = PDMA1 is a non-privileged module. + * Offset: 0x104 Peripheral Non-privileged Attribution Set Register1 (0x4002_0000~0x4003_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15] |SCU |Set SCU to Non-privileged State + * | | |0 = SCU is a privileged module (default). + * | | |1 = SCU is a non-privileged module. + * |[17] |CRC |Set CRC to Non-privileged State + * | | |0 = CRC is a privileged module (default). + * | | |1 = CRC is a non-privileged module. + * |[18] |CRPT |Set CRPT to Non-privileged State + * | | |0 = CRPT is a privileged module (default). + * | | |1 = CRPT is a non-privileged module. + * |[21] |KS |Set KS to Non-privileged State + * | | |0 = KS is a privileged module (default). + * | | |1 = KS is a non-privileged module. + * Offset: 0x108 Peripheral Non-privileged Attribution Set Register2 (0x4004_0000~0x4005_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WDT |Set WDT to Non-privileged State + * | | |0 = WDT is a privileged module (default). + * | | |1 = WDT is a non-privileged module. + * |[1] |RTC |Set RTC to Non-privileged State + * | | |0 = RTC is a privileged module (default). + * | | |1 = RTC is a non-privileged module. + * |[2] |EWDT |Set EWDT to Non-privileged State + * | | |0 = EWDT is a privileged module (default). + * | | |1 = EWDT is a non-privileged module. + * |[3] |EADC |Set EADC to Non-privileged State + * | | |0 = EADC is a privileged module (default). + * | | |1 = EADC is a non-privileged module. + * |[5] |ACMP01 |Set ACMP01 to Non-privileged State + * | | |0 = ACMP0, ACMP1 are privileged modules (default). + * | | |1 = ACMP0, ACMP1 are non-privileged modules. + * |[7] |DAC |Set DAC to Non-privileged State + * | | |0 = DAC is a privileged module (default). + * | | |1 = DAC is a non-privileged module. + * |[8] |I2S0 |Set I2S0 to Non-privileged State + * | | |0 = I2S0 is a privileged module (default). + * | | |1 = I2S0 is a non-privileged module. + * |[13] |OTG |Set OTG to Non-privileged State + * | | |0 = OTG is a privileged module (default). + * | | |1 = OTG is a non-privileged module. + * |[16:14] |TMR01 |Set TMR01 to Non-privileged State + * | | |0 = TMR01 is a privileged module (default). + * | | |1 = TMR01 is a non-privileged module. + * |[17] |TMR23 |Set TMR23 to Non-privileged State + * | | |0 = TMR23 is a privileged module (default). + * | | |1 = TMR23 is a non-privileged module. + * |[24] |EPWM0 |Set EPWM0 to Non-privileged State + * | | |0 = EPWM0 is a privileged module (default). + * | | |1 = EPWM0 is a non-privileged module. + * |[25] |EPWM1 |Set EPWM1 to Non-privileged State + * | | |0 = EPWM1 is a privileged module (default). + * | | |1 = EPWM1 is a non-privileged module. + * |[26] |BPWM0 |Set BPWM0 to Non-privileged State + * | | |0 = BPWM0 is a privileged module (default). + * | | |1 = BPWM0 is a non-privileged module. + * |[27] |BPWM1 |Set BPWM1 to Non-privileged State + * | | |0 = BPWM1 is a privileged module (default). + * | | |1 = BPWM1 is a non-privileged module. + * Offset: 0x10C Peripheral Non-privileged Attribution Set Register3 (0x4006_0000~0x4007_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |QSPI0 |Set QSPI0 to Non-privileged State + * | | |0 = QSPI0 is a privileged module (default). + * | | |1 = QSPI0 is a non-privileged module. + * |[1] |SPI0 |Set SPI0 to Non-privileged State + * | | |0 = SPI0 is a privileged module (default). + * | | |1 = SPI0 is a non-privileged module. + * |[2] |SPI1 |Set SPI1 to Non-privileged State + * | | |0 = SPI1 is a privileged module (default). + * | | |1 = SPI1 is a non-privileged module. + * |[3] |SPI2 |Set SPI2 to Non-privileged State + * | | |0 = SPI2 is a privileged module (default). + * | | |1 = SPI2 is a non-privileged module. + * |[4] |SPI3 |Set SPI3 to Non-privileged State + * | | |0 = SPI3 is a privileged module (default). + * | | |1 = SPI3 is a non-privileged module. + * |[16] |UART0 |Set UART0 to Non-privileged State + * | | |0 = UART0 is a privileged module (default). + * | | |1 = UART0 is a non-privileged module. + * |[17] |UART1 |Set UART1 to Non-privileged State + * | | |0 = UART1 is a privileged module (default). + * | | |1 = UART1 is a non-privileged module. + * |[18] |UART2 |Set UART2 to Non-privileged State + * | | |0 = UART2 is a privileged module (default). + * | | |1 = UART2 is a non-privileged module. + * |[19] |UART3 |Set UART3 to Non-privileged State + * | | |0 = UART3 is a privileged module (default). + * | | |1 = UART3 is a non-privileged module. + * |[20] |UART4 |Set UART4 to Non-privileged State + * | | |0 = UART4 is a privileged module (default). + * | | |1 = UART4 is a non-privileged module. + * |[21] |UART5 |Set UART5 to Non-privileged State + * | | |0 = UART5 is a privileged module (default). + * | | |1 = UART5 is a non-privileged module. + * Offset: 0x110 Peripheral Non-privileged Attribution Set Register4 (0x4008_0000~0x4009_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2C0 |Set I2C0 to Non-privileged State + * | | |0 = I2C0 is a privileged module (default). + * | | |1 = I2C0 is a non-privileged module. + * |[1] |I2C1 |Set I2C1 to Non-privileged State + * | | |0 = I2C1 is a privileged module (default). + * | | |1 = I2C1 is a non-privileged module. + * |[2] |I2C2 |Set I2C2 to Non-privileged State + * | | |0 = I2C2 is a privileged module (default). + * | | |1 = I2C2 is a non-privileged module. + * |[16] |SC0 |Set SC0 to Non-privileged State + * | | |0 = SC0 is a privileged module (default). + * | | |1 = SC0 is a non-privileged module. + * |[17] |SC1 |Set SC1 to Non-privileged State + * | | |0 = SC1 is a privileged module (default). + * | | |1 = SC1 is a non-privileged module. + * |[18] |SC2 |Set SC2 to Non-privileged State + * | | |0 = SC2 is a privileged module (default). + * | | |1 = SC2 is a non-privileged module. + * Offset: 0x114 Peripheral Non-privileged Attribution Set Register5 (0x400A_0000~0x400B_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAN0 |Set CAN0 to Non-privileged State + * | | |0 = CAN0 is a privileged module (default). + * | | |1 = CAN0 is a non-privileged module. + * |[16] |QEI0 |Set QEI0 to Non-privileged State + * | | |0 = QEI0 is a privileged module (default). + * | | |1 = QEI0 is a non-privileged module. + * |[17] |QEI1 |Set QEI1 to Non-privileged State + * | | |0 = QEI1 is a privileged module (default). + * | | |1 = QEI1 is a non-privileged module. + * |[20] |ECAP0 |Set ECAP0 to Non-privileged State + * | | |0 = ECAP0 is a privileged module (default). + * | | |1 = ECAP0 is a non-privileged module. + * |[21] |ECAP1 |Set ECAP1 to Non-privileged State + * | | |0 = ECAP1 is a privileged module (default). + * | | |1 = ECAP1 is a non-privileged module. + * |[25] |TRNG |Set TRNG to Non-privileged State + * | | |0 = TRNG is a privileged module (default). + * | | |1 = TRNG is a non-privileged module. + * |[27] |LCD |Set LCD to Non-privileged State + * | | |0 = LCD is a privileged module (default). + * | | |1 = LCD is a non-privileged module. + * |[29] |TAMPER |Set TAMPER to Non-privileged State + * | | |0 = TAMPER is a privileged module (default). + * | | |1 = TAMPER is a non-privileged module. + * Offset: 0x118 Peripheral Non-privileged Attribution Set Register6 (0x400C_0000~0x400D_FFFF) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBD |Set USBD to Non-privileged State + * | | |0 = USBD is a privileged module (default). + * | | |1 = USBD is a non-privileged module. + * |[16] |USCI0 |Set USCI0 to Non-privileged State + * | | |0 = USCI0 is a privileged module (default). + * | | |1 = USCI0 is a non-privileged module. + * |[17] |USCI1 |Set USCI1 to Non-privileged State + * | | |0 = USCI1 is a privileged module (default). + * | | |1 = USCI1 is a non-privileged module. + * @var SCU_T::IONPSET + * Offset: 0x120 IO Non-privileged Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PA |Set GPIO Port a to Non-privileged State + * | | |0 = GPIO port A is privileged (default). + * | | |1 = GPIO port A is non-privileged. + * |[1] |PB |Set GPIO Port B to Non-privileged State + * | | |0 = GPIO port B is privileged (default). + * | | |1 = GPIO port B is non-privileged. + * |[2] |PC |Set GPIO Port C to Non-privileged State + * | | |0 = GPIO port C is privileged (default). + * | | |1 = GPIO port C is non-privileged. + * |[3] |PD |Set GPIO Port D to Non-privileged State + * | | |0 = GPIO port D is privileged (default). + * | | |1 = GPIO port D is non-privileged. + * |[4] |PE |Set GPIO Port E to Nonj-privileged State + * | | |0 = GPIO port E is privileged (default). + * | | |1 = GPIO port E is non-privileged. + * |[5] |PF |Set GPIO Port F to Non-privileged State + * | | |0 = GPIO port F is privileged (default). + * | | |1 = GPIO port F is non-privileged. + * |[6] |PG |Set GPIO Port G to Non-privileged State + * | | |0 = GPIO port G is privileged (default). + * | | |1 = GPIO port G is non-privileged. + * |[7] |PH |Set GPIO Port H to Non-privileged State + * | | |0 = GPIO port H is privileged (default). + * | | |1 = GPIO port H is non-privileged. + * @var SCU_T::SRAMNPSET + * Offset: 0x124 SRAM Non-privileged Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[19:0] |SECn |Set SRAM Section n to Non-privileged State + * | | |0 = SRAM Section n is privileged (default). + * | | |1 = SRAM Section n is non-privileged. + * | | |Size per section is 16 Kbytes. + * | | |Secure SRAM section n is 0x2000_0000+0x4000*n to 0x2000_0000+0x4000*(n+1)-0x1 + * | | |Non-secure SRAM section n is 0x3000_0000+0x4000*n to 0x3000_0000+0x4000*(n+1)-0x1 + * @var SCU_T::MEMNPSET + * Offset: 0x128 Other Memory Non-privileged Attribution Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FLASH |Set Flash to Non-privileged State + * | | |Set the privileged state of memory ranging from 0x0000_0000 to 0x1FFF_FFFF. + * | | |0 = Flash is setting to privileged (default). + * | | |1 = Flash is setting to non-privileged. + * |[1] |EXTMEM |Set External Memory (EBI Memory) to Non-privileged State + * | | |Set the privileged state of memory ranging from 0x6000_0000 to 0x7FFF_FFFF. + * | | |0 = External Memory is setting to privileged (default). + * | | |1 = External Memory is setting to non-privileged. + * @var SCU_T::PVIOIEN + * Offset: 0x12C Privileged Violation Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APB0IEN |APB0 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of APB0 Disabled. + * | | |1 = Interrupt triggered from privileged violation of APB0 Enabled. + * |[1] |APB1IEN |APB1 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of APB1 Disabled. + * | | |1 = Interrupt triggered from privileged violation of APB1 Enabled. + * |[4] |GPIOIEN |GPIO Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of GPIO Disabled. + * | | |1 = Interrupt triggered from privileged violation of GPIO Enabled. + * |[5] |EBIIEN |EBI Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of EBI Disabled. + * | | |1 = Interrupt triggered from privileged violation of EBI Enabled. + * |[6] |USBHIEN |USBH Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of USB host Disabled. + * | | |1 = Interrupt triggered from privileged violation of USB host Enabled. + * |[7] |CRCIEN |CRC Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of CRC Disabled. + * | | |1 = Interrupt triggered from privileged violation of CRC Enabled. + * |[8] |SDH0IEN |SDH0 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of SD host 0 Disabled. + * | | |1 = Interrupt triggered from privileged violation of SD host 0 Enabled. + * |[10] |PDMA0IEN |PDMA0 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of PDMA0 Disabled. + * | | |1 = Interrupt triggered from privileged violation of PDMA0 Enabled. + * |[11] |PDMA1IEN |PDMA1 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of PDMA1 Disabled. + * | | |1 = Interrupt triggered from privileged violation of PDMA1 Enabled. + * |[12] |SRAM0IEN |SRAM Bank 0 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of SRAM bank0 Disabled. + * | | |1 = Interrupt triggered from privileged violation of SRAM bank0 Enabled. + * |[13] |SRAM1IEN |SRAM Bank 1 Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of SRAM bank1 Disabled. + * | | |1 = Interrupt triggered from privileged violation of SRAM bank1 Enabled. + * |[14] |FMCIEN |FMC Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of FMC Disabled. + * | | |1 = Interrupt triggered from privileged violation of FMC Enabled. + * |[15] |FLASHIEN |FLASH Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of Flash data Disabled. + * | | |1 = Interrupt triggered from privileged violation of Flash data Enabled. + * |[16] |SCUIEN |SCU Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of SCU Disabled. + * | | |1 = Interrupt triggered from privileged violation of SCU Enabled. + * |[17] |SYSIEN |SYS Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of system manager Disabled. + * | | |1 = Interrupt triggered from privileged violation of system manager Enabled. + * |[18] |CRPTIEN |CRPT Privileged Violation Interrupt Enable Bit + * | | |0 = Interrupt triggered from privileged violation of crypto Disabled. + * | | |1 = Interrupt triggered from privileged violation of crypto Enabled. + * |[19] |KSIEN |KS Privileged Violation Interrupt Enale Bit + * | | |0 = Interrupt triggered from privileged violation of keystore Disabled. + * | | |1 = Interrupt triggered from privileged violation of keystore Enabled. + * @var SCU_T::PVINTSTS + * Offset: 0x130 Privileged Violation Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |APB0IF |APB0 Privileged Violation Interrupt Status + * | | |0 = No APB0 violation interrupt event. + * | | |1 = There is APB0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[1] |APB1IF |APB1 Privileged Violation Interrupt Status + * | | |0 = No APB1 violation interrupt event. + * | | |1 = There is APB1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[4] |GPIOIF |GPIO Privileged Violation Interrupt Status + * | | |0 = No GPIO violation interrupt event. + * | | |1 = There is GPIO violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[5] |EBIIF |EBI Privileged Violation Interrupt Status + * | | |0 = No EBI violation interrupt event. + * | | |1 = There is EBI violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[6] |USBHIF |USBH Privileged Violation Interrupt Status + * | | |0 = No USBH violation interrupt event. + * | | |1 = There is USBH violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[7] |CRCIF |CRC Privileged Violation Interrupt Status + * | | |0 = No CRC violation interrupt event. + * | | |1 = There is CRC violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[8] |SDH0IF |SDH0 Privileged Violation Interrupt Status + * | | |0 = No SDH0 violation interrupt event. + * | | |1 = There is SDH0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[10] |PDMA0IF |PDMA0 Privileged Violation Interrupt Status + * | | |0 = No PDMA0 violation interrupt event. + * | | |1 = There is PDMA0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[11] |PDMA1IF |PDMA1 Privileged Violation Interrupt Status + * | | |0 = No PDMA1 violation interrupt event. + * | | |1 = There is PDMA1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[12] |SRAM0IF |SRAM0 Privileged Violation Interrupt Status + * | | |0 = No SRAM0 violation interrupt event. + * | | |1 = There is SRAM0 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[13] |SRAM1IF |SRAM Bank 1 Privileged Violation Interrupt Status + * | | |0 = No SRAM1 violation interrupt event. + * | | |1 = There is SRAM1 violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[14] |FMCIF |FMC Privileged Violation Interrupt Status + * | | |0 = No FMC violation interrupt event. + * | | |1 = There is FMC violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[15] |FLASHIF |FLASH Privileged Violation Interrupt Status + * | | |0 = No FLASH violation interrupt event. + * | | |1 = There is FLASH violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[16] |SCUIF |SCU Privileged Violation Interrupt Status + * | | |0 = No SCU violation interrupt event. + * | | |1 = There is SCU violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[17] |SYSIF |SYS Privileged Violation Interrupt Status + * | | |0 = No SYS violation interrupt event. + * | | |1 = There is SYS violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[18] |CRPTIF |CRPT Privileged Violation Interrupt Status + * | | |0 = No CRPT violation interrupt event. + * | | |1 = There is CRPT violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * |[19] |KSIF |KS Privileged Violation Interrupt Status + * | | |0 = No KS violation interrupt event. + * | | |1 = There is KS violation interrupt event. + * | | |Note: Write 1 to clear the interrupt flag. + * @var SCU_T::NSMCTL + * Offset: 0x200 Non-secure State Monitor Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PRESCALE |Pre-scale Value of Non-secure State Monitor Counter + * | | |0 = Counter Disabled. + * | | |Others = Counter Enabled and the counter clock source = HCLK/PRESCALE. + * |[8] |NSMIEN |Non-secure State Monitor Interrupt Enable Bit + * | | |0 = Non-secure state monitor interrupt Disabled. + * | | |1 = Non-secure state monitor interrupt Enabled. + * |[9] |AUTORLD |Auto Reload Non-secure State Monitor Counter When CURRNS Changing to 1 + * | | |0 = Disable clearing non-secure state monitor counter automtically (default). + * | | |1 = Enable clearing non-secure state monitor counter automatically when the core processor changes from secure state to non-secure state + * | | |(i.e.when CURRNS chagned from 0 to 1). + * |[10] |TMRMOD |Non-secure Monitor Mode Enable Bit + * | | |0 = Monitor mode. The counter will count down when the core processor is in non-secure state. (default) + * | | |1 = Free-counting mode + * | | |The counter will keep counting no mater the core processor is in secure or non-secure state. + * |[12] |IDLEON |Monitor Counter Keep Counting When the Chip Is in Idle Mode Enable Bit + * | | |0 = The counter will be halted when the chip is in idle mode. + * | | |1 = The counter will keep counting when the chip is in idle mode. (default) + * | | |Note: In monitor mode, the counter is always halted when the core processor is in secure state. + * |[13] |DBGON |Monitor Counter Keep Counting When the Chip Is in Debug Mode Enable Bit + * | | |0 = The counter will be halted when the core processor is halted by ICE. (default) + * | | |1 = The counter will keep counting when the core processor is halted by ICE. + * @var SCU_T::NSMLOAD + * Offset: 0x204 Non-secure State Monitor Reload Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |RELOAD |Reload Value for Non-secure State Monitor Counter + * | | |The RELOAD value will be reloaded to the counter whenever the counter counts down to 0. + * @var SCU_T::NSMVAL + * Offset: 0x208 Non-secure State Monitor Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |VALUE |Counter Value of Non-secure State Monitor Counter + * | | |Current value of non-secure state monitor counter + * | | |This is down counter and counts down only when CURRNS = 1 + * | | |When counting down to 0, VALUE will automatically be reloaded from NSMLOAD register. + * | | |A write of any value clears the VALUE to 0 and also clears NSMIF. + * @var SCU_T::NSMSTS + * Offset: 0x20C Non-secure State Monitor Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CURRNS |Current Core Processor Secure/Non-secure State (Read Only) + * | | |0 = Core processor is in secure state. + * | | |1 = Core processor is in non-secure state. + * | | |Note: This bit can be used to monitor the current secure/non-secure state of the core processor, even if the non-secure state monitor counter is disabled. + * |[1] |NSMIF |Non-secure State Monitor Interrupt Flag + * | | |0 = Counter doesnu2019t count down to 0 since the last NSMIF has been cleared. + * | | |1 = Counter counts down to 0. + * | | |Note: This bit is cleared by writing 1. + * @var SCU_T::BBE + * Offset: 0x300 Block Bus Error Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BBEEN |Block Bus-error Enable Bit + * | | |0 = Disable Blocking Bus Error to the core processor. + * | | |1 = Enable Blocking Bus Error to the core processor. + * | | |This bit is double write-protected, WRVERY and SYS_REGLCTL register. + * |[31:8] |WVERY |Write Verify Code + * | | |In order to write BBEEN bit, the code should be set as 0x59475A. + * | | |When read access, the return value of this field is always 0. + * @var SCU_T::IDAUANS + * Offset: 0x304 IDAU All Non-secure Set Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |IDAUANSEN |IDAU All Non-secure Enable Bit + * | | |0 = Disable IDAU sets all region Non-secure. + * | | |1 = Enable IDAU sets all region Non-secure. + * | | |This bit is double write-protected, WRVERY and SYS_REGLCTL register. + * |[31:8] |WVERY |Write Verify Code + * | | |In order to write BBEEN bit, the code should be set as 0x59475A. + * | | |When read access, the return value of this field is always 0. + * @var SCU_T::VERSION + * Offset: 0xFFC SCU RTL Design Version Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |MINOR |SCU RTL Design Minor Version + * | | |Minor version number is dependent on ECO version control. + * |[23:16] |SUB |SCU RTL Design Sub Version Number + * | | |Major version number is correlated to product line. + * |[31:24] |MAJOR |SCU RTL Design Major Version Number + * | | |Major version number is correlated to product line. + */ + __IO uint32_t PNSSET[7]; /*!< [0x0000:0x0018] Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x400D_FFFF) */ + __I uint32_t RESERVE0[2]; + __IO uint32_t SRAMNSSET; /*!< [0x0024] SRAM Non-secure Attribution Set Register */ + __I uint32_t FNSADDR; /*!< [0x0028] Flash Non-secure Boundary Address Register */ + __IO uint32_t SVIOIEN; /*!< [0x002c] Security Violation Interrupt Enable Register */ + __IO uint32_t SVINTSTS; /*!< [0x0030] Security Violation Interrupt Status Register */ + __I uint32_t APB0VSRC; /*!< [0x0034] APB0 Security Policy Violation Source */ + __I uint32_t APB0VA; /*!< [0x0038] APB0 Violation Address */ + __I uint32_t APB1VSRC; /*!< [0x003c] APB1 Security Policy Violation Source */ + __I uint32_t APB1VA; /*!< [0x0040] APB1 Violation Address */ + __I uint32_t GPIOVSRC; /*!< [0x0044] GPIO Security Policy Violation Source */ + __I uint32_t GPIOVA; /*!< [0x0048] GPIO Violation Address */ + __I uint32_t EBIVSRC; /*!< [0x004c] EBI Security Policy Violation Source */ + __I uint32_t EBIVA; /*!< [0x0050] EBI Violation Address */ + __I uint32_t USBHVSRC; /*!< [0x0054] USBH Security Policy Violation Source */ + __I uint32_t USBHVA; /*!< [0x0058] USBH Violation Address */ + __I uint32_t CRCVSRC; /*!< [0x005c] CRC Security Policy Violation Source */ + __I uint32_t CRCVA; /*!< [0x0060] CRC Violation Address */ + __I uint32_t SD0VSRC; /*!< [0x0064] SDH0 Security Policy Violation Source */ + __I uint32_t SD0VA; /*!< [0x0068] SDH0 Violation Address */ + __I uint32_t RESERVE1[2]; + __I uint32_t PDMA0VSRC; /*!< [0x0074] PDMA0 Security Policy Violation Source */ + __I uint32_t PDMA0VA; /*!< [0x0078] PDMA0 Violation Address */ + __I uint32_t PDMA1VSRC; /*!< [0x007c] PDMA1 Security Policy Violation Source */ + __I uint32_t PDMA1VA; /*!< [0x0080] PDMA1 Violation Address */ + __I uint32_t SRAM0VSRC; /*!< [0x0084] SRAM0 Security Policy Violation Source */ + __I uint32_t SRAM0VA; /*!< [0x0088] SRAM0 Violation Address */ + __I uint32_t SRAM1VSRC; /*!< [0x008c] SRAM1 Security Policy Violation Source */ + __I uint32_t SRAM1VA; /*!< [0x0090] SRAM1 Violation Address */ + __I uint32_t FMCVSRC; /*!< [0x0094] FMC Security Policy Violation Source */ + __I uint32_t FMCVA; /*!< [0x0098] FMC Violation Address */ + __I uint32_t FLASHVSRC; /*!< [0x009c] Flash Security Policy Violation Source */ + __I uint32_t FLASHVA; /*!< [0x00a0] Flash Violation Address */ + __I uint32_t SCUVSRC; /*!< [0x00a4] SCU Security Policy Violation Source */ + __I uint32_t SCUVA; /*!< [0x00a8] SCU Violation Address */ + __I uint32_t SYSVSRC; /*!< [0x00ac] System(GMISC) Security Policy Violation Source */ + __I uint32_t SYSVA; /*!< [0x00b0] System(GMISC) Violation Address */ + __I uint32_t CRPTVSRC; /*!< [0x00b4] Crypto Security Policy Violation Source */ + __I uint32_t CRPTVA; /*!< [0x00b8] Crypto Violation Address */ + __I uint32_t KSVSRC; /*!< [0x00bc] KS Security Policy Violation Source */ + __I uint32_t KSVA; /*!< [0x00c0] KS Violation Address */ + __I uint32_t SRAM2VSRC; /*!< [0x00c4] SRAM2 Security Policy Violation Source */ + __I uint32_t SRAM2VA; /*!< [0x00c8] SRAM2 Violation Address */ + __I uint32_t RESERVE2[9]; + __IO uint32_t SINFAEN; /*!< [0x00f0] Shared Information Access Enable Register */ + __I uint32_t RESERVE3[3]; + __IO uint32_t PNPSET[7]; /*!< [0x0100:0x0118] Peripheral Non-privileged Attribution Set Register0 (0x4000_0000~0x400D_FFFF) */ + __I uint32_t RESERVE4[1]; + __IO uint32_t IONPSET; /*!< [0x0120] IO Non-privileged Attribution Set Register */ + __IO uint32_t SRAMNPSET; /*!< [0x0124] SRAM Non-privileged Attribution Set Register */ + __IO uint32_t MEMNPSET; /*!< [0x0128] Other Memory Non-privileged Attribution Set Register */ + __IO uint32_t PVIOIEN; /*!< [0x012c] Privileged Violation Interrupt Enable Register */ + __IO uint32_t PVINTSTS; /*!< [0x0130] Privileged Violation Interrupt Status Register */ + __I uint32_t RESERVE5[3]; + __IO uint32_t IONSSET[8]; /*!< [0x0140:0x015C] IO Non-secure Attribution Set Register */ + __I uint32_t RESERVE6[40]; + __IO uint32_t NSMCTL; /*!< [0x0200] Non-secure State Monitor Control Register */ + __IO uint32_t NSMLOAD; /*!< [0x0204] Non-secure State Monitor Reload Value Register */ + __IO uint32_t NSMVAL; /*!< [0x0208] Non-secure State Monitor Counter Value Register */ + __IO uint32_t NSMSTS; /*!< [0x020c] Non-secure State Monitor Status Register */ + __I uint32_t RESERVE7[60]; + __IO uint32_t BBE; /*!< [0x0300] Block Bus Error Register */ + __IO uint32_t IDAUANS; /*!< [0x0304] IDAU All Non-secure Set Register */ + __I uint32_t RESERVE8[829]; + __I uint32_t VERSION; /*!< [0x0ffc] SCU RTL Design Version Register */ + +} SCU_T; + +/** + @addtogroup SCU_CONST SCU Bit Field Definition + Constant Definitions for SCU Controller + @{ +*/ + +#define SCU_PNSSET0_USBH_Pos (9) /*!< SCU_T::PNSSET0: USBH Position */ +#define SCU_PNSSET0_USBH_Msk (0x1ul << SCU_PNSSET0_USBH_Pos) /*!< SCU_T::PNSSET0: USBH Mask */ + +#define SCU_PNSSET0_SDH0_Pos (13) /*!< SCU_T::PNSSET0: SDH0 Position */ +#define SCU_PNSSET0_SDH0_Msk (0x1ul << SCU_PNSSET0_SDH0_Pos) /*!< SCU_T::PNSSET0: SDH0 Mask */ + +#define SCU_PNSSET0_EBI_Pos (16) /*!< SCU_T::PNSSET0: EBI Position */ +#define SCU_PNSSET0_EBI_Msk (0x1ul << SCU_PNSSET0_EBI_Pos) /*!< SCU_T::PNSSET0: EBI Mask */ + +#define SCU_PNSSET0_PDMA1_Pos (24) /*!< SCU_T::PNSSET0: PDMA1 Position */ +#define SCU_PNSSET0_PDMA1_Msk (0x1ul << SCU_PNSSET0_PDMA1_Pos) /*!< SCU_T::PNSSET0: PDMA1 Mask */ + +#define SCU_PNSSET1_CRC_Pos (17) /*!< SCU_T::PNSSET1: CRC Position */ +#define SCU_PNSSET1_CRC_Msk (0x1ul << SCU_PNSSET1_CRC_Pos) /*!< SCU_T::PNSSET1: CRC Mask */ + +#define SCU_PNSSET1_CRPT_Pos (18) /*!< SCU_T::PNSSET1: CRPT Position */ +#define SCU_PNSSET1_CRPT_Msk (0x1ul << SCU_PNSSET1_CRPT_Pos) /*!< SCU_T::PNSSET1: CRPT Mask */ + +#define SCU_PNSSET2_EWDT_Pos (2) /*!< SCU_T::PNSSET2: EWDT Position */ +#define SCU_PNSSET2_EWDT_Msk (0x1ul << SCU_PNSSET2_EWDT_Pos) /*!< SCU_T::PNSSET2: EWDT Mask */ + +#define SCU_PNSSET2_EADC_Pos (3) /*!< SCU_T::PNSSET2: EADC Position */ +#define SCU_PNSSET2_EADC_Msk (0x1ul << SCU_PNSSET2_EADC_Pos) /*!< SCU_T::PNSSET2: EADC Mask */ + +#define SCU_PNSSET2_ACMP01_Pos (5) /*!< SCU_T::PNSSET2: ACMP01 Position */ +#define SCU_PNSSET2_ACMP01_Msk (0x1ul << SCU_PNSSET2_ACMP01_Pos) /*!< SCU_T::PNSSET2: ACMP01 Mask */ + +#define SCU_PNSSET2_DAC_Pos (7) /*!< SCU_T::PNSSET2: DAC Position */ +#define SCU_PNSSET2_DAC_Msk (0x1ul << SCU_PNSSET2_DAC_Pos) /*!< SCU_T::PNSSET2: DAC Mask */ + +#define SCU_PNSSET2_I2S0_Pos (8) /*!< SCU_T::PNSSET2: I2S0 Position */ +#define SCU_PNSSET2_I2S0_Msk (0x1ul << SCU_PNSSET2_I2S0_Pos) /*!< SCU_T::PNSSET2: I2S0 Mask */ + +#define SCU_PNSSET2_OTG_Pos (13) /*!< SCU_T::PNSSET2: OTG Position */ +#define SCU_PNSSET2_OTG_Msk (0x1ul << SCU_PNSSET2_OTG_Pos) /*!< SCU_T::PNSSET2: OTG Mask */ + +#define SCU_PNSSET2_TMR23_Pos (17) /*!< SCU_T::PNSSET2: TMR23 Position */ +#define SCU_PNSSET2_TMR23_Msk (0x1ul << SCU_PNSSET2_TMR23_Pos) /*!< SCU_T::PNSSET2: TMR23 Mask */ + +#define SCU_PNSSET2_EPWM0_Pos (24) /*!< SCU_T::PNSSET2: EPWM0 Position */ +#define SCU_PNSSET2_EPWM0_Msk (0x1ul << SCU_PNSSET2_EPWM0_Pos) /*!< SCU_T::PNSSET2: EPWM0 Mask */ + +#define SCU_PNSSET2_EPWM1_Pos (25) /*!< SCU_T::PNSSET2: EPWM1 Position */ +#define SCU_PNSSET2_EPWM1_Msk (0x1ul << SCU_PNSSET2_EPWM1_Pos) /*!< SCU_T::PNSSET2: EPWM1 Mask */ + +#define SCU_PNSSET2_BPWM0_Pos (26) /*!< SCU_T::PNSSET2: BPWM0 Position */ +#define SCU_PNSSET2_BPWM0_Msk (0x1ul << SCU_PNSSET2_BPWM0_Pos) /*!< SCU_T::PNSSET2: BPWM0 Mask */ + +#define SCU_PNSSET2_BPWM1_Pos (27) /*!< SCU_T::PNSSET2: BPWM1 Position */ +#define SCU_PNSSET2_BPWM1_Msk (0x1ul << SCU_PNSSET2_BPWM1_Pos) /*!< SCU_T::PNSSET2: BPWM1 Mask */ + +#define SCU_PNSSET3_QSPI0_Pos (0) /*!< SCU_T::PNSSET3: QSPI0 Position */ +#define SCU_PNSSET3_QSPI0_Msk (0x1ul << SCU_PNSSET3_QSPI0_Pos) /*!< SCU_T::PNSSET3: QSPI0 Mask */ + +#define SCU_PNSSET3_SPI0_Pos (1) /*!< SCU_T::PNSSET3: SPI0 Position */ +#define SCU_PNSSET3_SPI0_Msk (0x1ul << SCU_PNSSET3_SPI0_Pos) /*!< SCU_T::PNSSET3: SPI0 Mask */ + +#define SCU_PNSSET3_SPI1_Pos (2) /*!< SCU_T::PNSSET3: SPI1 Position */ +#define SCU_PNSSET3_SPI1_Msk (0x1ul << SCU_PNSSET3_SPI1_Pos) /*!< SCU_T::PNSSET3: SPI1 Mask */ + +#define SCU_PNSSET3_SPI2_Pos (3) /*!< SCU_T::PNSSET3: SPI2 Position */ +#define SCU_PNSSET3_SPI2_Msk (0x1ul << SCU_PNSSET3_SPI2_Pos) /*!< SCU_T::PNSSET3: SPI2 Mask */ + +#define SCU_PNSSET3_SPI3_Pos (4) /*!< SCU_T::PNSSET3: SPI3 Position */ +#define SCU_PNSSET3_SPI3_Msk (0x1ul << SCU_PNSSET3_SPI3_Pos) /*!< SCU_T::PNSSET3: SPI3 Mask */ + +#define SCU_PNSSET3_UART0_Pos (16) /*!< SCU_T::PNSSET3: UART0 Position */ +#define SCU_PNSSET3_UART0_Msk (0x1ul << SCU_PNSSET3_UART0_Pos) /*!< SCU_T::PNSSET3: UART0 Mask */ + +#define SCU_PNSSET3_UART1_Pos (17) /*!< SCU_T::PNSSET3: UART1 Position */ +#define SCU_PNSSET3_UART1_Msk (0x1ul << SCU_PNSSET3_UART1_Pos) /*!< SCU_T::PNSSET3: UART1 Mask */ + +#define SCU_PNSSET3_UART2_Pos (18) /*!< SCU_T::PNSSET3: UART2 Position */ +#define SCU_PNSSET3_UART2_Msk (0x1ul << SCU_PNSSET3_UART2_Pos) /*!< SCU_T::PNSSET3: UART2 Mask */ + +#define SCU_PNSSET3_UART3_Pos (19) /*!< SCU_T::PNSSET3: UART3 Position */ +#define SCU_PNSSET3_UART3_Msk (0x1ul << SCU_PNSSET3_UART3_Pos) /*!< SCU_T::PNSSET3: UART3 Mask */ + +#define SCU_PNSSET3_UART4_Pos (20) /*!< SCU_T::PNSSET3: UART4 Position */ +#define SCU_PNSSET3_UART4_Msk (0x1ul << SCU_PNSSET3_UART4_Pos) /*!< SCU_T::PNSSET3: UART4 Mask */ + +#define SCU_PNSSET3_UART5_Pos (21) /*!< SCU_T::PNSSET3: UART5 Position */ +#define SCU_PNSSET3_UART5_Msk (0x1ul << SCU_PNSSET3_UART5_Pos) /*!< SCU_T::PNSSET3: UART5 Mask */ + +#define SCU_PNSSET4_I2C0_Pos (0) /*!< SCU_T::PNSSET4: I2C0 Position */ +#define SCU_PNSSET4_I2C0_Msk (0x1ul << SCU_PNSSET4_I2C0_Pos) /*!< SCU_T::PNSSET4: I2C0 Mask */ + +#define SCU_PNSSET4_I2C1_Pos (1) /*!< SCU_T::PNSSET4: I2C1 Position */ +#define SCU_PNSSET4_I2C1_Msk (0x1ul << SCU_PNSSET4_I2C1_Pos) /*!< SCU_T::PNSSET4: I2C1 Mask */ + +#define SCU_PNSSET4_I2C2_Pos (2) /*!< SCU_T::PNSSET4: I2C2 Position */ +#define SCU_PNSSET4_I2C2_Msk (0x1ul << SCU_PNSSET4_I2C2_Pos) /*!< SCU_T::PNSSET4: I2C2 Mask */ + +#define SCU_PNSSET4_SC0_Pos (16) /*!< SCU_T::PNSSET4: SC0 Position */ +#define SCU_PNSSET4_SC0_Msk (0x1ul << SCU_PNSSET4_SC0_Pos) /*!< SCU_T::PNSSET4: SC0 Mask */ + +#define SCU_PNSSET4_SC1_Pos (17) /*!< SCU_T::PNSSET4: SC1 Position */ +#define SCU_PNSSET4_SC1_Msk (0x1ul << SCU_PNSSET4_SC1_Pos) /*!< SCU_T::PNSSET4: SC1 Mask */ + +#define SCU_PNSSET4_SC2_Pos (18) /*!< SCU_T::PNSSET4: SC2 Position */ +#define SCU_PNSSET4_SC2_Msk (0x1ul << SCU_PNSSET4_SC2_Pos) /*!< SCU_T::PNSSET4: SC2 Mask */ + +#define SCU_PNSSET5_CAN0_Pos (0) /*!< SCU_T::PNSSET5: CAN0 Position */ +#define SCU_PNSSET5_CAN0_Msk (0x1ul << SCU_PNSSET5_CAN0_Pos) /*!< SCU_T::PNSSET5: CAN0 Mask */ + +#define SCU_PNSSET5_QEI0_Pos (16) /*!< SCU_T::PNSSET5: QEI0 Position */ +#define SCU_PNSSET5_QEI0_Msk (0x1ul << SCU_PNSSET5_QEI0_Pos) /*!< SCU_T::PNSSET5: QEI0 Mask */ + +#define SCU_PNSSET5_QEI1_Pos (17) /*!< SCU_T::PNSSET5: QEI1 Position */ +#define SCU_PNSSET5_QEI1_Msk (0x1ul << SCU_PNSSET5_QEI1_Pos) /*!< SCU_T::PNSSET5: QEI1 Mask */ + +#define SCU_PNSSET5_ECAP0_Pos (20) /*!< SCU_T::PNSSET5: ECAP0 Position */ +#define SCU_PNSSET5_ECAP0_Msk (0x1ul << SCU_PNSSET5_ECAP0_Pos) /*!< SCU_T::PNSSET5: ECAP0 Mask */ + +#define SCU_PNSSET5_ECAP1_Pos (21) /*!< SCU_T::PNSSET5: ECAP1 Position */ +#define SCU_PNSSET5_ECAP1_Msk (0x1ul << SCU_PNSSET5_ECAP1_Pos) /*!< SCU_T::PNSSET5: ECAP1 Mask */ + +#define SCU_PNSSET5_TRNG_Pos (25) /*!< SCU_T::PNSSET5: TRNG Position */ +#define SCU_PNSSET5_TRNG_Msk (0x1ul << SCU_PNSSET5_TRNG_Pos) /*!< SCU_T::PNSSET5: TRNG Mask */ + +#define SCU_PNSSET5_LCD_Pos (27) /*!< SCU_T::PNSSET5: LCD Position */ +#define SCU_PNSSET5_LCD_Msk (0x1ul << SCU_PNSSET5_LCD_Pos) /*!< SCU_T::PNSSET5: LCD Mask */ + +#define SCU_PNSSET6_USBD_Pos (0) /*!< SCU_T::PNSSET6: USBD Position */ +#define SCU_PNSSET6_USBD_Msk (0x1ul << SCU_PNSSET6_USBD_Pos) /*!< SCU_T::PNSSET6: USBD Mask */ + +#define SCU_PNSSET6_USCI0_Pos (16) /*!< SCU_T::PNSSET6: USCI0 Position */ +#define SCU_PNSSET6_USCI0_Msk (0x1ul << SCU_PNSSET6_USCI0_Pos) /*!< SCU_T::PNSSET6: USCI0 Mask */ + +#define SCU_PNSSET6_USCI1_Pos (17) /*!< SCU_T::PNSSET6: USCI1 Position */ +#define SCU_PNSSET6_USCI1_Msk (0x1ul << SCU_PNSSET6_USCI1_Pos) /*!< SCU_T::PNSSET6: USCI1 Mask */ + +#define SCU_IONSSET_PA_Pos (0) /*!< SCU_T::IONSSET: PA Position */ +#define SCU_IONSSET_PA_Msk (0x1ul << SCU_IONSSET_PA_Pos) /*!< SCU_T::IONSSET: PA Mask */ + +#define SCU_IONSSET_PB_Pos (1) /*!< SCU_T::IONSSET: PB Position */ +#define SCU_IONSSET_PB_Msk (0x1ul << SCU_IONSSET_PB_Pos) /*!< SCU_T::IONSSET: PB Mask */ + +#define SCU_IONSSET_PC_Pos (2) /*!< SCU_T::IONSSET: PC Position */ +#define SCU_IONSSET_PC_Msk (0x1ul << SCU_IONSSET_PC_Pos) /*!< SCU_T::IONSSET: PC Mask */ + +#define SCU_IONSSET_PD_Pos (3) /*!< SCU_T::IONSSET: PD Position */ +#define SCU_IONSSET_PD_Msk (0x1ul << SCU_IONSSET_PD_Pos) /*!< SCU_T::IONSSET: PD Mask */ + +#define SCU_IONSSET_PE_Pos (4) /*!< SCU_T::IONSSET: PE Position */ +#define SCU_IONSSET_PE_Msk (0x1ul << SCU_IONSSET_PE_Pos) /*!< SCU_T::IONSSET: PE Mask */ + +#define SCU_IONSSET_PF_Pos (5) /*!< SCU_T::IONSSET: PF Position */ +#define SCU_IONSSET_PF_Msk (0x1ul << SCU_IONSSET_PF_Pos) /*!< SCU_T::IONSSET: PF Mask */ + +#define SCU_IONSSET_PG_Pos (6) /*!< SCU_T::IONSSET: PG Position */ +#define SCU_IONSSET_PG_Msk (0x1ul << SCU_IONSSET_PG_Pos) /*!< SCU_T::IONSSET: PG Mask */ + +#define SCU_IONSSET_PH_Pos (7) /*!< SCU_T::IONSSET: PH Position */ +#define SCU_IONSSET_PH_Msk (0x1ul << SCU_IONSSET_PH_Pos) /*!< SCU_T::IONSSET: PH Mask */ + +#define SCU_SRAMNSSET_SECn_Pos (0) /*!< SCU_T::SRAMNSSET: SECn Position */ +#define SCU_SRAMNSSET_SECn_Msk (0xffful << SCU_SRAMNSSET_SECn_Pos) /*!< SCU_T::SRAMNSSET: SECn Mask */ + +#define SCU_FNSADDR_FNSADDR_Pos (0) /*!< SCU_T::FNSADDR: FNSADDR Position */ +#define SCU_FNSADDR_FNSADDR_Msk (0xfffffffful << SCU_FNSADDR_FNSADDR_Pos) /*!< SCU_T::FNSADDR: FNSADDR Mask */ + +#define SCU_SVIOIEN_APB0IEN_Pos (0) /*!< SCU_T::SVIOIEN: APB0IEN Position */ +#define SCU_SVIOIEN_APB0IEN_Msk (0x1ul << SCU_SVIOIEN_APB0IEN_Pos) /*!< SCU_T::SVIOIEN: APB0IEN Mask */ + +#define SCU_SVIOIEN_APB1IEN_Pos (1) /*!< SCU_T::SVIOIEN: APB1IEN Position */ +#define SCU_SVIOIEN_APB1IEN_Msk (0x1ul << SCU_SVIOIEN_APB1IEN_Pos) /*!< SCU_T::SVIOIEN: APB1IEN Mask */ + +#define SCU_SVIOIEN_GPIOIEN_Pos (4) /*!< SCU_T::SVIOIEN: GPIOIEN Position */ +#define SCU_SVIOIEN_GPIOIEN_Msk (0x1ul << SCU_SVIOIEN_GPIOIEN_Pos) /*!< SCU_T::SVIOIEN: GPIOIEN Mask */ + +#define SCU_SVIOIEN_EBIIEN_Pos (5) /*!< SCU_T::SVIOIEN: EBIIEN Position */ +#define SCU_SVIOIEN_EBIIEN_Msk (0x1ul << SCU_SVIOIEN_EBIIEN_Pos) /*!< SCU_T::SVIOIEN: EBIIEN Mask */ + +#define SCU_SVIOIEN_USBHIEN_Pos (6) /*!< SCU_T::SVIOIEN: USBHIEN Position */ +#define SCU_SVIOIEN_USBHIEN_Msk (0x1ul << SCU_SVIOIEN_USBHIEN_Pos) /*!< SCU_T::SVIOIEN: USBHIEN Mask */ + +#define SCU_SVIOIEN_CRCIEN_Pos (7) /*!< SCU_T::SVIOIEN: CRCIEN Position */ +#define SCU_SVIOIEN_CRCIEN_Msk (0x1ul << SCU_SVIOIEN_CRCIEN_Pos) /*!< SCU_T::SVIOIEN: CRCIEN Mask */ + +#define SCU_SVIOIEN_SDH0IEN_Pos (8) /*!< SCU_T::SVIOIEN: SDH0IEN Position */ +#define SCU_SVIOIEN_SDH0IEN_Msk (0x1ul << SCU_SVIOIEN_SDH0IEN_Pos) /*!< SCU_T::SVIOIEN: SDH0IEN Mask */ + +#define SCU_SVIOIEN_PDMA0IEN_Pos (10) /*!< SCU_T::SVIOIEN: PDMA0IEN Position */ +#define SCU_SVIOIEN_PDMA0IEN_Msk (0x1ul << SCU_SVIOIEN_PDMA0IEN_Pos) /*!< SCU_T::SVIOIEN: PDMA0IEN Mask */ + +#define SCU_SVIOIEN_PDMA1IEN_Pos (11) /*!< SCU_T::SVIOIEN: PDMA1IEN Position */ +#define SCU_SVIOIEN_PDMA1IEN_Msk (0x1ul << SCU_SVIOIEN_PDMA1IEN_Pos) /*!< SCU_T::SVIOIEN: PDMA1IEN Mask */ + +#define SCU_SVIOIEN_SRAM0IEN_Pos (12) /*!< SCU_T::SVIOIEN: SRAM0IEN Position */ +#define SCU_SVIOIEN_SRAM0IEN_Msk (0x1ul << SCU_SVIOIEN_SRAM0IEN_Pos) /*!< SCU_T::SVIOIEN: SRAM0IEN Mask */ + +#define SCU_SVIOIEN_SRAM1IEN_Pos (13) /*!< SCU_T::SVIOIEN: SRAM1IEN Position */ +#define SCU_SVIOIEN_SRAM1IEN_Msk (0x1ul << SCU_SVIOIEN_SRAM1IEN_Pos) /*!< SCU_T::SVIOIEN: SRAM1IEN Mask */ + +#define SCU_SVIOIEN_FMCIEN_Pos (14) /*!< SCU_T::SVIOIEN: FMCIEN Position */ +#define SCU_SVIOIEN_FMCIEN_Msk (0x1ul << SCU_SVIOIEN_FMCIEN_Pos) /*!< SCU_T::SVIOIEN: FMCIEN Mask */ + +#define SCU_SVIOIEN_FLASHIEN_Pos (15) /*!< SCU_T::SVIOIEN: FLASHIEN Position */ +#define SCU_SVIOIEN_FLASHIEN_Msk (0x1ul << SCU_SVIOIEN_FLASHIEN_Pos) /*!< SCU_T::SVIOIEN: FLASHIEN Mask */ + +#define SCU_SVIOIEN_SCUIEN_Pos (16) /*!< SCU_T::SVIOIEN: SCUIEN Position */ +#define SCU_SVIOIEN_SCUIEN_Msk (0x1ul << SCU_SVIOIEN_SCUIEN_Pos) /*!< SCU_T::SVIOIEN: SCUIEN Mask */ + +#define SCU_SVIOIEN_SYSIEN_Pos (17) /*!< SCU_T::SVIOIEN: SYSIEN Position */ +#define SCU_SVIOIEN_SYSIEN_Msk (0x1ul << SCU_SVIOIEN_SYSIEN_Pos) /*!< SCU_T::SVIOIEN: SYSIEN Mask */ + +#define SCU_SVIOIEN_CRPTIEN_Pos (18) /*!< SCU_T::SVIOIEN: CRPTIEN Position */ +#define SCU_SVIOIEN_CRPTIEN_Msk (0x1ul << SCU_SVIOIEN_CRPTIEN_Pos) /*!< SCU_T::SVIOIEN: CRPTIEN Mask */ + +#define SCU_SVIOIEN_KSIEN_Pos (19) /*!< SCU_T::SVIOIEN: KSIEN Position */ +#define SCU_SVIOIEN_KSIEN_Msk (0x1ul << SCU_SVIOIEN_KSIEN_Pos) /*!< SCU_T::SVIOIEN: KSIEN Mask */ + +#define SCU_SVINTSTS_APB0IF_Pos (0) /*!< SCU_T::SVINTSTS: APB0IF Position */ +#define SCU_SVINTSTS_APB0IF_Msk (0x1ul << SCU_SVINTSTS_APB0IF_Pos) /*!< SCU_T::SVINTSTS: APB0IF Mask */ + +#define SCU_SVINTSTS_APB1IF_Pos (1) /*!< SCU_T::SVINTSTS: APB1IF Position */ +#define SCU_SVINTSTS_APB1IF_Msk (0x1ul << SCU_SVINTSTS_APB1IF_Pos) /*!< SCU_T::SVINTSTS: APB1IF Mask */ + +#define SCU_SVINTSTS_GPIOIF_Pos (4) /*!< SCU_T::SVINTSTS: GPIOIF Position */ +#define SCU_SVINTSTS_GPIOIF_Msk (0x1ul << SCU_SVINTSTS_GPIOIF_Pos) /*!< SCU_T::SVINTSTS: GPIOIF Mask */ + +#define SCU_SVINTSTS_EBIIF_Pos (5) /*!< SCU_T::SVINTSTS: EBIIF Position */ +#define SCU_SVINTSTS_EBIIF_Msk (0x1ul << SCU_SVINTSTS_EBIIF_Pos) /*!< SCU_T::SVINTSTS: EBIIF Mask */ + +#define SCU_SVINTSTS_USBHIF_Pos (6) /*!< SCU_T::SVINTSTS: USBHIF Position */ +#define SCU_SVINTSTS_USBHIF_Msk (0x1ul << SCU_SVINTSTS_USBHIF_Pos) /*!< SCU_T::SVINTSTS: USBHIF Mask */ + +#define SCU_SVINTSTS_CRCIF_Pos (7) /*!< SCU_T::SVINTSTS: CRCIF Position */ +#define SCU_SVINTSTS_CRCIF_Msk (0x1ul << SCU_SVINTSTS_CRCIF_Pos) /*!< SCU_T::SVINTSTS: CRCIF Mask */ + +#define SCU_SVINTSTS_SDH0IF_Pos (8) /*!< SCU_T::SVINTSTS: SDH0IF Position */ +#define SCU_SVINTSTS_SDH0IF_Msk (0x1ul << SCU_SVINTSTS_SDH0IF_Pos) /*!< SCU_T::SVINTSTS: SDH0IF Mask */ + +#define SCU_SVINTSTS_PDMA0IF_Pos (10) /*!< SCU_T::SVINTSTS: PDMA0IF Position */ +#define SCU_SVINTSTS_PDMA0IF_Msk (0x1ul << SCU_SVINTSTS_PDMA0IF_Pos) /*!< SCU_T::SVINTSTS: PDMA0IF Mask */ + +#define SCU_SVINTSTS_PDMA1IF_Pos (11) /*!< SCU_T::SVINTSTS: PDMA1IF Position */ +#define SCU_SVINTSTS_PDMA1IF_Msk (0x1ul << SCU_SVINTSTS_PDMA1IF_Pos) /*!< SCU_T::SVINTSTS: PDMA1IF Mask */ + +#define SCU_SVINTSTS_SRAM0IF_Pos (12) /*!< SCU_T::SVINTSTS: SRAM0IF Position */ +#define SCU_SVINTSTS_SRAM0IF_Msk (0x1ul << SCU_SVINTSTS_SRAM0IF_Pos) /*!< SCU_T::SVINTSTS: SRAM0IF Mask */ + +#define SCU_SVINTSTS_SRAM1IF_Pos (13) /*!< SCU_T::SVINTSTS: SRAM1IF Position */ +#define SCU_SVINTSTS_SRAM1IF_Msk (0x1ul << SCU_SVINTSTS_SRAM1IF_Pos) /*!< SCU_T::SVINTSTS: SRAM1IF Mask */ + +#define SCU_SVINTSTS_FMCIF_Pos (14) /*!< SCU_T::SVINTSTS: FMCIF Position */ +#define SCU_SVINTSTS_FMCIF_Msk (0x1ul << SCU_SVINTSTS_FMCIF_Pos) /*!< SCU_T::SVINTSTS: FMCIF Mask */ + +#define SCU_SVINTSTS_FLASHIF_Pos (15) /*!< SCU_T::SVINTSTS: FLASHIF Position */ +#define SCU_SVINTSTS_FLASHIF_Msk (0x1ul << SCU_SVINTSTS_FLASHIF_Pos) /*!< SCU_T::SVINTSTS: FLASHIF Mask */ + +#define SCU_SVINTSTS_SCUIF_Pos (16) /*!< SCU_T::SVINTSTS: SCUIF Position */ +#define SCU_SVINTSTS_SCUIF_Msk (0x1ul << SCU_SVINTSTS_SCUIF_Pos) /*!< SCU_T::SVINTSTS: SCUIF Mask */ + +#define SCU_SVINTSTS_SYSIF_Pos (17) /*!< SCU_T::SVINTSTS: SYSIF Position */ +#define SCU_SVINTSTS_SYSIF_Msk (0x1ul << SCU_SVINTSTS_SYSIF_Pos) /*!< SCU_T::SVINTSTS: SYSIF Mask */ + +#define SCU_SVINTSTS_CRPTIF_Pos (18) /*!< SCU_T::SVINTSTS: CRPTIF Position */ +#define SCU_SVINTSTS_CRPTIF_Msk (0x1ul << SCU_SVINTSTS_CRPTIF_Pos) /*!< SCU_T::SVINTSTS: CRPTIF Mask */ + +#define SCU_SVINTSTS_KSIF_Pos (19) /*!< SCU_T::SVINTSTS: KSIF Position */ +#define SCU_SVINTSTS_KSIF_Msk (0x1ul << SCU_SVINTSTS_KSIF_Pos) /*!< SCU_T::SVINTSTS: KSIF Mask */ + +#define SCU_APB0VSRC_MASTER_Pos (0) /*!< SCU_T::APB0VSRC: MASTER Position */ +#define SCU_APB0VSRC_MASTER_Msk (0xful << SCU_APB0VSRC_MASTER_Pos) /*!< SCU_T::APB0VSRC: MASTER Mask */ + +#define SCU_APB0VA_VIOADDR_Pos (0) /*!< SCU_T::APB0VA: VIOADDR Position */ +#define SCU_APB0VA_VIOADDR_Msk (0xfffffffful << SCU_APB0VA_VIOADDR_Pos) /*!< SCU_T::APB0VA: VIOADDR Mask */ + +#define SCU_APB1VSRC_MASTER_Pos (0) /*!< SCU_T::APB1VSRC: MASTER Position */ +#define SCU_APB1VSRC_MASTER_Msk (0xful << SCU_APB1VSRC_MASTER_Pos) /*!< SCU_T::APB1VSRC: MASTER Mask */ + +#define SCU_APB1VA_VIOADDR_Pos (0) /*!< SCU_T::APB1VA: VIOADDR Position */ +#define SCU_APB1VA_VIOADDR_Msk (0xfffffffful << SCU_APB1VA_VIOADDR_Pos) /*!< SCU_T::APB1VA: VIOADDR Mask */ + +#define SCU_GPIOVSRC_MASTER_Pos (0) /*!< SCU_T::GPIOVSRC: MASTER Position */ +#define SCU_GPIOVSRC_MASTER_Msk (0xful << SCU_GPIOVSRC_MASTER_Pos) /*!< SCU_T::GPIOVSRC: MASTER Mask */ + +#define SCU_GPIOVA_VIOADDR_Pos (0) /*!< SCU_T::GPIOVA: VIOADDR Position */ +#define SCU_GPIOVA_VIOADDR_Msk (0xfffffffful << SCU_GPIOVA_VIOADDR_Pos) /*!< SCU_T::GPIOVA: VIOADDR Mask */ + +#define SCU_EBIVSRC_MASTER_Pos (0) /*!< SCU_T::EBIVSRC: MASTER Position */ +#define SCU_EBIVSRC_MASTER_Msk (0xful << SCU_EBIVSRC_MASTER_Pos) /*!< SCU_T::EBIVSRC: MASTER Mask */ + +#define SCU_EBIVA_VIOADDR_Pos (0) /*!< SCU_T::EBIVA: VIOADDR Position */ +#define SCU_EBIVA_VIOADDR_Msk (0xfffffffful << SCU_EBIVA_VIOADDR_Pos) /*!< SCU_T::EBIVA: VIOADDR Mask */ + +#define SCU_USBHVSRC_MASTER_Pos (0) /*!< SCU_T::USBHVSRC: MASTER Position */ +#define SCU_USBHVSRC_MASTER_Msk (0xful << SCU_USBHVSRC_MASTER_Pos) /*!< SCU_T::USBHVSRC: MASTER Mask */ + +#define SCU_USBHVA_VIOADDR_Pos (0) /*!< SCU_T::USBHVA: VIOADDR Position */ +#define SCU_USBHVA_VIOADDR_Msk (0xfffffffful << SCU_USBHVA_VIOADDR_Pos) /*!< SCU_T::USBHVA: VIOADDR Mask */ + +#define SCU_CRCVSRC_MASTER_Pos (0) /*!< SCU_T::CRCVSRC: MASTER Position */ +#define SCU_CRCVSRC_MASTER_Msk (0xful << SCU_CRCVSRC_MASTER_Pos) /*!< SCU_T::CRCVSRC: MASTER Mask */ + +#define SCU_CRCVA_VIOADDR_Pos (0) /*!< SCU_T::CRCVA: VIOADDR Position */ +#define SCU_CRCVA_VIOADDR_Msk (0xfffffffful << SCU_CRCVA_VIOADDR_Pos) /*!< SCU_T::CRCVA: VIOADDR Mask */ + +#define SCU_SD0VSRC_MASTER_Pos (0) /*!< SCU_T::SD0VSRC: MASTER Position */ +#define SCU_SD0VSRC_MASTER_Msk (0xful << SCU_SD0VSRC_MASTER_Pos) /*!< SCU_T::SD0VSRC: MASTER Mask */ + +#define SCU_SD0VA_VIOADDR_Pos (0) /*!< SCU_T::SD0VA: VIOADDR Position */ +#define SCU_SD0VA_VIOADDR_Msk (0xfffffffful << SCU_SD0VA_VIOADDR_Pos) /*!< SCU_T::SD0VA: VIOADDR Mask */ + +#define SCU_PDMA0VSRC_MASTER_Pos (0) /*!< SCU_T::PDMA0VSRC: MASTER Position */ +#define SCU_PDMA0VSRC_MASTER_Msk (0xful << SCU_PDMA0VSRC_MASTER_Pos) /*!< SCU_T::PDMA0VSRC: MASTER Mask */ + +#define SCU_PDMA0VA_VIOADDR_Pos (0) /*!< SCU_T::PDMA0VA: VIOADDR Position */ +#define SCU_PDMA0VA_VIOADDR_Msk (0xfffffffful << SCU_PDMA0VA_VIOADDR_Pos) /*!< SCU_T::PDMA0VA: VIOADDR Mask */ + +#define SCU_PDMA1VSRC_MASTER_Pos (0) /*!< SCU_T::PDMA1VSRC: MASTER Position */ +#define SCU_PDMA1VSRC_MASTER_Msk (0xful << SCU_PDMA1VSRC_MASTER_Pos) /*!< SCU_T::PDMA1VSRC: MASTER Mask */ + +#define SCU_PDMA1VA_VIOADDR_Pos (0) /*!< SCU_T::PDMA1VA: VIOADDR Position */ +#define SCU_PDMA1VA_VIOADDR_Msk (0xfffffffful << SCU_PDMA1VA_VIOADDR_Pos) /*!< SCU_T::PDMA1VA: VIOADDR Mask */ + +#define SCU_SRAM0VSRC_MASTER_Pos (0) /*!< SCU_T::SRAM0VSRC: MASTER Position */ +#define SCU_SRAM0VSRC_MASTER_Msk (0xful << SCU_SRAM0VSRC_MASTER_Pos) /*!< SCU_T::SRAM0VSRC: MASTER Mask */ + +#define SCU_SRAM0VA_VIOADDR_Pos (0) /*!< SCU_T::SRAM0VA: VIOADDR Position */ +#define SCU_SRAM0VA_VIOADDR_Msk (0xfffffffful << SCU_SRAM0VA_VIOADDR_Pos) /*!< SCU_T::SRAM0VA: VIOADDR Mask */ + +#define SCU_SRAM1VSRC_MASTER_Pos (0) /*!< SCU_T::SRAM1VSRC: MASTER Position */ +#define SCU_SRAM1VSRC_MASTER_Msk (0xful << SCU_SRAM1VSRC_MASTER_Pos) /*!< SCU_T::SRAM1VSRC: MASTER Mask */ + +#define SCU_SRAM1VA_VIOADDR_Pos (0) /*!< SCU_T::SRAM1VA: VIOADDR Position */ +#define SCU_SRAM1VA_VIOADDR_Msk (0xfffffffful << SCU_SRAM1VA_VIOADDR_Pos) /*!< SCU_T::SRAM1VA: VIOADDR Mask */ + +#define SCU_FMCVSRC_MASTER_Pos (0) /*!< SCU_T::FMCVSRC: MASTER Position */ +#define SCU_FMCVSRC_MASTER_Msk (0xful << SCU_FMCVSRC_MASTER_Pos) /*!< SCU_T::FMCVSRC: MASTER Mask */ + +#define SCU_FMCVA_VIOADDR_Pos (0) /*!< SCU_T::FMCVA: VIOADDR Position */ +#define SCU_FMCVA_VIOADDR_Msk (0xfffffffful << SCU_FMCVA_VIOADDR_Pos) /*!< SCU_T::FMCVA: VIOADDR Mask */ + +#define SCU_FLASHVSRC_MASTER_Pos (0) /*!< SCU_T::FLASHVSRC: MASTER Position */ +#define SCU_FLASHVSRC_MASTER_Msk (0xful << SCU_FLASHVSRC_MASTER_Pos) /*!< SCU_T::FLASHVSRC: MASTER Mask */ + +#define SCU_FLASHVA_VIOADDR_Pos (0) /*!< SCU_T::FLASHVA: VIOADDR Position */ +#define SCU_FLASHVA_VIOADDR_Msk (0xfffffffful << SCU_FLASHVA_VIOADDR_Pos) /*!< SCU_T::FLASHVA: VIOADDR Mask */ + +#define SCU_SCUVSRC_MASTER_Pos (0) /*!< SCU_T::SCUVSRC: MASTER Position */ +#define SCU_SCUVSRC_MASTER_Msk (0xful << SCU_SCUVSRC_MASTER_Pos) /*!< SCU_T::SCUVSRC: MASTER Mask */ + +#define SCU_SCUVA_VIOADDR_Pos (0) /*!< SCU_T::SCUVA: VIOADDR Position */ +#define SCU_SCUVA_VIOADDR_Msk (0xfffffffful << SCU_SCUVA_VIOADDR_Pos) /*!< SCU_T::SCUVA: VIOADDR Mask */ + +#define SCU_SYSVSRC_MASTER_Pos (0) /*!< SCU_T::SYSVSRC: MASTER Position */ +#define SCU_SYSVSRC_MASTER_Msk (0xful << SCU_SYSVSRC_MASTER_Pos) /*!< SCU_T::SYSVSRC: MASTER Mask */ + +#define SCU_SYSVA_VIOADDR_Pos (0) /*!< SCU_T::SYSVA: VIOADDR Position */ +#define SCU_SYSVA_VIOADDR_Msk (0xfffffffful << SCU_SYSVA_VIOADDR_Pos) /*!< SCU_T::SYSVA: VIOADDR Mask */ + +#define SCU_CRPTVSRC_MASTER_Pos (0) /*!< SCU_T::CRPTVSRC: MASTER Position */ +#define SCU_CRPTVSRC_MASTER_Msk (0xful << SCU_CRPTVSRC_MASTER_Pos) /*!< SCU_T::CRPTVSRC: MASTER Mask */ + +#define SCU_CRPTVA_VIOADDR_Pos (0) /*!< SCU_T::CRPTVA: VIOADDR Position */ +#define SCU_CRPTVA_VIOADDR_Msk (0xfffffffful << SCU_CRPTVA_VIOADDR_Pos) /*!< SCU_T::CRPTVA: VIOADDR Mask */ + +#define SCU_KSVSRC_MASTER_Pos (0) /*!< SCU_T::KSVSRC: MASTER Position */ +#define SCU_KSVSRC_MASTER_Msk (0xful << SCU_KSVSRC_MASTER_Pos) /*!< SCU_T::KSVSRC: MASTER Mask */ + +#define SCU_KSVA_VIOADDR_Pos (0) /*!< SCU_T::KSVA: VIOADDR Position */ +#define SCU_KSVA_VIOADDR_Msk (0xfffffffful << SCU_KSVA_VIOADDR_Pos) /*!< SCU_T::KSVA: VIOADDR Mask */ + +#define SCU_SRAM2VSRC_MASTER_Pos (0) /*!< SCU_T::SRAM2VSRC: MASTER Position */ +#define SCU_SRAM2VSRC_MASTER_Msk (0xful << SCU_SRAM2VSRC_MASTER_Pos) /*!< SCU_T::SRAM2VSRC: MASTER Mask */ + +#define SCU_SRAM2VA_VIOADDR_Pos (0) /*!< SCU_T::SRAM2VA: VIOADDR Position */ +#define SCU_SRAM2VA_VIOADDR_Msk (0xfffffffful << SCU_SRAM2VA_VIOADDR_Pos) /*!< SCU_T::SRAM2VA: VIOADDR Mask */ + +#define SCU_SINFAEN_SCUSIAEN_Pos (0) /*!< SCU_T::SINFAEN: SCUSIAEN Position */ +#define SCU_SINFAEN_SCUSIAEN_Msk (0x1ul << SCU_SINFAEN_SCUSIAEN_Pos) /*!< SCU_T::SINFAEN: SCUSIAEN Mask */ + +#define SCU_SINFAEN_SYSSIAEN_Pos (1) /*!< SCU_T::SINFAEN: SYSSIAEN Position */ +#define SCU_SINFAEN_SYSSIAEN_Msk (0x1ul << SCU_SINFAEN_SYSSIAEN_Pos) /*!< SCU_T::SINFAEN: SYSSIAEN Mask */ + +#define SCU_SINFAEN_FMCSIAEN_Pos (2) /*!< SCU_T::SINFAEN: FMCSIAEN Position */ +#define SCU_SINFAEN_FMCSIAEN_Msk (0x1ul << SCU_SINFAEN_FMCSIAEN_Pos) /*!< SCU_T::SINFAEN: FMCSIAEN Mask */ + +#define SCU_PNPSET0_SYS_Pos (0) /*!< SCU_T::PNPSET0: SYS Position */ +#define SCU_PNPSET0_SYS_Msk (0x1ul << SCU_PNPSET0_SYS_Pos) /*!< SCU_T::PNPSET0: SYS Mask */ + +#define SCU_PNPSET0_PDMA0_Pos (8) /*!< SCU_T::PNPSET0: PDMA0 Position */ +#define SCU_PNPSET0_PDMA0_Msk (0x1ul << SCU_PNPSET0_PDMA0_Pos) /*!< SCU_T::PNPSET0: PDMA0 Mask */ + +#define SCU_PNPSET0_USBH_Pos (9) /*!< SCU_T::PNPSET0: USBH Position */ +#define SCU_PNPSET0_USBH_Msk (0x1ul << SCU_PNPSET0_USBH_Pos) /*!< SCU_T::PNPSET0: USBH Mask */ + +#define SCU_PNPSET0_FMC_Pos (12) /*!< SCU_T::PNPSET0: FMC Position */ +#define SCU_PNPSET0_FMC_Msk (0x1ul << SCU_PNPSET0_FMC_Pos) /*!< SCU_T::PNPSET0: FMC Mask */ + +#define SCU_PNPSET0_SDH0_Pos (13) /*!< SCU_T::PNPSET0: SDH0 Position */ +#define SCU_PNPSET0_SDH0_Msk (0x1ul << SCU_PNPSET0_SDH0_Pos) /*!< SCU_T::PNPSET0: SDH0 Mask */ + +#define SCU_PNPSET0_EBI_Pos (16) /*!< SCU_T::PNPSET0: EBI Position */ +#define SCU_PNPSET0_EBI_Msk (0x1ul << SCU_PNPSET0_EBI_Pos) /*!< SCU_T::PNPSET0: EBI Mask */ + +#define SCU_PNPSET0_PDMA1_Pos (24) /*!< SCU_T::PNPSET0: PDMA1 Position */ +#define SCU_PNPSET0_PDMA1_Msk (0x1ul << SCU_PNPSET0_PDMA1_Pos) /*!< SCU_T::PNPSET0: PDMA1 Mask */ + +#define SCU_PNPSET1_SCU_Pos (15) /*!< SCU_T::PNPSET1: SCU Position */ +#define SCU_PNPSET1_SCU_Msk (0x1ul << SCU_PNPSET1_SCU_Pos) /*!< SCU_T::PNPSET1: SCU Mask */ + +#define SCU_PNPSET1_CRC_Pos (17) /*!< SCU_T::PNPSET1: CRC Position */ +#define SCU_PNPSET1_CRC_Msk (0x1ul << SCU_PNPSET1_CRC_Pos) /*!< SCU_T::PNPSET1: CRC Mask */ + +#define SCU_PNPSET1_CRPT_Pos (18) /*!< SCU_T::PNPSET1: CRPT Position */ +#define SCU_PNPSET1_CRPT_Msk (0x1ul << SCU_PNPSET1_CRPT_Pos) /*!< SCU_T::PNPSET1: CRPT Mask */ + +#define SCU_PNPSET1_KS_Pos (21) /*!< SCU_T::PNPSET1: KS Position */ +#define SCU_PNPSET1_KS_Msk (0x1ul << SCU_PNPSET1_KS_Pos) /*!< SCU_T::PNPSET1: KS Mask */ + +#define SCU_PNPSET2_WDT_Pos (0) /*!< SCU_T::PNPSET2: WDT Position */ +#define SCU_PNPSET2_WDT_Msk (0x1ul << SCU_PNPSET2_WDT_Pos) /*!< SCU_T::PNPSET2: WDT Mask */ + +#define SCU_PNPSET2_RTC_Pos (1) /*!< SCU_T::PNPSET2: RTC Position */ +#define SCU_PNPSET2_RTC_Msk (0x1ul << SCU_PNPSET2_RTC_Pos) /*!< SCU_T::PNPSET2: RTC Mask */ + +#define SCU_PNPSET2_EWDT_Pos (2) /*!< SCU_T::PNPSET2: EWDT Position */ +#define SCU_PNPSET2_EWDT_Msk (0x1ul << SCU_PNPSET2_EWDT_Pos) /*!< SCU_T::PNPSET2: EWDT Mask */ + +#define SCU_PNPSET2_EADC_Pos (3) /*!< SCU_T::PNPSET2: EADC Position */ +#define SCU_PNPSET2_EADC_Msk (0x1ul << SCU_PNPSET2_EADC_Pos) /*!< SCU_T::PNPSET2: EADC Mask */ + +#define SCU_PNPSET2_ACMP01_Pos (5) /*!< SCU_T::PNPSET2: ACMP01 Position */ +#define SCU_PNPSET2_ACMP01_Msk (0x1ul << SCU_PNPSET2_ACMP01_Pos) /*!< SCU_T::PNPSET2: ACMP01 Mask */ + +#define SCU_PNPSET2_DAC_Pos (7) /*!< SCU_T::PNPSET2: DAC Position */ +#define SCU_PNPSET2_DAC_Msk (0x1ul << SCU_PNPSET2_DAC_Pos) /*!< SCU_T::PNPSET2: DAC Mask */ + +#define SCU_PNPSET2_I2S0_Pos (8) /*!< SCU_T::PNPSET2: I2S0 Position */ +#define SCU_PNPSET2_I2S0_Msk (0x1ul << SCU_PNPSET2_I2S0_Pos) /*!< SCU_T::PNPSET2: I2S0 Mask */ + +#define SCU_PNPSET2_OTG_Pos (13) /*!< SCU_T::PNPSET2: OTG Position */ +#define SCU_PNPSET2_OTG_Msk (0x1ul << SCU_PNPSET2_OTG_Pos) /*!< SCU_T::PNPSET2: OTG Mask */ + +#define SCU_PNPSET2_TMR01_Pos (14) /*!< SCU_T::PNPSET2: TMR01 Position */ +#define SCU_PNPSET2_TMR01_Msk (0x7ul << SCU_PNPSET2_TMR01_Pos) /*!< SCU_T::PNPSET2: TMR01 Mask */ + +#define SCU_PNPSET2_TMR23_Pos (17) /*!< SCU_T::PNPSET2: TMR23 Position */ +#define SCU_PNPSET2_TMR23_Msk (0x1ul << SCU_PNPSET2_TMR23_Pos) /*!< SCU_T::PNPSET2: TMR23 Mask */ + +#define SCU_PNPSET2_EPWM0_Pos (24) /*!< SCU_T::PNPSET2: EPWM0 Position */ +#define SCU_PNPSET2_EPWM0_Msk (0x1ul << SCU_PNPSET2_EPWM0_Pos) /*!< SCU_T::PNPSET2: EPWM0 Mask */ + +#define SCU_PNPSET2_EPWM1_Pos (25) /*!< SCU_T::PNPSET2: EPWM1 Position */ +#define SCU_PNPSET2_EPWM1_Msk (0x1ul << SCU_PNPSET2_EPWM1_Pos) /*!< SCU_T::PNPSET2: EPWM1 Mask */ + +#define SCU_PNPSET2_BPWM0_Pos (26) /*!< SCU_T::PNPSET2: BPWM0 Position */ +#define SCU_PNPSET2_BPWM0_Msk (0x1ul << SCU_PNPSET2_BPWM0_Pos) /*!< SCU_T::PNPSET2: BPWM0 Mask */ + +#define SCU_PNPSET2_BPWM1_Pos (27) /*!< SCU_T::PNPSET2: BPWM1 Position */ +#define SCU_PNPSET2_BPWM1_Msk (0x1ul << SCU_PNPSET2_BPWM1_Pos) /*!< SCU_T::PNPSET2: BPWM1 Mask */ + +#define SCU_PNPSET3_QSPI0_Pos (0) /*!< SCU_T::PNPSET3: QSPI0 Position */ +#define SCU_PNPSET3_QSPI0_Msk (0x1ul << SCU_PNPSET3_QSPI0_Pos) /*!< SCU_T::PNPSET3: QSPI0 Mask */ + +#define SCU_PNPSET3_SPI0_Pos (1) /*!< SCU_T::PNPSET3: SPI0 Position */ +#define SCU_PNPSET3_SPI0_Msk (0x1ul << SCU_PNPSET3_SPI0_Pos) /*!< SCU_T::PNPSET3: SPI0 Mask */ + +#define SCU_PNPSET3_SPI1_Pos (2) /*!< SCU_T::PNPSET3: SPI1 Position */ +#define SCU_PNPSET3_SPI1_Msk (0x1ul << SCU_PNPSET3_SPI1_Pos) /*!< SCU_T::PNPSET3: SPI1 Mask */ + +#define SCU_PNPSET3_SPI2_Pos (3) /*!< SCU_T::PNPSET3: SPI2 Position */ +#define SCU_PNPSET3_SPI2_Msk (0x1ul << SCU_PNPSET3_SPI2_Pos) /*!< SCU_T::PNPSET3: SPI2 Mask */ + +#define SCU_PNPSET3_SPI3_Pos (4) /*!< SCU_T::PNPSET3: SPI3 Position */ +#define SCU_PNPSET3_SPI3_Msk (0x1ul << SCU_PNPSET3_SPI3_Pos) /*!< SCU_T::PNPSET3: SPI3 Mask */ + +#define SCU_PNPSET3_UART0_Pos (16) /*!< SCU_T::PNPSET3: UART0 Position */ +#define SCU_PNPSET3_UART0_Msk (0x1ul << SCU_PNPSET3_UART0_Pos) /*!< SCU_T::PNPSET3: UART0 Mask */ + +#define SCU_PNPSET3_UART1_Pos (17) /*!< SCU_T::PNPSET3: UART1 Position */ +#define SCU_PNPSET3_UART1_Msk (0x1ul << SCU_PNPSET3_UART1_Pos) /*!< SCU_T::PNPSET3: UART1 Mask */ + +#define SCU_PNPSET3_UART2_Pos (18) /*!< SCU_T::PNPSET3: UART2 Position */ +#define SCU_PNPSET3_UART2_Msk (0x1ul << SCU_PNPSET3_UART2_Pos) /*!< SCU_T::PNPSET3: UART2 Mask */ + +#define SCU_PNPSET3_UART3_Pos (19) /*!< SCU_T::PNPSET3: UART3 Position */ +#define SCU_PNPSET3_UART3_Msk (0x1ul << SCU_PNPSET3_UART3_Pos) /*!< SCU_T::PNPSET3: UART3 Mask */ + +#define SCU_PNPSET3_UART4_Pos (20) /*!< SCU_T::PNPSET3: UART4 Position */ +#define SCU_PNPSET3_UART4_Msk (0x1ul << SCU_PNPSET3_UART4_Pos) /*!< SCU_T::PNPSET3: UART4 Mask */ + +#define SCU_PNPSET3_UART5_Pos (21) /*!< SCU_T::PNPSET3: UART5 Position */ +#define SCU_PNPSET3_UART5_Msk (0x1ul << SCU_PNPSET3_UART5_Pos) /*!< SCU_T::PNPSET3: UART5 Mask */ + +#define SCU_PNPSET4_I2C0_Pos (0) /*!< SCU_T::PNPSET4: I2C0 Position */ +#define SCU_PNPSET4_I2C0_Msk (0x1ul << SCU_PNPSET4_I2C0_Pos) /*!< SCU_T::PNPSET4: I2C0 Mask */ + +#define SCU_PNPSET4_I2C1_Pos (1) /*!< SCU_T::PNPSET4: I2C1 Position */ +#define SCU_PNPSET4_I2C1_Msk (0x1ul << SCU_PNPSET4_I2C1_Pos) /*!< SCU_T::PNPSET4: I2C1 Mask */ + +#define SCU_PNPSET4_I2C2_Pos (2) /*!< SCU_T::PNPSET4: I2C2 Position */ +#define SCU_PNPSET4_I2C2_Msk (0x1ul << SCU_PNPSET4_I2C2_Pos) /*!< SCU_T::PNPSET4: I2C2 Mask */ + +#define SCU_PNPSET4_SC0_Pos (16) /*!< SCU_T::PNPSET4: SC0 Position */ +#define SCU_PNPSET4_SC0_Msk (0x1ul << SCU_PNPSET4_SC0_Pos) /*!< SCU_T::PNPSET4: SC0 Mask */ + +#define SCU_PNPSET4_SC1_Pos (17) /*!< SCU_T::PNPSET4: SC1 Position */ +#define SCU_PNPSET4_SC1_Msk (0x1ul << SCU_PNPSET4_SC1_Pos) /*!< SCU_T::PNPSET4: SC1 Mask */ + +#define SCU_PNPSET4_SC2_Pos (18) /*!< SCU_T::PNPSET4: SC2 Position */ +#define SCU_PNPSET4_SC2_Msk (0x1ul << SCU_PNPSET4_SC2_Pos) /*!< SCU_T::PNPSET4: SC2 Mask */ + +#define SCU_PNPSET5_CAN0_Pos (0) /*!< SCU_T::PNPSET5: CAN0 Position */ +#define SCU_PNPSET5_CAN0_Msk (0x1ul << SCU_PNPSET5_CAN0_Pos) /*!< SCU_T::PNPSET5: CAN0 Mask */ + +#define SCU_PNPSET5_QEI0_Pos (16) /*!< SCU_T::PNPSET5: QEI0 Position */ +#define SCU_PNPSET5_QEI0_Msk (0x1ul << SCU_PNPSET5_QEI0_Pos) /*!< SCU_T::PNPSET5: QEI0 Mask */ + +#define SCU_PNPSET5_QEI1_Pos (17) /*!< SCU_T::PNPSET5: QEI1 Position */ +#define SCU_PNPSET5_QEI1_Msk (0x1ul << SCU_PNPSET5_QEI1_Pos) /*!< SCU_T::PNPSET5: QEI1 Mask */ + +#define SCU_PNPSET5_ECAP0_Pos (20) /*!< SCU_T::PNPSET5: ECAP0 Position */ +#define SCU_PNPSET5_ECAP0_Msk (0x1ul << SCU_PNPSET5_ECAP0_Pos) /*!< SCU_T::PNPSET5: ECAP0 Mask */ + +#define SCU_PNPSET5_ECAP1_Pos (21) /*!< SCU_T::PNPSET5: ECAP1 Position */ +#define SCU_PNPSET5_ECAP1_Msk (0x1ul << SCU_PNPSET5_ECAP1_Pos) /*!< SCU_T::PNPSET5: ECAP1 Mask */ + +#define SCU_PNPSET5_TRNG_Pos (25) /*!< SCU_T::PNPSET5: TRNG Position */ +#define SCU_PNPSET5_TRNG_Msk (0x1ul << SCU_PNPSET5_TRNG_Pos) /*!< SCU_T::PNPSET5: TRNG Mask */ + +#define SCU_PNPSET5_LCD_Pos (27) /*!< SCU_T::PNPSET5: LCD Position */ +#define SCU_PNPSET5_LCD_Msk (0x1ul << SCU_PNPSET5_LCD_Pos) /*!< SCU_T::PNPSET5: LCD Mask */ + +#define SCU_PNPSET5_TAMPER_Pos (29) /*!< SCU_T::PNPSET5: TAMPER Position */ +#define SCU_PNPSET5_TAMPER_Msk (0x1ul << SCU_PNPSET5_TAMPER_Pos) /*!< SCU_T::PNPSET5: TAMPER Mask */ + +#define SCU_PNPSET6_USBD_Pos (0) /*!< SCU_T::PNPSET6: USBD Position */ +#define SCU_PNPSET6_USBD_Msk (0x1ul << SCU_PNPSET6_USBD_Pos) /*!< SCU_T::PNPSET6: USBD Mask */ + +#define SCU_PNPSET6_USCI0_Pos (16) /*!< SCU_T::PNPSET6: USCI0 Position */ +#define SCU_PNPSET6_USCI0_Msk (0x1ul << SCU_PNPSET6_USCI0_Pos) /*!< SCU_T::PNPSET6: USCI0 Mask */ + +#define SCU_PNPSET6_USCI1_Pos (17) /*!< SCU_T::PNPSET6: USCI1 Position */ +#define SCU_PNPSET6_USCI1_Msk (0x1ul << SCU_PNPSET6_USCI1_Pos) /*!< SCU_T::PNPSET6: USCI1 Mask */ + +#define SCU_IONPSET_PA_Pos (0) /*!< SCU_T::IONPSET: PA Position */ +#define SCU_IONPSET_PA_Msk (0x1ul << SCU_IONPSET_PA_Pos) /*!< SCU_T::IONPSET: PA Mask */ + +#define SCU_IONPSET_PB_Pos (1) /*!< SCU_T::IONPSET: PB Position */ +#define SCU_IONPSET_PB_Msk (0x1ul << SCU_IONPSET_PB_Pos) /*!< SCU_T::IONPSET: PB Mask */ + +#define SCU_IONPSET_PC_Pos (2) /*!< SCU_T::IONPSET: PC Position */ +#define SCU_IONPSET_PC_Msk (0x1ul << SCU_IONPSET_PC_Pos) /*!< SCU_T::IONPSET: PC Mask */ + +#define SCU_IONPSET_PD_Pos (3) /*!< SCU_T::IONPSET: PD Position */ +#define SCU_IONPSET_PD_Msk (0x1ul << SCU_IONPSET_PD_Pos) /*!< SCU_T::IONPSET: PD Mask */ + +#define SCU_IONPSET_PE_Pos (4) /*!< SCU_T::IONPSET: PE Position */ +#define SCU_IONPSET_PE_Msk (0x1ul << SCU_IONPSET_PE_Pos) /*!< SCU_T::IONPSET: PE Mask */ + +#define SCU_IONPSET_PF_Pos (5) /*!< SCU_T::IONPSET: PF Position */ +#define SCU_IONPSET_PF_Msk (0x1ul << SCU_IONPSET_PF_Pos) /*!< SCU_T::IONPSET: PF Mask */ + +#define SCU_IONPSET_PG_Pos (6) /*!< SCU_T::IONPSET: PG Position */ +#define SCU_IONPSET_PG_Msk (0x1ul << SCU_IONPSET_PG_Pos) /*!< SCU_T::IONPSET: PG Mask */ + +#define SCU_IONPSET_PH_Pos (7) /*!< SCU_T::IONPSET: PH Position */ +#define SCU_IONPSET_PH_Msk (0x1ul << SCU_IONPSET_PH_Pos) /*!< SCU_T::IONPSET: PH Mask */ + +#define SCU_SRAMNPSET_SECn_Pos (0) /*!< SCU_T::SRAMNPSET: SECn Position */ +#define SCU_SRAMNPSET_SECn_Msk (0xffffful << SCU_SRAMNPSET_SECn_Pos) /*!< SCU_T::SRAMNPSET: SECn Mask */ + +#define SCU_MEMNPSET_FLASH_Pos (0) /*!< SCU_T::MEMNPSET: FLASH Position */ +#define SCU_MEMNPSET_FLASH_Msk (0x1ul << SCU_MEMNPSET_FLASH_Pos) /*!< SCU_T::MEMNPSET: FLASH Mask */ + +#define SCU_MEMNPSET_EXTMEM_Pos (1) /*!< SCU_T::MEMNPSET: EXTMEM Position */ +#define SCU_MEMNPSET_EXTMEM_Msk (0x1ul << SCU_MEMNPSET_EXTMEM_Pos) /*!< SCU_T::MEMNPSET: EXTMEM Mask */ + +#define SCU_PVIOIEN_APB0IEN_Pos (0) /*!< SCU_T::PVIOIEN: APB0IEN Position */ +#define SCU_PVIOIEN_APB0IEN_Msk (0x1ul << SCU_PVIOIEN_APB0IEN_Pos) /*!< SCU_T::PVIOIEN: APB0IEN Mask */ + +#define SCU_PVIOIEN_APB1IEN_Pos (1) /*!< SCU_T::PVIOIEN: APB1IEN Position */ +#define SCU_PVIOIEN_APB1IEN_Msk (0x1ul << SCU_PVIOIEN_APB1IEN_Pos) /*!< SCU_T::PVIOIEN: APB1IEN Mask */ + +#define SCU_PVIOIEN_GPIOIEN_Pos (4) /*!< SCU_T::PVIOIEN: GPIOIEN Position */ +#define SCU_PVIOIEN_GPIOIEN_Msk (0x1ul << SCU_PVIOIEN_GPIOIEN_Pos) /*!< SCU_T::PVIOIEN: GPIOIEN Mask */ + +#define SCU_PVIOIEN_EBIIEN_Pos (5) /*!< SCU_T::PVIOIEN: EBIIEN Position */ +#define SCU_PVIOIEN_EBIIEN_Msk (0x1ul << SCU_PVIOIEN_EBIIEN_Pos) /*!< SCU_T::PVIOIEN: EBIIEN Mask */ + +#define SCU_PVIOIEN_USBHIEN_Pos (6) /*!< SCU_T::PVIOIEN: USBHIEN Position */ +#define SCU_PVIOIEN_USBHIEN_Msk (0x1ul << SCU_PVIOIEN_USBHIEN_Pos) /*!< SCU_T::PVIOIEN: USBHIEN Mask */ + +#define SCU_PVIOIEN_CRCIEN_Pos (7) /*!< SCU_T::PVIOIEN: CRCIEN Position */ +#define SCU_PVIOIEN_CRCIEN_Msk (0x1ul << SCU_PVIOIEN_CRCIEN_Pos) /*!< SCU_T::PVIOIEN: CRCIEN Mask */ + +#define SCU_PVIOIEN_SDH0IEN_Pos (8) /*!< SCU_T::PVIOIEN: SDH0IEN Position */ +#define SCU_PVIOIEN_SDH0IEN_Msk (0x1ul << SCU_PVIOIEN_SDH0IEN_Pos) /*!< SCU_T::PVIOIEN: SDH0IEN Mask */ + +#define SCU_PVIOIEN_PDMA0IEN_Pos (10) /*!< SCU_T::PVIOIEN: PDMA0IEN Position */ +#define SCU_PVIOIEN_PDMA0IEN_Msk (0x1ul << SCU_PVIOIEN_PDMA0IEN_Pos) /*!< SCU_T::PVIOIEN: PDMA0IEN Mask */ + +#define SCU_PVIOIEN_PDMA1IEN_Pos (11) /*!< SCU_T::PVIOIEN: PDMA1IEN Position */ +#define SCU_PVIOIEN_PDMA1IEN_Msk (0x1ul << SCU_PVIOIEN_PDMA1IEN_Pos) /*!< SCU_T::PVIOIEN: PDMA1IEN Mask */ + +#define SCU_PVIOIEN_SRAM0IEN_Pos (12) /*!< SCU_T::PVIOIEN: SRAM0IEN Position */ +#define SCU_PVIOIEN_SRAM0IEN_Msk (0x1ul << SCU_PVIOIEN_SRAM0IEN_Pos) /*!< SCU_T::PVIOIEN: SRAM0IEN Mask */ + +#define SCU_PVIOIEN_SRAM1IEN_Pos (13) /*!< SCU_T::PVIOIEN: SRAM1IEN Position */ +#define SCU_PVIOIEN_SRAM1IEN_Msk (0x1ul << SCU_PVIOIEN_SRAM1IEN_Pos) /*!< SCU_T::PVIOIEN: SRAM1IEN Mask */ + +#define SCU_PVIOIEN_FMCIEN_Pos (14) /*!< SCU_T::PVIOIEN: FMCIEN Position */ +#define SCU_PVIOIEN_FMCIEN_Msk (0x1ul << SCU_PVIOIEN_FMCIEN_Pos) /*!< SCU_T::PVIOIEN: FMCIEN Mask */ + +#define SCU_PVIOIEN_FLASHIEN_Pos (15) /*!< SCU_T::PVIOIEN: FLASHIEN Position */ +#define SCU_PVIOIEN_FLASHIEN_Msk (0x1ul << SCU_PVIOIEN_FLASHIEN_Pos) /*!< SCU_T::PVIOIEN: FLASHIEN Mask */ + +#define SCU_PVIOIEN_SCUIEN_Pos (16) /*!< SCU_T::PVIOIEN: SCUIEN Position */ +#define SCU_PVIOIEN_SCUIEN_Msk (0x1ul << SCU_PVIOIEN_SCUIEN_Pos) /*!< SCU_T::PVIOIEN: SCUIEN Mask */ + +#define SCU_PVIOIEN_SYSIEN_Pos (17) /*!< SCU_T::PVIOIEN: SYSIEN Position */ +#define SCU_PVIOIEN_SYSIEN_Msk (0x1ul << SCU_PVIOIEN_SYSIEN_Pos) /*!< SCU_T::PVIOIEN: SYSIEN Mask */ + +#define SCU_PVIOIEN_CRPTIEN_Pos (18) /*!< SCU_T::PVIOIEN: CRPTIEN Position */ +#define SCU_PVIOIEN_CRPTIEN_Msk (0x1ul << SCU_PVIOIEN_CRPTIEN_Pos) /*!< SCU_T::PVIOIEN: CRPTIEN Mask */ + +#define SCU_PVIOIEN_KSIEN_Pos (19) /*!< SCU_T::PVIOIEN: KSIEN Position */ +#define SCU_PVIOIEN_KSIEN_Msk (0x1ul << SCU_PVIOIEN_KSIEN_Pos) /*!< SCU_T::PVIOIEN: KSIEN Mask */ + +#define SCU_PVINTSTS_APB0IF_Pos (0) /*!< SCU_T::PVINTSTS: APB0IF Position */ +#define SCU_PVINTSTS_APB0IF_Msk (0x1ul << SCU_PVINTSTS_APB0IF_Pos) /*!< SCU_T::PVINTSTS: APB0IF Mask */ + +#define SCU_PVINTSTS_APB1IF_Pos (1) /*!< SCU_T::PVINTSTS: APB1IF Position */ +#define SCU_PVINTSTS_APB1IF_Msk (0x1ul << SCU_PVINTSTS_APB1IF_Pos) /*!< SCU_T::PVINTSTS: APB1IF Mask */ + +#define SCU_PVINTSTS_GPIOIF_Pos (4) /*!< SCU_T::PVINTSTS: GPIOIF Position */ +#define SCU_PVINTSTS_GPIOIF_Msk (0x1ul << SCU_PVINTSTS_GPIOIF_Pos) /*!< SCU_T::PVINTSTS: GPIOIF Mask */ + +#define SCU_PVINTSTS_EBIIF_Pos (5) /*!< SCU_T::PVINTSTS: EBIIF Position */ +#define SCU_PVINTSTS_EBIIF_Msk (0x1ul << SCU_PVINTSTS_EBIIF_Pos) /*!< SCU_T::PVINTSTS: EBIIF Mask */ + +#define SCU_PVINTSTS_USBHIF_Pos (6) /*!< SCU_T::PVINTSTS: USBHIF Position */ +#define SCU_PVINTSTS_USBHIF_Msk (0x1ul << SCU_PVINTSTS_USBHIF_Pos) /*!< SCU_T::PVINTSTS: USBHIF Mask */ + +#define SCU_PVINTSTS_CRCIF_Pos (7) /*!< SCU_T::PVINTSTS: CRCIF Position */ +#define SCU_PVINTSTS_CRCIF_Msk (0x1ul << SCU_PVINTSTS_CRCIF_Pos) /*!< SCU_T::PVINTSTS: CRCIF Mask */ + +#define SCU_PVINTSTS_SDH0IF_Pos (8) /*!< SCU_T::PVINTSTS: SDH0IF Position */ +#define SCU_PVINTSTS_SDH0IF_Msk (0x1ul << SCU_PVINTSTS_SDH0IF_Pos) /*!< SCU_T::PVINTSTS: SDH0IF Mask */ + +#define SCU_PVINTSTS_PDMA0IF_Pos (10) /*!< SCU_T::PVINTSTS: PDMA0IF Position */ +#define SCU_PVINTSTS_PDMA0IF_Msk (0x1ul << SCU_PVINTSTS_PDMA0IF_Pos) /*!< SCU_T::PVINTSTS: PDMA0IF Mask */ + +#define SCU_PVINTSTS_PDMA1IF_Pos (11) /*!< SCU_T::PVINTSTS: PDMA1IF Position */ +#define SCU_PVINTSTS_PDMA1IF_Msk (0x1ul << SCU_PVINTSTS_PDMA1IF_Pos) /*!< SCU_T::PVINTSTS: PDMA1IF Mask */ + +#define SCU_PVINTSTS_SRAM0IF_Pos (12) /*!< SCU_T::PVINTSTS: SRAM0IF Position */ +#define SCU_PVINTSTS_SRAM0IF_Msk (0x1ul << SCU_PVINTSTS_SRAM0IF_Pos) /*!< SCU_T::PVINTSTS: SRAM0IF Mask */ + +#define SCU_PVINTSTS_SRAM1IF_Pos (13) /*!< SCU_T::PVINTSTS: SRAM1IF Position */ +#define SCU_PVINTSTS_SRAM1IF_Msk (0x1ul << SCU_PVINTSTS_SRAM1IF_Pos) /*!< SCU_T::PVINTSTS: SRAM1IF Mask */ + +#define SCU_PVINTSTS_FMCIF_Pos (14) /*!< SCU_T::PVINTSTS: FMCIF Position */ +#define SCU_PVINTSTS_FMCIF_Msk (0x1ul << SCU_PVINTSTS_FMCIF_Pos) /*!< SCU_T::PVINTSTS: FMCIF Mask */ + +#define SCU_PVINTSTS_FLASHIF_Pos (15) /*!< SCU_T::PVINTSTS: FLASHIF Position */ +#define SCU_PVINTSTS_FLASHIF_Msk (0x1ul << SCU_PVINTSTS_FLASHIF_Pos) /*!< SCU_T::PVINTSTS: FLASHIF Mask */ + +#define SCU_PVINTSTS_SCUIF_Pos (16) /*!< SCU_T::PVINTSTS: SCUIF Position */ +#define SCU_PVINTSTS_SCUIF_Msk (0x1ul << SCU_PVINTSTS_SCUIF_Pos) /*!< SCU_T::PVINTSTS: SCUIF Mask */ + +#define SCU_PVINTSTS_SYSIF_Pos (17) /*!< SCU_T::PVINTSTS: SYSIF Position */ +#define SCU_PVINTSTS_SYSIF_Msk (0x1ul << SCU_PVINTSTS_SYSIF_Pos) /*!< SCU_T::PVINTSTS: SYSIF Mask */ + +#define SCU_PVINTSTS_CRPTIF_Pos (18) /*!< SCU_T::PVINTSTS: CRPTIF Position */ +#define SCU_PVINTSTS_CRPTIF_Msk (0x1ul << SCU_PVINTSTS_CRPTIF_Pos) /*!< SCU_T::PVINTSTS: CRPTIF Mask */ + +#define SCU_PVINTSTS_KSIF_Pos (19) /*!< SCU_T::PVINTSTS: KSIF Position */ +#define SCU_PVINTSTS_KSIF_Msk (0x1ul << SCU_PVINTSTS_KSIF_Pos) /*!< SCU_T::PVINTSTS: KSIF Mask */ + +#define SCU_NSMCTL_PRESCALE_Pos (0) /*!< SCU_T::NSMCTL: PRESCALE Position */ +#define SCU_NSMCTL_PRESCALE_Msk (0xfful << SCU_NSMCTL_PRESCALE_Pos) /*!< SCU_T::NSMCTL: PRESCALE Mask */ + +#define SCU_NSMCTL_NSMIEN_Pos (8) /*!< SCU_T::NSMCTL: NSMIEN Position */ +#define SCU_NSMCTL_NSMIEN_Msk (0x1ul << SCU_NSMCTL_NSMIEN_Pos) /*!< SCU_T::NSMCTL: NSMIEN Mask */ + +#define SCU_NSMCTL_AUTORLD_Pos (9) /*!< SCU_T::NSMCTL: AUTORLD Position */ +#define SCU_NSMCTL_AUTORLD_Msk (0x1ul << SCU_NSMCTL_AUTORLD_Pos) /*!< SCU_T::NSMCTL: AUTORLD Mask */ + +#define SCU_NSMCTL_TMRMOD_Pos (10) /*!< SCU_T::NSMCTL: TMRMOD Position */ +#define SCU_NSMCTL_TMRMOD_Msk (0x1ul << SCU_NSMCTL_TMRMOD_Pos) /*!< SCU_T::NSMCTL: TMRMOD Mask */ + +#define SCU_NSMCTL_IDLEON_Pos (12) /*!< SCU_T::NSMCTL: IDLEON Position */ +#define SCU_NSMCTL_IDLEON_Msk (0x1ul << SCU_NSMCTL_IDLEON_Pos) /*!< SCU_T::NSMCTL: IDLEON Mask */ + +#define SCU_NSMCTL_DBGON_Pos (13) /*!< SCU_T::NSMCTL: DBGON Position */ +#define SCU_NSMCTL_DBGON_Msk (0x1ul << SCU_NSMCTL_DBGON_Pos) /*!< SCU_T::NSMCTL: DBGON Mask */ + +#define SCU_NSMLOAD_RELOAD_Pos (0) /*!< SCU_T::NSMLOAD: RELOAD Position */ +#define SCU_NSMLOAD_RELOAD_Msk (0xfffffful << SCU_NSMLOAD_RELOAD_Pos) /*!< SCU_T::NSMLOAD: RELOAD Mask */ + +#define SCU_NSMVAL_VALUE_Pos (0) /*!< SCU_T::NSMVAL: VALUE Position */ +#define SCU_NSMVAL_VALUE_Msk (0xfffffful << SCU_NSMVAL_VALUE_Pos) /*!< SCU_T::NSMVAL: VALUE Mask */ + +#define SCU_NSMSTS_CURRNS_Pos (0) /*!< SCU_T::NSMSTS: CURRNS Position */ +#define SCU_NSMSTS_CURRNS_Msk (0x1ul << SCU_NSMSTS_CURRNS_Pos) /*!< SCU_T::NSMSTS: CURRNS Mask */ + +#define SCU_NSMSTS_NSMIF_Pos (1) /*!< SCU_T::NSMSTS: NSMIF Position */ +#define SCU_NSMSTS_NSMIF_Msk (0x1ul << SCU_NSMSTS_NSMIF_Pos) /*!< SCU_T::NSMSTS: NSMIF Mask */ + +#define SCU_BBE_BBEEN_Pos (0) /*!< SCU_T::BBE: BBEEN Position */ +#define SCU_BBE_BBEEN_Msk (0x1ul << SCU_BBE_BBEEN_Pos) /*!< SCU_T::BBE: BBEEN Mask */ + +#define SCU_BBE_WVERY_Pos (8) /*!< SCU_T::BBE: WVERY Position */ +#define SCU_BBE_WVERY_Msk (0xfffffful << SCU_BBE_WVERY_Pos) /*!< SCU_T::BBE: WVERY Mask */ + +#define SCU_IDAUANS_IDAUANSEN_Pos (0) /*!< SCU_T::IDAUANS: IDAUANSEN Position */ +#define SCU_IDAUANS_IDAUANSEN_Msk (0x1ul << SCU_IDAUANS_IDAUANSEN_Pos) /*!< SCU_T::IDAUANS: IDAUANSEN Mask */ + +#define SCU_IDAUANS_WVERY_Pos (8) /*!< SCU_T::IDAUANS: WVERY Position */ +#define SCU_IDAUANS_WVERY_Msk (0xfffffful << SCU_IDAUANS_WVERY_Pos) /*!< SCU_T::IDAUANS: WVERY Mask */ + +#define SCU_VERSION_MINOR_Pos (0) /*!< SCU_T::VERSION: MINOR Position */ +#define SCU_VERSION_MINOR_Msk (0xfffful << SCU_VERSION_MINOR_Pos) /*!< SCU_T::VERSION: MINOR Mask */ + +#define SCU_VERSION_SUB_Pos (16) /*!< SCU_T::VERSION: SUB Position */ +#define SCU_VERSION_SUB_Msk (0xfful << SCU_VERSION_SUB_Pos) /*!< SCU_T::VERSION: SUB Mask */ + +#define SCU_VERSION_MAJOR_Pos (24) /*!< SCU_T::VERSION: MAJOR Position */ +#define SCU_VERSION_MAJOR_Msk (0xfful << SCU_VERSION_MAJOR_Pos) /*!< SCU_T::VERSION: MAJOR Mask */ + +/**@}*/ /* SCU_CONST */ +/**@}*/ /* end of SCU register group */ + + +/**@}*/ /* end of REGISTER group */ +#endif /* __SCU_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/sdh_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/sdh_reg.h new file mode 100644 index 0000000000..9b61c64107 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/sdh_reg.h @@ -0,0 +1,528 @@ +/**************************************************************************//** + * @file sdh_reg.h + * @version V1.00 + * @brief SDH register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SDH_REG_H__ +#define __SDH_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- SD Card Host Interface -------------------------*/ +/** + @addtogroup SDH SD Card Host Interface(SDH) + Memory Mapped Structure for SDH Controller + @{ +*/ + +typedef struct +{ + + /** + * @var SDH_T::FB + * Offset: 0x00~0x7C Shared Buffer (FIFO) + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |BUFFER |Shared Buffer + * | | |Buffer for DMA transfer + * @var SDH_T::DMACTL + * Offset: 0x400 DMA Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DMAEN |DMA Engine Enable Bit + * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state. + * | | |0 = DMA Disabled. + * | | |1 = DMA Enabled. + * | | |Note: If target abort is occurred, DMAEN will be cleared. + * |[1] |DMARST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset internal state machine and pointers + * | | |The contents of control register will not be cleared + * | | |This bit will auto be cleared after few clock cycles. + * | | |Note: The software reset DMA related registers. + * |[3] |SGEN |Scatter-gather Function Enable Bit + * | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory). + * | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table + * | | |The format of these Pads' will be described later). + * |[9] |DMABUSY |DMA Transfer Is in Progress + * | | |This bit indicates if SD Host is granted and doing DMA transfer or not. + * | | |0 = DMA transfer is not in progress. + * | | |1 = DMA transfer is in progress. + * @var SDH_T::DMASA + * Offset: 0x408 DMA Transfer Starting Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ORDER |Determined to the PAD Table Fetching Is in Order or Out of Order + * | | |0 = PAD table is fetched in order. + * | | |1 = PAD table is fetched out of order. + * | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1. + * |[31:1] |DMASA |DMA Transfer Starting Address + * | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data. + * | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table. + * | | |Note: Starting address of the SRAM must be word aligned, for example, 0x0000_0000, 0x0000_0004. + * @var SDH_T::DMABCNT + * Offset: 0x40C DMA Transfer Byte Count Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[25:0] |BCNT |DMA Transfer Byte Count (Read Only) + * | | |This field indicates the remained byte count of DMA transfer + * | | |The value of this field is valid only when DMA is busy; otherwise, it is 0. + * @var SDH_T::DMAINTEN + * Offset: 0x410 DMA Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Bit + * | | |0 = Target abort interrupt generation Disabled during DMA transfer. + * | | |1 = Target abort interrupt generation Enabled during DMA transfer. + * |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Bit + * | | |0 = Interrupt generation Disabled when wrong EOT is encountered. + * | | |1 = Interrupt generation Enabled when wrong EOT is encountered. + * @var SDH_T::DMAINTSTS + * Offset: 0x414 DMA Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note1: This bit is read only, but can be cleared by writing '1' to it. + * | | |Note2: When DMA's bus master received ERROR response, it means that target abort is happened + * | | |DMA will stop transfer and respond this event and then go to IDLE state + * | | |When target abort occurred or WEOTIF is set, software must reset DMA and SD host, and then transfer those data again. + * |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag + * | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set. + * | | |0 = No EOT encountered before DMA transfer finished. + * | | |1 = EOT encountered before DMA transfer finished. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var SDH_T::GCTL + * Offset: 0x800 Global Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCTLRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset SD host + * | | |The contents of control register will not be cleared + * | | |This bit will auto cleared after reset complete. + * |[1] |SDEN |Secure Digital Functionality Enable Bit + * | | |0 = SD functionality disabled. + * | | |1 = SD functionality enabled. + * @var SDH_T::GINTEN + * Offset: 0x804 Global Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Bit + * | | |0 = DMA READ/WRITE target abort interrupt generation disabled. + * | | |1 = DMA READ/WRITE target abort interrupt generation enabled. + * @var SDH_T::GINTSTS + * Offset: 0x808 Global Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only) + * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation + * | | |When Target Abort is occurred, please reset all engine. + * | | |0 = No bus ERROR response received. + * | | |1 = Bus ERROR response received. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * @var SDH_T::CTL + * Offset: 0x820 SD Control and Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |COEN |Command Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output a command to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[1] |RIEN |Response Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive a response from SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[2] |DIEN |Data Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[3] |DOEN |Data Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[4] |R2EN |Response R2 Input Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7). + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output 74 clock cycles to SD card. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Bit + * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.) + * | | |1 = Enabled, SD host will output 8 clock cycles. + * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal). + * |[7] |CLKKEEP0 |SD Clock Enable Control for Port 0 + * | | |0 = SD host decided when to output clock and when to disable clock output automatically. + * | | |1 = SD clock always keeps free running. + * |[13:8] |CMDCODE |SD Command Code + * | | |This register contains the SD command code (0x00 ~ 0x3F). + * |[14] |CTLRST |Software Engine Reset + * | | |0 = No effect. + * | | |1 = Reset the internal state machine and counters + * | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2EN will be cleared) + * | | |This bit will be auto cleared after few clock cycles. + * |[15] |DBW |SD Data Bus Width (for 1-bit / 4-bit Selection) + * | | |0 = Data bus width is 1-bit. + * | | |1 = Data bus width is 4-bit. + * |[23:16] |BLKCNT |Block Counts to Be Transferred or Received + * | | |This field contains the block counts for data-in and data-out transfer + * | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance + * | | |Don't fill 0x0 to this field. + * | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1). + * |[27:24] |SDNWR |NWR Parameter for Block Write Operation + * | | |This value indicates the NWR parameter for data block write operation in SD clock counts + * | | |The actual clock cycle will be SDNWR+1. + * @var SDH_T::CMDARG + * Offset: 0x824 SD Command Argument Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ARGUMENT |SD Command Argument + * | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card + * | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field. + * @var SDH_T::INTEN + * Offset: 0x828 SD Interrupt Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Bit + * | | |0 = SD host will not generate interrupt when data-in (out) transfer done. + * | | |1 = SD host will generate interrupt when data-in (out) transfer done. + * |[1] |CRCIEN |CRC7, CRC16 and CRC Status Error Interrupt Enable Bit + * | | |0 = SD host will not generate interrupt when CRC7, CRC16 and CRC status is error. + * | | |1 = SD host will generate interrupt when CRC7, CRC16 and CRC status is error. + * |[8] |CDIEN0 |SD0 Card Detection Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when card 0 is inserted or removed. + * | | |0 = SD card detection interrupt Disabled. + * | | |1 = SD card detection interrupt Enabled. + * |[12] |RTOIEN |Response Time-out Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out + * | | |Time-out value is specified at TOUT register. + * | | |0 = Response time-out interrupt Disabled. + * | | |1 = Response time-out interrupt Enabled. + * |[13] |DITOIEN |Data Input Time-out Interrupt Enable Bit + * | | |Enable/Disable interrupts generation of SD controller when data input time-out + * | | |Time-out value is specified at TOUT register. + * | | |0 = Data input time-out interrupt Disabled. + * | | |1 = Data input time-out interrupt Enabled. + * |[14] |WKIEN |Wake-up Signal Generating Enable Bit + * | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host. + * | | |0 = Wake-up signal generating Disabled. + * | | |1 = Wake-up signal generating Enabled. + * |[30] |CDSRC0 |SD0 Card Detect Source Selection + * | | |0 = From SD0 card's DAT3 pin. + * | | |Host need clock to got data on pin DAT3 + * | | |Please make sure CLKKEEP0 (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin. + * | | |1 = From GPIO pin. + * @var SDH_T::INTSTS + * Offset: 0x82C SD Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only) + * | | |This bit indicates that SD host has finished all data-in or data-out block transfer + * | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set. + * | | |0 = Not finished yet. + * | | |1 = Done. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[1] |CRCIF |CRC7, CRC16 and CRC Status Error Interrupt Flag (Read Only) + * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer + * | | |When CRC error is occurred, software should reset SD engine + * | | |Some response (ex + * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag + * | | |In this condition, software should ignore CRC error and clears this bit manually. + * | | |0 = No CRC error is occurred. + * | | |1 = CRC error is occurred. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[2] |CRC7 |CRC7 Check Status (Read Only) + * | | |SD host will check CRC7 correctness during each response in + * | | |If that response does not contain CRC7 information (ex + * | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit. + * | | |0 = Fault. + * | | |1 = OK. + * |[3] |CRC16 |CRC16 Check Status of Data-in Transfer (Read Only) + * | | |SD host will check CRC16 correctness after data-in transfer. + * | | |0 = Fault. + * | | |1 = OK. + * |[6:4] |CRCSTS |CRC Status Value of Data-out Transfer (Read Only) + * | | |SD host will record CRC status of data-out transfer + * | | |Software could use this value to identify what type of error is during data-out transfer. + * | | |010 = Positive CRC status. + * | | |101 = Negative CRC status. + * | | |111 = SD card programming error occurs. + * |[7] |DAT0STS |DAT0 Pin Status of Current Selected SD Port (Read Only) + * | | |This bit is the DAT0 pin status of current selected SD port. + * |[8] |CDIF0 |SD0 Card Detection Interrupt Flag (Read Only) + * | | |This bit indicates that SD card 0 is inserted or removed + * | | |Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active. + * | | |0 = No card is inserted or removed. + * | | |1 = There is a card inserted in or removed from SD0. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[12] |RTOIF |Response Time-out Interrupt Flag (Read Only) + * | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit). + * | | |0 = Not time-out. + * | | |1 = Response time-out. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[13] |DITOIF |Data Input Time-out Interrupt Flag (Read Only) + * | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit). + * | | |0 = Not time-out. + * | | |1 = Data input time-out. + * | | |Note: This bit is read only, but can be cleared by writing '1' to it. + * |[16] |CDSTS0 |Card Detect Status of SD0 (Read Only) + * | | |This bit indicates the card detect pin status of SD0, and is used for card detection + * | | |When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal. + * | | |If CDSRC0 (SDH_INTEN[30]) = 0, to select DAT3 for card detection:. + * | | |0 = Card removed. + * | | |1 = Card inserted. + * | | |If CDSRC0 (SDH_INTEN[30]) = 1, to select GPIO for card detection:. + * | | |0 = Card inserted. + * | | |1 = Card removed. + * |[18] |DAT1STS |DAT1 Pin Status of SD Port (Read Only) + * | | |This bit indicates the DAT1 pin status of SD port. + * @var SDH_T::RESP0 + * Offset: 0x830 SD Receiving Response Token Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RESPTK0 |SD Receiving Response Token 0 + * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set + * | | |This field contains response bit 47-16 of the response token. + * @var SDH_T::RESP1 + * Offset: 0x834 SD Receiving Response Token Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |RESPTK1 |SD Receiving Response Token 1 + * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set + * | | |This register contains the bit 15-8 of the response token. + * @var SDH_T::BLEN + * Offset: 0x838 SD Block Length Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |BLKLEN |SD BLOCK LENGTH in Byte Unit + * | | |An 11-bit value specifies the SD transfer byte count of a block + * | | |The actual byte count is equal to BLKLEN+1. + * | | |Note: The default SD block length is 512 bytes + * @var SDH_T::TOUT + * Offset: 0x83C SD Response/Data-in Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |TOUT |SD Response/Data-in Time-out Value + * | | |A 24-bit value specifies the time-out counts of response and data input + * | | |SD host controller will wait start bit of response or data-in until this value reached + * | | |The time period depends on SD engine clock frequency + * | | |Do not write a small number into this field, or you may never get response or data due to time-out. + * | | |Note: Filling 0x0 into this field will disable hardware time-out function. + */ + + __IO uint32_t FB[32]; /*!< Shared Buffer (FIFO) */ + __I uint32_t RESERVE0[224]; + __IO uint32_t DMACTL; /*!< [0x0400] DMA Control and Status Register */ + __I uint32_t RESERVE1[1]; + __IO uint32_t DMASA; /*!< [0x0408] DMA Transfer Starting Address Register */ + __I uint32_t DMABCNT; /*!< [0x040c] DMA Transfer Byte Count Register */ + __IO uint32_t DMAINTEN; /*!< [0x0410] DMA Interrupt Enable Control Register */ + __IO uint32_t DMAINTSTS; /*!< [0x0414] DMA Interrupt Status Register */ + __I uint32_t RESERVE2[250]; + __IO uint32_t GCTL; /*!< [0x0800] Global Control and Status Register */ + __IO uint32_t GINTEN; /*!< [0x0804] Global Interrupt Control Register */ + __IO uint32_t GINTSTS; /*!< [0x0808] Global Interrupt Status Register */ + __I uint32_t RESERVE3[5]; + __IO uint32_t CTL; /*!< [0x0820] SD Control and Status Register */ + __IO uint32_t CMDARG; /*!< [0x0824] SD Command Argument Register */ + __IO uint32_t INTEN; /*!< [0x0828] SD Interrupt Control Register */ + __IO uint32_t INTSTS; /*!< [0x082c] SD Interrupt Status Register */ + __I uint32_t RESP0; /*!< [0x0830] SD Receiving Response Token Register 0 */ + __I uint32_t RESP1; /*!< [0x0834] SD Receiving Response Token Register 1 */ + __IO uint32_t BLEN; /*!< [0x0838] SD Block Length Register */ + __IO uint32_t TOUT; /*!< [0x083c] SD Response/Data-in Time-out Register */ + +} SDH_T; + +/** + @addtogroup SDH_CONST SDH Bit Field Definition + Constant Definitions for SDH Controller + @{ +*/ + +#define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH_T::DMACTL: DMAEN Position */ +#define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH_T::DMACTL: DMAEN Mask */ + +#define SDH_DMACTL_DMARST_Pos (1) /*!< SDH_T::DMACTL: DMARST Position */ +#define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH_T::DMACTL: DMARST Mask */ + +#define SDH_DMACTL_SGEN_Pos (3) /*!< SDH_T::DMACTL: SGEN Position */ +#define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH_T::DMACTL: SGEN Mask */ + +#define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH_T::DMACTL: DMABUSY Position */ +#define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH_T::DMACTL: DMABUSY Mask */ + +#define SDH_DMASA_ORDER_Pos (0) /*!< SDH_T::DMASA: ORDER Position */ +#define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH_T::DMASA: ORDER Mask */ + +#define SDH_DMASA_DMASA_Pos (1) /*!< SDH_T::DMASA: DMASA Position */ +#define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH_T::DMASA: DMASA Mask */ + +#define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH_T::DMABCNT: BCNT Position */ +#define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH_T::DMABCNT: BCNT Mask */ + +#define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH_T::DMAINTEN: ABORTIEN Position */ +#define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH_T::DMAINTEN: ABORTIEN Mask */ + +#define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH_T::DMAINTEN: WEOTIEN Position */ +#define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH_T::DMAINTEN: WEOTIEN Mask */ + +#define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH_T::DMAINTSTS: ABORTIF Position */ +#define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH_T::DMAINTSTS: ABORTIF Mask */ + +#define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH_T::DMAINTSTS: WEOTIF Position */ +#define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH_T::DMAINTSTS: WEOTIF Mask */ + +#define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH_T::GCTL: GCTLRST Position */ +#define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH_T::GCTL: GCTLRST Mask */ + +#define SDH_GCTL_SDEN_Pos (1) /*!< SDH_T::GCTL: SDEN Position */ +#define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH_T::GCTL: SDEN Mask */ + +#define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH_T::GINTEN: DTAIEN Position */ +#define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH_T::GINTEN: DTAIEN Mask */ + +#define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH_T::GINTSTS: DTAIF Position */ +#define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH_T::GINTSTS: DTAIF Mask */ + +#define SDH_CTL_COEN_Pos (0) /*!< SDH_T::CTL: COEN Position */ +#define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH_T::CTL: COEN Mask */ + +#define SDH_CTL_RIEN_Pos (1) /*!< SDH_T::CTL: RIEN Position */ +#define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH_T::CTL: RIEN Mask */ + +#define SDH_CTL_DIEN_Pos (2) /*!< SDH_T::CTL: DIEN Position */ +#define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH_T::CTL: DIEN Mask */ + +#define SDH_CTL_DOEN_Pos (3) /*!< SDH_T::CTL: DOEN Position */ +#define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH_T::CTL: DOEN Mask */ + +#define SDH_CTL_R2EN_Pos (4) /*!< SDH_T::CTL: R2EN Position */ +#define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH_T::CTL: R2EN Mask */ + +#define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH_T::CTL: CLK74OEN Position */ +#define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH_T::CTL: CLK74OEN Mask */ + +#define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH_T::CTL: CLK8OEN Position */ +#define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH_T::CTL: CLK8OEN Mask */ + +#define SDH_CTL_CLKKEEP_Pos (7) /*!< SDH_T::CTL: CLKKEEP Position */ +#define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) /*!< SDH_T::CTL: CLKKEEP Mask */ + +#define SDH_CTL_CMDCODE_Pos (8) /*!< SDH_T::CTL: CMDCODE Position */ +#define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH_T::CTL: CMDCODE Mask */ + +#define SDH_CTL_CTLRST_Pos (14) /*!< SDH_T::CTL: CTLRST Position */ +#define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH_T::CTL: CTLRST Mask */ + +#define SDH_CTL_DBW_Pos (15) /*!< SDH_T::CTL: DBW Position */ +#define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH_T::CTL: DBW Mask */ + +#define SDH_CTL_BLKCNT_Pos (16) /*!< SDH_T::CTL: BLKCNT Position */ +#define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH_T::CTL: BLKCNT Mask */ + +#define SDH_CTL_SDNWR_Pos (24) /*!< SDH_T::CTL: SDNWR Position */ +#define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH_T::CTL: SDNWR Mask */ + +#define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH_T::CMDARG: ARGUMENT Position */ +#define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH_T::CMDARG: ARGUMENT Mask */ + +#define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH_T::INTEN: BLKDIEN Position */ +#define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH_T::INTEN: BLKDIEN Mask */ + +#define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH_T::INTEN: CRCIEN Position */ +#define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH_T::INTEN: CRCIEN Mask */ + +#define SDH_INTEN_CDIEN_Pos (8) /*!< SDH_T::INTEN: CDIEN Position */ +#define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) /*!< SDH_T::INTEN: CDIEN Mask */ + +#define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH_T::INTEN: RTOIEN Position */ +#define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH_T::INTEN: RTOIEN Mask */ + +#define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH_T::INTEN: DITOIEN Position */ +#define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH_T::INTEN: DITOIEN Mask */ + +#define SDH_INTEN_WKIEN_Pos (14) /*!< SDH_T::INTEN: WKIEN Position */ +#define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH_T::INTEN: WKIEN Mask */ + +#define SDH_INTEN_CDSRC_Pos (30) /*!< SDH_T::INTEN: CDSRC Position */ +#define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) /*!< SDH_T::INTEN: CDSRC Mask */ + +#define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH_T::INTSTS: BLKDIF Position */ +#define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH_T::INTSTS: BLKDIF Mask */ + +#define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH_T::INTSTS: CRCIF Position */ +#define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH_T::INTSTS: CRCIF Mask */ + +#define SDH_INTSTS_CRC7_Pos (2) /*!< SDH_T::INTSTS: CRC7 Position */ +#define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH_T::INTSTS: CRC7 Mask */ + +#define SDH_INTSTS_CRC16_Pos (3) /*!< SDH_T::INTSTS: CRC16 Position */ +#define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH_T::INTSTS: CRC16 Mask */ + +#define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH_T::INTSTS: CRCSTS Position */ +#define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH_T::INTSTS: CRCSTS Mask */ + +#define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH_T::INTSTS: DAT0STS Position */ +#define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH_T::INTSTS: DAT0STS Mask */ + +#define SDH_INTSTS_CDIF_Pos (8) /*!< SDH_T::INTSTS: CDIF Position */ +#define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) /*!< SDH_T::INTSTS: CDIF Mask */ + +#define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH_T::INTSTS: RTOIF Position */ +#define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH_T::INTSTS: RTOIF Mask */ + +#define SDH_INTSTS_DITOIF_Pos (13) /*!< SDH_T::INTSTS: DITOIF Position */ +#define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) /*!< SDH_T::INTSTS: DITOIF Mask */ + +#define SDH_INTSTS_CDSTS_Pos (16) /*!< SDH_T::INTSTS: CDSTS Position */ +#define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) /*!< SDH_T::INTSTS: CDSTS Mask */ + +#define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH_T::INTSTS: DAT1STS Position */ +#define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH_T::INTSTS: DAT1STS Mask */ + +#define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH_T::RESP0: RESPTK0 Position */ +#define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH_T::RESP0: RESPTK0 Mask */ + +#define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH_T::RESP1: RESPTK1 Position */ +#define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH_T::RESP1: RESPTK1 Mask */ + +#define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH_T::BLEN: BLKLEN Position */ +#define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH_T::BLEN: BLKLEN Mask */ + +#define SDH_TOUT_TOUT_Pos (0) /*!< SDH_T::TOUT: TOUT Position */ +#define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH_T::TOUT: TOUT Mask */ + +/**@}*/ /* SDH_CONST */ +/**@}*/ /* end of SDH register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __SDH_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/spi_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/spi_reg.h new file mode 100644 index 0000000000..d224ad0d5e --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/spi_reg.h @@ -0,0 +1,854 @@ +/**************************************************************************//** + * @file spi_reg.h + * @version V1.00 + * @brief SPI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SPI_REG_H__ +#define __SPI_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Serial Peripheral Interface Controller -------------------------*/ +/** + @addtogroup SPI Serial Peripheral Interface Controller(SPI) + Memory Mapped Structure for SPI Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var SPI_T::CTL + * Offset: 0x00 SPI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SPIEN |SPI Transfer Control Enable Bit + * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 + * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. + * | | |0 = Transfer control Disabled. + * | | |1 = Transfer control Enabled. + * | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. + * |[1] |RXNEG |Receive on Negative Edge + * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock. + * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock. + * |[2] |TXNEG |Transmit on Negative Edge + * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. + * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock. + * |[3] |CLKPOL |Clock Polarity + * | | |0 = SPI bus clock is idle low. + * | | |1 = SPI bus clock is idle high. + * |[7:4] |SUSPITV |Suspend Interval (Master Only) + * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle. + * | | |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE .... 14.5 SPICLK clock cycle. + * | | |SUSPITV = 0xF .... 15.5 SPICLK clock cycle. + * |[12:8] |DWIDTH |Data Width + * | | |This field specifies how many bits can be transmitted / received in one transaction + * | | |The minimum bit length is 8 bits and can up to 32 bits. + * | | |DWIDTH = 0x08 .... 8 bits. + * | | |DWIDTH = 0x09 .... 9 bits. + * | | |..... + * | | |DWIDTH = 0x1F .... 31 bits. + * | | |DWIDTH = 0x00 .... 32 bits. + * | | |Note: For SPI0~SPI3, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode + * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI0~SPI3. + * |[13] |LSB |Send LSB First + * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX). + * |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit + * | | |This bit is used to select full-duplex or half-duplex for SPI transfer + * | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. + * | | |0 = SPI operates in full-duplex transfer. + * | | |1 = SPI operates in half-duplex transfer. + * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) + * | | |This bit field is only available in Master mode + * | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. + * | | |0 = Receive-only mode Disabled. + * | | |1 = Receive-only mode Enabled. + * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit + * | | |0 = SPI unit transfer interrupt Disabled. + * | | |1 = SPI unit transfer interrupt Enabled. + * |[18] |SLAVE |Slave Mode Control + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[19] |REORDER |Byte Reorder Function Enable Bit + * | | |0 = Byte Reorder function Disabled. + * | | |1 = Byte Reorder function Enabled + * | | |A byte suspend interval will be inserted among each byte + * | | |The period of the byte suspend interval depends on the setting of SUSPITV. + * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. + * |[20] |DATDIR |Data Port Direction Control + * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer + * | | |0 = SPI data is input direction. + * | | |1 = SPI data is output direction. + * @var SPI_T::CLKDIV + * Offset: 0x04 SPI Clock Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |DIVIDER |Clock Divider + * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master + * | | |The frequency is obtained according to the following equation. + * | | |where + * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. + * | | |Note 1: Not supported in I2S mode. + * | | |Note 2: The time interval must be larger than or equal 5 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register. + * @var SPI_T::SSCTL + * Offset: 0x08 SPI Slave Select Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SS |Slave Selection Control + * | | |If AUTOSS bit is cleared to 0, + * | | |0 = set the SPIx_SS line to inactive state. + * | | |1 = set the SPIx_SS line to active state. + * | | |If the AUTOSS bit is set to 1, + * | | |0 = Keep the SPIx_SS line at inactive state. + * | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time + * | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]). + * | | |Note: Master mode only. + * |[2] |SSACTPOL |Slave Selection Active Polarity + * | | |This bit defines the active polarity of slave selection signal (SPIx_SS). + * | | |0 = The slave selection signal SPIx_SS is active low. + * | | |1 = The slave selection signal SPIx_SS is active high. + * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) + * | | |0 = Automatic slave selection function Disabled + * | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]). + * | | |1 = Automatic slave selection function Enabled. + * | | |Note: Master mode only. + * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit + * | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIx_CLK, SPIx_MISO and SPIx_MOSI pins. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * | | |Note: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S mode is enabled. + * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |0 = Slave mode bit count error interrupt Disabled. + * | | |1 = Slave mode bit count error interrupt Enabled. + * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit + * | | |0 = Slave mode TX under run interrupt Disabled. + * | | |1 = Slave mode TX under run interrupt Enabled. + * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |0 = Slave select active interrupt Disabled. + * | | |1 = Slave select active interrupt Enabled. + * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |0 = Slave select inactive interrupt Disabled. + * | | |1 = Slave select inactive interrupt Enabled. + * @var SPI_T::PDMACTL + * Offset: 0x0C SPI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TXPDMAEN |Transmit PDMA Enable Bit + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function + * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. + * |[1] |RXPDMAEN |Receive PDMA Enable Bit + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[2] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0. + * @var SPI_T::FIFOCTL + * Offset: 0x10 SPI FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset receive FIFO pointer and receive circuit + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * |[1] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset transmit FIFO pointer and transmit circuit + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 + * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. + * | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. + * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit + * | | |0 = RX FIFO threshold interrupt Disabled. + * | | |1 = RX FIFO threshold interrupt Enabled. + * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit + * | | |0 = TX FIFO threshold interrupt Disabled. + * | | |1 = TX FIFO threshold interrupt Enabled. + * |[4] |RXTOIEN |Receive Time-out Interrupt Enable Bit + * | | |0 = Receive time-out interrupt Disabled. + * | | |1 = Receive time-out interrupt Enabled. + * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit + * | | |0 = Receive FIFO overrun interrupt Disabled. + * | | |1 = Receive FIFO overrun interrupt Enabled. + * |[6] |TXUFPOL |TX Underflow Data Polarity + * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. + * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. + * | | |Note: + * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. + * | | |2. This bit should be set as 0 in I2S mode. + * | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward + * | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. + * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit + * | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1 + * | | |This bit is used to enable the TX underflow interrupt. + * | | |0 = Slave TX underflow interrupt Disabled. + * | | |1 = Slave TX underflow interrupt Enabled. + * |[8] |RXFBCLR |Receive FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear receive FIFO pointer + * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The RX shift register will not be cleared. + * |[9] |TXFBCLR |Transmit FIFO Buffer Clear + * | | |0 = No effect. + * | | |1 = Clear transmit FIFO pointer + * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 + * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. + * | | |Note: The TX shift register will not be cleared. + * |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error + * | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in SPI Slave mode. + * | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in SPI Slave mode + * | | |User can read SLVBENUM (SPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened. + * | | |Note: Slave mode only. + * |[26:24] |RXTH |Receive FIFO Threshold + * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 + * | | |For SPI0~SPI3, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. + * |[30:28] |TXTH |Transmit FIFO Threshold + * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 + * | | |For SPI0~SPI3, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. + * @var SPI_T::STATUS + * Offset: 0x14 SPI Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSY |Busy Status (Read Only) + * | | |0 = SPI controller is in idle state. + * | | |1 = SPI controller is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0. + * | | |b + * | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1. + * | | |d. + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |e. + * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * | | |Note: By applications, this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF + * | | |Therefore the SPI transfer done events of TX/RX operations can be obtained at correct timing point. + * |[1] |UNITIF |Unit Transfer Interrupt Flag + * | | |0 = No transaction has been finished since this bit was cleared to 0. + * | | |1 = SPI controller has finished one unit transfer. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[2] |SSACTIF |Slave Select Active Interrupt Flag + * | | |0 = Slave select active interrupt was cleared or not occurred. + * | | |1 = Slave select active interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag + * | | |0 = Slave select inactive interrupt was cleared or not occurred. + * | | |1 = Slave select inactive interrupt event occurred. + * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. + * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * | | |Note: This bit is only available in Slave mode + * | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. + * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag + * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. + * | | |0 = No Slave mode bit count error event. + * | | |1 = Slave mode bit count error event occurs. + * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state + * | | |This bit will be cleared by writing 1 to it. + * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag + * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. + * | | |0 = No Slave TX under run event. + * | | |1 = Slave TX under run event occurs. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |0 = No FIFO is overrun. + * | | |1 = Receive FIFO is overrun. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |SPIENSTS |SPI Enable Status (Read Only) + * | | |0 = The SPI controller is disabled. + * | | |1 = The SPI controller is enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * |[19] |TXUFIF |TX Underflow Interrupt Flag + * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. + * | | |0 = No effect. + * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. + * | | |Note 1: This bit will be cleared by writing 1 to it. + * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + * @var SPI_T::STATUS2 + * Offset: 0x18 SPI Status2 Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX Data + * | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode + * | | |This status register will be fixed to 0x0 when SLVBERX (SPIx_FIFOCTL[10]) is disabled. + * | | |Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (SPIx_STATUS[6]). + * | | |Note 2: Slave mode only. + * @var SPI_T::TX + * Offset: 0x20 SPI Data Transmit Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |TX |Data Transmit Register + * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers + * | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode. + * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted + * | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer. + * | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0] + * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section + * | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. + * @var SPI_T::RX + * Offset: 0x30 SPI Data Receive Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RX |Data Receive Register (Read Only) + * | | |There are 4-level FIFO buffers in this controller. + * | | |The data receive register holds the data received from SPI data input pin. + * | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. + * @var SPI_T::I2SCTL + * Offset: 0x60 I2S Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |I2SEN |I2S Controller Enable Bit + * | | |0 = Disabled I2S mode. + * | | |1 = Enabled I2S mode. + * | | |Note: + * | | |1. If enable this bit, I2Sx_BCLK will start to output in Master mode. + * | | |2 + * | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. + * |[1] |TXEN |Transmit Enable Bit + * | | |0 = Data transmit Disabled. + * | | |1 = Data transmit Enabled. + * |[2] |RXEN |Receive Enable Bit + * | | |0 = Data receive Disabled. + * | | |1 = Data receive Enabled. + * |[3] |MUTE |Transmit Mute Enable Bit + * | | |0 = Transmit data is shifted from buffer. + * | | |1 = Transmit channel zero. + * |[5:4] |WDWIDTH |Word Width + * | | |00 = data size is 8-bit. + * | | |01 = data size is 16-bit. + * | | |10 = data size is 24-bit. + * | | |11 = data size is 32-bit. + * |[6] |MONO |Monaural Data + * | | |0 = Data is stereo format. + * | | |1 = Data is monaural format. + * |[7] |ORDER |Stereo Data Order in FIFO + * | | |0 = Left channel data at high byte. + * | | |1 = Left channel data at low byte. + * |[8] |SLAVE |Slave Mode + * | | |I2S can operate as master or slave + * | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from NuMicro M2354 series to audio CODEC chip + * | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[15] |MCLKEN |Master Clock Enable Bit + * | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. + * | | |0 = Master clock Disabled. + * | | |1 = Master clock Enabled. + * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Right channel zero cross detection Disabled. + * | | |1 = Right channel zero cross detection Enabled. + * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit + * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1 + * | | |This function is only available in transmit operation. + * | | |0 = Left channel zero cross detection Disabled. + * | | |1 = Left channel zero cross detection Enabled. + * |[23] |RXLCH |Receive Left Channel Enable Bit + * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1. + * | | |0 = Receive right channel data in Mono mode. + * | | |1 = Receive left channel data in Mono mode. + * |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit + * | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[29:28] |FORMAT |Data Format Selection + * | | |00 = I2S data format. + * | | |01 = MSB justified data format. + * | | |10 = PCM mode A. + * | | |11 = PCM mode B. + * |[31] |SLVERRIEN |Bit Clock Loss Interrupt Enable Bit for Slave Mode + * | | |Interrupt occurs if this bit is set to 1 and bit clock loss event occurs. + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * @var SPI_T::I2SCLK + * Offset: 0x64 I2S Clock Divider Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |MCLKDIV |Master Clock Divider + * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. + * | | |The frequency of master clock, F_MCLK, is determined by the following expressions: + * | | |If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)). + * | | |If MCLKDIV = 0, F_MCLK = F_I2SCLK. + * | | |where + * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. + * | | |F_I2SCLK is the frequency of I2S peripheral clock. + * | | |In general, the master clock rate is 256 times sampling clock rate. + * |[17:8] |BCLKDIV |Bit Clock Divider + * | | |The I2S controller will generate bit clock in Master mode. + * | | |The clock frequency of bit clock, F_BCLK, is determined by the following expression: + * | | |F_BCLK = F_I2SCLK/(2x(BCLKDIV + 1)), + * | | |where + * | | |F_I2SCLK is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. + * | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by F_I2SCLK/(BCLKDIV/2 + 1). + * | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. + * |[24] |I2SMODE |I2S Clock Divider Number Selection for I2S Mode and SPI Mode + * | | |User sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set. + * | | |User needs to set I2SMODE before I2SEN (SPIx_I2SCTL[0]) or SPIEN (SPIx_CTL[0]) is enabled. + * | | |0 = The frequency of peripheral clock is set to SPI mode. + * | | |1 = The frequency of peripheral clock is set to I2S mode. + * |[25] |I2SSLAVE |I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode + * | | |User sets I2SSLAVE to set frequency of peripheral clock of I2S master mode and I2S slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set. + * | | |I2SSLAVE needs to set before I2SEN (SPIx_I2SCTL[0]) is enabled. + * | | |0 = The frequency of peripheral clock is set to I2S Master mode. + * | | |1 = The frequency of peripheral clock is set to I2S Slave mode. + * @var SPI_T::I2SSTS + * Offset: 0x68 I2S Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4] |RIGHT |Right Channel (Read Only) + * | | |This bit indicates the current transmit data is belong to which channel. + * | | |0 = Left channel. + * | | |1 = Right channel. + * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not empty. + * | | |1 = Receive FIFO buffer is empty. + * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) + * | | |0 = Receive FIFO buffer is not full. + * | | |1 = Receive FIFO buffer is full. + * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. + * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. + * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag + * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[12] |RXTOIF |Receive Time-out Interrupt Flag + * | | |0 = No receive FIFO time-out event. + * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode + * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[15] |I2SENSTS |I2S Enable Status (Read Only) + * | | |0 = The SPI/I2S control logic is disabled. + * | | |1 = The SPI/I2S control logic is enabled. + * | | |Note: The SPI peripheral clock is asynchronous with the system clock + * | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. + * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not empty. + * | | |1 = Transmit FIFO buffer is empty. + * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) + * | | |0 = Transmit FIFO buffer is not full. + * | | |1 = Transmit FIFO buffer is full. + * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) + * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. + * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. + * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. + * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag + * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on right channel. + * | | |1 = Zero cross event occurred on right channel. + * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag + * | | |0 = No zero cross event occurred on left channel. + * | | |1 = Zero cross event occurred on left channel. + * |[22] |SLVERRIF |Bit Clock Loss Interrupt Flag for Slave Mode + * | | |0 = No bit clock loss event occurred. + * | | |1 = Bit clock loss event occurred. + * | | |Note: This bit will be cleared by writing 1 to it. + * |[23] |TXRXRST |TX or RX Reset Status (Read Only) + * | | |0 = The reset function of TXRST or RXRST is done. + * | | |1 = Doing the reset function of TXRST or RXRST. + * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles + * | | |User can check the status of this bit to monitor the reset function is doing or done. + * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of receive FIFO buffer. + * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only) + * | | |This bit field indicates the valid data count of transmit FIFO buffer. + */ + __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */ + __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */ + __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */ + __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */ + __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */ + __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */ + __I uint32_t STATUS2; /*!< [0x0018] SPI Status2 Register */ + __I uint32_t RESERVE0[1]; + __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */ + __I uint32_t RESERVE1[3]; + __I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */ + __I uint32_t RESERVE2[11]; + __IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */ + __IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */ + __IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */ + +} SPI_T; + +/** + @addtogroup SPI_CONST SPI Bit Field Definition + Constant Definitions for SPI Controller + @{ +*/ + +#define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */ +#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */ + +#define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */ +#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */ + +#define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */ +#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */ + +#define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */ +#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */ + +#define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */ +#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */ + +#define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */ +#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */ + +#define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */ +#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */ + +#define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */ +#define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */ + +#define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */ +#define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */ + +#define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */ +#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */ + +#define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */ +#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */ + +#define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */ +#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */ + +#define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */ +#define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */ + +#define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */ +#define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */ + +#define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */ +#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */ + +#define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */ +#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */ + +#define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */ +#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */ + +#define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */ +#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */ + +#define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */ +#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */ + +#define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */ +#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */ + +#define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */ +#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */ + +#define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */ +#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */ + +#define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */ +#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */ + +#define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */ +#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */ + +#define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */ +#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */ + +#define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */ +#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */ + +#define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */ +#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */ + +#define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */ +#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */ + +#define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */ +#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */ + +#define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */ +#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */ + +#define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */ +#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */ + +#define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */ +#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */ + +#define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */ +#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */ + +#define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */ +#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */ + +#define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */ +#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */ + +#define SPI_FIFOCTL_SLVBERX_Pos (10) /*!< SPI_T::FIFOCTL: SLVBERX Position */ +#define SPI_FIFOCTL_SLVBERX_Msk (0x1ul << SPI_FIFOCTL_SLVBERX_Pos) /*!< SPI_T::FIFOCTL: SLVBERX Mask */ + +#define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */ +#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */ + +#define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */ +#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */ + +#define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */ +#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */ + +#define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */ +#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */ + +#define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */ +#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */ + +#define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */ +#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */ + +#define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */ +#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */ + +#define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */ +#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */ + +#define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */ +#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */ + +#define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */ +#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */ + +#define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */ +#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */ + +#define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */ +#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */ + +#define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */ +#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */ + +#define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */ +#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */ + +#define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */ +#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */ + +#define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */ +#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */ + +#define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */ +#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */ + +#define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */ +#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */ + +#define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */ +#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */ + +#define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */ +#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */ + +#define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */ +#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */ + +#define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */ +#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */ + +#define SPI_STATUS2_SLVBENUM_Pos (24) /*!< SPI_T::STATUS2: SLVBENUM Position */ +#define SPI_STATUS2_SLVBENUM_Msk (0x3ful << SPI_STATUS2_SLVBENUM_Pos) /*!< SPI_T::STATUS2: SLVBENUM Mask */ + +#define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */ +#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */ + +#define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */ +#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */ + +#define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */ +#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */ + +#define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */ +#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */ + +#define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */ +#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */ + +#define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */ +#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */ + +#define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */ +#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */ + +#define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */ +#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */ + +#define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */ +#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */ + +#define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */ +#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */ + +#define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */ +#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */ + +#define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */ +#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */ + +#define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */ +#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */ + +#define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */ +#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */ + +#define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */ +#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */ + +#define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */ +#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */ + +#define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */ +#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */ + +#define SPI_I2SCTL_SLVERRIEN_Pos (31) /*!< SPI_T::I2SCTL: SLVERRIEN Position */ +#define SPI_I2SCTL_SLVERRIEN_Msk (0x1ul << SPI_I2SCTL_SLVERRIEN_Pos) /*!< SPI_T::I2SCTL: SLVERRIEN Mask */ + +#define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */ +#define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */ + +#define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */ +#define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */ + +#define SPI_I2SCLK_I2SMODE_Pos (24) /*!< SPI_T::I2SCLK: I2SMODE Position */ +#define SPI_I2SCLK_I2SMODE_Msk (0x1ul << SPI_I2SCLK_I2SMODE_Pos) /*!< SPI_T::I2SCLK: I2SMODE Mask */ + +#define SPI_I2SCLK_I2SSLAVE_Pos (25) /*!< SPI_T::I2SCLK: I2SSLAVE Position */ +#define SPI_I2SCLK_I2SSLAVE_Msk (0x1ul << SPI_I2SCLK_I2SSLAVE_Pos) /*!< SPI_T::I2SCLK: I2SSLAVE Mask */ + +#define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */ +#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */ + +#define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */ +#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */ + +#define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */ +#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */ + +#define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */ +#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */ + +#define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */ +#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */ + +#define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */ +#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */ + +#define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */ +#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */ + +#define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */ +#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */ + +#define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */ +#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */ + +#define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */ +#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */ + +#define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */ +#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */ + +#define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */ +#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */ + +#define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */ +#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */ + +#define SPI_I2SSTS_SLVERRIF_Pos (22) /*!< SPI_T::I2SSTS: SLVERRIF Position */ +#define SPI_I2SSTS_SLVERRIF_Msk (0x1ul << SPI_I2SSTS_SLVERRIF_Pos) /*!< SPI_T::I2SSTS: SLVERRIF Mask */ + +#define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */ +#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */ + +#define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */ +#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */ + +#define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */ +#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */ + +/**@}*/ /* SPI_CONST */ +/**@}*/ /* end of SPI register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __SPI_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/sys_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/sys_reg.h new file mode 100644 index 0000000000..34af470c86 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/sys_reg.h @@ -0,0 +1,2617 @@ +/**************************************************************************//** + * @file sys_reg.h + * @version V1.00 + * @brief SYS register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SYS_REG_H__ +#define __SYS_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- System Manger Controller -------------------------*/ +/** + @addtogroup SYS System Manger Controller(SYS) + Memory Mapped Structure for SYS Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var SYS_T::PDID + * Offset: 0x00 Part Device Identification Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |PDID |Part Device Identification Number (Read Only) + * | | |This register reflects device part number code. + * | | |Software can read this register to identify which device is used. + * @var SYS_T::RSTSTS + * Offset: 0x04 System Reset Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PORF |POR Reset Flag + * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. + * | | |0 = No reset from POR or CHIPRST. + * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[1] |PINRF |nRESET Pin Reset Flag + * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. + * | | |0 = No reset from nRESET pin. + * | | |1 = Pin nRESET had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[2] |WDTRF |WDT Reset Flag + * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. + * | | |0 = No reset from watchdog timer or window watchdog timer. + * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. + * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. + * | | |Note 3: Extra Watchdog Timer register RSTF(EWDT_CTL[2]) bit is set if the system has been reset by EWDT time-out reset. + * | | |Extra Window Watchdog Timer register WWDTRF(EWWDT_STATUS[1]) bit is set if the system has been reset by EWWDT time-out reset. + * |[3] |LVRF |LVR Reset Flag + * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. + * | | |0 = No reset from LVR. + * | | |1 = LVR controller had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[4] |BODRF |BOD Reset Flag + * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-out Detector to indicate the previous reset source. + * | | |0 = No reset from BOD. + * | | |1 = The BOD had issued the reset signal to reset the system. + * | | |Note: Write 1 to clear this bit to 0. + * |[5] |SYSRF |System Reset Flag + * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M23 Core to indicate the previous reset source. + * | | |0 = No reset from Cortex-M23. + * | | |1 = The Cortex-M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23 core. + * | | |Note: Write 1 to clear this bit to 0. + * |[7] |CPURF |CPU Reset Flag + * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M23 Core and Flash Memory Controller (FMC). + * | | |0 = No reset from CPU. + * | | |1 = The Cortex-M23 Core and FMC are reset by software setting CPURST to 1. + * | | |Note: Write 1 to clear this bit to 0. + * |[8] |CPULKRF |CPU Lockup Reset Flag + * | | |The CPULK reset flag is set by hardware if Cortex-M23 lockup happened. + * | | |0 = No reset from CPU lockup happened. + * | | |1 = The Cortex-M23 lockup happened and chip is reset. + * | | |Note1: Write 1 to clear this bit to 0. + * | | |Note2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset. + * @var SYS_T::IPRST0 + * Offset: 0x08 Peripheral Reset Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CHIPRST |Chip One-shot Reset (Write Protect) + * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. + * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. + * | | |0 = Chip normal operation. + * | | |1 = Chip one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |CPURST |Processor Core One-shot Reset (Write Protect) + * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. + * | | |0 = Processor core normal operation. + * | | |1 = Processor core one-shot reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |PDMA0RST |PDMA0 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the PDMA0 (always secure). + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = PDMA0 controller normal operation. + * | | |1 = PDMA0 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |EBIRST |EBI Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the EBI + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = EBI controller normal operation. + * | | |1 = EBI controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |USBHRST |USB Host Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the USB Host. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = USB Host controller normal operation. + * | | |1 = USB Host controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |SDH0RST |SDHOST0 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = SDHOST0 controller normal operation. + * | | |1 = SDHOST0 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect) + * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRC calculation controller normal operation. + * | | |1 = CRC calculation controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = CRYPTO controller normal operation. + * | | |1 = CRYPTO controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |KSRST |Key Store Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller. + * | | |User needs to set this bit to 0 to release from the reset state. + * | | |0 = Key Store controller normal operation. + * | | |1 = Key Store controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[29] |PDMA1RST |PDMA1 Controller Reset (Write Protect) + * | | |Setting this bit to 1 will generate a reset signal to the PDMA1. + * | | |User needs to set this bit to 0 to release from reset state. + * | | |0 = PDMA1 controller normal operation. + * | | |1 = PDMA1 controller reset. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::IPRST1 + * Offset: 0x0C Peripheral Reset Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |GPIORST |GPIO Controller Reset + * | | |0 = GPIO controller normal operation. + * | | |1 = GPIO controller reset. + * |[2] |TMR0RST |Timer0 Controller Reset + * | | |0 = Timer0 controller normal operation. + * | | |1 = Timer0 controller reset. + * |[3] |TMR1RST |Timer1 Controller Reset + * | | |0 = Timer1 controller normal operation. + * | | |1 = Timer1 controller reset. + * |[4] |TMR2RST |Timer2 Controller Reset + * | | |0 = Timer2 controller normal operation. + * | | |1 = Timer2 controller reset. + * |[5] |TMR3RST |Timer3 Controller Reset + * | | |0 = Timer3 controller normal operation. + * | | |1 = Timer3 controller reset. + * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset + * | | |0 = Analog Comparator 0/1 controller normal operation. + * | | |1 = Analog Comparator 0/1 controller reset. + * |[8] |I2C0RST |I2C0 Controller Reset + * | | |0 = I2C0 controller normal operation. + * | | |1 = I2C0 controller reset. + * |[9] |I2C1RST |I2C1 Controller Reset + * | | |0 = I2C1 controller normal operation. + * | | |1 = I2C1 controller reset. + * |[10] |I2C2RST |I2C2 Controller Reset + * | | |0 = I2C2 controller normal operation. + * | | |1 = I2C2 controller reset. + * |[12] |QSPI0RST |QSPI0 Controller Reset + * | | |0 = QSPI0 controller normal operation. + * | | |1 = QSPI0 controller reset. + * |[13] |SPI0RST |SPI0 Controller Reset + * | | |0 = SPI0 controller normal operation. + * | | |1 = SPI0 controller reset. + * |[14] |SPI1RST |SPI1 Controller Reset + * | | |0 = SPI1 controller normal operation. + * | | |1 = SPI1 controller reset. + * |[15] |SPI2RST |SPI2 Controller Reset + * | | |0 = SPI2 controller normal operation. + * | | |1 = SPI2 controller reset. + * |[16] |UART0RST |UART0 Controller Reset + * | | |0 = UART0 controller normal operation. + * | | |1 = UART0 controller reset. + * |[17] |UART1RST |UART1 Controller Reset + * | | |0 = UART1 controller normal operation. + * | | |1 = UART1 controller reset. + * |[18] |UART2RST |UART2 Controller Reset + * | | |0 = UART2 controller normal operation. + * | | |1 = UART2 controller reset. + * |[19] |UART3RST |UART3 Controller Reset + * | | |0 = UART3 controller normal operation. + * | | |1 = UART3 controller reset. + * |[20] |UART4RST |UART4 Controller Reset + * | | |0 = UART4 controller normal operation. + * | | |1 = UART4 controller reset. + * |[21] |UART5RST |UART5 Controller Reset + * | | |0 = UART5 controller normal operation. + * | | |1 = UART5 controller reset. + * |[24] |CAN0RST |CAN0 Controller Reset + * | | |0 = CAN0 controller normal operation. + * | | |1 = CAN0 controller reset. + * |[26] |OTGRST |OTG Controller Reset + * | | |0 = OTG controller normal operation. + * | | |1 = OTG controller reset. + * |[27] |USBDRST |USBD Controller Reset + * | | |0 = USBD controller normal operation. + * | | |1 = USBD controller reset. + * |[28] |EADCRST |EADC Controller Reset + * | | |0 = EADC controller normal operation. + * | | |1 = EADC controller reset. + * |[29] |I2S0RST |I2S0 Controller Reset + * | | |0 = I2S0 controller normal operation. + * | | |1 = I2S0 controller reset. + * |[30] |LCDRST |LCD Controller Reset + * | | |0 = LCD controller normal operation. + * | | |1 = LCD controller reset. + * |[31] |TRNGRST |TRNG Controller Reset + * | | |0 = TRNG controller normal operation. + * | | |1 = TRNG controller reset. + * @var SYS_T::IPRST2 + * Offset: 0x10 Peripheral Reset Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SC0RST |SC0 Controller Reset + * | | |0 = SC0 controller normal operation. + * | | |1 = SC0 controller reset. + * |[1] |SC1RST |SC1 Controller Reset + * | | |0 = SC1 controller normal operation. + * | | |1 = SC1 controller reset. + * |[2] |SC2RST |SC2 Controller Reset + * | | |0 = SC2 controller normal operation. + * | | |1 = SC2 controller reset. + * |[6] |SPI3RST |SPI3 Controller Reset + * | | |0 = SPI3 controller normal operation. + * | | |1 = SPI3 controller reset. + * |[8] |USCI0RST |USCI0 Controller Reset + * | | |0 = USCI0 controller normal operation. + * | | |1 = USCI0 controller reset. + * |[9] |USCI1RST |USCI1 Controller Reset + * | | |0 = USCI1 controller normal operation. + * | | |1 = USCI1 controller reset. + * |[12] |DACRST |DAC Controller Reset + * | | |0 = DAC controller normal operation. + * | | |1 = DAC controller reset. + * |[16] |EPWM0RST |EPWM0 Controller Reset + * | | |0 = EPWM0 controller normal operation. + * | | |1 = EPWM0 controller reset. + * |[17] |EPWM1RST |EPWM1 Controller Reset + * | | |0 = EPWM1 controller normal operation. + * | | |1 = EPWM1 controller reset. + * |[18] |BPWM0RST |BPWM0 Controller Reset + * | | |0 = BPWM0 controller normal operation. + * | | |1 = BPWM0 controller reset. + * |[19] |BPWM1RST |BPWM1 Controller Reset + * | | |0 = BPWM1 controller normal operation. + * | | |1 = BPWM1 controller reset. + * |[20] |TMR4RST |Timer4 Controller Reset + * | | |0 = Timer4 controller normal operation. + * | | |1 = Timer4 controller reset. + * |[21] |TMR5RST |Timer5 Controller Reset + * | | |0 = Timer5 controller normal operation. + * | | |1 = Timer5 controller reset. + * |[22] |QEI0RST |QEI0 Controller Reset + * | | |0 = QEI0 controller normal operation. + * | | |1 = QEI0 controller reset. + * |[23] |QEI1RST |QEI1 Controller Reset + * | | |0 = QEI1 controller normal operation. + * | | |1 = QEI1 controller reset. + * |[26] |ECAP0RST |ECAP0 Controller Reset + * | | |0 = ECAP0 controller normal operation. + * | | |1 = ECAP0 controller reset. + * |[27] |ECAP1RST |ECAP1 Controller Reset + * | | |0 = ECAP1 controller normal operation. + * | | |1 = ECAP1 controller reset. + * @var SYS_T::BODCTL + * Offset: 0x18 Brown-out Detector Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect) + * | | |The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]). + * | | |0 = Brown-out Detector function Disabled. + * | | |1 = Brown-out Detector function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect) + * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit . + * | | |0 = Brown-out INTERRUPT function Enabled. + * | | |1 = Brown-out RESET function Enabled. + * | | |Note1: + * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). + * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if AVDD high.than BODVL, BOD interrupt will keep till to the BODIF set to 0. + * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |BODIF |Brown-out Detector Interrupt Flag + * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. + * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. + * | | |Note: Write 1 to clear this bit to 0. + * |[6] |BODOUT |Brown-out Detector Output Status + * | | |0 = Brown-out Detector output status is 0. + * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0. + * | | |1 = Brown-out Detector output status is 1. + * | | |It means the detected voltage is lower than BODVL setting. + * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0. + * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect) + * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. + * | | |LVR function is enabled by default. + * | | |0 = Low Voltage Reset function Disabled. + * | | |1 = Low Voltage Reset function Enabled. + * | | |Note1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default). + * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect) + * | | |000 = BOD output is sampled by LIRC clock. + * | | |001 = 4 system clock (HCLK). + * | | |010 = 8 system clock (HCLK). + * | | |011 = 16 system clock (HCLK). + * | | |100 = 32 system clock (HCLK). + * | | |101 = 64 system clock (HCLK). + * | | |110 = 128 system clock (HCLK). + * | | |111 = 256 system clock (HCLK). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) + * | | |000 = Without de-glitch function. + * | | |001 = 4 system clock (HCLK). + * | | |010 = 8 system clock (HCLK). + * | | |011 = 16 system clock (HCLK). + * | | |100 = 32 system clock (HCLK). + * | | |101 = 64 system clock (HCLK). + * | | |110 = 128 system clock (HCLK). + * | | |111 = 256 system clock (HCLK). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[23] |STB |Circuit Stable Flag (Read Only) + * | | |This bit indicates LVR and BOD already stable, system cannot detect LVR and BOD event when this bit is not set. + * | | |0 = LVR and BOD is not stable. + * | | |1 = LVR and BOD already stable. + * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect) + * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]). + * | | |000 = Brown-out Detector threshold voltage is 1.6V. + * | | |001 = Brown-out Detector threshold voltage is 1.8V. + * | | |010 = Brown-out Detector threshold voltage is 2.0V. + * | | |011 = Brown-out Detector threshold voltage is 2.2V. + * | | |100 = Brown-out Detector threshold voltage is 2.4V. + * | | |101 = Brown-out Detector threshold voltage is 2.6V. + * | | |110 = Brown-out Detector threshold voltage is 2.8V. + * | | |111 = Brown-out Detector threshold voltage is 3.0V. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[31] |WRBUSY |Write Busy Flag (Read Only) + * | | |If SYS_BODCTL is written, this bit is asserted automatically by hardware, and is de-asserted when write procedure is finished. + * | | |0 = SYS_BODCTL register is ready for write operation. + * | | |1 = SYS_BODCTL register is busy on the last write operation. Other write operations are ignored. + * @var SYS_T::IVSCTL + * Offset: 0x1C Internal Voltage Source Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VTEMPEN |Temperature Sensor Enable Bit + * | | |This bit is used to enable/disable temperature sensor function. + * | | |0 = Temperature sensor function Disabled (default). + * | | |1 = Temperature sensor function Enabled. + * | | |Note: After this bit is set to 1, the value of temperature sensor output can be obtained through GPC.9. + * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit + * | | |This bit is used to enable/disable VBAT unity gain buffer function. + * | | |0 = VBAT unity gain buffer function Disabled (default). + * | | |1 = VBAT unity gain buffer function Enabled. + * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result. + * @var SYS_T::PORCTL0 + * Offset: 0x24 Power-on Reset Controller Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PORMASK |Power-on Reset Mask Enable Bit (Write Protect) + * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. + * | | |User can mask internal POR signal to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. + * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: + * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::VREFCTL + * Offset: 0x28 VREF Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[4:0] |VREFCTL |VREF Control Bits (Write Protect) + * | | |00000 = VREF is from external pin. + * | | |00011 = VREF is internal 1.6V. + * | | |00111 = VREF is internal 2.0V. + * | | |01011 = VREF is internal 2.5V. + * | | |01111 = VREF is internal 3.0V. + * | | |Others = Reserved. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[5] |IBIASSEL |VREF Bias Current Selection (Write Protect) + * | | |0 = Bias current from MEGBIAS. + * | | |1 = Bias current from internal. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7:6] |PRELOADSEL|Pre-load Timing Selection (Write Protect) + * | | |00 = pre-load time is 60us for 0.1uF Capacitor. + * | | |01 = pre-load time is 310us for 1uF Capacitor. + * | | |10 = pre-load time is 1270us for 4.7uF Capacitor. + * | | |11 = pre-load time is 2650us for 10uF Capacitor. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::USBPHY + * Offset: 0x2C USB PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |USBROLE |USB Role Option (Write Protect) + * | | |These two bits are used to select the role of USB. + * | | |00 = Standard USB Device mode. + * | | |01 = Standard USB Host mode. + * | | |10 = ID dependent mode. + * | | |11 = On-The-Go device mode (default). + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable. + * |[8] |OTGPHYEN |USB OTG PHY Enable + * | | |This bit is used to enable/disable OTG PHY function. + * | | |0 = OTG PHY function Disabled (default). + * | | |1 = OTG PHY function Enabled. + * @var SYS_T::GPA_MFPL + * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection + * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection + * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection + * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection + * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection + * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection + * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection + * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection + * @var SYS_T::GPA_MFPH + * Offset: 0x34 GPIOA High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection + * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection + * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection + * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection + * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection + * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection + * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection + * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection + * @var SYS_T::GPB_MFPL + * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection + * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection + * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection + * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection + * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection + * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection + * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection + * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection + * @var SYS_T::GPB_MFPH + * Offset: 0x3C GPIOB High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection + * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection + * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection + * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection + * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection + * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection + * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection + * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection + * @var SYS_T::GPC_MFPL + * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection + * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection + * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection + * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection + * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection + * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection + * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection + * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection + * @var SYS_T::GPC_MFPH + * Offset: 0x44 GPIOC High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection + * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection + * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection + * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection + * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection + * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection + * @var SYS_T::GPD_MFPL + * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection + * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection + * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection + * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection + * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection + * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection + * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection + * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection + * @var SYS_T::GPD_MFPH + * Offset: 0x4C GPIOD High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection + * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection + * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection + * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection + * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection + * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection + * @var SYS_T::GPE_MFPL + * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection + * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection + * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection + * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection + * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection + * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection + * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection + * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection + * @var SYS_T::GPE_MFPH + * Offset: 0x54 GPIOE High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection + * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection + * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection + * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection + * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection + * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection + * |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection + * |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection + * @var SYS_T::GPF_MFPL + * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection + * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection + * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection + * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection + * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection + * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection + * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection + * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection + * @var SYS_T::GPF_MFPH + * Offset: 0x5C GPIOF High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection + * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection + * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection + * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection + * @var SYS_T::GPG_MFPL + * Offset: 0x60 GPIOG Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection + * |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection + * |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection + * @var SYS_T::GPG_MFPH + * Offset: 0x64 GPIOG High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection + * |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection + * |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection + * |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection + * |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection + * |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection + * |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection + * @var SYS_T::GPH_MFPL + * Offset: 0x68 GPIOH Low Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection + * |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection + * |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection + * |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection + * @var SYS_T::GPH_MFPH + * Offset: 0x6C GPIOH High Byte Multiple Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection + * |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection + * |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection + * |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection + * @var SYS_T::VTORSET + * Offset: 0xA0 VTOR Setting Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VTORSET |VTOR Setting After SPD Wakeup (Write Protect) + * | | |This is the register to set the address of vector table after chip is waked up from SPD Power-down mode. + * | | |The value will be loaded to Vector Table Offset Register, which is at the address 0xE000ED08, when chip wake up from SPD mode. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::SRAMICTL + * Offset: 0xC0 System SRAM Parity Error Interrupt Enable Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit + * | | |0 = SRAM parity check error interrupt Disabled. + * | | |1 = SRAM parity check error interrupt Enabled. + * @var SYS_T::SRAMSTS + * Offset: 0xC4 System SRAM Parity Check Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PERRIF |SRAM Parity Check Error Flag + * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. + * | | |0 = No System SRAM parity error. + * | | |1 = System SRAM parity error occur. + * @var SYS_T::SRAMEADR + * Offset: 0xC8 System SRAM Parity Check Error Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |ERRADDR |System SRAM Parity Error Address + * | | |This register shows system SRAM parity error byte address. + * @var SYS_T::SRAMPC0 + * Offset: 0xDC SRAM Power Mode Control Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SRAM0PM0 |Bank0 SRAM Power Mode Select 0 (Write Protect) + * | | |This field can control SRAM bank0 selection 0 (4k) power mode for range 0x2000_0000 - 0x2000_0FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[3:2] |SRAM0PM1 |Bank0 SRAM Power Mode Select 1 (Write Protect) + * | | |This field can control SRAM bank0 selection 1 power mode for range 0x2000_1000 - 0x2000_1FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[5:4] |SRAM0PM2 |Bank0 SRAM Power Mode Select 2 (Write Protect) + * | | |This field can control SRAM bank0 selection 2 (8k) power mode for range 0x2000_2000 - 0x2000_3FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[7:6] |SRAM0PM3 |Bank0 SRAM Power Mode Select 3 (Write Protect) + * | | |This field can control SRAM bank0 selection 3 (8k) power mode for range 0x2000_4000 - 0x2000_5FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[9:8] |SRAM0PM4 |Bank0 SRAM Power Mode Select 4 (Write Protect) + * | | |This field can control SRAM0 bank0 selection 4 (8k) power mode for range 0x2000_6000 - 0x2000_7FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[11:10] |SRAM1PM0 |Bank1 SRAM Power Mode Select 0 (Write Protect) + * | | |This field can control SRAM bank1 selection 0 (16k) power mode for range 0x2000_8000 - 0x2000_BFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[13:12] |SRAM1PM1 |Bank1 SRAM Power Mode Select 1 (Write Protect) + * | | |This field can control SRAM bank1 selection 1 (16k) power mode for range 0x2000_C000 - 0x2000_FFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[15:14] |SRAM1PM2 |Bank1 SRAM Power Mode Select 2 (Write Protect) + * | | |This field can control SRAM bank1 selection 2 (16k) power mode for range 0x2001_0000 - 0x2001_3FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[17:16] |SRAM1PM3 |Bank1 SRAM Power Mode Select 3 (Write Protect) + * | | |This field can control SRAM bank1 selection 3 (16k) power mode for range 0x2001_4000 - 0x2001_7FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[19:18] |SRAM1PM4 |Bank1 SRAM Power Mode Select 4 (Write Protect) + * | | |This field can control SRAM bank1 selection 4 (16k) power mode for range 0x2001_8000 - 0x2001_BFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[21:20] |SRAM1PM5 |Bank1 SRAM Power Mode Select 5 (Write Protect) + * | | |This field can control SRAM bank1 selection 5 (16k) power mode for range 0x2001_C000 - 0x2001_FFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[23:22] |SRAM1PM6 |Bank1 SRAM Power Mode Select 6 (Write Protect) + * | | |This field can control SRAM bank1 selection 6 (16k) power mode for range 0x2002_0000 - 0x2002_3FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[25:24] |SRAM1PM7 |Bank1 SRAM Power Mode Select 7 (Write Protect) + * | | |This field can control SRAM bank1 selection 7 (16k) power mode for range 0x2002_4000 - 0x2002_7FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[27:26] |SRAM2PM0 |Bank2 SRAM Power Mode Select 0 (Write Protect) + * | | |This field can control SRAM bank2 selection 0 (16k) power mode for range 0x2002_8000 - 0x2002_BFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[29:28] |SRAM2PM1 |Bank2 SRAM Power Mode Select 1 (Write Protect) + * | | |This field can control SRAM bank2 selection 1 (16k) power mode for range 0x2002_C000 - 0x2002_FFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[31] |PCBUSY |Power Changing Busy Flag (Read Only) + * | | |This bit indicate SRAM power changing. + * | | |0 = SRAM power change finish. + * | | |1 = SRAM power changing. + * @var SYS_T::SRAMPC1 + * Offset: 0xE0 SRAM Power Mode Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SRAM2PM2 |Bank2 SRAM Power Mode Select 2 (Write Protect) + * | | |This field can control SRAM bank2 selection 2 (16k) power mode for range 0x2003_0000 - 0x2003_3FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[3:2] |SRAM2PM3 |Bank2 SRAM Power Mode Select 3 (Write Protect) + * | | |This field can control bank2 sram3 (16k) power mode for range 0x2003_4000 - 0x2003_7FFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[5:4] |SRAM2PM4 |Bank2 SRAM Power Mode Select 4 (Write Protect) + * | | |This field can control SRAM bank2 selection 4 (16k) power mode for range 0x2003_8000 - 0x2003_BFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[7:6] |SRAM2PM5 |Bank2 SRAM Power Mode Select 5 (Write Protect) + * | | |This field can control SRAM bank2 selection 5 (16k) power mode for range 0x2003_C000 - 0x2003_FFFF. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[17:16] |CAN |CAN SRAM Power Mode Select (Write Protect) + * | | |This field can control CAN sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved. + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[19:18] |USBD |USB Device SRAM Power Mode Select (Write Protect) + * | | |This field can control USB device sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[21:20] |PDMA0 |PDMA SRAM Power Mode Select (Write Protect) + * | | |This field can control PDMA0 (always secure) sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[23:22] |PDMA1 |PDMA SRAM Power Mode Select (Write Protect) + * | | |This field can control PDMA1 sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[25:24] |FMCCACHE |FMC Cache SRAM Power Mode Select (Write Protect) + * | | |This field can control FMC cache sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[27:26] |RSA |RSA SRAM Power Mode Select (Write Protect) + * | | |This field can control RSA sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * | | |Note 3: If CRPTPWREN of SYS_PSWCTL is set to 1, RSA SRAM is auto set to normal mode by hardware. + * |[29:28] |KS |Key Store SRAM Power Mode Select (Write Protect) + * | | |This field can control Key Store sram power mode. + * | | |00 = Normal mode. + * | | |01 = Retention mode. + * | | |10 = Power shut down mode. + * | | |11 = Reserved (Write Ignore). + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: Write ignore when PCBUSY is 1. + * |[31] |PCBUSY |Power Changing Busy Flag (Read Only) + * | | |This bit indicate SRAM power changing. + * | | |0 = SRAM power change finish. + * | | |1 = SRAM power changing. + * @var SYS_T::TCTL48M + * Offset: 0xE4 HIRC 48M Trim Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FREQSEL |Trim Frequency Selection + * | | |This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC48) auto trim. + * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. + * | | |00 = Disable HIRC auto trim function. + * | | |01 = Enable HIRC auto trim function and trim HIRC to 48 MHz. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[5:4] |LOOPSEL |Trim Calculation Loop Selection + * | | |This field defines that trim value calculation is based on how many reference clocks. + * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. + * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. + * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. + * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. + * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. + * |[7:6] |RETRYCNT |Trim Value Update Limitation Count + * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. + * | | |Once the HIRC locked, the internal trim value update counter will be reset. + * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. + * | | |00 = Trim retry count limitation is 64 loops. + * | | |01 = Trim retry count limitation is 128 loops. + * | | |10 = Trim retry count limitation is 256 loops. + * | | |11 = Trim retry count limitation is 512 loops. + * |[9] |BOUNDEN |Boundary Enable Bit + * | | |0 = Boundary function is disable. + * | | |1 = Boundary function is enable. + * |[8] |CESTOPEN |Clock Error Stop Enable Bit + * | | |0 = The trim operation is keep going if clock is inaccuracy. + * | | |1 = The trim operation is stopped if clock is inaccuracy. + * |[10] |REFCKSEL |Reference Clock Selection + * | | |0 = HIRC trim 48M reference clock is from external 32.768 kHz crystal oscillator. + * | | |1 = HIRC trim 48M reference clock is from internal USB synchronous mode. + * |[20:16] |BOUNDARY |Boundary Selection + * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. + * | | |Note: This field is effective only when the BOUNDEN(SYS_TCTL48M [9]) is enable. + * @var SYS_T::TIEN48M + * Offset: 0xE8 HIRC 48M Trim Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit + * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL48M[1:0]). + * | | |If this bit is high and TFAILIF(SYS_TISTS48M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |0 = Disable TFAILIF(SYS_TISTS48M[1]) status to trigger an interrupt to CPU. + * | | |1 = Enable TFAILIF(SYS_TISTS48MM[1]) status to trigger an interrupt to CPU. + * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit + * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. + * | | |If this bit is set to1, and CLKERRIF(SYS_TISTS48M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |0 = Disable CLKERRIF(SYS_TISTS48M[2]) status to trigger an interrupt to CPU. + * | | |1 = Enable CLKERRIF(SYS_TISTS48M[2]) status to trigger an interrupt to CPU. + * @var SYS_T::TISTS48M + * Offset: 0xEC HIRC 48M Trim Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FREQLOCK |HIRC Frequency Lock Status + * | | |This bit indicates the HIRC frequency is locked. + * | | |This is a status bit and doesn't trigger any interrupt. + * | | |Write 1 to clear this to 0. + * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. + * | | |0 = The internal high-speed oscillator frequency doesn't lock at 48 MHz yet. + * | | |1 = The internal high-speed oscillator frequency locked at 48 MHz. + * |[1] |TFAILIF |Trim Failure Interrupt Status + * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. + * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL48M[1:0]) will be cleared to 00 by hardware automatically. + * | | |If this bit is set and TFAILIEN(SYS_TIEN48M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |Write 1 to clear this to 0. + * | | |0 = Trim value update limitation count does not reach. + * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. + * |[2] |CLKERRIF |Clock Error Interrupt Status + * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC48) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy + * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TICTL48M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL48M[8]) is set to 1. + * | | |If this bit is set and CLKEIEN(SYS_TIEN48M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |Write 1 to clear this to 0. + * | | |0 = Clock frequency is accuracy. + * | | |1 = Clock frequency is inaccuracy. + * |[3] |OVBDIF |Over Boundary Status + * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. + * | | |0 = Over boundary condition did not occur. + * | | |1 = Over boundary condition occurred. + * | | |Note: Write 1 to clear this flag. + * @var SYS_T::TCTL12M + * Offset: 0xF0 HIRC 12M Trim Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |FREQSEL |Trim Frequency Selection + * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim. + * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. + * | | |00 = Disable HIRC auto trim function. + * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz. + * | | |10 = Reserved. + * | | |11 = Reserved. + * |[5:4] |LOOPSEL |Trim Calculation Loop Selection + * | | |This field defines that trim value calculation is based on how many reference clocks. + * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. + * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. + * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. + * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. + * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. + * |[7:6] |RETRYCNT |Trim Value Update Limitation Count + * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. + * | | |Once the HIRC locked, the internal trim value update counter will be reset. + * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. + * | | |00 = Trim retry count limitation is 64 loops. + * | | |01 = Trim retry count limitation is 128 loops. + * | | |10 = Trim retry count limitation is 256 loops. + * | | |11 = Trim retry count limitation is 512 loops. + * |[9] |BOUNDEN |Boundary Enable Bit + * | | |0 = Boundary function is disable. + * | | |1 = Boundary function is enable. + * |[8] |CESTOPEN |Clock Error Stop Enable Bit + * | | |0 = The trim operation is keep going if clock is inaccuracy. + * | | |1 = The trim operation is stopped if clock is inaccuracy. + * |[10] |REFCKSEL |Reference Clock Selection + * | | |0 = HIRC trim reference clock is from external 32.768 kHz crystal oscillator. + * | | |1 = HIRC trim reference clock is from internal USB synchronous mode. + * |[20:16] |BOUNDARY |Boundary Selection + * | | |Fill the boundary range from 0x1 to 0x31, 0x0 is reserved. + * | | |Note: This field is effective only when the BOUNDEN(SYS_TCTL12M[9]) is enabled. + * @var SYS_T::TIEN12M + * Offset: 0xF4 HIRC 12M Trim Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit + * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL12M[1:0]). + * | | |If this bit is high and TFAILIF(SYS_TISTS12M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |0 = Disable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU. + * | | |1 = Enable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU. + * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit + * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. + * | | |If this bit is set to1, and CLKERRIF(SYS_TISTS12M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |0 = Disable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU. + * | | |1 = Enable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU. + * @var SYS_T::TISTS12M + * Offset: 0xF8 HIRC 12M Trim Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FREQLOCK |HIRC Frequency Lock Status + * | | |This bit indicates the HIRC frequency is locked. + * | | |This is a status bit and doesn't trigger any interrupt. + * | | |Write 1 to clear this to 0. + * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. + * | | |0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet. + * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz. + * |[1] |TFAILIF |Trim Failure Interrupt Status + * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. + * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL12M[1:0]) will be cleared to 00 by hardware automatically. + * | | |If this bit is set and TFAILIEN(SYS_TIEN12M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. + * | | |Write 1 to clear this to 0. + * | | |0 = Trim value update limitation count does not reach. + * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. + * |[2] |CLKERRIF |Clock Error Interrupt Status + * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy + * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TICTL12M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL12M[8]) is set to 1. + * | | |If this bit is set and CLKEIEN(SYS_TIEN12M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. + * | | |Write 1 to clear this to 0. + * | | |0 = Clock frequency is accuracy. + * | | |1 = Clock frequency is inaccuracy. + * |[3] |OVBDIF |Over Boundary Status + * | | |When the over boundary function is set, if there occurs the over boundary condition, this flag will be set. + * | | |0 = Over boundary condition did not occur. + * | | |1 = Over boundary condition occurred. + * | | |Note: Write 1 to clear this flag. + * @var SYS_T::REGLCTL + * Offset: 0x100 Register Lock Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REGLCTL |Register Lock Control Code (Write Only) + * | | |Some registers have write-protection function + * | | |Writing these registers have to disable the protected function by writing the sequence value 59h, 16h, 88h to this field. + * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. + * |[0] |REGLCTL[0]|Register Lock Control Disable Index (Read Only) + * | | |0 = Write-protection Enabled for writing protected registers. + * | | |Any write to the protected register is ignored. + * | | |1 = Write-protection Disabled for writing protected registers. + * @var SYS_T::CPUCFG + * Offset: 0x1D8 CPU General Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INTRTEN |CPU Interrupt Realtime Enable Bit + * | | |When this bit is 0, the latency of CPU entering interrupt service routine (ISR) will be various but shorter. + * | | |When this bit is 1, the latency of CPU entering ISR will be kept constant. + * | | |0 = CPU Interrupt Realtime Disabled. + * | | |1 = CPU Interrupt Realtime Enabled. + * @var SYS_T::PORCTL1 + * Offset: 0x1EC Power-on Reset Controller Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect) + * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. + * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. + * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: + * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::PSWCTL + * Offset: 0x1F4 Power Switch Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[12] |CRPTPWREN |Cryptographic Accelerator Power Switch Enable Bit (Write Protect) + * | | |0 = Cryptographic accelerator power supply Disabled. + * | | |1 = Cryptographic accelerator power supply Enabled. + * | | |Note 1: If this bit is set 1, RSA of SYS_SRAMPC1 is set to normal mode by hardware. + * | | |Note 2: Write ignored when PCBUSY(SYS_SRAMPC1[31]) is 1. + * | | |Note 3: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::PLCTL + * Offset: 0x1F8 Power Level Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |PLSEL |Power Level Select (Write Protect) + * | | |00 = Set to Power level 0 (PL0). Support system clock up to 96MHz. + * | | |01 = Set to Power level 1 (PL1). Support system clock up to 84MHz. + * | | |10 = Set to Power level 2 (PL2). Support system clock up to 64MHz. + * | | |11 = Set to Power level 3 (PL3). Support system clock up to 4MHz. + * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: These bits not be reset when wake-up from Standby Power-down mode(SPD). + * |[4] |MVRS |Main Voltage Regulator Type Select (Write Protect) + * | | |This bit filed sets main voltage regulator type. + * | | |After setting main voltage regulator type to DCDC (MVRS (SYS_PLCTL[4]) = 1) system will set main voltage regulator type change busy flag MVRCBUSY(SYS_PLSTS[1]), detect inductor connection and update inductor connection status LCONS (SYS_PLSTS[3]). + * | | |If inductor exist LCONS will be cleared and main voltage regulator type can switch to DCDC (CURMVRS (SYS_PLSTS[12])=1). + * | | |0 = Set main voltage regulator to LDO. + * | | |1 = Set main voltage regulator to DCDC. + * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note 2: This bit not be reset when wake-up from Standby Power-down mode(SPD). + * |[7] |WRBUSY |Write Busy Flag + * | | |If SYS_PLCTL be written, this bit be asserted automatic by hardware, and be de-asserted when write procedure finish. + * | | |0 = SYS_PLCTL register is ready for write operation. + * | | |1 = SYS_PLCTL register is busy on the last write operation. Other write operations are ignored. + * |[21:16] |LVSSTEP |LDO Voltage Scaling Step (Write Protect) + * | | |The LVSSTEP value is LDO voltage rising step. + * | | |LDO voltage scaling step = (LVSSTEP + 1) * 10mV. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * |[31:24] |LVSPRD |LDO Voltage Scaling Period (Write Protect) + * | | |The LVSPRD value is the period of each LDO voltage rising step. + * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us. + * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. + * @var SYS_T::PLSTS + * Offset: 0x1FC Power Level Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only) + * | | |This bit is set by hardware when power level is changing. + * | | |After power level change is completed, this bit will be cleared automatically by hardware. + * | | |0 = Power level change is completed. + * | | |1 = Power level change is ongoing. + * |[1] |MVRCBUSY |Main Voltage Regulator Type Change Busy Bit (Read Only) + * | | |This bit is set by hardware when main voltage regulator type is changing. + * | | |After main voltage regulator type change is completed, this bit will be cleared automatically by hardware. + * | | |0 = Main voltage regulator type change is completed. + * | | |1 = Main voltage regulator type change is ongoing. + * |[2] |MVRCERR |Main Voltage Regulator Type Change Error Bit (Write Protect) + * | | |This bit is set to 1 when main voltage regulator type change from LDO to DCDC error, the following conditions will cause change errors: + * | | |1.System change to DC-DC mode but LDO change voltage process not finish. + * | | |2.Detect inductor fail. + * | | |Read: + * | | |0 = No main voltage regulator type change error. + * | | |1 = Main voltage regulator type change to DCDC error occurred. + * | | |Write: + * | | |0 = No effect. + * | | |1 = Clears MVRCERR to 0. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |LCONS |Inductor for DC-DC Connect Status (Read Only) + * | | |0 = Inductor connect between Vsw and LDO_CAP pin. + * | | |This bit is valid when current main voltage regulator type is DCDC (CURMVRS (SYS_PLSTS[12])=1). + * | | |If current main voltage regulator type is LDO (CURMVRS (SYS_PLSTS[12])=0), this bit is set to 1. + * | | |0 = Inductor connect between Vsw and LDO_CAP pin. + * | | |1 = No Inductor connect between Vsw and LDO_CAP pin. + * | | |Note: This bit is 1 when main voltage regulator is LDO. + * |[9:8] |PLSTATUS |Power Level Status (Read Only) + * | | |This bit field reflect the current power level. + * | | |00 = Power level is PL0. Support system clock up to 96MHz. + * | | |01 = Power level is PL1. Support system clock up to 84MHz. + * | | |10 = Power level is PL2. Support system clock up to 48MHz. + * | | |11 = Power level is PL3. Support system clock up to 4MHz. + * |[12] |CURMVR |Current Main Voltage Regulator Type (Read Only) + * | | |This bit field reflects current main voltage regulator type. + * | | |0 = Current main voltage regulator in active and Idle mode is LDO. + * | | |1 = Current main voltage regulator in active and Idle mode is DCDC. + * @var SYS_T::AHBMCTL + * Offset: 0x400 AHB Bus Matrix Priority Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex-M23 Core Enable Bit (Write Protect) + * | | |Enable Cortex-M23 core with highest AHB bus priority in AHB bus matrix. + * | | |0 = Run robin mode. + * | | |1 = Cortex-M23 CPU with highest bus priority when interrupt occurs. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + */ + + __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */ + __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */ + __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */ + __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */ + __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */ + __I uint32_t RESERVE0[1]; + __IO uint32_t BODCTL; /*!< [0x0018] Brown-out Detector Control Register */ + __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */ + __I uint32_t RESERVE1[1]; + __IO uint32_t PORCTL0; /*!< [0x0024] Power-on Reset Controller Register 0 */ + __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */ + __IO uint32_t USBPHY; /*!< [0x002C] USB PHY Control Register */ + __IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */ + __IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */ + __IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */ + __IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */ + __IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */ + __IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */ + __IO uint32_t GPF_MFPH; /*!< [0x005C] GPIOF High Byte Multiple Function Control Register */ + __IO uint32_t GPG_MFPL; /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register */ + __IO uint32_t GPG_MFPH; /*!< [0x0064] GPIOG High Byte Multiple Function Control Register */ + __IO uint32_t GPH_MFPL; /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register */ + __IO uint32_t GPH_MFPH; /*!< [0x006C] GPIOH High Byte Multiple Function Control Register */ + __I uint32_t RESERVE2[4]; + __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */ + __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */ + __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */ + __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */ + __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */ + __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */ + __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */ + __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */ + __IO uint32_t VTORSET; /*!< [0x00A0] VTOR Setting Register */ + __I uint32_t RESERVE3[7]; + __IO uint32_t SRAMICTL; /*!< [0x00C0] System SRAM Interrupt Enable Control Register */ + __I uint32_t SRAMSTS; /*!< [0x00C4] System SRAM Parity Error Status Register */ + __I uint32_t SRAMEADR; /*!< [0x00C8] System SRAM Parity Check Error Address Register */ + __IO uint32_t RESERVE4[4]; + __IO uint32_t SRAMPC0; /*!< [0x00DC] SRAM Power Mode Control Register 0 */ + __IO uint32_t SRAMPC1; /*!< [0x00E0] SRAM Power Mode Control Register 1 */ + __IO uint32_t TCTL48M; /*!< [0x00E4] HIRC 48M Trim Control Register */ + __IO uint32_t TIEN48M; /*!< [0x00E8] HIRC 48M Trim Interrupt Enable Register */ + __IO uint32_t TISTS48M; /*!< [0x00EC] HIRC 48M Trim Interrupt Status Register */ + __IO uint32_t TCTL12M; /*!< [0x00F0] HIRC 12M Trim Control Register */ + __IO uint32_t TIEN12M; /*!< [0x00F4] HIRC 12M Trim Interrupt Enable Register */ + __IO uint32_t TISTS12M; /*!< [0x00F8] HIRC 12M Trim Interrupt Status Register */ + __I uint32_t RESERVE6[1]; + __IO uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */ + __I uint32_t RESERVE7[53]; + __IO uint32_t CPUCFG; /*!< [0x01D8] CPU General Configuration Register */ + __IO uint32_t BATLDCTL; /*!< [0x01DC] Battery Loss Detector Control Register */ + __IO uint32_t OVDCTL; /*!< [0x01E0] Over Voltage Detector Control Register */ + __I uint32_t RESERVE8[2]; + __IO uint32_t PORCTL1; /*!< [0x01EC] Power-on Reset Controller Register 1 */ + __I uint32_t RESERVE9[1]; + __IO uint32_t PSWCTL; /*!< [0x01F4] Power Switch Control Register */ + __IO uint32_t PLCTL; /*!< [0x01F8] Power Level Control Register */ + __IO uint32_t PLSTS; /*!< [0x01FC] Power Level Status Register */ + __I uint32_t RESERVE10[128]; + __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */ + + +} SYS_T; + +/** + @addtogroup SYS_CONST SYS Bit Field Definition + Constant Definitions for SYS Controller + @{ +*/ + +#define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */ +#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */ + +#define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ +#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ + +#define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ +#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ + +#define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */ +#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */ + +#define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ +#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ + +#define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */ +#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */ + +#define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */ +#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */ + +#define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */ +#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */ + +#define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */ +#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */ + +#define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ +#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ + +#define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */ +#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */ + +#define SYS_IPRST0_PDMA0RST_Pos (2) /*!< SYS_T::IPRST0: PDMA0RST Position */ +#define SYS_IPRST0_PDMA0RST_Msk (0x1ul << SYS_IPRST0_PDMA0RST_Pos) /*!< SYS_T::IPRST0: PDMA0RST Mask */ + +#define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */ +#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ + +#define SYS_IPRST0_USBHRST_Pos (4) /*!< SYS_T::IPRST0: USBHRST Position */ +#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */ + +#define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */ +#define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */ + +#define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */ +#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */ + +#define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */ +#define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */ + +#define SYS_IPRST0_KSRST_Pos (13) /*!< SYS_T::IPRST0: KSRST Position */ +#define SYS_IPRST0_KSRST_Msk (0x1ul << SYS_IPRST0_KSRST_Pos) /*!< SYS_T::IPRST0: KSRST Mask */ + +#define SYS_IPRST0_PDMA1RST_Pos (29) /*!< SYS_T::IPRST0: PDMA1RST Position */ +#define SYS_IPRST0_PDMA1RST_Msk (0x1ul << SYS_IPRST0_PDMA1RST_Pos) /*!< SYS_T::IPRST0: PDMA1RST Mask */ + +#define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */ +#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */ + +#define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ +#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ + +#define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ +#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ + +#define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ +#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ + +#define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ +#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ + +#define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */ +#define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */ + +#define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ +#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ + +#define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ +#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ + +#define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */ +#define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */ + +#define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ +#define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ + +#define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ +#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ + +#define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */ +#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */ + +#define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */ +#define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */ + +#define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ +#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ + +#define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ +#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ + +#define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ +#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ + +#define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */ +#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */ + +#define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */ +#define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */ + +#define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ +#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ + +#define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */ +#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */ + +#define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */ +#define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */ + +#define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */ +#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */ + +#define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */ +#define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */ + +#define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */ +#define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */ + +#define SYS_IPRST1_LCDRST_Pos (30) /*!< SYS_T::IPRST1: LCDRST Position */ +#define SYS_IPRST1_LCDRST_Msk (0x1ul << SYS_IPRST1_LCDRST_Pos) /*!< SYS_T::IPRST1: LCDRST Mask */ + +#define SYS_IPRST1_TRNGRST_Pos (31) /*!< SYS_T::IPRST1: TRNGRST Position */ +#define SYS_IPRST1_TRNGRST_Msk (0x1ul << SYS_IPRST1_TRNGRST_Pos) /*!< SYS_T::IPRST1: TRNGRST Mask */ + +#define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */ +#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */ + +#define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */ +#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */ + +#define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */ +#define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */ + +#define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ +#define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ + +#define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ +#define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ + +#define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */ +#define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */ + +#define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */ +#define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */ + +#define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */ +#define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */ + +#define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */ +#define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */ + +#define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */ +#define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */ + +#define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */ +#define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */ + +#define SYS_IPRST2_TMR4RST_Pos (20) /*!< SYS_T::IPRST2: TMR4RST Position */ +#define SYS_IPRST2_TMR4RST_Msk (0x1ul << SYS_IPRST2_TMR4RST_Pos) /*!< SYS_T::IPRST2: TMR4RST Mask */ + +#define SYS_IPRST2_TMR5RST_Pos (21) /*!< SYS_T::IPRST2: TMR5RST Position */ +#define SYS_IPRST2_TMR5RST_Msk (0x1ul << SYS_IPRST2_TMR5RST_Pos) /*!< SYS_T::IPRST2: TMR5RST Mask */ + +#define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */ +#define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */ + +#define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */ +#define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */ + +#define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */ +#define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */ + +#define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */ +#define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */ + +#define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */ +#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */ + +#define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */ +#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */ + +#define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */ +#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */ + +#define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */ +#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */ + +#define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */ +#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */ + +#define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */ +#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */ + +#define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */ +#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */ + +#define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */ +#define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */ + +#define SYS_BODCTL_STB_Pos (23) /*!< SYS_T::BODCTL: STB Position */ +#define SYS_BODCTL_STB_Msk (0x1ul << SYS_BODCTL_STB_Pos) /*!< SYS_T::BODCTL: STB Mask */ + +#define SYS_BODCTL_WRBUSY_Pos (31) /*!< SYS_T::BODCTL: WRBUSY Position */ +#define SYS_BODCTL_WRBUSY_Msk (0x1ul << SYS_BODCTL_WRBUSY_Pos) /*!< SYS_T::BODCTL: WRBUSY Mask */ + +#define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */ +#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */ + +#define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */ +#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */ + +#define SYS_PORCTL0_PORMASK_Pos (0) /*!< SYS_T::PORCTL0: PORMASK Position */ +#define SYS_PORCTL0_PORMASK_Msk (0xfffful << SYS_PORCTL0_PORMASK_Pos) /*!< SYS_T::PORCTL0: PORMASK Mask */ + +#define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */ +#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */ + +#define SYS_VREFCTL_IBIASSEL_Pos (5) /*!< SYS_T::VREFCTL: IBIASSEL Position */ +#define SYS_VREFCTL_IBIASSEL_Msk (0x1ul << SYS_VREFCTL_IBIASSEL_Pos) /*!< SYS_T::VREFCTL: IBIASSEL Mask */ + +#define SYS_VREFCTL_PRELOADSEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOADSEL Position */ +#define SYS_VREFCTL_PRELOADSEL_Msk (0x3ul << SYS_VREFCTL_PRELOADSEL_Pos) /*!< SYS_T::VREFCTL: PRELOADSEL Mask */ + +#define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */ +#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */ + +#define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */ +#define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */ + +#define SYS_USBPHY_OTGPHYEN_Pos (8) /*!< SYS_T::USBPHY: OTGPHYEN Position */ +#define SYS_USBPHY_OTGPHYEN_Msk (0x1ul << SYS_USBPHY_OTGPHYEN_Pos) /*!< SYS_T::USBPHY: OTGPHYEN Mask */ + +#define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */ +#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */ + +#define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */ +#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */ + +#define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */ +#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */ + +#define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */ +#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */ + +#define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */ +#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */ + +#define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */ +#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */ + +#define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */ +#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */ + +#define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */ +#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */ + +#define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */ +#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */ + +#define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */ +#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */ + +#define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */ +#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */ + +#define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */ +#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */ + +#define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */ +#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */ + +#define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */ +#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */ + +#define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */ +#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */ + +#define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */ +#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */ + +#define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */ +#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */ + +#define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */ +#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */ + +#define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */ +#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */ + +#define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */ +#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */ + +#define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */ +#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */ + +#define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */ +#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */ + +#define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */ +#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */ + +#define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */ +#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */ + +#define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */ +#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */ + +#define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */ +#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */ + +#define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */ +#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */ + +#define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */ +#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */ + +#define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */ +#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */ + +#define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */ +#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */ + +#define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */ +#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */ + +#define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */ +#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */ + +#define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */ +#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */ + +#define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */ +#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */ + +#define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */ +#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */ + +#define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */ +#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */ + +#define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */ +#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */ + +#define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */ +#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */ + +#define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */ +#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */ + +#define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */ +#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */ + +#define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */ +#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */ + +#define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */ +#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */ + +#define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */ +#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */ + +#define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */ +#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */ + +#define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */ +#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */ + +#define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */ +#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */ + +#define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */ +#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */ + +#define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */ +#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */ + +#define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */ +#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */ + +#define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */ +#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */ + +#define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */ +#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */ + +#define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */ +#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */ + +#define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */ +#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */ + +#define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */ +#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */ + +#define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */ +#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */ + +#define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */ +#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */ + +#define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */ +#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */ + +#define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */ +#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */ + +#define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */ +#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */ + +#define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */ +#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */ + +#define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */ +#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */ + +#define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */ +#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */ + +#define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */ +#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */ + +#define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */ +#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */ + +#define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */ +#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */ + +#define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */ +#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */ + +#define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */ +#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */ + +#define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */ +#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */ + +#define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */ +#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */ + +#define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */ +#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */ + +#define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */ +#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */ + +#define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */ +#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */ + +#define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */ +#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */ + +#define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */ +#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */ + +#define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */ +#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */ + +#define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */ +#define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */ + +#define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */ +#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */ + +#define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */ +#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */ + +#define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */ +#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */ + +#define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */ +#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */ + +#define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */ +#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */ + +#define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */ +#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */ + +#define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */ +#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */ + +#define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */ +#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */ + +#define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */ +#define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */ + +#define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */ +#define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */ + +#define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */ +#define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */ + +#define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */ +#define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */ + +#define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */ +#define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */ + +#define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */ +#define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */ + +#define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */ +#define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */ + +#define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */ +#define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */ + +#define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */ +#define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */ + +#define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */ +#define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */ + +#define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */ +#define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */ + +#define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */ +#define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */ + +#define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */ +#define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */ + +#define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */ +#define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */ + +#define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */ +#define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */ + +#define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */ +#define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */ + +#define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */ +#define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */ + +#define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */ +#define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */ + +#define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */ +#define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */ + +#define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */ +#define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */ + +#define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */ +#define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */ + +#define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */ +#define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */ + +#define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */ +#define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */ + +#define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */ +#define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */ + +#define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */ +#define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */ + +#define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */ +#define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */ + +#define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */ +#define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */ + +#define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */ +#define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */ + +#define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */ +#define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */ + +#define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */ +#define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */ + +#define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */ +#define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */ + +#define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */ +#define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */ + +#define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */ +#define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */ + +#define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */ +#define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */ + +#define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */ +#define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */ + +#define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */ +#define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */ + +#define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */ +#define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */ + +#define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */ +#define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */ + +#define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */ +#define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */ + +#define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */ +#define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */ + +#define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */ +#define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */ + +#define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */ +#define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */ + +#define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */ +#define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */ + +#define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */ +#define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */ + +#define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */ +#define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */ + +#define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */ +#define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */ + +#define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */ +#define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */ + +#define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */ +#define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */ + +#define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */ +#define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */ + +#define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */ +#define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */ + +#define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */ +#define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */ + +#define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */ +#define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */ + +#define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */ +#define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */ + +#define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */ +#define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */ + +#define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */ +#define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */ + +#define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */ +#define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */ + +#define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */ +#define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */ + +#define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */ +#define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */ + +#define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */ +#define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */ + +#define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */ +#define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */ + +#define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */ +#define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */ + +#define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */ +#define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */ + +#define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */ +#define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */ + +#define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */ +#define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */ + +#define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */ +#define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */ + +#define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */ +#define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */ + +#define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */ +#define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */ + +#define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */ +#define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */ + +#define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */ +#define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */ + +#define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */ +#define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */ + +#define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */ +#define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */ + +#define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */ +#define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */ + +#define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */ +#define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */ + +#define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */ +#define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */ + +#define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */ +#define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */ + +#define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */ +#define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */ + +#define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */ +#define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */ + +#define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */ +#define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */ + +#define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */ +#define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */ + +#define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */ +#define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */ + +#define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */ +#define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */ + +#define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */ +#define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */ + +#define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */ +#define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */ + +#define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */ +#define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */ + +#define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */ +#define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */ + +#define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */ +#define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */ + +#define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */ +#define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */ + +#define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */ +#define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */ + +#define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */ +#define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */ + +#define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */ +#define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */ + +#define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */ +#define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */ + +#define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */ +#define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */ + +#define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */ +#define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */ + +#define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */ +#define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */ + +#define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */ +#define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */ + +#define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */ +#define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */ + +#define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */ +#define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */ + +#define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */ +#define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */ + +#define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */ +#define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */ + +#define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */ +#define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */ + +#define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */ +#define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */ + +#define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */ +#define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */ + +#define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */ +#define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */ + +#define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */ +#define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */ + +#define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */ +#define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */ + +#define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */ +#define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */ + +#define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */ +#define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */ + +#define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */ +#define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */ + +#define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */ +#define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */ + +#define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */ +#define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */ + +#define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */ +#define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */ + +#define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */ +#define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */ + +#define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */ +#define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */ + +#define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */ +#define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */ + +#define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */ +#define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */ + +#define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */ +#define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */ + +#define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */ +#define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */ + +#define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */ +#define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */ + +#define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */ +#define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */ + +#define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */ +#define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */ + +#define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */ +#define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */ + +#define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */ +#define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */ + +#define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */ +#define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */ + +#define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */ +#define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */ + +#define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */ +#define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */ + +#define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */ +#define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */ + +#define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */ +#define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */ + +#define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */ +#define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */ + +#define SYS_VTORSET_VTORSET_Pos (11) /*!< SYS_T::VTORSET: VTORSET Position */ +#define SYS_VTORSET_VTORSET_Msk (0x3fffful << SYS_VTORSET_VTORSET_Pos) /*!< SYS_T::VTORSET: VTORSET Mask */ + +#define SYS_SRAMICTL_PERRIEN_Pos (0) /*!< SYS_T::SRAMICTL: PERRIEN Position */ +#define SYS_SRAMICTL_PERRIEN_Msk (0x1ul << SYS_SRAMICTL_PERRIEN_Pos) /*!< SYS_T::SRAMICTL: PERRIEN Mask */ + +#define SYS_SRAMSTS_PERRIF_Pos (0) /*!< SYS_T::SRAMSTS: PERRIF Position */ +#define SYS_SRAMSTS_PERRIF_Msk (0x1ul << SYS_SRAMSTS_PERRIF_Pos) /*!< SYS_T::SRAMSTS: PERRIF Mask */ + +#define SYS_SRAMEADR_ERRADDR_Pos (0) /*!< SYS_T::SRAMEADR: ERRADDR Position */ +#define SYS_SRAMEADR_ERRADDR_Msk (0xfffffffful << SYS_SRAMEADR_ERRADDR_Pos) /*!< SYS_T::SRAMEADR: ERRADDR Mask */ + +#define SYS_SRAMPC0_SRAM0PM0_Pos (0) /*!< SYS_T::SRAMPC0: SRAM0PM0 Position */ +#define SYS_SRAMPC0_SRAM0PM0_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM0_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM0 Mask */ + +#define SYS_SRAMPC0_SRAM0PM1_Pos (2) /*!< SYS_T::SRAMPC0: SRAM0PM1 Position */ +#define SYS_SRAMPC0_SRAM0PM1_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM1_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM1 Mask */ + +#define SYS_SRAMPC0_SRAM0PM2_Pos (4) /*!< SYS_T::SRAMPC0: SRAM0PM2 Position */ +#define SYS_SRAMPC0_SRAM0PM2_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM2_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM2 Mask */ + +#define SYS_SRAMPC0_SRAM0PM3_Pos (6) /*!< SYS_T::SRAMPC0: SRAM0PM3 Position */ +#define SYS_SRAMPC0_SRAM0PM3_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM3_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM3 Mask */ + +#define SYS_SRAMPC0_SRAM0PM4_Pos (8) /*!< SYS_T::SRAMPC0: SRAM0PM4 Position */ +#define SYS_SRAMPC0_SRAM0PM4_Msk (0x3ul << SYS_SRAMPC0_SRAM0PM4_Pos) /*!< SYS_T::SRAMPC0: SRAM0PM4 Mask */ + +#define SYS_SRAMPC0_SRAM1PM0_Pos (10) /*!< SYS_T::SRAMPC0: SRAM1PM0 Position */ +#define SYS_SRAMPC0_SRAM1PM0_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM0_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM0 Mask */ + +#define SYS_SRAMPC0_SRAM1PM1_Pos (12) /*!< SYS_T::SRAMPC0: SRAM1PM1 Position */ +#define SYS_SRAMPC0_SRAM1PM1_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM1_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM1 Mask */ + +#define SYS_SRAMPC0_SRAM1PM2_Pos (14) /*!< SYS_T::SRAMPC0: SRAM1PM2 Position */ +#define SYS_SRAMPC0_SRAM1PM2_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM2_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM2 Mask */ + +#define SYS_SRAMPC0_SRAM1PM3_Pos (16) /*!< SYS_T::SRAMPC0: SRAM1PM3 Position */ +#define SYS_SRAMPC0_SRAM1PM3_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM3_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM3 Mask */ + +#define SYS_SRAMPC0_SRAM1PM4_Pos (18) /*!< SYS_T::SRAMPC0: SRAM1PM4 Position */ +#define SYS_SRAMPC0_SRAM1PM4_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM4_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM4 Mask */ + +#define SYS_SRAMPC0_SRAM1PM5_Pos (20) /*!< SYS_T::SRAMPC0: SRAM1PM5 Position */ +#define SYS_SRAMPC0_SRAM1PM5_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM5_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM5 Mask */ + +#define SYS_SRAMPC0_SRAM1PM6_Pos (22) /*!< SYS_T::SRAMPC0: SRAM1PM6 Position */ +#define SYS_SRAMPC0_SRAM1PM6_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM6_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM6 Mask */ + +#define SYS_SRAMPC0_SRAM1PM7_Pos (24) /*!< SYS_T::SRAMPC0: SRAM1PM7 Position */ +#define SYS_SRAMPC0_SRAM1PM7_Msk (0x3ul << SYS_SRAMPC0_SRAM1PM7_Pos) /*!< SYS_T::SRAMPC0: SRAM1PM7 Mask */ + +#define SYS_SRAMPC0_SRAM2PM0_Pos (26) /*!< SYS_T::SRAMPC0: SRAM2PM0 Position */ +#define SYS_SRAMPC0_SRAM2PM0_Msk (0x3ul << SYS_SRAMPC0_SRAM2PM0_Pos) /*!< SYS_T::SRAMPC0: SRAM2PM0 Mask */ + +#define SYS_SRAMPC0_SRAM2PM1_Pos (28) /*!< SYS_T::SRAMPC0: SRAM2PM1 Position */ +#define SYS_SRAMPC0_SRAM2PM1_Msk (0x3ul << SYS_SRAMPC0_SRAM2PM1_Pos) /*!< SYS_T::SRAMPC0: SRAM2PM1 Mask */ + +#define SYS_SRAMPC0_PCBUSY_Pos (31) /*!< SYS_T::SRAMPC0: PCBUSY Position */ +#define SYS_SRAMPC0_PCBUSY_Msk (0x1ul << SYS_SRAMPC0_PCBUSY_Pos) /*!< SYS_T::SRAMPC0: PCBUSY Mask */ + +#define SYS_SRAMPC1_SRAM2PM2_Pos (0) /*!< SYS_T::SRAMPC1: SRAM2PM2 Position */ +#define SYS_SRAMPC1_SRAM2PM2_Msk (0x3ul << SYS_SRAMPC1_SRAM2PM2_Pos) /*!< SYS_T::SRAMPC1: SRAM2PM2 Mask */ + +#define SYS_SRAMPC1_SRAM2PM3_Pos (2) /*!< SYS_T::SRAMPC1: SRAM2PM3 Position */ +#define SYS_SRAMPC1_SRAM2PM3_Msk (0x3ul << SYS_SRAMPC1_SRAM2PM3_Pos) /*!< SYS_T::SRAMPC1: SRAM2PM3 Mask */ + +#define SYS_SRAMPC1_SRAM2PM4_Pos (4) /*!< SYS_T::SRAMPC1: SRAM2PM4 Position */ +#define SYS_SRAMPC1_SRAM2PM4_Msk (0x3ul << SYS_SRAMPC1_SRAM2PM4_Pos) /*!< SYS_T::SRAMPC1: SRAM2PM4 Mask */ + +#define SYS_SRAMPC1_SRAM2PM5_Pos (6) /*!< SYS_T::SRAMPC1: SRAM2PM5 Position */ +#define SYS_SRAMPC1_SRAM2PM5_Msk (0x3ul << SYS_SRAMPC1_SRAM2PM5_Pos) /*!< SYS_T::SRAMPC1: SRAM2PM5 Mask */ + +#define SYS_SRAMPC1_CAN_Pos (16) /*!< SYS_T::SRAMPC1: CAN Position */ +#define SYS_SRAMPC1_CAN_Msk (0x3ul << SYS_SRAMPC1_CAN_Pos) /*!< SYS_T::SRAMPC1: CAN Mask */ + +#define SYS_SRAMPC1_USBD_Pos (18) /*!< SYS_T::SRAMPC1: USBD Position */ +#define SYS_SRAMPC1_USBD_Msk (0x3ul << SYS_SRAMPC1_USBD_Pos) /*!< SYS_T::SRAMPC1: USBD Mask */ + +#define SYS_SRAMPC1_PDMA0_Pos (20) /*!< SYS_T::SRAMPC1: PDMA0 Position */ +#define SYS_SRAMPC1_PDMA0_Msk (0x3ul << SYS_SRAMPC1_PDMA0_Pos) /*!< SYS_T::SRAMPC1: PDMA0 Mask */ + +#define SYS_SRAMPC1_PDMA1_Pos (22) /*!< SYS_T::SRAMPC1: PDMA1 Position */ +#define SYS_SRAMPC1_PDMA1_Msk (0x3ul << SYS_SRAMPC1_PDMA1_Pos) /*!< SYS_T::SRAMPC1: PDMA1 Mask */ + +#define SYS_SRAMPC1_FMCCACHE_Pos (24) /*!< SYS_T::SRAMPC1: FMCCACHE Position */ +#define SYS_SRAMPC1_FMCCACHE_Msk (0x3ul << SYS_SRAMPC1_FMCCACHE_Pos) /*!< SYS_T::SRAMPC1: FMCCACHE Mask */ + +#define SYS_SRAMPC1_RSA_Pos (26) /*!< SYS_T::SRAMPC1: RSA Position */ +#define SYS_SRAMPC1_RSA_Msk (0x3ul << SYS_SRAMPC1_RSA_Pos) /*!< SYS_T::SRAMPC1: RSA Mask */ + +#define SYS_SRAMPC1_KS_Pos (28) /*!< SYS_T::SRAMPC1: KS Position */ +#define SYS_SRAMPC1_KS_Msk (0x3ul << SYS_SRAMPC1_KS_Pos) /*!< SYS_T::SRAMPC1: KS Mask */ + +#define SYS_SRAMPC1_PCBUSY_Pos (31) /*!< SYS_T::SRAMPC1: PCBUSY Position */ +#define SYS_SRAMPC1_PCBUSY_Msk (0x1ul << SYS_SRAMPC1_PCBUSY_Pos) /*!< SYS_T::SRAMPC1: PCBUSY Mask */ + +#define SYS_TCTL48M_FREQSEL_Pos (0) /*!< SYS_T::TCTL48M: FREQSEL Position */ +#define SYS_TCTL48M_FREQSEL_Msk (0x3ul << SYS_TCTL48M_FREQSEL_Pos) /*!< SYS_T::TCTL48M: FREQSEL Mask */ + +#define SYS_TCTL48M_LOOPSEL_Pos (4) /*!< SYS_T::TCTL48M: LOOPSEL Position */ +#define SYS_TCTL48M_LOOPSEL_Msk (0x3ul << SYS_TCTL48M_LOOPSEL_Pos) /*!< SYS_T::TCTL48M: LOOPSEL Mask */ + +#define SYS_TCTL48M_RETRYCNT_Pos (6) /*!< SYS_T::TCTL48M: RETRYCNT Position */ +#define SYS_TCTL48M_RETRYCNT_Msk (0x3ul << SYS_TCTL48M_RETRYCNT_Pos) /*!< SYS_T::TCTL48M: RETRYCNT Mask */ + +#define SYS_TCTL48M_CESTOPEN_Pos (8) /*!< SYS_T::TCTL48M: CESTOPEN Position */ +#define SYS_TCTL48M_CESTOPEN_Msk (0x1ul << SYS_TCTL48M_CESTOPEN_Pos) /*!< SYS_T::TCTL48M: CESTOPEN Mask */ + +#define SYS_TCTL48M_BOUNDEN_Pos (9) /*!< SYS_T::TCTL48M: BOUNDEN Position */ +#define SYS_TCTL48M_BOUNDEN_Msk (0x1ul << SYS_TCTL48M_BOUNDEN_Pos) /*!< SYS_T::TCTL48M: BOUNDEN Mask */ + +#define SYS_TCTL48M_REFCKSEL_Pos (10) /*!< SYS_T::TCTL48M: REFCKSEL Position */ +#define SYS_TCTL48M_REFCKSEL_Msk (0x1ul << SYS_TCTL48M_REFCKSEL_Pos) /*!< SYS_T::TCTL48M: REFCKSEL Mask */ + +#define SYS_TCTL48M_BOUNDARY_Pos (16) /*!< SYS_T::TCTL48M: BOUNDARY Position */ +#define SYS_TCTL48M_BOUNDARY_Msk (0x1ful << SYS_TCTL48M_BOUNDARY_Pos) /*!< SYS_T::TCTL48M: BOUNDARY Mask */ + +#define SYS_TIEN48M_TFAILIEN_Pos (1) /*!< SYS_T::TIEN48M: TFAILIEN Position */ +#define SYS_TIEN48M_TFAILIEN_Msk (0x1ul << SYS_TIEN48M_TFAILIEN_Pos) /*!< SYS_T::TIEN48M: TFAILIEN Mask */ + +#define SYS_TIEN48M_CLKEIEN_Pos (2) /*!< SYS_T::TIEN48M: CLKEIEN Position */ +#define SYS_TIEN48M_CLKEIEN_Msk (0x1ul << SYS_TIEN48M_CLKEIEN_Pos) /*!< SYS_T::TIEN48M: CLKEIEN Mask */ + +#define SYS_TISTS48M_FREQLOCK_Pos (0) /*!< SYS_T::TISTS48M: FREQLOCK Position */ +#define SYS_TISTS48M_FREQLOCK_Msk (0x1ul << SYS_TISTS48M_FREQLOCK_Pos) /*!< SYS_T::TISTS48M: FREQLOCK Mask */ + +#define SYS_TISTS48M_TFAILIF_Pos (1) /*!< SYS_T::TISTS48M: TFAILIF Position */ +#define SYS_TISTS48M_TFAILIF_Msk (0x1ul << SYS_TISTS48M_TFAILIF_Pos) /*!< SYS_T::TISTS48M: TFAILIF Mask */ + +#define SYS_TISTS48M_CLKERRIF_Pos (2) /*!< SYS_T::TISTS48M: CLKERRIF Position */ +#define SYS_TISTS48M_CLKERRIF_Msk (0x1ul << SYS_TISTS48M_CLKERRIF_Pos) /*!< SYS_T::TISTS48M: CLKERRIF Mask */ + +#define SYS_TISTS48M_OVBDIF_Pos (3) /*!< SYS_T::TISTS48M: OVBDIF Position */ +#define SYS_TISTS48M_OVBDIF_Msk (0x1ul << SYS_TISTS48M_OVBDIF_Pos) /*!< SYS_T::TISTS48M: OVBDIF Mask */ + +#define SYS_TCTL12M_FREQSEL_Pos (0) /*!< SYS_T::TCTL12M: FREQSEL Position */ +#define SYS_TCTL12M_FREQSEL_Msk (0x3ul << SYS_TCTL12M_FREQSEL_Pos) /*!< SYS_T::TCTL12M: FREQSEL Mask */ + +#define SYS_TCTL12M_LOOPSEL_Pos (4) /*!< SYS_T::TCTL12M: LOOPSEL Position */ +#define SYS_TCTL12M_LOOPSEL_Msk (0x3ul << SYS_TCTL12M_LOOPSEL_Pos) /*!< SYS_T::TCTL12M: LOOPSEL Mask */ + +#define SYS_TCTL12M_RETRYCNT_Pos (6) /*!< SYS_T::TCTL12M: RETRYCNT Position */ +#define SYS_TCTL12M_RETRYCNT_Msk (0x3ul << SYS_TCTL12M_RETRYCNT_Pos) /*!< SYS_T::TCTL12M: RETRYCNT Mask */ + +#define SYS_TCTL12M_CESTOPEN_Pos (8) /*!< SYS_T::TCTL12M: CESTOPEN Position */ +#define SYS_TCTL12M_CESTOPEN_Msk (0x1ul << SYS_TCTL12M_CESTOPEN_Pos) /*!< SYS_T::TCTL12M: CESTOPEN Mask */ + +#define SYS_TCTL12M_BOUNDEN_Pos (9) /*!< SYS_T::TCTL12M: BOUNDEN Position */ +#define SYS_TCTL12M_BOUNDEN_Msk (0x1ul << SYS_TCTL12M_BOUNDEN_Pos) /*!< SYS_T::TCTL12M: BOUNDEN Mask */ + +#define SYS_TCTL12M_REFCKSEL_Pos (10) /*!< SYS_T::TCTL12M: REFCKSEL Position */ +#define SYS_TCTL12M_REFCKSEL_Msk (0x1ul << SYS_TCTL12M_REFCKSEL_Pos) /*!< SYS_T::TCTL12M: REFCKSEL Mask */ + +#define SYS_TCTL12M_BOUNDARY_Pos (16) /*!< SYS_T::TCTL12M: BOUNDARY Position */ +#define SYS_TCTL12M_BOUNDARY_Msk (0x1ful << SYS_TCTL12M_BOUNDARY_Pos) /*!< SYS_T::TCTL12M: BOUNDARY Mask */ + +#define SYS_TIEN12M_TFAILIEN_Pos (1) /*!< SYS_T::TIEN12M: TFAILIEN Position */ +#define SYS_TIEN12M_TFAILIEN_Msk (0x1ul << SYS_TIEN12M_TFAILIEN_Pos) /*!< SYS_T::TIEN12M: TFAILIEN Mask */ + +#define SYS_TIEN12M_CLKEIEN_Pos (2) /*!< SYS_T::TIEN12M: CLKEIEN Position */ +#define SYS_TIEN12M_CLKEIEN_Msk (0x1ul << SYS_TIEN12M_CLKEIEN_Pos) /*!< SYS_T::TIEN12M: CLKEIEN Mask */ + +#define SYS_TISTS12M_FREQLOCK_Pos (0) /*!< SYS_T::TISTS12M: FREQLOCK Position */ +#define SYS_TISTS12M_FREQLOCK_Msk (0x1ul << SYS_TISTS12M_FREQLOCK_Pos) /*!< SYS_T::TISTS12M: FREQLOCK Mask */ + +#define SYS_TISTS12M_TFAILIF_Pos (1) /*!< SYS_T::TISTS12M: TFAILIF Position */ +#define SYS_TISTS12M_TFAILIF_Msk (0x1ul << SYS_TISTS12M_TFAILIF_Pos) /*!< SYS_T::TISTS12M: TFAILIF Mask */ + +#define SYS_TISTS12M_CLKERRIF_Pos (2) /*!< SYS_T::TISTS12M: CLKERRIF Position */ +#define SYS_TISTS12M_CLKERRIF_Msk (0x1ul << SYS_TISTS12M_CLKERRIF_Pos) /*!< SYS_T::TISTS12M: CLKERRIF Mask */ + +#define SYS_TISTS12M_OVBDIF_Pos (3) /*!< SYS_T::TISTS12M: OVBDIF Position */ +#define SYS_TISTS12M_OVBDIF_Msk (0x1ul << SYS_TISTS12M_OVBDIF_Pos) /*!< SYS_T::TISTS12M: OVBDIF Mask */ + +#define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */ +#define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */ + +#define SYS_CPUCFG_INTRTEN_Pos (0) /*!< SYS_T::CPUCFG: INTRTEN Position */ +#define SYS_CPUCFG_INTRTEN_Msk (0x1ul << SYS_CPUCFG_INTRTEN_Pos) /*!< SYS_T::CPUCFG: INTRTEN Mask */ + +#define SYS_OVDCTL_OVDEN_Pos (0) /*!< SYS_T::OVDCTL: OVDEN Position */ +#define SYS_OVDCTL_OVDEN_Msk (0x1ul << SYS_OVDCTL_OVDEN_Pos) /*!< SYS_T::OVDCTL: OVDEN Mask */ + +#define SYS_OVDCTL_OVDSTB_Pos (31) /*!< SYS_T::OVDCTL: OVDSTB Position */ +#define SYS_OVDCTL_OVDSTB_Msk (0x1ul << SYS_OVDCTL_OVDSTB_Pos) /*!< SYS_T::OVDCTL: OVDSTB Mask */ + +#define SYS_PORCTL1_POROFF_Pos (0) /*!< SYS_T::PORCTL1: POROFF Position */ +#define SYS_PORCTL1_POROFF_Msk (0xfffful << SYS_PORCTL1_POROFF_Pos) /*!< SYS_T::PORCTL1: POROFF Mask */ + +#define SYS_PSWCTL_CRPTPWREN_Pos (12) /*!< SYS_T::PSWCTL: CRPTPWREN Position */ +#define SYS_PSWCTL_CRPTPWREN_Msk (0x1ul << SYS_PSWCTL_CRPTPWREN_Pos) /*!< SYS_T::PSWCTL: CRPTPWREN Mask */ + +#define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */ +#define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */ + +#define SYS_PLCTL_MVRS_Pos (4) /*!< SYS_T::PLCTL: MVRS Position */ +#define SYS_PLCTL_MVRS_Msk (0x1ul << SYS_PLCTL_MVRS_Pos) /*!< SYS_T::PLCTL: MVRS Mask */ + +#define SYS_PLCTL_WRBUSY_Pos (7) /*!< SYS_T::PLCTL: WRBUSY Position */ +#define SYS_PLCTL_WRBUSY_Msk (0x1ul << SYS_PLCTL_WRBUSY_Pos) /*!< SYS_T::PLCTL: WRBUSY Mask */ + +#define SYS_PLCTL_LVSSTEP_Pos (16) /*!< SYS_T::PLCTL: LVSSTEP Position */ +#define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTP_Pos) /*!< SYS_T::PLCTL: LVSSTEP Mask */ + +#define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */ +#define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */ + +#define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */ +#define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */ + +#define SYS_PLSTS_MVRCBUSY_Pos (1) /*!< SYS_T::PLSTS: MVRCBUSY Position */ +#define SYS_PLSTS_MVRCBUSY_Msk (0x1ul << SYS_PLSTS_MVRCBUSY_Pos) /*!< SYS_T::PLSTS: MVRCBUSY Mask */ + +#define SYS_PLSTS_MVRCERR_Pos (2) /*!< SYS_T::PLSTS: MVRCERR Position */ +#define SYS_PLSTS_MVRCERR_Msk (0x1ul << SYS_PLSTS_MVRCERR_Pos) /*!< SYS_T::PLSTS: MVRCERR Mask */ + +#define SYS_PLSTS_LCONS_Pos (3) /*!< SYS_T::PLSTS: LCONS Position */ +#define SYS_PLSTS_LCONS_Msk (0x1ul << SYS_PLSTS_LCONS_Pos) /*!< SYS_T::PLSTS: LCONS Mask */ + +#define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */ +#define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */ + +#define SYS_PLSTS_CURMVR_Pos (12) /*!< SYS_T::PLSTS: CURMVR Position */ +#define SYS_PLSTS_CURMVR_Msk (0x1ul << SYS_PLSTS_CURMVR_Pos) /*!< SYS_T::PLSTS: CURMVR Mask */ + +#define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */ +#define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */ + + +/**@}*/ /* SYS_CONST */ +typedef struct +{ + + /** + * @var SYS_INT_T::NMIEN + * Offset: 0x00 NMI Source Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODOUT |BOD NMI Source Enable (Write Protect) + * | | |0 = BOD NMI source Disabled. + * | | |1 = BOD NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[1] |IRCINT |IRC TRIM NMI Source Enable (Write Protect) + * | | |0 = IRC TRIM NMI source Disabled. + * | | |1 = IRC TRIM NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |PWRWUINT |Power-down Mode Wake-up NMI Source Enable (Write Protect) + * | | |0 = Power-down mode wake-up NMI source Disabled. + * | | |1 = Power-down mode wake-up NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[3] |SRAMPERR |SRAM Parity Check Error NMI Source Enable (Write Protect) + * | | |0 = SRAM parity check error NMI source Disabled. + * | | |1 = SRAM parity check error NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[4] |CLKFAIL |Clock Fail Detected NMI Source Enable (Write Protect) + * | | |0 = Clock fail detected interrupt NMI source Disabled. + * | | |1 = Clock fail detected interrupt NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[6] |RTCINT |RTC NMI Source Enable (Write Protect) + * | | |0 = RTC NMI source Disabled. + * | | |1 = RTC NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |TAMPERINT |Tamper Interrupt NMI Source Enable (Write Protect) + * | | |0 = Backup register tamper detected interrupt NMI source Disabled. + * | | |1 = Backup register tamper detected interrupt NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[8] |EINT0 |External Interrupt From PA.6, or PB.5 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.6, or PB.5 pin NMI source Disabled. + * | | |1 = External interrupt from PA.6, or PB.5 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[9] |EINT1 |External Interrupt From PA.7 or PB.4 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.7 or PB.4 pin NMI source Disabled. + * | | |1 = External interrupt from PA.7 or P4.4 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled. + * | | |1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.2 or PC.7pin NMI source Disabled. + * | | |1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[12] |EINT4 |External Interrupt From PA.8 or PB.6 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PA.8 or PB.6 pin NMI source Disabled. + * | | |1 = External interrupt from PA.8 or PB.6 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[13] |EINT5 |External Interrupt From PB.7 or PD.12 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.7 or PD.12 pin NMI source Disabled. + * | | |1 = External interrupt from PB.7 or PD.12 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[14] |UART0INT |UART0 NMI Source Enable (Write Protect) + * | | |0 = UART0 NMI source Disabled. + * | | |1 = UART0 NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[15] |UART1INT |UART1 NMI Source Enable (Write Protect) + * | | |0 = UART1 NMI source Disabled. + * | | |1 = UART1 NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[16] |EINT6 |External Interrupt From PB.8 or PD.11 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.8 or PD.11 pin NMI source Disabled. + * | | |1 = External interrupt from PB.8 or PD.11 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[17] |EINT7 |External Interrupt From PB.9 or PD.10 Pin NMI Source Enable (Write Protect) + * | | |0 = External interrupt from PB.9 or PD.10 pin NMI source Disabled. + * | | |1 = External interrupt from PB.9 or PD.10 pin NMI source Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var SYS_INT_T::NMISTS + * Offset: 0x04 NMI source interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BODOUT |BOD Interrupt Flag (Read Only) + * | | |0 = BOD interrupt is de-asserted. + * | | |1 = BOD interrupt is asserted. + * |[1] |IRCINT |IRC TRIM Interrupt Flag (Read Only) + * | | |0 = HIRC TRIM interrupt is de-asserted. + * | | |1 = HIRC TRIM interrupt is asserted. + * |[2] |PWRWUINT |Power-down Mode Wake-up Interrupt Flag (Read Only) + * | | |0 = Power-down mode wake-up interrupt is de-asserted. + * | | |1 = Power-down mode wake-up interrupt is asserted. + * |[3] |SRAMPERR |SRAM Parity Check Error Interrupt Flag (Read Only) + * | | |0 = SRAM parity check error interrupt is de-asserted. + * | | |1 = SRAM parity check error interrupt is asserted. + * |[4] |CLKFAIL |Clock Fail Detected Interrupt Flag (Read Only) + * | | |0 = Clock fail detected interrupt is de-asserted. + * | | |1 = Clock fail detected interrupt is asserted. + * |[6] |RTCINT |RTC Interrupt Flag (Read Only) + * | | |0 = RTC interrupt is de-asserted. + * | | |1 = RTC interrupt is asserted. + * |[7] |TAMPERINT |Tamper Interrupt Flag (Read Only) + * | | |0 = Backup register tamper detected interrupt is de-asserted. + * | | |1 = Backup register tamper detected interrupt is asserted. + * |[8] |EINT0 |External Interrupt From PA.6, or PB.5 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.6, or PB.5 interrupt is deasserted. + * | | |1 = External Interrupt from PA.6, or PB.5 interrupt is asserted. + * |[9] |EINT1 |External Interrupt From PA.7, or PB.4 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.7, or PB.4 interrupt is deasserted. + * | | |1 = External Interrupt from PA.7, or PB.4 interrupt is asserted. + * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted. + * | | |1 = External Interrupt from PB.3 or PC.6 interrupt is asserted. + * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted. + * | | |1 = External Interrupt from PB.2 or PC.7 interrupt is asserted. + * |[12] |EINT4 |External Interrupt From PA.8 or PB.6 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PA.8 or PB.6 interrupt is deasserted. + * | | |1 = External Interrupt from PA.8 or PB.6 interrupt is asserted. + * |[13] |EINT5 |External Interrupt From PB.7 or PD.12 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.7 or PD.12 interrupt is deasserted. + * | | |1 = External Interrupt from PB.7 or PD.12 interrupt is asserted. + * |[14] |UART0INT |UART0 Interrupt Flag (Read Only) + * | | |0 = UART1 interrupt is de-asserted. + * | | |1 = UART1 interrupt is asserted. + * |[15] |UART1INT |UART1 Interrupt Flag (Read Only) + * | | |0 = UART1 interrupt is de-asserted. + * | | |1 = UART1 interrupt is asserted. + * |[16] |EINT6 |External Interrupt From PB.8 or PD.11 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.8 or PD.11 interrupt is deasserted. + * | | |1 = External Interrupt from PB.8 or PD.11 interrupt is asserted. + * |[17] |EINT7 |External Interrupt From PB.9 or PD.10 Pin Interrupt Flag (Read Only) + * | | |0 = External Interrupt from PB.9 or PD.10 interrupt is deasserted. + * | | |1 = External Interrupt from PB.9 or PD.10 interrupt is asserted. + */ + + __IO uint32_t NMIEN; /* Offset: 0x00 NMI Source Interrupt Enable Register */ + __I uint32_t NMISTS; /* Offset: 0x04 NMI source interrupt Status Register */ + +} SYS_INT_T; +/** + @addtogroup INT_CONST INT Bit Field Definition + Constant Definitions for INT Controller + @{ +*/ + +#define SYS_NMIEN_BODOUT_Pos (0) /*!< SYS_INT_T::NMIEN: BODOUT Position */ +#define SYS_NMIEN_BODOUT_Msk (0x1ul << SYS_NMIEN_BODOUT_Pos ) /*!< SYS_INT_T::NMIEN: BODOUT Mask */ + +#define SYS_NMIEN_IRCINT_Pos (1) /*!< SYS_INT_T::NMIEN: IRCINT Position */ +#define SYS_NMIEN_IRCINT_Msk (0x1ul << SYS_NMIEN_IRCINT_Pos ) /*!< SYS_INT_T::NMIEN: IRCINT Mask */ + +#define SYS_NMIEN_PWRWUINT_Pos (2) /*!< SYS_INT_T::NMIEN: PWRWUINT Position */ +#define SYS_NMIEN_PWRWUINT_Msk (0x1ul << SYS_NMIEN_PWRWUINT_Pos ) /*!< SYS_INT_T::NMIEN: PWRWUINT Mask */ + +#define SYS_NMIEN_SRAMPERR_Pos (3) /*!< SYS_INT_T::NMIEN: SRAMPERR Position */ +#define SYS_NMIEN_SRAMPERR_Msk (0x1ul << SYS_NMIEN_SRAMPERR_Pos ) /*!< SYS_INT_T::NMIEN: SRAMPERR Mask */ + +#define SYS_NMIEN_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMIEN: CLKFAIL Position */ +#define SYS_NMIEN_CLKFAIL_Msk (0x1ul << SYS_NMIEN_CLKFAIL_Pos ) /*!< SYS_INT_T::NMIEN: CLKFAIL Mask */ + +#define SYS_NMIEN_RTCINT_Pos (6) /*!< SYS_INT_T::NMIEN: RTCINT Position */ +#define SYS_NMIEN_RTCINT_Msk (0x1ul << SYS_NMIEN_RTCINT_Pos ) /*!< SYS_INT_T::NMIEN: RTCINT Mask */ + +#define SYS_NMIEN_TAMPERINT_Pos (7) /*!< SYS_INT_T::NMIEN: TAMPERINT Position */ +#define SYS_NMIEN_TAMPERINT_Msk (0x1ul << SYS_NMIEN_TAMPERINT_Pos ) /*!< SYS_INT_T::NMIEN: TAMPERINT Mask */ + +#define SYS_NMIEN_EINT0_Pos (8) /*!< SYS_INT_T::NMIEN: EINT0 Position */ +#define SYS_NMIEN_EINT0_Msk (0x1ul << SYS_NMIEN_EINT0_Pos ) /*!< SYS_INT_T::NMIEN: EINT0 Mask */ + +#define SYS_NMIEN_EINT1_Pos (9) /*!< SYS_INT_T::NMIEN: EINT1 Position */ +#define SYS_NMIEN_EINT1_Msk (0x1ul << SYS_NMIEN_EINT1_Pos ) /*!< SYS_INT_T::NMIEN: EINT1 Mask */ + +#define SYS_NMIEN_EINT2_Pos (10) /*!< SYS_INT_T::NMIEN: EINT2 Position */ +#define SYS_NMIEN_EINT2_Msk (0x1ul << SYS_NMIEN_EINT2_Pos ) /*!< SYS_INT_T::NMIEN: EINT2 Mask */ + +#define SYS_NMIEN_EINT3_Pos (11) /*!< SYS_INT_T::NMIEN: EINT3 Position */ +#define SYS_NMIEN_EINT3_Msk (0x1ul << SYS_NMIEN_EINT3_Pos ) /*!< SYS_INT_T::NMIEN: EINT3 Mask */ + +#define SYS_NMIEN_EINT4_Pos (12) /*!< SYS_INT_T::NMIEN: EINT4 Position */ +#define SYS_NMIEN_EINT4_Msk (0x1ul << SYS_NMIEN_EINT4_Pos ) /*!< SYS_INT_T::NMIEN: EINT4 Mask */ + +#define SYS_NMIEN_EINT5_Pos (13) /*!< SYS_INT_T::NMIEN: EINT5 Position */ +#define SYS_NMIEN_EINT5_Msk (0x1ul << SYS_NMIEN_EINT5_Pos ) /*!< SYS_INT_T::NMIEN: EINT5 Mask */ + +#define SYS_NMIEN_UART0INT_Pos (14) /*!< SYS_INT_T::NMIEN: UART0INT Position */ +#define SYS_NMIEN_UART0INT_Msk (0x1ul << SYS_NMIEN_UART0INT_Pos ) /*!< SYS_INT_T::NMIEN: UART0INT Mask */ + +#define SYS_NMIEN_UART1INT_Pos (15) /*!< SYS_INT_T::NMIEN: UART1INT Position */ +#define SYS_NMIEN_UART1INT_Msk (0x1ul << SYS_NMIEN_UART1INT_Pos ) /*!< SYS_INT_T::NMIEN: UART1INT Mask */ + +#define SYS_NMIEN_EINT6_Pos (16) /*!< SYS_INT_T::NMIEN: EINT6 Position */ +#define SYS_NMIEN_EINT6_Msk (0x1ul << SYS_NMIEN_EINT6_Pos ) /*!< SYS_INT_T::NMIEN: EINT6 Mask */ + +#define SYS_NMIEN_EINT7_Pos (17) /*!< SYS_INT_T::NMIEN: EINT7 Position */ +#define SYS_NMIEN_EINT7_Msk (0x1ul << SYS_NMIEN_EINT7_Pos ) /*!< SYS_INT_T::NMIEN: EINT7 Mask */ + +#define SYS_NMISTS_BODOUT_Pos (0) /*!< SYS_INT_T::NMISTS: BODOUT Position */ +#define SYS_NMISTS_BODOUT_Msk (0x1ul << SYS_NMISTS_BODOUT_Pos ) /*!< SYS_INT_T::NMISTS: BODOUT Mask */ + +#define SYS_NMISTS_IRCINT_Pos (1) /*!< SYS_INT_T::NMISTS: IRCINT Position */ +#define SYS_NMISTS_IRCINT_Msk (0x1ul << SYS_NMISTS_IRCINT_Pos ) /*!< SYS_INT_T::NMISTS: IRCINT Mask */ + +#define SYS_NMISTS_PWRWUINT_Pos (2) /*!< SYS_INT_T::NMISTS: PWRWUINT Position */ +#define SYS_NMISTS_PWRWUINT_Msk (0x1ul << SYS_NMISTS_PWRWUINT_Pos ) /*!< SYS_INT_T::NMISTS: PWRWUINT Mask */ + +#define SYS_NMISTS_SRAMPERR_Pos (3) /*!< SYS_INT_T::NMISTS: SRAMPERR Position */ +#define SYS_NMISTS_SRAMPERR_Msk (0x1ul << SYS_NMISTS_SRAMPERR_Pos ) /*!< SYS_INT_T::NMISTS: SRAMPERR Mask */ + +#define SYS_NMISTS_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMISTS: CLKFAIL Position */ +#define SYS_NMISTS_CLKFAIL_Msk (0x1ul << SYS_NMISTS_CLKFAIL_Pos ) /*!< SYS_INT_T::NMISTS: CLKFAIL Mask */ + +#define SYS_NMISTS_RTCINT_Pos (6) /*!< SYS_INT_T::NMISTS: RTCINT Position */ +#define SYS_NMISTS_RTCINT_Msk (0x1ul << SYS_NMISTS_RTCINT_Pos ) /*!< SYS_INT_T::NMISTS: RTCINT Mask */ + +#define SYS_NMISTS_TAMPERINT_Pos (7) /*!< SYS_INT_T::NMISTS: TAMPERINT Position */ +#define SYS_NMISTS_TAMPERINT_Msk (0x1ul << SYS_NMISTS_TAMPERINT_Pos ) /*!< SYS_INT_T::NMISTS: TAMPERINT Mask */ + +#define SYS_NMISTS_EINT0_Pos (8) /*!< SYS_INT_T::NMISTS: EINT0 Position */ +#define SYS_NMISTS_EINT0_Msk (0x1ul << SYS_NMISTS_EINT0_Pos ) /*!< SYS_INT_T::NMISTS: EINT0 Mask */ + +#define SYS_NMISTS_EINT1_Pos (9) /*!< SYS_INT_T::NMISTS: EINT1 Position */ +#define SYS_NMISTS_EINT1_Msk (0x1ul << SYS_NMISTS_EINT1_Pos ) /*!< SYS_INT_T::NMISTS: EINT1 Mask */ + +#define SYS_NMISTS_EINT2_Pos (10) /*!< SYS_INT_T::NMISTS: EINT2 Position */ +#define SYS_NMISTS_EINT2_Msk (0x1ul << SYS_NMISTS_EINT2_Pos ) /*!< SYS_INT_T::NMISTS: EINT2 Mask */ + +#define SYS_NMISTS_EINT3_Pos (11) /*!< SYS_INT_T::NMISTS: EINT3 Position */ +#define SYS_NMISTS_EINT3_Msk (0x1ul << SYS_NMISTS_EINT3_Pos ) /*!< SYS_INT_T::NMISTS: EINT3 Mask */ + +#define SYS_NMISTS_EINT4_Pos (12) /*!< SYS_INT_T::NMISTS: EINT4 Position */ +#define SYS_NMISTS_EINT4_Msk (0x1ul << SYS_NMISTS_EINT4_Pos ) /*!< SYS_INT_T::NMISTS: EINT4 Mask */ + +#define SYS_NMISTS_EINT5_Pos (13) /*!< SYS_INT_T::NMISTS: EINT5 Position */ +#define SYS_NMISTS_EINT5_Msk (0x1ul << SYS_NMISTS_EINT5_Pos ) /*!< SYS_INT_T::NMISTS: EINT5 Mask */ + +#define SYS_NMISTS_UART0INT_Pos (14) /*!< SYS_INT_T::NMISTS: UART0_INT Position */ +#define SYS_NMISTS_UART0INT_Msk (0x1ul << SYS_NMISTS_UART0INT_Pos ) /*!< SYS_INT_T::NMISTS: UART0_INT Mask */ + +#define SYS_NMISTS_UART1INT_Pos (15) /*!< SYS_INT_T::NMISTS: UART1_INT Position */ +#define SYS_NMISTS_UART1INT_Msk (0x1ul << SYS_NMISTS_UART1INT_Pos ) /*!< SYS_INT_T::NMISTS: UART1_INT Mask */ + +#define SYS_NMISTS_EINT6_Pos (16) /*!< SYS_INT_T::NMISTS: EINT6 Position */ +#define SYS_NMISTS_EINT6_Msk (0x1ul << SYS_NMISTS_EINT6_Pos ) /*!< SYS_INT_T::NMISTS: EINT6 Mask */ + +#define SYS_NMISTS_EINT7_Pos (17) /*!< SYS_INT_T::NMISTS: EINT7 Position */ +#define SYS_NMISTS_EINT7_Msk (0x1ul << SYS_NMISTS_EINT7_Pos ) /*!< SYS_INT_T::NMISTS: EINT7 Mask */ + + +/**@}*/ /* INT_CONST */ +/**@}*/ /* end of SYS register group */ +/**@}*/ /* end of REGISTER group */ + + +#endif /* __SYS_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/tamper_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/tamper_reg.h new file mode 100644 index 0000000000..9319702311 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/tamper_reg.h @@ -0,0 +1,1042 @@ +/**************************************************************************//** + * @file tamper_reg.h + * @version V1.00 + * @brief Tamper register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TAMPER_REG_H__ +#define __TAMPER_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------------- Tamper Controller ----------------------------*/ +/** + @addtogroup Tamper Controller(TAMPER) + Memory Mapped Structure for Tamper Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var TAMPER_T::INIT + * Offset: 0x00 Tamper Function Initiation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TCORERST |Tamper Core Reset + * | | |0 = Write 0x5500; the Tamper core block reset will be released. + * | | |1 = Write 0x55AA; the Tamper core block will be reset. + * |[31] |TLDORDY |Voltage Regulator Power Ready (Read Only) + * | | |0 = The power status of voltage regulator is not ready. + * | | |1 = The power status of voltage regulator is ready. + * @var TAMPER_T::FUNEN + * Offset: 0x04 Tamper Block Function Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LXTDETEN |LXT Clock Detection Enable Bit + * | | |0 = Write 0x40; the LXT clock detection Disabled. + * | | |1 = Write 0x44; the LXT clock detection Enabled. + * |[13:8] |TMPIOSEL |Tamper I/O Detection Selection Bit + * | | |0 = Write 0x90/0xA0/0xB0/0xC0/0xD0/0xE0 for tamper I/O 0~5; the I/O tamper function is detected through RTC block. + * | | |1 = Write 0x94/0xA4/0xB4/0xC4/0xD4/0xE4 for tamper I/O 0~5; the I/O tamper function is detected through Tamper block. + * |[23:16] |HIRC48MEN |HIRC48M Enable Bit + * | | |The HIRC48M is disabled when these bits equal 0x5A, otherwise it will be enabled with any other values. + * |[24] |VGCHEN0 |Voltage Glitch Channel 0 Enable Bit + * | | |0 = Voltage glitch channel 0 Disabled. + * | | |1 = Voltage glitch channel 0 Enabled. + * | | |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled. + * |[25] |VGCHEN1 |Voltage Glitch Channel 1 Enable Bit + * | | |0 = Voltage glitch channel 1 Disabled. + * | | |1 = Voltage glitch channel 1 Enabled. + * | | |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled. + * |[26] |VGCHEN2 |Voltage Glitch Channel 2 Enable Bit + * | | |0 = Voltage glitch channel 2 Disabled. + * | | |1 = Voltage glitch channel 2 Enabled. + * | | |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled. + * |[27] |VGCHEN3 |Voltage Glitch Channel 3 Enable Bit + * | | |0 = Voltage glitch channel 3 Disabled. + * | | |1 = Voltage glitch channel 3 Enabled. + * | | |Note: To avoid the voltage glitch when the voltage channel is enabled, it is better to detect the voltage glitch about 150us after the channel is enabled. + * @var TAMPER_T::TRIEN + * Offset: 0x08 Tamper Trigger Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |KSTRIGEN |Key Store Trigger Enable Bit + * | | |0 = Tamper event is detected and to trigger Key Store Disabled. + * | | |1 = Tamper event is detected and to trigger Key Store Enabled. + * |[2] |WAKEUPEN |Wakeup Enable Bit + * | | |0 = Tamper wakeup event Disabled. + * | | |1 = Tamper wakeup event Enabled. + * |[3] |CRYPTOEN |Crypto Enable Bit + * | | |0 = Tamper event clear Crypto Disabled. + * | | |1 = Tamper event clear Crypto Enabled. + * |[4] |CHIPRSTEN |Chip Reset Enable Bit + * | | |0 = Tamper event trigger chip reset Disabled. + * | | |1 = Tamper event trigger chip reset Enabled. + * |[5] |RTCSPCLREN|RTC Spare Register Clear Enable Bit + * | | |0 = Tamper event trigger RTC spare register reset Disabled. + * | | |1 = Tamper event trigger RTC spare register reset Enabled. + * @var TAMPER_T::INTEN + * Offset: 0x0C Tamper Event Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TAMP0IEN |Tamper 0 Event Interrupt Enable Bit + * | | |0 = Tamper 0 event interrupt Disabled. + * | | |1 = Tamper 0 event interrupt Enabled. + * |[1] |TAMP1IEN |Tamper 1 or Pair 0 Event Interrupt Enable Bit + * | | |0 = Tamper 1 or Pair 0 event interrupt Disabled. + * | | |1 = Tamper 1 or Pair 0 event interrupt Enabled. + * |[2] |TAMP2IEN |Tamper 2 Event Interrupt Enable Bit + * | | |0 = Tamper 2 event interrupt Disabled. + * | | |1 = Tamper 2 event interrupt Enabled. + * |[3] |TAMP3IEN |Tamper 3 or Pair 1 Event Interrupt Enable Bit + * | | |0 = Tamper 3 or Pair 1 event interrupt Disabled. + * | | |1 = Tamper 3 or Pair 1 event interrupt Enabled. + * |[4] |TAMP4IEN |Tamper 4 Event Interrupt Enable Bit + * | | |0 = Tamper 4 event interrupt Disabled. + * | | |1 = Tamper 4 event interrupt Enabled. + * |[5] |TAMP5IEN |Tamper 5 or Pair 2 Event Interrupt Enable Bit + * | | |0 = Tamper 5 or Pair 2 event interrupt Disabled. + * | | |1 = Tamper 5 or Pair 2 event interrupt Enabled. + * |[6] |CLKFIEN |LXT Clock Frequency Monitor Fail Event Interrupt Enable Bit + * | | |0 = LXT frequency fail event interrupt Disabled. + * | | |1 = LXT frequency fail event interrupt Enabled. + * |[7] |CLKSTOPIEN|LXT Clock Frequency Monitor Stop Event Interrupt Enable Bit + * | | |0 = LXT frequency stop event interrupt Disabled. + * | | |1 = LXT frequency stop event interrupt Enabled. + * |[8] |OVPIEN |VDD Over Voltage Protect Detection Interrupt Enable Bit + * | | |0 = Detect VDD over voltage protect detection interrupt Disabled. + * | | |1 = Detect VDD over voltage protect detection interrupt Enabled. + * | | |Note: The function enable of the over voltage detection is defined in system manager. + * |[9] |VGPIEN |Voltage Glitch Positive Detection Event Interrupt Enable Bit + * | | |0 = LDO_CAP positive glitch event interrupt Disabled. + * | | |1 = LDO_CAP positive glitch event interrupt Enabled. + * |[10] |VGNIEN |Voltage Glitch Negative Detection Event Interrupt Enable Bit + * | | |0 = LDO_CAP negative glitch event interrupt Disabled. + * | | |1 = LDO_CAP negative glitch event interrupt Enabled. + * |[11] |ACTSIEN |Active Shield Event Interrupt Enable Bit + * | | |0 = Active shield event interrupt Disabled. + * | | |1 = Active shield event interrupt Enabled. + * |[16] |RTCLVRIEN |RTC Low Voltage Detection Event Interrupt Enable Bit + * | | |0 = VBAT low voltage detection event interrupt Disabled. + * | | |1 = VBAT low voltage detection event interrupt Enabled. + * |[17] |RTCIOIEN |RTC Tamper I/O Event Interrupt Enable Bit + * | | |0 = RTC tamper I/O detection event interrupt Disabled. + * | | |1 = RTC tamper I/O detection event interrupt Enabled. + * |[18] |RTCLKIEN |RTC Clock Monitor Detection Event Interrupt Enable Bit + * | | |0 = RTC clock monitor event interrupt Disabled. + * | | |1 = RTC clock monitor event interrupt Enabled. + * |[22] |BODIEN |BOD Event Interrupt Enable Bit + * | | |0 = Brown-out event interrupt Disabled. + * | | |1 = Brown-out event interrupt Enabled. + * @var TAMPER_T::INTSTS + * Offset: 0x10 Tamper Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TAMP0IF |Tamper 0 Event Interrupt Flag + * | | |0 = No Tamper 0 event interrupt flag is generated. + * | | |1 = Tamper 0 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[1] |TAMP1IF |Tamper 1 Event Interrupt Flag + * | | |0 = No Tamper 1 event interrupt flag is generated. + * | | |1 = Tamper 1 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[2] |TAMP2IF |Tamper 2 Event Interrupt Flag + * | | |0 = No Tamper 2 event interrupt flag is generated. + * | | |1 = Tamper 2 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[3] |TAMP3IF |Tamper 3 Event Interrupt Flag + * | | |0 = No Tamper 3 event interrupt flag is generated. + * | | |1 = Tamper 3 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[4] |TAMP4IF |Tamper 4 Event Interrupt Flag + * | | |0 = No Tamper 4 event interrupt flag is generated. + * | | |1 = Tamper 4 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[5] |TAMP5IF |Tamper 5 Event Interrupt Flag + * | | |0 = No Tamper 5 event interrupt flag is generated. + * | | |1 = Tamper 5 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[6] |CLKFAILIF |LXT Clock Frequency Monitor Fail Event Interrupt Flag + * | | |0 = LXT frequency is normal. + * | | |1 = LXT frequency is abnormal. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: LXT detector will be automatically disabled when Fail/Stop flag rises, and resumes after Fail/Stop flag is cleared. + * |[7] |CLKSTOPIF |LXT Clock Frequency Monitor Stop Event Interrupt Flag + * | | |0 = LXT frequency is normal. + * | | |1 = LXT frequency is almost stopped. + * | | |Note 1: Write 1 to clear this bit to 0. + * | | |Note 2: LXT detector will be automatically disabled when Fail/Stop flag rises, and resumes after Fail/Stop flag is cleared. + * |[8] |OVPOUTIF |VDD Over Voltage Event Interrupt Flag + * | | |0 = VDD no over voltage is detected. + * | | |1 = VDD over voltage is detected. + * | | |Note: Write 1 to clear this bit. + * |[9] |VGPEVIF |Voltage Glitch Positive Detection Interrupt Flag + * | | |0 = LDO_CAP positive glitch is not detected. + * | | |1 = LDO_CAP positive glitch is detected. + * | | |Note: It can be written 1 to clear only (No clear by TCORERST) + * |[10] |VGNEVIF |Voltage Glitch Negative Detection Interrupt Flag + * | | |0 = LDO_CAP negative glitch is not detected. + * | | |1 = LDO_CAP negative glitch is detected. + * | | |Note: It can be written 1 to clear only (No clear by TCORERST) + * |[11] |ACTSEIF |Active Shield Event Detection Interrupt Flag + * | | |0 = Active shield event interrupt flag is not detected. + * | | |1 = Active shield event interrupt flag is detected including the voltage of voltage regulator and GND attack. + * | | |Note: Write 1 to clear this bit after all of ACTSTxIF bits have been cleaned. + * |[13] |ACTST5IF |Active Shield Tamper 5 Event Interrupt Flag + * | | |0 = No Active shield Tamper 5 event interrupt flag is generated. + * | | |1 = Active shield Tamper 5 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[15] |ACTST25IF |Active Shield Tamper 5 Event Interrupt Flag + * | | |0 = No Active shield Tamper 5 event interrupt flag is generated. + * | | |1 = 2th Active shield Tamper 5 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[16] |RTCLVRIF |RTC Low Voltage Detection Event Interrupt Flag + * | | |0 = VBAT low voltage detection event interrupt flag is not detected. + * | | |1 = VBAT low voltage detection event interrupt flag is detected. + * |[17] |RIOTRIGIF |RTC Tamper I/O Event Interrupt Flag + * | | |0 = There is no RTC tamper I/O detection event interrupt flag. + * | | |1 = There is RTC tamper I/O detection event interrupt flag. + * |[18] |RCLKTRIGIF|RTC Clock Monitor Detection Event Interrupt Flag + * | | |0 = There is no RTC clock monitor detection event interrupt flag. + * | | |1 = There is RTC clock monitor detection event interrupt flag. + * |[22] |BODIF |BOD Event Interrupt Flag + * | | |0 = Brown-out event interrupt flag is no detected. + * | | |1 = Brown-out interrupt flag is detected. + * | | |Note: It is used to detect the LDO_CAP. Write 1 to clear this bit. + * |[25] |ACTST1IF |Active Shield Tamper 1 Event Interrupt Flag + * | | |0 = No Active shield Tamper 1 event interrupt flag is generated. + * | | |1 = Active shield Tamper 1 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[27] |ACTST3IF |Active Shield Tamper 3 Event Interrupt Flag + * | | |0 = No Active shield Tamper 3 event interrupt flag is generated. + * | | |1 = Active shield Tamper 3 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[29] |ACTST21IF |2th Active Shield Tamper 1 Event Interrupt Flag + * | | |0 = No Active shield Tamper 1 event interrupt flag is generated. + * | | |1 = 2th Active shield Tamper 1 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * |[31] |ACTST23IF |2th Active Shield Tamper 3 Event Interrupt Flag + * | | |0 = No Active shield Tamper 3 event interrupt flag is generated. + * | | |1 = 2th Active shield Tamper 3 event interrupt flag is generated. + * | | |Note: Write 1 to clear this bit. + * @var TAMPER_T::LIRCTL + * Offset: 0x14 Tamper LIRC Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |TLRCTRIM |Tamper TLIRC32K Trim Value + * | | |TLIRC32K trim value setting + * |[10:9] |TRIMMOS |Tamper TLIRC32K Trim MOS Value + * | | |TLIRC32K trim MOS value setting + * @var TAMPER_T::TIOCTL + * Offset: 0x18 Tamper I/O Function Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |DYN1ISS |Dynamic Pair 1 Input Source Select + * | | |This bit determines Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 2. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit is effective only when DYNPR1EN (TAMPER_TIOCTL[23]) and DYNPR0EN (TAMPER_TIOCTL[15]) are set. + * |[1] |DYN2ISS |Dynamic Pair 2 Input Source Select + * | | |This bit determines Tamper 5 input is from Tamper 4 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 4. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit has effect only when DYNPR2EN (TAMPER_TIOCTL[31]) and DYNPR0EN (TAMPER_TIOCTL[15]) are set. + * |[3] |DYNSRC |Dynamic Reference Pattern + * | | |This field determines the new reference pattern when current pattern run out in dynamic pair mode. + * | | |0 = The new reference pattern is generated by random number generator when the reference pattern run out. + * | | |1 = The new reference pattern is repeated from SEED (TAMPER_SEED[31:0]) when the reference pattern run out. + * | | |Note: After this bit is modified, the SEEDRLD (TAMPER_TIOCTL[4]) should be set. + * |[4] |SEEDRLD |Reload New Seed for PRNG Engine + * | | |Setting this bit, the tamper configuration will be reloaded. + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * | | |Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. + * | | |Note 2: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. + * |[7:5] |DYNRATE |Dynamic Change Rate + * | | |This item is choice the dynamic tamper output change rate. + * | | |000 = 26 * RTC_CLK. + * | | |001 = 27 * RTC_CLK. + * | | |010 = 28 * RTC_CLK. + * | | |011 = 29 * RTC_CLK. + * | | |100 = 210 * RTC_CLK. + * | | |101 = 211 * RTC_CLK. + * | | |110 = 212 * RTC_CLK. + * | | |111 = 213 * RTC_CLK. + * | | |Note: After revising this field, setting SEEDRLD (TAMPER_TIOCTL[4]) can reload change rate immediately. + * |[8] |TAMP0EN |Tamper0 Detect Enable Bit + * | | |0 = Tamper 0 detect Disabled. + * | | |1 = Tamper 0 detect Enabled. + * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. + * |[9] |TAMP0LV |Tamper 0 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[10] |TAMP0DBEN |Tamper 0 De-bounce Enable Bit + * | | |0 = Tamper 0 de-bounce Disabled. + * | | |1 = Tamper 0 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. + * |[12] |TAMP1EN |Tamper 1 Detect Enable Bit + * | | |0 = Tamper 1 detect Disabled. + * | | |1 = Tamper 1 detect Enabled. + * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. + * |[13] |TAMP1LV |Tamper 1 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[14] |TAMP1DBEN |Tamper 1 De-bounce Enable Bit + * | | |0 = Tamper 1 de-bounce Disabled. + * | | |1 = Tamper 1 de-bounce Enabled, tamper detection pin will sync 1 RTC clock. + * |[15] |DYNPR0EN |Dynamic Pair 0 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[16] |TAMP2EN |Tamper 2 Detect Enable Bit + * | | |0 = Tamper 2 detect Disabled. + * | | |1 = Tamper 2 detect Enabled. + * | | |Note: The reference is RTC-clock. Tamper detector need sync 2 ~ 3 RTC-clock. + * |[17] |TAMP2LV |Tamper 2 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[18] |TAMP2DBEN |Tamper 2 De-bounce Enable Bit + * | | |0 = Tamper 2 de-bounce Disabled. + * | | |1 = Tamper 2 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. + * |[20] |TAMP3EN |Tamper 3 Detect Enable Bit + * | | |0 = Tamper 3 detect Disabled. + * | | |1 = Tamper 3 detect Enabled. + * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. + * |[21] |TAMP3LV |Tamper 3 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[22] |TAMP3DBEN |Tamper 3 De-bounce Enable Bit + * | | |0 = Tamper 3 de-bounce Disabled. + * | | |1 = Tamper 3 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. + * |[23] |DYNPR1EN |Dynamic Pair 1 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * |[24] |TAMP4EN |Tamper4 Detect Enable Bit + * | | |0 = Tamper 4 detect Disabled. + * | | |1 = Tamper 4 detect Enabled. + * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. + * |[25] |TAMP4LV |Tamper 4 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[26] |TAMP4DBEN |Tamper 4 De-bounce Enable Bit + * | | |0 = Tamper 4 de-bounce Disabled. + * | | |1 = Tamper 4 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. + * |[28] |TAMP5EN |Tamper 5 Detect Enable Bit + * | | |0 = Tamper 5 detect Disabled. + * | | |1 = Tamper 5 detect Enabled. + * | | |Note: The reference is RTC-clock. Tamper detector needs sync 2 ~ 3 RTC-clock. + * |[29] |TAMP5LV |Tamper 5 Level + * | | |This bit depends on level attribute of tamper pin for static tamper detection. + * | | |0 = Detect voltage level is low. + * | | |1 = Detect voltage level is high. + * |[30] |TAMP5DBEN |Tamper 5 De-bounce Enable Bit + * | | |0 = Tamper 5 de-bounce Disabled. + * | | |1 = Tamper 5 de-bounce Enabled. Tamper detection pin will sync 1 RTC clock. + * |[31] |DYNPR2EN |Dynamic Pair 2 Enable Bit + * | | |0 = Static detect. + * | | |1 = Dynamic detect. + * @var TAMPER_T::SEED + * Offset: 0x1C Tamper Seed Value Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED |Seed value. + * @var TAMPER_T::SEED2 + * Offset: 0x20 Tamper 2nd Seed Value Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |SEED2 |Seed value. These seed value are used for 2nd active shield I/O. + * @var TAMPER_T::ACTSTIOCTL1 + * Offset: 0x24 Tamper Active Shield Tamper I/O Function Control Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADYN1ISS |Active Shied Dynamic Pair 1 Input Source Select + * | | |This bit determines Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 2. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit is effective only when ADYNPR1EN (TAMPER_ACTSTIOCTL1[23]) and ADYNPR0EN (TAMPER_ACTSTIOCTL1[15]) are set. + * |[3] |ADYNSRC |Active Shied Dynamic Reference Pattern + * | | |This field determines the new reference pattern when current pattern run out in dynamic pair mode. + * | | |0 = The new reference pattern is generated by random number generator when the reference pattern run out. + * | | |1 = The new reference pattern is repeated from SEED (TAMPER_SEED[31:0]) when the reference pattern run out. + * | | |Note: After this bit is modified, the SEEDRLD (TAMPER_TIOCTL[4]) should be set. + * |[7:5] |ADYNRATE |Active Shied Dynamic Change Rate + * | | |Use the bits to choose the dynamic tamper output change rate. + * | | |000 = 210 * TLIRC32K. + * | | |001 = 211 * TLIRC32K. + * | | |010 = 212 * TLIRC32K. + * | | |011 = 213 * TLIRC32K. + * | | |100 = 214 * TLIRC32K. + * | | |101 = 215 * TLIRC32K. + * | | |110 = 216 * TLIRC32K. + * | | |111 = 217 * TLIRC32K. + * | | |Note: After this field is modified, setting SEEDRLD (TAMPER_TIOCTL[4]) can reload the change rate immediately. + * |[8] |ATAMP0EN |Active Shied Tamper0 Detect Enable Bit + * | | |0 = Tamper 0 detect Disabled. + * | | |1 = Tamper 0 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. + * |[12] |ATAMP1EN |Active Shied Tamper 1 Detect Enable Bit + * | | |0 = Tamper 1 detect Disabled. + * | | |1 = Tamper 1 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[15] |ADYNPR0EN |Active Shied Dynamic Pair 0 Enable Bit + * | | |0 = Static detect (Not supported). + * | | |1 = Dynamic detect. + * |[16] |ATAMP2EN |Active Shied Tamper 2 Detect Enable Bit + * | | |0 = Tamper 2 detect Disabled. + * | | |1 = Tamper 2 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[20] |ATAMP3EN |Active Shied Tamper 3 Detect Enable Bit + * | | |0 = Tamper 3 detect Disabled. + * | | |1 = Tamper 3 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[23] |ADYNPR1EN |Active Shied Dynamic Pair 1 Enable Bit + * | | |0 = Static detect (Not supported). + * | | |1 = Dynamic detect. + * |[24] |ATAMP4EN |Active Tamper4 Detect Enable Bit + * | | |0 = Tamper 4 detect Disabled. + * | | |1 = Tamper 4 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. + * |[28] |ATAMP5EN |Active Tamper 5 Detect Enable Bit + * | | |0 = Tamper 5 detect Disabled. + * | | |1 = Tamper 5 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. + * |[31] |ADYNPR2EN |Active Shied Dynamic Pair 2 Enable Bit + * | | |0 = Static detect (Not supported). + * | | |1 = Dynamic detect. + * @var TAMPER_T::ACTSTIOCTL2 + * Offset: 0x28 Tamper Active Shield Tamper I/O Function Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADYN1ISS2 |Active Shied Dynamic Pair 1 Input Source Select 2 + * | | |This bit determines if Tamper 3 input is from Tamper 2 or Tamper 0 in dynamic mode. + * | | |0 = Tamper input is from Tamper 2. + * | | |1 = Tamper input is from Tamper 0. + * | | |Note: This bit is effective only when ADYNPR1EN2 (TAMPER_ACTSTIOCTL2[23]) and ADYNPR0EN2 (TAMPER_ACTSTIOCTL2[15]) are set. + * |[3] |ADYNSRC2 |Active Shied Dynamic Reference Pattern 2 + * | | |This field determines the new reference pattern when current pattern run out in dynamic pair mode. + * | | |0 = The new reference pattern is generated by random number generator when the reference pattern run out. + * | | |1 = The new reference pattern is repeated from SEED2 (TAMPER_SEED2[31:0]) when the reference pattern run out. + * | | |Note: After this bit is modified, the SEEDRLD2 (TAMPER_ACTSTIOCTL2[4]) should be set. + * |[4] |SEEDRLD2 |Reload New Seed for PRNG Engine 2 + * | | |Setting this bit, the tamper configuration will be reloaded. + * | | |0 = Generating key based on the current seed. + * | | |1 = Reload new seed. + * | | |Note 1: Before this bit is set, the tamper configuration should be set to complete and this bit will be auto clear to 0 after reload new seed completed. + * | | |Note 2: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[7:5] |ADYNRATE2 |Active Shied Dynamic Change Rate 2 + * | | |Use the bits to choose the dynamic tamper output change rate. + * | | |000 = 210 * TLIRC32K. + * | | |001 = 211 * TLIRC32K. + * | | |010 = 212 * TLIRC32K. + * | | |011 = 213 * TLIRC32K. + * | | |100 = 214 * TLIRC32K. + * | | |101 = 215 * TLIRC32K. + * | | |110 = 216 * TLIRC32K. + * | | |111 = 217 * TLIRC32K. + * | | |Note: After this field is modified, setting SEEDRLD2 (TAMPER_ACTSTIOCTL2[4]) can reload change rate immediately. + * |[8] |ATAMP0EN2 |Active Shied Tamper0 Detect Enable Bit 2 + * | | |0 = Tamper 0 detect Disabled. + * | | |1 = Tamper 0 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[12] |ATAMP1EN2 |Active Shied Tamper 1 Detect Enable Bit 2 + * | | |0 = Tamper 1 detect Disabled. + * | | |1 = Tamper 1 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[15] |ADYNPR0EN2|Active Shied Dynamic Pair 0 Enable Bit 2 + * | | |0 = Static detect (Not supported). + * | | |1 = Dynamic detect. + * |[16] |ATAMP2EN2 |Active Shied Tamper 2 Detect Enable Bit 2 + * | | |0 = Tamper 2 detect Disabled. + * | | |1 = Tamper 2 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[20] |ATAMP3EN2 |Active Shied Tamper 3 Detect Enable Bit 2 + * | | |0 = Tamper 3 detect Disabled. + * | | |1 = Tamper 3 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector needs sync 2 ~ 3 TLIRC 32K-clock. + * |[23] |ADYNPR1EN2|Active Shied Dynamic Pair 1 Enable Bit 2 + * | | |0 = Static detect (Not supported). + * | | |1 = Dynamic detect. + * |[24] |ATAMP4EN2 |Active Shied Tamper4 Detect Enable Bit 2 + * | | |0 = Tamper 4 detect Disabled. + * | | |1 = Tamper 4 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. + * |[28] |ATAMP5EN2 |Active Tamper 5 Detect Enable Bit 2 + * | | |0 = Tamper 5 detect Disabled. + * | | |1 = Tamper 5 detect Enabled. + * | | |Note: The reference is TLIRC 32K-clock. Tamper detector need sync 2 ~ 3 TLIRC 32K-clock. + * |[31] |ADYNPR2EN2|Active Shied Dynamic Pair 2 Enable Bit 2 + * | | |0 = Static detect (Not supported). + * | | |1 = Dynamic detect. + * @var TAMPER_T::CDBR + * Offset: 0x2C Tamper Clock Frequency Detector Boundary Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |STOPBD |LXT Clock Frequency Detector Stop Boundary + * | | |The bits define the stop value of frequency monitor window. + * | | |When LXT frequency monitor counter lower than Clock Frequency Detector Stop Boundary, the LXT frequency detect stop interrupt flag will set to 1. + * | | |Note: The boundary is defined as the maximum value of LXT among 256 Tamper clock time. + * |[23:16] |FAILBD |LXT Clock Frequency Detector Fail Boundary + * | | |The bits define the fail value of frequency monitor window. + * | | |When LXT frequency monitor counter lower than Clock Frequency Detector Fail Boundary, the LXT frequency detect fail interrupt flag will set to 1. + * | | |Note: The boundary is defined as the minimum value of LXT among 256 Tamper clock time. + * @var TAMPER_T::VG + * Offset: 0x30 Tamper Voltage Glitch Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PCLKSEL0 |PL0 Positive Clock Trim Range + * | | |The setting value of the positive clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * | | |Note: PL0 means the power level is 1.26V + * | | |The power level is controlled in system manager + * |[7:4] |NCLKSEL0 |PL0 Negative Clock Trim Range + * | | |The setting value of the negative clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[11:8] |PDATSEL0 |PL0 Positive Data Trim Range + * | | |The setting value of the positive data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[15:12] |NDATSEL0 |PL0 Negative Data Trim Range + * | | |The setting value of the negative data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[19:16] |PCLKSEL1 |PL1 Positive Clock Trim Range + * | | |The setting value of the positive clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * | | |Note: PL1 means the power level is 1.2V + * |[23:20] |NCLKSEL1 |PL1 Negative Clock Trim Range + * | | |The setting value of the negative clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[27:24] |PDATSEL1 |PL1 Positive Data Trim Range + * | | |The setting value of the positive data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[31:28] |NDATSEL1 |PL1 Negative Data Trim Range + * | | |The setting value of the negative data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * @var TAMPER_T::VGEV + * Offset: 0x34 Tamper Voltage Glitch Event Tolerance Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |VGECNTP |Positive Voltage Glitch Error Tolerance + * | | |The value indicates the tolerance count for positive voltage glitch event. + * |[15:8] |VGECNTN |Negative Voltage Glitch Error Tolerance + * | | |The value indicates the tolerance count for negative voltage glitch event. + * @var TAMPER_T::LDOTRIM + * Offset: 0x38 Tamper LDO Trim Value Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |TLDOTRIM |Voltage Regulator Output Voltage Trim + * | | |The value indicates the trim value of the voltage regulator output voltage. + * |[9:8] |TLDOIQSEL |Voltage Regulator Qu Current Selection + * | | |Indicates the Qu current selection of voltage regulator. + * @var TAMPER_T::LBSTRIM + * Offset: 0x3C Tamper LDO BIAS Trim Value Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TLVDSEL |Under-shoot Detect Level Trim Bits + * | | |The value indicates the trim value of the under-shoot detection level + * |[4] |TOVDSEL |Over-shoot Detect Level Trim Bits + * | | |The value indicates the trim value of the over-shoot detection level + * |[9:8] |BSCMPLV |Under-shoot Detect Comparator Current Trim Bits + * | | |The value indicates the trim value of the under-shoot detection comparator current trim level + * |[11:10] |BSCMPOV |Over-shoot Detect Comparator Current Trim Bits + * | | |The value indicates the trim value of the over-shoot detection comparator current trim level + * |[13:12] |HYSCMPLV |Under-shoot Detect Comparator Hysteresis Trim Bits + * | | |The value indicates the trim value of the under-shoot detection comparator of hysteresis trim level + * |[15:14] |HYSCMPOV |Over-shoot Detect Comparator Hysteresis Trim Bits + * | | |The value indicates the trim value of the over-shoot detection comparator of hysteresis trim level + * @var TAMPER_T::VG2 + * Offset: 0x40 Tamper Voltage Glitch Control Register 2 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |PCLKSEL2 |PL2 Positive Clock Trim Range + * | | |The setting value of the positive clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * | | |Note: PL2 means the power level is 1.1V + * | | |The power level is controlled in system manager. + * |[7:4] |NCLKSEL2 |PL2 Negative Clock Trim Range + * | | |The setting value of the negative clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[11:8] |PDATSEL2 |PL2 Positive Data Trim Range + * | | |The setting value of the positive data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[15:12] |NDATSEL2 |PL2 Negative Data Trim Range + * | | |The setting value of the negative data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[19:16] |PCLKSEL3 |PL3 Positive Clock Trim Range + * | | |The setting value of the positive clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * | | |Note: PL3 means the power level is 0.9V + * |[23:20] |NCLKSEL3 |PL3 Negative Clock Trim Range + * | | |The setting value of the negative clock tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[27:24] |PDATSEL3 |PL3 Positive Data Trim Range + * | | |The setting value of the positive data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + * |[31:28] |NDATSEL3 |PL3 Negative Data Trim Range + * | | |The setting value of the negative data tolerance. + * | | |One step is about 2.5% tolerance. The maximum tolerance is 20%. + */ + __IO uint32_t INIT; /*!< [0x0000] Tamper Function Initiation Register */ + __IO uint32_t FUNEN; /*!< [0x0004] Tamper Block Function Enable Register */ + __IO uint32_t TRIEN; /*!< [0x0008] Tamper Trigger Enable Register */ + __IO uint32_t INTEN; /*!< [0x000c] Tamper Event Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0010] Tamper Interrupt Status Register */ + __IO uint32_t LIRCTL; /*!< [0x0014] Tamper LIRC Control Register */ + __IO uint32_t TIOCTL; /*!< [0x0018] Tamper I/O Function Control Register */ + __IO uint32_t SEED; /*!< [0x001c] Tamper Seed Value Control Register */ + __IO uint32_t SEED2; /*!< [0x0020] Tamper 2nd Seed Value Control Register */ + __IO uint32_t ACTSTIOCTL1; /*!< [0x0024] Tamper Active Shield Tamper I/O Function Control Register 1 */ + __IO uint32_t ACTSTIOCTL2; /*!< [0x0028] Tamper Active Shield Tamper I/O Function Control Register 2 */ + __IO uint32_t CDBR; /*!< [0x002c] Tamper Clock Frequency Detector Boundary Register */ + __IO uint32_t VG; /*!< [0x0030] Tamper Voltage Glitch Control Register */ + __IO uint32_t VGEV; /*!< [0x0034] Tamper Voltage Glitch Event Tolerance Control Register */ + __IO uint32_t LDOTRIM; /*!< [0x0038] Tamper LDO Trim Value Control Register */ + __IO uint32_t LBSTRIM; /*!< [0x003c] Tamper LDO BIAS Trim Value Control Register */ + __IO uint32_t VG2; /*!< [0x0040] Tamper Voltage Glitch Control Register 2 */ + +} TAMPER_T; + +/** + @addtogroup TAMPER_CONST Tamper Bit Field Definition + Constant Definitions for Tamper Controller + @{ +*/ + +#define TAMPER_INIT_TCORERST_Pos (0) /*!< TAMPER_T::INIT: TCORERST Position */ +#define TAMPER_INIT_TCORERST_Msk (0x1ul << TAMPER_INIT_TCORERST_Pos) /*!< TAMPER_T::INIT: TCORERST Mask */ + +#define TAMPER_INIT_TLDORDY_Pos (31) /*!< TAMPER_T::INIT: TLDORDY Position */ +#define TAMPER_INIT_TLDORDY_Msk (0x1ul << TAMPER_INIT_TLDORDY_Pos) /*!< TAMPER_T::INIT: TLDORDY Mask */ + +#define TAMPER_FUNEN_LXTDETEN_Pos (0) /*!< TAMPER_T::FUNEN: LXTDETEN Position */ +#define TAMPER_FUNEN_LXTDETEN_Msk (0x1ul << TAMPER_FUNEN_LXTDETEN_Pos) /*!< TAMPER_T::FUNEN: LXTDETEN Mask */ + +#define TAMPER_FUNEN_TMPIOSEL_Pos (8) /*!< TAMPER_T::FUNEN: TMPIOSEL Position */ +#define TAMPER_FUNEN_TMPIOSEL_Msk (0x3ful << TAMPER_FUNEN_TMPIOSEL_Pos) /*!< TAMPER_T::FUNEN: TMPIOSEL Mask */ + +#define TAMPER_FUNEN_HIRC48MEN_Pos (16) /*!< TAMPER_T::FUNEN: HIRC48MEN Position */ +#define TAMPER_FUNEN_HIRC48MEN_Msk (0xfful << TAMPER_FUNEN_HIRC48MEN_Pos) /*!< TAMPER_T::FUNEN: HIRC48MEN Mask */ + +#define TAMPER_FUNEN_VGCHEN0_Pos (24) /*!< TAMPER_T::FUNEN: VGCHEN0 Position */ +#define TAMPER_FUNEN_VGCHEN0_Msk (0x1ul << TAMPER_FUNEN_VGCHEN0_Pos) /*!< TAMPER_T::FUNEN: VGCHEN0 Mask */ + +#define TAMPER_FUNEN_VGCHEN1_Pos (25) /*!< TAMPER_T::FUNEN: VGCHEN1 Position */ +#define TAMPER_FUNEN_VGCHEN1_Msk (0x1ul << TAMPER_FUNEN_VGCHEN1_Pos) /*!< TAMPER_T::FUNEN: VGCHEN1 Mask */ + +#define TAMPER_FUNEN_VGCHEN2_Pos (26) /*!< TAMPER_T::FUNEN: VGCHEN2 Position */ +#define TAMPER_FUNEN_VGCHEN2_Msk (0x1ul << TAMPER_FUNEN_VGCHEN2_Pos) /*!< TAMPER_T::FUNEN: VGCHEN2 Mask */ + +#define TAMPER_FUNEN_VGCHEN3_Pos (27) /*!< TAMPER_T::FUNEN: VGCHEN3 Position */ +#define TAMPER_FUNEN_VGCHEN3_Msk (0x1ul << TAMPER_FUNEN_VGCHEN3_Pos) /*!< TAMPER_T::FUNEN: VGCHEN3 Mask */ + +#define TAMPER_TRIEN_KSTRIGEN_Pos (1) /*!< TAMPER_T::TRIEN: KSTRIGEN Position */ +#define TAMPER_TRIEN_KSTRIGEN_Msk (0x1ul << TAMPER_TRIEN_KSTRIGEN_Pos) /*!< TAMPER_T::TRIEN: KSTRIGEN Mask */ + +#define TAMPER_TRIEN_WAKEUPEN_Pos (2) /*!< TAMPER_T::TRIEN: WAKEUPEN Position */ +#define TAMPER_TRIEN_WAKEUPEN_Msk (0x1ul << TAMPER_TRIEN_WAKEUPEN_Pos) /*!< TAMPER_T::TRIEN: WAKEUPEN Mask */ + +#define TAMPER_TRIEN_CRYPTOEN_Pos (3) /*!< TAMPER_T::TRIEN: CRYPTOEN Position */ +#define TAMPER_TRIEN_CRYPTOEN_Msk (0x1ul << TAMPER_TRIEN_CRYPTOEN_Pos) /*!< TAMPER_T::TRIEN: CRYPTOEN Mask */ + +#define TAMPER_TRIEN_CHIPRSTEN_Pos (4) /*!< TAMPER_T::TRIEN: CHIPRSTEN Position */ +#define TAMPER_TRIEN_CHIPRSTEN_Msk (0x1ul << TAMPER_TRIEN_CHIPRSTEN_Pos) /*!< TAMPER_T::TRIEN: CHIPRSTEN Mask */ + +#define TAMPER_TRIEN_RTCSPCLREN_Pos (5) /*!< TAMPER_T::TRIEN: RTCSPCLREN Position */ +#define TAMPER_TRIEN_RTCSPCLREN_Msk (0x1ul << TAMPER_TRIEN_RTCSPCLREN_Pos) /*!< TAMPER_T::TRIEN: RTCSPCLREN Mask */ + +#define TAMPER_INTEN_TAMP0IEN_Pos (0) /*!< TAMPER_T::INTEN: TAMP0IEN Position */ +#define TAMPER_INTEN_TAMP0IEN_Msk (0x1ul << TAMPER_INTEN_TAMP0IEN_Pos) /*!< TAMPER_T::INTEN: TAMP0IEN Mask */ + +#define TAMPER_INTEN_TAMP1IEN_Pos (1) /*!< TAMPER_T::INTEN: TAMP1IEN Position */ +#define TAMPER_INTEN_TAMP1IEN_Msk (0x1ul << TAMPER_INTEN_TAMP1IEN_Pos) /*!< TAMPER_T::INTEN: TAMP1IEN Mask */ + +#define TAMPER_INTEN_TAMP2IEN_Pos (2) /*!< TAMPER_T::INTEN: TAMP2IEN Position */ +#define TAMPER_INTEN_TAMP2IEN_Msk (0x1ul << TAMPER_INTEN_TAMP2IEN_Pos) /*!< TAMPER_T::INTEN: TAMP2IEN Mask */ + +#define TAMPER_INTEN_TAMP3IEN_Pos (3) /*!< TAMPER_T::INTEN: TAMP3IEN Position */ +#define TAMPER_INTEN_TAMP3IEN_Msk (0x1ul << TAMPER_INTEN_TAMP3IEN_Pos) /*!< TAMPER_T::INTEN: TAMP3IEN Mask */ + +#define TAMPER_INTEN_TAMP4IEN_Pos (4) /*!< TAMPER_T::INTEN: TAMP4IEN Position */ +#define TAMPER_INTEN_TAMP4IEN_Msk (0x1ul << TAMPER_INTEN_TAMP4IEN_Pos) /*!< TAMPER_T::INTEN: TAMP4IEN Mask */ + +#define TAMPER_INTEN_TAMP5IEN_Pos (5) /*!< TAMPER_T::INTEN: TAMP5IEN Position */ +#define TAMPER_INTEN_TAMP5IEN_Msk (0x1ul << TAMPER_INTEN_TAMP5IEN_Pos) /*!< TAMPER_T::INTEN: TAMP5IEN Mask */ + +#define TAMPER_INTEN_CLKFIEN_Pos (6) /*!< TAMPER_T::INTEN: CLKFIEN Position */ +#define TAMPER_INTEN_CLKFIEN_Msk (0x1ul << TAMPER_INTEN_CLKFIEN_Pos) /*!< TAMPER_T::INTEN: CLKFIEN Mask */ + +#define TAMPER_INTEN_CLKSTOPIEN_Pos (7) /*!< TAMPER_T::INTEN: CLKSTOPIEN Position */ +#define TAMPER_INTEN_CLKSTOPIEN_Msk (0x1ul << TAMPER_INTEN_CLKSTOPIEN_Pos) /*!< TAMPER_T::INTEN: CLKSTOPIEN Mask */ + +#define TAMPER_INTEN_OVPIEN_Pos (8) /*!< TAMPER_T::INTEN: OVPIEN Position */ +#define TAMPER_INTEN_OVPIEN_Msk (0x1ul << TAMPER_INTEN_OVPIEN_Pos) /*!< TAMPER_T::INTEN: OVPIEN Mask */ + +#define TAMPER_INTEN_VGPIEN_Pos (9) /*!< TAMPER_T::INTEN: VGPIEN Position */ +#define TAMPER_INTEN_VGPIEN_Msk (0x1ul << TAMPER_INTEN_VGPIEN_Pos) /*!< TAMPER_T::INTEN: VGPIEN Mask */ + +#define TAMPER_INTEN_VGNIEN_Pos (10) /*!< TAMPER_T::INTEN: VGNIEN Position */ +#define TAMPER_INTEN_VGNIEN_Msk (0x1ul << TAMPER_INTEN_VGNIEN_Pos) /*!< TAMPER_T::INTEN: VGNIEN Mask */ + +#define TAMPER_INTEN_ACTSIEN_Pos (11) /*!< TAMPER_T::INTEN: ACTSIEN Position */ +#define TAMPER_INTEN_ACTSIEN_Msk (0x1ul << TAMPER_INTEN_ACTSIEN_Pos) /*!< TAMPER_T::INTEN: ACTSIEN Mask */ + +#define TAMPER_INTEN_RTCLVRIEN_Pos (16) /*!< TAMPER_T::INTEN: RTCLVRIEN Position */ +#define TAMPER_INTEN_RTCLVRIEN_Msk (0x1ul << TAMPER_INTEN_RTCLVRIEN_Pos) /*!< TAMPER_T::INTEN: RTCLVRIEN Mask */ + +#define TAMPER_INTEN_RTCIOIEN_Pos (17) /*!< TAMPER_T::INTEN: RTCIOIEN Position */ +#define TAMPER_INTEN_RTCIOIEN_Msk (0x1ul << TAMPER_INTEN_RTCIOIEN_Pos) /*!< TAMPER_T::INTEN: RTCIOIEN Mask */ + +#define TAMPER_INTEN_RTCLKIEN_Pos (18) /*!< TAMPER_T::INTEN: RTCLKIEN Position */ +#define TAMPER_INTEN_RTCLKIEN_Msk (0x1ul << TAMPER_INTEN_RTCLKIEN_Pos) /*!< TAMPER_T::INTEN: RTCLKIEN Mask */ + +#define TAMPER_INTEN_BODIEN_Pos (22) /*!< TAMPER_T::INTEN: BODIEN Position */ +#define TAMPER_INTEN_BODIEN_Msk (0x1ul << TAMPER_INTEN_BODIEN_Pos) /*!< TAMPER_T::INTEN: BODIEN Mask */ + +#define TAMPER_INTSTS_TAMP0IF_Pos (0) /*!< TAMPER_T::INTSTS: TAMP0IF Position */ +#define TAMPER_INTSTS_TAMP0IF_Msk (0x1ul << TAMPER_INTSTS_TAMP0IF_Pos) /*!< TAMPER_T::INTSTS: TAMP0IF Mask */ + +#define TAMPER_INTSTS_TAMP1IF_Pos (1) /*!< TAMPER_T::INTSTS: TAMP1IF Position */ +#define TAMPER_INTSTS_TAMP1IF_Msk (0x1ul << TAMPER_INTSTS_TAMP1IF_Pos) /*!< TAMPER_T::INTSTS: TAMP1IF Mask */ + +#define TAMPER_INTSTS_TAMP2IF_Pos (2) /*!< TAMPER_T::INTSTS: TAMP2IF Position */ +#define TAMPER_INTSTS_TAMP2IF_Msk (0x1ul << TAMPER_INTSTS_TAMP2IF_Pos) /*!< TAMPER_T::INTSTS: TAMP2IF Mask */ + +#define TAMPER_INTSTS_TAMP3IF_Pos (3) /*!< TAMPER_T::INTSTS: TAMP3IF Position */ +#define TAMPER_INTSTS_TAMP3IF_Msk (0x1ul << TAMPER_INTSTS_TAMP3IF_Pos) /*!< TAMPER_T::INTSTS: TAMP3IF Mask */ + +#define TAMPER_INTSTS_TAMP4IF_Pos (4) /*!< TAMPER_T::INTSTS: TAMP4IF Position */ +#define TAMPER_INTSTS_TAMP4IF_Msk (0x1ul << TAMPER_INTSTS_TAMP4IF_Pos) /*!< TAMPER_T::INTSTS: TAMP4IF Mask */ + +#define TAMPER_INTSTS_TAMP5IF_Pos (5) /*!< TAMPER_T::INTSTS: TAMP5IF Position */ +#define TAMPER_INTSTS_TAMP5IF_Msk (0x1ul << TAMPER_INTSTS_TAMP5IF_Pos) /*!< TAMPER_T::INTSTS: TAMP5IF Mask */ + +#define TAMPER_INTSTS_CLKFAILIF_Pos (6) /*!< TAMPER_T::INTSTS: CLKFAILIF Position */ +#define TAMPER_INTSTS_CLKFAILIF_Msk (0x1ul << TAMPER_INTSTS_CLKFAILIF_Pos) /*!< TAMPER_T::INTSTS: CLKFAILIF Mask */ + +#define TAMPER_INTSTS_CLKSTOPIF_Pos (7) /*!< TAMPER_T::INTSTS: CLKSTOPIF Position */ +#define TAMPER_INTSTS_CLKSTOPIF_Msk (0x1ul << TAMPER_INTSTS_CLKSTOPIF_Pos) /*!< TAMPER_T::INTSTS: CLKSTOPIF Mask */ + +#define TAMPER_INTSTS_OVPOUTIF_Pos (8) /*!< TAMPER_T::INTSTS: OVPOUTIF Position */ +#define TAMPER_INTSTS_OVPOUTIF_Msk (0x1ul << TAMPER_INTSTS_OVPOUTIF_Pos) /*!< TAMPER_T::INTSTS: OVPOUTIF Mask */ + +#define TAMPER_INTSTS_VGPEVIF_Pos (9) /*!< TAMPER_T::INTSTS: VGPEVIF Position */ +#define TAMPER_INTSTS_VGPEVIF_Msk (0x1ul << TAMPER_INTSTS_VGPEVIF_Pos) /*!< TAMPER_T::INTSTS: VGPEVIF Mask */ + +#define TAMPER_INTSTS_VGNEVIF_Pos (10) /*!< TAMPER_T::INTSTS: VGNEVIF Position */ +#define TAMPER_INTSTS_VGNEVIF_Msk (0x1ul << TAMPER_INTSTS_VGNEVIF_Pos) /*!< TAMPER_T::INTSTS: VGNEVIF Mask */ + +#define TAMPER_INTSTS_ACTSEIF_Pos (11) /*!< TAMPER_T::INTSTS: ACTSEIF Position */ +#define TAMPER_INTSTS_ACTSEIF_Msk (0x1ul << TAMPER_INTSTS_ACTSEIF_Pos) /*!< TAMPER_T::INTSTS: ACTSEIF Mask */ + +#define TAMPER_INTSTS_ACTST5IF_Pos (13) /*!< TAMPER_T::INTSTS: ACTST5IF Position */ +#define TAMPER_INTSTS_ACTST5IF_Msk (0x1ul << TAMPER_INTSTS_ACTST5IF_Pos) /*!< TAMPER_T::INTSTS: ACTST5IF Mask */ + +#define TAMPER_INTSTS_ACTST25IF_Pos (15) /*!< TAMPER_T::INTSTS: ACTST25IF Position */ +#define TAMPER_INTSTS_ACTST25IF_Msk (0x1ul << TAMPER_INTSTS_ACTST25IF_Pos) /*!< TAMPER_T::INTSTS: ACTST25IF Mask */ + +#define TAMPER_INTSTS_RTCLVRIF_Pos (16) /*!< TAMPER_T::INTSTS: RTCLVRIF Position */ +#define TAMPER_INTSTS_RTCLVRIF_Msk (0x1ul << TAMPER_INTSTS_RTCLVRIF_Pos) /*!< TAMPER_T::INTSTS: RTCLVRIF Mask */ + +#define TAMPER_INTSTS_RIOTRIGIF_Pos (17) /*!< TAMPER_T::INTSTS: RIOTRIGIF Position */ +#define TAMPER_INTSTS_RIOTRIGIF_Msk (0x1ul << TAMPER_INTSTS_RIOTRIGIF_Pos) /*!< TAMPER_T::INTSTS: RIOTRIGIF Mask */ + +#define TAMPER_INTSTS_RCLKTRIGIF_Pos (18) /*!< TAMPER_T::INTSTS: RCLKTRIGIF Position */ +#define TAMPER_INTSTS_RCLKTRIGIF_Msk (0x1ul << TAMPER_INTSTS_RCLKTRIGIF_Pos) /*!< TAMPER_T::INTSTS: RCLKTRIGIF Mask */ + +#define TAMPER_INTSTS_BODIF_Pos (22) /*!< TAMPER_T::INTSTS: BODIF Position */ +#define TAMPER_INTSTS_BODIF_Msk (0x1ul << TAMPER_INTSTS_BODIF_Pos) /*!< TAMPER_T::INTSTS: BODIF Mask */ + +#define TAMPER_INTSTS_ACTST1IF_Pos (25) /*!< TAMPER_T::INTSTS: ACTST1IF Position */ +#define TAMPER_INTSTS_ACTST1IF_Msk (0x1ul << TAMPER_INTSTS_ACTST1IF_Pos) /*!< TAMPER_T::INTSTS: ACTST1IF Mask */ + +#define TAMPER_INTSTS_ACTST3IF_Pos (27) /*!< TAMPER_T::INTSTS: ACTST3IF Position */ +#define TAMPER_INTSTS_ACTST3IF_Msk (0x1ul << TAMPER_INTSTS_ACTST3IF_Pos) /*!< TAMPER_T::INTSTS: ACTST3IF Mask */ + +#define TAMPER_INTSTS_ACTST21IF_Pos (29) /*!< TAMPER_T::INTSTS: ACTST21IF Position */ +#define TAMPER_INTSTS_ACTST21IF_Msk (0x1ul << TAMPER_INTSTS_ACTST21IF_Pos) /*!< TAMPER_T::INTSTS: ACTST21IF Mask */ + +#define TAMPER_INTSTS_ACTST23IF_Pos (31) /*!< TAMPER_T::INTSTS: ACTST23IF Position */ +#define TAMPER_INTSTS_ACTST23IF_Msk (0x1ul << TAMPER_INTSTS_ACTST23IF_Pos) /*!< TAMPER_T::INTSTS: ACTST23IF Mask */ + +#define TAMPER_LIRCTL_TLRCTRIM_Pos (0) /*!< TAMPER_T::LIRCTL: TLRCTRIM Position */ +#define TAMPER_LIRCTL_TLRCTRIM_Msk (0x1fful << TAMPER_LIRCTL_TLRCTRIM_Pos) /*!< TAMPER_T::LIRCTL: TLRCTRIM Mask */ + +#define TAMPER_LIRCTL_TRIMMOS_Pos (9) /*!< TAMPER_T::LIRCTL: TRIMMOS Position */ +#define TAMPER_LIRCTL_TRIMMOS_Msk (0x3ul << TAMPER_LIRCTL_TRIMMOS_Pos) /*!< TAMPER_T::LIRCTL: TRIMMOS Mask */ + +#define TAMPER_TIOCTL_DYN1ISS_Pos (0) /*!< TAMPER_T::TIOCTL: DYN1ISS Position */ +#define TAMPER_TIOCTL_DYN1ISS_Msk (0x1ul << TAMPER_TIOCTL_DYN1ISS_Pos) /*!< TAMPER_T::TIOCTL: DYN1ISS Mask */ + +#define TAMPER_TIOCTL_DYN2ISS_Pos (1) /*!< TAMPER_T::TIOCTL: DYN2ISS Position */ +#define TAMPER_TIOCTL_DYN2ISS_Msk (0x1ul << TAMPER_TIOCTL_DYN2ISS_Pos) /*!< TAMPER_T::TIOCTL: DYN2ISS Mask */ + +#define TAMPER_TIOCTL_DYNSRC_Pos (3) /*!< TAMPER_T::TIOCTL: DYNSRC Position */ +#define TAMPER_TIOCTL_DYNSRC_Msk (0x1ul << TAMPER_TIOCTL_DYNSRC_Pos) /*!< TAMPER_T::TIOCTL: DYNSRC Mask */ + +#define TAMPER_TIOCTL_SEEDRLD_Pos (4) /*!< TAMPER_T::TIOCTL: SEEDRLD Position */ +#define TAMPER_TIOCTL_SEEDRLD_Msk (0x1ul << TAMPER_TIOCTL_SEEDRLD_Pos) /*!< TAMPER_T::TIOCTL: SEEDRLD Mask */ + +#define TAMPER_TIOCTL_DYNRATE_Pos (5) /*!< TAMPER_T::TIOCTL: DYNRATE Position */ +#define TAMPER_TIOCTL_DYNRATE_Msk (0x7ul << TAMPER_TIOCTL_DYNRATE_Pos) /*!< TAMPER_T::TIOCTL: DYNRATE Mask */ + +#define TAMPER_TIOCTL_TAMP0EN_Pos (8) /*!< TAMPER_T::TIOCTL: TAMP0EN Position */ +#define TAMPER_TIOCTL_TAMP0EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP0EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP0EN Mask */ + +#define TAMPER_TIOCTL_TAMP0LV_Pos (9) /*!< TAMPER_T::TIOCTL: TAMP0LV Position */ +#define TAMPER_TIOCTL_TAMP0LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP0LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP0LV Mask */ + +#define TAMPER_TIOCTL_TAMP0DBEN_Pos (10) /*!< TAMPER_T::TIOCTL: TAMP0DBEN Position */ +#define TAMPER_TIOCTL_TAMP0DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP0DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP0DBEN Mask */ + +#define TAMPER_TIOCTL_TAMP1EN_Pos (12) /*!< TAMPER_T::TIOCTL: TAMP1EN Position */ +#define TAMPER_TIOCTL_TAMP1EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP1EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP1EN Mask */ + +#define TAMPER_TIOCTL_TAMP1LV_Pos (13) /*!< TAMPER_T::TIOCTL: TAMP1LV Position */ +#define TAMPER_TIOCTL_TAMP1LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP1LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP1LV Mask */ + +#define TAMPER_TIOCTL_TAMP1DBEN_Pos (14) /*!< TAMPER_T::TIOCTL: TAMP1DBEN Position */ +#define TAMPER_TIOCTL_TAMP1DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP1DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP1DBEN Mask */ + +#define TAMPER_TIOCTL_DYNPR0EN_Pos (15) /*!< TAMPER_T::TIOCTL: DYNPR0EN Position */ +#define TAMPER_TIOCTL_DYNPR0EN_Msk (0x1ul << TAMPER_TIOCTL_DYNPR0EN_Pos) /*!< TAMPER_T::TIOCTL: DYNPR0EN Mask */ + +#define TAMPER_TIOCTL_TAMP2EN_Pos (16) /*!< TAMPER_T::TIOCTL: TAMP2EN Position */ +#define TAMPER_TIOCTL_TAMP2EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP2EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP2EN Mask */ + +#define TAMPER_TIOCTL_TAMP2LV_Pos (17) /*!< TAMPER_T::TIOCTL: TAMP2LV Position */ +#define TAMPER_TIOCTL_TAMP2LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP2LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP2LV Mask */ + +#define TAMPER_TIOCTL_TAMP2DBEN_Pos (18) /*!< TAMPER_T::TIOCTL: TAMP2DBEN Position */ +#define TAMPER_TIOCTL_TAMP2DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP2DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP2DBEN Mask */ + +#define TAMPER_TIOCTL_TAMP3EN_Pos (20) /*!< TAMPER_T::TIOCTL: TAMP3EN Position */ +#define TAMPER_TIOCTL_TAMP3EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP3EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP3EN Mask */ + +#define TAMPER_TIOCTL_TAMP3LV_Pos (21) /*!< TAMPER_T::TIOCTL: TAMP3LV Position */ +#define TAMPER_TIOCTL_TAMP3LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP3LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP3LV Mask */ + +#define TAMPER_TIOCTL_TAMP3DBEN_Pos (22) /*!< TAMPER_T::TIOCTL: TAMP3DBEN Position */ +#define TAMPER_TIOCTL_TAMP3DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP3DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP3DBEN Mask */ + +#define TAMPER_TIOCTL_DYNPR1EN_Pos (23) /*!< TAMPER_T::TIOCTL: DYNPR1EN Position */ +#define TAMPER_TIOCTL_DYNPR1EN_Msk (0x1ul << TAMPER_TIOCTL_DYNPR1EN_Pos) /*!< TAMPER_T::TIOCTL: DYNPR1EN Mask */ + +#define TAMPER_TIOCTL_TAMP4EN_Pos (24) /*!< TAMPER_T::TIOCTL: TAMP4EN Position */ +#define TAMPER_TIOCTL_TAMP4EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP4EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP4EN Mask */ + +#define TAMPER_TIOCTL_TAMP4LV_Pos (25) /*!< TAMPER_T::TIOCTL: TAMP4LV Position */ +#define TAMPER_TIOCTL_TAMP4LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP4LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP4LV Mask */ + +#define TAMPER_TIOCTL_TAMP4DBEN_Pos (26) /*!< TAMPER_T::TIOCTL: TAMP4DBEN Position */ +#define TAMPER_TIOCTL_TAMP4DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP4DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP4DBEN Mask */ + +#define TAMPER_TIOCTL_TAMP5EN_Pos (28) /*!< TAMPER_T::TIOCTL: TAMP5EN Position */ +#define TAMPER_TIOCTL_TAMP5EN_Msk (0x1ul << TAMPER_TIOCTL_TAMP5EN_Pos) /*!< TAMPER_T::TIOCTL: TAMP5EN Mask */ + +#define TAMPER_TIOCTL_TAMP5LV_Pos (29) /*!< TAMPER_T::TIOCTL: TAMP5LV Position */ +#define TAMPER_TIOCTL_TAMP5LV_Msk (0x1ul << TAMPER_TIOCTL_TAMP5LV_Pos) /*!< TAMPER_T::TIOCTL: TAMP5LV Mask */ + +#define TAMPER_TIOCTL_TAMP5DBEN_Pos (30) /*!< TAMPER_T::TIOCTL: TAMP5DBEN Position */ +#define TAMPER_TIOCTL_TAMP5DBEN_Msk (0x1ul << TAMPER_TIOCTL_TAMP5DBEN_Pos) /*!< TAMPER_T::TIOCTL: TAMP5DBEN Mask */ + +#define TAMPER_TIOCTL_DYNPR2EN_Pos (31) /*!< TAMPER_T::TIOCTL: DYNPR2EN Position */ +#define TAMPER_TIOCTL_DYNPR2EN_Msk (0x1ul << TAMPER_TIOCTL_DYNPR2EN_Pos) /*!< TAMPER_T::TIOCTL: DYNPR2EN Mask */ + +#define TAMPER_SEED_SEED_Pos (0) /*!< TAMPER_T::SEED: SEED Position */ +#define TAMPER_SEED_SEED_Msk (0xfffffffful << TAMPER_SEED_SEED_Pos) /*!< TAMPER_T::SEED: SEED Mask */ + +#define TAMPER_SEED2_SEED2_Pos (0) /*!< TAMPER_T::SEED2: SEED2 Position */ +#define TAMPER_SEED2_SEED2_Msk (0xfffffffful << TAMPER_SEED2_SEED2_Pos) /*!< TAMPER_T::SEED2: SEED2 Mask */ + +#define TAMPER_ACTSTIOCTL1_ADYN1ISS_Pos (0) /*!< TAMPER_T::ACTSTIOCTL1: ADYN1ISS Position*/ +#define TAMPER_ACTSTIOCTL1_ADYN1ISS_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYN1ISS_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYN1ISS Mask */ + +#define TAMPER_ACTSTIOCTL1_ADYNSRC_Pos (3) /*!< TAMPER_T::ACTSTIOCTL1: ADYNSRC Position*/ +#define TAMPER_ACTSTIOCTL1_ADYNSRC_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNSRC_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNSRC Mask */ + +#define TAMPER_ACTSTIOCTL1_ADYNRATE_Pos (5) /*!< TAMPER_T::ACTSTIOCTL1: ADYNRATE Position*/ +#define TAMPER_ACTSTIOCTL1_ADYNRATE_Msk (0x7ul << TAMPER_ACTSTIOCTL1_ADYNRATE_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNRATE Mask */ + +#define TAMPER_ACTSTIOCTL1_ATAMP0EN_Pos (8) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP0EN Position*/ +#define TAMPER_ACTSTIOCTL1_ATAMP0EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP0EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP0EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ATAMP1EN_Pos (12) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP1EN Position*/ +#define TAMPER_ACTSTIOCTL1_ATAMP1EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP1EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP1EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ADYNPR0EN_Pos (15) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR0EN Position*/ +#define TAMPER_ACTSTIOCTL1_ADYNPR0EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNPR0EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR0EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ATAMP2EN_Pos (16) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP2EN Position*/ +#define TAMPER_ACTSTIOCTL1_ATAMP2EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP2EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP2EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ATAMP3EN_Pos (20) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP3EN Position*/ +#define TAMPER_ACTSTIOCTL1_ATAMP3EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP3EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP3EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ADYNPR1EN_Pos (23) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR1EN Position*/ +#define TAMPER_ACTSTIOCTL1_ADYNPR1EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNPR1EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR1EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ATAMP4EN_Pos (24) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP4EN Position*/ +#define TAMPER_ACTSTIOCTL1_ATAMP4EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP4EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP4EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ATAMP5EN_Pos (28) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP5EN Position*/ +#define TAMPER_ACTSTIOCTL1_ATAMP5EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ATAMP5EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ATAMP5EN Mask */ + +#define TAMPER_ACTSTIOCTL1_ADYNPR2EN_Pos (31) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR2EN Position*/ +#define TAMPER_ACTSTIOCTL1_ADYNPR2EN_Msk (0x1ul << TAMPER_ACTSTIOCTL1_ADYNPR2EN_Pos) /*!< TAMPER_T::ACTSTIOCTL1: ADYNPR2EN Mask */ + +#define TAMPER_ACTSTIOCTL2_ADYN1ISS2_Pos (0) /*!< TAMPER_T::ACTSTIOCTL2: ADYN1ISS2 Position*/ +#define TAMPER_ACTSTIOCTL2_ADYN1ISS2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYN1ISS2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYN1ISS2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ADYNSRC2_Pos (3) /*!< TAMPER_T::ACTSTIOCTL2: ADYNSRC2 Position*/ +#define TAMPER_ACTSTIOCTL2_ADYNSRC2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNSRC2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNSRC2 Mask */ + +#define TAMPER_ACTSTIOCTL2_SEEDRLD2_Pos (4) /*!< TAMPER_T::ACTSTIOCTL2: SEEDRLD2 Position*/ +#define TAMPER_ACTSTIOCTL2_SEEDRLD2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_SEEDRLD2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: SEEDRLD2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ADYNRATE2_Pos (5) /*!< TAMPER_T::ACTSTIOCTL2: ADYNRATE2 Position*/ +#define TAMPER_ACTSTIOCTL2_ADYNRATE2_Msk (0x7ul << TAMPER_ACTSTIOCTL2_ADYNRATE2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNRATE2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ATAMP0EN2_Pos (8) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP0EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ATAMP0EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP0EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP0EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ATAMP1EN2_Pos (12) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP1EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ATAMP1EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP1EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP1EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Pos (15) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR0EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR0EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ATAMP2EN2_Pos (16) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP2EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ATAMP2EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP2EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP2EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ATAMP3EN2_Pos (20) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP3EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ATAMP3EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP3EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP3EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ADYNPR1EN2_Pos (23) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR1EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ADYNPR1EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNPR1EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR1EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ATAMP4EN2_Pos (24) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP4EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ATAMP4EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP4EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP4EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ATAMP5EN2_Pos (28) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP5EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ATAMP5EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ATAMP5EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ATAMP5EN2 Mask */ + +#define TAMPER_ACTSTIOCTL2_ADYNPR2EN2_Pos (31) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR2EN2 Position*/ +#define TAMPER_ACTSTIOCTL2_ADYNPR2EN2_Msk (0x1ul << TAMPER_ACTSTIOCTL2_ADYNPR2EN2_Pos) /*!< TAMPER_T::ACTSTIOCTL2: ADYNPR2EN2 Mask */ + +#define TAMPER_CDBR_STOPBD_Pos (0) /*!< TAMPER_T::CDBR: STOPBD Position */ +#define TAMPER_CDBR_STOPBD_Msk (0xfful << TAMPER_CDBR_STOPBD_Pos) /*!< TAMPER_T::CDBR: STOPBD Mask */ + +#define TAMPER_CDBR_FAILBD_Pos (16) /*!< TAMPER_T::CDBR: FAILBD Position */ +#define TAMPER_CDBR_FAILBD_Msk (0xfful << TAMPER_CDBR_FAILBD_Pos) /*!< TAMPER_T::CDBR: FAILBD Mask */ + +#define TAMPER_VG_PCLKSEL0_Pos (0) /*!< TAMPER_T::VG: PCLKSEL0 Position */ +#define TAMPER_VG_PCLKSEL0_Msk (0xful << TAMPER_VG_PCLKSEL0_Pos) /*!< TAMPER_T::VG: PCLKSEL0 Mask */ + +#define TAMPER_VG_NCLKSEL0_Pos (4) /*!< TAMPER_T::VG: NCLKSEL0 Position */ +#define TAMPER_VG_NCLKSEL0_Msk (0xful << TAMPER_VG_NCLKSEL0_Pos) /*!< TAMPER_T::VG: NCLKSEL0 Mask */ + +#define TAMPER_VG_PDATSEL0_Pos (8) /*!< TAMPER_T::VG: PDATSEL0 Position */ +#define TAMPER_VG_PDATSEL0_Msk (0xful << TAMPER_VG_PDATSEL0_Pos) /*!< TAMPER_T::VG: PDATSEL0 Mask */ + +#define TAMPER_VG_NDATSEL0_Pos (12) /*!< TAMPER_T::VG: NDATSEL0 Position */ +#define TAMPER_VG_NDATSEL0_Msk (0xful << TAMPER_VG_NDATSEL0_Pos) /*!< TAMPER_T::VG: NDATSEL0 Mask */ + +#define TAMPER_VG_PCLKSEL1_Pos (16) /*!< TAMPER_T::VG: PCLKSEL1 Position */ +#define TAMPER_VG_PCLKSEL1_Msk (0xful << TAMPER_VG_PCLKSEL1_Pos) /*!< TAMPER_T::VG: PCLKSEL1 Mask */ + +#define TAMPER_VG_NCLKSEL1_Pos (20) /*!< TAMPER_T::VG: NCLKSEL1 Position */ +#define TAMPER_VG_NCLKSEL1_Msk (0xful << TAMPER_VG_NCLKSEL1_Pos) /*!< TAMPER_T::VG: NCLKSEL1 Mask */ + +#define TAMPER_VG_PDATSEL1_Pos (24) /*!< TAMPER_T::VG: PDATSEL1 Position */ +#define TAMPER_VG_PDATSEL1_Msk (0xful << TAMPER_VG_PDATSEL1_Pos) /*!< TAMPER_T::VG: PDATSEL1 Mask */ + +#define TAMPER_VG_NDATSEL1_Pos (28) /*!< TAMPER_T::VG: NDATSEL1 Position */ +#define TAMPER_VG_NDATSEL1_Msk (0xful << TAMPER_VG_NDATSEL1_Pos) /*!< TAMPER_T::VG: NDATSEL1 Mask */ + +#define TAMPER_VGEV_VGECNTP_Pos (0) /*!< TAMPER_T::VGEV: VGECNTP Position */ +#define TAMPER_VGEV_VGECNTP_Msk (0xfful << TAMPER_VGEV_VGECNTP_Pos) /*!< TAMPER_T::VGEV: VGECNTP Mask */ + +#define TAMPER_VGEV_VGECNTN_Pos (8) /*!< TAMPER_T::VGEV: VGECNTN Position */ +#define TAMPER_VGEV_VGECNTN_Msk (0xfful << TAMPER_VGEV_VGECNTN_Pos) /*!< TAMPER_T::VGEV: VGECNTN Mask */ + +#define TAMPER_LDOTRIM_TLDOTRIM_Pos (0) /*!< TAMPER_T::LDOTRIM: TLDOTRIM Position */ +#define TAMPER_LDOTRIM_TLDOTRIM_Msk (0xful << TAMPER_LDOTRIM_TLDOTRIM_Pos) /*!< TAMPER_T::LDOTRIM: TLDOTRIM Mask */ + +#define TAMPER_LDOTRIM_TLDOIQSEL_Pos (8) /*!< TAMPER_T::LDOTRIM: TLDOIQSEL Position */ +#define TAMPER_LDOTRIM_TLDOIQSEL_Msk (0x3ul << TAMPER_LDOTRIM_TLDOIQSEL_Pos) /*!< TAMPER_T::LDOTRIM: TLDOIQSEL Mask */ + +#define TAMPER_LBSTRIM_TLVDSEL_Pos (0) /*!< TAMPER_T::LBSTRIM: TLVDSEL Position */ +#define TAMPER_LBSTRIM_TLVDSEL_Msk (0x7ul << TAMPER_LBSTRIM_TLVDSEL_Pos) /*!< TAMPER_T::LBSTRIM: TLVDSEL Mask */ + +#define TAMPER_LBSTRIM_TOVDSEL_Pos (4) /*!< TAMPER_T::LBSTRIM: TOVDSEL Position */ +#define TAMPER_LBSTRIM_TOVDSEL_Msk (0x1ul << TAMPER_LBSTRIM_TOVDSEL_Pos) /*!< TAMPER_T::LBSTRIM: TOVDSEL Mask */ + +#define TAMPER_LBSTRIM_BSCMPLV_Pos (8) /*!< TAMPER_T::LBSTRIM: BSCMPLV Position */ +#define TAMPER_LBSTRIM_BSCMPLV_Msk (0x3ul << TAMPER_LBSTRIM_BSCMPLV_Pos) /*!< TAMPER_T::LBSTRIM: BSCMPLV Mask */ + +#define TAMPER_LBSTRIM_BSCMPOV_Pos (10) /*!< TAMPER_T::LBSTRIM: BSCMPOV Position */ +#define TAMPER_LBSTRIM_BSCMPOV_Msk (0x3ul << TAMPER_LBSTRIM_BSCMPOV_Pos) /*!< TAMPER_T::LBSTRIM: BSCMPOV Mask */ + +#define TAMPER_LBSTRIM_HYSCMPLV_Pos (12) /*!< TAMPER_T::LBSTRIM: HYSCMPLV Position */ +#define TAMPER_LBSTRIM_HYSCMPLV_Msk (0x3ul << TAMPER_LBSTRIM_HYSCMPLV_Pos) /*!< TAMPER_T::LBSTRIM: HYSCMPLV Mask */ + +#define TAMPER_LBSTRIM_HYSCMPOV_Pos (14) /*!< TAMPER_T::LBSTRIM: HYSCMPOV Position */ +#define TAMPER_LBSTRIM_HYSCMPOV_Msk (0x3ul << TAMPER_LBSTRIM_HYSCMPOV_Pos) /*!< TAMPER_T::LBSTRIM: HYSCMPOV Mask */ + +#define TAMPER_VG2_PCLKSEL2_Pos (0) /*!< TAMPER_T::VG2: PCLKSEL2 Position */ +#define TAMPER_VG2_PCLKSEL2_Msk (0xful << TAMPER_VG2_PCLKSEL2_Pos) /*!< TAMPER_T::VG2: PCLKSEL2 Mask */ + +#define TAMPER_VG2_NCLKSEL2_Pos (4) /*!< TAMPER_T::VG2: NCLKSEL2 Position */ +#define TAMPER_VG2_NCLKSEL2_Msk (0xful << TAMPER_VG2_NCLKSEL2_Pos) /*!< TAMPER_T::VG2: NCLKSEL2 Mask */ + +#define TAMPER_VG2_PDATSEL2_Pos (8) /*!< TAMPER_T::VG2: PDATSEL2 Position */ +#define TAMPER_VG2_PDATSEL2_Msk (0xful << TAMPER_VG2_PDATSEL2_Pos) /*!< TAMPER_T::VG2: PDATSEL2 Mask */ + +#define TAMPER_VG2_NDATSEL2_Pos (12) /*!< TAMPER_T::VG2: NDATSEL2 Position */ +#define TAMPER_VG2_NDATSEL2_Msk (0xful << TAMPER_VG2_NDATSEL2_Pos) /*!< TAMPER_T::VG2: NDATSEL2 Mask */ + +#define TAMPER_VG2_PCLKSEL3_Pos (16) /*!< TAMPER_T::VG2: PCLKSEL3 Position */ +#define TAMPER_VG2_PCLKSEL3_Msk (0xful << TAMPER_VG2_PCLKSEL3_Pos) /*!< TAMPER_T::VG2: PCLKSEL3 Mask */ + +#define TAMPER_VG2_NCLKSEL3_Pos (20) /*!< TAMPER_T::VG2: NCLKSEL3 Position */ +#define TAMPER_VG2_NCLKSEL3_Msk (0xful << TAMPER_VG2_NCLKSEL3_Pos) /*!< TAMPER_T::VG2: NCLKSEL3 Mask */ + +#define TAMPER_VG2_PDATSEL3_Pos (24) /*!< TAMPER_T::VG2: PDATSEL3 Position */ +#define TAMPER_VG2_PDATSEL3_Msk (0xful << TAMPER_VG2_PDATSEL3_Pos) /*!< TAMPER_T::VG2: PDATSEL3 Mask */ + +#define TAMPER_VG2_NDATSEL3_Pos (28) /*!< TAMPER_T::VG2: NDATSEL3 Position */ +#define TAMPER_VG2_NDATSEL3_Msk (0xful << TAMPER_VG2_NDATSEL3_Pos) /*!< TAMPER_T::VG2: NDATSEL3 Mask */ + +/**@}*/ /* TAMPER_CONST */ +/**@}*/ /* end of TAMPER register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __TAMPER_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/timer_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/timer_reg.h new file mode 100644 index 0000000000..eee7fe6433 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/timer_reg.h @@ -0,0 +1,1168 @@ +/**************************************************************************//** + * @file timer_reg.h + * @version V1.00 + * @brief TIMER register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_REG_H__ +#define __TIMER_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- Timer Controller -------------------------*/ +/** + @addtogroup TIMER Timer Controller(TIMER) + Memory Mapped Structure for TIMER Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var TIMER_T::CTL + * Offset: 0x00 Timer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |PSC |Prescale Counter + * | | |Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter + * | | |If this field is 0 (PSC = 0), then there is no scaling. + * | | |Note: Update prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value. + * |[15] |FUNCSEL |Function Selection + * | | |This bit sets the operation mode of Timer4 and Timer5 to PWM function. + * | | |0 = Timer controller is used as timer function. + * | | |1 = Timer controller is used as PWM function. + * | | |Note: The Timer0 ~ Timer3 function selection is controlled in TIMERx_ALTCTL[0], x= 0~3. + * |[19] |INTRGEN |Inter-timer Trigger Mode Enable Control + * | | |Setting this bit will enable the inter-timer trigger capture function. + * | | |The Timer0/2/4 will be in event counter mode and counting with external clock source or event + * | | |Also, Timer1/3/5 will be in trigger-counting mode of capture function. + * | | |0 = Inter-Timer Trigger Capture mode Disabled. + * | | |1 = Inter-Timer Trigger Capture mode Enabled. + * | | |Note: For Timer1/3/5, this bit is ignored and the read back value is always 0. + * |[20] |PERIOSEL |Periodic Mode Behavior Selection Enable Bit + * | | |0 = The behavior selection in periodic mode is Disabled. + * | | |When user updates CMPDAT while timer is running in periodic mode, CNT will be reset to default value. + * | | |1 = The behavior selection in periodic mode is Enabled. + * | | |When user update CMPDAT while timer is running in periodic mode, the limitations as bellows list, + * | | |If updated CMPDAT value > CNT, CMPDAT will be updated and CNT keep running continually. + * | | |If updated CMPDAT value = CNT, timer time-out interrupt will be asserted immediately. + * | | |If updated CMPDAT value < CNT, CNT will be reset to default value. + * |[21] |TGLPINSEL |Toggle-output Pin Select + * | | |0 = Toggle mode output to TMx (Timer Event Counter Pin). + * | | |1 = Toggle mode output to TMx_EXT (Timer External Capture Pin). + * |[22] |CAPSRC |Capture Pin Source Selection + * | | |0 = Capture Function source is from TMx_EXT (x= 0~5) pin. + * | | |1 = Capture Function source is from internal ACMP output signal, internal clock source (HIRC, LIRC, MIRC) or external clock (HXT, LXT). + * | | |Note1: When CAPSRC = 1, user can set INTERCAPSEL (TIMERx_EXTCTL[10:8]) to decide which internal ACMP output signal or which clock is as timer capture source. + * | | |Note2: MIRC clock source is only available in Timer4 ~ Timer5. + * |[23] |WKEN |Wake-up Function Enable Bit + * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU. + * | | |0 = Wake-up function Disabled if timer interrupt signal generated. + * | | |1 = Wake-up function Enabled if timer interrupt signal generated. + * |[24] |EXTCNTEN |Event Counter Mode Enable Bit + * | | |This bit is for external counting pin function enabled. + * | | |0 = Event counter mode Disabled. + * | | |1 = Event counter mode Enabled. + * | | |Note: When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source. + * |[25] |ACTSTS |Timer Active Status Bit (Read Only) + * | | |This bit indicates the 24-bit up counter status. + * | | |0 = 24-bit up counter is not active. + * | | |1 = 24-bit up counter is active. + * | | |Note: This bit may active when CNT 0 transition to CNT 1. + * |[28:27] |OPMODE |Timer Counting Mode Select + * | | |00 = The Timer controller is operated in One-shot mode. + * | | |01 = The Timer controller is operated in Periodic mode. + * | | |10 = The Timer controller is operated in Toggle-output mode. + * | | |11 = The Timer controller is operated in Continuous Counting mode. + * |[29] |INTEN |Timer Interrupt Enable Bit + * | | |0 = Timer time-out interrupt Disabled. + * | | |1 = Timer time-out interrupt Enabled. + * | | |Note: If this bit is enabled, when the timer time-out interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU. + * |[30] |CNTEN |Timer Counting Enable Bit + * | | |0 = Stops/Suspends counting. + * | | |1 = Starts counting. + * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value. + * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer time-out interrupt flag TIF (TIMERx_INTSTS[0]) is generated. + * | | |Note3: Set enable/disable this bit needs 2 * TMR_CLK period to become active, user can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgment effects TIMER counting. + * | | |TIMER counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgment Disabled. + * | | |TIMER counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var TIMER_T::CMP + * Offset: 0x04 Timer Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CMPDAT |Timer Comparator Value + * | | |CMPDAT is a 24-bit compared value register. + * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1. + * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT). + * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state. + * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. + * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field. + * @var TIMER_T::INTSTS + * Offset: 0x08 Timer Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TIF |Timer Interrupt Flag + * | | |This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value. + * | | |0 = No effect. + * | | |1 = CNT value matches the CMPDAT value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |TWKF |Timer Wake-up Flag + * | | |This bit indicates the interrupt wake-up flag status of timer. + * | | |0 = Timer does not cause CPU wake-up. + * | | |1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated. + * | | |Note: This bit is cleared by writing 1 to it. + * @var TIMER_T::CNT + * Offset: 0x0C Timer Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CNT |Timer Data Register + * | | |Read operation. + * | | |Read this register to get CNT value. For example: + * | | |If EXTCNTEN (TIMERx_CTL[24]) is 0, user can read CNT value for getting current 24-bit counter value. + * | | |If EXTCNTEN (TIMERx_CTL[24]) is 1, user can read CNT value for getting current 24-bit event input counter value. + * | | |Write operation. + * | | |Writing any value to this register will reset current CNT value to 0 and reload internal 8-bit prescale counter. + * |[31] |RSTACT |Timer Data Register Reset Active (Read Only) + * | | |This bit indicates if the counter reset operation active. + * | | |When user writes this CNT register, timer starts to reset its internal 24-bit timer up-counter to 0 and reload 8-bit pre-scale counter. + * | | |At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. + * | | |Once the counter reset operation done, timer clear this bit to 0 automatically. + * | | |0 = Reset operation is done. + * | | |1 = Reset operation triggered by writing TIMERx_CNT is in progress. + * | | |Note: This bit is read only. + * @var TIMER_T::CAP + * Offset: 0x10 Timer Capture Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[23:0] |CAPDAT |Timer Capture Data Register + * | | |When CAPEN (TIMERx_EXTCTL[3]) bit is set, the transition on the capture source matches the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, + * | | |CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field. + * @var TIMER_T::EXTCTL + * Offset: 0x14 Timer External Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTPHASE |Timer External Count Phase + * | | |This bit indicates the detection phase of external counting pin TMx (x= 0~5). + * | | |0 = A falling edge of external counting pin will be counted. + * | | |1 = A rising edge of external counting pin will be counted. + * |[3] |CAPEN |Timer Capture Function Enable Bit + * | | |This bit enables the capture input function. + * | | |0 = Timer capture function Disabled. + * | | |1 = Timer capture function Enabled. + * |[4] |CAPFUNCS |Capture Function Selection + * | | |0 = Capture Mode Enabled. + * | | |1 = Reset Mode Enabled. + * | | |Note1: When CAPFUNCS is 0 and CAPIF becomes 1, the current 24-bit timer counter value (CNT value) will be saved to CAPDAT field. + * | | |Note2: When CAPFUNCS is 1 and CAPIF becomes 1, the current 24-bit timer counter value (CNT value) will be saved to CAPDAT field then CNT value will be reset immediately. + * |[5] |CAPIEN |Timer Capture Interrupt Enable Bit + * | | |0 = TMx_EXT (x= 0~5), ACMP, internal clock, or external clock detection Interrupt Disabled. + * | | |1 = TMx_EXT (x= 0~5), ACMP, internal clock, or external clock detection Interrupt Enabled. + * | | |Note: CAPIEN is used to enable timer capture interrupt. + * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1. + * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TMx_EXT pin, ACMP, internal clock, or external clock + * | | |will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU. + * |[6] |CAPDBEN |Timer Capture De-bounce Enable Bit + * | | |0 = TMx_EXT (x= 0~5) pin de-bounce or ACMP output de-bounce Disabled. + * | | |1 = TMx_EXT (x= 0~5) pin de-bounce or ACMP output de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit. + * |[7] |CNTDBEN |Timer External Counter Pin De-bounce Enable Bit + * | | |0 = TMx (x= 0~5) pin de-bounce Disabled. + * | | |1 = TMx (x= 0~5) pin de-bounce Enabled. + * | | |Note: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit. + * |[10:8] |INTERCAPSEL|Internal Capture Source Select + * | | |000 = Capture Function source is from internal ACMP0 output signal. + * | | |001 = Capture Function source is from internal ACMP1 output signal. + * | | |010 = Capture Function source is from HXT. + * | | |011 = Capture Function source is from LXT. + * | | |100 = Capture Function source is from HIRC. + * | | |101 = Capture Function source is from LIRC. + * | | |101 = Capture Function source is from LIRC. + * | | |110 = Capture Function source is from MIRC, only available in Timer4 and Timer5. + * | | |111 = Reserved. + * | | |Note: These bits only available when CAPSRC (TIMERx_CTL[22]) is 1. + * |[14:12] |CAPEDGE |Timer Capture Edge Detect + * | | |When first capture event is generated, the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) should be to 0. + * | | |000 = Capture event occurred when detect falling edge transfer on capture source. + * | | |001 = Capture event occurred when detect rising edge transfer on capture source. + * | | |010 = Capture event occurred when detect both falling and rising edge transfer on capture source, and the first capture event occurred at falling edge transfer. + * | | |011 = Capture event occurred when detect both rising and falling edge transfer on capture source, and the first capture event occurred at rising edge transfer. + * | | |110 = First capture event occurred at falling edge, follows capture events are at rising edge transfer on capture source. + * | | |111 = First capture event occurred at rising edge, follows capture events are at falling edge transfer on capture source. + * | | |100, 101 = Reserved. + * | | |Note: Set CAPSRC (TIMERx_CTL[22]) and INTERCAPSEL (TIMERx_EXTCTL[10:8]) to select capture source. + * |[16] |ECNTSSEL |Event Counter Source Selection to Trigger Event Counter Function + * | | |0 = Event Counter input source is from TMx (x= 0~5) pin. + * | | |1 = Event Counter input source is from USB internal SOF output signal. + * |[31:28] |CAPDIVSCL |Timer Capture Source Divider Scale + * | | |This bits indicate the divide scale for capture source divider. + * | | |0000 = Capture source/1. + * | | |0001 = Capture source/2. + * | | |0010 = Capture source/4. + * | | |0011 = Capture source/8. + * | | |0100 = Capture source/16. + * | | |0101 = Capture source/32. + * | | |0110 = Capture source/64. + * | | |0111 = Capture source/128. + * | | |1000 = Capture source/256. + * | | |1001~1111 = Reserved. + * | | |Note: Sets INTERCAPSEL (TIMERx_EXTCTL[10:8]) and CAPSRC (TIMERx_CTL[22]) to select capture source. + * @var TIMER_T::EINTSTS + * Offset: 0x18 Timer External Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CAPIF |Timer Capture Interrupt Flag + * | | |This bit indicates the timer capture interrupt flag status. + * | | |0 = TMx_EXT (x= 0~5) pin, ACMP, internal clock, or external clock capture interrupt did not occur. + * | | |1 = TMx_EXT (x= 0~5) pin, ACMP, internal clock, or external clock capture interrupt occurred. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, the transition on the capture source matches the CAPEDGE (TIMERx_EXTCTL[14:12]) setting, this bit will set to 1 by hardware. + * | | |Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status. + * | | |If the above condition occurred, the timer will keep register TIMERx_CAP unchanged and drop the new capture value. + * @var TIMER_T::TRGCTL + * Offset: 0x1C Timer Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TRGSSEL |Trigger Source Select Bit + * | | |This bit is used to select internal trigger source is form timer time-out interrupt signal or capture interrupt signal. + * | | |0 = Time-out interrupt signal is used to internal trigger EPWM/BPWM, PDMA, DAC, and EADC. + * | | |1 = Capture interrupt signal is used to internal trigger EPWM/BPWM, PDMA, DAC, and EADC. + * |[1] |TRGPWM |Trigger EPWM and BPWM Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be as EPWM and BPWM counter clock source. + * | | |0 = Timer interrupt trigger EPWM and BPWM Disabled. + * | | |1 = Timer interrupt trigger EPWM and BPWM Enabled. + * | | |Note1: This bit is not available in Timer4 and Timer5. + * | | |Note2: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal as EPWM and BPWM counter clock source. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal as EPWM and BPWM counter clock source. + * |[2] |TRGEADC |Trigger EADC Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered EADC conversion. + * | | |0 = Timer interrupt trigger EADC Disabled. + * | | |1 = Timer interrupt trigger EADC Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger EADC conversion. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger EADC conversion. + * |[3] |TRGDAC |Trigger DAC Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered DAC. + * | | |0 = Timer interrupt trigger DAC Disabled. + * | | |1 = Timer interrupt trigger DAC Enabled. + * | | |Note1: This bit is not available in Timer4 and Timer5. + * | | |Note2: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger DAC. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger DAC. + * |[4] |TRGPDMA |Trigger PDMA Enable Bit + * | | |If this bit is set to 1, each timer time-out event or capture event can be triggered PDMA transfer. + * | | |0 = Timer interrupt trigger PDMA Disabled. + * | | |1 = Timer interrupt trigger PDMA Enabled. + * | | |Note: If TRGSSEL (TIMERx_TRGCTL[0]) = 0, time-out interrupt signal will trigger PDMA transfer. + * | | |If TRGSSEL (TIMERx_TRGCTL[0]) = 1, capture interrupt signal will trigger PDMA transfer. + * @var TIMER_T::ALTCTL + * Offset: 0x20 Timer Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |FUNCSEL |Function Selection + * | | |This bit sets the operation mode of Timer0 ~ Timer3 to PWM function. + * | | |0 = Timer controller is used as timer function. + * | | |1 = Timer controller is used as PWM function. + * | | |Note1: The Timer4 and Timer5 function selection is controlled in TIMERx_CTL[15], x= 4~5. + * | | |Note2: When timer is used as PWM, the clock source of time controller will be forced to PCLKx automatically. + * @var TIMER_T::PWMCTL + * Offset: 0x40 Timer PWM Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTEN |PWM Counter Enable Bit + * | | |0 = PWM counter and clock prescale Stop Running. + * | | |1 = PWM counter and clock prescale Start Running. + * |[2:1] |CNTTYPE |PWM Counter Behavior Type + * | | |These bits are used to set the count type of Timer0 ~ Timer3. The count type of Timer4 and Timer5 is fixed as the up count type. + * | | |00 = Up count type. + * | | |01 = Down count type. + * | | |10 = Up-down count type. + * | | |11 = Reserved. + * | | |Note: These bits are not available in Timer4 and Timer5. + * |[3] |CNTMODE |PWM Counter Mode + * | | |0 = Auto-reload mode. + * | | |1 = One-shot mode. + * |[8] |CTRLD |Center Re-load + * | | |In up-down count type, PERIOD will load to PBUF when current PWM period is completed always and CMP will load to CMPBUF at the center point of current period. + * | | |Note: This bit is not available in Timer4 and Timer5. + * |[9] |IMMLDEN |Immediately Load Enable Bit + * | | |0 = PERIOD will load to PBUF when current PWM period is completed no matter CTRLD is enabled/disabled. + * | | |If CTRLD is disabled, CMP will load to CMPBUF when current PWM period is completed; if CTRLD is enabled in up-down count type, CMP will load to CMPBUF at the center point of current period. + * | | |1 = PERIOD/CMP will load to PBUF/CMPBUF immediately when user update PERIOD/CMP. + * | | |Note1: This bit is not available in Timer4 and Timer5. + * | | |Note2: If IMMLDEN is enabled, CTRLD will be invalid. + * |[12] |WKEN |PWM Wake-up Enable Bit + * | | |If this bit is set to 1, the Timer4 and Timer5 PWM interrupt eventl will generate a wake-up trigger event to CPU. + * | | |0 = PWM interrupt wake-up Disabled. + * | | |1 = PWM interrupt wake-up Enabled. + * | | |Note: This bit is only available in Timer4 and Timer5. + * |[16] |OUTMODE |PWM Output Mode + * | | |This bit controls the output mode of corresponding PWM channel. + * | | |0 = PWM independent mode. + * | | |1 = PWM complementary mode. + * | | |Note: This bit is not available in Timer4 and Timer5. + * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) + * | | |If debug mode counter halt is enabled, PWM counter will keep current value until exit ICE debug mode. + * | | |0 = ICE debug mode counter halt disable. + * | | |1 = ICE debug mode counter halt enable. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Bit (Write Protect) + * | | |0 = ICE debug mode acknowledgment effects PWM output. + * | | |PWM output pin will be forced as tri-state while ICE debug mode acknowledged. + * | | |1 = ICE debug mode acknowledgment disabled. + * | | |PWM output pin will keep output no matter ICE debug mode acknowledged or not. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var TIMER_T::PWMCLKSRC + * Offset: 0x44 Timer PWM Counter Clock Source Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |CLKSRC |PWM Counter Clock Source Select + * | | |The PWM counter clock source can be selected from TMRx_CLK or internal timer time-out or capture event in Timer0 ~ Timer3. + * | | |000 = TMRx_CLK. + * | | |001 = Internal TIMER0 time-out or capture event. + * | | |010 = Internal TIMER1 time-out or capture event. + * | | |011 = Internal TIMER2 time-out or capture event. + * | | |100 = Internal TIMER3 time-out or capture event. + * | | |Others = Reserved. + * | | |Note1: These bits are not available in Timer4 and Timer5. + * | | |Note2: If TIMER0 PWM function is enabled, the PWM counter clock source can be selected from TMR0_CLK, TIMER1 interrupt events, TIMER2 interrupt events, or TIMER3 interrupt events. + * @var TIMER_T::PWMCLKPSC + * Offset: 0x48 Timer PWM Counter Clock Pre-scale Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |CLKPSC |PWM Counter Clock Pre-scale + * | | |The active clock of PWM counter is decided by counter clock prescale and divided by (CLKPSC + 1). + * | | |If CLKPSC is 0, then there is no scaling in PWM counter clock source. + * | | |Note: The valid value is 12-bit TIMERx_PWMCLKPSC[11:0] in Timer0 ~ Timer3, and 8-bit TIMERx_PWMCLKPSC[7:0] in Timer4 and Timer5. + * @var TIMER_T::PWMCNTCLR + * Offset: 0x4C Timer PWM Clear Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTCLR |Clear PWM Counter Control Bit + * | | |It is automatically cleared by hardware. + * | | |0 = No effect. + * | | |1 = In Timer0 ~ Timer3, clears 16-bit PWM counter to 0x10000 in up and up-down count type and reset counter value to PERIOD in down count type. + * | | |In Timer4 and Timer5, clears 16-bit PWM counter to 0x0 in up count type. + * @var TIMER_T::PWMPERIOD + * Offset: 0x50 Timer PWM Period Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PERIOD |PWM Period Register + * | | |In up count type: PWM counter counts from 0 to PERIOD, and restarts from 0. + * | | |In down count type: PWM counter counts from PERIOD to 0, and restarts from PERIOD. + * | | |In up-down count type: PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. + * | | |In up and down count type: + * | | |PWM period time = (PERIOD + 1) * (CLKPSC + 1) * TMRx_PWMCLK. + * | | |In up-down count type: + * | | |PWM period time = 2 * PERIOD * (CLKPSC+ 1) * TMRx_PWMCLK. + * | | |Note1: The count type of Timer4 and Timer5 is fixed as up count type. + * | | |Note2: User should take care DIRF (TIMERx_PWMCNT[16]) bit in up/down/up-down count type to monitor current counter direction in each count type in Timer0 ~ Timer3. + * @var TIMER_T::PWMCMPDAT + * Offset: 0x54 Timer PWM Comparator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMP |PWM Comparator Register + * | | |PWM CMP is used to compare with PWM CNT to generate PWM output waveform, interrupt events and trigger EADC and PDMA to start conversion. + * @var TIMER_T::PWMDTCTL + * Offset: 0x58 Timer PWM Dead-Time Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |DTCNT |Dead-time Counter (Write Protect) + * | | |The dead-time can be calculated from the following two formulas: + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK, if DTCKSEL is 0. + * | | |Dead-time = (DTCNT[11:0] + 1) * TMRx_PWMCLK * (CLKPSC + 1), if DTCKSEL is 1. + * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. + * |[16] |DTEN |Enable Dead-time Insertion for PWMx_CH0 and PWMx_CH1 (Write Protect) + * | | |Dead-time insertion function is only active when PWM complementary mode is enabled. + * | | |If dead-time insertion is inactive, the outputs of PWMx_CH0 and PWMx_CH1 are complementary without any delay. + * | | |0 = Dead-time insertion Disabled on the pin pair. + * | | |1 = Dead-time insertion Enabled on the pin pair. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) + * | | |0 = Dead-time clock source from TMRx_PWMCLK without counter clock prescale. + * | | |1 = Dead-time clock source from TMRx_PWMCLK with counter clock prescale. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var TIMER_T::PWMCNT + * Offset: 0x5C Timer PWM Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CNT |PWM Counter Value Register (Read Only) + * | | |User can monitor CNT to know the current counter value in 16-bit period counter. + * |[16] |DIRF |PWM Counter Direction Indicator Flag (Read Only) + * | | |0 = Counter is active in down count. + * | | |1 = Counter is active up count. + * | | |Note1: This indicator flag is used for Timer0 ~ Timer3 only. + * | | |Note2: Since the count type of Timer4 ~ Timer5 is fixed as up count, this bit is fixed 0 in Timer4 and Timer5. + * @var TIMER_T::PWMMSKEN + * Offset: 0x60 Timer PWM Output Mask Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKEN0 |PWMx_CH0 Output Mask Enable Bit + * | | |The PWMx_CH0 output signal will be masked when this bit is enabled. + * | | |The PWMx_CH0 will output MSKDAT0 (TIMERx_PWMMSK[0]) data. + * | | |0 = PWMx_CH0 output signal is non-masked. + * | | |1 = PWMx_CH0 output signal is masked and output MSKDAT0 data. + * |[1] |MSKEN1 |PWMx_CH1 Output Mask Enable Bit + * | | |The PWMx_CH1 output signal will be masked when this bit is enabled. + * | | |The PWMx_CH1 will output MSKDAT1 (TIMERx_PWMMSK[1]) data. + * | | |0 = PWMx_CH1 output signal is non-masked. + * | | |1 = PWMx_CH1 output signal is masked and output MSKDAT1 data. + * @var TIMER_T::PWMMSK + * Offset: 0x64 Timer PWM Output Mask Data Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |MSKDAT0 |PWMx_CH0 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH0 pin when PWMx_CH0 output mask function is enabled (MSKEN0 = 1). + * | | |0 = Output logic Low to PWMx_CH0. + * | | |1 = Output logic High to PWMx_CH0. + * |[1] |MSKDAT1 |PWMx_CH1 Output Mask Data Control Bit + * | | |This bit is used to control the output state of PWMx_CH1 pin when PWMx_CH1 output mask function is enabled (MSKEN1 = 1). + * | | |0 = Output logic Low to PWMx_CH1. + * | | |1 = Output logic High to PWMx_CH1. + * @var TIMER_T::PWMBNF + * Offset: 0x68 Timer PWM Brake Pin Noise Filter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKNFEN |Brake Pin Noise Filter Enable Bit + * | | |0 = Pin noise filter detect of PWMx_BRAKEy Disabled. + * | | |1 = Pin noise filter detect of PWMx_BRAKEy Enabled. + * |[3:1] |BRKNFSEL |Brake Pin Noise Filter Clock Selection + * | | |000 = Noise filter clock is PCLKx. + * | | |001 = Noise filter clock is PCLKx/2. + * | | |010 = Noise filter clock is PCLKx/4. + * | | |011 = Noise filter clock is PCLKx/8. + * | | |100 = Noise filter clock is PCLKx/16. + * | | |101 = Noise filter clock is PCLKx/32. + * | | |110 = Noise filter clock is PCLKx/64. + * | | |111 = Noise filter clock is PCLKx/128. + * |[6:4] |BRKFCNT |Brake Pin Noise Filter Count + * | | |The fields is used to control the active noise filter sample time. + * | | |Once noise filter sample time = (Period time of BRKNFSEL) * (BRKFCNT + 1). + * |[7] |BRKPINV |Brake Pin Detection Control Bit + * | | |0 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from low to high in edge-detect, or pin status is high in level-detect. + * | | |1 = Brake pin event will be detected if PWMx_BRAKEy pin status transfer from high to low in edge-detect, or pin status is low in level-detect . + * |[17:16] |BKPINSRC |Brake Pin Source Select + * | | |00 = Brake pin source comes from PWM0_BRAKE0 pin. + * | | |01 = Brake pin source comes from PWM0_BRAKE1 pin. + * | | |10 = Brake pin source comes from PWM1_BRAKE0 pin. + * | | |11 = Brake pin source comes from PWM1_BRAKE1 pin. + * @var TIMER_T::PWMFAILBRK + * Offset: 0x6C Timer PWM System Fail Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CSSBRKEN |Clock Security System Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by clock fail detection Disabled. + * | | |1 = Brake Function triggered by clock fail detection Enabled. + * |[1] |BODBRKEN |Brown-out Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by BOD event Disabled. + * | | |1 = Brake Function triggered by BOD event Enabled. + * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. + * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. + * |[3] |CORBRKEN |Core Lockup Detection Trigger PWM Brake Function Enable Bit + * | | |0 = Brake Function triggered by core lockup event Disabled. + * | | |1 = Brake Function triggered by core lockup event Enabled. + * @var TIMER_T::PWMBRKCTL + * Offset: 0x70 Timer PWM Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CPO0EBEN |Enable Internal ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP0_O signal as edge-detect brake source Disabled. + * | | |1 = Internal ACMP0_O signal as edge-detect brake source Enabled. + * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[1] |CPO1EBEN |Enable Internal ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP1_O signal as edge-detect brake source Disabled. + * | | |1 = Internal ACMP1_O signal as edge-detect brake source Enabled. + * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[4] |BRKPEEN |Enable TM_BRAKEx Pin As Edge-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as edge-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) + * | | |0 = System fail condition as edge-detect brake source Disabled. + * | | |1 = System fail condition as edge-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[8] |CPO0LBEN |Enable Internal ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP0_O signal as level-detect brake source Disabled. + * | | |1 = Internal ACMP0_O signal as level-detect brake source Enabled. + * | | |Note1: Only internal ACMP0_O signal from low to high will be detected as brake event. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[9] |CPO1LBEN |Enable Internal ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) + * | | |0 = Internal ACMP1_O signal as level-detect brake source Disabled. + * | | |1 = Internal ACMP1_O signal as level-detect brake source Enabled. + * | | |Note1: Only internal ACMP1_O signal from low to high will be detected as brake event. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[12] |BRKPLEN |Enable TM_BRAKEx Pin As Level-detect Brake Source (Write Protect) + * | | |0 = PWMx_BRAKEy pin event as level-detect brake source Disabled. + * | | |1 = PWMx_BRAKEy pin event as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) + * | | |0 = System fail condition as level-detect brake source Disabled. + * | | |1 = System fail condition as level-detect brake source Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[17:16] |BRKAEVEN |PWM Brake Action Select for PWMx_CH0 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH0 output. + * | | |01 = PWMx_CH0 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH0 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH0 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. + * |[19:18] |BRKAODD |PWM Brake Action Select for PWMx_CH1 (Write Protect) + * | | |00 = PWMx_BRAKEy brake event will not affect PWMx_CH1 output. + * | | |01 = PWMx_CH1 output tri-state when PWMx_BRAKEy brake event happened. + * | | |10 = PWMx_CH1 output low level when PWMx_BRAKEy brake event happened. + * | | |11 = PWMx_CH1 output high level when PWMx_BRAKEy brake event happened. + * | | |Note: These bits are write protected. Refer to SYS_REGLCTL register. + * @var TIMER_T::PWMPOLCTL + * Offset: 0x74 Timer PWM Pin Output Polar Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PINV0 |PWMx_CH0 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH0 output pin. + * | | |0 = PWMx_CH0 output pin polar inverse Disabled. + * | | |1 = PWMx_CH0 output pin polar inverse Enabled. + * | | |Note: In Timer4 and Timer5, the PWMx_CH0 output pin can be selected as TMx or TMx_EXT pin by POSEL (TIMERx_PWMPOEN[8]), x= 4~5. + * |[1] |PINV1 |PWMx_CH1 Output Pin Polar Control Bit + * | | |The bit is used to control polarity state of PWMx_CH1 output pin. + * | | |0 = PWMx_CH1 output pin polar inverse Disabled. + * | | |1 = PWMx_CH1 output pin polar inverse Enabled. + * | | |Note: This bit is not available in Timer4 and Timer5. + * @var TIMER_T::PWMPOEN + * Offset: 0x78 Timer PWM Pin Output Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |POEN0 |PWMx_CH0 Output Pin Enable Bit + * | | |0 = PWMx_CH0 pin at tri-state mode. + * | | |1 = PWMx_CH0 pin in output mode. + * | | |Note: In Timer4 and Timer5, the PWMx_CH0 output pin can be selected as TMx or TMx_EXT pin by POSEL (TIMERx_PWMPOEN[8]), x= 4~5. + * |[1] |POEN1 |PWMx_CH1 Output Pin Enable Bit + * | | |0 = PWMx_CH1 pin at tri-state mode. + * | | |1 = PWMx_CH1 pin in output mode. + * | | |Note: This bit is not available in Timer4 and Timer5. + * |[8] |POSEL |PWMx_CH0 Output Pin Select + * | | |This bit is used to select the output channel of Timer4 and Timer5 PWM. + * | | |0 = PWMx_CH0 pin is TMx. + * | | |1 = PWMx_CH0 pin is TMx_EXT. + * | | |Note: This bit is only available in Timer4 and Timer5. + * @var TIMER_T::PWMSWBRK + * Offset: 0x7C Timer PWM Software Trigger Brake Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKETRG |Software Trigger Edge-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM edge-detect brake source, then BRKEIF0 and BRKEIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLTRG |Software Trigger Level-detect Brake Source (Write Only) (Write Protect) + * | | |Write 1 to this bit will trigger PWM level-detect brake source, then BRKLIF0 and BRKLIF1 will set to 1 automatically in TIMERx_PWMINTSTS1 register. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var TIMER_T::PWMINTEN0 + * Offset: 0x80 Timer PWM Interrupt Enable Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIEN |PWM Zero Point Interrupt Enable Bit + * | | |0 = Zero point interrupt Disabled. + * | | |1 = Zero point interrupt Enabled. + * | | |Note: This bit is not available in Timer4 and Timer5. + * |[1] |PIEN |PWM Period Point Interrupt Enable Bit + * | | |0 = Period point interrupt Disabled. + * | | |1 = Period point interrupt Enabled. + * | | |Note: In up-down count type, period point means the center point of current PWM period. + * |[2] |CMPUIEN |PWM Compare Up Count Interrupt Enable Bit + * | | |0 = Compare up count interrupt Disabled. + * | | |1 = Compare up count interrupt Enabled. + * |[3] |CMPDIEN |PWM Compare Down Count Interrupt Enable Bit + * | | |0 = Compare down count interrupt Disabled. + * | | |1 = Compare down count interrupt Enabled. + * | | |Note: This bit is not available in Timer4 and Timer5. + * @var TIMER_T::PWMINTEN1 + * Offset: 0x84 Timer PWM Interrupt Enable Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIEN |PWM Edge-detect Brake Interrupt Enable (Write Protect) + * | | |0 = PWM edge-detect brake interrupt Disabled. + * | | |1 = PWM edge-detect brake interrupt Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLIEN |PWM Level-detect Brake Interrupt Enable (Write Protect) + * | | |0 = PWM level-detect brake interrupt Disabled. + * | | |1 = PWM level-detect brake interrupt Enabled. + * | | |Note: This bit is write protected. Refer to SYS_REGLCTL register. + * @var TIMER_T::PWMINTSTS0 + * Offset: 0x88 Timer PWM Interrupt Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ZIF |PWM Zero Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches zero. + * | | |Note1: This bit is not available in Timer4 and Timer5. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[1] |PIF |PWM Period Point Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter reaches PERIOD. + * | | |Note1: In up-down count type, PIF flag means the center point flag of current PWM period. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[2] |CMPUIF |PWM Compare Up Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in up count direction and reaches CMP. + * | | |Note1: If CMP equal to PERIOD, there is no CMPUIF flag in up count type and up-down count type.. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[3] |CMPDIF |PWM Compare Down Count Interrupt Flag + * | | |This bit is set by hardware when TIMERx_PWM counter in down count direction and reaches CMP. + * | | |Note1: This bit is not available in Timer4 and Timer5. + * | | |Note2: If CMP equal to PERIOD, there is no CMPDIF flag in down count type. + * | | |Note3: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMINTSTS1 + * Offset: 0x8C Timer PWM Interrupt Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BRKEIF0 |Edge-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 edge-detect brake event do not happened. + * | | |1 = PWMx_CH0 edge-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[1] |BRKEIF1 |Edge-detect Brake Interrupt Flag PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 edge-detect brake event do not happened. + * | | |1 = PWMx_CH1 edge-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[8] |BRKLIF0 |Level-detect Brake Interrupt Flag on PWMx_CH0 (Write Protect) + * | | |0 = PWMx_CH0 level-detect brake event do not happened. + * | | |1 = PWMx_CH0 level-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[9] |BRKLIF1 |Level-detect Brake Interrupt Flag on PWMx_CH1 (Write Protect) + * | | |0 = PWMx_CH1 level-detect brake event do not happened. + * | | |1 = PWMx_CH1 level-detect brake event happened. + * | | |Note1: This bit is cleared by writing 1 to it. + * | | |Note2: This bit is write protected. Refer to SYS_REGLCTL register. + * |[16] |BRKESTS0 |Edge -detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 edge-detect brake state is released. + * | | |1 = PWMx_CH0 at edge-detect brake state. + * | | |Note: User can set BRKEIF0 1 to clear BRKEIF0 flag and PWMx_CH0 will release brake state when current PWM period finished and resume PWMx_CH0 output waveform start from next full PWM period. + * |[17] |BRKESTS1 |Edge-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 edge-detect brake state is released. + * | | |1 = PWMx_CH1 at edge-detect brake state. + * | | |Note: User can set BRKEIF1 1 to clear BRKEIF1 flag and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH1 output waveform start from next full PWM period. + * |[24] |BRKLSTS0 |Level-detect Brake Status of PWMx_CH0 (Read Only) + * | | |0 = PWMx_CH0 level-detect brake state is released. + * | | |1 = PWMx_CH0 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * |[25] |BRKLSTS1 |Level-detect Brake Status of PWMx_CH1 (Read Only) + * | | |0 = PWMx_CH1 level-detect brake state is released. + * | | |1 = PWMx_CH1 at level-detect brake state. + * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. + * @var TIMER_T::PWMTRGCTL + * Offset: 0x90 Timer PWM Trigger Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |TRGSEL |PWM Counter Event Source Select to Trigger Conversion + * | | |In Timer0 ~ Timer3, + * | | |000 = Trigger conversion at zero point (ZIF). + * | | |001 = Trigger conversion at period point (PIF). + * | | |010 = Trigger conversion at zero or period point (ZIF or PIF). + * | | |011 = Trigger conversion at compare up count point (CMPUIF). + * | | |100 = Trigger conversion at compare down count point (CMPDIF). + * | | |In Timer4 and Timer5, + * | | |001 = Trigger conversion at period point (PIF). + * | | |011 = Trigger conversion at compare up count point (CMPUIF). + * | | |101 = Trigger conversion at period or compare up count point (PIF or CMPUIF). + * | | |Others = Reserved. + * |[7] |TRGEADC |PWM Counter Event Trigger EADC Conversion Enable Bit + * | | |0 = PWM counter event trigger EADC conversion Disabled. + * | | |1 = PWM counter event trigger EADC conversion Enabled. + * | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[2:0]) to select PWM trigger conversion source. + * |[9] |TRGPDMA |PWM Counter Event Trigger PDMA Conversion Enable Bit + * | | |0 = PWM counter event trigger PDMA conversion Disabled. + * | | |1 = PWM counter event trigger PDMA conversion Enabled. + * | | |Note: Set TRGSEL (TIMERx_PWMTRGCTL[2:0]) to select PWM trigger conversion source. + * @var TIMER_T::PWMSCTL + * Offset: 0x94 Timer PWM Synchronous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |SYNCMODE |PWM Synchronous Mode Enable Select + * | | |00 = PWM synchronous function Disabled. + * | | |01 = PWM synchronous counter start function Enabled. + * | | |10 = Reserved. + * | | |11 = PWM synchronous counter clear function Enabled. + * |[8] |SYNCSRC |PWM Synchronous Counter Start/Clear Source Select + * | | |0 = Counter synchronous start/clear by trigger TIMER0_PWMSTRG STRGEN. + * | | |1 = Counter synchronous start/clear by trigger TIMER2_PWMSTRG STRGEN. + * | | |Note1: If TIMER0/1/2/3 PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8], TIMER1_PWMSCTL[8], TIMER2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be 0. + * | | |Note2: If TIMER0/1/ PWM counter synchronous source are from TIMER0, TIMER0_PWMSCTL[8] and TIMER1_PWMSCTL[8] should be set 0, and TIMER2/3/ PWM counter synchronous source are from TIMER2, TIME2_PWMSCTL[8] and TIMER3_PWMSCTL[8] should be set 1. + * @var TIMER_T::PWMSTRG + * Offset: 0x98 Timer PWM Synchronous Trigger Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STRGEN |PWM Counter Synchronous Trigger Enable Bit (Write Only) + * | | |PMW counter synchronous function is used to make selected PWM channels (include TIMER0/1/2/3 PWM, TIMER0/1 PWM and TIMER2/3 PWM) start counting or clear counter at the same time according to TIMERx_PWMSCTL setting. + * | | |Note: This bit is only available in TIMER0 and TIMER2. + * @var TIMER_T::PWMSTATUS + * Offset: 0x9C Timer PWM Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CNTMAXF |PWM Counter Equal to 0xFFFF Flag + * | | |0 = The PWM counter value never reached its maximum value 0xFFFF. + * | | |1 = The PWM counter value has reached its maximum value. + * | | |Note: This bit is cleared by writing 1 to it. + * |[8] |WKF |PWM Wake-up Flag + * | | |0 = PWM interrupt wake-up has not occurred. + * | | |1 = PWM interrupt wake-up has occurred. + * | | |Note1: This bit is only available in Timer4 and Timer5. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[16] |EADCTRGF |Trigger EADC Start Conversion Flag + * | | |0 = PWM counter event trigger EADC start conversion is not occurred. + * | | |1 = PWM counter event trigger EADC start conversion has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[19] |PDMATRGF |Trigger PDMA Start Conversion Flag + * | | |0 = PWM counter event trigger PDMA start conversion is not occurred. + * | | |1 = PWM counter event trigger PDMA start conversion has occurred. + * | | |Note1: This bit is only available in Timer4 and Timer5. + * | | |Note2: This bit is cleared by writing 1 to it. + * @var TIMER_T::PWMPBUF + * Offset: 0xA0 Timer PWM Period Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |PBUF |PWM Period Buffer Register (Read Only) + * | | |Used as PERIOD active register. + * @var TIMER_T::PWMCMPBUF + * Offset: 0xA4 Timer PWM Comparator Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |CMPBUF |PWM Comparator Buffer Register (Read Only) + * | | |Used as CMP active register. + */ + __IO uint32_t CTL; /*!< [0x0000] Timer Control Register */ + __IO uint32_t CMP; /*!< [0x0004] Timer Comparator Register */ + __IO uint32_t INTSTS; /*!< [0x0008] Timer Interrupt Status Register */ + __IO uint32_t CNT; /*!< [0x000c] Timer Data Register */ + __I uint32_t CAP; /*!< [0x0010] Timer Capture Data Register */ + __IO uint32_t EXTCTL; /*!< [0x0014] Timer External Control Register */ + __IO uint32_t EINTSTS; /*!< [0x0018] Timer External Interrupt Status Register */ + __IO uint32_t TRGCTL; /*!< [0x001c] Timer Trigger Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0020] Timer Alternative Control Register */ + __I uint32_t RESERVE0[7]; + __IO uint32_t PWMCTL; /*!< [0x0040] Timer PWM Control Register */ + __IO uint32_t PWMCLKSRC; /*!< [0x0044] Timer PWM Counter Clock Source Register */ + __IO uint32_t PWMCLKPSC; /*!< [0x0048] Timer PWM Counter Clock Pre-scale Register */ + __IO uint32_t PWMCNTCLR; /*!< [0x004c] Timer PWM Clear Counter Register */ + __IO uint32_t PWMPERIOD; /*!< [0x0050] Timer PWM Period Register */ + __IO uint32_t PWMCMPDAT; /*!< [0x0054] Timer PWM Comparator Register */ + __IO uint32_t PWMDTCTL; /*!< [0x0058] Timer PWM Dead-Time Control Register */ + __I uint32_t PWMCNT; /*!< [0x005c] Timer PWM Counter Register */ + __IO uint32_t PWMMSKEN; /*!< [0x0060] Timer PWM Output Mask Enable Register */ + __IO uint32_t PWMMSK; /*!< [0x0064] Timer PWM Output Mask Data Control Register */ + __IO uint32_t PWMBNF; /*!< [0x0068] Timer PWM Brake Pin Noise Filter Register */ + __IO uint32_t PWMFAILBRK; /*!< [0x006c] Timer PWM System Fail Brake Control Register */ + __IO uint32_t PWMBRKCTL; /*!< [0x0070] Timer PWM Brake Control Register */ + __IO uint32_t PWMPOLCTL; /*!< [0x0074] Timer PWM Pin Output Polar Control Register */ + __IO uint32_t PWMPOEN; /*!< [0x0078] Timer PWM Pin Output Enable Register */ + __O uint32_t PWMSWBRK; /*!< [0x007c] Timer PWM Software Trigger Brake Control Register */ + __IO uint32_t PWMINTEN0; /*!< [0x0080] Timer PWM Interrupt Enable Register 0 */ + __IO uint32_t PWMINTEN1; /*!< [0x0084] Timer PWM Interrupt Enable Register 1 */ + __IO uint32_t PWMINTSTS0; /*!< [0x0088] Timer PWM Interrupt Status Register 0 */ + __IO uint32_t PWMINTSTS1; /*!< [0x008c] Timer PWM Interrupt Status Register 1 */ + __IO uint32_t PWMTRGCTL; /*!< [0x0090] Timer PWM Trigger Control Register */ + __IO uint32_t PWMSCTL; /*!< [0x0094] Timer PWM Synchronous Control Register */ + __O uint32_t PWMSTRG; /*!< [0x0098] Timer PWM Synchronous Trigger Register */ + __IO uint32_t PWMSTATUS; /*!< [0x009c] Timer PWM Status Register */ + __I uint32_t PWMPBUF; /*!< [0x00a0] Timer PWM Period Buffer Register */ + __I uint32_t PWMCMPBUF; /*!< [0x00a4] Timer PWM Comparator Buffer Register */ + +} TIMER_T; + +/** + @addtogroup TIMER_CONST TIMER Bit Field Definition + Constant Definitions for TIMER Controller + @{ +*/ + +#define TIMER_CTL_PSC_Pos (0) /*!< TIMER_T::CTL: PSC Position */ +#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER_T::CTL: PSC Mask */ + +#define TIMER_CTL_FUNCSEL_Pos (15) /*!< TIMER_T::CTL: FUNCSEL Position */ +#define TIMER_CTL_FUNCSEL_Msk (0x1ul << TIMER_CTL_FUNCSEL_Pos) /*!< TIMER_T::CTL: FUNCSEL Mask */ + +#define TIMER_CTL_INTRGEN_Pos (19) /*!< TIMER_T::CTL: INTRGEN Position */ +#define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) /*!< TIMER_T::CTL: INTRGEN Mask */ + +#define TIMER_CTL_PERIOSEL_Pos (20) /*!< TIMER_T::CTL: PERIOSEL Position */ +#define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) /*!< TIMER_T::CTL: PERIOSEL Mask */ + +#define TIMER_CTL_TGLPINSEL_Pos (21) /*!< TIMER_T::CTL: TGLPINSEL Position */ +#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) /*!< TIMER_T::CTL: TGLPINSEL Mask */ + +#define TIMER_CTL_CAPSRC_Pos (22) /*!< TIMER_T::CTL: CAPSRC Position */ +#define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) /*!< TIMER_T::CTL: CAPSRC Mask */ + +#define TIMER_CTL_WKEN_Pos (23) /*!< TIMER_T::CTL: WKEN Position */ +#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER_T::CTL: WKEN Mask */ + +#define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER_T::CTL: EXTCNTEN Position */ +#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER_T::CTL: EXTCNTEN Mask */ + +#define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER_T::CTL: ACTSTS Position */ +#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER_T::CTL: ACTSTS Mask */ + +#define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER_T::CTL: OPMODE Position */ +#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER_T::CTL: OPMODE Mask */ + +#define TIMER_CTL_INTEN_Pos (29) /*!< TIMER_T::CTL: INTEN Position */ +#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER_T::CTL: INTEN Mask */ + +#define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER_T::CTL: CNTEN Position */ +#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER_T::CTL: CNTEN Mask */ + +#define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER_T::CTL: ICEDEBUG Position */ +#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER_T::CTL: ICEDEBUG Mask */ + +#define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER_T::CMP: CMPDAT Position */ +#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER_T::CMP: CMPDAT Mask */ + +#define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER_T::INTSTS: TIF Position */ +#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER_T::INTSTS: TIF Mask */ + +#define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER_T::INTSTS: TWKF Position */ +#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER_T::INTSTS: TWKF Mask */ + +#define TIMER_CNT_CNT_Pos (0) /*!< TIMER_T::CNT: CNT Position */ +#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) /*!< TIMER_T::CNT: CNT Mask */ + +#define TIMER_CNT_RSTACT_Pos (31) /*!< TIMER_T::CNT: RSTACT Position */ +#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) /*!< TIMER_T::CNT: RSTACT Mask */ + +#define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER_T::CAP: CAPDAT Position */ +#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER_T::CAP: CAPDAT Mask */ + +#define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER_T::EXTCTL: CNTPHASE Position */ +#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER_T::EXTCTL: CNTPHASE Mask */ + +#define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER_T::EXTCTL: CAPEN Position */ +#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER_T::EXTCTL: CAPEN Mask */ + +#define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER_T::EXTCTL: CAPFUNCS Position */ +#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER_T::EXTCTL: CAPFUNCS Mask */ + +#define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER_T::EXTCTL: CAPIEN Position */ +#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER_T::EXTCTL: CAPIEN Mask */ + +#define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER_T::EXTCTL: CAPDBEN Position */ +#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER_T::EXTCTL: CAPDBEN Mask */ + +#define TIMER_EXTCTL_CNTDBEN_Pos (7) /*!< TIMER_T::EXTCTL: CNTDBEN Position */ +#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) /*!< TIMER_T::EXTCTL: CNTDBEN Mask */ + +#define TIMER_EXTCTL_INTERCAPSEL_Pos (8) /*!< TIMER_T::EXTCTL: INTERCAPSEL Position */ +#define TIMER_EXTCTL_INTERCAPSEL_Msk (0x7ul << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< TIMER_T::EXTCTL: INTERCAPSEL Mask */ + +#define TIMER_EXTCTL_CAPEDGE_Pos (12) /*!< TIMER_T::EXTCTL: CAPEDGE Position */ +#define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER_T::EXTCTL: CAPEDGE Mask */ + +#define TIMER_EXTCTL_ECNTSSEL_Pos (16) /*!< TIMER_T::EXTCTL: ECNTSSEL Position */ +#define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) /*!< TIMER_T::EXTCTL: ECNTSSEL Mask */ + +#define TIMER_EXTCTL_CAPDIVSCL_Pos (28) /*!< TIMER_T::EXTCTL: CAPDIVSCL Position */ +#define TIMER_EXTCTL_CAPDIVSCL_Msk (0xful << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< TIMER_T::EXTCTL: CAPDIVSCL Mask */ + +#define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER_T::EINTSTS: CAPIF Position */ +#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER_T::EINTSTS: CAPIF Mask */ + +#define TIMER_TRGCTL_TRGSSEL_Pos (0) /*!< TIMER_T::TRGCTL: TRGSSEL Position */ +#define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) /*!< TIMER_T::TRGCTL: TRGSSEL Mask */ + +#define TIMER_TRGCTL_TRGPWM_Pos (1) /*!< TIMER_T::TRGCTL: TRGPWM Position */ +#define TIMER_TRGCTL_TRGPWM_Msk (0x1ul << TIMER_TRGCTL_TRGPWM_Pos) /*!< TIMER_T::TRGCTL: TRGPWM Mask */ + +#define TIMER_TRGCTL_TRGEADC_Pos (2) /*!< TIMER_T::TRGCTL: TRGEADC Position */ +#define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) /*!< TIMER_T::TRGCTL: TRGEADC Mask */ + +#define TIMER_TRGCTL_TRGDAC_Pos (3) /*!< TIMER_T::TRGCTL: TRGDAC Position */ +#define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) /*!< TIMER_T::TRGCTL: TRGDAC Mask */ + +#define TIMER_TRGCTL_TRGPDMA_Pos (4) /*!< TIMER_T::TRGCTL: TRGPDMA Position */ +#define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) /*!< TIMER_T::TRGCTL: TRGPDMA Mask */ + +#define TIMER_ALTCTL_FUNCSEL_Pos (0) /*!< TIMER_T::ALTCTL: FUNCSEL Position */ +#define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) /*!< TIMER_T::ALTCTL: FUNCSEL Mask */ + +#define TIMER_PWMCTL_CNTEN_Pos (0) /*!< TIMER_T::PWMCTL: CNTEN Position */ +#define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) /*!< TIMER_T::PWMCTL: CNTEN Mask */ + +#define TIMER_PWMCTL_CNTTYPE_Pos (1) /*!< TIMER_T::PWMCTL: CNTTYPE Position */ +#define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) /*!< TIMER_T::PWMCTL: CNTTYPE Mask */ + +#define TIMER_PWMCTL_CNTMODE_Pos (3) /*!< TIMER_T::PWMCTL: CNTMODE Position */ +#define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) /*!< TIMER_T::PWMCTL: CNTMODE Mask */ + +#define TIMER_PWMCTL_CTRLD_Pos (8) /*!< TIMER_T::PWMCTL: CTRLD Position */ +#define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) /*!< TIMER_T::PWMCTL: CTRLD Mask */ + +#define TIMER_PWMCTL_IMMLDEN_Pos (9) /*!< TIMER_T::PWMCTL: IMMLDEN Position */ +#define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) /*!< TIMER_T::PWMCTL: IMMLDEN Mask */ + +#define TIMER_PWMCTL_WKEN_Pos (12) /*!< TIMER_T::PWMCTL: WKEN Position */ +#define TIMER_PWMCTL_WKEN_Msk (0x1ul << TIMER_PWMCTL_WKEN_Pos) /*!< TIMER_T::PWMCTL: WKEN Mask */ + +#define TIMER_PWMCTL_OUTMODE_Pos (16) /*!< TIMER_T::PWMCTL: OUTMODE Position */ +#define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) /*!< TIMER_T::PWMCTL: OUTMODE Mask */ + +#define TIMER_PWMCTL_DBGHALT_Pos (30) /*!< TIMER_T::PWMCTL: DBGHALT Position */ +#define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) /*!< TIMER_T::PWMCTL: DBGHALT Mask */ + +#define TIMER_PWMCTL_DBGTRIOFF_Pos (31) /*!< TIMER_T::PWMCTL: DBGTRIOFF Position */ +#define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) /*!< TIMER_T::PWMCTL: DBGTRIOFF Mask */ + +#define TIMER_PWMCLKSRC_CLKSRC_Pos (0) /*!< TIMER_T::PWMCLKSRC: CLKSRC Position */ +#define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) /*!< TIMER_T::PWMCLKSRC: CLKSRC Mask */ + +#define TIMER_PWMCLKPSC_CLKPSC_Pos (0) /*!< TIMER_T::PWMCLKPSC: CLKPSC Position */ +#define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) /*!< TIMER_T::PWMCLKPSC: CLKPSC Mask */ + +#define TIMER_PWMCNTCLR_CNTCLR_Pos (0) /*!< TIMER_T::PWMCNTCLR: CNTCLR Position */ +#define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) /*!< TIMER_T::PWMCNTCLR: CNTCLR Mask */ + +#define TIMER_PWMPERIOD_PERIOD_Pos (0) /*!< TIMER_T::PWMPERIOD: PERIOD Position */ +#define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) /*!< TIMER_T::PWMPERIOD: PERIOD Mask */ + +#define TIMER_PWMCMPDAT_CMP_Pos (0) /*!< TIMER_T::PWMCMPDAT: CMP Position */ +#define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) /*!< TIMER_T::PWMCMPDAT: CMP Mask */ + +#define TIMER_PWMDTCTL_DTCNT_Pos (0) /*!< TIMER_T::PWMDTCTL: DTCNT Position */ +#define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) /*!< TIMER_T::PWMDTCTL: DTCNT Mask */ + +#define TIMER_PWMDTCTL_DTEN_Pos (16) /*!< TIMER_T::PWMDTCTL: DTEN Position */ +#define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) /*!< TIMER_T::PWMDTCTL: DTEN Mask */ + +#define TIMER_PWMDTCTL_DTCKSEL_Pos (24) /*!< TIMER_T::PWMDTCTL: DTCKSEL Position */ +#define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) /*!< TIMER_T::PWMDTCTL: DTCKSEL Mask */ + +#define TIMER_PWMCNT_CNT_Pos (0) /*!< TIMER_T::PWMCNT: CNT Position */ +#define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) /*!< TIMER_T::PWMCNT: CNT Mask */ + +#define TIMER_PWMCNT_DIRF_Pos (16) /*!< TIMER_T::PWMCNT: DIRF Position */ +#define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) /*!< TIMER_T::PWMCNT: DIRF Mask */ + +#define TIMER_PWMMSKEN_MSKEN0_Pos (0) /*!< TIMER_T::PWMMSKEN: MSKEN0 Position */ +#define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN0 Mask */ + +#define TIMER_PWMMSKEN_MSKEN1_Pos (1) /*!< TIMER_T::PWMMSKEN: MSKEN1 Position */ +#define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) /*!< TIMER_T::PWMMSKEN: MSKEN1 Mask */ + +#define TIMER_PWMMSK_MSKDAT0_Pos (0) /*!< TIMER_T::PWMMSK: MSKDAT0 Position */ +#define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) /*!< TIMER_T::PWMMSK: MSKDAT0 Mask */ + +#define TIMER_PWMMSK_MSKDAT1_Pos (1) /*!< TIMER_T::PWMMSK: MSKDAT1 Position */ +#define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) /*!< TIMER_T::PWMMSK: MSKDAT1 Mask */ + +#define TIMER_PWMBNF_BRKNFEN_Pos (0) /*!< TIMER_T::PWMBNF: BRKNFEN Position */ +#define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) /*!< TIMER_T::PWMBNF: BRKNFEN Mask */ + +#define TIMER_PWMBNF_BRKNFSEL_Pos (1) /*!< TIMER_T::PWMBNF: BRKNFSEL Position */ +#define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) /*!< TIMER_T::PWMBNF: BRKNFSEL Mask */ + +#define TIMER_PWMBNF_BRKFCNT_Pos (4) /*!< TIMER_T::PWMBNF: BRKFCNT Position */ +#define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) /*!< TIMER_T::PWMBNF: BRKFCNT Mask */ + +#define TIMER_PWMBNF_BRKPINV_Pos (7) /*!< TIMER_T::PWMBNF: BRKPINV Position */ +#define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) /*!< TIMER_T::PWMBNF: BRKPINV Mask */ + +#define TIMER_PWMBNF_BKPINSRC_Pos (16) /*!< TIMER_T::PWMBNF: BKPINSRC Position */ +#define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) /*!< TIMER_T::PWMBNF: BKPINSRC Mask */ + +#define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Position */ +#define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CSSBRKEN Mask */ + +#define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Position */ +#define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: BODBRKEN Mask */ + +#define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Position */ +#define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: RAMBRKEN Mask */ + +#define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Position */ +#define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) /*!< TIMER_T::PWMFAILBRK: CORBRKEN Mask */ + +#define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Position */ +#define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0EBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Position */ +#define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1EBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Position */ +#define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPEEN Mask */ + +#define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Position */ +#define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSEBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Position */ +#define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO0LBEN Mask */ + +#define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Position */ +#define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) /*!< TIMER_T::PWMBRKCTL: CPO1LBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Position */ +#define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKPLEN Mask */ + +#define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Position */ +#define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) /*!< TIMER_T::PWMBRKCTL: SYSLBEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Position */ +#define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAEVEN Mask */ + +#define TIMER_PWMBRKCTL_BRKAODD_Pos (18) /*!< TIMER_T::PWMBRKCTL: BRKAODD Position */ +#define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) /*!< TIMER_T::PWMBRKCTL: BRKAODD Mask */ + +#define TIMER_PWMPOLCTL_PINV0_Pos (0) /*!< TIMER_T::PWMPOLCTL: PINV0 Position */ +#define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) /*!< TIMER_T::PWMPOLCTL: PINV0 Mask */ + +#define TIMER_PWMPOLCTL_PINV1_Pos (1) /*!< TIMER_T::PWMPOLCTL: PINV1 Position */ +#define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) /*!< TIMER_T::PWMPOLCTL: PINV1 Mask */ + +#define TIMER_PWMPOEN_POEN0_Pos (0) /*!< TIMER_T::PWMPOEN: POEN0 Position */ +#define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) /*!< TIMER_T::PWMPOEN: POEN0 Mask */ + +#define TIMER_PWMPOEN_POEN1_Pos (1) /*!< TIMER_T::PWMPOEN: POEN1 Position */ +#define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) /*!< TIMER_T::PWMPOEN: POEN1 Mask */ + +#define TIMER_PWMPOEN_POSEL_Pos (8) /*!< TIMER_T::PWMPOEN: POSEL Position */ +#define TIMER_PWMPOEN_POSEL_Msk (0x1ul << TIMER_PWMPOEN_POSEL_Pos) /*!< TIMER_T::PWMPOEN: POSEL Mask */ + +#define TIMER_PWMSWBRK_BRKETRG_Pos (0) /*!< TIMER_T::PWMSWBRK: BRKETRG Position */ +#define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKETRG Mask */ + +#define TIMER_PWMSWBRK_BRKLTRG_Pos (8) /*!< TIMER_T::PWMSWBRK: BRKLTRG Position */ +#define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) /*!< TIMER_T::PWMSWBRK: BRKLTRG Mask */ + +#define TIMER_PWMINTEN0_ZIEN_Pos (0) /*!< TIMER_T::PWMINTEN0: ZIEN Position */ +#define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) /*!< TIMER_T::PWMINTEN0: ZIEN Mask */ + +#define TIMER_PWMINTEN0_PIEN_Pos (1) /*!< TIMER_T::PWMINTEN0: PIEN Position */ +#define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) /*!< TIMER_T::PWMINTEN0: PIEN Mask */ + +#define TIMER_PWMINTEN0_CMPUIEN_Pos (2) /*!< TIMER_T::PWMINTEN0: CMPUIEN Position */ +#define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPUIEN Mask */ + +#define TIMER_PWMINTEN0_CMPDIEN_Pos (3) /*!< TIMER_T::PWMINTEN0: CMPDIEN Position */ +#define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) /*!< TIMER_T::PWMINTEN0: CMPDIEN Mask */ + +#define TIMER_PWMINTEN1_BRKEIEN_Pos (0) /*!< TIMER_T::PWMINTEN1: BRKEIEN Position */ +#define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKEIEN Mask */ + +#define TIMER_PWMINTEN1_BRKLIEN_Pos (8) /*!< TIMER_T::PWMINTEN1: BRKLIEN Position */ +#define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) /*!< TIMER_T::PWMINTEN1: BRKLIEN Mask */ + +#define TIMER_PWMINTSTS0_ZIF_Pos (0) /*!< TIMER_T::PWMINTSTS0: ZIF Position */ +#define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) /*!< TIMER_T::PWMINTSTS0: ZIF Mask */ + +#define TIMER_PWMINTSTS0_PIF_Pos (1) /*!< TIMER_T::PWMINTSTS0: PIF Position */ +#define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) /*!< TIMER_T::PWMINTSTS0: PIF Mask */ + +#define TIMER_PWMINTSTS0_CMPUIF_Pos (2) /*!< TIMER_T::PWMINTSTS0: CMPUIF Position */ +#define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPUIF Mask */ + +#define TIMER_PWMINTSTS0_CMPDIF_Pos (3) /*!< TIMER_T::PWMINTSTS0: CMPDIF Position */ +#define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) /*!< TIMER_T::PWMINTSTS0: CMPDIF Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Position */ +#define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Position */ +#define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKEIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Position */ +#define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Position */ +#define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLIF1 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Position */ +#define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Position */ +#define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKESTS1 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS0 Mask */ + +#define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Position */ +#define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) /*!< TIMER_T::PWMINTSTS1: BRKLSTS1 Mask */ + +#define TIMER_PWMTRGCTL_TRGSEL_Pos (0) /*!< TIMER_T::PWMTRGCTL: TRGSEL Position */ +#define TIMER_PWMTRGCTL_TRGSEL_Msk (0x7ul << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< TIMER_T::PWMTRGCTL: TRGSEL Mask */ + +#define TIMER_PWMTRGCTL_TRGEADC_Pos (7) /*!< TIMER_T::PWMTRGCTL: TRGEADC Position */ +#define TIMER_PWMTRGCTL_TRGEADC_Msk (0x1ul << TIMER_PWMTRGCTL_TRGEADC_Pos) /*!< TIMER_T::PWMTRGCTL: TRGEADC Mask */ + +#define TIMER_PWMTRGCTL_TRGPDMA_Pos (9) /*!< TIMER_T::PWMTRGCTL: TRGPDMA Position */ +#define TIMER_PWMTRGCTL_TRGPDMA_Msk (0x1ul << TIMER_PWMTRGCTL_TRGPDMA_Pos) /*!< TIMER_T::PWMTRGCTL: TRGPDMA Mask */ + +#define TIMER_PWMSCTL_SYNCMODE_Pos (0) /*!< TIMER_T::PWMSCTL: SYNCMODE Position */ +#define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) /*!< TIMER_T::PWMSCTL: SYNCMODE Mask */ + +#define TIMER_PWMSCTL_SYNCSRC_Pos (8) /*!< TIMER_T::PWMSCTL: SYNCSRC Position */ +#define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) /*!< TIMER_T::PWMSCTL: SYNCSRC Mask */ + +#define TIMER_PWMSTRG_STRGEN_Pos (0) /*!< TIMER_T::PWMSTRG: STRGEN Position */ +#define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) /*!< TIMER_T::PWMSTRG: STRGEN Mask */ + +#define TIMER_PWMSTATUS_CNTMAXF_Pos (0) /*!< TIMER_T::PWMSTATUS: CNTMAXF Position */ +#define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) /*!< TIMER_T::PWMSTATUS: CNTMAXF Mask */ + +#define TIMER_PWMSTATUS_WKF_Pos (8) /*!< TIMER_T::PWMSTATUS: WKF Position */ +#define TIMER_PWMSTATUS_WKF_Msk (0x1ul << TIMER_PWMSTATUS_WKF_Pos) /*!< TIMER_T::PWMSTATUS: WKF Mask */ + +#define TIMER_PWMSTATUS_EADCTRGF_Pos (16) /*!< TIMER_T::PWMSTATUS: EADCTRGF Position */ +#define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) /*!< TIMER_T::PWMSTATUS: EADCTRGF Mask */ + +#define TIMER_PWMSTATUS_PDMATRGF_Pos (18) /*!< TIMER_T::PWMSTATUS: PDMATRGF Position */ +#define TIMER_PWMSTATUS_PDMATRGF_Msk (0x1ul << TIMER_PWMSTATUS_PDMATRGF_Pos) /*!< TIMER_T::PWMSTATUS: PDMATRGF Mask */ + +#define TIMER_PWMPBUF_PBUF_Pos (0) /*!< TIMER_T::PWMPBUF: PBUF Position */ +#define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) /*!< TIMER_T::PWMPBUF: PBUF Mask */ + +#define TIMER_PWMCMPBUF_CMPBUF_Pos (0) /*!< TIMER_T::PWMCMPBUF: CMPBUF Position */ +#define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) /*!< TIMER_T::PWMCMPBUF: CMPBUF Mask */ + +/**@}*/ /* TIMER_CONST */ +/**@}*/ /* end of TIMER register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __TIMER_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/trng_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/trng_reg.h new file mode 100644 index 0000000000..e93e99fa50 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/trng_reg.h @@ -0,0 +1,156 @@ +/**************************************************************************//** + * @file trng_reg.h + * @version V1.00 + * @brief TRNG register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TRNG_REG_H__ +#define __TRNG_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- True Random Number Generator -------------------------*/ +/** + @addtogroup TRNG True Random Number Generator(TRNG) + Memory Mapped Structure for TRNG Controller + @{ +*/ + +typedef struct +{ + + +/** + * @var TRNG_T::CTL + * Offset: 0x00 TRNG Control Register and Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TRNGEN |Random Number Generator Enable Bit + * | | |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became to 1. + * | | |0 = TRNG Disabled. + * | | |1 = TRNG Enabled. + * | | |Note: TRNGEN is an enable bit of digital part + * | | |When TRNG is not required to generate random number, TRNGEN bit and ACT (TRNG_ACT[7]) bit should be set to 0 to reduce power consumption. + * |[1] |DVIF |Data Valid (Read Only) + * | | |0 = Data is not valid. Reading from RNGD returns 0x00000000. + * | | |1 = Data is valid. A valid random number can be read form RNGD. + * | | |This bit is cleared to u20180u2019 by read TRNG_DATA. + * |[5:2] |CLKPSC |Clock Prescaler + * | | |The CLKP is the peripheral clock frequency range for the selected value , the CLKP must higher than or equal to the actual peripheral clock frequency (for correct random bit generation) + * | | |To change the CLKP contents, first set TRNGEN bit to 0 and then change CLKP; finally, set TRNGEN bit to 1 to re-enable the TRNG module. + * | | |0000 = 80 ~ 100 MHz. + * | | |0001 = 60 ~ 80 MHz. + * | | |0010 = 50 ~60 MHz. + * | | |0011 = 40 ~50 MHz. + * | | |0100 = 30 ~40 MHz. + * | | |0101 = 25 ~30 MHz. + * | | |0110 = 20 ~25 MHz. + * | | |0111 = 15 ~20 MHz. + * | | |1000 = 12 ~15 MHz. + * | | |1001 = 9 ~12 MHz. + * | | |1010 = 7 ~9 MHz. + * | | |1011 = 6 ~7 MHz. + * | | |1100 = 5 ~6 MHz. + * | | |1101 = 4 ~5 MHz. + * | | |1111 = Reserved. + * |[6] |DVIEN |Data Valid Interrupt Enable Bit + * | | |0 = Interrupt Disabled. + * | | |1 = Interrupt Enabled. + * |[7] |READY |Random Number Generator Ready (Read Only) + * | | |After ACT (TRNG_ACT[7]) bit is set, the READY bit become to 1 after a delay of 90us~120us. + * | | |0 = RNG is not ready or was not activated. + * | | |1 = RNG is ready to be enabled.. + * |[8] |SEEDGEN |Random Number Seed Generator Enable Bit [for TRNG+PRNG] + * | | |This bit can be set to 1 only after ACT (TRNG_ACT[7]) bit was set to 1 and READY (TRNG_CTL[7]) bit became to 1. + * | | |0 = Seed generator disabled. + * | | |1 = Seed generator enabled. + * | | |Note: If users want to execute TRNG+PRNG mode, they should set SEEDGEN to 1 + * | | |When SEEDGEN was set to 1, users canu2019t read the data from TRNG Data Register. + * |[9] |SEEDRDY |Random Number Seed Ready (Read Only) [for TRNG+PRNG] + * | | |0 = Seed is not ready or was not activated. + * | | |1 = Seed is ready for PRNG. + * | | |Note 1:This bit is cleared to u20180u2019 when SEEDGEN is 1. + * | | |Note 2: If SEEDRDY become to 1, then SEEDGEN will be cleared to 0. + * |[31:10] |Reversed |Reversed + * @var TRNG_T::DATA + * Offset: 0x04 TRNG Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DATA |Random Number Generator Data (Read Only) + * | | |The DATA store the random number generated by TRNG and can be read only once. + * @var TRNG_T::ACT + * Offset: 0x0C TRNG Activation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |VER |TRNG Version + * | | |TRNG version number is dependent on TRNG module. + * | | |0x02:(Current Version Number) + * |[7] |ACT |Random Number Generator Activation + * | | |After enabling the ACT bit, it will active the TRNG module and wait the READY (TRNG_CTL[7]) bit to become 1. + * | | |0 = TRNG inactive. + * | | |1 = TRNG active. + * | | |Note: ACT is an enable bit of analog part + * | | |When TRNG is not required to generate random number, TRNGEN (TRNG_CTL[0]) bit and ACT bit should be set to 0 to reduce power consumption. + */ + __IO uint32_t CTL; /*!< [0x0000] TRNG Control Register and Status */ + __I uint32_t DATA; /*!< [0x0004] TRNG Data Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t ACT; /*!< [0x000c] TRNG Activation Register */ + +} TRNG_T; + +/** + @addtogroup TRNG_CONST TRNG Bit Field Definition + Constant Definitions for TRNG Controller + @{ +*/ + +#define TRNG_CTL_TRNGEN_Pos (0) /*!< TRNG_T::CTL: TRNGEN Position */ +#define TRNG_CTL_TRNGEN_Msk (0x1ul << TRNG_CTL_TRNGEN_Pos) /*!< TRNG_T::CTL: TRNGEN Mask */ + +#define TRNG_CTL_DVIF_Pos (1) /*!< TRNG_T::CTL: DVIF Position */ +#define TRNG_CTL_DVIF_Msk (0x1ul << TRNG_CTL_DVIF_Pos) /*!< TRNG_T::CTL: DVIF Mask */ + +#define TRNG_CTL_CLKPSC_Pos (2) /*!< TRNG_T::CTL: CLKPSC Position */ +#define TRNG_CTL_CLKPSC_Msk (0xful << TRNG_CTL_CLKPSC_Pos) /*!< TRNG_T::CTL: CLKPSC Mask */ + +#define TRNG_CTL_DVIEN_Pos (6) /*!< TRNG_T::CTL: DVIEN Position */ +#define TRNG_CTL_DVIEN_Msk (0x1ul << TRNG_CTL_DVIEN_Pos) /*!< TRNG_T::CTL: DVIEN Mask */ + +#define TRNG_CTL_READY_Pos (7) /*!< TRNG_T::CTL: READY Position */ +#define TRNG_CTL_READY_Msk (0x1ul << TRNG_CTL_READY_Pos) /*!< TRNG_T::CTL: READY Mask */ + +#define TRNG_CTL_SEEDGEN_Pos (8) /*!< TRNG_T::CTL: SEEDGEN Position */ +#define TRNG_CTL_SEEDGEN_Msk (0x1ul << TRNG_CTL_SEEDGEN_Pos) /*!< TRNG_T::CTL: SEEDGEN Mask */ + +#define TRNG_CTL_SEEDRDY_Pos (9) /*!< TRNG_T::CTL: SEEDRDY Position */ +#define TRNG_CTL_SEEDRDY_Msk (0x1ul << TRNG_CTL_SEEDRDY_Pos) /*!< TRNG_T::CTL: SEEDRDY Mask */ + +#define TRNG_CTL_Reversed_Pos (10) /*!< TRNG_T::CTL: Reversed Position */ +#define TRNG_CTL_Reversed_Msk (0x3ffffful << TRNG_CTL_Reversed_Pos) /*!< TRNG_T::CTL: Reversed Mask */ + +#define TRNG_DATA_DATA_Pos (0) /*!< TRNG_T::DATA: DATA Position */ +#define TRNG_DATA_DATA_Msk (0xfful << TRNG_DATA_DATA_Pos) /*!< TRNG_T::DATA: DATA Mask */ + +#define TRNG_ACT_VER_Pos (0) /*!< TRNG_T::ACT: VER Position */ +#define TRNG_ACT_VER_Msk (0x7ful << TRNG_ACT_VER_Pos) /*!< TRNG_T::ACT: VER Mask */ + +#define TRNG_ACT_ACT_Pos (7) /*!< TRNG_T::ACT: ACT Position */ +#define TRNG_ACT_ACT_Msk (0x1ul << TRNG_ACT_ACT_Pos) /*!< TRNG_T::ACT: ACT Mask */ + +/**@}*/ /* TRNG_CONST */ +/**@}*/ /* end of TRNG register group */ + +/**@}*/ /* end of REGISTER group */ + + +#endif /* __TRNG_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/uart_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/uart_reg.h new file mode 100644 index 0000000000..e19082afb5 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/uart_reg.h @@ -0,0 +1,1276 @@ +/**************************************************************************//** + * @file uart_reg.h + * @version V1.00 + * @brief UART register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UART_REG_H__ +#define __UART_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/ +/** + @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART) + Memory Mapped Structure for UART Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var UART_T::DAT + * Offset: 0x00 UART Receive/Transmit Buffer Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |DAT |Data Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO. + * | | |The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD. + * | | |Read Operation: + * | | |By reading this register, the UART controller will return an 8-bit data received from receiver FIFO. + * |[8] |PARITY |Parity Bit Receive/Transmit Buffer + * | | |Write Operation: + * | | |By writing to this bit, the parity bit will be stored in transmitter FIFO. + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set, the UART controller will send out this bit follow the DAT (UART_DAT[7:0]) through the UART_TXD. + * | | |Read Operation: + * | | |If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are enabled, the parity bit can be read by this bit. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set. + * @var UART_T::INTEN + * Offset: 0x04 UART Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIEN |Receive Data Available Interrupt Enable Bit + * | | |0 = Receive data available interrupt Disabled. + * | | |1 = Receive data available interrupt Enabled. + * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Bit + * | | |0 = Transmit holding register empty interrupt Disabled. + * | | |1 = Transmit holding register empty interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive Line Status interrupt Disabled. + * | | |1 = Receive Line Status interrupt Enabled. + * |[3] |MODEMIEN |Modem Status Interrupt Enable Bit + * | | |0 = Modem status interrupt Disabled. + * | | |1 = Modem status interrupt Enabled. + * |[4] |RXTOIEN |RX Time-out Interrupt Enable Bit + * | | |0 = RX time-out interrupt Disabled. + * | | |1 = RX time-out interrupt Enabled. + * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Bit + * | | |0 = Buffer error interrupt Disabled. + * | | |1 = Buffer error interrupt Enabled. + * |[6] |WKIEN |Wake-up Interrupt Enable Bit + * | | |0 = Wake-up Interrupt Disabled. + * | | |1 = Wake-up Interrupt Enabled. + * |[8] |LINIEN |LIN Bus Interrupt Enable Bit + * | | |0 = LIN bus interrupt Disabled. + * | | |1 = LIN bus interrupt Enabled. + * | | |Note: This bit is used for LIN function mode. + * |[11] |TOCNTEN |Receive Buffer Time-out Counter Enable Bit + * | | |0 = Receive Buffer Time-out counter Disabled. + * | | |1 = Receive Buffer Time-out counter Enabled. + * |[12] |ATORTSEN |nRTS Auto-flow Control Enable Bit + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal. + * |[13] |ATOCTSEN |nCTS Auto-flow Control Enable Bit + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * | | |Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted). + * |[14] |TXPDMAEN |TX PDMA Enable Bit + * | | |This bit can enable or disable TX PDMA service. + * | | |0 = TX PDMA Disabled. + * | | |1 = TX PDMA Enabled. + * |[15] |RXPDMAEN |RX PDMA Enable Bit + * | | |This bit can enable or disable RX PDMA service. + * | | |0 = RX PDMA Disabled. + * | | |1 = RX PDMA Enabled. + * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. + * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stop. + * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing 1 to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. + * |[16] |SWBEIEN |Single-wire Bit Error Detection Interrupt Enable Bit + * | | |Set this bit, the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT(UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF(UART_INTSTS[16]) is set. + * | | |0 = Single-wire Bit Error Detect Interrupt Disabled. + * | | |1 = Single-wire Bit Error Detect Interrupt Enabled. + * | | |Note: This bit is valid when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. + * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[22] |TXENDIEN |Transmitter Empty Interrupt Enable Bit + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted). + * | | |0 = Transmitter empty interrupt Disabled. + * | | |1 = Transmitter empty interrupt Enabled. + * @var UART_T::FIFO + * Offset: 0x08 UART FIFO Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RXRST |RX Field Software Reset + * | | |When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the RX internal state machine and pointers. + * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note2: Before setting this bit, it should wait for the RXIDLE (UART_FIFOSTS[29]) be set. + * |[2] |TXRST |TX Field Software Reset + * | | |When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared. + * | | |0 = No effect. + * | | |1 = Reset the TX internal state machine and pointers. + * | | |Note1: This bit will automatically clear at least 3 UART peripheral clock cycles. + * | | |Note2: Before setting this bit, it should wait for the TXEMPTYF (UART_FIFOSTS[28]) be set. + * |[7:4] |RFITL |RX FIFO Interrupt Trigger Level + * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). + * | | |0000 = RX FIFO Interrupt Trigger Level is 1 byte. + * | | |0001 = RX FIFO Interrupt Trigger Level is 4 bytes. + * | | |0010 = RX FIFO Interrupt Trigger Level is 8 bytes. + * | | |0011 = RX FIFO Interrupt Trigger Level is 14 bytes. + * | | |Others = Reserved. + * |[8] |RXOFF |Receiver Disable Bit + * | | |The receiver is disabled or not (set 1 to disable receiver). + * | | |0 = Receiver Enabled. + * | | |1 = Receiver Disabled. + * | | |Note: This bit is used for RS-485 Normal Multi-drop mode. + * | | |It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed. + * |[19:16] |RTSTRGLV |nRTS Trigger Level for Auto-flow Control Use + * | | |0000 = nRTS Trigger Level is 1 byte. + * | | |0001 = nRTS Trigger Level is 4 bytes. + * | | |0010 = nRTS Trigger Level is 8 bytes. + * | | |0011 = nRTS Trigger Level is 14 bytes. + * | | |Others = Reserved. + * | | |Note: This field is used for auto nRTS flow control. + * @var UART_T::LINE + * Offset: 0x0C UART Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |WLS |Word Length Selection + * | | |This field sets UART word length. + * | | |00 = 5 bits. + * | | |01 = 6 bits. + * | | |10 = 7 bits. + * | | |11 = 8 bits. + * |[2] |NSB |Number of STOP Bit + * | | |0 = One STOP bit is generated in the transmitted data. + * | | |1 = When select 5-bit word length, 1.5 STOP bit is generated in the transmitted data. + * | | |When select 6-, 7- and 8-bit word length, 2 STOP bit is generated in the transmitted data. + * |[3] |PBE |Parity Bit Enable Bit + * | | |0 = Parity bit generated Disabled. + * | | |1 = Parity bit generated Enabled. + * | | |Note: Parity bit is generated on each outgoing character and is checked on each incoming data. + * |[4] |EPE |Even Parity Enable Bit + * | | |0 = Odd number of logic 1's is transmitted and checked in each word. + * | | |1 = Even number of logic 1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PBE (UART_LINE[3]) is set. + * |[5] |SPE |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. + * | | |If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1. + * |[6] |BCB |Break Control Bit + * | | |0 = Break Control Disabled. + * | | |1 = Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the transmitted serial data output (TX) is forced to the Spacing State (logic 0) + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[7] |PSS |Parity Bit Source Selection + * | | |The parity bit can be selected to be generated and checked automatically or by software. + * | | |0 = Parity bit is generated by EPE (UART_LINE[4]) and SPE (UART_LINE[5]) setting and checked automatically. + * | | |1 = Parity bit generated and checked by software. + * | | |Note1: This bit has effect only when PBE (UART_LINE[3]) is set. + * | | |Note2: If PSS is 0, the parity bit is transmitted and checked automatically. + * | | |If PSS is 1, the transmitted parity bit value can be determined by writing PARITY (UART_DAT[8]) and the parity bit can be read by reading PARITY (UART_DAT[8]). + * |[8] |TXDINV |TX Data Inverted + * | | |0 = Transmitted data signal inverted Disabled. + * | | |1 = Transmitted data signal inverted Enabled. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. + * |[9] |RXDINV |RX Data Inverted + * | | |0 = Received data signal inverted Disabled. + * | | |1 = Received data signal inverted Enabled. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select UART, LIN or RS485 function. + * @var UART_T::MODEM + * Offset: 0x10 UART Modem Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RTS |nRTS (Request-to-send) Signal Control + * | | |This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration. + * | | |0 = nRTS signal is active. + * | | |1 = nRTS signal is inactive. + * | | |Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode. + * | | |Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode. + * |[9] |RTSACTLV |nRTS Pin Active Level + * | | |This bit defines the active level state of nRTS pin output. + * | | |0 = nRTS pin output is high level active. + * | | |1 = nRTS pin output is low level active. (Default) + * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * |[13] |RTSSTS |nRTS Pin Status (Read Only) + * | | |This bit mirror from nRTS pin output of voltage logic status. + * | | |0 = nRTS pin output is low level voltage logic state. + * | | |1 = nRTS pin output is high level voltage logic state. + * @var UART_T::MODEMSTS + * Offset: 0x14 UART Modem Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSDETF |Detect nCTS State Change Flag + * | | |This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1. + * | | |0 = nCTS input has not change state. + * | | |1 = nCTS input has change state. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[4] |CTSSTS |nCTS Pin Status (Read Only) + * | | |This bit mirror from nCTS pin input of voltage logic status. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + * | | |Note: This bit echoes when UART controller peripheral clock is enabled, and nCTS multi-function port is selected. + * |[8] |CTSACTLV |nCTS Pin Active Level + * | | |This bit defines the active level state of nCTS pin input. + * | | |0 = nCTS pin input is high level active. + * | | |1 = nCTS pin input is low level active. (Default) + * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * @var UART_T::FIFOSTS + * Offset: 0x18 UART FIFO Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXOVIF |RX Overflow Error Interrupt Flag + * | | |This bit is set when RX FIFO overflow. + * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes, this bit will be set. + * | | |0 = RX FIFO is not overflow. + * | | |1 = RX FIFO is overflow. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[1] |ABRDIF |Auto-baud Rate Detect Interrupt Flag + * | | |This bit is set to logic 1 when auto-baud rate detect function is finished. + * | | |0 = Auto-baud rate detect function is not finished. + * | | |1 = Auto-baud rate detect function is finished. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[2] |ABRDTOIF |Auto-baud Rate Detect Time-out Interrupt Flag + * | | |This bit is set to logic 1 in Auto-baud Rate Detect mode when the baud rate counter is overflow. + * | | |0 = Auto-baud rate counter is underflow. + * | | |1 = Auto-baud rate counter is overflow. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[3] |ADDRDETF |RS-485 Address Byte Detect Flag + * | | |0 = Receiver detects a data that is not an address bit (bit 9 ='0'). + * | | |1 = Receiver detects a data that is an address bit (bit 9 ='1'). + * | | |Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[4] |PEF |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[5] |FEF |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[6] |BIF |Break Interrupt Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). + * | | |0 = No Break interrupt is generated. + * | | |1 = Break interrupt is generated. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[13:8] |RXPTR |RX FIFO Pointer (Read Only) + * | | |This field indicates the RX FIFO Buffer Pointer. + * | | |When UART receives one byte from external device, RXPTR increases one. + * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one. + * | | |The Maximum value shown in RXPTR is 15 + * | | |When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. + * | | |As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15. + * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only) + * | | |This bit initiate RX FIFO empty or not. + * | | |0 = RX FIFO is not empty. + * | | |1 = RX FIFO is empty. + * | | |Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. + * | | |It will be cleared when UART receives any new data. + * |[15] |RXFULL |Receiver FIFO Full (Read Only) + * | | |This bit initiates RX FIFO full or not. + * | | |0 = RX FIFO is not full. + * | | |1 = RX FIFO is full. + * | | |Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[21:16] |TXPTR |TX FIFO Pointer (Read Only) + * | | |This field indicates the TX FIFO Buffer Pointer. + * | | |When CPU writes one byte into UART_DAT, TXPTR increases one. + * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one. + * | | |The Maximum value shown in TXPTR is 15. + * | | |When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. + * | | |As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15. + * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only) + * | | |This bit indicates TX FIFO empty or not. + * | | |0 = TX FIFO is not empty. + * | | |1 = TX FIFO is empty. + * | | |Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. + * | | |It will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[23] |TXFULL |Transmitter FIFO Full (Read Only) + * | | |This bit indicates TX FIFO full or not. + * | | |0 = TX FIFO is not full. + * | | |1 = TX FIFO is full. + * | | |Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise it is cleared by hardware. + * |[24] |TXOVIF |TX Overflow Error Interrupt Flag + * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. + * | | |0 = TX FIFO is not overflow. + * | | |1 = TX FIFO is overflow. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only) + * | | |This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted. + * | | |0 = TX FIFO is not empty or the STOP bit of the last byte has been not transmitted. + * | | |1 = TX FIFO is empty and the STOP bit of the last byte has been transmitted. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[29] |RXIDLE |RX Idle Status (Read Only) + * | | |This bit is set by hardware when RX is idle. + * | | |0 = RX is busy. + * | | |1 = RX is idle. (Default) + * |[31] |TXRXACT |TX and RX Active Status (Read Only) + * | | |This bit indicates TX and RX are active or inactive. + * | | |0 = TX and RX are inactive. + * | | |1 = TX and RX are active. (Default) + * | | |Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state, this bit is cleared. + * | | |The UART controller can not transmit or receive data at this moment. + * | | |Otherwise this bit is set. + * @var UART_T::INTSTS + * Offset: 0x1C UART Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RDAIF |Receive Data Available Interrupt Flag + * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. + * | | |If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated. + * | | |0 = No RDA interrupt flag is generated. + * | | |1 = RDA interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4]). + * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag + * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. + * | | |If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated. + * | | |0 = No THRE interrupt flag is generated. + * | | |1 = THRE interrupt flag is generated. + * | | |Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty). + * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated. + * | | |1 = RLS interrupt flag is generated. + * | | |Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = 1) bit. + * | | |At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set. + * | | |Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. + * |[3] |MODEMIF |MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated. + * | | |1 = Modem interrupt flag is generated. + * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]). + * |[4] |RXTOIF |RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. + * | | |0 = No RX time-out interrupt flag is generated. + * | | |1 = RX time-out interrupt flag is generated. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer is not correct. + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated. + * | | |1 = Buffer error interrupt flag is generated. + * | | |Note: This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]). + * |[6] |WKIF |UART Wake-up Interrupt Flag (Read Only) + * | | |This bit is set when TOUTWKF (UART_WKSTS[4]), RS485WKF (UART_WKSTS[3]), RFRTWKF (UART_WKSTS[2]), DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1. + * | | |0 = No UART wake-up interrupt flag is generated. + * | | |1 = UART wake-up interrupt flag is generated. + * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. + * |[7] |LINIF |LIN Bus Interrupt Flag + * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0]=1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])) + * | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated. + * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. + * | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing 1 to LINIF(UART_INTSTS[7]). + * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only) + * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. + * | | |0 = No RDA interrupt is generated. + * | | |1 = RDA interrupt is generated. + * |[9] |THREINT |Transmit Holding Register Empty Interrupt Indicator (Read Only) + * | | |This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1. + * | | |0 = No THRE interrupt is generated. + * | | |1 = THRE interrupt is generated. + * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1. + * | | |0 = No RLS interrupt is generated. + * | | |1 = RLS interrupt is generated. + * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1 + * | | |0 = No Modem interrupt is generated. + * | | |1 = Modem interrupt is generated.. + * |[12] |RXTOINT |RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated. + * | | |1 = RX time-out interrupt is generated. + * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1. + * | | |0 = No buffer error interrupt is generated. + * | | |1 = Buffer error interrupt is generated. + * |[14] |WKINT |UART Wake-up Interrupt Indicator (Read Only) + * | | |This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1. + * | | |0 = No UART wake-up interrupt is generated. + * | | |1 = UART wake-up interrupt is generated. + * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only) + * | | |This bit is set if LINIEN (UART_INTEN[8]) and LINIF(UART_INTSTS[7]) are both set to 1. + * | | |0 = No LIN Bus interrupt is generated. + * | | |1 = The LIN Bus interrupt is generated. + * |[16] |SWBEIF |Single-wire Bit Error Detection Interrupt Flag + * | | |This bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode. + * | | |0 = No single-wire bit error detection interrupt flag is generated. + * | | |1 = Single-wire bit error detection interrupt flag is generated. + * | | |Note 1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire mode. + * | | |Note 2: This bit can be cleared by writing "1" to it. + * |[18] |HWRLSIF |PDMA Mode Receive Line Status Flag (Read Only) + * | | |This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). + * | | |If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated. + * | | |0 = No RLS interrupt flag is generated in PDMA mode. + * | | |1 = RLS interrupt flag is generated in PDMA mode. + * | | |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = 1) bit. + * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. + * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. + * |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only) + * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]=1)). + * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. + * | | |0 = No Modem interrupt flag is generated in PDMA mode. + * | | |1 = Modem interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0]). + * |[20] |HWTOIF |PDMA Mode RX Time-out Interrupt Flag (Read Only) + * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]). + * | | |If RXTOIEN (UART_INTEN [4]) is enabled, the RX time-out interrupt will be generated. + * | | |0 = No RX time-out interrupt flag is generated in PDMA mode. + * | | |1 = RX time-out interrupt flag is generated in PDMA mode. + * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it. + * |[21] |HWBUFEIF |PDMA Mode Buffer Error Interrupt Flag (Read Only) + * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). + * | | |When BUFERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct. + * | | |If BUFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated. + * | | |0 = No buffer error interrupt flag is generated in PDMA mode. + * | | |1 = Buffer error interrupt flag is generated in PDMA mode. + * | | |Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared. + * |[22] |TXENDIF |Transmitter Empty Interrupt Flag + * | | |This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). + * | | |If TXENDIEN (UART_INTEN[22]) is enabled, the Transmitter Empty interrupt will be generated. + * | | |0 = No transmitter empty interrupt flag is generated. + * | | |1 = Transmitter empty interrupt flag is generated. + * | | |Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed. + * |[24] |SWBEINT |Single-wire Bit Error Detect Interrupt Indicator (Read Only) + * | | |This bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1. + * | | |0 = No Single-wire Bit Error Detection Interrupt generated. + * | | |1 = Single-wire Bit Error Detection Interrupt generated. + * |[26] |HWRLSINT |PDMA Mode Receive Line Status Interrupt Indicator (Read Only) + * | | |This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1. + * | | |0 = No RLS interrupt is generated in PDMA mode. + * | | |1 = RLS interrupt is generated in PDMA mode. + * |[27] |HWMODINT |PDMA Mode MODEM Status Interrupt Indicator (Read Only) + * | | |This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1. + * | | |0 = No Modem interrupt is generated in PDMA mode. + * | | |1 = Modem interrupt is generated in PDMA mode. + * |[28] |HWTOINT |PDMA Mode RX Time-out Interrupt Indicator (Read Only) + * | | |This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1. + * | | |0 = No RX time-out interrupt is generated in PDMA mode. + * | | |1 = RX time-out interrupt is generated in PDMA mode. + * |[29] |HWBUFEINT |PDMA Mode Buffer Error Interrupt Indicator (Read Only) + * | | |This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1. + * | | |0 = No buffer error interrupt is generated in PDMA mode. + * | | |1 = Buffer error interrupt is generated in PDMA mode. + * |[30] |TXENDINT |Transmitter Empty Interrupt Indicator (Read Only) + * | | |This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1. + * | | |0 = No Transmitter Empty interrupt is generated. + * | | |1 = Transmitter Empty interrupt is generated. + * |[31] |ABRINT |Auto-baud Rate Interrupt Indicator (Read Only) + * | | |This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1. + * | | |0 = No Auto-baud Rate interrupt is generated. + * | | |1 = The Auto-baud Rate interrupt is generated. + * @var UART_T::TOUT + * Offset: 0x20 UART Time-out Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |TOIC |Time-out Interrupt Comparator + * | | |The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word if time out counter is enabled by setting TOCNTEN (UART_INTEN[11]). + * | | |Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled. + * | | |A new incoming data word or RX FIFO empty will clear RXTOIF (UART_INTSTS[4]). + * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255. + * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer. + * |[15:8] |DLY |TX Delay Time Value + * | | |This field is used to programming the transfer delay time between the last stop bit and next start bit. + * | | |The unit is bit time. + * @var UART_T::BAUD + * Offset: 0x24 UART Baud Rate Divider Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |BRD |Baud Rate Divider + * | | |The field indicates the baud rate divider. + * | | |This filed is used in baud rate calculation. + * |[27:24] |EDIVM1 |Extra Divider for BAUD Rate Mode 1 + * | | |This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. + * |[28] |BAUDM0 |BAUD Rate Mode Selection Bit 0 + * | | |This bit is baud rate mode selection bit 0 + * | | |UART provides three baud rate calculation modes. + * | | |This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. + * |[29] |BAUDM1 |BAUD Rate Mode Selection Bit 1 + * | | |This bit is baud rate mode selection bit 1. + * | | |UART provides three baud rate calculation modes. + * | | |This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. + * | | |Note: In IrDA mode must be operated in mode 0. + * @var UART_T::IRDA + * Offset: 0x28 UART IrDA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit + * | | |0 = IrDA Transmitter Disabled and Receiver Enabled. (Default) + * | | |1 = IrDA Transmitter Enabled and Receiver Disabled. + * |[5] |TXINV |IrDA Inverse Transmitting Output Signal + * | | |0 = None inverse transmitting signal. (Default). + * | | |1 = Inverse transmitting output signal. + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. + * |[6] |RXINV |IrDA Inverse Receive Input Signal + * | | |0 = None inverse receiving input signal. + * | | |1 = Inverse receiving input signal. (Default) + * | | |Note1: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. + * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. + * | | |Note2: This bit is valid when FUNCSEL (UART_FUNCSEL[1:0]) is select IrDA function. + * @var UART_T::ALTCTL + * Offset: 0x2C UART Alternate Control/Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |BRKFL |UART LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: This break field length is BRKFL + 1. + * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13). + * |[6] |LINRXEN |LIN RX Enable Bit + * | | |0 = LIN RX mode Disabled. + * | | |1 = LIN RX mode Enabled. + * |[7] |LINTXEN |LIN TX Break Mode Enable Bit + * | | |0 = LIN TX Break mode Disabled. + * | | |1 = LIN TX Break mode Enabled. + * | | |Note: When TX break field transfer operation finished, this bit will be cleared automatically. + * |[8] |RS485NMM |RS-485 Normal Multi-drop Operation Mode (NMM) + * | | |0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled. + * | | |1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled. + * | | |Note: It cannot be active with RS-485_AAD operation mode. + * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD) + * | | |0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled. + * | | |1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled. + * | | |Note: It cannot be active with RS-485_NMM operation mode. + * |[10] |RS485AUD |RS-485 Auto Direction Function (AUD) + * | | |0 = RS-485 Auto Direction Operation function (AUD) Disabled. + * | | |1 = RS-485 Auto Direction Operation function (AUD) Enabled. + * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode. + * |[15] |ADDRDEN |RS-485 Address Detection Enable Bit + * | | |This bit is used to enable RS-485 Address Detection mode. + * | | |0 = Address detection mode Disabled. + * | | |1 = Address detection mode Enabled. + * | | |Note: This bit is used for RS-485 any operation mode. + * |[17] |ABRIF |Auto-baud Rate Interrupt Flag (Read Only) + * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. + * | | |0 = No auto-baud rate interrupt flag is generated. + * | | |1 = Auto-baud rate interrupt flag is generated. + * | | |Note: This bit is read only, but it can be cleared by writing 1 to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]). + * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note : This bit is cleared automatically after auto-baud detection is finished. + * |[20:19] |ABRDBITS |Auto-baud Rate Detect Bit Length + * | | |00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01. + * | | |01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02. + * | | |10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08. + * | | |11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80. + * | | |Note : The calculation of bit number includes the START bit. + * |[31:24] |ADDRMV |Address Match Value + * | | |This field contains the RS-485 address match values. + * | | |Note: This field is used for RS-485 auto address detection mode. + * @var UART_T::FUNCSEL + * Offset: 0x30 UART Function Select Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNCSEL |Function Select + * | | |000 = UART function. + * | | |001 = LIN function. + * | | |010 = IrDA function. + * | | |011 = RS-485 function. + * | | |100 = UART Single-wire function. + * | | |Others = Reserved. + * |[3] |TXRXDIS |TX and RX Disable Bit + * | | |Setting this bit can disable TX and RX. + * | | |0 = TX and RX Enabled. + * | | |1 = TX and RX Disabled. + * | | |Note: The TX and RX will not disable immediately when this bit is set. + * | | |The TX and RX complete current task before disable TX and RX. + * | | |When TX and RX disable, the TXRXACT (UART_FIFOSTS[31]) is cleared. + * @var UART_T::LINCTL + * Offset: 0x34 UART LIN Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVEN |LIN Slave Mode Enable Bit + * | | |0 = LIN slave mode Disabled. + * | | |1 = LIN slave mode Enabled. + * |[1] |SLVHDEN |LIN Slave Header Detection Enable Bit + * | | |0 = LIN slave header detection Disabled. + * | | |1 = LIN slave header detection Enabled. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: In LIN function mode, when detect header field (break + sync + frame ID), SLVHDETF (UART_LINSTS [0]) flag will be asserted. + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Bit + * | | |0 = LIN automatic resynchronization Disabled. + * | | |1 = LIN automatic resynchronization Enabled. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD [29]) and BAUDM0 (UART_BAUD [28]) must be 1). + * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Bit + * | | |0 = UART_BAUD updated is written by software (if no automatic resynchronization update occurs at the same time). + * | | |1 = UART_BAUD is updated at the next received character + * | | |User must set the bit before checksum reception. + * | | |Note1: This bit only valid when in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1). + * | | |Note2: This bit used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) + * |[4] |MUTE |LIN Mute Mode Enable Bit + * | | |0 = LIN mute mode Disabled. + * | | |1 = LIN mute mode Enabled. + * | | |Note: The exit from mute mode condition and each control and interactions of this field are explained in 6.16.5.10 (LIN slave mode). + * |[8] |SENDH |LIN TX Send Header Enable Bit + * | | |The LIN TX header can be break field or break and sync field or break, sync and frame ID field, it is depend on setting HSEL (UART_LINCTL[23:22]). + * | | |0 = Send LIN TX header Disabled. + * | | |1 = Send LIN TX header Enabled. + * | | |Note1: This bit is shadow bit of LINTXEN (UART_ALTCTL [7]); user can read/write it by setting LINTXEN (UART_ALTCTL [7]) or SENDH (UART_LINCTL [8]). + * | | |Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by HSEL (UART_LINCTL[23:22]) field) transfer operation finished, this bit will be cleared automatically. + * |[9] |IDPEN |LIN ID Parity Enable Bit + * | | |0 = LIN frame ID parity Disabled. + * | | |1 = LIN frame ID parity Enabled. + * | | |Note1: This bit can be used for LIN master to sending header field (SENDH (UART_LINCTL[8])) = 1 and HSEL (UART_LINCTL[23:22]) = 10 or be used for enable LIN slave received frame ID parity checked. + * | | |Note2: This bit is only used when the operation header transmitter is in HSEL (UART_LINCTL[23:22]) = 10. + * |[10] |BRKDETEN |LIN Break Detection Enable Bit + * | | |When detect consecutive dominant greater than 11 bits, and are followed by a delimiter character, the BRKDETF (UART_LINSTS[8]) flag is set at the end of break field. + * | | |If the LINIEN (UART_INTEN [8])=1, an interrupt will be generated. + * | | |0 = LIN break detection Disabled . + * | | |1 = LIN break detection Enabled. + * |[11] |LINRXOFF |LIN Receiver Disable Bit + * | | |If the receiver is enabled (RXOFF (UART_LINCTL[11] ) = 0), all received byte data will be accepted and stored in the RX FIFO, and if the receiver is disabled (RXOFF (UART_LINCTL[11] = 1), all received byte data will be ignore. + * | | |0 = LIN receiver Enabled. + * | | |1 = LIN receiver Disabled. + * | | |Note: This bit is only valid when operating in LIN function mode (FUNCSEL (UART_FUNCSEL[1:0]) = 01). + * |[12] |BITERREN |Bit Error Detect Enable Bit + * | | |0 = Bit error detection function Disabled. + * | | |1 = Bit error detection function Enabled. + * | | |Note: In LIN function mode, when occur bit error, the BITEF (UART_LINSTS[9]) flag will be asserted. + * | | |If the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * |[19:16] |BRKFL |LIN Break Field Length + * | | |This field indicates a 4-bit LIN TX break field count. + * | | |Note1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]), User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL (UART_LINCTL[19:16]). + * | | |Note2: This break field length is BRKFL + 1. + * | | |Note3: According to LIN spec, the reset value is 12 (break field length = 13). + * |[21:20] |BSL |LIN Break/Sync Delimiter Length + * | | |00 = The LIN break/sync delimiter length is 1-bit time. + * | | |01 = The LIN break/sync delimiter length is 2-bit time. + * | | |10 = The LIN break/sync delimiter length is 3-bit time. + * | | |11 = The LIN break/sync delimiter length is 4-bit time. + * | | |Note: This bit used for LIN master to sending header field. + * |[23:22] |HSEL |LIN Header Select + * | | |00 = The LIN header includes break field. + * | | |01 = The LIN header includes break field and sync field. + * | | |10 = The LIN header includes break field, sync field and frame ID field. + * | | |11 = Reserved. + * | | |Note: This bit is used to master mode for LIN to send header field (SENDH (UART_LINCTL [8]) = 1) or used to slave to indicates exit from mute mode condition (MUTE (UART_LINCTL[4] = 1). + * |[31:24] |PID |LIN PID Bits + * | | |This field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on IDPEN (UART_LINCTL[9]) = 1. + * | | |If the parity generated by hardware, user fill ID0~ID5 (PID [29:24] ), hardware will calculate P0 (PID[30]) and P1 (PID[31]), otherwise user must filled frame ID and parity in this field. + * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first). + * | | |Note2: This field can be used for LIN master mode or slave mode. + * @var UART_T::LINSTS + * Offset: 0x38 UART LIN Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLVHDETF |LIN Slave Header Detection Flag + * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it. + * | | |0 = LIN header not detected. + * | | |1 = LIN header detected (break + sync + frame ID). + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * | | |Note3: When enable ID parity check IDPEN (UART_LINCTL [9]), if hardware detect complete header (break + sync + frame ID), the SLVHDETF will be set whether the frame ID correct or not. + * |[1] |SLVHEF |LIN Slave Header Error Flag + * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it + * | | |The header errors include break delimiter is too short (less than 0.5 bit time), frame error in sync field or Identifier field, sync field data is not 0x55 in Non-Automatic Resynchronization mode, sync field deviation error with Automatic Resynchronization mode, sync field measure time-out with Automatic Resynchronization mode and LIN header reception time-out. + * | | |0 = LIN header error not detected. + * | | |1 = LIN header error detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when UART is operated in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enables LIN slave header detection function (SLVHDEN (UART_LINCTL [1])). + * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag + * | | |This bit is set by hardware when receipted frame ID parity is not correct. + * | | |0 = No active. + * | | |1 = Receipted frame ID parity is not correct. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]). + * |[3] |SLVSYNCF |LIN Slave Sync Field + * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. + * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. + * | | |0 = The current character is not at LIN sync state. + * | | |1 = The current character is at LIN sync state. + * | | |Note1: This bit is only valid when in LIN Slave mode (SLVEN(UART_LINCTL[0]) = 1). + * | | |Note2: This bit can be cleared by writing 1 to it. + * | | |Note3: When writing 1 to it, hardware will reload the initial baud rate and re-search a new frame header. + * |[8] |BRKDETF |LIN Break Detection Flag + * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it through software. + * | | |0 = LIN break not detected. + * | | |1 = LIN break detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) = 1). + * |[9] |BITEF |Bit Error Detect Status Flag + * | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. + * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. + * | | |0 = Bit error not detected. + * | | |1 = Bit error detected. + * | | |Note1: This bit can be cleared by writing 1 to it. + * | | |Note2: This bit is only valid when enable bit error detection function (BITERREN (UART_LINCTL [12]) = 1). + * @var UART_T::BRCOMP + * Offset: 0x3C UART Baud Rate Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |BRCOMP |Baud Rate Compensation Patten + * | | |These 9-bits are used to define the relative bit is compensated or not. + * | | |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOMP[8] is used to define the parity bit. + * |[31] |BRCOMPDEC |Baud Rate Compensation Decrease + * | | |0 = Positive (increase one module clock) compensation for each compensated bit. + * | | |1 = Negative (decrease one module clock) compensation for each compensated bit. + * @var UART_T::WKCTL + * Offset: 0x40 UART Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKCTSEN |nCTS Wake-up Enable Bit + * | | |0 = nCTS Wake-up system function Disabled. + * | | |1 = nCTS Wake-up system function Enabled, when the system is in Power-down mode, an external. + * | | |nCTS change will wake-up system from Power-down mode. + * |[1] |WKDATEN |Incoming Data Wake-up Enable Bit + * | | |0 = Incoming data wake-up system function Disabled. + * | | |1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode,. + * | | |incoming data will wake-up system from Power-down mode. + * |[2] |WKRFRTEN |Received Data FIFO Reached Threshold Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold wake-up system function Enabled, when the system is. + * | | |in Power-down mode, Received Data FIFO reached threshold will wake-up system from + * | | |Power-down mode. + * |[3] |WKRS485EN |RS-485 Address Match (AAD Mode) Wake-up Enable Bit + * | | |0 = RS-485 Address Match (AAD mode) wake-up system function Disabled. + * | | |1 = RS-485 Address Match (AAD mode) wake-up system function Enabled, when the system is in Power-down mode, RS-485 Address Match will wake-up system from Power-down mode. + * | | |Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1. + * |[4] |WKTOUTEN |Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit + * | | |0 = Received Data FIFO reached threshold time-out wake-up system function Disabled. + * | | |1 = Received Data FIFO reached threshold time-out wake-up system function Enabled, when the system is in Power-down mode, Received Data FIFO reached threshold time-out will wake-up system from Power-down mode. + * | | |Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1. + * @var UART_T::WKSTS + * Offset: 0x44 UART Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CTSWKF |nCTS Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by nCTS wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by nCTS wake-up. + * | | |Note1: If WKCTSEN (UART_WKCTL[0]) is enabled, the nCTS wake-up cause this bit is set to 1. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[1] |DATWKF |Incoming Data Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by data wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Incoming Data wake-up. + * | | |Note1: If WKDATEN (UART_WKCTL[1]) is enabled, the Incoming Data wake-up cause this bit is set to 1. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[2] |RFRTWKF |Received Data FIFO Reached Threshold Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO Reached Threshold wake-up. + * | | |Note1: If WKRFRTEN (UART_WKCTL[2]) is enabled, the Received Data FIFO Reached Threshold wake-up cause this bit is set to 1. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[3] |RS485WKF |RS-485 Address Match (AAD Mode) Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode). + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by RS-485 Address Match (AAD mode) wake-up. + * | | |Note1: If WKRS485EN (UART_WKCTL[3]) is enabled, the RS-485 Address Match (AAD mode) wake-up cause this bit is set to 1. + * | | |Note2: This bit can be cleared by writing 1 to it. + * |[4] |TOUTWKF |Received Data FIFO Threshold Time-out Wake-up Flag + * | | |This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up. + * | | |0 = Chip stays in power-down state. + * | | |1 = Chip wake-up from power-down state by Received Data FIFO reached threshold time-out wake-up. + * | | |Note1: If WKTOUTEN (UART_WKCTL[4]) is enabled, the Received Data FIFO reached threshold time-out wake-up cause this bit is set to 1. + * | | |Note2: This bit can be cleared by writing 1 to it. + * @var UART_T::DWKCOMP + * Offset: 0x48 UART Incoming Data Wake-up Compensation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |STCOMP |Start Bit Compensation Value + * | | |These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode. + * | | |Note: It is valid only when WKDATEN (UART_WKCTL[1]) is set. + */ + + + __IO uint32_t DAT; /*!< [0x0000] UART Receive/Transmit Buffer Register */ + __IO uint32_t INTEN; /*!< [0x0004] UART Interrupt Enable Register */ + __IO uint32_t FIFO; /*!< [0x0008] UART FIFO Control Register */ + __IO uint32_t LINE; /*!< [0x000c] UART Line Control Register */ + __IO uint32_t MODEM; /*!< [0x0010] UART Modem Control Register */ + __IO uint32_t MODEMSTS; /*!< [0x0014] UART Modem Status Register */ + __IO uint32_t FIFOSTS; /*!< [0x0018] UART FIFO Status Register */ + __IO uint32_t INTSTS; /*!< [0x001c] UART Interrupt Status Register */ + __IO uint32_t TOUT; /*!< [0x0020] UART Time-out Register */ + __IO uint32_t BAUD; /*!< [0x0024] UART Baud Rate Divider Register */ + __IO uint32_t IRDA; /*!< [0x0028] UART IrDA Control Register */ + __IO uint32_t ALTCTL; /*!< [0x002c] UART Alternate Control/Status Register */ + __IO uint32_t FUNCSEL; /*!< [0x0030] UART Function Select Register */ + __IO uint32_t LINCTL; /*!< [0x0034] UART LIN Control Register */ + __IO uint32_t LINSTS; /*!< [0x0038] UART LIN Status Register */ + __IO uint32_t BRCOMP; /*!< [0x003c] UART Baud Rate Compensation Register */ + __IO uint32_t WKCTL; /*!< [0x0040] UART Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0044] UART Wake-up Status Register */ + __IO uint32_t DWKCOMP; /*!< [0x0048] UART Incoming Data Wake-up Compensation Register */ + + +} UART_T; + +/** + @addtogroup UART_CONST UART Bit Field Definition + Constant Definitions for UART Controller + @{ +*/ + +#define UART_DAT_DAT_Pos (0) /*!< UART_T::DAT: DAT Position */ +#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART_T::DAT: DAT Mask */ + +#define UART_DAT_PARITY_Pos (8) /*!< UART_T::DAT: PARITY Position */ +#define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) /*!< UART_T::DAT: PARITY Mask */ + +#define UART_INTEN_RDAIEN_Pos (0) /*!< UART_T::INTEN: RDAIEN Position */ +#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART_T::INTEN: RDAIEN Mask */ + +#define UART_INTEN_THREIEN_Pos (1) /*!< UART_T::INTEN: THREIEN Position */ +#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART_T::INTEN: THREIEN Mask */ + +#define UART_INTEN_RLSIEN_Pos (2) /*!< UART_T::INTEN: RLSIEN Position */ +#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART_T::INTEN: RLSIEN Mask */ + +#define UART_INTEN_MODEMIEN_Pos (3) /*!< UART_T::INTEN: MODEMIEN Position */ +#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART_T::INTEN: MODEMIEN Mask */ + +#define UART_INTEN_RXTOIEN_Pos (4) /*!< UART_T::INTEN: RXTOIEN Position */ +#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART_T::INTEN: RXTOIEN Mask */ + +#define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART_T::INTEN: BUFERRIEN Position */ +#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART_T::INTEN: BUFERRIEN Mask */ + +#define UART_INTEN_WKIEN_Pos (6) /*!< UART_T::INTEN: WKIEN Position */ +#define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) /*!< UART_T::INTEN: WKIEN Mask */ + +#define UART_INTEN_LINIEN_Pos (8) /*!< UART_T::INTEN: LINIEN Position */ +#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART_T::INTEN: LINIEN Mask */ + +#define UART_INTEN_TOCNTEN_Pos (11) /*!< UART_T::INTEN: TOCNTEN Position */ +#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART_T::INTEN: TOCNTEN Mask */ + +#define UART_INTEN_ATORTSEN_Pos (12) /*!< UART_T::INTEN: ATORTSEN Position */ +#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART_T::INTEN: ATORTSEN Mask */ + +#define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART_T::INTEN: ATOCTSEN Position */ +#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART_T::INTEN: ATOCTSEN Mask */ + +#define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART_T::INTEN: TXPDMAEN Position */ +#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART_T::INTEN: TXPDMAEN Mask */ + +#define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART_T::INTEN: RXPDMAEN Position */ +#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART_T::INTEN: RXPDMAEN Mask */ + +#define UART_INTEN_SWBEIEN_Pos (16) /*!< UART_T::INTEN: SWBEIEN Position */ +#define UART_INTEN_SWBEIEN_Msk (0x1ul << UART_INTEN_SWBEIEN_Pos) /*!< UART_T::INTEN: SWBEIEN Mask */ + +#define UART_INTEN_ABRIEN_Pos (18) /*!< UART_T::INTEN: ABRIEN Position */ +#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) /*!< UART_T::INTEN: ABRIEN Mask */ + +#define UART_INTEN_TXENDIEN_Pos (22) /*!< UART_T::INTEN: TXENDIEN Position */ +#define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) /*!< UART_T::INTEN: TXENDIEN Mask */ + +#define UART_FIFO_RXRST_Pos (1) /*!< UART_T::FIFO: RXRST Position */ +#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART_T::FIFO: RXRST Mask */ + +#define UART_FIFO_TXRST_Pos (2) /*!< UART_T::FIFO: TXRST Position */ +#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART_T::FIFO: TXRST Mask */ + +#define UART_FIFO_RFITL_Pos (4) /*!< UART_T::FIFO: RFITL Position */ +#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART_T::FIFO: RFITL Mask */ + +#define UART_FIFO_RXOFF_Pos (8) /*!< UART_T::FIFO: RXOFF Position */ +#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART_T::FIFO: RXOFF Mask */ + +#define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART_T::FIFO: RTSTRGLV Position */ +#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART_T::FIFO: RTSTRGLV Mask */ + +#define UART_LINE_WLS_Pos (0) /*!< UART_T::LINE: WLS Position */ +#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART_T::LINE: WLS Mask */ + +#define UART_LINE_NSB_Pos (2) /*!< UART_T::LINE: NSB Position */ +#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART_T::LINE: NSB Mask */ + +#define UART_LINE_PBE_Pos (3) /*!< UART_T::LINE: PBE Position */ +#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART_T::LINE: PBE Mask */ + +#define UART_LINE_EPE_Pos (4) /*!< UART_T::LINE: EPE Position */ +#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART_T::LINE: EPE Mask */ + +#define UART_LINE_SPE_Pos (5) /*!< UART_T::LINE: SPE Position */ +#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART_T::LINE: SPE Mask */ + +#define UART_LINE_BCB_Pos (6) /*!< UART_T::LINE: BCB Position */ +#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART_T::LINE: BCB Mask */ + +#define UART_LINE_PSS_Pos (7) /*!< UART_T::LINE: PSS Position */ +#define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) /*!< UART_T::LINE: PSS Mask */ + +#define UART_LINE_TXDINV_Pos (8) /*!< UART_T::LINE: TXDINV Position */ +#define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) /*!< UART_T::LINE: TXDINV Mask */ + +#define UART_LINE_RXDINV_Pos (9) /*!< UART_T::LINE: RXDINV Position */ +#define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) /*!< UART_T::LINE: RXDINV Mask */ + +#define UART_MODEM_RTS_Pos (1) /*!< UART_T::MODEM: RTS Position */ +#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART_T::MODEM: RTS Mask */ + +#define UART_MODEM_RTSACTLV_Pos (9) /*!< UART_T::MODEM: RTSACTLV Position */ +#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART_T::MODEM: RTSACTLV Mask */ + +#define UART_MODEM_RTSSTS_Pos (13) /*!< UART_T::MODEM: RTSSTS Position */ +#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART_T::MODEM: RTSSTS Mask */ + +#define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART_T::MODEMSTS: CTSDETF Position */ +#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART_T::MODEMSTS: CTSDETF Mask */ + +#define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART_T::MODEMSTS: CTSSTS Position */ +#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART_T::MODEMSTS: CTSSTS Mask */ + +#define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART_T::MODEMSTS: CTSACTLV Position */ +#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART_T::MODEMSTS: CTSACTLV Mask */ + +#define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART_T::FIFOSTS: RXOVIF Position */ +#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART_T::FIFOSTS: RXOVIF Mask */ + +#define UART_FIFOSTS_ABRDIF_Pos (1) /*!< UART_T::FIFOSTS: ABRDIF Position */ +#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) /*!< UART_T::FIFOSTS: ABRDIF Mask */ + +#define UART_FIFOSTS_ABRDTOIF_Pos (2) /*!< UART_T::FIFOSTS: ABRDTOIF Position */ +#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) /*!< UART_T::FIFOSTS: ABRDTOIF Mask */ + +#define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART_T::FIFOSTS: ADDRDETF Position */ +#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART_T::FIFOSTS: ADDRDETF Mask */ + +#define UART_FIFOSTS_PEF_Pos (4) /*!< UART_T::FIFOSTS: PEF Position */ +#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART_T::FIFOSTS: PEF Mask */ + +#define UART_FIFOSTS_FEF_Pos (5) /*!< UART_T::FIFOSTS: FEF Position */ +#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART_T::FIFOSTS: FEF Mask */ + +#define UART_FIFOSTS_BIF_Pos (6) /*!< UART_T::FIFOSTS: BIF Position */ +#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART_T::FIFOSTS: BIF Mask */ + +#define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART_T::FIFOSTS: RXPTR Position */ +#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART_T::FIFOSTS: RXPTR Mask */ + +#define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART_T::FIFOSTS: RXEMPTY Position */ +#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART_T::FIFOSTS: RXEMPTY Mask */ + +#define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART_T::FIFOSTS: RXFULL Position */ +#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART_T::FIFOSTS: RXFULL Mask */ + +#define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART_T::FIFOSTS: TXPTR Position */ +#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART_T::FIFOSTS: TXPTR Mask */ + +#define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART_T::FIFOSTS: TXEMPTY Position */ +#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART_T::FIFOSTS: TXEMPTY Mask */ + +#define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART_T::FIFOSTS: TXFULL Position */ +#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART_T::FIFOSTS: TXFULL Mask */ + +#define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART_T::FIFOSTS: TXOVIF Position */ +#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART_T::FIFOSTS: TXOVIF Mask */ + +#define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART_T::FIFOSTS: TXEMPTYF Position */ +#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART_T::FIFOSTS: TXEMPTYF Mask */ + +#define UART_FIFOSTS_RXIDLE_Pos (29) /*!< UART_T::FIFOSTS: RXIDLE Position */ +#define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) /*!< UART_T::FIFOSTS: RXIDLE Mask */ + +#define UART_FIFOSTS_TXRXACT_Pos (31) /*!< UART_T::FIFOSTS: TXRXACT Position */ +#define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) /*!< UART_T::FIFOSTS: TXRXACT Mask */ + +#define UART_INTSTS_RDAIF_Pos (0) /*!< UART_T::INTSTS: RDAIF Position */ +#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART_T::INTSTS: RDAIF Mask */ + +#define UART_INTSTS_THREIF_Pos (1) /*!< UART_T::INTSTS: THREIF Position */ +#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART_T::INTSTS: THREIF Mask */ + +#define UART_INTSTS_RLSIF_Pos (2) /*!< UART_T::INTSTS: RLSIF Position */ +#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART_T::INTSTS: RLSIF Mask */ + +#define UART_INTSTS_MODEMIF_Pos (3) /*!< UART_T::INTSTS: MODEMIF Position */ +#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) /*!< UART_T::INTSTS: MODEMIF Mask */ + +#define UART_INTSTS_RXTOIF_Pos (4) /*!< UART_T::INTSTS: RXTOIF Position */ +#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART_T::INTSTS: RXTOIF Mask */ + +#define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART_T::INTSTS: BUFERRIF Position */ +#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART_T::INTSTS: BUFERRIF Mask */ + +#define UART_INTSTS_WKIF_Pos (6) /*!< UART_T::INTSTS: WKIF Position */ +#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) /*!< UART_T::INTSTS: WKIF Mask */ + +#define UART_INTSTS_LINIF_Pos (7) /*!< UART_T::INTSTS: LINIF Position */ +#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART_T::INTSTS: LINIF Mask */ + +#define UART_INTSTS_RDAINT_Pos (8) /*!< UART_T::INTSTS: RDAINT Position */ +#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART_T::INTSTS: RDAINT Mask */ + +#define UART_INTSTS_THREINT_Pos (9) /*!< UART_T::INTSTS: THREINT Position */ +#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART_T::INTSTS: THREINT Mask */ + +#define UART_INTSTS_RLSINT_Pos (10) /*!< UART_T::INTSTS: RLSINT Position */ +#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART_T::INTSTS: RLSINT Mask */ + +#define UART_INTSTS_MODEMINT_Pos (11) /*!< UART_T::INTSTS: MODEMINT Position */ +#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART_T::INTSTS: MODEMINT Mask */ + +#define UART_INTSTS_RXTOINT_Pos (12) /*!< UART_T::INTSTS: RXTOINT Position */ +#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART_T::INTSTS: RXTOINT Mask */ + +#define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART_T::INTSTS: BUFERRINT Position */ +#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART_T::INTSTS: BUFERRINT Mask */ + +#define UART_INTSTS_WKINT_Pos (14) /*!< UART_T::INTSTS: WKINT Position */ +#define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) /*!< UART_T::INTSTS: WKINT Mask */ + +#define UART_INTSTS_LININT_Pos (15) /*!< UART_T::INTSTS: LININT Position */ +#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART_T::INTSTS: LININT Mask */ + +#define UART_INTSTS_SWBEIF_Pos (16) /*!< UART_T::INTSTS: SWBEIF Position */ +#define UART_INTSTS_SWBEIF_Msk (0x1ul << UART_INTSTS_SWBEIF_Pos) /*!< UART_T::INTSTS: SWBEIF Mask */ + +#define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART_T::INTSTS: HWRLSIF Position */ +#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART_T::INTSTS: HWRLSIF Mask */ + +#define UART_INTSTS_HWMODIF_Pos (19) /*!< UART_T::INTSTS: HWMODIF Position */ +#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART_T::INTSTS: HWMODIF Mask */ + +#define UART_INTSTS_HWTOIF_Pos (20) /*!< UART_T::INTSTS: HWTOIF Position */ +#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART_T::INTSTS: HWTOIF Mask */ + +#define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART_T::INTSTS: HWBUFEIF Position */ +#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART_T::INTSTS: HWBUFEIF Mask */ + +#define UART_INTSTS_TXENDIF_Pos (22) /*!< UART_T::INTSTS: TXENDIF Position */ +#define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) /*!< UART_T::INTSTS: TXENDIF Mask */ + +#define UART_INTSTS_SWBEINT_Pos (24) /*!< UART_T::INTSTS: SWBEINT Position */ +#define UART_INTSTS_SWBEINT_Msk (0x1ul << UART_INTSTS_SWBEINT_Pos) /*!< UART_T::INTSTS: SWBEINT Mask */ + +#define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART_T::INTSTS: HWRLSINT Position */ +#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART_T::INTSTS: HWRLSINT Mask */ + +#define UART_INTSTS_HWMODINT_Pos (27) /*!< UART_T::INTSTS: HWMODINT Position */ +#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART_T::INTSTS: HWMODINT Mask */ + +#define UART_INTSTS_HWTOINT_Pos (28) /*!< UART_T::INTSTS: HWTOINT Position */ +#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART_T::INTSTS: HWTOINT Mask */ + +#define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART_T::INTSTS: HWBUFEINT Position */ +#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART_T::INTSTS: HWBUFEINT Mask */ + +#define UART_INTSTS_TXENDINT_Pos (30) /*!< UART_T::INTSTS: TXENDINT Position */ +#define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) /*!< UART_T::INTSTS: TXENDINT Mask */ + +#define UART_INTSTS_ABRINT_Pos (31) /*!< UART_T::INTSTS: ABRINT Position */ +#define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) /*!< UART_T::INTSTS: ABRINT Mask */ + +#define UART_TOUT_TOIC_Pos (0) /*!< UART_T::TOUT: TOIC Position */ +#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART_T::TOUT: TOIC Mask */ + +#define UART_TOUT_DLY_Pos (8) /*!< UART_T::TOUT: DLY Position */ +#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART_T::TOUT: DLY Mask */ + +#define UART_BAUD_BRD_Pos (0) /*!< UART_T::BAUD: BRD Position */ +#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART_T::BAUD: BRD Mask */ + +#define UART_BAUD_EDIVM1_Pos (24) /*!< UART_T::BAUD: EDIVM1 Position */ +#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART_T::BAUD: EDIVM1 Mask */ + +#define UART_BAUD_BAUDM0_Pos (28) /*!< UART_T::BAUD: BAUDM0 Position */ +#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART_T::BAUD: BAUDM0 Mask */ + +#define UART_BAUD_BAUDM1_Pos (29) /*!< UART_T::BAUD: BAUDM1 Position */ +#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART_T::BAUD: BAUDM1 Mask */ + +#define UART_IRDA_TXEN_Pos (1) /*!< UART_T::IRDA: TXEN Position */ +#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART_T::IRDA: TXEN Mask */ + +#define UART_IRDA_TXINV_Pos (5) /*!< UART_T::IRDA: TXINV Position */ +#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART_T::IRDA: TXINV Mask */ + +#define UART_IRDA_RXINV_Pos (6) /*!< UART_T::IRDA: RXINV Position */ +#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART_T::IRDA: RXINV Mask */ + +#define UART_ALTCTL_BRKFL_Pos (0) /*!< UART_T::ALTCTL: BRKFL Position */ +#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) /*!< UART_T::ALTCTL: BRKFL Mask */ + +#define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART_T::ALTCTL: LINRXEN Position */ +#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART_T::ALTCTL: LINRXEN Mask */ + +#define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART_T::ALTCTL: LINTXEN Position */ +#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART_T::ALTCTL: LINTXEN Mask */ + +#define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART_T::ALTCTL: RS485NMM Position */ +#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART_T::ALTCTL: RS485NMM Mask */ + +#define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART_T::ALTCTL: RS485AAD Position */ +#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART_T::ALTCTL: RS485AAD Mask */ + +#define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART_T::ALTCTL: RS485AUD Position */ +#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART_T::ALTCTL: RS485AUD Mask */ + +#define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART_T::ALTCTL: ADDRDEN Position */ +#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART_T::ALTCTL: ADDRDEN Mask */ + +#define UART_ALTCTL_ABRIF_Pos (17) /*!< UART_T::ALTCTL: ABRIF Position */ +#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) /*!< UART_T::ALTCTL: ABRIF Mask */ + +#define UART_ALTCTL_ABRDEN_Pos (18) /*!< UART_T::ALTCTL: ABRDEN Position */ +#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) /*!< UART_T::ALTCTL: ABRDEN Mask */ + +#define UART_ALTCTL_ABRDBITS_Pos (19) /*!< UART_T::ALTCTL: ABRDBITS Position */ +#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) /*!< UART_T::ALTCTL: ABRDBITS Mask */ + +#define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART_T::ALTCTL: ADDRMV Position */ +#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART_T::ALTCTL: ADDRMV Mask */ + +#define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART_T::FUNCSEL: FUNCSEL Position */ +#define UART_FUNCSEL_FUNCSEL_Msk (0x7ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_T::FUNCSEL: FUNCSEL Mask */ + +#define UART_FUNCSEL_TXRXDIS_Pos (3) /*!< UART_T::FUNCSEL: TXRXDIS Position */ +#define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) /*!< UART_T::FUNCSEL: TXRXDIS Mask */ + +#define UART_LINCTL_SLVEN_Pos (0) /*!< UART_T::LINCTL: SLVEN Position */ +#define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART_T::LINCTL: SLVEN Mask */ + +#define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART_T::LINCTL: SLVHDEN Position */ +#define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART_T::LINCTL: SLVHDEN Mask */ + +#define UART_LINCTL_SLVAREN_Pos (2) /*!< UART_T::LINCTL: SLVAREN Position */ +#define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART_T::LINCTL: SLVAREN Mask */ + +#define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART_T::LINCTL: SLVDUEN Position */ +#define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART_T::LINCTL: SLVDUEN Mask */ + +#define UART_LINCTL_MUTE_Pos (4) /*!< UART_T::LINCTL: MUTE Position */ +#define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART_T::LINCTL: MUTE Mask */ + +#define UART_LINCTL_SENDH_Pos (8) /*!< UART_T::LINCTL: SENDH Position */ +#define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART_T::LINCTL: SENDH Mask */ + +#define UART_LINCTL_IDPEN_Pos (9) /*!< UART_T::LINCTL: IDPEN Position */ +#define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART_T::LINCTL: IDPEN Mask */ + +#define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART_T::LINCTL: BRKDETEN Position */ +#define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART_T::LINCTL: BRKDETEN Mask */ + +#define UART_LINCTL_LINRXOFF_Pos (11) /*!< UART_T::LINCTL: LINRXOFF Position */ +#define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) /*!< UART_T::LINCTL: LINRXOFF Mask */ + +#define UART_LINCTL_BITERREN_Pos (12) /*!< UART_T::LINCTL: BITERREN Position */ +#define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART_T::LINCTL: BITERREN Mask */ + +#define UART_LINCTL_BRKFL_Pos (16) /*!< UART_T::LINCTL: BRKFL Position */ +#define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART_T::LINCTL: BRKFL Mask */ + +#define UART_LINCTL_BSL_Pos (20) /*!< UART_T::LINCTL: BSL Position */ +#define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART_T::LINCTL: BSL Mask */ + +#define UART_LINCTL_HSEL_Pos (22) /*!< UART_T::LINCTL: HSEL Position */ +#define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART_T::LINCTL: HSEL Mask */ + +#define UART_LINCTL_PID_Pos (24) /*!< UART_T::LINCTL: PID Position */ +#define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART_T::LINCTL: PID Mask */ + +#define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART_T::LINSTS: SLVHDETF Position */ +#define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART_T::LINSTS: SLVHDETF Mask */ + +#define UART_LINSTS_SLVHEF_Pos (1) /*!< UART_T::LINSTS: SLVHEF Position */ +#define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART_T::LINSTS: SLVHEF Mask */ + +#define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART_T::LINSTS: SLVIDPEF Position */ +#define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART_T::LINSTS: SLVIDPEF Mask */ + +#define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART_T::LINSTS: SLVSYNCF Position */ +#define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART_T::LINSTS: SLVSYNCF Mask */ + +#define UART_LINSTS_BRKDETF_Pos (8) /*!< UART_T::LINSTS: BRKDETF Position */ +#define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART_T::LINSTS: BRKDETF Mask */ + +#define UART_LINSTS_BITEF_Pos (9) /*!< UART_T::LINSTS: BITEF Position */ +#define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART_T::LINSTS: BITEF Mask */ + +#define UART_BRCOMP_BRCOMP_Pos (0) /*!< UART_T::BRCOMP: BRCOMP Position */ +#define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) /*!< UART_T::BRCOMP: BRCOMP Mask */ + +#define UART_BRCOMP_BRCOMPDEC_Pos (31) /*!< UART_T::BRCOMP: BRCOMPDEC Position */ +#define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) /*!< UART_T::BRCOMP: BRCOMPDEC Mask */ + +#define UART_WKCTL_WKCTSEN_Pos (0) /*!< UART_T::WKCTL: WKCTSEN Position */ +#define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) /*!< UART_T::WKCTL: WKCTSEN Mask */ + +#define UART_WKCTL_WKDATEN_Pos (1) /*!< UART_T::WKCTL: WKDATEN Position */ +#define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) /*!< UART_T::WKCTL: WKDATEN Mask */ + +#define UART_WKCTL_WKRFRTEN_Pos (2) /*!< UART_T::WKCTL: WKRFRTEN Position */ +#define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) /*!< UART_T::WKCTL: WKRFRTEN Mask */ + +#define UART_WKCTL_WKRS485EN_Pos (3) /*!< UART_T::WKCTL: WKRS485EN Position */ +#define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) /*!< UART_T::WKCTL: WKRS485EN Mask */ + +#define UART_WKCTL_WKTOUTEN_Pos (4) /*!< UART_T::WKCTL: WKTOUTEN Position */ +#define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) /*!< UART_T::WKCTL: WKTOUTEN Mask */ + +#define UART_WKSTS_CTSWKF_Pos (0) /*!< UART_T::WKSTS: CTSWKF Position */ +#define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) /*!< UART_T::WKSTS: CTSWKF Mask */ + +#define UART_WKSTS_DATWKF_Pos (1) /*!< UART_T::WKSTS: DATWKF Position */ +#define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) /*!< UART_T::WKSTS: DATWKF Mask */ + +#define UART_WKSTS_RFRTWKF_Pos (2) /*!< UART_T::WKSTS: RFRTWKF Position */ +#define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) /*!< UART_T::WKSTS: RFRTWKF Mask */ + +#define UART_WKSTS_RS485WKF_Pos (3) /*!< UART_T::WKSTS: RS485WKF Position */ +#define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) /*!< UART_T::WKSTS: RS485WKF Mask */ + +#define UART_WKSTS_TOUTWKF_Pos (4) /*!< UART_T::WKSTS: TOUTWKF Position */ +#define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) /*!< UART_T::WKSTS: TOUTWKF Mask */ + +#define UART_DWKCOMP_STCOMP_Pos (0) /*!< UART_T::DWKCOMP: STCOMP Position */ +#define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) /*!< UART_T::DWKCOMP: STCOMP Mask */ + +/**@}*/ /* UART_CONST */ +/**@}*/ /* end of UART register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __UART_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ui2c_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ui2c_reg.h new file mode 100644 index 0000000000..00cf3576e1 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/ui2c_reg.h @@ -0,0 +1,568 @@ +/**************************************************************************//** + * @file ui2c_reg.h + * @version V1.00 + * @brief UI2C register definition header file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UI2C_REG_H__ +#define __UI2C_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- I2C Mode of USCI Controller -------------------------*/ +/** + @addtogroup UI2C I2C Mode of USCI Controller(UI2C) + Memory Mapped Structure for UI2C Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var UI2C_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var UI2C_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK = fDIV_CLK. + * | | |01 = fSAMP_CLK = fPROT_CLK. + * | | |10 = fSAMP_CLK = fSCLK. + * | | |11 = fSAMP_CLK = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UI2C_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits. + * @var UI2C_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UI2C_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C. + * | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UI2C_PROTSTS[7:5]). + * @var UI2C_T::DEVADDR0 + * Offset: 0x44 USCI Device Address Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. + * @var UI2C_T::DEVADDR1 + * Offset: 0x48 USCI Device Address Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |DEVADDR |Device Address + * | | |In I2C protocol, this bit field contains the programmed slave address + * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit + * | | |Then the second address byte is also compared to DEVADDR[7:0]. + * | | |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. + * @var UI2C_T::ADDRMSK0 + * Offset: 0x4C USCI Device Address Mask Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not set address mask. + * @var UI2C_T::ADDRMSK1 + * Offset: 0x50 USCI Device Address Mask Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[9:0] |ADDRMSK |USCI Device Address Mask + * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). + * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). + * | | |USCI support multiple address recognition with two address mask register + * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care + * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. + * | | |Note: The wake-up function can not set address mask. + * @var UI2C_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * @var UI2C_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var UI2C_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |GCFUNC |General Call Function + * | | |0 = General Call Function Disabled. + * | | |1 = General Call Function Enabled. + * |[1] |AA |Assert Acknowledge Control + * | | |When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter + * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. + * |[2] |STO |I2C STOP Control + * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically + * | | |In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode when bus error (UI2C_PROTSTS.ERRIF = 1). + * |[3] |STA |I2C START Control + * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. + * |[4] |ADDR10EN |Address 10-bit Function Enable Bit + * | | |0 = Address match 10 bit function is disabled. + * | | |1 = Address match 10 bit function is enabled. + * |[5] |PTRG |I2C Protocol Trigger (Write Only) + * | | |When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested + * | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. + * | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead. + * | | |1 = I2C's stretch active. + * |[8] |SCLOUTEN |SCL Output Enable Bit + * | | |This bit enables monitor pulling SCL to low + * | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. + * | | |0 = SCL output will be forced high due to open drain mechanism. + * | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt. + * |[9] |MONEN |Monitor Mode Enable Bit + * | | |This bit enables monitor mode + * | | |In monitor mode the SDA output will be put in high impedance mode + * | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. + * | | |0 = The monitor mode is disabled. + * | | |1 = The monitor mode is enabled. + * | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. + * |[25:16] |TOCNT |Time-out Clock Cycle + * | | |This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear + * | | |The time-out is enable when TOCNT bigger than 0. + * | | |Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. + * |[31] |PROTEN |I2C Protocol Enable Bit + * | | |0 = I2C Protocol disable. + * | | |1 = I2C Protocol enable. + * @var UI2C_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |TOIEN |Time-out Interrupt Enable Control + * | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event. + * | | |0 = The time-out interrupt is disabled. + * | | |1 = The time-out interrupt is enabled. + * |[1] |STARIEN |Start Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a start condition is detected. + * | | |0 = The start condition interrupt is disabled. + * | | |1 = The start condition interrupt is enabled. + * |[2] |STORIEN |Stop Condition Received Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a stop condition is detected. + * | | |0 = The stop condition interrupt is disabled. + * | | |1 = The stop condition interrupt is enabled. + * |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master. + * | | |0 = The non - acknowledge interrupt is disabled. + * | | |1 = The non - acknowledge interrupt is enabled. + * |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. + * | | |0 = The arbitration lost interrupt is disabled. + * | | |1 = The arbitration lost interrupt is enabled. + * |[5] |ERRIEN |Error Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])). + * | | |0 = The error interrupt is disabled. + * | | |1 = The error interrupt is enabled. + * |[6] |ACKIEN |Acknowledge Interrupt Enable Control + * | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. + * | | |0 = The acknowledge interrupt is disabled. + * | | |1 = The acknowledge interrupt is enabled. + * @var UI2C_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5] |TOIF |Time-out Interrupt Flag + * | | |0 = A time-out interrupt status has not occurred. + * | | |1 = A time-out interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit + * |[6] |ONBUSY |On Bus Busy + * | | |Indicates that a communication is in progress on the bus + * | | |It is set by hardware when a START condition is detected + * | | |It is cleared by hardware when a STOP condition is detected + * | | |0 = The bus is IDLE (both SCLK and SDA High). + * | | |1 = The bus is busy. + * |[8] |STARIF |Start Condition Received Interrupt Flag + * | | |This bit indicates that a start condition or repeated start condition has been detected on master mode + * | | |However, this bit also indicates that a repeated start condition has been detected on slave mode. + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.STARIEN = 1. + * | | |0 = A start condition has not yet been detected. + * | | |1 = A start condition has been detected. + * | | |It is cleared by software writing one into this bit + * |[9] |STORIF |Stop Condition Received Interrupt Flag + * | | |This bit indicates that a stop condition has been detected on the I2C bus lines + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.STORIEN = 1. + * | | |0 = A stop condition has not yet been detected. + * | | |1 = A stop condition has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave RX mode. + * |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag + * | | |This bit indicates that a non - acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.NACKIEN = 1. + * | | |0 = A non - acknowledge has not been received. + * | | |1 = A non - acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[11] |ARBLOIF |Arbitration Lost Interrupt Flag + * | | |This bit indicates that an arbitration has been lost + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ARBLOIEN = 1. + * | | |0 = An arbitration has not been lost. + * | | |1 = An arbitration has been lost. + * | | |It is cleared by software writing one into this bit + * |[12] |ERRIF |Error Interrupt Flag + * | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame + * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ERRIEN = 1. + * | | |0 = An I2C error has not been detected. + * | | |1 = An I2C error has been detected. + * | | |It is cleared by software writing one into this bit + * | | |Note: This bit is set when slave mode, user must write one into STO register to the defined not addressed slave mode. + * |[13] |ACKIF |Acknowledge Received Interrupt Flag + * | | |This bit indicates that an acknowledge has been received in master mode + * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ACKIEN = 1. + * | | |0 = An acknowledge has not been received. + * | | |1 = An acknowledge has been received. + * | | |It is cleared by software writing one into this bit + * |[14] |SLASEL |Slave Select Status + * | | |This bit indicates that this device has been selected as slave. + * | | |0 = The device is not selected as slave. + * | | |1 = The device is selected as slave. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[15] |SLAREAD |Slave Read Request Status + * | | |This bit indicates that a slave read request has been detected. + * | | |0 = A slave R/W bit is 1 has not been detected. + * | | |1 = A slave R/W bit is 1 has been detected. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. + * |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done + * | | |0 = The ACK bit cycle of address match frame isn't done. + * | | |1 = The ACK bit cycle of address match frame is done in power-down. + * | | |Note: This bit can't release when WKUPIF is set. + * |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame + * | | |0 = Write command be record on the address match wakeup frame. + * | | |1 = Read command be record on the address match wakeup frame. + * |[18] |BUSHANG |Bus Hang-up + * | | |This bit indicates bus hang-up status + * | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK + * | | |The hang-up counter will count to overflow and set this bit when SDA is low + * | | |The counter will be reset by falling edge of SCL signal. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is hang-up status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * |[19] |ERRARBLO |Error Arbitration Lost + * | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor + * | | |The I2C can send start condition when ERRARBLO is set + * | | |Thus this bit doesn't be cared on slave mode. + * | | |0 = The bus is normal status for transmission. + * | | |1 = The bus is error arbitration lost status for transmission. + * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. + * @var UI2C_T::ADMAT + * Offset: 0x88 I2C Slave Match Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |ADMAT0 |USCI Address 0 Match Status Register + * | | |When address 0 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * |[1] |ADMAT1 |USCI Address 1 Match Status Register + * | | |When address 1 is matched, hardware will inform which address used + * | | |This bit will set to 1, and software can write 1 to clear this bit. + * @var UI2C_T::TMCTL + * Offset: 0x8C I2C Timing Configure Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |STCTL |Setup Time Configure Control Register + * | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.. + * | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK. + * |[24:16] |HTCTL |Hold Time Configure Control Register + * | | |This field is used to generate the delay timing between SCL falling edge SDA edge in + * | | |transmission mode. + * | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + __I uint32_t RESERVE1[8]; + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __I uint32_t RESERVE2[3]; + __IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */ + __IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */ + __IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */ + __IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */ + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + __I uint32_t RESERVE3[8]; + __IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */ + __IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */ + +} UI2C_T; + +/** + @addtogroup UI2C_CONST UI2C Bit Field Definition + Constant Definitions for UI2C Controller + @{ +*/ + +#define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */ +#define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */ + +#define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */ +#define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */ + +#define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */ +#define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */ + +#define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */ +#define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */ + +#define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */ +#define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */ + +#define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */ +#define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */ + +#define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */ +#define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */ + +#define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */ +#define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */ + +#define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */ +#define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */ + +#define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */ +#define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */ + +#define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */ +#define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */ + +#define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */ +#define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */ + +#define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */ +#define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */ + +#define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */ +#define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */ + +#define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */ +#define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */ + +#define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */ +#define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */ + +#define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */ +#define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */ + +#define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */ +#define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */ + +#define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */ +#define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */ + +#define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */ +#define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */ + +#define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */ +#define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */ + +#define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */ +#define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */ + +#define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */ +#define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */ + +#define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */ +#define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */ + +#define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */ +#define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */ + +#define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */ +#define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */ + +#define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */ +#define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */ + +#define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */ +#define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */ + +#define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */ +#define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */ + +#define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */ +#define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */ + +#define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */ +#define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */ + +#define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */ +#define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */ + +#define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */ +#define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */ + +#define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */ +#define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */ + +#define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */ +#define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */ + +#define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */ +#define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */ + +#define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */ +#define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */ + +#define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */ +#define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */ + +#define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */ +#define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */ + +#define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */ +#define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */ + +#define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */ +#define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */ + +#define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */ +#define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */ + +#define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */ +#define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */ + +#define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */ +#define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */ + +#define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */ +#define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */ + +#define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */ +#define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */ + +#define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */ +#define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */ + +#define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */ +#define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */ + +#define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */ +#define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */ + +#define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */ +#define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */ + +#define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */ +#define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */ + +#define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */ +#define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */ + +#define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */ +#define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */ + +#define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */ +#define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */ + +#define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */ +#define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */ + +/**@}*/ /* UI2C_CONST */ +/**@}*/ /* end of UI2C register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __UI2C_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/usbd_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/usbd_reg.h new file mode 100644 index 0000000000..ca5e9b430d --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/usbd_reg.h @@ -0,0 +1,658 @@ +/**************************************************************************//** + * @file usbd_reg.h + * @version V1.00 + * @brief USBD register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBD_REG_H__ +#define __USBD_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- USB Device Controller -------------------------*/ +/** + @addtogroup USBD USB Device Controller(USBD) + Memory Mapped Structure for USBD Controller + @{ +*/ + + + +/** + * @brief USBD endpoints register + */ +typedef struct +{ + /** + * @var USBD_EP_T::BUFSEG + * Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570/0x580/0x590/0x5A0/0x5B0 Endpoint Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |BUFSEG |Endpoint Buffer Segmentation + * | | |It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is + * | | |USBD_SRAM address + {BUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Refer to the section 6.32.5.7 for the endpoint SRAM structure and its description. + * @var USBD_EP_T::MXPLD + * Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574/0x584/0x594/0x5A4/0x5B4 Endpoint Maximal Payload Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:0] |MXPLD |Maximal Payload + * | | |Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token) + * | | |It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token. + * | | |(1) When the register is written by CPU, + * | | |For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready. + * | | |For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host. + * | | |(2) When the register is read by CPU, + * | | |For IN token, the value of MXPLD is indicated by the data length be transmitted to host. + * | | |For OUT token, the value of MXPLD is indicated the actual data length receiving from host. + * | | |Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived. + * @var USBD_EP_T::CFG + * Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578/0x588/0x598/0x5A8/0x5B8 Endpoint Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPNUM |Endpoint Number + * | | |These bits are used to define the endpoint number of the current endpoint. + * |[4] |ISOCH |Isochronous Endpoint + * | | |This bit is used to set the endpoint as Isochronous endpoint, no handshake. + * | | |0 = No Isochronous endpoint. + * | | |1 = Isochronous endpoint. + * |[6:5] |STATE |Endpoint State + * | | |00 = Endpoint Disabled. + * | | |01 = Out endpoint. + * | | |10 = IN endpoint. + * | | |11 = Undefined. + * |[7] |DSQSYNC |Data Sequence Synchronization + * | | |0 = DATA0 PID. + * | | |1 = DATA1 PID. + * | | |For IN token, DSQSYNC specify DATA0 or DATA1 PID in transfer data packet. + * | | |For OUT token, DSQSYNC specify DATA0 or DATA1 PID in received data packet. + * | | |DSQSYNC will be toggled automatically by hardware when IN or OUT token transfer successfully in single buffer mode, but won’t be toggled in double buffer mode. + * | | |Note 1: When double buffer is enabled, hardware will automatically write 0 to DSQSYNC with active double buffer and write 1 to DSQSYNC with inactive double buffer. + * | | |Note 2: It won’t be toggled by hardware when DBEN = 1. USB data toggle will be guaranteed by changing endpoint. + * |[9] |CSTALL |Clear STALL Response + * | | |0 = Disable the device to clear the STALL handshake in setup stage. + * | | |1 = Clear the device to response STALL handshake in setup stage. + * |[10] |DBTGACTIVE|Double Buffer Toggle Active Bit + * | | |0 = Inactive in double buffer mode. + * | | |1 = Active in double buffer mode. + * | | |When DBEN = 1 and endpoint successful transfer, DBTGACTIVE of each double buffer will be toggled automatically by hardware. + * |[11] |DBEN |Double Buffer Enable + * | | |0 = Single buffer mode. + * | | |1 = Double buffer mode. + * @var USBD_EP_T::CFGP + * Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C/0x58C/0x59C/0x5AC/0x5BC Endpoint Set Stall and Clear In/Out Ready Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CLRRDY |Clear Ready + * | | |When the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data + * | | |If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is automatically cleared to 0. + * | | |For IN token, write '1' to clear the IN token had ready to transmit the data to USB. + * | | |For OUT token, write '1' to clear the OUT token had ready to receive the data from USB. + * | | |This bit is written 1 only and is always 0 when it is read back. + * |[1] |SSTALL |Set STALL + * | | |0 = Disable the device to response STALL. + * | | |1 = Set the device to respond STALL automatically. + */ + __IO uint32_t BUFSEG; /*!< [0x0000] Endpoint Buffer Segmentation Register */ + __IO uint32_t MXPLD; /*!< [0x0004] Endpoint Maximal Payload Register */ + __IO uint32_t CFG; /*!< [0x0008] Endpoint Configuration Register */ + __IO uint32_t CFGP; /*!< [0x000c] Endpoint Set Stall and Clear In/Out Ready Control Register */ + +} USBD_EP_T; + +typedef struct +{ + + + /** + * @var USBD_T::INTEN + * Offset: 0x00 USB Device Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIEN |Bus Event Interrupt Enable Bit + * | | |0 = BUS event interrupt Disabled. + * | | |1 = BUS event interrupt Enabled. + * |[1] |USBIEN |USB Event Interrupt Enable Bit + * | | |0 = USB event interrupt Disabled. + * | | |1 = USB event interrupt Enabled. + * |[2] |VBDETIEN |VBUS Detection Interrupt Enable Bit + * | | |0 = VBUS detection Interrupt Disabled. + * | | |1 = VBUS detection Interrupt Enabled. + * |[3] |NEVWKIEN |USB No-event-wake-up Interrupt Enable Bit + * | | |0 = No-event-wake-up Interrupt Disabled. + * | | |1 = No-event-wake-up Interrupt Enabled. + * |[4] |SOFIEN |Start of Frame Interrupt Enable Bit + * | | |0 = SOF Interrupt Disabled. + * | | |1 = SOF Interrupt Enabled. + * |[8] |WKEN |Wake-up Function Enable Bit + * | | |0 = USB wake-up function Disabled. + * | | |1 = USB wake-up function Enabled. + * |[15] |INNAKEN |Active NAK Function and Its Status in IN Token + * | | |0 = When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS0 and USBD_EPSTS1register, so that the USB interrupt event will not be asserted. + * | | |1 = IN NAK status will be updated to USBD_EPSTS0 and USBD_EPSTS1 register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token. + * @var USBD_T::INTSTS + * Offset: 0x04 USB Device Interrupt Event Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |BUSIF |BUS Interrupt Status + * | | |The BUS event means that there is one of the suspense or the resume function in the bus. + * | | |0 = No BUS event occurred. + * | | |1 = Bus event occurred. Check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by writing 1 to USBD_INTSTS[0]. + * |[1] |USBIF |USB Event Interrupt Status + * | | |The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus. + * | | |0 = No USB event occurred. + * | | |1 = USB event occurred. Check EPSTS0~11[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[1] or EPSTS0~11 and SETUP (USBD_INTSTS[31]). + * |[2] |VBDETIF |VBUS Detection Interrupt Status + * | | |0 = There is no attached/detached event in the USB. + * | | |1 = There is attached/detached event in the USB bus and it is cleared by writing 1 to USBD_INTSTS[2]. + * |[3] |NEVWKIF |No-event-wake-up Interrupt Status + * | | |0 = NEVWK event did not occur. + * | | |1 = No-event-wake-up event occurred, cleared by writing 1 to USBD_INTSTS[3]. + * |[4] |SOFIF |Start of Frame Interrupt Status + * | | |0 = SOF event did not occur. + * | | |1 = SOF event occurred, cleared by writing 1 to USBD_INTSTS[4]. + * |[16] |EPEVT0 |Endpoint 0's USB Event Status + * | | |0 = No event occurred in endpoint 0. + * | | |1 = USB event occurred on Endpoint 0. Check USBD_EPSTS0[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[16] or USBD_INTSTS[1]. + * |[17] |EPEVT1 |Endpoint 1's USB Event Status + * | | |0 = No event occurred in endpoint 1. + * | | |1 = USB event occurred on Endpoint 1. Check USBD_EPSTS0[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[17] or USBD_INTSTS[1]. + * |[18] |EPEVT2 |Endpoint 2's USB Event Status + * | | |0 = No event occurred in endpoint 2. + * | | |1 = USB event occurred on Endpoint 2. Check USBD_EPSTS0[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[18] or USBD_INTSTS[1]. + * |[19] |EPEVT3 |Endpoint 3's USB Event Status + * | | |0 = No event occurred in endpoint 3. + * | | |1 = USB event occurred on Endpoint 3. Check USBD_EPSTS0[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[19] or USBD_INTSTS[1]. + * |[20] |EPEVT4 |Endpoint 4's USB Event Status + * | | |0 = No event occurred in endpoint 4. + * | | |1 = USB event occurred on Endpoint 4. Check USBD_EPSTS0[19:16] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[20] or USBD_INTSTS[1]. + * |[21] |EPEVT5 |Endpoint 5's USB Event Status + * | | |0 = No event occurred in endpoint 5. + * | | |1 = USB event occurred on Endpoint 5. Check USBD_EPSTS0[23:20] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[21] or USBD_INTSTS[1]. + * |[22] |EPEVT6 |Endpoint 6's USB Event Status + * | | |0 = No event occurred in endpoint 6. + * | | |1 = USB event occurred on Endpoint 6. Check USBD_EPSTS0[27:24] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[22] or USBD_INTSTS[1]. + * |[23] |EPEVT7 |Endpoint 7's USB Event Status + * | | |0 = No event occurred in endpoint 7. + * | | |1 = USB event occurred on Endpoint 7. Check USBD_EPSTS0[31:28] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[23] or USBD_INTSTS[1]. + * |[24] |EPEVT8 |Endpoint 8's USB Event Status + * | | |0 = No event occurred in endpoint 8. + * | | |1 = USB event occurred on Endpoint 8. Check USBD_EPSTS1[3:0] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[24] or USBD_INTSTS[1]. + * |[25] |EPEVT9 |Endpoint 9's USB Event Status + * | | |0 = No event occurred in endpoint 9. + * | | |1 = USB event occurred on Endpoint 9. Check USBD_EPSTS1[7:4] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[25] or USBD_INTSTS[1]. + * |[26] |EPEVT10 |Endpoint 10's USB Event Status + * | | |0 = No event occurred in endpoint 10. + * | | |1 = USB event occurred on Endpoint 10. Check USBD_EPSTS1[11:8] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[26] or USBD_INTSTS[1]. + * |[27] |EPEVT11 |Endpoint 11's USB Event Status + * | | |0 = No event occurred in endpoint 11. + * | | |1 = USB event occurred on Endpoint 11. Check USBD_EPSTS1[15:12] to know which kind of USB event was occurred, cleared by writing 1 to USBD_INTSTS[27] or USBD_INTSTS[1]. + * |[31] |SETUP |Setup Event Status + * | | |0 = No Setup event. + * | | |1 = Setup event occurred, cleared by writing 1 to USBD_INTSTS[31]. + * @var USBD_T::FADDR + * Offset: 0x08 USB Device Function Address Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6:0] |FADDR |USB Device Function Address + * @var USBD_T::EPSTS + * Offset: 0x0C USB Device Endpoint Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |OV |Overrun + * | | |It indicates that the received data is over the maximum payload number or not. + * | | |0 = No overrun. + * | | |1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 bytes. + * @var USBD_T::ATTR + * Offset: 0x10 USB Device Bus Status and Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |USBRST |USB Reset Status (Read Only) + * | | |0 = Bus no reset. + * | | |1 = Bus reset when SE0 (single-ended 0) more than 2.5us. + * |[1] |SUSPEND |Suspend Status (Read Only) + * | | |0 = Bus no suspend. + * | | |1 = Bus idle more than 3ms, either cable is plugged-out or host is sleeping. + * |[2] |RESUME |Resume Status (Read Only) + * | | |0 = No bus resume. + * | | |1 = Resume from suspend. + * |[3] |TOUT |Time-out Status (Read Only) + * | | |0 = No time-out. + * | | |1 = No Bus response more than 18 bits time. + * |[4] |PHYEN |PHY Transceiver Function Enable Bit + * | | |0 = PHY transceiver function Disabled. + * | | |1 = PHY transceiver function Enabled. + * |[5] |RWAKEUP |Remote Wake-up + * | | |0 = Release the USB bus from K state. + * | | |1 = Force USB bus to K (USB_D+ low, USB_D-: high) state, used for remote wake-up. + * |[7] |USBEN |USB Controller Enable Bit + * | | |0 = USB Controller Disabled. + * | | |1 = USB Controller Enabled. + * |[8] |DPPUEN |Pull-up Resistor on USB_DP Enable Bit + * | | |0 = Pull-up resistor in USB_D+ bus Disabled. + * | | |1 = Pull-up resistor in USB_D+ bus Active. + * |[10] |BYTEM |CPU Access USB SRAM Size Mode Selection + * | | |0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only. + * | | |1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only. + * |[11] |LPMACK |LPM Token Acknowledge Enable Bit + * | | |The NYET/ACK will be returned only on a successful LPM transaction if no errors in both the EXT token and the LPM token and a valid bLinkState = 0001 (L1) is received, else ERROR and STALL will be returned automatically, respectively. + * | | |0= The valid LPM Token will be NYET. + * | | |1= The valid LPM Token will be ACK. + * |[12] |L1SUSPEND |LPM L1 Suspend (Read Only) + * | | |0 = Bus no L1 state suspend. + * | | |1 = This bit is set by the hardware when LPM command to enter the L1 state is successfully received and acknowledged. + * |[13] |L1RESUME |LPM L1 Resume (Read Only) + * | | |0 = Bus no LPM L1 state resume. + * | | |1 = LPM L1 state resume from LPM L1 state suspend. + * @var USBD_T::VBUSDET + * Offset: 0x14 USB Device VBUS Detection Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |VBUSDET |Device VBUS Detection + * | | |0 = Controller is not attached to the USB host. + * | | |1 = Controller is attached to the USB host. + * @var USBD_T::STBUFSEG + * Offset: 0x18 SETUP Token Buffer Segmentation Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[8:3] |STBUFSEG |SETUP Token Buffer Segmentation + * | | |It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is + * | | |USBD_SRAM address + {STBUFSEG, 3'b000} + * | | |Where the USBD_SRAM address = USBD_BA+0x100h. + * | | |Note: It is used for SETUP token only. + * @var USBD_T::EPSTS0 + * Offset: 0x20 USB Device Endpoint Status Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPSTS0 |Endpoint 0 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[7:4] |EPSTS1 |Endpoint 1 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:8] |EPSTS2 |Endpoint 2 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS3 |Endpoint 3 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[19:16] |EPSTS4 |Endpoint 4 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[23:20] |EPSTS5 |Endpoint 5 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[27:24] |EPSTS6 |Endpoint 6 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[31:28] |EPSTS7 |Endpoint 7 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::EPSTS1 + * Offset: 0x24 USB Device Endpoint Status Register 1 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |EPSTS8 |Endpoint 8 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[7:4] |EPSTS9 |Endpoint 9 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[11:8] |EPSTS10 |Endpoint 10 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * |[15:12] |EPSTS11 |Endpoint 11 Status + * | | |These bits are used to indicate the current status of this endpoint. + * | | |0000 = In ACK. + * | | |0001 = In NAK. + * | | |0010 = Out Packet Data0 ACK. + * | | |0110 = Out Packet Data1 ACK. + * | | |0111 = Isochronous transfer end. + * @var USBD_T::LPMATTR + * Offset: 0x88 USB LPM Attribution Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[3:0] |LPMLINKSTS|LPM Link State + * | | |These bits contain the bLinkState received with last ACK LPM Token. + * | | |0000 = Reserve. + * | | |0001 = L1 (Sleep). + * | | |0010 - 1111 = Reserve. + * |[7:4] |LPMBESL |LPM Best Effort Service Latency + * | | |These bits contain the BESL value received with last ACK LPM Token. + * | | |0000 = 125us. + * | | |0001 = 150us. + * | | |0010 = 200us. + * | | |0011 = 300us. + * | | |0100 = 400us. + * | | |0101 = 500us. + * | | |0110 = 1000us. + * | | |0111 = 2000us. + * | | |1000 = 3000us. + * | | |1001 = 4000us. + * | | |1010 = 5000us. + * | | |1011 = 6000us. + * | | |1100 = 7000us. + * | | |1101 = 8000us. + * | | |1110 = 9000us. + * | | |1111 = 10000us. + * |[8] |LPMRWAKUP |LPM Remote Wakeup + * | | |This bit contains the bRemoteWake value received with last ACK LPM Token. + * @var USBD_T::FN + * Offset: 0x8C USB Frame Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[10:0] |FN |Frame Number + * | | |These bits contain the 11-bits frame number in the last received SOF packet. + * @var USBD_T::SE0 + * Offset: 0x90 USB Device Drive SE0 Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SE0 |Drive Single Ended Zero in USB Bus + * | | |The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low. + * | | |0 = Normal operation. + * | | |1 = Force USB PHY transceiver to drive SE0. + */ + __IO uint32_t INTEN; /*!< [0x0000] USB Device Interrupt Enable Register */ + __IO uint32_t INTSTS; /*!< [0x0004] USB Device Interrupt Event Status Register */ + __IO uint32_t FADDR; /*!< [0x0008] USB Device Function Address Register */ + __I uint32_t EPSTS; /*!< [0x000c] USB Device Endpoint Status Register */ + __IO uint32_t ATTR; /*!< [0x0010] USB Device Bus Status and Attribution Register */ + __I uint32_t VBUSDET; /*!< [0x0014] USB Device VBUS Detection Register */ + __IO uint32_t STBUFSEG; /*!< [0x0018] SETUP Token Buffer Segmentation Register */ + __I uint32_t RESERVE0[1]; + __I uint32_t EPSTS0; /*!< [0x0020] USB Device Endpoint Status Register 0 */ + __I uint32_t EPSTS1; /*!< [0x0024] USB Device Endpoint Status Register 1 */ + __I uint32_t RESERVE1[24]; + __I uint32_t LPMATTR; /*!< [0x0088] USB LPM Attribution Register */ + __I uint32_t FN; /*!< [0x008c] USB Frame Number Register */ + __IO uint32_t SE0; /*!< [0x0090] USB Device Drive SE0 Control Register */ + __I uint32_t RESERVE2[283]; + USBD_EP_T EP[12]; /*!< [0x500~0x5bc] USB End Point 0 ~ 11 Configuration Register */ + +} USBD_T; + +/** + @addtogroup USBD_CONST USBD Bit Field Definition + Constant Definitions for USBD Controller + @{ +*/ + +#define USBD_INTEN_BUSIEN_Pos (0) /*!< USBD_T::INTEN: BUSIEN Position */ +#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) /*!< USBD_T::INTEN: BUSIEN Mask */ + +#define USBD_INTEN_USBIEN_Pos (1) /*!< USBD_T::INTEN: USBIEN Position */ +#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) /*!< USBD_T::INTEN: USBIEN Mask */ + +#define USBD_INTEN_VBDETIEN_Pos (2) /*!< USBD_T::INTEN: VBDETIEN Position */ +#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) /*!< USBD_T::INTEN: VBDETIEN Mask */ + +#define USBD_INTEN_NEVWKIEN_Pos (3) /*!< USBD_T::INTEN: NEVWKIEN Position */ +#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) /*!< USBD_T::INTEN: NEVWKIEN Mask */ + +#define USBD_INTEN_SOFIEN_Pos (4) /*!< USBD_T::INTEN: SOFIEN Position */ +#define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) /*!< USBD_T::INTEN: SOFIEN Mask */ + +#define USBD_INTEN_WKEN_Pos (8) /*!< USBD_T::INTEN: WKEN Position */ +#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) /*!< USBD_T::INTEN: WKEN Mask */ + +#define USBD_INTEN_INNAKEN_Pos (15) /*!< USBD_T::INTEN: INNAKEN Position */ +#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) /*!< USBD_T::INTEN: INNAKEN Mask */ + +#define USBD_INTSTS_BUSIF_Pos (0) /*!< USBD_T::INTSTS: BUSIF Position */ +#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) /*!< USBD_T::INTSTS: BUSIF Mask */ + +#define USBD_INTSTS_USBIF_Pos (1) /*!< USBD_T::INTSTS: USBIF Position */ +#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) /*!< USBD_T::INTSTS: USBIF Mask */ + +#define USBD_INTSTS_VBDETIF_Pos (2) /*!< USBD_T::INTSTS: VBDETIF Position */ +#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) /*!< USBD_T::INTSTS: VBDETIF Mask */ + +#define USBD_INTSTS_NEVWKIF_Pos (3) /*!< USBD_T::INTSTS: NEVWKIF Position */ +#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) /*!< USBD_T::INTSTS: NEVWKIF Mask */ + +#define USBD_INTSTS_SOFIF_Pos (4) /*!< USBD_T::INTSTS: SOFIF Position */ +#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) /*!< USBD_T::INTSTS: SOFIF Mask */ + +#define USBD_INTSTS_EPEVT0_Pos (16) /*!< USBD_T::INTSTS: EPEVT0 Position */ +#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) /*!< USBD_T::INTSTS: EPEVT0 Mask */ + +#define USBD_INTSTS_EPEVT1_Pos (17) /*!< USBD_T::INTSTS: EPEVT1 Position */ +#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) /*!< USBD_T::INTSTS: EPEVT1 Mask */ + +#define USBD_INTSTS_EPEVT2_Pos (18) /*!< USBD_T::INTSTS: EPEVT2 Position */ +#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) /*!< USBD_T::INTSTS: EPEVT2 Mask */ + +#define USBD_INTSTS_EPEVT3_Pos (19) /*!< USBD_T::INTSTS: EPEVT3 Position */ +#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) /*!< USBD_T::INTSTS: EPEVT3 Mask */ + +#define USBD_INTSTS_EPEVT4_Pos (20) /*!< USBD_T::INTSTS: EPEVT4 Position */ +#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) /*!< USBD_T::INTSTS: EPEVT4 Mask */ + +#define USBD_INTSTS_EPEVT5_Pos (21) /*!< USBD_T::INTSTS: EPEVT5 Position */ +#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) /*!< USBD_T::INTSTS: EPEVT5 Mask */ + +#define USBD_INTSTS_EPEVT6_Pos (22) /*!< USBD_T::INTSTS: EPEVT6 Position */ +#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) /*!< USBD_T::INTSTS: EPEVT6 Mask */ + +#define USBD_INTSTS_EPEVT7_Pos (23) /*!< USBD_T::INTSTS: EPEVT7 Position */ +#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) /*!< USBD_T::INTSTS: EPEVT7 Mask */ + +#define USBD_INTSTS_EPEVT8_Pos (24) /*!< USBD_T::INTSTS: EPEVT8 Position */ +#define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) /*!< USBD_T::INTSTS: EPEVT8 Mask */ + +#define USBD_INTSTS_EPEVT9_Pos (25) /*!< USBD_T::INTSTS: EPEVT9 Position */ +#define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) /*!< USBD_T::INTSTS: EPEVT9 Mask */ + +#define USBD_INTSTS_EPEVT10_Pos (26) /*!< USBD_T::INTSTS: EPEVT10 Position */ +#define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) /*!< USBD_T::INTSTS: EPEVT10 Mask */ + +#define USBD_INTSTS_EPEVT11_Pos (27) /*!< USBD_T::INTSTS: EPEVT11 Position */ +#define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) /*!< USBD_T::INTSTS: EPEVT11 Mask */ + +#define USBD_INTSTS_SETUP_Pos (31) /*!< USBD_T::INTSTS: SETUP Position */ +#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) /*!< USBD_T::INTSTS: SETUP Mask */ + +#define USBD_FADDR_FADDR_Pos (0) /*!< USBD_T::FADDR: FADDR Position */ +#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD_T::FADDR: FADDR Mask */ + +#define USBD_EPSTS_OV_Pos (7) /*!< USBD_T::EPSTS: OV Position */ +#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) /*!< USBD_T::EPSTS: OV Mask */ + +#define USBD_ATTR_USBRST_Pos (0) /*!< USBD_T::ATTR: USBRST Position */ +#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) /*!< USBD_T::ATTR: USBRST Mask */ + +#define USBD_ATTR_SUSPEND_Pos (1) /*!< USBD_T::ATTR: SUSPEND Position */ +#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) /*!< USBD_T::ATTR: SUSPEND Mask */ + +#define USBD_ATTR_RESUME_Pos (2) /*!< USBD_T::ATTR: RESUME Position */ +#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) /*!< USBD_T::ATTR: RESUME Mask */ + +#define USBD_ATTR_TOUT_Pos (3) /*!< USBD_T::ATTR: TOUT Position */ +#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) /*!< USBD_T::ATTR: TOUT Mask */ + +#define USBD_ATTR_PHYEN_Pos (4) /*!< USBD_T::ATTR: PHYEN Position */ +#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) /*!< USBD_T::ATTR: PHYEN Mask */ + +#define USBD_ATTR_RWAKEUP_Pos (5) /*!< USBD_T::ATTR: RWAKEUP Position */ +#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) /*!< USBD_T::ATTR: RWAKEUP Mask */ + +#define USBD_ATTR_USBEN_Pos (7) /*!< USBD_T::ATTR: USBEN Position */ +#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) /*!< USBD_T::ATTR: USBEN Mask */ + +#define USBD_ATTR_DPPUEN_Pos (8) /*!< USBD_T::ATTR: DPPUEN Position */ +#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) /*!< USBD_T::ATTR: DPPUEN Mask */ + +#define USBD_ATTR_BYTEM_Pos (10) /*!< USBD_T::ATTR: BYTEM Position */ +#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) /*!< USBD_T::ATTR: BYTEM Mask */ + +#define USBD_ATTR_LPMACK_Pos (11) /*!< USBD_T::ATTR: LPMACK Position */ +#define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) /*!< USBD_T::ATTR: LPMACK Mask */ + +#define USBD_ATTR_L1SUSPEND_Pos (12) /*!< USBD_T::ATTR: L1SUSPEND Position */ +#define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) /*!< USBD_T::ATTR: L1SUSPEND Mask */ + +#define USBD_ATTR_L1RESUME_Pos (13) /*!< USBD_T::ATTR: L1RESUME Position */ +#define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) /*!< USBD_T::ATTR: L1RESUME Mask */ + +#define USBD_VBUSDET_VBUSDET_Pos (0) /*!< USBD_T::VBUSDET: VBUSDET Position */ +#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) /*!< USBD_T::VBUSDET: VBUSDET Mask */ + +#define USBD_STBUFSEG_STBUFSEG_Pos (3) /*!< USBD_T::STBUFSEG: STBUFSEG Position */ +#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) /*!< USBD_T::STBUFSEG: STBUFSEG Mask */ + +#define USBD_EPSTS0_EPSTS0_Pos (0) /*!< USBD_T::EPSTS0: EPSTS0 Position */ +#define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) /*!< USBD_T::EPSTS0: EPSTS0 Mask */ + +#define USBD_EPSTS0_EPSTS1_Pos (4) /*!< USBD_T::EPSTS0: EPSTS1 Position */ +#define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) /*!< USBD_T::EPSTS0: EPSTS1 Mask */ + +#define USBD_EPSTS0_EPSTS2_Pos (8) /*!< USBD_T::EPSTS0: EPSTS2 Position */ +#define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) /*!< USBD_T::EPSTS0: EPSTS2 Mask */ + +#define USBD_EPSTS0_EPSTS3_Pos (12) /*!< USBD_T::EPSTS0: EPSTS3 Position */ +#define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) /*!< USBD_T::EPSTS0: EPSTS3 Mask */ + +#define USBD_EPSTS0_EPSTS4_Pos (16) /*!< USBD_T::EPSTS0: EPSTS4 Position */ +#define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) /*!< USBD_T::EPSTS0: EPSTS4 Mask */ + +#define USBD_EPSTS0_EPSTS5_Pos (20) /*!< USBD_T::EPSTS0: EPSTS5 Position */ +#define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) /*!< USBD_T::EPSTS0: EPSTS5 Mask */ + +#define USBD_EPSTS0_EPSTS6_Pos (24) /*!< USBD_T::EPSTS0: EPSTS6 Position */ +#define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) /*!< USBD_T::EPSTS0: EPSTS6 Mask */ + +#define USBD_EPSTS0_EPSTS7_Pos (28) /*!< USBD_T::EPSTS0: EPSTS7 Position */ +#define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) /*!< USBD_T::EPSTS0: EPSTS7 Mask */ + +#define USBD_EPSTS1_EPSTS8_Pos (0) /*!< USBD_T::EPSTS1: EPSTS8 Position */ +#define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) /*!< USBD_T::EPSTS1: EPSTS8 Mask */ + +#define USBD_EPSTS1_EPSTS9_Pos (4) /*!< USBD_T::EPSTS1: EPSTS9 Position */ +#define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) /*!< USBD_T::EPSTS1: EPSTS9 Mask */ + +#define USBD_EPSTS1_EPSTS10_Pos (8) /*!< USBD_T::EPSTS1: EPSTS10 Position */ +#define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) /*!< USBD_T::EPSTS1: EPSTS10 Mask */ + +#define USBD_EPSTS1_EPSTS11_Pos (12) /*!< USBD_T::EPSTS1: EPSTS11 Position */ +#define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) /*!< USBD_T::EPSTS1: EPSTS11 Mask */ + +#define USBD_LPMATTR_LPMLINKSTS_Pos (0) /*!< USBD_T::LPMATTR: LPMLINKSTS Position */ +#define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) /*!< USBD_T::LPMATTR: LPMLINKSTS Mask */ + +#define USBD_LPMATTR_LPMBESL_Pos (4) /*!< USBD_T::LPMATTR: LPMBESL Position */ +#define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) /*!< USBD_T::LPMATTR: LPMBESL Mask */ + +#define USBD_LPMATTR_LPMRWAKUP_Pos (8) /*!< USBD_T::LPMATTR: LPMRWAKUP Position */ +#define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) /*!< USBD_T::LPMATTR: LPMRWAKUP Mask */ + +#define USBD_FN_FN_Pos (0) /*!< USBD_T::FN: FN Position */ +#define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) /*!< USBD_T::FN: FN Mask */ + +#define USBD_SE0_SE0_Pos (0) /*!< USBD_T::SE0: SE0 Position */ +#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) /*!< USBD_T::SE0: SE0 Mask */ + +#define USBD_BUFSEG_BUFSEG_Pos (3) /*!< USBD_EP_T::BUFSEG: BUFSEG Position */ +#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) /*!< USBD_EP_T::BUFSEG: BUFSEG Mask */ + +#define USBD_MXPLD_MXPLD_Pos (0) /*!< USBD_EP_T::MXPLD: MXPLD Position */ +#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) /*!< USBD_EP_T::MXPLD: MXPLD Mask */ + +#define USBD_CFG_EPNUM_Pos (0) /*!< USBD_EP_T::CFG: EPNUM Position */ +#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) /*!< USBD_EP_T::CFG: EPNUM Mask */ + +#define USBD_CFG_ISOCH_Pos (4) /*!< USBD_EP_T::CFG: ISOCH Position */ +#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) /*!< USBD_EP_T::CFG: ISOCH Mask */ + +#define USBD_CFG_STATE_Pos (5) /*!< USBD_EP_T::CFG: STATE Position */ +#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) /*!< USBD_EP_T::CFG: STATE Mask */ + +#define USBD_CFG_DSQSYNC_Pos (7) /*!< USBD_EP_T::CFG: DSQSYNC Position */ +#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) /*!< USBD_EP_T::CFG: DSQSYNC Mask */ + +#define USBD_CFG_CSTALL_Pos (9) /*!< USBD_EP_T::CFG: CSTALL Position */ +#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) /*!< USBD_EP_T::CFG: CSTALL Mask */ + +#define USBD_CFG_DBTGACTIVE_Pos (10) /*!< USBD_EP_T::CFG: DBTGACTIVE Position */ +#define USBD_CFG_DBTGACTIVE_Msk (0x1ul << USBD_CFG_DBTGACTIVE_Pos) /*!< USBD_EP_T::CFG: DBTGACTIVE Mask */ + +#define USBD_CFG_DBEN_Pos (11) /*!< USBD_EP_T::CFG: DBEN Position */ +#define USBD_CFG_DBEN_Msk (0x1ul << USBD_CFG_DBEN_Pos) /*!< USBD_EP_T::CFG: DBEN Mask */ + +#define USBD_CFGP_CLRRDY_Pos (0) /*!< USBD_EP_T::CFGP: CLRRDY Position */ +#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) /*!< USBD_EP_T::CFGP: CLRRDY Mask */ + +#define USBD_CFGP_SSTALL_Pos (1) /*!< USBD_EP_T::CFGP: SSTALL Position */ +#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /*!< USBD_EP_T::CFGP: SSTALL Mask */ + +/**@}*/ /* USBD_CONST */ +/**@}*/ /* end of USBD register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __USBD_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/usbh_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/usbh_reg.h new file mode 100644 index 0000000000..eabb714182 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/usbh_reg.h @@ -0,0 +1,799 @@ +/**************************************************************************//** + * @file usbh_reg.h + * @version V1.00 + * @brief USBH register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USBH_REG_H__ +#define __USBH_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- USB Host Controller -------------------------*/ +/** + @addtogroup USBH USB Host Controller(USBH) + Memory Mapped Structure for USBH Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var USBH_T::HcRevision + * Offset: 0x00 Host Controller Revision Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |REV |Revision Number + * | | |Indicates the Open HCI Specification revision number implemented by the Hardware + * | | |Host Controller supports 1.1 specification. + * | | |(X.Y = XYh). + * @var USBH_T::HcControl + * Offset: 0x04 Host Controller Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |CBSR |Control Bulk Service Ratio + * | | |This specifies the service ratio between Control and Bulk EDs + * | | |Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs + * | | |The internal count will be retained when crossing the frame boundary + * | | |In case of reset, HCD is responsible for restoring this value. + * | | |00 = Number of Control EDs over Bulk EDs served is 1:1. + * | | |01 = Number of Control EDs over Bulk EDs served is 2:1. + * | | |10 = Number of Control EDs over Bulk EDs served is 3:1. + * | | |11 = Number of Control EDs over Bulk EDs served is 4:1. + * |[2] |PLE |Periodic List Enable Bit + * | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list + * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame. + * | | |0 = Processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Periodic (Interrupt and Isochronous) list in the next frame Enabled. + * | | |Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high. + * |[3] |IE |Isochronous List Enable Bit + * | | |Both IE and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list + * | | |Either IE or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list. + * | | |0 = Processing of the Isochronous list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Isochronous list in the next frame Enabled, if the PLE (HcControl[2]) is high, too. + * |[4] |CLE |Control List Enable Bit + * | | |0 = Processing of the Control list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Control list in the next frame Enabled. + * |[5] |BLE |Bulk List Enable Bit + * | | |0 = Processing of the Bulk list after next SOF (Start-Of-Frame) Disabled. + * | | |1 = Processing of the Bulk list in the next frame Enabled. + * |[7:6] |HCFS |Host Controller Functional State + * | | |This field sets the Host Controller state + * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port + * | | |States are: + * | | |00 = USBRESET. + * | | |01 = USBRESUME. + * | | |10 = USBOPERATIONAL. + * | | |11 = USBSUSPEND. + * @var USBH_T::HcCommandStatus + * Offset: 0x08 Host Controller Command Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |HCR |Host Controller Reset + * | | |This bit is set to initiate the software reset of Host Controller + * | | |This bit is cleared by the Host Controller, upon completed of the reset operation. + * | | |This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports. + * | | |0 = Host Controller is not in software reset state. + * | | |1 = Host Controller is in software reset state. + * |[1] |CLF |Control List Filled + * | | |Set high to indicate there is an active TD on the Control List + * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List. + * | | |0 = No active TD found or Host Controller begins to process the head of the Control list. + * | | |1 = An active TD added or found on the Control list. + * |[2] |BLF |Bulk List Filled + * | | |Set high to indicate there is an active TD on the Bulk list + * | | |This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list. + * | | |0 = No active TD found or Host Controller begins to process the head of the Bulk list. + * | | |1 = An active TD added or found on the Bulk list. + * |[17:16] |SOC |Schedule Overrun Count (Read-Only) + * | | |These bits are incremented on each scheduling overrun error + * | | |It is initialized to 00b and wraps around at 11b + * | | |This will be incremented when a scheduling overrun is detected even if SO (HcInterruptStatus[0]) has already been set. + * @var USBH_T::HcInterruptStatus + * Offset: 0x0C Host Controller Interrupt Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun + * | | |Set when the List Processor determines a Schedule Overrun has occurred. + * | | |0 = Schedule Overrun didn't occur. + * | | |1 = Schedule Overrun has occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WDH |Write Back Done Head + * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead + * | | |Further updates of the HccaDoneHead will not occur until this bit has been cleared. + * | | |0 = Host Controller didn't update HccaDoneHead. + * | | |1 = Host Controller has written HcDoneHead to HccaDoneHead. + * | | |Note: This bit is cleared by writing 1 to it. + * |[2] |SF |Start of Frame + * | | |Set when the Frame Management functional block signals a u2018Start of Frame' event + * | | |Host Control generates a SOF token at the same time. + * | | |0 = Not the start of a frame. + * | | |1 = Indicate the start of a frame and Host Controller generates a SOF token. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |RD |Resume Detected + * | | |Set when Host Controller detects resume signaling on a downstream port. + * | | |0 = No resume signaling detected on a downstream port. + * | | |1 = Resume signaling detected on a downstream port. + * | | |Note: This bit is cleared by writing 1 to it. + * |[5] |FNO |Frame Number Overflow + * | | |This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * | | |0 = The bit 15 of Frame Number didn't change. + * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. + * | | |Note: This bit is cleared by writing 1 to it. + * |[6] |RHSC |Root Hub Status Change + * | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed. + * | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change. + * | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed. + * | | |Note: This bit is cleared by writing ‘1Fh’ to HcRhPortStatus1[20:16]. + * @var USBH_T::HcInterruptEnable + * Offset: 0x10 Host Controller Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Enable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Enable Bit + * | | |This bit is a global interrupt enable + * | | |A write of u20181' allows interrupts to be enabled via the specific enable bits listed above. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcInterruptDisable + * Offset: 0x14 Host Controller Interrupt Disable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SO |Scheduling Overrun Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SO (HcInterruptStatus[0]) Disabled. + * | | |1 = Interrupt generation due to SO (HcInterruptStatus[0]) Enabled. + * |[1] |WDH |Write Back Done Head Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to WDH (HcInterruptStatus[1]) Disabled. + * | | |1 = Interrupt generation due to WDH (HcInterruptStatus[1]) Enabled. + * |[2] |SF |Start of Frame Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to SF (HcInterruptStatus[2]) Disabled. + * | | |1 = Interrupt generation due to SF (HcInterruptStatus[2]) Enabled. + * |[3] |RD |Resume Detected Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RD (HcInterruptStatus[3]) Disabled. + * | | |1 = Interrupt generation due to RD (HcInterruptStatus[3]) Enabled. + * |[5] |FNO |Frame Number Overflow Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to FNO (HcInterruptStatus[5]) Disabled. + * | | |1 = Interrupt generation due to FNO (HcInterruptStatus[5]) Enabled. + * |[6] |RHSC |Root Hub Status Change Disable Bit + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Disabled. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]) Enabled. + * |[31] |MIE |Master Interrupt Disable Bit + * | | |Global interrupt disable. Writing u20181' to disable all interrupts. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled if the corresponding bit in HcInterruptEnable is high. + * | | |Read Operation: + * | | |0 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Disabled even if the corresponding bit in HcInterruptEnable is high. + * | | |1 = Interrupt generation due to RHSC (HcInterruptStatus[6]), FNO (HcInterruptStatus[5]), RD (HcInterruptStatus[3]), SF (HcInterruptStatus[2]), WDH (HcInterruptStatus[1]) or SO (HcInterruptStatus[0]) Enabled if the corresponding bit in HcInterruptEnable is high. + * @var USBH_T::HcHCCA + * Offset: 0x18 Host Controller Communication Area Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:8] |HCCA |Host Controller Communication Area + * | | |Pointer to indicate the base address of the Host Controller Communication Area (HCCA). + * @var USBH_T::HcPeriodCurrentED + * Offset: 0x1C Host Controller Period Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |PCED |Periodic Current ED + * | | |Pointer to indicate the physical address of the current Isochronous or Interrupt Endpoint Descriptor. + * @var USBH_T::HcControlHeadED + * Offset: 0x20 Host Controller Control ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CHED |Control Head ED + * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Control list. + * @var USBH_T::HcControlCurrentED + * Offset: 0x24 Host Controller Control Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |CCED |Control Current Head ED + * | | |Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list. + * @var USBH_T::HcBulkHeadED + * Offset: 0x28 Host Controller Bulk Head ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BHED |Bulk Head ED + * | | |Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list. + * @var USBH_T::HcBulkCurrentED + * Offset: 0x2C Host Controller Bulk Current ED Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |BCED |Bulk Current Head ED + * | | |Pointer to indicate the physical address of the current endpoint of the Bulk list. + * @var USBH_T::HcDoneHead + * Offset: 0x30 Host Controller Done Head Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:4] |DH |Done Head + * | | |Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue. + * @var USBH_T::HcFmInterval + * Offset: 0x34 Host Controller Frame Interval Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FI |Frame Interval + * | | |This field specifies the length of a frame as (bit times - 1) + * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here. + * |[29:16] |FSMPS |FS Largest Data Packet + * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. + * |[31] |FIT |Frame Interval Toggle + * | | |This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmInterval[13:0]). + * | | |0 = Host Controller Driver didn't load new value into FI (HcFmInterval[13:0]). + * | | |1 = Host Controller Driver loads a new value into FI (HcFmInterval[13:0]). + * @var USBH_T::HcFmRemaining + * Offset: 0x38 Host Controller Frame Remaining Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |FR |Frame Remaining + * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period + * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval + * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL. + * |[31] |FRT |Frame Remaining Toggle + * | | |This bit is loaded from the FIT (HcFmInterval[31]) whenever FR (HcFmRemaining[13:0]) reaches 0. + * @var USBH_T::HcFmNumber + * Offset: 0x3C Host Controller Frame Number Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |FN |Frame Number + * | | |This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRemaining[13:0]) + * | | |The count rolls over from u2018FFFFh' to u20180h.' + * @var USBH_T::HcPeriodicStart + * Offset: 0x40 Host Controller Periodic Start Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[13:0] |PS |Periodic Start + * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin. + * @var USBH_T::HcLSThreshold + * Offset: 0x44 Host Controller Low-speed Threshold Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[11:0] |LST |Low-speed Threshold + * | | |This field contains a value which is compared to the FR (HcFmRemaining[13:0]) field prior to initiating a Low-speed transaction + * | | |The transaction is started only if FR (HcFmRemaining[13:0]) >= this field + * | | |The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead. + * @var USBH_T::HcRhDescriptorA + * Offset: 0x48 Host Controller Root Hub Descriptor A Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7:0] |NDP |Number Downstream Ports + * | | |USB host control supports two downstream ports and only one port is available in this series of chip. + * | | |Note: NDP = 1 in this series of chip. + * |[8] |PSM |Power Switching Mode + * | | |This bit is used to specify how the power switching of the Root Hub ports is controlled. + * | | |0 = Global switching. + * | | |1 = Individual switching. + * |[11] |OCPM |Over Current Protection Mode + * | | |This bit describes how the over current status for the Root Hub ports reported + * | | |This bit is only valid when NOCP (HcRhDescriptorA[12]) is cleared. + * | | |0 = Global over current. + * | | |1 = Individual over current. + * |[12] |NOCP |No Over Current Protection + * | | |This bit describes how the over current status for the Root Hub ports reported. + * | | |0 = Over current status is reported. + * | | |1 = Over current status is not reported. + * @var USBH_T::HcRhDescriptorB + * Offset: 0x4C Host Controller Root Hub Descriptor B Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:16] |PPCM |Port Power Control Mask + * | | |Global power switching + * | | |This field is only valid if Power Switching Mode is set (individual port switching) + * | | |When set, the port only responds to individual port power switching commands (Set/Clear Port Power) + * | | |When cleared, the port only responds to global power switching commands (Set/Clear Global Power). + * | | |0 = Port power controlled by global power switching. + * | | |1 = Port power controlled by port power switching. + * | | |Note: PPCM[15:2] and PPCM[0] are reserved. + * @var USBH_T::HcRhStatus + * Offset: 0x50 Host Controller Root Hub Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LPS |Clear Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to clear all ports' power. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear global power. + * |[1] |OCI |Over Current Indicator (Read-Only) + * | | |This bit reflects the state of the over current status pin + * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) and OCPM (HcRhDescriptorA[11]) are cleared. + * | | |0 = No over current condition. + * | | |1 = Over current condition. + * |[15] |DRWE |Device Remote Wakeup Enable Bit + * | | |This bit controls if port's Connect Status Change as a remote wake-up event. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * | | |Read Operation: + * | | |0 = Connect Status Change as a remote wake-up event Disabled. + * | | |1 = Connect Status Change as a remote wake-up event Enabled. + * |[16] |LPSC |Set Global Power + * | | |In global power mode (PSM (HcRhDescriptorA[8]) = 0), this bit is written to one to enable power to all ports. + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set global power. + * |[17] |OCIC |Over Current Indicator Change + * | | |This bit is set by hardware when a change has occurred in OCI (HcRhStatus[1]). + * | | |Write 1 to clear this bit to zero. + * | | |0 = OCI (HcRhStatus[1]) didn't change. + * | | |1 = OCI (HcRhStatus[1]) change. + * |[31] |CRWE |Clear Remote Wake-up Enable Bit + * | | |This bit is use to clear DRWE (HcRhStatus[15]). + * | | |This bit always read as zero. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear DRWE (HcRhStatus[15]). + * @var USBH_T::HcRhPortStatus[2] + * Offset: 0x54 Host Controller Root Hub Port Status + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |CCS |Current Connect Status (Read) or Clear Port Enable (Write) + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port enable. + * | | |Read Operation: + * | | |0 = No device connected. + * | | |1 = Device connected. + * |[1] |PES |Port Enable Status (Read) or Set Port Enable (Write) + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port enable. + * | | |Read Operation: + * | | |0 = Port Disabled. + * | | |1 = Port Enabled. + * |[2] |PSS |Port Suspend Status (Read) or Set Port Suspend (Write) + * | | |This bit indicates the port is suspended + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port suspend. + * | | |Read Operation: + * | | |0 = Port is not suspended. + * | | |1 = Port is selectively suspended. + * |[3] |POCI |Port Over Current Indicator (Read) or Clear Port Suspend (Write) + * | | |This bit reflects the state of the over current status pin dedicated to this port + * | | |This field is only valid if NOCP (HcRhDescriptorA[12]) is cleared and OCPM (HcRhDescriptorA[11]) is set. + * | | |This bit is also used to initiate the selective result sequence for the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear port suspend. + * | | |Read Operation: + * | | |0 = No over current condition. + * | | |1 = Over current condition. + * |[4] |PRS |Port Reset Status (Read) or Set Port Reset (Write) + * | | |This bit reflects the reset state of the port. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Set port reset. + * | | |Read Operation + * | | |0 = Port reset signal is not active. + * | | |1 = Port reset signal is active. + * |[8] |PPS |Port Power Status (Read) or Set Port Power (Write) + * | | |This bit reflects the power state of the port regardless of the power switching mode. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Port Power Enabled. + * | | |Read Operation: + * | | |0 = Port power is Disabled. + * | | |1 = Port power is Enabled. + * |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write) + * | | |This bit defines the speed (and bus idle) of the attached device + * | | |It is only valid when CCS (HcRhPortStatus[0]) is set. + * | | |This bit is also used to clear port power. + * | | |Write Operation: + * | | |0 = No effect. + * | | |1 = Clear PPS (HcRhPortStatus[8]). + * | | |Read Operation: + * | | |0 = Full Speed device. + * | | |1 = Low-speed device. + * |[16] |CSC |Connect Status Change + * | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus[0]) changed). + * | | |Write 1 to clear this bit to zero. + * | | |0 = No connect/disconnect event (CCS (HcRhPortStatus[0]) didn't change). + * | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus[0]) changed). + * |[17] |PESC |Port Enable Status Change + * | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus[1]) cleared) due to a hardware event. + * | | |Write 1 to clear this bit to zero. + * | | |0 = PES (HcRhPortStatus[1]) didn't change. + * | | |1 = PES (HcRhPortStatus[1]) changed. + * |[18] |PSSC |Port Suspend Status Change + * | | |This bit indicates the completion of the selective resume sequence for the port. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port resume is not complete. + * | | |1 = Port resume complete. + * |[19] |OCIC |Port Over Current Indicator Change + * | | |This bit is set when POCI (HcRhPortStatus[3]) changes. + * | | |Write 1 to clear this bit to zero. + * | | |0 = POCI (HcRhPortStatus[3]) didn't change. + * | | |1 = POCI (HcRhPortStatus[3]) changes. + * |[20] |PRSC |Port Reset Status Change + * | | |This bit indicates that the port reset signal has completed. + * | | |Write 1 to clear this bit to zero. + * | | |0 = Port reset is not complete. + * | | |1 = Port reset is complete. + * @var USBH_T::HcPhyControl + * Offset: 0x200 Host Controller PHY Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[27] |STBYEN |USB Transceiver Standby Enable Bit + * | | |This bit controls if USB transceiver could enter the standby mode to reduce power consumption. + * | | |0 = The USB transceiver would never enter the standby mode. + * | | |1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive). + * @var USBH_T::HcMiscControl + * Offset: 0x204 Host Controller Miscellaneous Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABORT |AHB Bus Error Response + * | | |This bit indicates there is an Error response received in AHB bus. + * | | |0 = No Error response received. + * | | |1 = Error response received. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |OCAL |over Current Active Low + * | | |This bit controls the polarity of over current flag from external power IC. + * | | |0 = Over current flag is high active. + * | | |1 = Over current flag is low active. + * |[16] |DPRT1 |Disable Port 1 + * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled + * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus. + * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is. + * | | |0 = The connection between USB host controller and transceiver of port 1 Enabled. + * | | |1 = The connection between USB host controller and transceiver of port 1 Disabled and the transceiver of port 1 will also be forced into the standby mode. + */ + __I uint32_t HcRevision; /*!< [0x0000] Host Controller Revision Register */ + __IO uint32_t HcControl; /*!< [0x0004] Host Controller Control Register */ + __IO uint32_t HcCommandStatus; /*!< [0x0008] Host Controller Command Status Register */ + __IO uint32_t HcInterruptStatus; /*!< [0x000c] Host Controller Interrupt Status Register */ + __IO uint32_t HcInterruptEnable; /*!< [0x0010] Host Controller Interrupt Enable Register */ + __IO uint32_t HcInterruptDisable; /*!< [0x0014] Host Controller Interrupt Disable Register */ + __IO uint32_t HcHCCA; /*!< [0x0018] Host Controller Communication Area Register */ + __IO uint32_t HcPeriodCurrentED; /*!< [0x001c] Host Controller Period Current ED Register */ + __IO uint32_t HcControlHeadED; /*!< [0x0020] Host Controller Control Head ED Register */ + __IO uint32_t HcControlCurrentED; /*!< [0x0024] Host Controller Control Current ED Register */ + __IO uint32_t HcBulkHeadED; /*!< [0x0028] Host Controller Bulk Head ED Register */ + __IO uint32_t HcBulkCurrentED; /*!< [0x002c] Host Controller Bulk Current ED Register */ + __IO uint32_t HcDoneHead; /*!< [0x0030] Host Controller Done Head Register */ + __IO uint32_t HcFmInterval; /*!< [0x0034] Host Controller Frame Interval Register */ + __I uint32_t HcFmRemaining; /*!< [0x0038] Host Controller Frame Remaining Register */ + __I uint32_t HcFmNumber; /*!< [0x003c] Host Controller Frame Number Register */ + __IO uint32_t HcPeriodicStart; /*!< [0x0040] Host Controller Periodic Start Register */ + __IO uint32_t HcLSThreshold; /*!< [0x0044] Host Controller Low-speed Threshold Register */ + __IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */ + __IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */ + __IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */ + __IO uint32_t HcRhPortStatus[2]; /*!< [0x0054] Host Controller Root Hub Port Status */ + __I uint32_t RESERVE0[105]; + __IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */ + __IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */ + +} USBH_T; + +/** + @addtogroup USBH_CONST USBH Bit Field Definition + Constant Definitions for USBH Controller + @{ +*/ + +#define USBH_HcRevision_REV_Pos (0) /*!< USBH_T::HcRevision: REV Position */ +#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH_T::HcRevision: REV Mask */ + +#define USBH_HcControl_CBSR_Pos (0) /*!< USBH_T::HcControl: CBSR Position */ +#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH_T::HcControl: CBSR Mask */ + +#define USBH_HcControl_PLE_Pos (2) /*!< USBH_T::HcControl: PLE Position */ +#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH_T::HcControl: PLE Mask */ + +#define USBH_HcControl_IE_Pos (3) /*!< USBH_T::HcControl: IE Position */ +#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH_T::HcControl: IE Mask */ + +#define USBH_HcControl_CLE_Pos (4) /*!< USBH_T::HcControl: CLE Position */ +#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH_T::HcControl: CLE Mask */ + +#define USBH_HcControl_BLE_Pos (5) /*!< USBH_T::HcControl: BLE Position */ +#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH_T::HcControl: BLE Mask */ + +#define USBH_HcControl_HCFS_Pos (6) /*!< USBH_T::HcControl: HCFS Position */ +#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH_T::HcControl: HCFS Mask */ + +#define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH_T::HcCommandStatus: HCR Position */ +#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH_T::HcCommandStatus: HCR Mask */ + +#define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH_T::HcCommandStatus: CLF Position */ +#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH_T::HcCommandStatus: CLF Mask */ + +#define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH_T::HcCommandStatus: BLF Position */ +#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH_T::HcCommandStatus: BLF Mask */ + +#define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH_T::HcCommandStatus: SOC Position */ +#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH_T::HcCommandStatus: SOC Mask */ + +#define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH_T::HcInterruptStatus: SO Position */ +#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH_T::HcInterruptStatus: SO Mask */ + +#define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH_T::HcInterruptStatus: WDH Position*/ +#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH_T::HcInterruptStatus: WDH Mask */ + +#define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH_T::HcInterruptStatus: SF Position */ +#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH_T::HcInterruptStatus: SF Mask */ + +#define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH_T::HcInterruptStatus: RD Position */ +#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH_T::HcInterruptStatus: RD Mask */ + +#define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH_T::HcInterruptStatus: FNO Position*/ +#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH_T::HcInterruptStatus: FNO Mask */ + +#define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH_T::HcInterruptStatus: RHSC Position*/ +#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH_T::HcInterruptStatus: RHSC Mask */ + +#define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH_T::HcInterruptEnable: SO Position */ +#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH_T::HcInterruptEnable: SO Mask */ + +#define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH_T::HcInterruptEnable: WDH Position*/ +#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH_T::HcInterruptEnable: WDH Mask */ + +#define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH_T::HcInterruptEnable: SF Position */ +#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH_T::HcInterruptEnable: SF Mask */ + +#define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH_T::HcInterruptEnable: RD Position */ +#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH_T::HcInterruptEnable: RD Mask */ + +#define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH_T::HcInterruptEnable: FNO Position*/ +#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH_T::HcInterruptEnable: FNO Mask */ + +#define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH_T::HcInterruptEnable: RHSC Position*/ +#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH_T::HcInterruptEnable: RHSC Mask */ + +#define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH_T::HcInterruptEnable: MIE Position*/ +#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH_T::HcInterruptEnable: MIE Mask */ + +#define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH_T::HcInterruptDisable: SO Position*/ +#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH_T::HcInterruptDisable: SO Mask */ + +#define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH_T::HcInterruptDisable: WDH Position*/ +#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH_T::HcInterruptDisable: WDH Mask */ + +#define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH_T::HcInterruptDisable: SF Position*/ +#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH_T::HcInterruptDisable: SF Mask */ + +#define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH_T::HcInterruptDisable: RD Position*/ +#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH_T::HcInterruptDisable: RD Mask */ + +#define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH_T::HcInterruptDisable: FNO Position*/ +#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH_T::HcInterruptDisable: FNO Mask */ + +#define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH_T::HcInterruptDisable: RHSC Position*/ +#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH_T::HcInterruptDisable: RHSC Mask */ + +#define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH_T::HcInterruptDisable: MIE Position*/ +#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH_T::HcInterruptDisable: MIE Mask */ + +#define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH_T::HcHCCA: HCCA Position */ +#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH_T::HcHCCA: HCCA Mask */ + +#define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH_T::HcPeriodCurrentED: PCED Position*/ +#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH_T::HcPeriodCurrentED: PCED Mask */ + +#define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH_T::HcControlHeadED: CHED Position */ +#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH_T::HcControlHeadED: CHED Mask */ + +#define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH_T::HcControlCurrentED: CCED Position*/ +#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH_T::HcControlCurrentED: CCED Mask */ + +#define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH_T::HcBulkHeadED: BHED Position */ +#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH_T::HcBulkHeadED: BHED Mask */ + +#define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH_T::HcBulkCurrentED: BCED Position */ +#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH_T::HcBulkCurrentED: BCED Mask */ + +#define USBH_HcDoneHead_DH_Pos (4) /*!< USBH_T::HcDoneHead: DH Position */ +#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH_T::HcDoneHead: DH Mask */ + +#define USBH_HcFmInterval_FI_Pos (0) /*!< USBH_T::HcFmInterval: FI Position */ +#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH_T::HcFmInterval: FI Mask */ + +#define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH_T::HcFmInterval: FSMPS Position */ +#define USBH_HcFmInterval_FSMPS_Msk (0x3ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH_T::HcFmInterval: FSMPS Mask */ + +#define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH_T::HcFmInterval: FIT Position */ +#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH_T::HcFmInterval: FIT Mask */ + +#define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH_T::HcFmRemaining: FR Position */ +#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH_T::HcFmRemaining: FR Mask */ + +#define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH_T::HcFmRemaining: FRT Position */ +#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH_T::HcFmRemaining: FRT Mask */ + +#define USBH_HcFmNumber_FN_Pos (0) /*!< USBH_T::HcFmNumber: FN Position */ +#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH_T::HcFmNumber: FN Mask */ + +#define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH_T::HcPeriodicStart: PS Position */ +#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH_T::HcPeriodicStart: PS Mask */ + +#define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH_T::HcLSThreshold: LST Position */ +#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH_T::HcLSThreshold: LST Mask */ + +#define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH_T::HcRhDescriptorA: NDP Position */ +#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH_T::HcRhDescriptorA: NDP Mask */ + +#define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH_T::HcRhDescriptorA: PSM Position */ +#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH_T::HcRhDescriptorA: PSM Mask */ + +#define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH_T::HcRhDescriptorA: OCPM Position */ +#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH_T::HcRhDescriptorA: OCPM Mask */ + +#define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH_T::HcRhDescriptorA: NOCP Position */ +#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH_T::HcRhDescriptorA: NOCP Mask */ + +#define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH_T::HcRhDescriptorB: PPCM Position */ +#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH_T::HcRhDescriptorB: PPCM Mask */ + +#define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH_T::HcRhStatus: LPS Position */ +#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH_T::HcRhStatus: LPS Mask */ + +#define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH_T::HcRhStatus: OCI Position */ +#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH_T::HcRhStatus: OCI Mask */ + +#define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH_T::HcRhStatus: DRWE Position */ +#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH_T::HcRhStatus: DRWE Mask */ + +#define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH_T::HcRhStatus: LPSC Position */ +#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH_T::HcRhStatus: LPSC Mask */ + +#define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH_T::HcRhStatus: OCIC Position */ +#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH_T::HcRhStatus: OCIC Mask */ + +#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */ +#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */ + +#define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus: CCS Position */ +#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus: CCS Mask */ + +#define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus: PES Position */ +#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus: PES Mask */ + +#define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus: PSS Position */ +#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus: PSS Mask */ + +#define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus: POCI Position */ +#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus: POCI Mask */ + +#define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus: PRS Position */ +#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus: PRS Mask */ + +#define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus: PPS Position */ +#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus: PPS Mask */ + +#define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus: LSDA Position */ +#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus: LSDA Mask */ + +#define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus: CSC Position */ +#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus: CSC Mask */ + +#define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus: PESC Position */ +#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus: PESC Mask */ + +#define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus: PSSC Position */ +#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus: PSSC Mask */ + +#define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus: OCIC Position */ +#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus: OCIC Mask */ + +#define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus: PRSC Position */ +#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus: PRSC Mask */ + +#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */ +#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */ + +#define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH_T::HcMiscControl: ABORT Position */ +#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH_T::HcMiscControl: ABORT Mask */ + +#define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH_T::HcMiscControl: OCAL Position */ +#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH_T::HcMiscControl: OCAL Mask */ + +#define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH_T::HcMiscControl: DPRT1 Position */ +#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH_T::HcMiscControl: DPRT1 Mask */ + +/**@}*/ /* USBH_CONST */ +/**@}*/ /* end of USBH register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __USBH_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/uspi_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/uspi_reg.h new file mode 100644 index 0000000000..8f383ec7c6 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/uspi_reg.h @@ -0,0 +1,666 @@ +/**************************************************************************//** + * @file uspi_reg.h + * @version V1.00 + * @brief USPI register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __USPI_REG_H__ +#define __USPI_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + +/*---------------------- SPI Mode of USCI Controller -------------------------*/ +/** + @addtogroup USPI SPI Mode of USCI Controller(USPI) + Memory Mapped Structure for USPI Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var USPI_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Note: Other bit combinations are reserved. + * @var USPI_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var USPI_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fDIV_CLK. + * | | |01 = fPROT_CLK. + * | | |10 = fSCLK. + * | | |11 = fREF_CLK. + * |[4] |TMCNTEN |Time Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Time measurement counter is Disabled. + * | | |1 = Time measurement counter is Enabled. + * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection + * | | |0 = Time measurement counter with fPROT_CLK. + * | | |1 = Time measurement counter with fDIV_CLK. + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(USPI_PROTCTL[6])) is enabled + * | | |The revised value is the average bit time between bit 5 and bit 6 + * | | |The user can use revised CLKDIV and new BRDETITV (USPI_PROTCTL[24:16]) to calculate the precise baud rate. + * @var USPI_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, it is suggested this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * | | |Note: In SPI protocol, it is suggested this bit should be set as 0. + * @var USPI_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, it is suggested this bit should be set as 0. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var USPI_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * | | |Note: In SPI protocol, it is suggested this bit should be set as 0. + * @var USPI_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pin. + * | | |0 = Data output level is not inverted. + * | | |1 = Data output level is inverted. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: The control signal has different definitions in different protocol + * | | |In SPI protocol, the control signal means slave select signal + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1: Reserved. + * | | |0x2: Reserved. + * | | |0x3: Reserved. + * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. + * @var USPI_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission + * | | |In order to avoid overwriting the transmit data, user have to check TXEMPTY (USPI_BUFSTS[8]) status before writing transmit data into this bit field. + * |[16] |PORTDIR |Port Direction Control + * | | |This bit field is only available while USCI operates in SPI protocol (FUNMODE = 0x1) with half-duplex transfer + * | | |It is used to define the direction of the data port pin + * | | |When software writes USPI_TXDAT register, the transmit data and its port direction are settled simultaneously. + * | | |0 = The data pin is configured as output mode. + * | | |1 = The data pin is configured as input mode. + * @var USPI_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * @var USPI_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[6] |TXUDRIEN |Slave Transmit Under-run Interrupt Enable Bit + * | | |0 = Transmit under-run interrupt Disabled. + * | | |1 = Transmit under-run interrupt Enabled. + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Interrupt Enable Bit + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note 1: It is cleared automatically after one PCLK cycle. + * | | |Note 2: Write 1 to this bit will set the output data pin to zero if USPI_PROTCTL[28]=0. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * @var USPI_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator (Read Only) + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator (Read Only) + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Overrun Interrupt Status + * | | |This bit indicates that a receive buffer overrun event has been detected + * | | |If RXOVIEN (USPI_BUFCTL[14]) is enabled, the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun event has not been detected. + * | | |1 = A receive buffer overrun event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator (Read Only) + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty and available for the next transmission datum. + * |[9] |TXFULL |Transmit Buffer Full Indicator (Read Only) + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * |[11] |TXUDRIF |Transmit Buffer Under-run Interrupt Status + * | | |This bit indicates that a transmit buffer under-run event has been detected + * | | |If enabled by TXUDRIEN (USPI_BUFCTL[6]), the corresponding interrupt request is activated + * | | |It is cleared by software writes 1 to this bit + * | | |0 = A transmit buffer under-run event has not been detected. + * | | |1 = A transmit buffer under-run event has been detected. + * @var USPI_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * | | |Note: The I2C is not supporting PDMA function. + * @var USPI_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[1] |WKADDREN |Wake-up Address Match Enable Bit + * | | |0 = The chip is woken up according data toggle. + * | | |1 = The chip is woken up according address match. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var USPI_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var USPI_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SLAVE |Slave Mode Selection + * | | |0 = Master mode. + * | | |1 = Slave mode. + * |[1] |SLV3WIRE |Slave 3-wire Mode Selection (Slave Only) + * | | |The SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode. + * | | |0 = 4-wire bi-direction interface. + * | | |1 = 3-wire bi-direction interface. + * |[2] |SS |Slave Select Control (Master Only) + * | | |If AUTOSS bit is cleared, setting this bit to 1 will set the slave select signal to active state, and setting this bit to 0 will set the slave select signal back to inactive state. + * | | |If the AUTOSS function is enabled (AUTOSS = 1), the setting value of this bit will not affect the current state of slave select signal. + * | | |Note: In SPI protocol, the internal slave select signal is active high. + * |[3] |AUTOSS |Automatic Slave Select Function Enable (Master Only) + * | | |0 = Slave select signal will be controlled by the setting value of SS (USPI_PROTCTL[2]) bit. + * | | |1 = Slave select signal will be generated automatically + * | | |The slave select signal will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished. + * |[7:6] |SCLKMODE |Serial Bus Clock Mode + * | | |This bit field defines the SCLK idle status, data transmit, and data receive edge. + * | | |00 = MODE0. The idle state of SPI clock is low level. + * | | |Data is transmitted with falling edge and received with rising edge. + * | | |01 = MODE1. The idle state of SPI clock is low level. + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |10 = MODE2. The idle state of SPI clock is high level. + * | | |Data is transmitted with rising edge and received with falling edge. + * | | |11 = MODE3. The idle state of SPI clock is high level. + * | | |Data is transmitted with falling edge and received with rising edge. + * |[11:8] |SUSPITV |Suspend Interval (Master Only) + * | | |This bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer + * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word + * | | |The default value is 0x3 + * | | |The period of the suspend interval is obtained according to the following equation. + * | | |(SUSPITV[3:0] + 0.5) * period of SPI_CLK clock cycle + * | | |Example: + * | | |SUSPITV = 0x0 ... 0.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0x1 ... 1.5 SPI_CLK clock cycle. + * | | |..... + * | | |SUSPITV = 0xE ... 14.5 SPI_CLK clock cycle. + * | | |SUSPITV = 0xF ... 15.5 SPI_CLK clock cycle. + * |[14:12] |TSMSEL |Transmit Data Mode Selection + * | | |This bit field describes how receive and transmit data is shifted in and out. + * | | |TSMSEL = 000b: Full-duplex SPI. + * | | |TSMSEL = 100b: Half-duplex SPI. + * | | |Others = Reserved. + * | | |Note: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer automatically. + * |[25:16] |SLVTOCNT |Slave Mode Time-out Period (Slave Only) + * | | |In Slave mode, this bit field is used for Slave time-out period + * | | |This bit field indicates how many clock periods (selected by TMCNTSRC, USPI_BRGEN[5]) between the two edges of input SCLK will assert the Slave time-out event + * | | |Writing 0x0 into this bit field will disable the Slave time-out function. + * | | |Example: Assume SLVTOCNT is 0x0A and TMCNTSRC (USPI_BRGEN[5]) is 1, it means the time-out event will occur if the state of SPI bus clock pin is not changed more than (10+1) periods of fDIV_CLK. + * |[28] |TXUDRPOL |Transmit Under-run Data Polarity (Slave Only) + * | | |This bit defines the transmitting data level when no data is available for transferring. + * | | |0 = The output data level is 0 if TX under-run event occurs. + * | | |1 = The output data level is 1 if TX under-run event occurs. + * |[31] |PROTEN |SPI Protocol Enable Bit + * | | |0 = SPI Protocol Disabled. + * | | |1 = SPI Protocol Enabled. + * @var USPI_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive. + * | | |0 = Slave select inactive interrupt generation Disabled. + * | | |1 = Slave select inactive interrupt generation Enabled. + * |[1] |SSACTIEN |Slave Select Active Interrupt Enable Bit + * | | |This bit enables/disables the generation of a slave select interrupt if the slave select changes to active. + * | | |0 = Slave select active interrupt generation Disabled. + * | | |1 = Slave select active interrupt generation Enabled. + * |[2] |SLVTOIEN |Slave Time-out Interrupt Enable Bit + * | | |In SPI protocol, this bit enables the interrupt generation in case of a Slave time-out event. + * | | |0 = The Slave time-out interrupt Disabled. + * | | |1 = The Slave time-out interrupt Enabled. + * |[3] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit + * | | |If data transfer is terminated by slave time-out or slave select inactive event in Slave mode, so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8]) + * | | |Bit count error event occurs. + * | | |0 = The Slave mode bit count error interrupt Disabled. + * | | |1 = The Slave mode bit count error interrupt Enabled. + * @var USPI_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = Transmit start event did not occur. + * | | |1 = Transmit start event occurred. + * | | |Note: It is cleared by software write 1 to this bit + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = Transmit end event did not occur. + * | | |1 = Transmit end event occurred. + * | | |Note: It is cleared by software write 1 to this bit + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = Receive start event did not occur. + * | | |1 = Receive start event occurred. + * | | |Note: It is cleared by software write 1 to this bit + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = Receive end event did not occur. + * | | |1 = Receive end event occurred. + * | | |Note: It is cleared by software write 1 to this bit + * |[5] |SLVTOIF |Slave Time-out Interrupt Flag (Slave Only) + * | | |0 = Slave time-out event did not occur. + * | | |1 = Slave time-out event occurred. + * | | |Note: It is cleared by software write 1 to this bit + * |[6] |SLVBEIF |Slave Bit Count Error Interrupt Flag (Slave Only) + * | | |0 = Slave bit count error event did not occur. + * | | |1 = Slave bit count error event occurred. + * | | |Note: It is cleared by software write 1 to this bit. + * |[8] |SSINAIF |Slave Select Inactive Interrupt Flag (Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to inactive + * | | |It is cleared by software writes 1 to this bit + * | | |0 = The slave select signal has not changed to inactive. + * | | |1 = The slave select signal has changed to inactive. + * | | |Note: The internal slave select signal is active high. + * |[9] |SSACTIF |Slave Select Active Interrupt Flag (Slave Only) + * | | |This bit indicates that the internal slave select signal has changed to active + * | | |It is cleared by software writes one to this bit + * | | |0 = The slave select signal has not changed to active. + * | | |1 = The slave select signal has changed to active. + * | | |Note: The internal slave select signal is active high. + * |[16] |SSLINE |Slave Select Line Bus Status (Read Only) + * | | |This bit is only available in Slave mode + * | | |It used to monitor the current status of the input slave select signal on the bus. + * | | |0 = The slave select line status is 0. + * | | |1 = The slave select line status is 1. + * |[17] |BUSY |Busy Status (Read Only) + * | | |0 = SPI is in idle state. + * | | |1 = SPI is in busy state. + * | | |The following listing are the bus busy conditions: + * | | |a. USPI_PROTCTL[31] = 1 and the TXEMPTY = 0. + * | | |b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet. + * | | |c. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and there is serial clock input into the SPI core logic when slave select is active. + * | | |d. For SPI Slave mode, the USPI_PROTCTL[31] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. + * |[18] |SLVUDR |Slave Mode Transmit Under-run Status (Read Only) + * | | |In Slave mode, if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock, this status flag will be set to 1 + * | | |This bit indicates whether the current shift-out data of word transmission is switched to TXUDRPOL (USPI_PROTCTL[28]) or not. + * | | |0 = Slave transmit under-run event did not occur. + * | | |1 = Slave transmit under-run event occurred. + */ + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + __I uint32_t RESERVE1[3]; + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + __I uint32_t RESERVE2[1]; + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + __I uint32_t RESERVE3[4]; + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + +} USPI_T; + +/** + @addtogroup USPI_CONST USPI Bit Field Definition + Constant Definitions for USPI Controller + @{ +*/ + +#define USPI_CTL_FUNMODE_Pos (0) /*!< USPI_T::CTL: FUNMODE Position */ +#define USPI_CTL_FUNMODE_Msk (0x7ul << USPI_CTL_FUNMODE_Pos) /*!< USPI_T::CTL: FUNMODE Mask */ + +#define USPI_INTEN_TXSTIEN_Pos (1) /*!< USPI_T::INTEN: TXSTIEN Position */ +#define USPI_INTEN_TXSTIEN_Msk (0x1ul << USPI_INTEN_TXSTIEN_Pos) /*!< USPI_T::INTEN: TXSTIEN Mask */ + +#define USPI_INTEN_TXENDIEN_Pos (2) /*!< USPI_T::INTEN: TXENDIEN Position */ +#define USPI_INTEN_TXENDIEN_Msk (0x1ul << USPI_INTEN_TXENDIEN_Pos) /*!< USPI_T::INTEN: TXENDIEN Mask */ + +#define USPI_INTEN_RXSTIEN_Pos (3) /*!< USPI_T::INTEN: RXSTIEN Position */ +#define USPI_INTEN_RXSTIEN_Msk (0x1ul << USPI_INTEN_RXSTIEN_Pos) /*!< USPI_T::INTEN: RXSTIEN Mask */ + +#define USPI_INTEN_RXENDIEN_Pos (4) /*!< USPI_T::INTEN: RXENDIEN Position */ +#define USPI_INTEN_RXENDIEN_Msk (0x1ul << USPI_INTEN_RXENDIEN_Pos) /*!< USPI_T::INTEN: RXENDIEN Mask */ + +#define USPI_BRGEN_RCLKSEL_Pos (0) /*!< USPI_T::BRGEN: RCLKSEL Position */ +#define USPI_BRGEN_RCLKSEL_Msk (0x1ul << USPI_BRGEN_RCLKSEL_Pos) /*!< USPI_T::BRGEN: RCLKSEL Mask */ + +#define USPI_BRGEN_PTCLKSEL_Pos (1) /*!< USPI_T::BRGEN: PTCLKSEL Position */ +#define USPI_BRGEN_PTCLKSEL_Msk (0x1ul << USPI_BRGEN_PTCLKSEL_Pos) /*!< USPI_T::BRGEN: PTCLKSEL Mask */ + +#define USPI_BRGEN_SPCLKSEL_Pos (2) /*!< USPI_T::BRGEN: SPCLKSEL Position */ +#define USPI_BRGEN_SPCLKSEL_Msk (0x3ul << USPI_BRGEN_SPCLKSEL_Pos) /*!< USPI_T::BRGEN: SPCLKSEL Mask */ + +#define USPI_BRGEN_TMCNTEN_Pos (4) /*!< USPI_T::BRGEN: TMCNTEN Position */ +#define USPI_BRGEN_TMCNTEN_Msk (0x1ul << USPI_BRGEN_TMCNTEN_Pos) /*!< USPI_T::BRGEN: TMCNTEN Mask */ + +#define USPI_BRGEN_TMCNTSRC_Pos (5) /*!< USPI_T::BRGEN: TMCNTSRC Position */ +#define USPI_BRGEN_TMCNTSRC_Msk (0x1ul << USPI_BRGEN_TMCNTSRC_Pos) /*!< USPI_T::BRGEN: TMCNTSRC Mask */ + +#define USPI_BRGEN_CLKDIV_Pos (16) /*!< USPI_T::BRGEN: CLKDIV Position */ +#define USPI_BRGEN_CLKDIV_Msk (0x3fful << USPI_BRGEN_CLKDIV_Pos) /*!< USPI_T::BRGEN: CLKDIV Mask */ + +#define USPI_DATIN0_SYNCSEL_Pos (0) /*!< USPI_T::DATIN0: SYNCSEL Position */ +#define USPI_DATIN0_SYNCSEL_Msk (0x1ul << USPI_DATIN0_SYNCSEL_Pos) /*!< USPI_T::DATIN0: SYNCSEL Mask */ + +#define USPI_DATIN0_ININV_Pos (2) /*!< USPI_T::DATIN0: ININV Position */ +#define USPI_DATIN0_ININV_Msk (0x1ul << USPI_DATIN0_ININV_Pos) /*!< USPI_T::DATIN0: ININV Mask */ + +#define USPI_CTLIN0_SYNCSEL_Pos (0) /*!< USPI_T::CTLIN0: SYNCSEL Position */ +#define USPI_CTLIN0_SYNCSEL_Msk (0x1ul << USPI_CTLIN0_SYNCSEL_Pos) /*!< USPI_T::CTLIN0: SYNCSEL Mask */ + +#define USPI_CTLIN0_ININV_Pos (2) /*!< USPI_T::CTLIN0: ININV Position */ +#define USPI_CTLIN0_ININV_Msk (0x1ul << USPI_CTLIN0_ININV_Pos) /*!< USPI_T::CTLIN0: ININV Mask */ + +#define USPI_CLKIN_SYNCSEL_Pos (0) /*!< USPI_T::CLKIN: SYNCSEL Position */ +#define USPI_CLKIN_SYNCSEL_Msk (0x1ul << USPI_CLKIN_SYNCSEL_Pos) /*!< USPI_T::CLKIN: SYNCSEL Mask */ + +#define USPI_LINECTL_LSB_Pos (0) /*!< USPI_T::LINECTL: LSB Position */ +#define USPI_LINECTL_LSB_Msk (0x1ul << USPI_LINECTL_LSB_Pos) /*!< USPI_T::LINECTL: LSB Mask */ + +#define USPI_LINECTL_DATOINV_Pos (5) /*!< USPI_T::LINECTL: DATOINV Position */ +#define USPI_LINECTL_DATOINV_Msk (0x1ul << USPI_LINECTL_DATOINV_Pos) /*!< USPI_T::LINECTL: DATOINV Mask */ + +#define USPI_LINECTL_CTLOINV_Pos (7) /*!< USPI_T::LINECTL: CTLOINV Position */ +#define USPI_LINECTL_CTLOINV_Msk (0x1ul << USPI_LINECTL_CTLOINV_Pos) /*!< USPI_T::LINECTL: CTLOINV Mask */ + +#define USPI_LINECTL_DWIDTH_Pos (8) /*!< USPI_T::LINECTL: DWIDTH Position */ +#define USPI_LINECTL_DWIDTH_Msk (0xful << USPI_LINECTL_DWIDTH_Pos) /*!< USPI_T::LINECTL: DWIDTH Mask */ + +#define USPI_TXDAT_TXDAT_Pos (0) /*!< USPI_T::TXDAT: TXDAT Position */ +#define USPI_TXDAT_TXDAT_Msk (0xfffful << USPI_TXDAT_TXDAT_Pos) /*!< USPI_T::TXDAT: TXDAT Mask */ + +#define USPI_TXDAT_PORTDIR_Pos (16) /*!< USPI_T::TXDAT: PORTDIR Position */ +#define USPI_TXDAT_PORTDIR_Msk (0x1ul << USPI_TXDAT_PORTDIR_Pos) /*!< USPI_T::TXDAT: PORTDIR Mask */ + +#define USPI_RXDAT_RXDAT_Pos (0) /*!< USPI_T::RXDAT: RXDAT Position */ +#define USPI_RXDAT_RXDAT_Msk (0xfffful << USPI_RXDAT_RXDAT_Pos) /*!< USPI_T::RXDAT: RXDAT Mask */ + +#define USPI_BUFCTL_TXUDRIEN_Pos (6) /*!< USPI_T::BUFCTL: TXUDRIEN Position */ +#define USPI_BUFCTL_TXUDRIEN_Msk (0x1ul << USPI_BUFCTL_TXUDRIEN_Pos) /*!< USPI_T::BUFCTL: TXUDRIEN Mask */ + +#define USPI_BUFCTL_TXCLR_Pos (7) /*!< USPI_T::BUFCTL: TXCLR Position */ +#define USPI_BUFCTL_TXCLR_Msk (0x1ul << USPI_BUFCTL_TXCLR_Pos) /*!< USPI_T::BUFCTL: TXCLR Mask */ + +#define USPI_BUFCTL_RXOVIEN_Pos (14) /*!< USPI_T::BUFCTL: RXOVIEN Position */ +#define USPI_BUFCTL_RXOVIEN_Msk (0x1ul << USPI_BUFCTL_RXOVIEN_Pos) /*!< USPI_T::BUFCTL: RXOVIEN Mask */ + +#define USPI_BUFCTL_RXCLR_Pos (15) /*!< USPI_T::BUFCTL: RXCLR Position */ +#define USPI_BUFCTL_RXCLR_Msk (0x1ul << USPI_BUFCTL_RXCLR_Pos) /*!< USPI_T::BUFCTL: RXCLR Mask */ + +#define USPI_BUFCTL_TXRST_Pos (16) /*!< USPI_T::BUFCTL: TXRST Position */ +#define USPI_BUFCTL_TXRST_Msk (0x1ul << USPI_BUFCTL_TXRST_Pos) /*!< USPI_T::BUFCTL: TXRST Mask */ + +#define USPI_BUFCTL_RXRST_Pos (17) /*!< USPI_T::BUFCTL: RXRST Position */ +#define USPI_BUFCTL_RXRST_Msk (0x1ul << USPI_BUFCTL_RXRST_Pos) /*!< USPI_T::BUFCTL: RXRST Mask */ + +#define USPI_BUFSTS_RXEMPTY_Pos (0) /*!< USPI_T::BUFSTS: RXEMPTY Position */ +#define USPI_BUFSTS_RXEMPTY_Msk (0x1ul << USPI_BUFSTS_RXEMPTY_Pos) /*!< USPI_T::BUFSTS: RXEMPTY Mask */ + +#define USPI_BUFSTS_RXFULL_Pos (1) /*!< USPI_T::BUFSTS: RXFULL Position */ +#define USPI_BUFSTS_RXFULL_Msk (0x1ul << USPI_BUFSTS_RXFULL_Pos) /*!< USPI_T::BUFSTS: RXFULL Mask */ + +#define USPI_BUFSTS_RXOVIF_Pos (3) /*!< USPI_T::BUFSTS: RXOVIF Position */ +#define USPI_BUFSTS_RXOVIF_Msk (0x1ul << USPI_BUFSTS_RXOVIF_Pos) /*!< USPI_T::BUFSTS: RXOVIF Mask */ + +#define USPI_BUFSTS_TXEMPTY_Pos (8) /*!< USPI_T::BUFSTS: TXEMPTY Position */ +#define USPI_BUFSTS_TXEMPTY_Msk (0x1ul << USPI_BUFSTS_TXEMPTY_Pos) /*!< USPI_T::BUFSTS: TXEMPTY Mask */ + +#define USPI_BUFSTS_TXFULL_Pos (9) /*!< USPI_T::BUFSTS: TXFULL Position */ +#define USPI_BUFSTS_TXFULL_Msk (0x1ul << USPI_BUFSTS_TXFULL_Pos) /*!< USPI_T::BUFSTS: TXFULL Mask */ + +#define USPI_BUFSTS_TXUDRIF_Pos (11) /*!< USPI_T::BUFSTS: TXUDRIF Position */ +#define USPI_BUFSTS_TXUDRIF_Msk (0x1ul << USPI_BUFSTS_TXUDRIF_Pos) /*!< USPI_T::BUFSTS: TXUDRIF Mask */ + +#define USPI_PDMACTL_PDMARST_Pos (0) /*!< USPI_T::PDMACTL: PDMARST Position */ +#define USPI_PDMACTL_PDMARST_Msk (0x1ul << USPI_PDMACTL_PDMARST_Pos) /*!< USPI_T::PDMACTL: PDMARST Mask */ + +#define USPI_PDMACTL_TXPDMAEN_Pos (1) /*!< USPI_T::PDMACTL: TXPDMAEN Position */ +#define USPI_PDMACTL_TXPDMAEN_Msk (0x1ul << USPI_PDMACTL_TXPDMAEN_Pos) /*!< USPI_T::PDMACTL: TXPDMAEN Mask */ + +#define USPI_PDMACTL_RXPDMAEN_Pos (2) /*!< USPI_T::PDMACTL: RXPDMAEN Position */ +#define USPI_PDMACTL_RXPDMAEN_Msk (0x1ul << USPI_PDMACTL_RXPDMAEN_Pos) /*!< USPI_T::PDMACTL: RXPDMAEN Mask */ + +#define USPI_PDMACTL_PDMAEN_Pos (3) /*!< USPI_T::PDMACTL: PDMAEN Position */ +#define USPI_PDMACTL_PDMAEN_Msk (0x1ul << USPI_PDMACTL_PDMAEN_Pos) /*!< USPI_T::PDMACTL: PDMAEN Mask */ + +#define USPI_WKCTL_WKEN_Pos (0) /*!< USPI_T::WKCTL: WKEN Position */ +#define USPI_WKCTL_WKEN_Msk (0x1ul << USPI_WKCTL_WKEN_Pos) /*!< USPI_T::WKCTL: WKEN Mask */ + +#define USPI_WKCTL_WKADDREN_Pos (1) /*!< USPI_T::WKCTL: WKADDREN Position */ +#define USPI_WKCTL_WKADDREN_Msk (0x1ul << USPI_WKCTL_WKADDREN_Pos) /*!< USPI_T::WKCTL: WKADDREN Mask */ + +#define USPI_WKCTL_PDBOPT_Pos (2) /*!< USPI_T::WKCTL: PDBOPT Position */ +#define USPI_WKCTL_PDBOPT_Msk (0x1ul << USPI_WKCTL_PDBOPT_Pos) /*!< USPI_T::WKCTL: PDBOPT Mask */ + +#define USPI_WKSTS_WKF_Pos (0) /*!< USPI_T::WKSTS: WKF Position */ +#define USPI_WKSTS_WKF_Msk (0x1ul << USPI_WKSTS_WKF_Pos) /*!< USPI_T::WKSTS: WKF Mask */ + +#define USPI_PROTCTL_SLAVE_Pos (0) /*!< USPI_T::PROTCTL: SLAVE Position */ +#define USPI_PROTCTL_SLAVE_Msk (0x1ul << USPI_PROTCTL_SLAVE_Pos) /*!< USPI_T::PROTCTL: SLAVE Mask */ + +#define USPI_PROTCTL_SLV3WIRE_Pos (1) /*!< USPI_T::PROTCTL: SLV3WIRE Position */ +#define USPI_PROTCTL_SLV3WIRE_Msk (0x1ul << USPI_PROTCTL_SLV3WIRE_Pos) /*!< USPI_T::PROTCTL: SLV3WIRE Mask */ + +#define USPI_PROTCTL_SS_Pos (2) /*!< USPI_T::PROTCTL: SS Position */ +#define USPI_PROTCTL_SS_Msk (0x1ul << USPI_PROTCTL_SS_Pos) /*!< USPI_T::PROTCTL: SS Mask */ + +#define USPI_PROTCTL_AUTOSS_Pos (3) /*!< USPI_T::PROTCTL: AUTOSS Position */ +#define USPI_PROTCTL_AUTOSS_Msk (0x1ul << USPI_PROTCTL_AUTOSS_Pos) /*!< USPI_T::PROTCTL: AUTOSS Mask */ + +#define USPI_PROTCTL_SCLKMODE_Pos (6) /*!< USPI_T::PROTCTL: SCLKMODE Position */ +#define USPI_PROTCTL_SCLKMODE_Msk (0x3ul << USPI_PROTCTL_SCLKMODE_Pos) /*!< USPI_T::PROTCTL: SCLKMODE Mask */ + +#define USPI_PROTCTL_SUSPITV_Pos (8) /*!< USPI_T::PROTCTL: SUSPITV Position */ +#define USPI_PROTCTL_SUSPITV_Msk (0xful << USPI_PROTCTL_SUSPITV_Pos) /*!< USPI_T::PROTCTL: SUSPITV Mask */ + +#define USPI_PROTCTL_TSMSEL_Pos (12) /*!< USPI_T::PROTCTL: TSMSEL Position */ +#define USPI_PROTCTL_TSMSEL_Msk (0x7ul << USPI_PROTCTL_TSMSEL_Pos) /*!< USPI_T::PROTCTL: TSMSEL Mask */ + +#define USPI_PROTCTL_SLVTOCNT_Pos (16) /*!< USPI_T::PROTCTL: SLVTOCNT Position */ +#define USPI_PROTCTL_SLVTOCNT_Msk (0x3fful << USPI_PROTCTL_SLVTOCNT_Pos) /*!< USPI_T::PROTCTL: SLVTOCNT Mask */ + +#define USPI_PROTCTL_TXUDRPOL_Pos (28) /*!< USPI_T::PROTCTL: TXUDRPOL Position */ +#define USPI_PROTCTL_TXUDRPOL_Msk (0x1ul << USPI_PROTCTL_TXUDRPOL_Pos) /*!< USPI_T::PROTCTL: TXUDRPOL Mask */ + +#define USPI_PROTCTL_PROTEN_Pos (31) /*!< USPI_T::PROTCTL: PROTEN Position */ +#define USPI_PROTCTL_PROTEN_Msk (0x1ul << USPI_PROTCTL_PROTEN_Pos) /*!< USPI_T::PROTCTL: PROTEN Mask */ + +#define USPI_PROTIEN_SSINAIEN_Pos (0) /*!< USPI_T::PROTIEN: SSINAIEN Position */ +#define USPI_PROTIEN_SSINAIEN_Msk (0x1ul << USPI_PROTIEN_SSINAIEN_Pos) /*!< USPI_T::PROTIEN: SSINAIEN Mask */ + +#define USPI_PROTIEN_SSACTIEN_Pos (1) /*!< USPI_T::PROTIEN: SSACTIEN Position */ +#define USPI_PROTIEN_SSACTIEN_Msk (0x1ul << USPI_PROTIEN_SSACTIEN_Pos) /*!< USPI_T::PROTIEN: SSACTIEN Mask */ + +#define USPI_PROTIEN_SLVTOIEN_Pos (2) /*!< USPI_T::PROTIEN: SLVTOIEN Position */ +#define USPI_PROTIEN_SLVTOIEN_Msk (0x1ul << USPI_PROTIEN_SLVTOIEN_Pos) /*!< USPI_T::PROTIEN: SLVTOIEN Mask */ + +#define USPI_PROTIEN_SLVBEIEN_Pos (3) /*!< USPI_T::PROTIEN: SLVBEIEN Position */ +#define USPI_PROTIEN_SLVBEIEN_Msk (0x1ul << USPI_PROTIEN_SLVBEIEN_Pos) /*!< USPI_T::PROTIEN: SLVBEIEN Mask */ + +#define USPI_PROTSTS_TXSTIF_Pos (1) /*!< USPI_T::PROTSTS: TXSTIF Position */ +#define USPI_PROTSTS_TXSTIF_Msk (0x1ul << USPI_PROTSTS_TXSTIF_Pos) /*!< USPI_T::PROTSTS: TXSTIF Mask */ + +#define USPI_PROTSTS_TXENDIF_Pos (2) /*!< USPI_T::PROTSTS: TXENDIF Position */ +#define USPI_PROTSTS_TXENDIF_Msk (0x1ul << USPI_PROTSTS_TXENDIF_Pos) /*!< USPI_T::PROTSTS: TXENDIF Mask */ + +#define USPI_PROTSTS_RXSTIF_Pos (3) /*!< USPI_T::PROTSTS: RXSTIF Position */ +#define USPI_PROTSTS_RXSTIF_Msk (0x1ul << USPI_PROTSTS_RXSTIF_Pos) /*!< USPI_T::PROTSTS: RXSTIF Mask */ + +#define USPI_PROTSTS_RXENDIF_Pos (4) /*!< USPI_T::PROTSTS: RXENDIF Position */ +#define USPI_PROTSTS_RXENDIF_Msk (0x1ul << USPI_PROTSTS_RXENDIF_Pos) /*!< USPI_T::PROTSTS: RXENDIF Mask */ + +#define USPI_PROTSTS_SLVTOIF_Pos (5) /*!< USPI_T::PROTSTS: SLVTOIF Position */ +#define USPI_PROTSTS_SLVTOIF_Msk (0x1ul << USPI_PROTSTS_SLVTOIF_Pos) /*!< USPI_T::PROTSTS: SLVTOIF Mask */ + +#define USPI_PROTSTS_SLVBEIF_Pos (6) /*!< USPI_T::PROTSTS: SLVBEIF Position */ +#define USPI_PROTSTS_SLVBEIF_Msk (0x1ul << USPI_PROTSTS_SLVBEIF_Pos) /*!< USPI_T::PROTSTS: SLVBEIF Mask */ + +#define USPI_PROTSTS_SSINAIF_Pos (8) /*!< USPI_T::PROTSTS: SSINAIF Position */ +#define USPI_PROTSTS_SSINAIF_Msk (0x1ul << USPI_PROTSTS_SSINAIF_Pos) /*!< USPI_T::PROTSTS: SSINAIF Mask */ + +#define USPI_PROTSTS_SSACTIF_Pos (9) /*!< USPI_T::PROTSTS: SSACTIF Position */ +#define USPI_PROTSTS_SSACTIF_Msk (0x1ul << USPI_PROTSTS_SSACTIF_Pos) /*!< USPI_T::PROTSTS: SSACTIF Mask */ + +#define USPI_PROTSTS_SSLINE_Pos (16) /*!< USPI_T::PROTSTS: SSLINE Position */ +#define USPI_PROTSTS_SSLINE_Msk (0x1ul << USPI_PROTSTS_SSLINE_Pos) /*!< USPI_T::PROTSTS: SSLINE Mask */ + +#define USPI_PROTSTS_BUSY_Pos (17) /*!< USPI_T::PROTSTS: BUSY Position */ +#define USPI_PROTSTS_BUSY_Msk (0x1ul << USPI_PROTSTS_BUSY_Pos) /*!< USPI_T::PROTSTS: BUSY Mask */ + +#define USPI_PROTSTS_SLVUDR_Pos (18) /*!< USPI_T::PROTSTS: SLVUDR Position */ +#define USPI_PROTSTS_SLVUDR_Msk (0x1ul << USPI_PROTSTS_SLVUDR_Pos) /*!< USPI_T::PROTSTS: SLVUDR Mask */ + +/**@}*/ /* USPI_CONST */ +/**@}*/ /* end of USPI register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __USPI_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/uuart_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/uuart_reg.h new file mode 100644 index 0000000000..7db6134a85 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/uuart_reg.h @@ -0,0 +1,662 @@ +/**************************************************************************//** + * @file uuart_reg.h + * @version V1.00 + * @brief UUART register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __UUART_REG_H__ +#define __UUART_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- UART Mode of USCI Controller -------------------------*/ +/** + @addtogroup UUART UART Mode of USCI Controller(UUART) + Memory Mapped Structure for UUART Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var UUART_T::CTL + * Offset: 0x00 USCI Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[2:0] |FUNMODE |Function Mode + * | | |This bit field selects the protocol for this USCI controller. + * | | |Selecting a protocol that is not available or a reserved combination disables the USCI. + * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol. + * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. + * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. + * | | |001 = The SPI protocol is selected. + * | | |010 = The UART protocol is selected. + * | | |100 = The I2C protocol is selected. + * | | |Others = Reserved. + * @var UUART_T::INTEN + * Offset: 0x04 USCI Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIEN |Transmit Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit start event. + * | | |0 = The transmit start interrupt is disabled. + * | | |1 = The transmit start interrupt is enabled. + * |[2] |TXENDIEN |Transmit End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a transmit finish event. + * | | |0 = The transmit finish interrupt is disabled. + * | | |1 = The transmit finish interrupt is enabled. + * |[3] |RXSTIEN |Receive Start Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive start event. + * | | |0 = The receive start interrupt is disabled. + * | | |1 = The receive start interrupt is enabled. + * |[4] |RXENDIEN |Receive End Interrupt Enable Bit + * | | |This bit enables the interrupt generation in case of a receive finish event. + * | | |0 = The receive end interrupt is disabled. + * | | |1 = The receive end interrupt is enabled. + * @var UUART_T::BRGEN + * Offset: 0x08 USCI Baud Rate Generator Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RCLKSEL |Reference Clock Source Selection + * | | |This bit selects the source signal of reference clock (fREF_CLK). + * | | |0 = Peripheral device clock fPCLK. + * | | |1 = Reserved. + * |[1] |PTCLKSEL |Protocol Clock Source Selection + * | | |This bit selects the source signal of protocol clock (fPROT_CLK). + * | | |0 = Reference clock fREF_CLK. + * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). + * |[3:2] |SPCLKSEL |Sample Clock Source Selection + * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. + * | | |00 = fSAMP_CLK frequency is fDIV_CLK. + * | | |01 = fSAMP_CLK frequency is from fPROT_CLK. + * | | |10 = fSAMP_CLK frequency is from fSCLK. + * | | |11 = fSAMP_CLK frequency is from fREF_CLK. + * |[4] |TMCNTEN |Timing Measurement Counter Enable Bit + * | | |This bit enables the 10-bit timing measurement counter. + * | | |0 = Timing measurement counter is Disabled. + * | | |1 = Timing measurement counter is Enabled. + * |[5] |TMCNTSRC |Timing Measurement Counter Clock Source Selection + * | | |0 = Timing measurement counter with fPROT_CLK. + * | | |1 = Timing measurement counter with fDIV_CLK. + * |[9:8] |PDSCNT |Pre-divider for Sample Counter + * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK. + * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). + * |[14:10] |DSCNT |Denominator for Sample Counter + * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. + * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). + * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value. + * |[25:16] |CLKDIV |Clock Divider + * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). + * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. + * | | |The revised value is the average bit time between bit 5 and bit 6. + * | | |The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate. + * @var UUART_T::DATIN0 + * Offset: 0x10 USCI Input Data Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Signal Synchronization Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * |[4:3] |EDGEDET |Input Signal Edge Detection Mode + * | | |This bit field selects which edge actives the trigger event of input data signal. + * | | |00 = The trigger event activation is disabled. + * | | |01 = A rising edge activates the trigger event of input data signal. + * | | |10 = A falling edge activates the trigger event of input data signal. + * | | |11 = Both edges activate the trigger event of input data signal. + * | | |Note: In UART function mode, it is suggested to set this bit field as 10. + * @var UUART_T::CTLIN0 + * Offset: 0x20 USCI Input Control Signal Configuration Register 0 + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * |[2] |ININV |Input Signal Inverse Selection + * | | |This bit defines the inverter enable of the input asynchronous signal. + * | | |0 = The un-synchronized input signal will not be inverted. + * | | |1 = The un-synchronized input signal will be inverted. + * @var UUART_T::CLKIN + * Offset: 0x28 USCI Input Clock Signal Configuration Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |SYNCSEL |Input Synchronization Signal Selection + * | | |This bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit. + * | | |0 = The un-synchronized signal can be taken as input for the data shift unit. + * | | |1 = The synchronized signal can be taken as input for the data shift unit. + * @var UUART_T::LINECTL + * Offset: 0x2C USCI Line Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |LSB |LSB First Transmission Selection + * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. + * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. + * |[5] |DATOINV |Data Output Inverse Selection + * | | |This bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin. + * | | |0 = The value of USCIx_DAT1 is equal to the data shift register. + * | | |1 = The value of USCIx_DAT1 is the inversion of data shift register. + * |[7] |CTLOINV |Control Signal Output Inverse Selection + * | | |This bit defines the relation between the internal control signal and the output control signal. + * | | |0 = No effect. + * | | |1 = The control signal will be inverted before its output. + * | | |Note: In UART protocol, the control signal means nRTS signal. + * |[11:8] |DWIDTH |Word Length of Transmission + * | | |This bit field defines the data word length (amount of bits) for reception and transmission + * | | |The data word is always right-aligned in the data buffer + * | | |USCI support word length from 4 to 16 bits. + * | | |0x0 = The data word contains 16 bits located at bit positions [15:0]. + * | | |0x1 = Reserved. + * | | |0x2 = Reserved. + * | | |0x3 = Reserved. + * | | |0x4 = The data word contains 4 bits located at bit positions [3:0]. + * | | |0x5 = The data word contains 5 bits located at bit positions [4:0]. + * | | |... + * | | |0xF = The data word contains 15 bits located at bit positions [14:0]. + * | | |Note: In UART protocol, the length can be configured as 6~13 bits. + * @var UUART_T::TXDAT + * Offset: 0x30 USCI Transmit Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |TXDAT |Transmit Data + * | | |Software can use this bit field to write 16-bit transmit data for transmission. + * @var UUART_T::RXDAT + * Offset: 0x34 USCI Receive Data Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[15:0] |RXDAT |Received Data + * | | |This bit field monitors the received data which stored in receive data buffer. + * | | |Note: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]). + * @var UUART_T::BUFCTL + * Offset: 0x38 USCI Transmit/Receive Buffer Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[7] |TXCLR |Clear Transmit Buffer + * | | |0 = No effect. + * | | |1 = The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[14] |RXOVIEN |Receive Buffer Overrun Error Interrupt Enable Control + * | | |0 = Receive overrun interrupt Disabled. + * | | |1 = Receive overrun interrupt Enabled. + * |[15] |RXCLR |Clear Receive Buffer + * | | |0 = No effect. + * | | |1 = The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). + * | | |Should only be used while the buffer is not taking part in data traffic. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[16] |TXRST |Transmit Reset + * | | |0 = No effect. + * | | |1 = Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer. + * | | |Note: It is cleared automatically after one PCLK cycle. + * |[17] |RXRST |Receive Reset + * | | |0 = No effect. + * | | |1 = Reset the receive-related counters, state machine, and the content of receive shift register and data buffer. + * | | |Note1: It is cleared automatically after one PCLK cycle. + * | | |Note2: It is suggest to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1. + * @var UUART_T::BUFSTS + * Offset: 0x3C USCI Transmit/Receive Buffer Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |RXEMPTY |Receive Buffer Empty Indicator + * | | |0 = Receive buffer is not empty. + * | | |1 = Receive buffer is empty. + * |[1] |RXFULL |Receive Buffer Full Indicator + * | | |0 = Receive buffer is not full. + * | | |1 = Receive buffer is full. + * |[3] |RXOVIF |Receive Buffer Over-run Error Interrupt Status + * | | |This bit indicates that a receive buffer overrun error event has been detected. + * | | |If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. + * | | |It is cleared by software writes 1 to this bit. + * | | |0 = A receive buffer overrun error event has not been detected. + * | | |1 = A receive buffer overrun error event has been detected. + * |[8] |TXEMPTY |Transmit Buffer Empty Indicator + * | | |0 = Transmit buffer is not empty. + * | | |1 = Transmit buffer is empty. + * |[9] |TXFULL |Transmit Buffer Full Indicator + * | | |0 = Transmit buffer is not full. + * | | |1 = Transmit buffer is full. + * @var UUART_T::PDMACTL + * Offset: 0x40 USCI PDMA Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |PDMARST |PDMA Reset + * | | |0 = No effect. + * | | |1 = Reset the USCI PDMA control logic. This bit will be cleared to 0 automatically. + * |[1] |TXPDMAEN |PDMA Transmit Channel Available + * | | |0 = Transmit PDMA function Disabled. + * | | |1 = Transmit PDMA function Enabled. + * |[2] |RXPDMAEN |PDMA Receive Channel Available + * | | |0 = Receive PDMA function Disabled. + * | | |1 = Receive PDMA function Enabled. + * |[3] |PDMAEN |PDMA Mode Enable Bit + * | | |0 = PDMA function Disabled. + * | | |1 = PDMA function Enabled. + * @var UUART_T::WKCTL + * Offset: 0x54 USCI Wake-up Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKEN |Wake-up Enable Bit + * | | |0 = Wake-up function Disabled. + * | | |1 = Wake-up function Enabled. + * |[2] |PDBOPT |Power Down Blocking Option + * | | |0 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately. + * | | |1 = If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately. + * @var UUART_T::WKSTS + * Offset: 0x58 USCI Wake-up Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WKF |Wake-up Flag + * | | |When chip is woken up from Power-down mode, this bit is set to 1 + * | | |Software can write 1 to clear this bit. + * @var UUART_T::PROTCTL + * Offset: 0x5C USCI Protocol Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |STOPB |Stop Bits + * | | |This bit defines the number of stop bits in an UART frame. + * | | |0 = The number of stop bits is 1. + * | | |1 = The number of stop bits is 2. + * |[1] |PARITYEN |Parity Enable Bit + * | | |This bit defines the parity bit is enabled in an UART frame. + * | | |0 = The parity bit Disabled. + * | | |1 = The parity bit Enabled. + * |[2] |EVENPARITY|Even Parity Enable Bit + * | | |0 = Odd number of logic 1's is transmitted and checked in each word. + * | | |1 = Even number of logic 1's is transmitted and checked in each word. + * | | |Note: This bit has effect only when PARITYEN is set. + * |[3] |RTSAUTOEN |nRTS Auto-flow Control Enable Bit + * | | |When nRTS auto-flow is enabled, if the receiver buffer is full (RXFULL (UUART_BUFSTS[1] = 1)), the UART will de-assert nRTS signal. + * | | |0 = nRTS auto-flow control Disabled. + * | | |1 = nRTS auto-flow control Enabled. + * | | |Note: This bit has effect only when the RTSAUDIREN is not set. + * |[4] |CTSAUTOEN |nCTS Auto-flow Control Enable Bit + * | | |When nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted). + * | | |0 = nCTS auto-flow control Disabled. + * | | |1 = nCTS auto-flow control Enabled. + * |[5] |RTSAUDIREN|nRTS Auto Direction Enable Bit + * | | |When nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the nRTS signal is inactive. + * | | |0 = nRTS auto direction control Disabled. + * | | |1 = nRTS auto direction control Enabled. + * | | |Note1: This bit is used for nRTS auto direction control for RS485. + * | | |Note2: This bit has effect only when the RTSAUTOEN is not set. + * |[6] |ABREN |Auto-baud Rate Detect Enable Bit + * | | |0 = Auto-baud rate detect function Disabled. + * | | |1 = Auto-baud rate detect function Enabled. + * | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit. + * | | |The associated interrupt ABRDETIF (UUART_PROTSTS[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). + * |[9] |DATWKEN |Data Wake-up Mode Enable Bit + * | | |0 = Data wake-up mode Disabled. + * | | |1 = Data wake-up mode Enabled. + * |[10] |CTSWKEN |nCTS Wake-up Mode Enable Bit + * | | |0 = nCTS wake-up mode Disabled. + * | | |1 = nCTS wake-up mode Enabled. + * |[14:11] |WAKECNT |Wake-up Counter + * | | |These bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode. + * |[24:16] |BRDETITV |Baud Rate Detection Interval + * | | |This bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. + * | | |The order of the bus shall be 1 and 0 step by step (e.g + * | | |the input data pattern shall be 0x55) + * | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set. + * | | |Note: This bit can be cleared to 0 by software writing 1 to the BRDETITV. + * |[26] |STICKEN |Stick Parity Enable Bit + * | | |0 = Stick parity Disabled. + * | | |1 = Stick parity Enabled. + * | | |Note: Refer to RS-485 Support section for detail information. + * |[29] |BCEN |Transmit Break Control Enable Bit + * | | |0 = Transmit Break Control Disabled. + * | | |1 = Transmit Break Control Enabled. + * | | |Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). + * | | |This bit acts only on TX line and has no effect on the transmitter logic. + * |[31] |PROTEN |UART Protocol Enable Bit + * | | |0 = UART Protocol Disabled. + * | | |1 = UART Protocol Enabled. + * @var UUART_T::PROTIEN + * Offset: 0x60 USCI Protocol Interrupt Enable Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |ABRIEN |Auto-baud Rate Interrupt Enable Bit + * | | |0 = Auto-baud rate interrupt Disabled. + * | | |1 = Auto-baud rate interrupt Enabled. + * |[2] |RLSIEN |Receive Line Status Interrupt Enable Bit + * | | |0 = Receive line status interrupt Disabled. + * | | |1 = Receive line status interrupt Enabled. + * | | |Note: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt. + * @var UUART_T::PROTSTS + * Offset: 0x64 USCI Protocol Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |TXSTIF |Transmit Start Interrupt Flag + * | | |0 = A transmit start interrupt status has not occurred. + * | | |1 = A transmit start interrupt status has occurred. + * | | |Note1: It is cleared by software writing one into this bit. + * | | |Note2: Used for user to load next transmit data when there is no data in transmit buffer. + * |[2] |TXENDIF |Transmit End Interrupt Flag + * | | |0 = A transmit end interrupt status has not occurred. + * | | |1 = A transmit end interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[3] |RXSTIF |Receive Start Interrupt Flag + * | | |0 = A receive start interrupt status has not occurred. + * | | |1 = A receive start interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[4] |RXENDIF |Receive End Interrupt Flag + * | | |0 = A receive finish interrupt status has not occurred. + * | | |1 = A receive finish interrupt status has occurred. + * | | |Note: It is cleared by software writing one into this bit. + * |[5] |PARITYERR |Parity Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. + * | | |0 = No parity error is generated. + * | | |1 = Parity error is generated. + * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. + * |[6] |FRMERR |Framing Error Flag + * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). + * | | |0 = No framing error is generated. + * | | |1 = Framing error is generated. + * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. + * |[7] |BREAK |Break Flag + * | | |This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). + * | | |0 = No Break is generated. + * | | |1 = Break is generated in the receiver bus. + * | | |Note: This bit can be cleared by write 1 among the BREAK, FRMERR and PARITYERR bits. + * |[9] |ABRDETIF |Auto-baud Rate Interrupt Flag + * | | |This bit is set when auto-baud rate detection is done among the falling edge of the input data. + * | | |If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. + * | | |This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus. + * | | |0 = Auto-baud rate detect function is not done. + * | | |1 = One Bit auto-baud rate detect function is done. + * | | |Note: This bit can be cleared by writing 1 to it. + * |[10] |RXBUSY |RX Bus Status Flag (Read Only) + * | | |This bit indicates the busy status of the receiver. + * | | |0 = The receiver is Idle. + * | | |1 = The receiver is BUSY. + * |[11] |ABERRSTS |Auto-baud Rate Error Status + * | | |This bit is set when auto-baud rate detection counter overrun. + * | | |When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again. + * | | |0 = Auto-baud rate detect counter is not overrun. + * | | |1 = Auto-baud rate detect counter is overrun. + * | | |Note1: This bit is set at the same time of ABRDETIF. + * | | |Note2: This bit can be cleared by writing 1 to ABRDETIF or ABERRSTS. + * |[16] |CTSSYNCLV |nCTS Synchronized Level Status (Read Only) + * | | |This bit used to indicate the current status of the internal synchronized nCTS signal. + * | | |0 = The internal synchronized nCTS is low. + * | | |1 = The internal synchronized nCTS is high. + * |[17] |CTSLV |nCTS Pin Status (Read Only) + * | | |This bit used to monitor the current status of nCTS pin input. + * | | |0 = nCTS pin input is low level voltage logic state. + * | | |1 = nCTS pin input is high level voltage logic state. + */ + + __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ + __IO uint32_t INTEN; /*!< [0x0004] USCI Interrupt Enable Register */ + __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ + __I uint32_t RESERVE0[1]; + __IO uint32_t DATIN0; /*!< [0x0010] USCI Input Data Signal Configuration Register 0 */ + __I uint32_t RESERVE1[3]; + __IO uint32_t CTLIN0; /*!< [0x0020] USCI Input Control Signal Configuration Register 0 */ + __I uint32_t RESERVE2[1]; + __IO uint32_t CLKIN; /*!< [0x0028] USCI Input Clock Signal Configuration Register */ + __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ + __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ + __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ + __IO uint32_t BUFCTL; /*!< [0x0038] USCI Transmit/Receive Buffer Control Register */ + __IO uint32_t BUFSTS; /*!< [0x003c] USCI Transmit/Receive Buffer Status Register */ + __IO uint32_t PDMACTL; /*!< [0x0040] USCI PDMA Control Register */ + __I uint32_t RESERVE3[4]; + __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ + __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ + __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ + __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ + __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ + +} UUART_T; + +/** + @addtogroup UUART_CONST UUART Bit Field Definition + Constant Definitions for UUART Controller + @{ +*/ + +#define UUART_CTL_FUNMODE_Pos (0) /*!< UUART_T::CTL: FUNMODE Position */ +#define UUART_CTL_FUNMODE_Msk (0x7ul << UUART_CTL_FUNMODE_Pos) /*!< UUART_T::CTL: FUNMODE Mask */ + +#define UUART_INTEN_TXSTIEN_Pos (1) /*!< UUART_T::INTEN: TXSTIEN Position */ +#define UUART_INTEN_TXSTIEN_Msk (0x1ul << UUART_INTEN_TXSTIEN_Pos) /*!< UUART_T::INTEN: TXSTIEN Mask */ + +#define UUART_INTEN_TXENDIEN_Pos (2) /*!< UUART_T::INTEN: TXENDIEN Position */ +#define UUART_INTEN_TXENDIEN_Msk (0x1ul << UUART_INTEN_TXENDIEN_Pos) /*!< UUART_T::INTEN: TXENDIEN Mask */ + +#define UUART_INTEN_RXSTIEN_Pos (3) /*!< UUART_T::INTEN: RXSTIEN Position */ +#define UUART_INTEN_RXSTIEN_Msk (0x1ul << UUART_INTEN_RXSTIEN_Pos) /*!< UUART_T::INTEN: RXSTIEN Mask */ + +#define UUART_INTEN_RXENDIEN_Pos (4) /*!< UUART_T::INTEN: RXENDIEN Position */ +#define UUART_INTEN_RXENDIEN_Msk (0x1ul << UUART_INTEN_RXENDIEN_Pos) /*!< UUART_T::INTEN: RXENDIEN Mask */ + +#define UUART_BRGEN_RCLKSEL_Pos (0) /*!< UUART_T::BRGEN: RCLKSEL Position */ +#define UUART_BRGEN_RCLKSEL_Msk (0x1ul << UUART_BRGEN_RCLKSEL_Pos) /*!< UUART_T::BRGEN: RCLKSEL Mask */ + +#define UUART_BRGEN_PTCLKSEL_Pos (1) /*!< UUART_T::BRGEN: PTCLKSEL Position */ +#define UUART_BRGEN_PTCLKSEL_Msk (0x1ul << UUART_BRGEN_PTCLKSEL_Pos) /*!< UUART_T::BRGEN: PTCLKSEL Mask */ + +#define UUART_BRGEN_SPCLKSEL_Pos (2) /*!< UUART_T::BRGEN: SPCLKSEL Position */ +#define UUART_BRGEN_SPCLKSEL_Msk (0x3ul << UUART_BRGEN_SPCLKSEL_Pos) /*!< UUART_T::BRGEN: SPCLKSEL Mask */ + +#define UUART_BRGEN_TMCNTEN_Pos (4) /*!< UUART_T::BRGEN: TMCNTEN Position */ +#define UUART_BRGEN_TMCNTEN_Msk (0x1ul << UUART_BRGEN_TMCNTEN_Pos) /*!< UUART_T::BRGEN: TMCNTEN Mask */ + +#define UUART_BRGEN_TMCNTSRC_Pos (5) /*!< UUART_T::BRGEN: TMCNTSRC Position */ +#define UUART_BRGEN_TMCNTSRC_Msk (0x1ul << UUART_BRGEN_TMCNTSRC_Pos) /*!< UUART_T::BRGEN: TMCNTSRC Mask */ + +#define UUART_BRGEN_PDSCNT_Pos (8) /*!< UUART_T::BRGEN: PDSCNT Position */ +#define UUART_BRGEN_PDSCNT_Msk (0x3ul << UUART_BRGEN_PDSCNT_Pos) /*!< UUART_T::BRGEN: PDSCNT Mask */ + +#define UUART_BRGEN_DSCNT_Pos (10) /*!< UUART_T::BRGEN: DSCNT Position */ +#define UUART_BRGEN_DSCNT_Msk (0x1ful << UUART_BRGEN_DSCNT_Pos) /*!< UUART_T::BRGEN: DSCNT Mask */ + +#define UUART_BRGEN_CLKDIV_Pos (16) /*!< UUART_T::BRGEN: CLKDIV Position */ +#define UUART_BRGEN_CLKDIV_Msk (0x3fful << UUART_BRGEN_CLKDIV_Pos) /*!< UUART_T::BRGEN: CLKDIV Mask */ + +#define UUART_DATIN0_SYNCSEL_Pos (0) /*!< UUART_T::DATIN0: SYNCSEL Position */ +#define UUART_DATIN0_SYNCSEL_Msk (0x1ul << UUART_DATIN0_SYNCSEL_Pos) /*!< UUART_T::DATIN0: SYNCSEL Mask */ + +#define UUART_DATIN0_ININV_Pos (2) /*!< UUART_T::DATIN0: ININV Position */ +#define UUART_DATIN0_ININV_Msk (0x1ul << UUART_DATIN0_ININV_Pos) /*!< UUART_T::DATIN0: ININV Mask */ + +#define UUART_DATIN0_EDGEDET_Pos (3) /*!< UUART_T::DATIN0: EDGEDET Position */ +#define UUART_DATIN0_EDGEDET_Msk (0x3ul << UUART_DATIN0_EDGEDET_Pos) /*!< UUART_T::DATIN0: EDGEDET Mask */ + +#define UUART_CTLIN0_SYNCSEL_Pos (0) /*!< UUART_T::CTLIN0: SYNCSEL Position */ +#define UUART_CTLIN0_SYNCSEL_Msk (0x1ul << UUART_CTLIN0_SYNCSEL_Pos) /*!< UUART_T::CTLIN0: SYNCSEL Mask */ + +#define UUART_CTLIN0_ININV_Pos (2) /*!< UUART_T::CTLIN0: ININV Position */ +#define UUART_CTLIN0_ININV_Msk (0x1ul << UUART_CTLIN0_ININV_Pos) /*!< UUART_T::CTLIN0: ININV Mask */ + +#define UUART_CLKIN_SYNCSEL_Pos (0) /*!< UUART_T::CLKIN: SYNCSEL Position */ +#define UUART_CLKIN_SYNCSEL_Msk (0x1ul << UUART_CLKIN_SYNCSEL_Pos) /*!< UUART_T::CLKIN: SYNCSEL Mask */ + +#define UUART_LINECTL_LSB_Pos (0) /*!< UUART_T::LINECTL: LSB Position */ +#define UUART_LINECTL_LSB_Msk (0x1ul << UUART_LINECTL_LSB_Pos) /*!< UUART_T::LINECTL: LSB Mask */ + +#define UUART_LINECTL_DATOINV_Pos (5) /*!< UUART_T::LINECTL: DATOINV Position */ +#define UUART_LINECTL_DATOINV_Msk (0x1ul << UUART_LINECTL_DATOINV_Pos) /*!< UUART_T::LINECTL: DATOINV Mask */ + +#define UUART_LINECTL_CTLOINV_Pos (7) /*!< UUART_T::LINECTL: CTLOINV Position */ +#define UUART_LINECTL_CTLOINV_Msk (0x1ul << UUART_LINECTL_CTLOINV_Pos) /*!< UUART_T::LINECTL: CTLOINV Mask */ + +#define UUART_LINECTL_DWIDTH_Pos (8) /*!< UUART_T::LINECTL: DWIDTH Position */ +#define UUART_LINECTL_DWIDTH_Msk (0xful << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_T::LINECTL: DWIDTH Mask */ + +#define UUART_TXDAT_TXDAT_Pos (0) /*!< UUART_T::TXDAT: TXDAT Position */ +#define UUART_TXDAT_TXDAT_Msk (0xfffful << UUART_TXDAT_TXDAT_Pos) /*!< UUART_T::TXDAT: TXDAT Mask */ + +#define UUART_RXDAT_RXDAT_Pos (0) /*!< UUART_T::RXDAT: RXDAT Position */ +#define UUART_RXDAT_RXDAT_Msk (0xfffful << UUART_RXDAT_RXDAT_Pos) /*!< UUART_T::RXDAT: RXDAT Mask */ + +#define UUART_BUFCTL_TXCLR_Pos (7) /*!< UUART_T::BUFCTL: TXCLR Position */ +#define UUART_BUFCTL_TXCLR_Msk (0x1ul << UUART_BUFCTL_TXCLR_Pos) /*!< UUART_T::BUFCTL: TXCLR Mask */ + +#define UUART_BUFCTL_RXOVIEN_Pos (14) /*!< UUART_T::BUFCTL: RXOVIEN Position */ +#define UUART_BUFCTL_RXOVIEN_Msk (0x1ul << UUART_BUFCTL_RXOVIEN_Pos) /*!< UUART_T::BUFCTL: RXOVIEN Mask */ + +#define UUART_BUFCTL_RXCLR_Pos (15) /*!< UUART_T::BUFCTL: RXCLR Position */ +#define UUART_BUFCTL_RXCLR_Msk (0x1ul << UUART_BUFCTL_RXCLR_Pos) /*!< UUART_T::BUFCTL: RXCLR Mask */ + +#define UUART_BUFCTL_TXRST_Pos (16) /*!< UUART_T::BUFCTL: TXRST Position */ +#define UUART_BUFCTL_TXRST_Msk (0x1ul << UUART_BUFCTL_TXRST_Pos) /*!< UUART_T::BUFCTL: TXRST Mask */ + +#define UUART_BUFCTL_RXRST_Pos (17) /*!< UUART_T::BUFCTL: RXRST Position */ +#define UUART_BUFCTL_RXRST_Msk (0x1ul << UUART_BUFCTL_RXRST_Pos) /*!< UUART_T::BUFCTL: RXRST Mask */ + +#define UUART_BUFSTS_RXEMPTY_Pos (0) /*!< UUART_T::BUFSTS: RXEMPTY Position */ +#define UUART_BUFSTS_RXEMPTY_Msk (0x1ul << UUART_BUFSTS_RXEMPTY_Pos) /*!< UUART_T::BUFSTS: RXEMPTY Mask */ + +#define UUART_BUFSTS_RXFULL_Pos (1) /*!< UUART_T::BUFSTS: RXFULL Position */ +#define UUART_BUFSTS_RXFULL_Msk (0x1ul << UUART_BUFSTS_RXFULL_Pos) /*!< UUART_T::BUFSTS: RXFULL Mask */ + +#define UUART_BUFSTS_RXOVIF_Pos (3) /*!< UUART_T::BUFSTS: RXOVIF Position */ +#define UUART_BUFSTS_RXOVIF_Msk (0x1ul << UUART_BUFSTS_RXOVIF_Pos) /*!< UUART_T::BUFSTS: RXOVIF Mask */ + +#define UUART_BUFSTS_TXEMPTY_Pos (8) /*!< UUART_T::BUFSTS: TXEMPTY Position */ +#define UUART_BUFSTS_TXEMPTY_Msk (0x1ul << UUART_BUFSTS_TXEMPTY_Pos) /*!< UUART_T::BUFSTS: TXEMPTY Mask */ + +#define UUART_BUFSTS_TXFULL_Pos (9) /*!< UUART_T::BUFSTS: TXFULL Position */ +#define UUART_BUFSTS_TXFULL_Msk (0x1ul << UUART_BUFSTS_TXFULL_Pos) /*!< UUART_T::BUFSTS: TXFULL Mask */ + +#define UUART_PDMACTL_PDMARST_Pos (0) /*!< UUART_T::PDMACTL: PDMARST Position */ +#define UUART_PDMACTL_PDMARST_Msk (0x1ul << UUART_PDMACTL_PDMARST_Pos) /*!< UUART_T::PDMACTL: PDMARST Mask */ + +#define UUART_PDMACTL_TXPDMAEN_Pos (1) /*!< UUART_T::PDMACTL: TXPDMAEN Position */ +#define UUART_PDMACTL_TXPDMAEN_Msk (0x1ul << UUART_PDMACTL_TXPDMAEN_Pos) /*!< UUART_T::PDMACTL: TXPDMAEN Mask */ + +#define UUART_PDMACTL_RXPDMAEN_Pos (2) /*!< UUART_T::PDMACTL: RXPDMAEN Position */ +#define UUART_PDMACTL_RXPDMAEN_Msk (0x1ul << UUART_PDMACTL_RXPDMAEN_Pos) /*!< UUART_T::PDMACTL: RXPDMAEN Mask */ + +#define UUART_PDMACTL_PDMAEN_Pos (3) /*!< UUART_T::PDMACTL: PDMAEN Position */ +#define UUART_PDMACTL_PDMAEN_Msk (0x1ul << UUART_PDMACTL_PDMAEN_Pos) /*!< UUART_T::PDMACTL: PDMAEN Mask */ + +#define UUART_WKCTL_WKEN_Pos (0) /*!< UUART_T::WKCTL: WKEN Position */ +#define UUART_WKCTL_WKEN_Msk (0x1ul << UUART_WKCTL_WKEN_Pos) /*!< UUART_T::WKCTL: WKEN Mask */ + +#define UUART_WKCTL_PDBOPT_Pos (2) /*!< UUART_T::WKCTL: PDBOPT Position */ +#define UUART_WKCTL_PDBOPT_Msk (0x1ul << UUART_WKCTL_PDBOPT_Pos) /*!< UUART_T::WKCTL: PDBOPT Mask */ + +#define UUART_WKSTS_WKF_Pos (0) /*!< UUART_T::WKSTS: WKF Position */ +#define UUART_WKSTS_WKF_Msk (0x1ul << UUART_WKSTS_WKF_Pos) /*!< UUART_T::WKSTS: WKF Mask */ + +#define UUART_PROTCTL_STOPB_Pos (0) /*!< UUART_T::PROTCTL: STOPB Position */ +#define UUART_PROTCTL_STOPB_Msk (0x1ul << UUART_PROTCTL_STOPB_Pos) /*!< UUART_T::PROTCTL: STOPB Mask */ + +#define UUART_PROTCTL_PARITYEN_Pos (1) /*!< UUART_T::PROTCTL: PARITYEN Position */ +#define UUART_PROTCTL_PARITYEN_Msk (0x1ul << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_T::PROTCTL: PARITYEN Mask */ + +#define UUART_PROTCTL_EVENPARITY_Pos (2) /*!< UUART_T::PROTCTL: EVENPARITY Position */ +#define UUART_PROTCTL_EVENPARITY_Msk (0x1ul << UUART_PROTCTL_EVENPARITY_Pos) /*!< UUART_T::PROTCTL: EVENPARITY Mask */ + +#define UUART_PROTCTL_RTSAUTOEN_Pos (3) /*!< UUART_T::PROTCTL: RTSAUTOEN Position */ +#define UUART_PROTCTL_RTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_RTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: RTSAUTOEN Mask */ + +#define UUART_PROTCTL_CTSAUTOEN_Pos (4) /*!< UUART_T::PROTCTL: CTSAUTOEN Position */ +#define UUART_PROTCTL_CTSAUTOEN_Msk (0x1ul << UUART_PROTCTL_CTSAUTOEN_Pos) /*!< UUART_T::PROTCTL: CTSAUTOEN Mask */ + +#define UUART_PROTCTL_RTSAUDIREN_Pos (5) /*!< UUART_T::PROTCTL: RTSAUDIREN Position */ +#define UUART_PROTCTL_RTSAUDIREN_Msk (0x1ul << UUART_PROTCTL_RTSAUDIREN_Pos) /*!< UUART_T::PROTCTL: RTSAUDIREN Mask */ + +#define UUART_PROTCTL_ABREN_Pos (6) /*!< UUART_T::PROTCTL: ABREN Position */ +#define UUART_PROTCTL_ABREN_Msk (0x1ul << UUART_PROTCTL_ABREN_Pos) /*!< UUART_T::PROTCTL: ABREN Mask */ + +#define UUART_PROTCTL_DATWKEN_Pos (9) /*!< UUART_T::PROTCTL: DATWKEN Position */ +#define UUART_PROTCTL_DATWKEN_Msk (0x1ul << UUART_PROTCTL_DATWKEN_Pos) /*!< UUART_T::PROTCTL: DATWKEN Mask */ + +#define UUART_PROTCTL_CTSWKEN_Pos (10) /*!< UUART_T::PROTCTL: CTSWKEN Position */ +#define UUART_PROTCTL_CTSWKEN_Msk (0x1ul << UUART_PROTCTL_CTSWKEN_Pos) /*!< UUART_T::PROTCTL: CTSWKEN Mask */ + +#define UUART_PROTCTL_WAKECNT_Pos (11) /*!< UUART_T::PROTCTL: WAKECNT Position */ +#define UUART_PROTCTL_WAKECNT_Msk (0xful << UUART_PROTCTL_WAKECNT_Pos) /*!< UUART_T::PROTCTL: WAKECNT Mask */ + +#define UUART_PROTCTL_BRDETITV_Pos (16) /*!< UUART_T::PROTCTL: BRDETITV Position */ +#define UUART_PROTCTL_BRDETITV_Msk (0x1fful << UUART_PROTCTL_BRDETITV_Pos) /*!< UUART_T::PROTCTL: BRDETITV Mask */ + +#define UUART_PROTCTL_STICKEN_Pos (26) /*!< UUART_T::PROTCTL: STICKEN Position */ +#define UUART_PROTCTL_STICKEN_Msk (0x1ul << UUART_PROTCTL_STICKEN_Pos) /*!< UUART_T::PROTCTL: STICKEN Mask */ + +#define UUART_PROTCTL_BCEN_Pos (29) /*!< UUART_T::PROTCTL: BCEN Position */ +#define UUART_PROTCTL_BCEN_Msk (0x1ul << UUART_PROTCTL_BCEN_Pos) /*!< UUART_T::PROTCTL: BCEN Mask */ + +#define UUART_PROTCTL_PROTEN_Pos (31) /*!< UUART_T::PROTCTL: PROTEN Position */ +#define UUART_PROTCTL_PROTEN_Msk (0x1ul << UUART_PROTCTL_PROTEN_Pos) /*!< UUART_T::PROTCTL: PROTEN Mask */ + +#define UUART_PROTIEN_ABRIEN_Pos (1) /*!< UUART_T::PROTIEN: ABRIEN Position */ +#define UUART_PROTIEN_ABRIEN_Msk (0x1ul << UUART_PROTIEN_ABRIEN_Pos) /*!< UUART_T::PROTIEN: ABRIEN Mask */ + +#define UUART_PROTIEN_RLSIEN_Pos (2) /*!< UUART_T::PROTIEN: RLSIEN Position */ +#define UUART_PROTIEN_RLSIEN_Msk (0x1ul << UUART_PROTIEN_RLSIEN_Pos) /*!< UUART_T::PROTIEN: RLSIEN Mask */ + +#define UUART_PROTSTS_TXSTIF_Pos (1) /*!< UUART_T::PROTSTS: TXSTIF Position */ +#define UUART_PROTSTS_TXSTIF_Msk (0x1ul << UUART_PROTSTS_TXSTIF_Pos) /*!< UUART_T::PROTSTS: TXSTIF Mask */ + +#define UUART_PROTSTS_TXENDIF_Pos (2) /*!< UUART_T::PROTSTS: TXENDIF Position */ +#define UUART_PROTSTS_TXENDIF_Msk (0x1ul << UUART_PROTSTS_TXENDIF_Pos) /*!< UUART_T::PROTSTS: TXENDIF Mask */ + +#define UUART_PROTSTS_RXSTIF_Pos (3) /*!< UUART_T::PROTSTS: RXSTIF Position */ +#define UUART_PROTSTS_RXSTIF_Msk (0x1ul << UUART_PROTSTS_RXSTIF_Pos) /*!< UUART_T::PROTSTS: RXSTIF Mask */ + +#define UUART_PROTSTS_RXENDIF_Pos (4) /*!< UUART_T::PROTSTS: RXENDIF Position */ +#define UUART_PROTSTS_RXENDIF_Msk (0x1ul << UUART_PROTSTS_RXENDIF_Pos) /*!< UUART_T::PROTSTS: RXENDIF Mask */ + +#define UUART_PROTSTS_PARITYERR_Pos (5) /*!< UUART_T::PROTSTS: PARITYERR Position */ +#define UUART_PROTSTS_PARITYERR_Msk (0x1ul << UUART_PROTSTS_PARITYERR_Pos) /*!< UUART_T::PROTSTS: PARITYERR Mask */ + +#define UUART_PROTSTS_FRMERR_Pos (6) /*!< UUART_T::PROTSTS: FRMERR Position */ +#define UUART_PROTSTS_FRMERR_Msk (0x1ul << UUART_PROTSTS_FRMERR_Pos) /*!< UUART_T::PROTSTS: FRMERR Mask */ + +#define UUART_PROTSTS_BREAK_Pos (7) /*!< UUART_T::PROTSTS: BREAK Position */ +#define UUART_PROTSTS_BREAK_Msk (0x1ul << UUART_PROTSTS_BREAK_Pos) /*!< UUART_T::PROTSTS: BREAK Mask */ + +#define UUART_PROTSTS_ABRDETIF_Pos (9) /*!< UUART_T::PROTSTS: ABRDETIF Position */ +#define UUART_PROTSTS_ABRDETIF_Msk (0x1ul << UUART_PROTSTS_ABRDETIF_Pos) /*!< UUART_T::PROTSTS: ABRDETIF Mask */ + +#define UUART_PROTSTS_RXBUSY_Pos (10) /*!< UUART_T::PROTSTS: RXBUSY Position */ +#define UUART_PROTSTS_RXBUSY_Msk (0x1ul << UUART_PROTSTS_RXBUSY_Pos) /*!< UUART_T::PROTSTS: RXBUSY Mask */ + +#define UUART_PROTSTS_ABERRSTS_Pos (11) /*!< UUART_T::PROTSTS: ABERRSTS Position */ +#define UUART_PROTSTS_ABERRSTS_Msk (0x1ul << UUART_PROTSTS_ABERRSTS_Pos) /*!< UUART_T::PROTSTS: ABERRSTS Mask */ + +#define UUART_PROTSTS_CTSSYNCLV_Pos (16) /*!< UUART_T::PROTSTS: CTSSYNCLV Position */ +#define UUART_PROTSTS_CTSSYNCLV_Msk (0x1ul << UUART_PROTSTS_CTSSYNCLV_Pos) /*!< UUART_T::PROTSTS: CTSSYNCLV Mask */ + +#define UUART_PROTSTS_CTSLV_Pos (17) /*!< UUART_T::PROTSTS: CTSLV Position */ +#define UUART_PROTSTS_CTSLV_Msk (0x1ul << UUART_PROTSTS_CTSLV_Pos) /*!< UUART_T::PROTSTS: CTSLV Mask */ + +/**@}*/ /* UUART_CONST */ +/**@}*/ /* end of UUART register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __UUART_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/wdt_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/wdt_reg.h new file mode 100644 index 0000000000..17024b5e14 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/wdt_reg.h @@ -0,0 +1,177 @@ +/**************************************************************************//** + * @file wdt_reg.h + * @version V1.00 + * @brief WDT register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_REG_H__ +#define __WDT_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Watch Dog Timer Controller -------------------------*/ +/** + @addtogroup WDT Watch Dog Timer Controller(WDT) + Memory Mapped Structure for WDT Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var WDT_T::CTL + * Offset: 0x00 WDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1] |RSTEN |WDT Time-out Reset Enable Control (Write Protect) + * | | |Setting this bit will enable the WDT time-out reset system function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires. + * | | |0 = WDT time-out reset system function Disabled. + * | | |1 = WDT time-out reset system function Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[2] |RSTF |WDT Time-out Reset Flag + * | | |This bit indicates the system has been reset by WDT time-out reset system event or not. + * | | |0 = WDT time-out reset system event did not occur. + * | | |1 = WDT time-out reset system event has been occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[3] |IF |WDT Time-out Interrupt Flag + * | | |This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval + * | | |0 = WDT time-out interrupt event interrupt did not occur. + * | | |1 = WDT time-out interrupt interrupt event occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * |[4] |WKEN |WDT Time-out Wake-up Function Control (Write Protect) + * | | |If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a event to trigger CPU wake-up trigger event to chip. + * | | |0 = Trigger wWake-up trigger event function Disabled if WDT time-out interrupt signal generated. + * | | |1 = Trigger Wake-up trigger event function Enabled if WDT time-out interrupt signal generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: Chip can be woken-up by while WDT time-out interrupt signal generated only if WDT clock source is selected to LIRC or LXT (32 kHz). + * |[5] |WKF |WDT Time-out Wake-up Flag (Write Protect) + * | | |This bit indicates the WDT time-out event has triggered interrupt chip wake-up or not.flag status of WDT + * | | |0 = WDT does not cause chip wake-up. + * | | |1 = Chip wake-up from Idle or Power-down mode if when WDT time-out interrupt signal is generated. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This bit is cleared by writing 1 to it. + * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect) + * | | |If this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and the WDT time-out interrupt signal is generated and inform to CPU. + * | | |0 = WDT time-out interrupt Disabled. + * | | |1 = WDT time-out interrupt Enabled. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[7] |WDTEN |WDT Enable Control (Write Protect) + * | | |0 = Set WDT counter stop Disabled, and (This action will reset the internal up counter value will be reset also). + * | | |1 = Set WDT counter start Enabled. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enable/disable command is completed or not. + * | | |Note32: If CWDTEN[2:0] (combined by with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0. + * | | |Note3: This bit disabled needs 2 * WDT_CLK. + * |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) + * | | |These three bits select the time-out interval period after for the WDT starts counting. + * | | |000 = 2^4 * WDT_CLK. + * | | |001 = 2^6 * WDT_CLK. + * | | |010 = 2^8 * WDT_CLK. + * | | |011 = 2^10 * WDT_CLK. + * | | |100 = 2^12 * WDT_CLK. + * | | |101 = 2^14 * WDT_CLK. + * | | |110 = 2^16 * WDT_CLK. + * | | |111 = 2^18 * WDT_CLK. + * | | |111 = 2^20 * WDT_CLK. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * |[30] |SYNC |WDT Enable Control SYNC SYNC Flag Indicator (Read Only) + * | | |If use to synchronization, software er can check execute enable/disable this flag after enable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is become completed or not active or not.. + * | | |SYNC delay is + * | | |0 = Set WDTEN bit is WDT enable control synccompletedhronizing is completion. + * | | |1 = Set WDTEN bit WDT enable control is synchronizing and not become active yet.. + * | | |Note: Perform enable or disable WDTEN bit + * | | |This bit enabled needs 2 * WDT_CLK period to become active. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) + * | | |0 = ICE debug mode acknowledgment affects WDT counting. + * | | |WDT up counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgment Disabled. + * | | |WDT up counter will keep going no matter CPU is held by ICE or not. + * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. + * @var WDT_T::ALTCTL + * Offset: 0x04 WDT Alternative Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[1:0] |RSTDSEL |WDT Reset Delay Period Selection (Write Protect) + * | | |When WDT time-out event happened, user has a time named WDT Reset Delay Period to clear execute WDT counter by setting RSTCNT (WDT_CTL[0]) reset to prevent WDT time-out reset system occurred happened + * | | |User can select a suitable setting of RSTDSEL for different application program WDT Reset Delay Period. + * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. + * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. + * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. + * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. + * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. + * | | |Note2: This register will be reset to 0 if WDT time-out reset system event occurred happened. + * @var WDT_T::RSTCNT + * Offset: 0x08 WDT Reset Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RSTCNT |WDT Reset Counter Register + * | | |Writing 0x00005AA5 to this register field will reset the internal 18-bit WDT up counter value to 0. + * | | |Note: This WDT_RSTCNT is not write protected, but this RSTCNT (WDT_CTL[0]) is write protected. + * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. + */ + __IO uint32_t CTL; /*!< [0x0000] WDT Control Register */ + __IO uint32_t ALTCTL; /*!< [0x0004] WDT Alternative Control Register */ + __O uint32_t RSTCNT; /*!< [0x0008] WDT Reset Counter Register */ + +} WDT_T; + +/** + @addtogroup WDT_CONST WDT Bit Field Definition + Constant Definitions for WDT Controller + @{ +*/ + +#define WDT_CTL_RSTEN_Pos (1) /*!< WDT_T::CTL: RSTEN Position */ +#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT_T::CTL: RSTEN Mask */ + +#define WDT_CTL_RSTF_Pos (2) /*!< WDT_T::CTL: RSTF Position */ +#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT_T::CTL: RSTF Mask */ + +#define WDT_CTL_IF_Pos (3) /*!< WDT_T::CTL: IF Position */ +#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT_T::CTL: IF Mask */ + +#define WDT_CTL_WKEN_Pos (4) /*!< WDT_T::CTL: WKEN Position */ +#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT_T::CTL: WKEN Mask */ + +#define WDT_CTL_WKF_Pos (5) /*!< WDT_T::CTL: WKF Position */ +#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT_T::CTL: WKF Mask */ + +#define WDT_CTL_INTEN_Pos (6) /*!< WDT_T::CTL: INTEN Position */ +#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT_T::CTL: INTEN Mask */ + +#define WDT_CTL_WDTEN_Pos (7) /*!< WDT_T::CTL: WDTEN Position */ +#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT_T::CTL: WDTEN Mask */ + +#define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT_T::CTL: TOUTSEL Position */ +#define WDT_CTL_TOUTSEL_Msk (0xful << WDT_CTL_TOUTSEL_Pos) /*!< WDT_T::CTL: TOUTSEL Mask */ + +#define WDT_CTL_SYNC_Pos (30) /*!< WDT_T::CTL: SYNC Position */ +#define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) /*!< WDT_T::CTL: SYNC Mask */ + +#define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT_T::CTL: ICEDEBUG Position */ +#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT_T::CTL: ICEDEBUG Mask */ + +#define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT_T::ALTCTL: RSTDSEL Position */ +#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT_T::ALTCTL: RSTDSEL Mask */ + +#define WDT_RSTCNT_RSTCNT_Pos (0) /*!< WDT_T::RSTCNT: RSTCNT Position */ +#define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) /*!< WDT_T::RSTCNT: RSTCNT Mask */ + + +/**@}*/ /* WDT_CONST */ +/**@}*/ /* end of WDT register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __WDT_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/wwdt_reg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/wwdt_reg.h new file mode 100644 index 0000000000..b51df9714c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/Reg/wwdt_reg.h @@ -0,0 +1,148 @@ +/**************************************************************************//** + * @file wwdt_reg.h + * @version V1.00 + * @brief WWDT register definition header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_REG_H__ +#define __WWDT_REG_H__ + +/** @addtogroup REGISTER Control Register + + @{ + +*/ + + +/*---------------------- Window Watchdog Timer -------------------------*/ +/** + @addtogroup WWDT Window Watchdog Timer(WWDT) + Memory Mapped Structure for WWDT Controller + @{ +*/ + +typedef struct +{ + + + /** + * @var WWDT_T::RLDCNT + * Offset: 0x00 WWDT Reload Counter Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[31:0] |RLDCNT |WWDT Reload Counter Register + * | | |Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F. + * | | |Note1: User can only write execute WWDT_RLDCNT register to the reload WWDT counter value command when current current WWDT counter value CNTDAT (WWDT_CNT[5:0]) is between 10 and CMPDAT (WWDT_CTL[21:16]) + * | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current current CNTDATWWDT counter value is larger than CMPDAT, WWDT reset signal system event will be generated immediately. + * | | |Note2: Execute WWDT counter reload always needs (WWDT_CLK *3) period to reload CNTDAT to 0x3F and internal prescale counter will be reset also. + * @var WWDT_T::CTL + * Offset: 0x04 WWDT Control Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTEN |WWDT Enable Control Bit + * | | |Set this bit to enable start WWDT counter counting. + * | | |0 = WWDT counter is stopped. + * | | |1 = WWDT counter is starting counting. + * |[1] |INTEN |WWDT Interrupt Enable Control Bit + * | | |If this bit is enabled, when WWDTIF (WWDT_STATUS[0]) is set to 1, the WWDT counter compare match interrupt signal is generated and inform to CPU. + * | | |0 = WWDT counter compare match interrupt Disabled. + * | | |1 = WWDT counter compare match interrupt Enabled. + * |[11:8] |PSCSEL |WWDT Counter Prescale Period Selection + * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * WWDT_CLK. + * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * WWDT_CLK. + * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * WWDT_CLK. + * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * WWDT_CLK. + * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * WWDT_CLK. + * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * WWDT_CLK. + * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * WWDT_CLK. + * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * WWDT_CLK. + * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * WWDT_CLK. + * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * WWDT_CLK. + * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * WWDT_CLK. + * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * WWDT_CLK. + * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * WWDT_CLK. + * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * WWDT_CLK. + * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * WWDT_CLK. + * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * WWDT_CLK. + * |[21:16] |CMPDAT |WWDT Window Compare Register Value + * | | |Set this register field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated.. + * | | |Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT CNTDAT (WWDT_CNT[5:]) is counter value between 10 and CMPDAT + * | | |If user writes 0x00005AA5 in WWDT_RLDCNT register when current WWDT counter value CNTDAT is larger than CMPDAT, WWDT reset system event signal will be generated immediately. + * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control + * | | |0 = ICE debug mode acknowledgment effects WWDT counter counting. + * | | |WWDT down counter will be held while CPU is held by ICE. + * | | |1 = ICE debug mode acknowledgment Disabled. + * | | |WWDT down counter will keep going counting no matter CPU is held by ICE or not. + * @var WWDT_T::STATUS + * Offset: 0x08 WWDT Status Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag + * | | |This bit indicates the that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16])interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]). + * | | |0 = No effect. + * | | |1 = WWDT WWDT CNTDAT counter value matches the CMPDAT. + * | | |Note: This bit is cleared by writing 1 to it. + * |[1] |WWDTRF |WWDT Timer-out Reset System Flag + * | | |If this bit is set to 1, it This bit indicates the that system has been reset by WWDT counter time-out reset system event.or not. + * | | |0 = WWDT time-out reset system event did not occur. + * | | |1 = WWDT time-out reset system event occurred. + * | | |Note: This bit is cleared by writing 1 to it. + * @var WWDT_T::CNT + * Offset: 0x0C WWDT Counter Value Register + * --------------------------------------------------------------------------------------------------- + * |Bits |Field |Descriptions + * | :----: | :----: | :---- | + * |[5:0] |CNTDAT |WWDT Counter Value + * | | |CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value. + */ + __O uint32_t RLDCNT; /*!< [0x0000] WWDT Reload Counter Register */ + __IO uint32_t CTL; /*!< [0x0004] WWDT Control Register */ + __IO uint32_t STATUS; /*!< [0x0008] WWDT Status Register */ + __I uint32_t CNT; /*!< [0x000c] WWDT Counter Value Register */ + +} WWDT_T; + + +/** + @addtogroup WWDT_CONST WWDT Bit Field Definition + Constant Definitions for WWDT Controller + @{ +*/ + +#define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT_T::RLDCNT: RLDCNT Position */ +#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT_T::RLDCNT: RLDCNT Mask */ + +#define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT_T::CTL: WWDTEN Position */ +#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT_T::CTL: WWDTEN Mask */ + +#define WWDT_CTL_INTEN_Pos (1) /*!< WWDT_T::CTL: INTEN Position */ +#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT_T::CTL: INTEN Mask */ + +#define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT_T::CTL: PSCSEL Position */ +#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT_T::CTL: PSCSEL Mask */ + +#define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT_T::CTL: CMPDAT Position */ +#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT_T::CTL: CMPDAT Mask */ + +#define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT_T::CTL: ICEDEBUG Position */ +#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT_T::CTL: ICEDEBUG Mask */ + +#define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT_T::STATUS: WWDTIF Position */ +#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT_T::STATUS: WWDTIF Mask */ + +#define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT_T::STATUS: WWDTRF Position */ +#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT_T::STATUS: WWDTRF Mask */ + +#define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT_T::CNT: CNTDAT Position */ +#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT_T::CNT: CNTDAT Mask */ + +/**@}*/ /* WWDT_CONST */ +/**@}*/ /* end of WWDT register group */ +/**@}*/ /* end of REGISTER group */ + +#endif /* __WWDT_REG_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_acmp.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_acmp.h new file mode 100644 index 0000000000..28c764a29b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_acmp.h @@ -0,0 +1,384 @@ +/**************************************************************************//** + * @file acmp.h + * @version V3.00 + * @brief ACMP Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __ACMP_H__ +#define __ACMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_CTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_CTL_FILTSEL_OFF (0UL << 13) /*!< ACMP_CTL setting for filter function disabled. */ +#define ACMP_CTL_FILTSEL_1PCLK (1UL << 13) /*!< ACMP_CTL setting for 1 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_2PCLK (2UL << 13) /*!< ACMP_CTL setting for 2 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_4PCLK (3UL << 13) /*!< ACMP_CTL setting for 4 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_8PCLK (4UL << 13) /*!< ACMP_CTL setting for 8 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_16PCLK (5UL << 13) /*!< ACMP_CTL setting for 16 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_32PCLK (6UL << 13) /*!< ACMP_CTL setting for 32 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_64PCLK (7UL << 13) /*!< ACMP_CTL setting for 64 PCLK filter count. */ +#define ACMP_CTL_INTPOL_RF (0UL << 8) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. */ +#define ACMP_CTL_INTPOL_R (1UL << 8) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. */ +#define ACMP_CTL_INTPOL_F (2UL << 8) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. */ +#define ACMP_CTL_POSSEL_P0 (0UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. */ +#define ACMP_CTL_POSSEL_P1 (1UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. */ +#define ACMP_CTL_POSSEL_P2 (2UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. */ +#define ACMP_CTL_POSSEL_P3 (3UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. */ +#define ACMP_CTL_NEGSEL_PIN (0UL << 4) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. */ +#define ACMP_CTL_NEGSEL_CRV (1UL << 4) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. */ +#define ACMP_CTL_NEGSEL_VBG (2UL << 4) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. */ +#define ACMP_CTL_NEGSEL_DAC (3UL << 4) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. */ +#define ACMP_CTL_HYSTERESIS_30MV (3UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. */ +#define ACMP_CTL_HYSTERESIS_20MV (2UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. */ +#define ACMP_CTL_HYSTERESIS_10MV (1UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. */ +#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << 2) /*!< ACMP_CTL setting for disabling the hysteresis function. */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_VREF constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_VREF_CRVSSEL_VDDA (0UL << 6) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage */ +#define ACMP_VREF_CRVSSEL_INTVREF (1UL << 6) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage */ + + +/**@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function. + */ +#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to disable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function. + */ +#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to select ACMP negative input source + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Src is comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @return None + * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input. + */ +#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to enable hysteresis function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + */ +#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV) + +/** + * @brief This macro is used to disable hysteresis function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set HYSSEL of ACMP_CTL register to disable hysteresis function. + */ +#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk) + +/** + * @brief This macro is used to select hysteresis level + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * @return None + */ +#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel)) + +/** + * @brief This macro is used to enable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function. + * If wake-up function is enabled, the wake-up interrupt will be enabled as well. + */ +#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to disable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function. + */ +#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to enable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator. + */ +#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to disable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + */ +#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to get ACMP output value + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP output value + * @details This macro will return the ACMP output value. + */ +#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to get ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP interrupt occurred (1) or not (0) + * @details This macro will return the ACMP interrupt flag. + */ +#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to clear ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag. + */ +#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to clear ACMP wake-up interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag. + */ +#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to enable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function. + */ +#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function. + */ +#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to select ACMP positive input pin + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Pin Comparator positive pin selection. Including: + * - \ref ACMP_CTL_POSSEL_P0 + * - \ref ACMP_CTL_POSSEL_P1 + * - \ref ACMP_CTL_POSSEL_P2 + * - \ref ACMP_CTL_POSSEL_P3 + * @return None + * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin. + */ +#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin)) + +/** + * @brief This macro is used to enable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function. + */ +#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to disable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function. + */ +#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to set ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cnt is comparator filter count setting. + * - \ref ACMP_CTL_FILTSEL_OFF + * - \ref ACMP_CTL_FILTSEL_1PCLK + * - \ref ACMP_CTL_FILTSEL_2PCLK + * - \ref ACMP_CTL_FILTSEL_4PCLK + * - \ref ACMP_CTL_FILTSEL_8PCLK + * - \ref ACMP_CTL_FILTSEL_16PCLK + * - \ref ACMP_CTL_FILTSEL_32PCLK + * - \ref ACMP_CTL_FILTSEL_64PCLK + * @return None + * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]). + */ +#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt)) + +/** + * @brief This macro is used to select comparator reference voltage + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32Level The comparator reference voltage setting. + * The formula is: + * comparator reference voltage = CRV source voltage x (1/6 + u32Level/24) + * The range of u32Level is 0 ~ 15. + * @return None + * @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]). + */ +#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to select ACMP interrupt condition + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cond Comparator interrupt condition selection. Including: + * - \ref ACMP_CTL_INTPOL_RF + * - \ref ACMP_CTL_INTPOL_R + * - \ref ACMP_CTL_INTPOL_F + * @return None + * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge. + */ +#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond)) + +/** + * @brief This macro is used to enable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode. + * When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch + * block; when ACMP0/1_WLAT pin is at low level, the output of window latch block, + * WLATOUT, is frozen. + */ +#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to disable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode. + */ +#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to enable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode. + * When window compare mode is enabled, user can connect the specific analog voltage + * source to either the positive inputs of both comparators or the negative inputs of + * both comparators. The upper bound and lower bound of the designated range are + * determined by the voltages applied to the other inputs of both comparators. If the + * output of a comparator is low and the other comparator outputs high, which means two + * comparators implies the upper and lower bound. User can directly monitor a specific + * analog voltage source via ACMPWO (ACMP_STATUS[16]). + */ +#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk) + +/** + * @brief This macro is used to disable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode. + */ +#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk) + + + + +/* Function prototype declaration */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel); +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum); + + +/**@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ +/**@}*/ /* end of group ACMP_Driver */ +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ACMP_H__ */ + + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_bpwm.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_bpwm.h new file mode 100644 index 0000000000..b596e20536 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_bpwm.h @@ -0,0 +1,362 @@ +/**************************************************************************//** + * @file bpwm.h + * @version V1.00 + * @brief M2354 series BPWM driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BPWM_H__ +#define __BPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + +/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants + @{ +*/ +#define BPWM_CHANNEL_NUM (6UL) /*!< BPWM channel number */ +#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask \hideinitializer */ +#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask \hideinitializer */ +#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask \hideinitializer */ +#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask \hideinitializer */ +#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask \hideinitializer */ +#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_UP_COUNTER (0UL) /*!< Up counter type */ +#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type */ +#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) */ +#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing */ +#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low */ +#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high */ +#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_SSCTL_SSRC_PWM0 (0UL<SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief This macro enable BPWM counter synchronous start counting function. + * @param[in] bpwm The pointer of the specified BPWM module + * @return None + * @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * \hideinitializer + */ +#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \ + { \ + (bpwm)->MSKEN = (u32ChannelMask); \ + (bpwm)->MSK = (u32LevelMask); \ + } + +/** + * @brief This macro set the prescaler of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF + * @return None + * \hideinitializer + */ +#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler)) + +/** + * @brief This macro set the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * \hideinitializer + */ +#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR)) + +/** + * @brief This macro get the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the comparator of specified channel. + * \hideinitializer + */ +#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * @note BPWM counter will stop if period length set to 0 + * \hideinitializer + */ +#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR)) + +/** + * @brief This macro get the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * \hideinitializer + */ +#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD) + +/** + * @brief This macro set the BPWM aligned type + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @param[in] u32AlignedType BPWM aligned type, valid values are: + * - \ref BPWM_EDGE_ALIGNED + * - \ref BPWM_CENTER_ALIGNED + * @return None + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType)) + +/** + * @brief Clear counter of channel 0 + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to clear counter of channel 0 + * \hideinitializer + */ +#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * \hideinitializer + */ +#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) { \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ + } \ + } \ + }while(0) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define BPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); + +/**@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group BPWM_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BPWM_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_can.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_can.h new file mode 100644 index 0000000000..7edcd49c8a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_can.h @@ -0,0 +1,191 @@ +/**************************************************************************//** + * @file can.h + * @version V3.00 + * @brief CAN Driver Header File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __CAN_H__ +#define __CAN_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CAN Test Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_NORMAL_MODE 0U /*!< CAN select normal mode */ +#define CAN_BASIC_MODE 1U /*!< CAN select basic mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Message ID Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_STD_ID 0UL /*!< CAN select standard ID */ +#define CAN_EXT_ID 1UL /*!< CAN select extended ID */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Message Frame Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_REMOTE_FRAME 0 /*!< CAN frame select remote frame */ +#define CAN_DATA_FRAME 1 /*!< CAN frame select data frame */ + +/**@}*/ /* end of group CAN_EXPORTED_CONSTANTS */ + + +/** @addtogroup CAN_EXPORTED_STRUCTS CAN Exported Structs + @{ +*/ +/** + * @details CAN message structure + */ +typedef struct +{ + uint32_t IdType; /*!< ID type */ + uint32_t FrameType; /*!< Frame type */ + uint32_t Id; /*!< Message ID */ + uint8_t DLC; /*!< Data length */ + uint8_t Data[8]; /*!< Data */ + uint8_t padding[3]; /*!< Just for padding for memory alignment*/ +} STR_CANMSG_T; + +/** + * @details CAN mask message structure + */ +typedef struct +{ + uint8_t u8Xtd; /*!< Extended ID */ + uint8_t u8Dir; /*!< Direction */ + uint32_t u32Id; /*!< Message ID */ + uint8_t u8IdType; /*!< ID type*/ +} STR_CANMASK_T; + +/**@}*/ /* end of group CAN_EXPORTED_STRUCTS */ + +/** @cond HIDDEN_SYMBOLS */ +#define MSG(id) (id) +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions + @{ +*/ + +/** + * @brief Get interrupt status. + * + * @param[in] can The base address of can module. + * + * @return CAN module status register value. + * + * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]), + * EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]). + */ +#define CAN_GET_INT_STATUS(can) ((can)->STATUS) + +/** + * @brief Get specified interrupt pending status. + * + * @param[in] can The base address of can module. + * + * @return The source of the interrupt. + * + * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt + * with the highest priority, disregarding their chronological order. + */ +#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR) + +/** + * @brief Disable wake-up function. + * + * @param[in] can The base address of can module. + * + * @return None + * + * @details The macro is used to disable wake-up function. + */ +#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0) + +/** + * @brief Enable wake-up function. + * + * @param[in] can The base address of can module. + * + * @return None + * + * @details User can wake-up system when there is a falling edge in the CAN_Rx pin. + */ +#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk) + +/** + * @brief Get specified Message Object new data into bit value. + * + * @param[in] can The base address of can module. + * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31. + * + * @return Specified Message Object new data into bit value. + * + * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers + * or by the Message Handler after reception of a Data Frame or after a successful transmission. + */ +#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16))) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define CAN functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate); +void CAN_Close(CAN_T *tCAN); +uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode); +void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum); +void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask); +void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask); +int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID); +int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID); +int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask); +int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum); +void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask); +void CAN_LeaveInitMode(CAN_T *tCAN); +void CAN_WaitMsg(CAN_T *tCAN); +uint32_t CAN_GetCANBitRate(CAN_T *tCAN); +void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask); +void CAN_LeaveTestMode(CAN_T *tCAN); +uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj); +int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg); +int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg); +int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast); +int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast); +int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg); + + +/**@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CAN_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CAN_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_clk.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_clk.h new file mode 100644 index 0000000000..b0a685ba9d --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_clk.h @@ -0,0 +1,1074 @@ +/**************************************************************************//** + * @file clk.h + * @version V3.0 + * @brief Clock Controller (CLK) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __CLK_H__ +#define __CLK_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants + @{ +*/ + + +#define FREQ_2MHZ 2000000UL +#define FREQ_4MHZ 4000000UL +#define FREQ_8MHZ 8000000UL +#define FREQ_12MHZ 12000000UL +#define FREQ_24MHZ 24000000UL +#define FREQ_25MHZ 25000000UL +#define FREQ_48MHZ 48000000UL +#define FREQ_50MHZ 50000000UL +#define FREQ_64MHZ 64000000UL +#define FREQ_75MHZ 75000000UL +#define FREQ_84MHZ 84000000UL +#define FREQ_96MHZ 96000000UL +#define FREQ_144MHZ 144000000UL +#define FREQ_200MHZ 200000000UL + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL0 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<>30) & 0x3UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */ +#define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */ +#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL) /*!< Calculate CLKSEL mask offset on MODULE index */ +#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index */ +#define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x4:CLKDIV4 */ +#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL) /*!< Calculate CLKDIV mask offset on MODULE index */ +#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index */ +#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index */ +#define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index */ +#define NA MODULE_NoMsk /*!< Not Available */ + +#define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */ +#define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */ +#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25) /*!< CLKSEL mask offset on MODULE index */ +#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20) /*!< CLKSEL position offset on MODULE index */ +#define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1, 0x4:CLKDIV4 */ +#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10) /*!< CLKDIV mask offset on MODULE index */ +#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index */ +#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index */ + + +/* AHBCLK */ +#define PDMA0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_PDMA0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */ + +#define PDMA1_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_PDMA1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */ + +#define ISP_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_ISPCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module */ + +#define EBI_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_EBICKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EBI Module */ + +#define EXST_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_EXSTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EXST Module */ + +#define SDH0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SDH0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(24UL))/*!< SDH0 Module */ + +#define CRC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */ + +#define CRPT_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRPTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRPT Module */ + +#define KS_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_KSCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< KS Module */ + +#define TRACE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_TRACECKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TRACE Module */ + +#define FMCIDLE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_FMCIDLE_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< FMCIDLE Module */ + +#define USBH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_USBHCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< USBH Module */ + +#define SRAM0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SRAM0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SRAM0 Module */ + +#define SRAM1_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SRAM1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SRAM1 Module */ + +#define SRAM2_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SRAM2CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SRAM2 Module */ + +#define GPA_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPACKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPA Module */ + +#define GPB_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPBCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPB Module */ + +#define GPC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPC Module */ + +#define GPD_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPDCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPD Module */ + +#define GPE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPECKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPE Module */ + +#define GPF_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPFCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPF Module */ + +#define GPG_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPGCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPG Module */ + +#define GPH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_GPHCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPH Module */ + +/* APBCLK0 */ +#define WDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< WDT Module */ + +#define WWDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WWDT Module */ + +#define RTC_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_RTCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module */ + +#define TMR0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR0 Module */ + +#define TMR1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR1 Module */ + +#define TMR2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR2 Module */ + +#define TMR3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR3CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR3 Module */ + +#define TMR4_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TMR4CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(8UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR4 Module */ + +#define TMR5_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TMR5CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR5 Module */ + +#define CLKO_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CLKOCKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< CLKO Module */ + +#define ACMP01_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_ACMP01CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP01 Module */ + +#define I2C0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module */ + +#define I2C1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module */ + +#define I2C2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C2 Module */ + +#define QSPI0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_QSPI0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< QSPI0 Module */ + +#define SPI0_MODULE (MODULE_APBCLK_ENC(1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI0CKEN_Pos) |\ + MODULE_CLKSEL_ENC(2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI0 Module */ + +#define SPI1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 6UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI1 Module */ + +#define SPI2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(10UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI2 Module */ + +#define UART0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART0 Module */ + +#define UART1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART1 Module */ + +#define UART2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART2CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< UART2 Module */ + +#define UART3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART3CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< UART3 Module */ + +#define UART4_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART4CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART4 Module */ + +#define UART5_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART5CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART5 Module */ + +#define TAMPER_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TAMPERCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC( NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TAMPER Module */ + +#define CAN0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CAN0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CAN0 Module */ + +#define OTG_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_OTGCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< OTG Module */ + +#define USBD_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_USBDCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(4UL)) /*!< USBD Module */ + +#define EADC_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EADCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC( NA)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< EADC Module */ + +#define I2S0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2S0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< I2S0 Module */ + +#define EWDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EWDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< EWDT Module */ + +#define EWWDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EWDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 6UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EWWDT Module */ + + +/* APBCLK1 */ +#define SC0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\ + MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< SC0 Module */ + +#define SC1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\ + MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< SC1 Module */ + +#define SC2_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\ + MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< SC2 Module */ + +#define SPI3_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SPI3CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI3 Module */ + +#define USCI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI0 Module */ + +#define USCI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI1 Module */ + +#define DAC_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_DACCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< DAC Module */ + +#define EPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM0 Module */ + +#define EPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM1 Module */ + +#define BPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM0 Module */ + +#define BPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM1 Module */ + +#define QEI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QEI0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QEI0 Module */ + +#define QEI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QEI1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QEI1 Module */ + +#define LCD_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_LCDCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(1UL)|MODULE_CLKSEL_Pos_ENC(2UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< LCD Module */ + +#define LCDCP_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_LCDCPCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(1UL)|MODULE_CLKSEL_Pos_ENC(3UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< LCDCP Module */ + +#define TRNG_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TRNGCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TRNG Module */ + +#define ECAP0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP0 Module */ + +#define ECAP1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP1 Module */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* PDMSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Power-down mode */ +#define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Low leakage Power-down mode */ +#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Fast Wake-up Power-down mode */ +#define CLK_PMUCTL_PDMSEL_ULLPD (0x3UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Ultra Low leakage Power-down mode */ +#define CLK_PMUCTL_PDMSEL_SPD (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Standby Power-down mode */ +#define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Deep Power-down mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WKTMRIS constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_WKTMRIS_410 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 410 LIRC clocks (12.8 ms) */ +#define CLK_PMUCTL_WKTMRIS_819 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 819 LIRC clocks (25.6 ms) */ +#define CLK_PMUCTL_WKTMRIS_1638 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1638 LIRC clocks (51.2 ms) */ +#define CLK_PMUCTL_WKTMRIS_3277 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 3277 LIRC clocks (102.4ms) */ +#define CLK_PMUCTL_WKTMRIS_13107 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 13107 LIRC clocks (409.6ms) */ +#define CLK_PMUCTL_WKTMRIS_26214 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 26214 LIRC clocks (819.2ms) */ +#define CLK_PMUCTL_WKTMRIS_52429 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 52429 LIRC clocks (1638.4ms) */ +#define CLK_PMUCTL_WKTMRIS_209715 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 209715 LIRC clocks (6553.6ms) */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SWKDBCLKSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin (GPC.0) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin (GPC.0) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin (GPC.0) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin (GPC.0) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN0_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN0_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN0_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN0_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin0 (GPC.0) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN1_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN1_RISING (0x1UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN1_FALLING (0x2UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN1_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN2_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN2_RISING (0x1UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN2_FALLING (0x2UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN2_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN3_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN3_RISING (0x1UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN3_FALLING (0x2UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN3_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) both edge at Deep Power-down mode \hideinitializer */ + +#define CLK_DPDWKPIN4_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN4_RISING (0x1UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) rising edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN4_FALLING (0x2UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) falling edge at Deep Power-down mode \hideinitializer */ +#define CLK_DPDWKPIN4_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) both edge at Deep Power-down mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up */ +#define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge */ +#define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge */ +#define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function */ +#define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function */ + + +/**@}*/ /* end of group CLK_EXPORTED_CONSTANTS */ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + +/** + * @brief Disable Wake-up Timer + * @param None + * @return None + * @details This macro disables Wake-up timer at Standby or Deep Power-down mode. + */ +#define CLK_DISABLE_WKTMR() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk; \ + }while(0) + +/** + * @brief Enable Wake-up Timer + * @param None + * @return None + * @details This macro enables Wake-up timer at Standby or Deep Power-down mode. + */ +#define CLK_ENABLE_WKTMR() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk; \ + }while(0) + +/** + * @brief Disable DPD Mode Wake-up Pin + * @param None + * @return None + * @details This macro disables Wake-up pin at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk; \ + }while(0) + +/** + * @brief Disable DPD Mode Wake-up Pin 0 + * @param None + * @return None + * @details This macro disables Wake-up pin 0 (GPC.0) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN0() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN0EN_Msk; \ + }while(0) + +/** + * @brief Disable DPD Mode Wake-up Pin 1 + * @param None + * @return None + * @details This macro disables Wake-up pin 1 (GPB.0) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN1() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN1EN_Msk; \ + }while(0) + +/** + * @brief Disable DPD Mode Wake-up Pin 2 + * @param None + * @return None + * @details This macro disables Wake-up pin 2 (GPB.2) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN2() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN2EN_Msk; \ + }while(0) + +/** + * @brief Disable DPD Mode Wake-up Pin 3 + * @param None + * @return None + * @details This macro disables Wake-up pin 3 (GPB.12) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN3() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN3EN_Msk; \ + }while(0) + +/** + * @brief Disable DPD Mode Wake-up Pin 4 + * @param None + * @return None + * @details This macro disables Wake-up pin 4 (GPF.6) at Deep Power-down mode. + */ +#define CLK_DISABLE_DPDWKPIN4() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_WKPIN4EN_Msk; \ + }while(0) + +/** + * @brief Disable SPD Mode ACMP Wake-up + * @param None + * @return None + * @details This macro disables ACMP wake-up at Standby Power-down mode. + */ +#define CLK_DISABLE_SPDACMP() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk; \ + }while(0) + +/** + * @brief Enable SPD Mode ACMP Wake-up + * @param None + * @return None + * @details This macro enables ACMP wake-up at Standby Power-down mode. + */ +#define CLK_ENABLE_SPDACMP() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk; \ + }while(0) + +/** + * @brief Disable SPD and DPD Mode RTC Wake-up + * @param None + * @return None + * @details This macro disables RTC Wake-up at Standby or Deep Power-down mode. + */ +#define CLK_DISABLE_RTCWK() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk; \ + }while(0) + +/** + * @brief Enable SPD and DPD Mode RTC Wake-up + * @param None + * @return None + * @details This macro enables RTC Wake-up at Standby or Deep Power-down mode. + */ +#define CLK_ENABLE_RTCWK() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk; \ + }while(0) + +/** + * @brief Set Wake-up Timer Time-out Interval + * + * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be + * - \ref CLK_PMUCTL_WKTMRIS_410 + * - \ref CLK_PMUCTL_WKTMRIS_819 + * - \ref CLK_PMUCTL_WKTMRIS_1638 + * - \ref CLK_PMUCTL_WKTMRIS_3277 + * - \ref CLK_PMUCTL_WKTMRIS_13107 + * - \ref CLK_PMUCTL_WKTMRIS_26214 + * - \ref CLK_PMUCTL_WKTMRIS_52429 + * - \ref CLK_PMUCTL_WKTMRIS_209715 + * + * @return None + * + * @details This function set Wake-up Timer Time-out Interval. + * + * + */ +#define CLK_SET_WKTMR_INTERVAL(u32Interval) \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_WKTMRIS_Msk)) | (u32Interval); \ + }while(0) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256 + * + * @return None + * + * @details This function set Set De-bounce Sampling Cycle Time for Standby Power-down pin wake-up. + * + * + */ +#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel)) + +/** + * @brief Disable SPD Mode Tamper Wake-up + * @param None + * @return None + * @details This macro disables tamper Wake-up at Standby Power-down mode. + */ +#define CLK_DISABLE_SPDTAMPER() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL &= ~CLK_PMUCTL_TAMPERWK_Msk; \ + }while(0) + +/** + * @brief Enable SPD and DPD Mode RTC Wake-up + * @param None + * @return None + * @details This macro enables tamper Wake-up at Standby Power-down mode. + */ +#define CLK_ENABLE_SPDTAMPER() \ + do{ \ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); \ + CLK->PMUCTL |= CLK_PMUCTL_TAMPERWK_Msk; \ + }while(0) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us); +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us); + + +/** + * @brief This function execute delay function. + * @param[in] us Delay time. The Max value is (2^24-1) / CPU Clock(MHz). Ex: + * 96MHz => 174762us, 84MHz => 199728us, + * 64MHz => 262143us, 48MHz => 349525us ... + * @return None + * @details Use the SysTick to generate the delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us) +{ + SysTick->LOAD = us * CyclesPerUs; + SysTick->VAL = (0x0UL); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL) + { + } + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; +} + +/** + * @brief This function execute long delay function. + * @param[in] us Delay time. + * @return None + * @details Use the SysTick to generate the long delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us) +{ + uint32_t u32Delay; + + /* It should <= 65536us for each delay loop */ + u32Delay = 65536UL; + + do + { + if(us > u32Delay) + { + us -= u32Delay; + } + else + { + u32Delay = us; + us = 0UL; + } + + SysTick->LOAD = u32Delay * CyclesPerUs; + SysTick->VAL = (0x0UL); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL); + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; + + } + while(us > 0UL); + +} + + +void CLK_DisableCKO(void); +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En); +void CLK_PowerDown(void); +void CLK_Idle(void); +uint32_t CLK_GetHXTFreq(void); +uint32_t CLK_GetLXTFreq(void); +uint32_t CLK_GetHCLKFreq(void); +uint32_t CLK_GetPCLK0Freq(void); +uint32_t CLK_GetPCLK1Freq(void); +uint32_t CLK_GetCPUFreq(void); +uint32_t CLK_SetCoreClock(uint32_t u32Hclk); +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc); +void CLK_EnableXtalRC(uint32_t u32ClkMask); +void CLK_DisableXtalRC(uint32_t u32ClkMask); +void CLK_EnableModuleClock(uint32_t u32ModuleIdx); +void CLK_DisableModuleClock(uint32_t u32ModuleIdx); +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq); +void CLK_DisablePLL(void); +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask); +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count); +void CLK_DisableSysTick(void); +void CLK_SetPowerDownMode(uint32_t u32PDMode); +void CLK_EnableDPDWKPin(uint32_t u32TriggerType); +uint32_t CLK_GetPMUWKSrc(void); +void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn); +uint32_t CLK_GetPLLClockFreq(void); +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx); +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx); + + +/**@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CLK_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + + +#endif /* __CLK_H__ */ + + + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_crc.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_crc.h new file mode 100644 index 0000000000..3628f936bd --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_crc.h @@ -0,0 +1,116 @@ +/**************************************************************************//** + * @file crc.h + * @version V3.00 + * @brief Cyclic Redundancy Check(CRC) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_H__ +#define __CRC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CRC Polynomial Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!SEED = (u32Seed); (crc)->CTL |= CRC_CTL_CHKSINIT_Msk; } while(0) + +/** + * @brief Get CRC Seed Value + * + * @param[in] crc The pointer of CRC module. + * + * @return CRC seed value + * + * @details This macro gets the current CRC seed value. + * \hideinitializer + */ +#define CRC_GET_SEED(crc) ((crc)->SEED) + +/** + * @brief CRC Write Data + * + * @param[in] crc The pointer of CRC module. + * @param[in] u32Data Write data + * + * @return None + * + * @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation. + * \hideinitializer + */ +#define CRC_WRITE_DATA(crc, u32Data) ((crc)->DAT = (u32Data)) + + +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen); +uint32_t CRC_GetChecksum(void); + +/**@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CRC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRC_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_crypto.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_crypto.h new file mode 100644 index 0000000000..50b139f1ed --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_crypto.h @@ -0,0 +1,559 @@ +/**************************************************************************//** + * @file crypto.h + * @version V3.00 + * @brief Cryptographic Accelerator driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __CRYPTO_H__ +#define __CRYPTO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants + @{ +*/ + + +#define PRNG_KEY_SIZE_128 ( 0UL) /*!< Select to generate 128-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_163 ( 1UL) /*!< Select to generate 163-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_192 ( 2UL) /*!< Select to generate 192-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_224 ( 3UL) /*!< Select to generate 224-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_255 ( 4UL) /*!< Select to generate 255-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_256 ( 6UL) /*!< Select to generate 256-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_283 ( 7UL) /*!< Select to generate 283-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_384 ( 8UL) /*!< Select to generate 384-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_409 ( 9UL) /*!< Select to generate 409-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_512 (10UL) /*!< Select to generate 512-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_521 (11UL) /*!< Select to generate 521-bit random key (Key Store Only) \hideinitializer */ +#define PRNG_KEY_SIZE_571 (12UL) /*!< Select to generate 571-bit random key (Key Store Only) \hideinitializer */ + +#define PRNG_SEED_CONT (0UL) /*!< PRNG using current seed \hideinitializer */ +#define PRNG_SEED_RELOAD (1UL) /*!< PRNG reload new seed \hideinitializer */ + +#define AES_KEY_SIZE_128 (0UL) /*!< AES select 128-bit key length \hideinitializer */ +#define AES_KEY_SIZE_192 (1UL) /*!< AES select 192-bit key length \hideinitializer */ +#define AES_KEY_SIZE_256 (2UL) /*!< AES select 256-bit key length \hideinitializer */ + +#define AES_MODE_ECB (0UL) /*!< AES select ECB mode \hideinitializer */ +#define AES_MODE_CBC (1UL) /*!< AES select CBC mode \hideinitializer */ +#define AES_MODE_CFB (2UL) /*!< AES select CFB mode \hideinitializer */ +#define AES_MODE_OFB (3UL) /*!< AES select OFB mode \hideinitializer */ +#define AES_MODE_CTR (4UL) /*!< AES select CTR mode \hideinitializer */ +#define AES_MODE_CBC_CS1 (0x10UL) /*!< AES select CBC CS1 mode \hideinitializer */ +#define AES_MODE_CBC_CS2 (0x11UL) /*!< AES select CBC CS2 mode \hideinitializer */ +#define AES_MODE_CBC_CS3 (0x12UL) /*!< AES select CBC CS3 mode \hideinitializer */ +#define AES_MODE_GCM (0x20UL) +#define AES_MODE_GHASH (0x21UL) +#define AES_MODE_CCM (0x22UL) + +#define SM4_MODE_ECB (0x200UL) /*!< SM4 select ECB mode \hideinitializer */ +#define SM4_MODE_CBC (0x201UL) /*!< SM4 select CBC mode \hideinitializer */ +#define SM4_MODE_CFB (0x202UL) /*!< SM4 select CFB mode \hideinitializer */ +#define SM4_MODE_OFB (0x203UL) /*!< SM4 select OFB mode \hideinitializer */ +#define SM4_MODE_CTR (0x204UL) /*!< SM4 select CTR mode \hideinitializer */ +#define SM4_MODE_CBC_CS1 (0x210UL) /*!< SM4 select CBC CS1 mode \hideinitializer */ +#define SM4_MODE_CBC_CS2 (0x211UL) /*!< SM4 select CBC CS2 mode \hideinitializer */ +#define SM4_MODE_CBC_CS3 (0x212UL) /*!< SM4 select CBC CS3 mode \hideinitializer */ +#define SM4_MODE_GCM (0x220UL) +#define SM4_MODE_GHASH (0x221UL) +#define SM4_MODE_CCM (0x222UL) + + +#define AES_NO_SWAP (0UL) /*!< AES do not swap input and output data \hideinitializer */ +#define AES_OUT_SWAP (1UL) /*!< AES swap output data \hideinitializer */ +#define AES_IN_SWAP (2UL) /*!< AES swap input data \hideinitializer */ +#define AES_IN_OUT_SWAP (3UL) /*!< AES swap both input and output data \hideinitializer */ + +#define DES_MODE_ECB (0x000UL) /*!< DES select ECB mode \hideinitializer */ +#define DES_MODE_CBC (0x100UL) /*!< DES select CBC mode \hideinitializer */ +#define DES_MODE_CFB (0x200UL) /*!< DES select CFB mode \hideinitializer */ +#define DES_MODE_OFB (0x300UL) /*!< DES select OFB mode \hideinitializer */ +#define DES_MODE_CTR (0x400UL) /*!< DES select CTR mode \hideinitializer */ +#define TDES_MODE_ECB (0x004UL) /*!< TDES select ECB mode \hideinitializer */ +#define TDES_MODE_CBC (0x104UL) /*!< TDES select CBC mode \hideinitializer */ +#define TDES_MODE_CFB (0x204UL) /*!< TDES select CFB mode \hideinitializer */ +#define TDES_MODE_OFB (0x304UL) /*!< TDES select OFB mode \hideinitializer */ +#define TDES_MODE_CTR (0x404UL) /*!< TDES select CTR mode \hideinitializer */ + +#define TDES_NO_SWAP (0UL) /*!< TDES do not swap data \hideinitializer */ +#define TDES_WHL_SWAP (1UL) /*!< TDES swap high-low word \hideinitializer */ +#define TDES_OUT_SWAP (2UL) /*!< TDES swap output data \hideinitializer */ +#define TDES_OUT_WHL_SWAP (3UL) /*!< TDES swap output data and high-low word \hideinitializer */ +#define TDES_IN_SWAP (4UL) /*!< TDES swap input data \hideinitializer */ +#define TDES_IN_WHL_SWAP (5UL) /*!< TDES swap input data and high-low word \hideinitializer */ +#define TDES_IN_OUT_SWAP (6UL) /*!< TDES swap both input and output data \hideinitializer */ +#define TDES_IN_OUT_WHL_SWAP (7UL) /*!< TDES swap input, output and high-low word \hideinitializer */ + +#define SHA_MODE_SHA1 (0UL) /*!< SHA select SHA-1 160-bit \hideinitializer */ +#define SHA_MODE_SHA224 (5UL) /*!< SHA select SHA-224 224-bit \hideinitializer */ +#define SHA_MODE_SHA256 (4UL) /*!< SHA select SHA-256 256-bit \hideinitializer */ +#define SHA_MODE_SHA384 (7UL) /*!< SHA select SHA-384 384-bit \hideinitializer */ +#define SHA_MODE_SHA512 (6UL) /*!< SHA select SHA-512 512-bit \hideinitializer */ + +#define HMAC_MODE_SHA1 (8UL) /*!< HMAC select SHA-1 160-bit \hideinitializer */ +#define HMAC_MODE_SHA224 (13UL) /*!< HMAC select SHA-224 224-bit \hideinitializer */ +#define HMAC_MODE_SHA256 (12UL) /*!< HMAC select SHA-256 256-bit \hideinitializer */ +#define HMAC_MODE_SHA384 (15UL) /*!< HMAC select SHA-384 384-bit \hideinitializer */ +#define HMAC_MODE_SHA512 (14UL) /*!< HMAC select SHA-512 512-bit \hideinitializer */ + + +#define SHA_NO_SWAP (0UL) /*!< SHA do not swap input and output data \hideinitializer */ +#define SHA_OUT_SWAP (1UL) /*!< SHA swap output data \hideinitializer */ +#define SHA_IN_SWAP (2UL) /*!< SHA swap input data \hideinitializer */ +#define SHA_IN_OUT_SWAP (3UL) /*!< SHA swap both input and output data \hideinitializer */ + +#define CRYPTO_DMA_FIRST (0x4UL) /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_ONE_SHOT (0x5UL) /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */ +#define CRYPTO_DMA_CONTINUE (0x6UL) /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_LAST (0x7UL) /*!< Do last encrypt/decrypt in DMA cascade \hideinitializer */ + +//--------------------------------------------------- + +#define RSA_MAX_KLEN (4096) +#define RSA_KBUF_HLEN (RSA_MAX_KLEN/4 + 8) +#define RSA_KBUF_BLEN (RSA_MAX_KLEN + 32) + +#define RSA_KEY_SIZE_1024 (0UL) /*!< RSA select 1024-bit key length \hideinitializer */ +#define RSA_KEY_SIZE_2048 (1UL) /*!< RSA select 2048-bit key length \hideinitializer */ +#define RSA_KEY_SIZE_3072 (2UL) /*!< RSA select 3072-bit key length \hideinitializer */ +#define RSA_KEY_SIZE_4096 (3UL) /*!< RSA select 4096-bit key length \hideinitializer */ + +#define RSA_MODE_NORMAL (0x000UL) /*!< RSA select normal mode \hideinitializer */ +#define RSA_MODE_CRT (0x004UL) /*!< RSA select CRT mode \hideinitializer */ +#define RSA_MODE_CRTBYPASS (0x00CUL) /*!< RSA select CRT bypass mode \hideinitializer */ +#define RSA_MODE_SCAP (0x100UL) /*!< RSA select SCAP mode \hideinitializer */ +#define RSA_MODE_CRT_SCAP (0x104UL) /*!< RSA select CRT SCAP mode \hideinitializer */ +#define RSA_MODE_CRTBYPASS_SCAP (0x10CUL) /*!< RSA select CRT bypass SCAP mode \hideinitializer */ + + +typedef enum +{ + /*!< ECC curve \hideinitializer */ + CURVE_P_192, /*!< ECC curve P-192 \hideinitializer */ + CURVE_P_224, /*!< ECC curve P-224 \hideinitializer */ + CURVE_P_256, /*!< ECC curve P-256 \hideinitializer */ + CURVE_P_384, /*!< ECC curve P-384 \hideinitializer */ + CURVE_P_521, /*!< ECC curve P-521 \hideinitializer */ + CURVE_K_163, /*!< ECC curve K-163 \hideinitializer */ + CURVE_K_233, /*!< ECC curve K-233 \hideinitializer */ + CURVE_K_283, /*!< ECC curve K-283 \hideinitializer */ + CURVE_K_409, /*!< ECC curve K-409 \hideinitializer */ + CURVE_K_571, /*!< ECC curve K-571 \hideinitializer */ + CURVE_B_163, /*!< ECC curve B-163 \hideinitializer */ + CURVE_B_233, /*!< ECC curve B-233 \hideinitializer */ + CURVE_B_283, /*!< ECC curve B-283 \hideinitializer */ + CURVE_B_409, /*!< ECC curve B-409 \hideinitializer */ + CURVE_B_571, /*!< ECC curve K-571 \hideinitializer */ + CURVE_KO_192, /*!< ECC 192-bits "Koblitz" curve \hideinitializer */ + CURVE_KO_224, /*!< ECC 224-bits "Koblitz" curve \hideinitializer */ + CURVE_KO_256, /*!< ECC 256-bits "Koblitz" curve \hideinitializer */ + CURVE_BP_256, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_BP_384, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_BP_512, /*!< ECC Brainpool 256-bits curve \hideinitializer */ + CURVE_25519, /*!< ECC curve-25519 \hideinitializer */ + CURVE_SM2_256, /*!< SM2 \hideinitializer */ + CURVE_UNDEF = -0x7fffffff, /*!< Invalid curve \hideinitializer */ +} +E_ECC_CURVE; + + + +typedef struct e_curve_t +{ + E_ECC_CURVE curve_id; + int32_t Echar; + char Ea[144]; + char Eb[144]; + char Px[144]; + char Py[144]; + int32_t Epl; + char Pp[176]; + int32_t Eol; + char Eorder[176]; + int32_t key_len; + int32_t irreducible_k1; + int32_t irreducible_k2; + int32_t irreducible_k3; + int32_t GF; +} ECC_CURVE; + + +/* RSA working buffer for normal mode */ +typedef struct +{ + uint32_t au32RsaOutput[128]; /* The RSA answer. */ + uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + uint32_t au32RsaM[128]; /* The base of exponentiation words. */ + uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */ +} RSA_BUF_NORMAL_T; + +/* RSA working buffer for CRT ( + CRT bypass) mode */ +typedef struct +{ + uint32_t au32RsaOutput[128]; /* The RSA answer. */ + uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + uint32_t au32RsaM[128]; /* The base of exponentiation words. */ + uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */ + uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */ + uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */ + uint32_t au32RsaTmpCp[128]; /* The Temporary Value(Cp) of RSA CRT. */ + uint32_t au32RsaTmpCq[128]; /* The Temporary Value(Cq) of RSA CRT. */ + uint32_t au32RsaTmpDp[128]; /* The Temporary Value(Dp) of RSA CRT. */ + uint32_t au32RsaTmpDq[128]; /* The Temporary Value(Dq) of RSA CRT. */ + uint32_t au32RsaTmpRp[128]; /* The Temporary Value(Rp) of RSA CRT. */ + uint32_t au32RsaTmpRq[128]; /* The Temporary Value(Rq) of RSA CRT. */ +} RSA_BUF_CRT_T; + +/* RSA working buffer for SCAP mode */ +typedef struct +{ + uint32_t au32RsaOutput[128]; /* The RSA answer. */ + uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + uint32_t au32RsaM[128]; /* The base of exponentiation words. */ + uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */ + uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */ + uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */ + uint32_t au32RsaTmpBlindKey[128]; /* The Temporary Value(blind key) of RSA SCAP. */ +} RSA_BUF_SCAP_T; + +/* RSA working buffer for CRT ( + CRT bypass ) + SCAP mode */ +typedef struct +{ + uint32_t au32RsaOutput[128]; /* The RSA answer. */ + uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + uint32_t au32RsaM[128]; /* The base of exponentiation words. */ + uint32_t au32RsaE[128]; /* The exponent of exponentiation words. */ + uint32_t au32RsaP[128]; /* The Factor of Modulus Operation. */ + uint32_t au32RsaQ[128]; /* The Factor of Modulus Operation. */ + uint32_t au32RsaTmpCp[128]; /* The Temporary Value(Cp) of RSA CRT. */ + uint32_t au32RsaTmpCq[128]; /* The Temporary Value(Cq) of RSA CRT. */ + uint32_t au32RsaTmpDp[128]; /* The Temporary Value(Dp) of RSA CRT. */ + uint32_t au32RsaTmpDq[128]; /* The Temporary Value(Dq) of RSA CRT. */ + uint32_t au32RsaTmpRp[128]; /* The Temporary Value(Rp) of RSA CRT. */ + uint32_t au32RsaTmpRq[128]; /* The Temporary Value(Rq) of RSA CRT. */ + uint32_t au32RsaTmpBlindKey[128]; /* The Temporary Value(blind key) of RSA SCAP. */ +} RSA_BUF_CRT_SCAP_T; + +/* RSA working buffer for using key store */ +typedef struct +{ + uint32_t au32RsaOutput[128]; /* The RSA answer. */ + uint32_t au32RsaN[128]; /* The base of modulus operation word. */ + uint32_t au32RsaM[128]; /* The base of exponentiation words. */ +} RSA_BUF_KS_T; + +/**@}*/ /* end of group CRYPTO_EXPORTED_CONSTANTS */ + + +/** @addtogroup CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros + @{ +*/ + +/*----------------------------------------------------------------------------------------------*/ +/* Macros */ +/*----------------------------------------------------------------------------------------------*/ + +/** + * @brief This macro enables PRNG interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define PRNG_ENABLE_INT(crpt) ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro disables PRNG interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define PRNG_DISABLE_INT(crpt) ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro gets PRNG interrupt flag. + * @param crpt Specified crypto module + * @return PRNG interrupt flag. + * \hideinitializer + */ +#define PRNG_GET_INT_FLAG(crpt) ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro clears PRNG interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define PRNG_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro enables AES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro disables AES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro gets AES interrupt flag. + * @param crpt Specified crypto module + * @return AES interrupt flag. + * \hideinitializer + */ +#define AES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro clears AES interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro enables AES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables AES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables TDES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro disables TDES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro gets TDES interrupt flag. + * @param crpt Specified crypto module + * @return TDES interrupt flag. + * \hideinitializer + */ +#define TDES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro clears TDES interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro enables TDES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables TDES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL = ((crpt)->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16UL<TDES_CTL &= ~CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables SHA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define SHA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro disables SHA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define SHA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro gets SHA interrupt flag. + * @param crpt Specified crypto module + * @return SHA interrupt flag. + * \hideinitializer + */ +#define SHA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro clears SHA interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define SHA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro enables ECC interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define ECC_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro disables ECC interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define ECC_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro gets ECC interrupt flag. + * @param crpt Specified crypto module + * @return ECC interrupt flag. + * \hideinitializer + */ +#define ECC_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + +/** + * @brief This macro clears ECC interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define ECC_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + +/** + * @brief This macro enables RSA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define RSA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_RSAIEN_Msk|CRPT_INTEN_RSAEIEN_Msk)) + +/** + * @brief This macro disables RSA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define RSA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_RSAIEN_Msk|CRPT_INTEN_RSAEIEN_Msk)) + +/** + * @brief This macro gets RSA interrupt flag. + * @param crpt Specified crypto module + * @return ECC interrupt flag. + * \hideinitializer + */ +#define RSA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_RSAIF_Msk|CRPT_INTSTS_RSAEIF_Msk)) + +/** + * @brief This macro clears RSA interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define RSA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_RSAIF_Msk|CRPT_INTSTS_RSAEIF_Msk)) + + +/**@}*/ /* end of group CRYPTO_EXPORTED_MACROS */ + + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed); +void PRNG_Start(CRPT_T *crpt); +void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]); +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType); +void AES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode); +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize); +void AES_SetKey_KS(CRPT_T *crpt, KS_MEM_Type mem, int32_t i32KeyIdx); +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]); +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); +void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len); +void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode); +void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt); +void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]); +void ECC_DriverISR(CRPT_T *crpt); +int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]); +int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]); +int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]); +int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S); +int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S); + + +int32_t RSA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32KeySize, void *psRSA_Buf, uint32_t u32BufSize, uint32_t u32UseKS); +int32_t RSA_SetKey(CRPT_T *crpt, char *Key); +int32_t RSA_SetDMATransfer(CRPT_T *crpt, char *Src, char *n, char *P, char *Q); +void RSA_Start(CRPT_T *crpt); +int32_t RSA_Read(CRPT_T *crpt, char * Output); +int32_t RSA_SetKey_KS(CRPT_T *crpt, uint32_t u32KeyNum, uint32_t u32KSMemType, uint32_t u32BlindKeyNum); +int32_t RSA_SetDMATransfer_KS(CRPT_T *crpt, char *Src, char *n, uint32_t u32PNum, + uint32_t u32QNum, uint32_t u32CpNum, uint32_t u32CqNum, uint32_t u32DpNum, + uint32_t u32DqNum, uint32_t u32RpNum, uint32_t u32RqNum); +int32_t ECC_GeneratePublicKey_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[], uint32_t u32ExtraOp); +int32_t ECC_GenerateSignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,KS_MEM_Type mem_d, int32_t i32KeyIdx_d,KS_MEM_Type mem_k, int32_t i32KeyIdx_k, char *R, char *S); +int32_t ECC_VerifySignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,KS_MEM_Type mem_pk1, int32_t i32KeyIdx_pk1,KS_MEM_Type mem_pk2, int32_t i32KeyIdx_pk2, char *R, char *S); +int32_t ECC_GenerateSecretZ_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve,KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[]); + +void CRPT_Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]); +void CRPT_Hex2Reg(char input[], uint32_t volatile reg[]); +int32_t ECC_GetCurve(CRPT_T *crpt, E_ECC_CURVE ecc_curve, ECC_CURVE *curve); + +/**@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CRYPTO_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRYPTO_H__ */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_dac.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_dac.h new file mode 100644 index 0000000000..7cfd030dd7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_dac.h @@ -0,0 +1,257 @@ +/****************************************************************************** + * @file dac.h + * @version V1.00 + * @brief M2354 series DAC driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __DAC_H__ +#define __DAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + + +/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DAC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<SWTRG = DAC_SWTRG_SWTRG_Msk) + +/** + * @brief Enable DAC data left-aligned. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion. + */ +#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable DAC data right-aligned. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion. + */ +#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable output voltage buffer. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and + * drive external loads directly without having to add an external operational amplifier. + */ +#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk) + +/** + * @brief Disable output voltage buffer. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable output voltage buffer. + */ +#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @return None + * @details This macro is used to enable DAC interrupt. + */ +#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk) + +/** + * @brief Disable the interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @return None + * @details This macro is used to disable DAC interrupt. + */ +#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk) + +/** + * @brief Enable DMA under-run interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to enable DMA under-run interrupt. + */ +#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Disable DMA under-run interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable DMA under-run interrupt. + */ +#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Enable PDMA mode. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set. + */ +#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk) + +/** + * @brief Disable PDMA mode. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable DMA mode. + */ +#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk) + +/** + * @brief Write data for conversion. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF. + * @return None + * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. + * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. + */ +#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data)) + +/** + * @brief Read DAC 12-bit holding data. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @return Return DAC 12-bit holding data. + * @details This macro is used to read DAC_DAT register. + */ +#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT) + +/** + * @brief Get the busy state of DAC. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state. + */ +#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos) + +/** + * @brief Get the interrupt flag. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @retval 0 DAC is in conversion state. + * @retval 1 DAC conversion finish. + * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag. + */ +#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk) + +/** + * @brief Get the DMA under-run flag. + * @param[in] dac The pointer of the specified DAC module. + * @retval 0 No DMA under-run error condition occurred. + * @retval 1 DMA under-run error condition occurred. + * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state. + */ +#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos) + +/** + * @brief This macro clear the interrupt status bit. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2355 Series DAC. + * @return None + * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag. + */ +#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk) + +/** + * @brief This macro clear the DMA under-run flag. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag. + */ +#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk) + + +/** + * @brief Enable DAC group mode + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @note Only DAC0 has this control bit. + * \hideinitializer + */ +#define DAC_ENABLE_GROUP_MODE(dac) ((dac)->CTL |= DAC_CTL_GRPEN_Msk) + +/** + * @brief Disable DAC group mode + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @note Only DAC0 has this control bit. + * \hideinitializer + */ +#define DAC_DISABLE_GROUP_MODE(dac) ((dac)->CTL &= ~DAC_CTL_GRPEN_Msk) + +void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc); +void DAC_Close(DAC_T *dac, uint32_t u32Ch); +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay); + +/**@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group DAC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_dpm.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_dpm.h new file mode 100644 index 0000000000..e8b4f7e0cb --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_dpm.h @@ -0,0 +1,132 @@ +/**************************************************************************//** + * @file dpm.h + * @version V3.00 + * @brief Debug Protection Mechanism (DPM) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __DPM_H__ +#define __DPM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DPM_Driver DPM Driver + @{ +*/ + +/** @addtogroup DPM_EXPORTED_CONSTANTS DPM Exported Constants + @{ +*/ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* DPM Control Register Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SECURE_DPM 0 /*!< Secure DPM module */ +#define NONSECURE_DPM 1 /*!< Non-secure DPM module */ + + +#define DPM_CTL_WVCODE (0x5AUL<STS & DPM_STS_BUSY_Msk); \ + DPM->CTL = (DPM->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE|DPM_CTL_INTEN_Msk); \ + }while(0) + +/** + * @brief Disable DPM Interrupt + * @param None + * @return None + * @details This macro disables DPM interrupt. + * This macro is for Secure DPM and Secure region only. + */ +#define DPM_DISABLE_INT() \ + do{ \ + while(DPM->STS & DPM_STS_BUSY_Msk); \ + DPM->CTL = (DPM->CTL & (~(DPM_CTL_WVCODE_Msk|DPM_CTL_INTEN_Msk))) | (DPM_CTL_WVCODE); \ + }while(0) + +/** + * @brief Enable Debugger to Access DPM Registers + * @param None + * @return None + * @details This macro enables debugger to access Secure and Non-secure DPM registers. + * This macro is for Secure DPM and Secure region only. + */ +#define DPM_ENABLE_DBG_ACCESS() \ + do{ \ + while(DPM->STS & DPM_STS_BUSY_Msk); \ + DPM->CTL = (DPM->CTL & (~(DPM_CTL_WVCODE_Msk|DPM_CTL_DACCDIS_Msk))) | (DPM_CTL_WVCODE); \ + }while(0) + +/** + * @brief Disable Debugger to Access DPM Registers + * @param None + * @return None + * @details This macro disables debugger to access Secure and Non-secure DPM registers. + * This macro is for Secure DPM and Secure region only. + */ +#define DPM_DISABLE_DBG_ACCESS() \ + do{ \ + while(DPM->STS & DPM_STS_BUSY_Msk); \ + DPM->CTL = (DPM->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE|DPM_CTL_DACCDIS_Msk); \ + }while(0) + + +void DPM_SetDebugDisable(uint32_t u32dpm); +void DPM_SetDebugLock(uint32_t u32dpm); +uint32_t DPM_GetDebugDisable(uint32_t u32dpm); +uint32_t DPM_GetDebugLock(uint32_t u32dpm); +uint32_t DPM_SetPasswordUpdate(uint32_t u32dpm, uint32_t au32Pwd[]); +uint32_t DPM_SetPasswordCompare(uint32_t u32dpm, uint32_t au32Pwd[]); +uint32_t DPM_GetPasswordErrorFlag(uint32_t u32dpm); +uint32_t DPM_GetIntFlag(void); +void DPM_ClearPasswordErrorFlag(uint32_t u32dpm); +void DPM_EnableDebuggerWriteAccess(uint32_t u32dpm); +void DPM_DisableDebuggerWriteAccess(uint32_t u32dpm); + + + +/**@}*/ /* end of group DPM_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group DPM_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DPM_H__ */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_eadc.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_eadc.h new file mode 100644 index 0000000000..9da0783a8b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_eadc.h @@ -0,0 +1,562 @@ +/****************************************************************************** + * @file eadc.h + * @version V0.10 + * @brief M2354 series EADC driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __EADC_H__ +#define __EADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EADC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EADC_CTL_DIFFEN_SINGLE_END (0UL<CTL |= EADC_CTL_ADCRST_Msk) + +/** + * @brief Enable Sample Module PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, + * user can enable this bit to generate a PDMA data transfer request. + * \hideinitializer + */ +#define EADC_ENABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL |= u32ModuleMask) + +/** + * @brief Disable Sample Module PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details This macro is used to disable sample module PDMA transfer. + * \hideinitializer + */ +#define EADC_DISABLE_SAMPLE_MODULE_PDMA(eadc, u32ModuleMask) ((eadc)->PDMACTL &= (~u32ModuleMask)) + +/** + * @brief Enable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details The ADC controller supports a double buffer mode in sample module 0~3. + * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable. + */ +#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk) + +/** + * @brief Disable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details Sample has one sample result register. + */ +#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk) + +/** + * @brief Set ADIFn at A/D end of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion. + */ +#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) + +/** + * @brief Set ADIFn at A/D start of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion. + */ +#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion. + * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3). + */ +#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Disable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details Specific sample module A/D ADINT0 interrupt function Disabled. + */ +#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Enable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + */ +#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) + +/** + * @brief Disable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + */ +#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= (uint32_t)(~(u32ModuleMask))) + +/** + * @brief Set the input mode output format. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Format Decides the output format. Valid values are: + * - \ref EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result. + * - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result. + * @return None + * @details The macro is used to set A/D input mode output format. + */ +#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) + +/** + * @brief Start the A/D conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18. + * @return None + * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion. + */ +#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) + +/** + * @brief Cancel the conversion for sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18. + * @return None + * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + */ +#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) + +/** + * @brief Get the conversion pending flag. + * @param[in] eadc The pointer of the specified EADC module. + * @return Return the conversion pending sample module. + * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end, + * the STPFn (n=0~18) bit is automatically cleared to 0. + */ +#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) + +/** + * @brief Get the conversion data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the conversion data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data. + */ +#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) + +/** + * @brief Get the data overrun flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. + * @return Return the data overrun flag of the user-specified sample module. + * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status. + */ +#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) + +/** + * @brief Get the data valid flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. + * @return Return the data valid flag of the user-specified sample module. + * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status. + */ +#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) + +/** + * @brief Get the double data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the double data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data. + */ +#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk) + +/** + * @brief Get the user-specified interrupt flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return Return the user-specified interrupt flags. + * @details This macro is used to get the user-specified interrupt flags. + */ +#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) + +/** + * @brief Get the user-specified sample module overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF. + * @return Return the user-specified sample module overrun flags. + * @details This macro is used to get the user-specified sample module overrun flags. + */ +#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) + +/** + * @brief Clear the selected interrupt status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return None + * @details This macro is used to clear clear the selected interrupt status bits. + */ +#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) + +/** + * @brief Clear the selected sample module overrun status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. + * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18. + * @return None + * @details This macro is used to clear the selected sample module overrun status bits. + */ +#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) + +/** + * @brief Check all sample module A/D result data register overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register overrun flag is set to 1. + * @retval 1 Any one of sample module data register overrun flag is set to 1. + * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + */ +#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) + +/** + * @brief Check all sample module A/D result data register valid flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register valid flag is set to 1. + * @retval 1 Any one of sample module data register valid flag is set to 1. + * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + */ +#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) + +/** + * @brief Check all A/D sample module start of conversion overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module event overrun flag is set to 1. + * @retval 1 Any one of sample module event overrun flag is set to 1. + * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + */ +#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) + +/** + * @brief Check all A/D interrupt flag overrun bits. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of ADINT interrupt flag is overwritten to 1. + * @retval 1 Any one of ADINT interrupt flag is overwritten to 1. + * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + */ +#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) + +/** + * @brief Get the busy state of EADC. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state. + */ +#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) + +/** + * @brief Configure the comparator 0 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP0(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 1 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP1(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 2 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP2(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 3 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP3(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Enable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. + */ +#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) + +/** + * @brief Disable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + */ +#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) + +/** + * @brief Enable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) + * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, + * if ADCMPIE is set to 1, a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details This macro is used to disable the compare interrupt. + */ +#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable comparator 0. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 0. + */ +#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0UL) + +/** + * @brief Disable comparator 1. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 1. + */ +#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0UL) + +/** + * @brief Disable comparator 2. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 2. + */ +#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0UL) + +/** + * @brief Disable comparator 3. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 3. + */ +#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0UL) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EADC functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode); +void EADC_Close(EADC_T *eadc); +void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel); +void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider); +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime); + +/**@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EADC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EADC_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_ebi.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_ebi.h new file mode 100644 index 0000000000..30c9144aaf --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_ebi.h @@ -0,0 +1,371 @@ +/**************************************************************************//** + * @file ebi.h + * @version V3.00 + * @brief External Bus Interface(EBI) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EBI_H__ +#define __EBI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + +/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address \hideinitializer */ +#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address \hideinitializer */ +#define EBI_BANK2_BASE_ADDR 0x60200000UL /*!< EBI bank2 base address \hideinitializer */ +#define EBI_BANK0_BASE_ADDR_NS 0x70000000UL /*!< EBI bank0 base address for Non-Secure \hideinitializer */ +#define EBI_BANK1_BASE_ADDR_NS 0x70100000UL /*!< EBI bank1 base address for Non-Secure \hideinitializer */ +#define EBI_BANK2_BASE_ADDR_NS 0x70200000UL /*!< EBI bank2 base address for Non-Secure \hideinitializer */ +#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI bank number */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */ +#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */ +#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI data bus width */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */ +#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI CS Active Level */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */ +#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI MCLK divider and Timing */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */ +#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */ +#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */ +#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */ +#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */ +#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */ +#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */ +#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */ + +#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */ +#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */ +#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */ +#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */ +#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */ +#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */ +#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */ + +#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */ +#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */ +#define EBI_OPMODE_ADSEPARATE (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode \hideinitializer */ + +/**@}*/ /* end of group EBI_EXPORTED_CONSTANTS */ + + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Read 8-bit data on EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA8(ebi, u32Addr) (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA8(ebi, u32Addr, u32Data) (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA16(ebi, u32Addr) (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA16(ebi, u32Addr, u32Data) (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA32(ebi, u32Addr) (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA32(ebi, u32Addr, u32Data) (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA8(ebi, u32Addr) (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA8(ebi, u32Addr, u32Data) (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA16(ebi, u32Addr) (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA16(ebi, u32Addr, u32Data) (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA32(ebi, u32Addr) (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA32(ebi, u32Addr, u32Data) (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA8(ebi, u32Addr) (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA8(ebi, u32Addr, u32Data) (*((volatile unsigned char *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank2. + */ +#define EBI2_READ_DATA16(ebi, u32Addr) (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA16(ebi, u32Addr, u32Data) (*((volatile unsigned short *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA32(ebi, u32Addr) (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr)))) +/** + * @brief Write 32-bit data to EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA32(ebi, u32Addr, u32Data) (*((volatile unsigned int *)((((ebi)==EBI_S)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Enable EBI Write Buffer + * + * @param[in] ebi The pointer of EBI module. + * + * @return None + * + * @details This macro is used to improve EBI write operation for all EBI banks. + * \hideinitializer + */ +#define EBI_ENABLE_WRITE_BUFFER(ebi) ((ebi)->CTL0 |= EBI_CTL_WBUFEN_Msk) + +/** + * @brief Disable EBI Write Buffer + * + * @param[in] ebi The pointer of EBI module. + * + * @return None + * + * @details This macro is used to disable EBI write buffer function. + * \hideinitializer + */ +#define EBI_DISABLE_WRITE_BUFFER(ebi) ((ebi)->CTL0 &= ~EBI_CTL_WBUFEN_Msk) + +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel); +void EBI_Close(uint32_t u32Bank); +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv); + +/**@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EBI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EBI_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_ecap.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_ecap.h new file mode 100644 index 0000000000..9ad071e7e6 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_ecap.h @@ -0,0 +1,461 @@ +/**************************************************************************//** + * @file ecap.h + * @version V3.00 + + * @brief EnHanced Input Capture Timer(ECAP) driver header file + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __ECAP_H__ +#define __ECAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants + @{ +*/ + +#define ECAP_IC0 (0UL) /*!< ECAP IC0 Unit \hideinitializer */ +#define ECAP_IC1 (1UL) /*!< ECAP IC1 Unit \hideinitializer */ +#define ECAP_IC2 (2UL) /*!< ECAP IC2 Unit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ECAP CTL0 constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ECAP_NOISE_FILTER_CLKDIV_1 (0UL<CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|(u32ClkSel)) + +/** + * @brief This macro is used to disable noise filter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the noise filter of input capture. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPNFDIS_Msk) + +/** + * @brief This macro is used to enable noise filter + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSel Select noise filter clock divide number + * - \ref ECAP_NOISE_FILTER_CLKDIV_1 + * - \ref ECAP_NOISE_FILTER_CLKDIV_2 + * - \ref ECAP_NOISE_FILTER_CLKDIV_4 + * - \ref ECAP_NOISE_FILTER_CLKDIV_16 + * - \ref ECAP_NOISE_FILTER_CLKDIV_32 + * - \ref ECAP_NOISE_FILTER_CLKDIV_64 + * @return None + * @details This macro will enable the noise filter of input capture and set noise filter clock divide. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_ENABLE(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPNFDIS_Msk|ECAP_CTL0_NFCLKSEL_Msk))|(u32ClkSel)) + +/** + * @brief This macro is used to enable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will enable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will disable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to select input channel source + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Src The input source + * - \ref ECAP_CAP_INPUT_SRC_FROM_IC + * - \ref ECAP_CAP_INPUT_SRC_FROM_CH + * @return None + * @details This macro will select the input source from ICx, CHx. + * \hideinitializer + */ +#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|(((u32Src)<CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return None + * @details This macro will disable the input channel_n interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to enable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to disable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to enable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to disable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to start capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will start capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to stop capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will stop capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to set event to clear capture counter + * @param[in] ecap Specify ECAP port + * @param[in] u32Event The input channel number + * - \ref ECAP_CTL0_CMPCLREN_Msk + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + + * @return None + * @details This macro will enable and select compare or capture event that can clear capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) do{ \ + if((u32Event) & ECAP_CTL0_CMPCLREN_Msk) \ + (ecap)->CTL0 |= ECAP_CTL0_CMPCLREN_Msk; \ + else \ + (ecap)->CTL0 &= ~ECAP_CTL0_CMPCLREN_Msk; \ + (ecap)->CTL1 = ((ecap)->CTL1 &(uint32_t)(~0xF00)) | ((u32Event) & 0xF00); \ + }while(0); + +/** + * @brief This macro is used to enable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the compare function. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to disable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the compare function. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to enable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to disable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to select input channel edge detection + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Edge The input source + * - \ref ECAP_RISING_EDGE + * - \ref ECAP_FALLING_EDGE + * - \ref ECAP_RISING_FALLING_EDGE + * @return None + * @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change. + * \hideinitializer + */ +#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<((u32Index)<<1))) + +/** + * @brief This macro is used to select ECAP counter reload trigger source + * @param[in] ecap Specify ECAP port + * @param[in] u32TrigSrc The input source + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + * @return None + * @details This macro will select capture counter reload trigger source. + * \hideinitializer + */ +#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~0xF00)|(u32TrigSrc)) + +/** + * @brief This macro is used to select capture timer clock divide. + * @param[in] ecap Specify ECAP port + * @param[in] u32Clkdiv The input source + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_1 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_4 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_16 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_32 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_64 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_96 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_112 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_128 + * @return None + * @details This macro will select capture timer clock has a pre-divider with eight divided option. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32Clkdiv)) + +/** + * @brief This macro is used to select capture timer/counter clock source + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSrc The input source + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2 + * @return None + * @details This macro will select capture timer/clock clock source. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CNTSRCSEL_Msk)|(u32ClkSrc)) + +/** + * @brief This macro is used to read input capture status + * @param[in] ecap Specify ECAP port + * @return Input capture status flags + * @details This macro will get the input capture interrupt status. + * \hideinitializer + */ +#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS) + +/** + * @brief This macro is used to get input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to get the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0) + +/** + * @brief This macro is used to clear input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to clear the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask)) + +/** + * @brief This macro is used to set input capture counter value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Counter value + * @return None + * @details This macro will set a counter value of input capture. + * \hideinitializer + */ +#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val)) + +/** + * @brief This macro is used to get input capture counter value + * @param[in] ecap Specify ECAP port + * @return Capture counter value + * @details This macro will get a counter value of input capture. + * \hideinitializer + */ +#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT) + +/** + * @brief This macro is used to get input capture counter hold value + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return Capture counter hold value + * @details This macro will get a hold value of input capture channel_n. + * \hideinitializer + */ +#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index))) + +/** + * @brief This macro is used to set input capture counter compare value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Input capture compare value + * @return None + * @details This macro will set a compare value of input capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val)) + +void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask); +void ECAP_Close(ECAP_T* ecap); +void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask); +void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask); +/**@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group ECAP_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__ECAP_H__*/ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_epwm.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_epwm.h new file mode 100644 index 0000000000..2749059a0b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_epwm.h @@ -0,0 +1,657 @@ +/**************************************************************************//** + * @file epwm.h + * @version V3.00 + * @brief M2354 series EPWM driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EPWM_H__ +#define __EPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + +/** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants + @{ +*/ +#define EPWM_CHANNEL_NUM (6UL) /*!< EPWM channel number */ +#define EPWM_CH_0_MASK (0x1UL) /*!< EPWM channel 0 mask \hideinitializer */ +#define EPWM_CH_1_MASK (0x2UL) /*!< EPWM channel 1 mask \hideinitializer */ +#define EPWM_CH_2_MASK (0x4UL) /*!< EPWM channel 2 mask \hideinitializer */ +#define EPWM_CH_3_MASK (0x8UL) /*!< EPWM channel 3 mask \hideinitializer */ +#define EPWM_CH_4_MASK (0x10UL) /*!< EPWM channel 4 mask \hideinitializer */ +#define EPWM_CH_5_MASK (0x20UL) /*!< EPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_UP_COUNTER (0UL) /*!< Up counter type */ +#define EPWM_DOWN_COUNTER (1UL) /*!< Down counter type */ +#define EPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_EDGE_ALIGNED (1UL) /*!< EPWM working in edge aligned type(down count) */ +#define EPWM_CENTER_ALIGNED (2UL) /*!< EPWM working in center aligned type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_OUTPUT_NOTHING (0UL) /*!< EPWM output nothing */ +#define EPWM_OUTPUT_LOW (1UL) /*!< EPWM output low */ +#define EPWM_OUTPUT_HIGH (2UL) /*!< EPWM output high */ +#define EPWM_OUTPUT_TOGGLE (3UL) /*!< EPWM output toggle */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_SSCTL_SSRC_EPWM0 (0UL<CTL1 = (epwm)->CTL1 | (0x7ul<CTL1 = (epwm)->CTL1 & ~(0x7ul<CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief This macro disable group mode + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to disable group mode of EPWM module. + * \hideinitializer + */ +#define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief Enable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32SyncSrc Synchronous start source selection, valid values are: + * - \ref EPWM_SSCTL_SSRC_EPWM0 + * - \ref EPWM_SSCTL_SSRC_EPWM1 + * - \ref EPWM_SSCTL_SSRC_BPWM0 + * - \ref EPWM_SSCTL_SSRC_BPWM1 + * @return None + * @details This macro is used to enable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask)) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \ + do{ \ + int i;\ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1UL << i)) \ + { \ + (epwm)->SSCTL &= ~(1UL << i); \ + } \ + } \ + }while(0) + +/** + * @brief This macro enable EPWM counter synchronous start counting function. + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to enable output inverter of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured rising data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured falling data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \ + do{ \ + (epwm)->MSKEN = (u32ChannelMask); \ + (epwm)->MSK = (u32LevelMask); \ + }while(0) + +/** + * @brief This macro set the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @return None + * @details This macro is used to set the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler)) + +/** + * @brief This macro get the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @details This macro is used to get the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U]) + +/** + * @brief This macro set the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR)) + +/** + * @brief This macro get the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the comparator of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the free trigger comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the free trigger comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR)) + +/** + * @brief This macro set the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the period of specified channel. + * @note This new setting will take effect on next EPWM period. + * @note EPWM counter will stop if period length set to 0. + * \hideinitializer + */ +#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR)) + +/** + * @brief This macro get the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the period of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the period of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)]) + +/** + * @brief This macro set the EPWM aligned type + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32AlignedType EPWM aligned type, valid values are: + * - \ref EPWM_EDGE_ALIGNED + * - \ref EPWM_CENTER_ALIGNED + * @return None + * @details This macro is used to set the EPWM aligned type of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) \ + { \ + (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \ + } \ + } \ + }while(0) + +/** + * @brief Set load window of window loading mode for specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to set load window of window loading mode for specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask)) + +/** + * @brief Trigger synchronous event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4 + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @return None + * @details This macro is used to trigger synchronous event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1U << ((u32ChannelNum) >> 1))) + +/** + * @brief Clear counter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to clear counter of specified channel(s). + * \hideinitializer + */ +#define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) { \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ + } \ + } \ + }while(0) + +/** + * @brief Trigger brake event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @param[in] u32BrakeType Type of brake trigger. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This macro is used to trigger brake event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) + +/** + * @brief Set Dead zone clock source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). + * @return None + * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. + * @note The write-protection function should be disabled before using this function. + * \hideinitializer + */ +#define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \ + (((epwm)->DTCTL[(u32ChannelNum) >> 1]) = ((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \ + ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos)) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, + uint32_t u32ChannelNum, + uint32_t u32Frequency, + uint32_t u32HighDutyCycle, + uint32_t u32Frequency2); +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt); +void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration); +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase); +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm); +void EPWM_EnableSyncPinInverse(EPWM_T *epwm); +void EPWM_DisableSyncPinInverse(EPWM_T *epwm); +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable); +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel); +void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle); +void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt); +void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum); + + +/**@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EPWM_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EPWM_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_ewdt.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_ewdt.h new file mode 100644 index 0000000000..7171225ba3 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_ewdt.h @@ -0,0 +1,219 @@ +/**************************************************************************//** + * @file ewdt.h + * @version V3.00 + * @brief Extra Watchdog Timer(EWDT) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EWDT_H__ +#define __EWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EWDT_Driver EWDT Driver + @{ +*/ + +/** @addtogroup EWDT_EXPORTED_CONSTANTS EWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* EWDT Time-out Interval Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EWDT_TIMEOUT_2POW4 (0UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^4 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW6 (1UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^6 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW8 (2UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^8 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW10 (3UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^10 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW12 (4UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^12 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW14 (5UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^14 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW16 (6UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^16 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW18 (7UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^18 * EWDT clocks \hideinitializer */ +#define EWDT_TIMEOUT_2POW20 (8UL << EWDT_CTL_TOUTSEL_Pos) /*!< Setting EWDT time-out interval to 2^20 * EWDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EWDT Reset Delay Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EWDT_RESET_DELAY_1026CLK (0UL << EWDT_ALTCTL_RSTDSEL_Pos) /*!< Setting EWDT reset delay period to 1026 * EWDT clocks \hideinitializer */ +#define EWDT_RESET_DELAY_130CLK (1UL << EWDT_ALTCTL_RSTDSEL_Pos) /*!< Setting EWDT reset delay period to 130 * EWDT clocks \hideinitializer */ +#define EWDT_RESET_DELAY_18CLK (2UL << EWDT_ALTCTL_RSTDSEL_Pos) /*!< Setting EWDT reset delay period to 18 * EWDT clocks \hideinitializer */ +#define EWDT_RESET_DELAY_3CLK (3UL << EWDT_ALTCTL_RSTDSEL_Pos) /*!< Setting EWDT reset delay period to 3 * EWDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EWDT Free Reset Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EWDT_RESET_COUNTER_KEYWORD (0x00005AA5UL) /*!< Fill this value to EWDT_RSTCNT register to free reset EWDT counter \hideinitializer */ + +/**@}*/ /* end of group EWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup EWDT_EXPORTED_FUNCTIONS EWDT Exported Functions + @{ +*/ + +/** + * @brief Clear EWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro clears EWDT time-out reset system flag. + * \hideinitializer + */ +#define EWDT_CLEAR_RESET_FLAG() (EWDT->CTL = (EWDT->CTL & ~(EWDT_CTL_IF_Msk | EWDT_CTL_WKF_Msk)) | EWDT_CTL_RSTF_Msk) + +/** + * @brief Clear EWDT Time-out Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro clears EWDT time-out interrupt flag. + * \hideinitializer + */ +#define EWDT_CLEAR_TIMEOUT_INT_FLAG() (EWDT->CTL = (EWDT->CTL & ~(EWDT_CTL_RSTF_Msk | EWDT_CTL_WKF_Msk)) | EWDT_CTL_IF_Msk) + +/** + * @brief Clear EWDT Wake-up Flag + * + * @param None + * + * @return None + * + * @details This macro clears EWDT time-out wake-up system flag. + * \hideinitializer + */ +#define EWDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (EWDT->CTL = (EWDT->CTL & ~(EWDT_CTL_RSTF_Msk | EWDT_CTL_IF_Msk)) | EWDT_CTL_WKF_Msk) + +/** + * @brief Get EWDT Time-out Reset Flag + * + * @param None + * + * @retval 0 EWDT time-out reset system did not occur + * @retval 1 EWDT time-out reset system occurred + * + * @details This macro indicates system has been reset by EWDT time-out reset or not. + * \hideinitializer + */ +#define EWDT_GET_RESET_FLAG() ((EWDT->CTL & EWDT_CTL_RSTF_Msk)? 1UL : 0UL) + +/** + * @brief Get EWDT Time-out Interrupt Flag + * + * @param None + * + * @retval 0 EWDT time-out interrupt did not occur + * @retval 1 EWDT time-out interrupt occurred + * + * @details This macro indicates EWDT time-out interrupt occurred or not. + * \hideinitializer + */ +#define EWDT_GET_TIMEOUT_INT_FLAG() ((EWDT->CTL & EWDT_CTL_IF_Msk)? 1UL : 0UL) + +/** + * @brief Get EWDT Time-out Wake-up Flag + * + * @param None + * + * @retval 0 EWDT time-out interrupt does not cause CPU wake-up + * @retval 1 EWDT time-out interrupt event cause CPU wake-up + * + * @details This macro indicates EWDT time-out interrupt event has waked up system or not. + * \hideinitializer + */ +#define EWDT_GET_TIMEOUT_WAKEUP_FLAG() ((EWDT->CTL & EWDT_CTL_WKF_Msk)? 1UL : 0UL) + +/** + * @brief Reset EWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reset the internal 20-bit EWDT up counter value. + * @note If EWDT is activated and time-out reset system function is enabled also, user should \n + * reset the 20-bit EWDT up counter value to avoid generate EWDT time-out reset signal to \n + * reset system before the EWDT time-out reset delay period expires. + * \hideinitializer + */ +#define EWDT_RESET_COUNTER() (EWDT->RSTCNT = EWDT_RESET_COUNTER_KEYWORD) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void EWDT_Close(void); +__STATIC_INLINE void EWDT_EnableInt(void); +__STATIC_INLINE void EWDT_DisableInt(void); + +/** + * @brief Stop EWDT Counting + * + * @param None + * + * @return None + * + * @details This function will stop EWDT counting and disable EWDT module. + */ +__STATIC_INLINE void EWDT_Close(void) +{ + EWDT->CTL = 0UL; + while((EWDT->CTL & EWDT_CTL_SYNC_Msk) == EWDT_CTL_SYNC_Msk) {} /* Wait disable WDTEN bit completed, it needs 2 * EWDT_CLK. */ +} + +/** + * @brief Enable EWDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable the EWDT time-out interrupt function. + */ +__STATIC_INLINE void EWDT_EnableInt(void) +{ + EWDT->CTL |= EWDT_CTL_INTEN_Msk; +} + +/** + * @brief Disable EWDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable the EWDT time-out interrupt function. + */ +__STATIC_INLINE void EWDT_DisableInt(void) +{ + /* Do not touch another write 1 clear bits */ + EWDT->CTL &= ~(EWDT_CTL_INTEN_Msk | EWDT_CTL_RSTF_Msk | EWDT_CTL_IF_Msk | EWDT_CTL_WKF_Msk); +} + +void EWDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup); + +/**@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group WDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EWDT_H__ */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_ewwdt.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_ewwdt.h new file mode 100644 index 0000000000..38c09d29ce --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_ewwdt.h @@ -0,0 +1,152 @@ +/**************************************************************************//** + * @file ewwdt.h + * @version V3.00 + * @brief Extra Window Watchdog Timer(EWWDT) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EWWDT_H__ +#define __EWWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EWWDT_Driver EWWDT Driver + @{ +*/ + +/** @addtogroup EWWDT_EXPORTED_CONSTANTS EWWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* EWWDT Prescale Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EWWDT_PRESCALER_1 (0 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_2 (1 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_4 (2 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_8 (3 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_16 (4 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_32 (5 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_64 (6 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_128 (7 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_192 (8 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_256 (9 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_384 (10 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_512 (11 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_768 (12 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_1024 (13 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_1536 (14 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*EWWDT_CLK) \hideinitializer */ +#define EWWDT_PRESCALER_2048 (15 << EWWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*EWWDT_CLK) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EWWDT Reload Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EWWDT_RELOAD_WORD (0x00005AA5UL) /*!< Fill this value to EWWDT_RLDCNT register to reload EWWDT counter \hideinitializer */ + +/**@}*/ /* end of group EWWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup EWWDT_EXPORTED_FUNCTIONS EWWDT Exported Functions + @{ +*/ + +/** + * @brief Clear EWWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear EWWDT time-out reset system flag. + * \hideinitializer + */ +#define EWWDT_CLEAR_RESET_FLAG() (EWWDT->STATUS = EWWDT_STATUS_WWDTRF_Msk) + +/** + * @brief Clear EWWDT Compared Match Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear EWWDT compared match interrupt flag. + * \hideinitializer + */ +#define EWWDT_CLEAR_INT_FLAG() (EWWDT->STATUS = EWWDT_STATUS_WWDTIF_Msk) + +/** + * @brief Get EWWDT Reset System Flag + * + * @param None + * + * @retval 0 EWWDT time-out reset system did not occur + * @retval 1 EWWDT time-out reset system occurred + * + * @details This macro is used to indicate system has been reset by EWWDT time-out reset or not. + * \hideinitializer + */ +#define EWWDT_GET_RESET_FLAG() ((EWWDT->STATUS & EWWDT_STATUS_WWDTRF_Msk)? 1 : 0) + +/** + * @brief Get EWWDT Compared Match Interrupt Flag + * + * @param None + * + * @retval 0 EWWDT compare match interrupt did not occur + * @retval 1 EWWDT compare match interrupt occurred + * + * @details This macro is used to indicate EWWDT counter value matches CMPDAT value or not. + * \hideinitializer + */ +#define EWWDT_GET_INT_FLAG() ((EWWDT->STATUS & EWWDT_STATUS_WWDTIF_Msk)? 1 : 0) + +/** + * @brief Get EWWDT Counter + * + * @param None + * + * @return EWWDT Counter Value + * + * @details This macro reflects the current EWWDT counter value. + * \hideinitializer + */ +#define EWWDT_GET_COUNTER() (EWWDT->CNT) + +/** + * @brief Reload EWWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reload the EWWDT counter value to 0x3F. + * @note User can only write EWWDT_RLDCNT register to reload EWWDT counter value when current EWWDT counter value \n + * between 0 and CMPDAT value. If user writes EWWDT_RLDCNT when current EWWDT counter value is larger than CMPDAT, \n + * EWWDT reset signal will generate immediately to reset system. + * \hideinitializer + */ +#define EWWDT_RELOAD_COUNTER() (EWWDT->RLDCNT = EWWDT_RELOAD_WORD) + +void EWWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt); + +/**@}*/ /* end of group EWWDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EWWDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EWWDT_H__ */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_fmc.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_fmc.h new file mode 100644 index 0000000000..aab7227d0b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_fmc.h @@ -0,0 +1,618 @@ +/**************************************************************************//** + * @file fmc.h + * @version V3.0 + * $Revision: 2 $ + * $Date: 19/11/27 3:11p $ + * @brief M2355 Series Flash Memory Controller(FMC) driver header file + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __FMC_H__ +#define __FMC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + +/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ISBEN 0UL +#define FMC_ISP ( (__PC() & 0x10000000) ? FMC_NS : FMC) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Base Address */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */ +#define FMC_APROM_END 0x00100000UL /*!< APROM end address */ +#define FMC_APROM_BANK0_END (FMC_APROM_END/2UL) /*!< APROM bank0 end address */ +#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */ +#define FMC_LDROM_END 0x00104000UL /*!< LDROM end address */ +#define FMC_DTFSH_BASE 0x00110000UL /*!< LDROM Base Address */ +#define FMC_DTFSH_END 0x00112000UL /*!< LDROM end address */ +#define FMC_XOM_BASE 0x00200000UL /*!< XOM Base Address */ +#define FMC_XOMR0_BASE 0x00200000UL /*!< XOMR 0 Base Address */ +#define FMC_XOMR1_BASE 0x00200010UL /*!< XOMR 1 Base Address */ +#define FMC_XOMR2_BASE 0x00200020UL /*!< XOMR 2 Base Address */ +#define FMC_XOMR3_BASE 0x00200030UL /*!< XOMR 3 Base Address */ +#define FMC_NSCBA_BASE 0x00210800UL /*!< Non-Secure base address */ +#define FMC_SCRLOCK_BASE 0x00610000UL /*!< Secure Region Lock base address */ +#define FMC_ARLOCK_BASE 0x00610008UL /*!< All Region Lock base address */ +#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */ +#define FMC_USER_CONFIG_0 0x00300000UL /*!< CONFIG 0 Address */ +#define FMC_USER_CONFIG_1 0x00300004UL /*!< CONFIG 1 Address */ +#define FMC_USER_CONFIG_2 0x00300008UL /*!< CONFIG 2 Address */ +#define FMC_USER_CONFIG_3 0x0030000CUL /*!< CONFIG 3 Address */ +#define FMC_OTP_BASE 0x00310000UL /*!< OTP flash base address */ + +#define FMC_FLASH_PAGE_SIZE 0x800UL /*!< Flash Page Size (2048 Bytes) */ +#define FMC_PAGE_ADDR_MASK 0xFFFFF800UL /*!< Flash page address mask */ +#define FMC_MULTI_WORD_PROG_LEN 512UL /*!< The maximum length of a multi-word program. */ + +#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size */ +#define FMC_BANK_SIZE (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size */ +#define FMC_LDROM_SIZE 0x4000UL /*!< LDROM Size (4 Kbytes) */ +#define FMC_OTP_ENTRY_CNT 256UL /*!< OTP entry number */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* XOM region number constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define XOMR0 0UL /*!< XOM region 0 */ +#define XOMR1 1UL /*!< XOM region 1 */ +#define XOMR2 2UL /*!< XOM region 2 */ +#define XOMR3 3UL /*!< XOM region 3 */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define IS_BOOT_FROM_LDROM 0x1UL /*!< ISPCTL setting to select to boot from LDROM */ +#define IS_BOOT_FROM_APROM 0x0UL /*!< ISPCTL setting to select to boot from APROM */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCMD constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read Flash */ +#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID */ +#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result */ +#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID */ +#define FMC_ISPCMD_READ_DID 0x0CUL /*!< ISP Command: Read Device ID */ +#define FMC_ISPCMD_READ_CKS 0x0DUL /*!< ISP Command: Read Checksum */ +#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: 32-bit Program Flash */ +#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash */ +#define FMC_ISPCMD_BANK_ERASE 0x23UL /*!< ISP Command: Erase Flash bank 0 or 1 */ +#define FMC_ISPCMD_PROGRAM_MUL 0x27UL /*!< ISP Command: Flash Multi-Word Program */ +#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification */ +#define FMC_ISPCMD_BANK_SWAP 0x2CUL /*!< ISP Command: Bank Swap */ +#define FMC_ISPCMD_RUN_CKS 0x2DUL /*!< ISP Command: Run Check Calculation */ +#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Set vector mapping */ +#define FMC_ISPCMD_READ_64 0x40UL /*!< ISP Command: 64-bit read Flash */ +#define FMC_ISPCMD_PROGRAM_64 0x61UL /*!< ISP Command: 64-bit program Flash */ + +#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. */ +#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. */ +#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. */ + +/**@}*/ /* end of group FMC_EXPORTED_CONSTANTS */ + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* FMC Macro Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Enable ISP Function + * + * @param None + * + * @return None + * + * @details This function will set ISPEN bit of ISPCTL control register to enable ISP function. + * + */ +#define FMC_ENABLE_ISP() (FMC_ISP->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP Function */ + +/** + * @brief Disable ISP Function + * + * @param None + * + * @return None + * + * @details This function will clear ISPEN bit of ISPCTL control register to disable ISP function. + * + */ +#define FMC_DISABLE_ISP() (FMC_ISP->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP Function */ + +/** + * @brief Disable Non Secure ISP Function + * + * @param None + * + * @return None + * + * @details This function will clear ISPEN bit of ISPCTL control register to disable Non Secure ISP function. + * + */ + +#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM Update Function */ + +/** + * @brief Disable LDROM Update Function + * + * @param None + * + * @return None + * + * @details This function will set ISPEN bit of ISPCTL control register to disable LDROM update function. + * + */ +#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM Update Function */ + +/** + * @brief Enable User Configuration Update Function + * + * @param None + * + * @return None + * + * @details This function will set CFGUEN bit of ISPCTL control register to enable User Configuration update function. + * User needs to set CFGUEN bit before they can update User Configuration area. + * + */ +#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable CONFIG Update Function */ + +/** + * @brief Disable User Configuration Update Function + * + * @param None + * + * @return None + * + * @details This function will clear CFGUEN bit of ISPCTL control register to disable User Configuration update function. + * + */ +#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable CONFIG Update Function */ + + +/** + * @brief Enable APROM Update Function + * + * @param None + * + * @return None + * + * @details This function will set APUEN bit of ISPCTL control register to enable APROM update function. + * User needs to set APUEN bit before they can update APROM in APROM boot mode. + * + */ +#define FMC_ENABLE_AP_UPDATE() (FMC_ISP->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM Update Function */ + +/** + * @brief Disable APROM Update Function + * + * @param None + * + * @return None + * + * @details This function will clear APUEN bit of ISPCTL control register to disable APROM update function. + * + */ +#define FMC_DISABLE_AP_UPDATE() (FMC_ISP->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM Update Function */ + +/** + * @brief Set Boot from APROM + * + * @param None + * + * @return None + * + * @details This function is select booting from APROM. + * + */ +#define FMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk) /*!< Select booting from APROM */ + +/** + * @brief Set Boot from LDROM + * + * @param None + * + * @return None + * + * @details This function is select booting from LDROM. + * + */ +#define FMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk) /*!< Select booting from LDROM */ + +/** + * @brief Get ISP Fail Flag + * + * @param None + * + * @return None + * + * @details This function is used to get ISP fail flag when do ISP actoin. + * + */ +#define FMC_GET_FAIL_FLAG() ((FMC_ISP->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag */ + +/** + * @brief Clear ISP Fail Flag + * + * @param None + * + * @return None + * + * @details This function is used to clear ISP fail flag when ISP fail flag set. + * + */ +#define FMC_CLR_FAIL_FLAG() (FMC_ISP->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag */ + +/** + * @brief Enable ISP Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable ISP action interrupt. + * + */ +#define FMC_ENABLE_ISP_INT() (FMC_ISP->ISPCTL |= FMC_ISPCTL_INTEN_Msk) /*!< Enable ISP interrupt */ + +/** + * @brief Disable ISP Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable ISP action interrupt. + * + */ +#define FMC_DISABLE_ISP_INT() (FMC_ISP->ISPCTL &= ~FMC_ISPCTL_INTEN_Msk) /*!< Disable ISP interrupt */ + +/** + * @brief Get ISP Interrupt Flag + * + * @param None + * + * @return None + * + * @details This function will get ISP action interrupt status + * + */ +#define FMC_GET_ISP_INT_FLAG() ((FMC_ISP->ISPSTS & FMC_ISPSTS_INTFLAG_Msk) ? 1UL : 0UL) /*!< Get ISP interrupt flag Status */ + +/** + * @brief Clear ISP Interrupt Flag + * + * @param None + * + * @return None + * + * @details This function will clear ISP interrupt flag + * + */ +#define FMC_CLEAR_ISP_INT_FLAG() (FMC_ISP->ISPSTS = FMC_ISPSTS_INTFLAG_Msk) /*!< Clear ISP interrupt flag*/ + +/** + * @brief Enable Data Flash Scrambling Function + * + * @param None + * + * @return None + * + * @details This function will set SCRAMEN bit of DFCTL control register to enable Data Flash Scrambling Function. + * + */ +#define FMC_ENABLE_SCRAMBLE() (FMC->DFCTL |= FMC_DFCTL_SCRAMEN_Msk) /*!< Enable Data Flash Scrambling Function */ + +/** + * @brief Disable Data Flash Scrambling Function + * + * @param None + * + * @return None + * + * @details This function will clear SCRAMEN bit of DFCTL control register to disable Data Flash Scrambling Function. + * + */ +#define FMC_DISABLE_SCRAMBLE() (FMC->DFCTL &= ~FMC_DFCTL_SCRAMEN_Msk) /*!< Disable Data Flash Scrambling Function */ + +/** + * @brief Enable Data Flash Silent Access Function + * + * @param None + * + * @return None + * + * @details This function will set SILENTEN bit of DFCTL control register to enable Data Flash Silent Access Function. + * + */ +#define FMC_ENABLE_SILENT() (FMC->DFCTL |= FMC_DFCTL_SILENTEN_Msk) /*!< Enable Data Flash Silent Access Function */ + +/** + * @brief Disable Data Flash Silent Access Function + * + * @param None + * + * @return None + * + * @details This function will clear SILENTEN bit of DFCTL control register to disable Data Flash Silent Access Function. + * + */ +#define FMC_DISABLE_SILENT() (FMC->DFCTL &= ~FMC_DFCTL_SILENTEN_Msk) /*!< Disable Data Flash Silent Access Function */ + +/** + * @brief Enable Data Flash Temper Attack Program Function + * + * @param None + * + * @return None + * + * @details This function will set TMPCLR bit of DFCTL control register to enable Data Flash Temper Attack Program Function. + * + */ +#define FMC_ENABLE_TMPCLR() (FMC->DFCTL |= FMC_DFCTL_TMPCLR_Msk) /*!< Enable Data Flash Temper Attack Program Function */ + +/** + * @brief Disable Data Flash Temper Attack Program Function + * + * @param None + * + * @return None + * + * @details This function will clear TMPCLR bit of DFCTL control register to disable Data Flash Temper Attack Program Function. + * + */ +#define FMC_DISABLE_TMPCLR() (FMC->DFCTL &= ~FMC_DFCTL_TMPCLR_Msk) /*!< Disable Data Flash Temper Attack Program Function */ + +/** + * @brief Get Data Flash Temper Attack Programming Done Flag + * + * @param None + * + * @return None + * + * @details This function will get Data Flash Temper Attack Programming Done flag + * + */ +#define FMC_GET_TMPCLRDONE_FLAG() ((FMC->DFSTS & FMC_DFSTS_TMPCLRDONE_Msk) ? 1UL : 0UL) /*!< Get Data Flash Temper Attack Programming Done Flag */ + +/** + * @brief Get Data Flash Temper Attack Programming Busy Flag + * + * @param None + * + * @return None + * + * @details This function will get Data Flash Temper Attack Programming Busy flag + * + */ +#define FMC_GET_TMPCLRBUSY_FLAG() ((FMC->DFSTS & FMC_DFSTS_TMPCLRBUSY_Msk) ? 1UL : 0UL) /*!< Get Data Flash Temper Attack Programming Busy Flag */ + +/** + * @brief Clear Data Flash Temper Attack Programming Done Flag + * + * @param None + * + * @return None + * + * @details This function will clear Data Flash Temper Attack Programming Done flag + * + */ +#define FMC_CLEAR_TMPCLRDONE_FLAG() (FMC->DFSTS |= FMC_DFSTS_TMPCLRDONE_Msk) /*!< Clear Data Flash Temper Attack Programming Done Flag */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +__STATIC_INLINE uint32_t FMC_ReadCID(void); +__STATIC_INLINE uint32_t FMC_ReadPID(void); +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index); +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index); +__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr); +__STATIC_INLINE uint32_t FMC_GetVECMAP(void); +__STATIC_INLINE void FMC_SetScrambleKey(uint32_t u32ScrambleKey); + +/** + * @brief Get current vector mapping address. + * + * @param None + * + * @return The current vector mapping address. + * + * @details To get VECMAP value which is the page address for remapping to vector page (0x0). + * + */ +__STATIC_INLINE uint32_t FMC_GetVECMAP(void) +{ + return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk); +} + +/** + * @brief Read company ID + * + * @param None + * + * @return The company ID (32-bit) + * + * @details The company ID of Nuvoton is fixed to be 0xDA + */ +__STATIC_INLINE uint32_t FMC_ReadCID(void) +{ + FMC_ISP->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */ + FMC_ISP->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */ + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC_ISP->ISPDAT; +} + +/** + * @brief Read product ID + * + * @param None + * + * @return The product ID (32-bit) + * + * @details This function is used to read product ID. + */ +__STATIC_INLINE uint32_t FMC_ReadPID(void) +{ + FMC_ISP->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */ + FMC_ISP->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */ + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC_ISP->ISPDAT; +} + + +/** + * @brief Read Unique ID + * + * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64] + * + * @return The 32-bit unique ID data of specified UID index. + * + * @details To read out 96-bit Unique ID. + */ +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index) +{ + FMC_ISP->ISPCMD = FMC_ISPCMD_READ_UID; + FMC_ISP->ISPADDR = ((uint32_t)u8Index << 2u); + FMC_ISP->ISPDAT = 0u; + FMC_ISP->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + while(FMC_ISP->ISPTRG) {} + + return FMC_ISP->ISPDAT; +} + +/** + * @brief To read UCID + * + * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3. + * + * @return The UCID of specified index + * + * @details This function is used to read unique chip ID (UCID). + */ +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index) +{ + FMC_ISP->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ + FMC_ISP->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */ + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC_ISP->ISPDAT; +} + + +/** + * @brief Set vector mapping address + * + * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment. + * + * @return To set VECMAP to remap specified page address to 0x0. + * + * @details This function is used to set VECMAP to map specified page to vector page (0x0). + */ +__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr) +{ + FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */ + FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */ + FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG) {} /* Waiting for ISP Done */ +} + +/** + * @brief Set Data Flash scrambling key + * + * @param[in] u32ScramKey The value of scrambling key. + * + * @return NULL + * + * @details This function is used to set Data Flash scrambling key. + */ +__STATIC_INLINE void FMC_SetScrambleKey(uint32_t u32ScrambleKey) +{ + FMC->SCRKEY = u32ScrambleKey; +} + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +extern uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count); +extern void FMC_Close(void); +extern int32_t FMC_ConfigXOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page); +extern int32_t FMC_Erase(uint32_t u32PageAddr); +extern int32_t FMC_EraseBank(uint32_t u32BankAddr); +extern int32_t FMC_EraseXOM(uint32_t xom_num); +extern int32_t FMC_GetBootSource(void); +extern uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count); +extern int32_t FMC_IsOTPLocked(uint32_t otp_num); +extern int32_t FMC_GetXOMState(uint32_t xom_num); +extern int32_t FMC_LockOTP(uint32_t otp_num); +extern void FMC_Open(void); +extern uint32_t FMC_Read(uint32_t u32Addr); +extern int32_t FMC_Read64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1); +extern int32_t FMC_ReadOTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word); +extern int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count); +extern void FMC_SetBootSource(int32_t i32BootSrc); +extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data); +extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1); +extern int32_t FMC_WriteConfig(uint32_t au32Config[], uint32_t u32Count); +extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len); +extern int32_t FMC_WriteOTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word); +extern int32_t FMC_WriteMultipleA(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len); +extern int32_t FMC_SwapBank(uint32_t u32Bank); + +/**@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group FMC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FMC_H__ */ + +/*** (C) COPYRIGHT 2019 Nuvoton Technology Corp. ***/ + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_fvc.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_fvc.h new file mode 100644 index 0000000000..caa6a3ca87 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_fvc.h @@ -0,0 +1,64 @@ +/**************************************************************************//** + * @file fvc.h + * @version V3.00 + * @brief Firmware Version Counter Driver Header + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __FVC_H__ +#define __FVC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FVC_Driver FVC Driver + @{ +*/ + +/** @addtogroup FVC_EXPORTED_CONSTANTS FVC Exported Constants + @{ +*/ + +#define FVC_VCODE (0x77100000ul) /*!< The key code for FVC_CTL write. */ +#define FVC_BL2 (FVC->BL2) /*!< Version number of BL2 Firmware */ +#define FVC_BL32 (FVC->BL32) /*!< Version number of BL32 Firmware */ +#define FVC_BL33 (FVC->BL33) /*!< Version number of BL33 Firmware */ +#define FVC_UDF (FVC->UDF) /*!< Version number of User Firmware */ + +/**@}*/ /* end of group FVC_EXPORTED_CONSTANTS */ + + +/** @addtogroup FVC_EXPORTED_FUNCTIONS FVC Exported Functions + @{ +*/ + +int32_t FVC_Open(void); +void FVC_EnableMonotone(void); +int32_t FVC_SetBL2Ver(uint32_t u32Ver); +int32_t FVC_SetBL32Ver(uint32_t u32Ver); +int32_t FVC_SetBL33Ver(uint32_t u32Ver); +int32_t FVC_SetUDFVer(uint32_t u32Ver); + + +/**@}*/ /* end of group FVC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group FVC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FVC_H__ */ + +/*** (C) COPYRIGHT 2019 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_gpio.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_gpio.h new file mode 100644 index 0000000000..2e1fbaa628 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_gpio.h @@ -0,0 +1,1158 @@ +/**************************************************************************//** + * @file gpio.h + * @version V3.0 + * @brief M2354 series General Purpose I/O (GPIO) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants + @{ +*/ + +#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_MODE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode */ +#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */ +#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */ +#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Interrupt Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */ +#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */ +#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */ +#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */ +#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_INTTYPE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode */ +#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Slew Rate Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for normal Mode */ +#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode */ +#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Pull-up And Pull-down Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode */ +#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode */ +#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_DBCTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset */ +#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */ + +#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz */ +#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK */ + +#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks */ +#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks */ +#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks */ +#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks */ +#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks */ +#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks */ +#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks */ +#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks */ +#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks */ +#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks */ +#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks */ +#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks */ +#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks */ +#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks */ +#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks */ +#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks */ + + +/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping. + * Example 1: + * + * PA0 = 1; + * + * It is used to set PA.0 to high; + * + * Example 2: + * + * if (PA0) + * PA0 = 0; + * + * If PA.0 pin status is high, then set PA.0 data output to low. + */ + + +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT0 ) +#define PA0 PA0_NS /*!< Specify PA.0 Pin Data Input/Output */ +#else +#define PA0 PA0_S /*!< Specify PA.0 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT1 ) +#define PA1 PA1_NS /*!< Specify PA.1 Pin Data Input/Output */ +#else +#define PA1 PA1_S /*!< Specify PA.1 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT2 ) +#define PA2 PA2_NS /*!< Specify PA.2 Pin Data Input/Output */ +#else +#define PA2 PA2_S /*!< Specify PA.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT3 ) +#define PA3 PA3_NS /*!< Specify PA.3 Pin Data Input/Output */ +#else +#define PA3 PA3_S /*!< Specify PA.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT4 ) +#define PA4 PA4_NS /*!< Specify PA.4 Pin Data Input/Output */ +#else +#define PA4 PA4_S /*!< Specify PA.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT5 ) +#define PA5 PA5_NS /*!< Specify PA.5 Pin Data Input/Output */ +#else +#define PA5 PA5_S /*!< Specify PA.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT6 ) +#define PA6 PA6_NS /*!< Specify PA.6 Pin Data Input/Output */ +#else +#define PA6 PA6_S /*!< Specify PA.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT7 ) +#define PA7 PA7_NS /*!< Specify PA.7 Pin Data Input/Output */ +#else +#define PA7 PA7_S /*!< Specify PA.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT8 ) +#define PA8 PA8_NS /*!< Specify PA.8 Pin Data Input/Output */ +#else +#define PA8 PA8_S /*!< Specify PA.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT9 ) +#define PA9 PA9_NS /*!< Specify PA.9 Pin Data Input/Output */ +#else +#define PA9 PA9_S /*!< Specify PA.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT10 ) +#define PA10 PA10_NS /*!< Specify PA.10 Pin Data Input/Output */ +#else +#define PA10 PA10_S /*!< Specify PA.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT11 ) +#define PA11 PA11_NS /*!< Specify PA.11 Pin Data Input/Output */ +#else +#define PA11 PA11_S /*!< Specify PA.11 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT12 ) +#define PA12 PA12_NS /*!< Specify PA.12 Pin Data Input/Output */ +#else +#define PA12 PA12_S /*!< Specify PA.12 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT13 ) +#define PA13 PA13_NS /*!< Specify PA.13 Pin Data Input/Output */ +#else +#define PA13 PA13_S /*!< Specify PA.13 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT14 ) +#define PA14 PA14_NS /*!< Specify PA.14 Pin Data Input/Output */ +#else +#define PA14 PA14_S /*!< Specify PA.14 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET0_VAL) && (SCU_INIT_IONSSET0_VAL & BIT15 ) +#define PA15 PA15_NS /*!< Specify PA.15 Pin Data Input/Output */ +#else +#define PA15 PA15_S /*!< Specify PA.15 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT0 ) +#define PB0 PB0_NS /*!< Specify PB.0 Pin Data Input/Output */ +#else +#define PB0 PB0_S /*!< Specify PB.0 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT1 ) +#define PB1 PB1_NS /*!< Specify PB.1 Pin Data Input/Output */ +#else +#define PB1 PB1_S /*!< Specify PB.1 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT2 ) +#define PB2 PB2_NS /*!< Specify PB.2 Pin Data Input/Output */ +#else +#define PB2 PB2_S /*!< Specify PB.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT3 ) +#define PB3 PB3_NS /*!< Specify PB.3 Pin Data Input/Output */ +#else +#define PB3 PB3_S /*!< Specify PB.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT4 ) +#define PB4 PB4_NS /*!< Specify PB.4 Pin Data Input/Output */ +#else +#define PB4 PB4_S /*!< Specify PB.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT5 ) +#define PB5 PB5_NS /*!< Specify PB.5 Pin Data Input/Output */ +#else +#define PB5 PB5_S /*!< Specify PB.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT6 ) +#define PB6 PB6_NS /*!< Specify PB.6 Pin Data Input/Output */ +#else +#define PB6 PB6_S /*!< Specify PB.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT7 ) +#define PB7 PB7_NS /*!< Specify PB.7 Pin Data Input/Output */ +#else +#define PB7 PB7_S /*!< Specify PB.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT8 ) +#define PB8 PB8_NS /*!< Specify PB.8 Pin Data Input/Output */ +#else +#define PB8 PB8_S /*!< Specify PB.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT9 ) +#define PB9 PB9_NS /*!< Specify PB.9 Pin Data Input/Output */ +#else +#define PB9 PB9_S /*!< Specify PB.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT10 ) +#define PB10 PB10_NS /*!< Specify PB.10 Pin Data Input/Output */ +#else +#define PB10 PB10_S /*!< Specify PB.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT11 ) +#define PB11 PB11_NS /*!< Specify PB.11 Pin Data Input/Output */ +#else +#define PB11 PB11_S /*!< Specify PB.11 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT12 ) +#define PB12 PB12_NS /*!< Specify PB.12 Pin Data Input/Output */ +#else +#define PB12 PB12_S /*!< Specify PB.12 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT13 ) +#define PB13 PB13_NS /*!< Specify PB.13 Pin Data Input/Output */ +#else +#define PB13 PB13_S /*!< Specify PB.13 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT14 ) +#define PB14 PB14_NS /*!< Specify PB.14 Pin Data Input/Output */ +#else +#define PB14 PB14_S /*!< Specify PB.14 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET1_VAL) && (SCU_INIT_IONSSET1_VAL & BIT15 ) +#define PB15 PB15_NS /*!< Specify PB.15 Pin Data Input/Output */ +#else +#define PB15 PB15_S /*!< Specify PB.15 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT0 ) +#define PC0 PC0_NS /*!< Specify PC.0 Pin Data Input/Output */ +#else +#define PC0 PC0_S /*!< Specify PC.0 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT1 ) +#define PC1 PC1_NS /*!< Specify PC.1 Pin Data Input/Output */ +#else +#define PC1 PC1_S /*!< Specify PC.1 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT2 ) +#define PC2 PC2_NS /*!< Specify PC.2 Pin Data Input/Output */ +#else +#define PC2 PC2_S /*!< Specify PC.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT3 ) +#define PC3 PC3_NS /*!< Specify PC.3 Pin Data Input/Output */ +#else +#define PC3 PC3_S /*!< Specify PC.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT4 ) +#define PC4 PC4_NS /*!< Specify PC.4 Pin Data Input/Output */ +#else +#define PC4 PC4_S /*!< Specify PC.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT5 ) +#define PC5 PC5_NS /*!< Specify PC.5 Pin Data Input/Output */ +#else +#define PC5 PC5_S /*!< Specify PC.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT6 ) +#define PC6 PC6_NS /*!< Specify PC.6 Pin Data Input/Output */ +#else +#define PC6 PC6_S /*!< Specify PC.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT7 ) +#define PC7 PC7_NS /*!< Specify PC.7 Pin Data Input/Output */ +#else +#define PC7 PC7_S /*!< Specify PC.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT8 ) +#define PC8 PC8_NS /*!< Specify PC.8 Pin Data Input/Output */ +#else +#define PC8 PC8_S /*!< Specify PC.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT9 ) +#define PC9 PC9_NS /*!< Specify PC.9 Pin Data Input/Output */ +#else +#define PC9 PC9_S /*!< Specify PC.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT10 ) +#define PC10 PC10_NS /*!< Specify PC.10 Pin Data Input/Output */ +#else +#define PC10 PC10_S /*!< Specify PC.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT11 ) +#define PC11 PC11_NS /*!< Specify PC.11 Pin Data Input/Output */ +#else +#define PC11 PC11_S /*!< Specify PC.11 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT12 ) +#define PC12 PC12_NS /*!< Specify PC.12 Pin Data Input/Output */ +#else +#define PC12 PC12_S /*!< Specify PC.12 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET2_VAL) && (SCU_INIT_IONSSET2_VAL & BIT13 ) +#define PC13 PC13_NS /*!< Specify PC.13 Pin Data Input/Output */ +#else +#define PC13 PC13_S /*!< Specify PC.13 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT0 ) +#define PD0 PD0_NS /*!< Specify PD.0 Pin Data Input/Output */ +#else +#define PD0 PD0_S /*!< Specify PD.0 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT1 ) +#define PD1 PD1_NS /*!< Specify PD.1 Pin Data Input/Output */ +#else +#define PD1 PD1_S /*!< Specify PD.1 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT2 ) +#define PD2 PD2_NS /*!< Specify PD.2 Pin Data Input/Output */ +#else +#define PD2 PD2_S /*!< Specify PD.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT3 ) +#define PD3 PD3_NS /*!< Specify PD.3 Pin Data Input/Output */ +#else +#define PD3 PD3_S /*!< Specify PD.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT4 ) +#define PD4 PD4_NS /*!< Specify PD.4 Pin Data Input/Output */ +#else +#define PD4 PD4_S /*!< Specify PD.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT5 ) +#define PD5 PD5_NS /*!< Specify PD.5 Pin Data Input/Output */ +#else +#define PD5 PD5_S /*!< Specify PD.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT6 ) +#define PD6 PD6_NS /*!< Specify PD.6 Pin Data Input/Output */ +#else +#define PD6 PD6_S /*!< Specify PD.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT7 ) +#define PD7 PD7_NS /*!< Specify PD.7 Pin Data Input/Output */ +#else +#define PD7 PD7_S /*!< Specify PD.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT8 ) +#define PD8 PD8_NS /*!< Specify PD.8 Pin Data Input/Output */ +#else +#define PD8 PD8_S /*!< Specify PD.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT9 ) +#define PD9 PD9_NS /*!< Specify PD.9 Pin Data Input/Output */ +#else +#define PD9 PD9_S /*!< Specify PD.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT10 ) +#define PD10 PD10_NS /*!< Specify PD.10 Pin Data Input/Output */ +#else +#define PD10 PD10_S /*!< Specify PD.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT11 ) +#define PD11 PD11_NS /*!< Specify PD.11 Pin Data Input/Output */ +#else +#define PD11 PD11_S /*!< Specify PD.11 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT12 ) +#define PD12 PD12_NS /*!< Specify PD.12 Pin Data Input/Output */ +#else +#define PD12 PD12_S /*!< Specify PD.12 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET3_VAL) && (SCU_INIT_IONSSET3_VAL & BIT14 ) +#define PD14 PD14_NS /*!< Specify PD.14 Pin Data Input/Output */ +#else +#define PD14 PD14_S /*!< Specify PD.14 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT0 ) +#define PE0 PE0_NS /*!< Specify PE.0 Pin Data Input/Output */ +#else +#define PE0 PE0_S /*!< Specify PE.0 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT1 ) +#define PE1 PE1_NS /*!< Specify PE.1 Pin Data Input/Output */ +#else +#define PE1 PE1_S /*!< Specify PE.1 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT2 ) +#define PE2 PE2_NS /*!< Specify PE.2 Pin Data Input/Output */ +#else +#define PE2 PE2_S /*!< Specify PE.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT3 ) +#define PE3 PE3_NS /*!< Specify PE.3 Pin Data Input/Output */ +#else +#define PE3 PE3_S /*!< Specify PE.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT4 ) +#define PE4 PE4_NS /*!< Specify PE.4 Pin Data Input/Output */ +#else +#define PE4 PE4_S /*!< Specify PE.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT5 ) +#define PE5 PE5_NS /*!< Specify PE.5 Pin Data Input/Output */ +#else +#define PE5 PE5_S /*!< Specify PE.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT6 ) +#define PE6 PE6_NS /*!< Specify PE.6 Pin Data Input/Output */ +#else +#define PE6 PE6_S /*!< Specify PE.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT7 ) +#define PE7 PE7_NS /*!< Specify PE.7 Pin Data Input/Output */ +#else +#define PE7 PE7_S /*!< Specify PE.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT8 ) +#define PE8 PE8_NS /*!< Specify PE.8 Pin Data Input/Output */ +#else +#define PE8 PE8_S /*!< Specify PE.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT9 ) +#define PE9 PE9_NS /*!< Specify PE.9 Pin Data Input/Output */ +#else +#define PE9 PE9_S /*!< Specify PE.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT10 ) +#define PE10 PE10_NS /*!< Specify PE.10 Pin Data Input/Output */ +#else +#define PE10 PE10_S /*!< Specify PE.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT11 ) +#define PE11 PE11_NS /*!< Specify PE.11 Pin Data Input/Output */ +#else +#define PE11 PE11_S /*!< Specify PE.11 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT12 ) +#define PE12 PE12_NS /*!< Specify PE.12 Pin Data Input/Output */ +#else +#define PE12 PE12_S /*!< Specify PE.12 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT13 ) +#define PE13 PE13_NS /*!< Specify PE.13 Pin Data Input/Output */ +#else +#define PE13 PE13_S /*!< Specify PE.13 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT14 ) +#define PE14 PE14_NS /*!< Specify PE.14 Pin Data Input/Output */ +#else +#define PE14 PE14_S /*!< Specify PE.14 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET4_VAL) && (SCU_INIT_IONSSET4_VAL & BIT15 ) +#define PE15 PE15_NS /*!< Specify PE.15 Pin Data Input/Output */ +#else +#define PE15 PE15_S /*!< Specify PE.15 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT0 ) +#define PF0 PF0_NS /*!< Specify PF.0 Pin Data Input/Output */ +#else +#define PF0 PF0_S /*!< Specify PF.0 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT1 ) +#define PF1 PF1_NS /*!< Specify PF.1 Pin Data Input/Output */ +#else +#define PF1 PF1_S /*!< Specify PF.1 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT2 ) +#define PF2 PF2_NS /*!< Specify PF.2 Pin Data Input/Output */ +#else +#define PF2 PF2_S /*!< Specify PF.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT3 ) +#define PF3 PF3_NS /*!< Specify PF.3 Pin Data Input/Output */ +#else +#define PF3 PF3_S /*!< Specify PF.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT4 ) +#define PF4 PF4_NS /*!< Specify PF.4 Pin Data Input/Output */ +#else +#define PF4 PF4_S /*!< Specify PF.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT5 ) +#define PF5 PF5_NS /*!< Specify PF.5 Pin Data Input/Output */ +#else +#define PF5 PF5_S /*!< Specify PF.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT6 ) +#define PF6 PF6_NS /*!< Specify PF.6 Pin Data Input/Output */ +#else +#define PF6 PF6_S /*!< Specify PF.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT7 ) +#define PF7 PF7_NS /*!< Specify PF.7 Pin Data Input/Output */ +#else +#define PF7 PF7_S /*!< Specify PF.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT8 ) +#define PF8 PF8_NS /*!< Specify PF.8 Pin Data Input/Output */ +#else +#define PF8 PF8_S /*!< Specify PF.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT9 ) +#define PF9 PF9_NS /*!< Specify PF.9 Pin Data Input/Output */ +#else +#define PF9 PF9_S /*!< Specify PF.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT10 ) +#define PF10 PF10_NS /*!< Specify PF.10 Pin Data Input/Output */ +#else +#define PF10 PF10_S /*!< Specify PF.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET5_VAL) && (SCU_INIT_IONSSET5_VAL & BIT11 ) +#define PF11 PF11_NS /*!< Specify PF.11 Pin Data Input/Output */ +#else +#define PF11 PF11_S /*!< Specify PF.11 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT2 ) +#define PG2 PG2_NS /*!< Specify PG.2 Pin Data Input/Output */ +#else +#define PG2 PG2_S /*!< Specify PG.2 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT3 ) +#define PG3 PG3_NS /*!< Specify PG.3 Pin Data Input/Output */ +#else +#define PG3 PG3_S /*!< Specify PG.3 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT4 ) +#define PG4 PG4_NS /*!< Specify PG.4 Pin Data Input/Output */ +#else +#define PG4 PG4_S /*!< Specify PG.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT9 ) +#define PG9 PG9_NS /*!< Specify PG.9 Pin Data Input/Output */ +#else +#define PG9 PG9_S /*!< Specify PG.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT10 ) +#define PG10 PG10_NS /*!< Specify PG.10 Pin Data Input/Output */ +#else +#define PG10 PG10_S /*!< Specify PG.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT11 ) +#define PG11 PG11_NS /*!< Specify PG.11 Pin Data Input/Output */ +#else +#define PG11 PG11_S /*!< Specify PG.11 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT12 ) +#define PG12 PG12_NS /*!< Specify PG.12 Pin Data Input/Output */ +#else +#define PG12 PG12_S /*!< Specify PG.12 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT13 ) +#define PG13 PG13_NS /*!< Specify PG.13 Pin Data Input/Output */ +#else +#define PG13 PG13_S /*!< Specify PG.13 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT14 ) +#define PG14 PG14_NS /*!< Specify PG.14 Pin Data Input/Output */ +#else +#define PG14 PG14_S /*!< Specify PG.14 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET6_VAL) && (SCU_INIT_IONSSET6_VAL & BIT15 ) +#define PG15 PG15_NS /*!< Specify PG.15 Pin Data Input/Output */ +#else +#define PG15 PG15_S /*!< Specify PG.15 Pin Data Input/Output */ +#endif + +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT4 ) +#define PH4 PH4_NS /*!< Specify PH.4 Pin Data Input/Output */ +#else +#define PH4 PH4_S /*!< Specify PH.4 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT5 ) +#define PH5 PH5_NS /*!< Specify PH.5 Pin Data Input/Output */ +#else +#define PH5 PH5_S /*!< Specify PH.5 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT6 ) +#define PH6 PH6_NS /*!< Specify PH.6 Pin Data Input/Output */ +#else +#define PH6 PH6_S /*!< Specify PH.6 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT7 ) +#define PH7 PH7_NS /*!< Specify PH.7 Pin Data Input/Output */ +#else +#define PH7 PH7_S /*!< Specify PH.7 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT8 ) +#define PH8 PH8_NS /*!< Specify PH.8 Pin Data Input/Output */ +#else +#define PH8 PH8_S /*!< Specify PH.8 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT9 ) +#define PH9 PH9_NS /*!< Specify PH.9 Pin Data Input/Output */ +#else +#define PH9 PH9_S /*!< Specify PH.9 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT10 ) +#define PH10 PH10_NS /*!< Specify PH.10 Pin Data Input/Output */ +#else +#define PH10 PH10_S /*!< Specify PH.10 Pin Data Input/Output */ +#endif +#if defined (SCU_INIT_IONSSET7_VAL) && (SCU_INIT_IONSSET7_VAL & BIT11 ) +#define PH11 PH11_NS /*!< Specify PH.11 Pin Data Input/Output */ +#else +#define PH11 PH11_S /*!< Specify PH.11 Pin Data Input/Output */ +#endif + + +/* GPIO bit definitions for secure */ +#define GPIO_PIN_DATA_S(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#define PA0_S GPIO_PIN_DATA_S(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */ +#define PA1_S GPIO_PIN_DATA_S(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */ +#define PA2_S GPIO_PIN_DATA_S(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */ +#define PA3_S GPIO_PIN_DATA_S(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */ +#define PA4_S GPIO_PIN_DATA_S(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */ +#define PA5_S GPIO_PIN_DATA_S(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */ +#define PA6_S GPIO_PIN_DATA_S(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */ +#define PA7_S GPIO_PIN_DATA_S(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */ +#define PA8_S GPIO_PIN_DATA_S(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */ +#define PA9_S GPIO_PIN_DATA_S(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */ +#define PA10_S GPIO_PIN_DATA_S(0, 10) /*!< Specify PA.10 Pin Data Input/Output */ +#define PA11_S GPIO_PIN_DATA_S(0, 11) /*!< Specify PA.11 Pin Data Input/Output */ +#define PA12_S GPIO_PIN_DATA_S(0, 12) /*!< Specify PA.12 Pin Data Input/Output */ +#define PA13_S GPIO_PIN_DATA_S(0, 13) /*!< Specify PA.13 Pin Data Input/Output */ +#define PA14_S GPIO_PIN_DATA_S(0, 14) /*!< Specify PA.14 Pin Data Input/Output */ +#define PA15_S GPIO_PIN_DATA_S(0, 15) /*!< Specify PA.15 Pin Data Input/Output */ +#define PB0_S GPIO_PIN_DATA_S(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */ +#define PB1_S GPIO_PIN_DATA_S(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */ +#define PB2_S GPIO_PIN_DATA_S(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */ +#define PB3_S GPIO_PIN_DATA_S(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */ +#define PB4_S GPIO_PIN_DATA_S(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */ +#define PB5_S GPIO_PIN_DATA_S(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */ +#define PB6_S GPIO_PIN_DATA_S(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */ +#define PB7_S GPIO_PIN_DATA_S(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */ +#define PB8_S GPIO_PIN_DATA_S(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */ +#define PB9_S GPIO_PIN_DATA_S(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */ +#define PB10_S GPIO_PIN_DATA_S(1, 10) /*!< Specify PB.10 Pin Data Input/Output */ +#define PB11_S GPIO_PIN_DATA_S(1, 11) /*!< Specify PB.11 Pin Data Input/Output */ +#define PB12_S GPIO_PIN_DATA_S(1, 12) /*!< Specify PB.12 Pin Data Input/Output */ +#define PB13_S GPIO_PIN_DATA_S(1, 13) /*!< Specify PB.13 Pin Data Input/Output */ +#define PB14_S GPIO_PIN_DATA_S(1, 14) /*!< Specify PB.14 Pin Data Input/Output */ +#define PB15_S GPIO_PIN_DATA_S(1, 15) /*!< Specify PB.15 Pin Data Input/Output */ +#define PC0_S GPIO_PIN_DATA_S(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */ +#define PC1_S GPIO_PIN_DATA_S(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */ +#define PC2_S GPIO_PIN_DATA_S(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */ +#define PC3_S GPIO_PIN_DATA_S(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */ +#define PC4_S GPIO_PIN_DATA_S(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */ +#define PC5_S GPIO_PIN_DATA_S(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */ +#define PC6_S GPIO_PIN_DATA_S(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */ +#define PC7_S GPIO_PIN_DATA_S(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */ +#define PC8_S GPIO_PIN_DATA_S(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */ +#define PC9_S GPIO_PIN_DATA_S(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */ +#define PC10_S GPIO_PIN_DATA_S(2, 10) /*!< Specify PC.10 Pin Data Input/Output */ +#define PC11_S GPIO_PIN_DATA_S(2, 11) /*!< Specify PC.11 Pin Data Input/Output */ +#define PC12_S GPIO_PIN_DATA_S(2, 12) /*!< Specify PC.12 Pin Data Input/Output */ +#define PC13_S GPIO_PIN_DATA_S(2, 13) /*!< Specify PC.13 Pin Data Input/Output */ +#define PD0_S GPIO_PIN_DATA_S(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */ +#define PD1_S GPIO_PIN_DATA_S(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */ +#define PD2_S GPIO_PIN_DATA_S(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */ +#define PD3_S GPIO_PIN_DATA_S(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */ +#define PD4_S GPIO_PIN_DATA_S(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */ +#define PD5_S GPIO_PIN_DATA_S(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */ +#define PD6_S GPIO_PIN_DATA_S(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */ +#define PD7_S GPIO_PIN_DATA_S(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */ +#define PD8_S GPIO_PIN_DATA_S(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */ +#define PD9_S GPIO_PIN_DATA_S(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */ +#define PD10_S GPIO_PIN_DATA_S(3, 10) /*!< Specify PD.10 Pin Data Input/Output */ +#define PD11_S GPIO_PIN_DATA_S(3, 11) /*!< Specify PD.11 Pin Data Input/Output */ +#define PD12_S GPIO_PIN_DATA_S(3, 12) /*!< Specify PD.12 Pin Data Input/Output */ +#define PD14_S GPIO_PIN_DATA_S(3, 14) /*!< Specify PD.14 Pin Data Input/Output */ +#define PE0_S GPIO_PIN_DATA_S(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */ +#define PE1_S GPIO_PIN_DATA_S(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */ +#define PE2_S GPIO_PIN_DATA_S(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */ +#define PE3_S GPIO_PIN_DATA_S(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */ +#define PE4_S GPIO_PIN_DATA_S(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */ +#define PE5_S GPIO_PIN_DATA_S(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */ +#define PE6_S GPIO_PIN_DATA_S(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */ +#define PE7_S GPIO_PIN_DATA_S(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */ +#define PE8_S GPIO_PIN_DATA_S(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */ +#define PE9_S GPIO_PIN_DATA_S(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */ +#define PE10_S GPIO_PIN_DATA_S(4, 10) /*!< Specify PE.10 Pin Data Input/Output */ +#define PE11_S GPIO_PIN_DATA_S(4, 11) /*!< Specify PE.11 Pin Data Input/Output */ +#define PE12_S GPIO_PIN_DATA_S(4, 12) /*!< Specify PE.12 Pin Data Input/Output */ +#define PE13_S GPIO_PIN_DATA_S(4, 13) /*!< Specify PE.13 Pin Data Input/Output */ +#define PE14_S GPIO_PIN_DATA_S(4, 14) /*!< Specify PE.14 Pin Data Input/Output */ +#define PE15_S GPIO_PIN_DATA_S(4, 15) /*!< Specify PE.15 Pin Data Input/Output */ +#define PF0_S GPIO_PIN_DATA_S(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */ +#define PF1_S GPIO_PIN_DATA_S(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */ +#define PF2_S GPIO_PIN_DATA_S(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */ +#define PF3_S GPIO_PIN_DATA_S(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */ +#define PF4_S GPIO_PIN_DATA_S(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */ +#define PF5_S GPIO_PIN_DATA_S(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */ +#define PF6_S GPIO_PIN_DATA_S(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */ +#define PF7_S GPIO_PIN_DATA_S(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */ +#define PF8_S GPIO_PIN_DATA_S(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */ +#define PF9_S GPIO_PIN_DATA_S(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */ +#define PF10_S GPIO_PIN_DATA_S(5, 10) /*!< Specify PF.10 Pin Data Input/Output */ +#define PF11_S GPIO_PIN_DATA_S(5, 11) /*!< Specify PF.11 Pin Data Input/Output */ +#define PG2_S GPIO_PIN_DATA_S(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */ +#define PG3_S GPIO_PIN_DATA_S(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */ +#define PG4_S GPIO_PIN_DATA_S(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */ +#define PG9_S GPIO_PIN_DATA_S(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */ +#define PG10_S GPIO_PIN_DATA_S(6, 10) /*!< Specify PG.10 Pin Data Input/Output */ +#define PG11_S GPIO_PIN_DATA_S(6, 11) /*!< Specify PG.11 Pin Data Input/Output */ +#define PG12_S GPIO_PIN_DATA_S(6, 12) /*!< Specify PG.12 Pin Data Input/Output */ +#define PG13_S GPIO_PIN_DATA_S(6, 13) /*!< Specify PG.13 Pin Data Input/Output */ +#define PG14_S GPIO_PIN_DATA_S(6, 14) /*!< Specify PG.14 Pin Data Input/Output */ +#define PG15_S GPIO_PIN_DATA_S(6, 15) /*!< Specify PG.15 Pin Data Input/Output */ +#define PH4_S GPIO_PIN_DATA_S(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */ +#define PH5_S GPIO_PIN_DATA_S(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */ +#define PH6_S GPIO_PIN_DATA_S(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */ +#define PH7_S GPIO_PIN_DATA_S(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */ +#define PH8_S GPIO_PIN_DATA_S(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */ +#define PH9_S GPIO_PIN_DATA_S(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */ +#define PH10_S GPIO_PIN_DATA_S(7, 10) /*!< Specify PH.10 Pin Data Input/Output */ +#define PH11_S GPIO_PIN_DATA_S(7, 11) /*!< Specify PH.11 Pin Data Input/Output */ + +/* GPIO bit definitions for non-secure */ +#define GPIO_PIN_DATA_NS(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2)))) +#define PA0_NS GPIO_PIN_DATA_NS(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */ +#define PA1_NS GPIO_PIN_DATA_NS(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */ +#define PA2_NS GPIO_PIN_DATA_NS(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */ +#define PA3_NS GPIO_PIN_DATA_NS(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */ +#define PA4_NS GPIO_PIN_DATA_NS(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */ +#define PA5_NS GPIO_PIN_DATA_NS(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */ +#define PA6_NS GPIO_PIN_DATA_NS(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */ +#define PA7_NS GPIO_PIN_DATA_NS(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */ +#define PA8_NS GPIO_PIN_DATA_NS(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */ +#define PA9_NS GPIO_PIN_DATA_NS(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */ +#define PA10_NS GPIO_PIN_DATA_NS(0, 10) /*!< Specify PA.10 Pin Data Input/Output */ +#define PA11_NS GPIO_PIN_DATA_NS(0, 11) /*!< Specify PA.11 Pin Data Input/Output */ +#define PA12_NS GPIO_PIN_DATA_NS(0, 12) /*!< Specify PA.12 Pin Data Input/Output */ +#define PA13_NS GPIO_PIN_DATA_NS(0, 13) /*!< Specify PA.13 Pin Data Input/Output */ +#define PA14_NS GPIO_PIN_DATA_NS(0, 14) /*!< Specify PA.14 Pin Data Input/Output */ +#define PA15_NS GPIO_PIN_DATA_NS(0, 15) /*!< Specify PA.15 Pin Data Input/Output */ +#define PB0_NS GPIO_PIN_DATA_NS(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */ +#define PB1_NS GPIO_PIN_DATA_NS(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */ +#define PB2_NS GPIO_PIN_DATA_NS(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */ +#define PB3_NS GPIO_PIN_DATA_NS(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */ +#define PB4_NS GPIO_PIN_DATA_NS(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */ +#define PB5_NS GPIO_PIN_DATA_NS(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */ +#define PB6_NS GPIO_PIN_DATA_NS(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */ +#define PB7_NS GPIO_PIN_DATA_NS(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */ +#define PB8_NS GPIO_PIN_DATA_NS(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */ +#define PB9_NS GPIO_PIN_DATA_NS(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */ +#define PB10_NS GPIO_PIN_DATA_NS(1, 10) /*!< Specify PB.10 Pin Data Input/Output */ +#define PB11_NS GPIO_PIN_DATA_NS(1, 11) /*!< Specify PB.11 Pin Data Input/Output */ +#define PB12_NS GPIO_PIN_DATA_NS(1, 12) /*!< Specify PB.12 Pin Data Input/Output */ +#define PB13_NS GPIO_PIN_DATA_NS(1, 13) /*!< Specify PB.13 Pin Data Input/Output */ +#define PB14_NS GPIO_PIN_DATA_NS(1, 14) /*!< Specify PB.14 Pin Data Input/Output */ +#define PB15_NS GPIO_PIN_DATA_NS(1, 15) /*!< Specify PB.15 Pin Data Input/Output */ +#define PC0_NS GPIO_PIN_DATA_NS(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */ +#define PC1_NS GPIO_PIN_DATA_NS(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */ +#define PC2_NS GPIO_PIN_DATA_NS(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */ +#define PC3_NS GPIO_PIN_DATA_NS(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */ +#define PC4_NS GPIO_PIN_DATA_NS(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */ +#define PC5_NS GPIO_PIN_DATA_NS(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */ +#define PC6_NS GPIO_PIN_DATA_NS(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */ +#define PC7_NS GPIO_PIN_DATA_NS(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */ +#define PC8_NS GPIO_PIN_DATA_NS(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */ +#define PC9_NS GPIO_PIN_DATA_NS(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */ +#define PC10_NS GPIO_PIN_DATA_NS(2, 10) /*!< Specify PC.10 Pin Data Input/Output */ +#define PC11_NS GPIO_PIN_DATA_NS(2, 11) /*!< Specify PC.11 Pin Data Input/Output */ +#define PC12_NS GPIO_PIN_DATA_NS(2, 12) /*!< Specify PC.12 Pin Data Input/Output */ +#define PC13_NS GPIO_PIN_DATA_NS(2, 13) /*!< Specify PC.13 Pin Data Input/Output */ +#define PD0_NS GPIO_PIN_DATA_NS(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */ +#define PD1_NS GPIO_PIN_DATA_NS(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */ +#define PD2_NS GPIO_PIN_DATA_NS(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */ +#define PD3_NS GPIO_PIN_DATA_NS(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */ +#define PD4_NS GPIO_PIN_DATA_NS(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */ +#define PD5_NS GPIO_PIN_DATA_NS(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */ +#define PD6_NS GPIO_PIN_DATA_NS(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */ +#define PD7_NS GPIO_PIN_DATA_NS(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */ +#define PD8_NS GPIO_PIN_DATA_NS(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */ +#define PD9_NS GPIO_PIN_DATA_NS(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */ +#define PD10_NS GPIO_PIN_DATA_NS(3, 10) /*!< Specify PD.10 Pin Data Input/Output */ +#define PD11_NS GPIO_PIN_DATA_NS(3, 11) /*!< Specify PD.11 Pin Data Input/Output */ +#define PD12_NS GPIO_PIN_DATA_NS(3, 12) /*!< Specify PD.12 Pin Data Input/Output */ +#define PD14_NS GPIO_PIN_DATA_NS(3, 14) /*!< Specify PD.14 Pin Data Input/Output */ +#define PE0_NS GPIO_PIN_DATA_NS(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */ +#define PE1_NS GPIO_PIN_DATA_NS(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */ +#define PE2_NS GPIO_PIN_DATA_NS(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */ +#define PE3_NS GPIO_PIN_DATA_NS(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */ +#define PE4_NS GPIO_PIN_DATA_NS(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */ +#define PE5_NS GPIO_PIN_DATA_NS(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */ +#define PE6_NS GPIO_PIN_DATA_NS(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */ +#define PE7_NS GPIO_PIN_DATA_NS(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */ +#define PE8_NS GPIO_PIN_DATA_NS(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */ +#define PE9_NS GPIO_PIN_DATA_NS(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */ +#define PE10_NS GPIO_PIN_DATA_NS(4, 10) /*!< Specify PE.10 Pin Data Input/Output */ +#define PE11_NS GPIO_PIN_DATA_NS(4, 11) /*!< Specify PE.11 Pin Data Input/Output */ +#define PE12_NS GPIO_PIN_DATA_NS(4, 12) /*!< Specify PE.12 Pin Data Input/Output */ +#define PE13_NS GPIO_PIN_DATA_NS(4, 13) /*!< Specify PE.13 Pin Data Input/Output */ +#define PE14_NS GPIO_PIN_DATA_NS(4, 14) /*!< Specify PE.14 Pin Data Input/Output */ +#define PE15_NS GPIO_PIN_DATA_NS(4, 15) /*!< Specify PE.15 Pin Data Input/Output */ +#define PF0_NS GPIO_PIN_DATA_NS(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */ +#define PF1_NS GPIO_PIN_DATA_NS(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */ +#define PF2_NS GPIO_PIN_DATA_NS(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */ +#define PF3_NS GPIO_PIN_DATA_NS(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */ +#define PF4_NS GPIO_PIN_DATA_NS(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */ +#define PF5_NS GPIO_PIN_DATA_NS(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */ +#define PF6_NS GPIO_PIN_DATA_NS(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */ +#define PF7_NS GPIO_PIN_DATA_NS(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */ +#define PF8_NS GPIO_PIN_DATA_NS(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */ +#define PF9_NS GPIO_PIN_DATA_NS(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */ +#define PF10_NS GPIO_PIN_DATA_NS(5, 10) /*!< Specify PF.10 Pin Data Input/Output */ +#define PF11_NS GPIO_PIN_DATA_NS(5, 11) /*!< Specify PF.11 Pin Data Input/Output */ +#define PG2_NS GPIO_PIN_DATA_NS(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */ +#define PG3_NS GPIO_PIN_DATA_NS(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */ +#define PG4_NS GPIO_PIN_DATA_NS(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */ +#define PG9_NS GPIO_PIN_DATA_NS(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */ +#define PG10_NS GPIO_PIN_DATA_NS(6, 10) /*!< Specify PG.10 Pin Data Input/Output */ +#define PG11_NS GPIO_PIN_DATA_NS(6, 11) /*!< Specify PG.11 Pin Data Input/Output */ +#define PG12_NS GPIO_PIN_DATA_NS(6, 12) /*!< Specify PG.12 Pin Data Input/Output */ +#define PG13_NS GPIO_PIN_DATA_NS(6, 13) /*!< Specify PG.13 Pin Data Input/Output */ +#define PG14_NS GPIO_PIN_DATA_NS(6, 14) /*!< Specify PG.14 Pin Data Input/Output */ +#define PG15_NS GPIO_PIN_DATA_NS(6, 15) /*!< Specify PG.15 Pin Data Input/Output */ +#define PH4_NS GPIO_PIN_DATA_NS(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */ +#define PH5_NS GPIO_PIN_DATA_NS(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */ +#define PH6_NS GPIO_PIN_DATA_NS(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */ +#define PH7_NS GPIO_PIN_DATA_NS(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */ +#define PH8_NS GPIO_PIN_DATA_NS(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */ +#define PH9_NS GPIO_PIN_DATA_NS(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */ +#define PH10_NS GPIO_PIN_DATA_NS(7, 10) /*!< Specify PH.10 Pin Data Input/Output */ +#define PH11_NS GPIO_PIN_DATA_NS(7, 11) /*!< Specify PH.11 Pin Data Input/Output */ + + +/**@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */ + + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Clear GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Clear the interrupt status of specified GPIO pin. + */ +#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask)) + +/** + * @brief Disable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Disable the interrupt de-bounce function of specified GPIO pin. + */ +#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask)) + +/** + * @brief Enable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * @return None + * + * @details Enable the interrupt de-bounce function of specified GPIO pin. + */ +#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask)) + +/** + * @brief Disable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Disable I/O digital input path of specified GPIO pin. + */ +#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16)) + +/** + * @brief Enable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Enable I/O digital input path of specified GPIO pin. + */ +#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16)) + +/** + * @brief Disable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Disable I/O DOUT mask of specified GPIO pin. + */ +#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask)) + +/** + * @brief Enable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Enable I/O DOUT mask of specified GPIO pin. + */ +#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask)) + +/** + * @brief Get GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @retval 0 No interrupt at specified GPIO pin + * @retval 1 The specified GPIO pin generate an interrupt + * + * @details Get the interrupt status of specified GPIO pin. + */ +#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC. + * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be + * - \ref GPIO_DBCTL_DBCLKSEL_1 + * - \ref GPIO_DBCTL_DBCLKSEL_2 + * - \ref GPIO_DBCTL_DBCLKSEL_4 + * - \ref GPIO_DBCTL_DBCLKSEL_8 + * - \ref GPIO_DBCTL_DBCLKSEL_16 + * - \ref GPIO_DBCTL_DBCLKSEL_32 + * - \ref GPIO_DBCTL_DBCLKSEL_64 + * - \ref GPIO_DBCTL_DBCLKSEL_128 + * - \ref GPIO_DBCTL_DBCLKSEL_256 + * - \ref GPIO_DBCTL_DBCLKSEL_512 + * - \ref GPIO_DBCTL_DBCLKSEL_1024 + * - \ref GPIO_DBCTL_DBCLKSEL_2048 + * - \ref GPIO_DBCTL_DBCLKSEL_4096 + * - \ref GPIO_DBCTL_DBCLKSEL_8192 + * - \ref GPIO_DBCTL_DBCLKSEL_16384 + * - \ref GPIO_DBCTL_DBCLKSEL_32768 + * + * @return None + * + * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n + * Example: _GPIO_SET_DEBOUNCE_TIME(PA, GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n + * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n + * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us, + * and system will sampling interrupt input once per 400 us. + */ +#define GPIO_SET_DEBOUNCE_TIME(port, u32ClkSrc, u32ClkSel) ((port)->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel))) + +/** + * @brief Get GPIO Port IN Data + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * + * @return The specified port data + * + * @details Get the PIN register of specified GPIO port. + */ +#define GPIO_GET_IN_DATA(port) ((port)->PIN) + +/** + * @brief Set GPIO Port OUT Data + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Data GPIO port data. + * + * @return None + * + * @details Set the Data into specified GPIO port. + */ +#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data)) + +/** + * @brief Toggle Specified GPIO pin + * + * @param[in] u32Pin Pxy + * + * @return None + * + * @details Toggle the specified GPIO pint. + */ +#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1) + + +/** + * @brief Enable External GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB and PE. \n + * It could be 0 ~ 13 for PC GPIO port. \n + * It could be 0 ~ 12, 14 for PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n + * It could be 4 ~ 11 for PH GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be + * - \ref GPIO_INT_RISING + * - \ref GPIO_INT_FALLING + * - \ref GPIO_INT_BOTH_EDGE + * - \ref GPIO_INT_HIGH + * - \ref GPIO_INT_LOW + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_EnableEINT GPIO_EnableInt + +/** + * @brief Disable External GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB and PE. \n + * It could be 0 ~ 13 for PC GPIO port. \n + * It could be 0 ~ 12, 14 for PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n + * It could be 4 ~ 11 for PH GPIO port. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_DisableEINT GPIO_DisableInt + + +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs); +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin); +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); + + +/**@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group GPIO_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_H__ */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_i2c.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_i2c.h new file mode 100644 index 0000000000..7ff944cfdf --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_i2c.h @@ -0,0 +1,527 @@ +/**************************************************************************//** + * @file i2c.h + * @version V3.0 + * $Revision: 1 $ + * $Date: 16/07/07 7:50p $ + * @brief M2355 series I2C Serial Interface Controller(I2C) driver header file + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + +/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C_CTL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_CTL_STA_SI (0x28U) /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits */ +#define I2C_CTL_STA_SI_AA (0x2CU) /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits */ +#define I2C_CTL_STO_SI (0x18U) /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits */ +#define I2C_CTL_STO_SI_AA (0x1CU) /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits */ +#define I2C_CTL_SI (0x08U) /*!< I2C_CTL setting for I2C control bits. It would set SI bit */ +#define I2C_CTL_SI_AA (0x0CU) /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits */ +#define I2C_CTL_STA (0x20U) /*!< I2C_CTL setting for I2C control bits. It would set STA bit */ +#define I2C_CTL_STO (0x10U) /*!< I2C_CTL setting for I2C control bits. It would set STO bit */ +#define I2C_CTL_AA (0x04U) /*!< I2C_CTL setting for I2C control bits. It would set AA bit */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C GCMode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_GCMODE_ENABLE (1U) /*!< Enable I2C GC Mode */ +#define I2C_GCMODE_DISABLE (0U) /*!< Disable I2C GC Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C SMBUS constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_SMBH_ENABLE (1U) /*!< Enable SMBus Host Mode enable */ +#define I2C_SMBD_ENABLE (0U) /*!< Enable SMBus Device Mode enable */ +#define I2C_PECTX_ENABLE (1U) /*!< Enable SMBus Packet Error Check Transmit function */ +#define I2C_PECTX_DISABLE (0U) /*!< Disable SMBus Packet Error Check Transmit function */ + +/**@}*/ /* end of group I2C_EXPORTED_CONSTANTS */ + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ +/** + * @brief The macro is used to set I2C bus condition at One Time + * + * @param[in] i2c Specify I2C port + * @param[in] u8Ctrl A byte writes to I2C control register + * + * @return None + * + * @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK. + */ +#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3Cu) | (u8Ctrl)) + +/** + * @brief The macro is used to set START condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus START condition in I2C_CTL register. + */ +#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 | I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk) + +/** + * @brief The macro is used to wait I2C bus status get ready + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register. + */ +#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk)) + +/** + * @brief The macro is used to Read I2C Bus Data Register + * + * @param[in] i2c Specify I2C port + * + * @return A byte of I2C data register + * + * @details I2C controller read data from bus and save it in I2CDAT register. + */ +#define I2C_GET_DATA(i2c) ((i2c)->DAT) + +/** + * @brief Write a Data to I2C Data Register + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data A byte that writes to data register + * + * @return None + * + * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus. + */ +#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data)) + +/** + * @brief Get I2C Bus status code + * + * @param[in] i2c Specify I2C port + * + * @return I2C status code + * + * @details To get this status code to monitor I2C bus event. + */ +#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0) + +/** + * @brief Get Time-out flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 I2C Bus time-out is not happened + * @retval 1 I2C Bus time-out is happened + * + * @details When I2C bus occurs time-out event, the time-out flag will be set. + */ +#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1u : 0u) + +/** + * @brief To get wake-up flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details I2C bus occurs wake-up event, wake-up flag will be set. + */ +#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1u : 0u) + +/** + * @brief To clear wake-up flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details If wake-up flag is set, use this macro to clear it. + */ +#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk) + +/** + * @brief To get wake-up address frame ACK done flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 The ACK bit cycle of address match frame is not done + * @retval 1 The ACK bit cycle of address match frame is done in power-down + * + * @details I2C bus occurs wake-up event and address frame ACK is done, this flag will be set. + * + * \hideinitializer + */ +#define I2C_GET_WAKEUP_DONE(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKAKDONE_Msk) == I2C_WKSTS_WKAKDONE_Msk ? 1u : 0u) + +/** + * @brief To clear address frame ACK done flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details If wake-up done is set, use this macro to clear it. + * + * \hideinitializer + */ +#define I2C_CLEAR_WAKEUP_DONE(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKAKDONE_Msk) + +/** + * @brief To get read/write status bit in address wakeup frame + * + * @param[in] i2c Specify I2C port + * + * @retval 0 Write command be record on the address match wakeup frame + * @retval 1 Read command be record on the address match wakeup frame. + * + * @details I2C bus occurs wake-up event and address frame is received, this bit will record read/write status. + * + * \hideinitializer +*/ +#define I2C_GET_WAKEUP_WR_STATUS(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WRSTSWK_Msk) == I2C_WKSTS_WRSTSWK_Msk ? 1u : 0u) + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * + */ +#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS) + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return Packet error check byte value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * + */ +#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC) + +/** + * @brief Set SMBus Bytes number of Transmission or reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * + */ +#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize)) + +/** + * @brief Enable SMBus Alert function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger) + * + */ +#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Disable SMBus Alert pin function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger) + * + */ +#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is output mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode. + * + * + */ +#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is input mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode. + * + * + */ +#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin output high state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state. + * + */ +#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk) + + +/** + * @brief Set SMBus SUSCON pin output low state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state. + * + */ +#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk) + +/** + * @brief Enable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse. + * + */ +#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Disable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable acknowledge response control by user. + * + */ +#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Enable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * + */ +#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Disable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * + */ +#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Enable SMBus PEC clear at REPEAT START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation. + * + */ +#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Disable SMBus PEC clear at Repeat START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable the condition of Repeat START can clear the PEC calculation. + * + */ +#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Enable RX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function. + */ +#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Enable TX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function. + */ +#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function. + */ +#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function. + */ +#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Enable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared. + */ +#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Disable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C wil send STOP after PDMA transfers done automatically. + */ +#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Reset PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C PDMA engine will be reset after this function is called. + */ +#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk) + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +static __INLINE void I2C_STOP(I2C_T *i2c); + +/** + * @brief The macro is used to set STOP condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus STOP condition in I2C_CTL register. + */ +static __INLINE void I2C_STOP(I2C_T *i2c) +{ + + (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk); + while(i2c->CTL0 & I2C_CTL0_STO_Msk) {} +} + + +void I2C_ClearTimeoutFlag(I2C_T *i2c); +void I2C_Close(I2C_T *i2c); +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack); +void I2C_DisableInt(I2C_T *i2c); +void I2C_EnableInt(I2C_T *i2c); +uint32_t I2C_GetBusClockFreq(I2C_T *i2c); +uint32_t I2C_GetIntFlag(I2C_T *i2c); +uint32_t I2C_GetStatus(I2C_T *i2c); +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock); +uint8_t I2C_GetData(I2C_T *i2c); +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode); +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask); +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock); +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout); +void I2C_DisableTimeout(I2C_T *i2c); +void I2C_EnableWakeup(I2C_T *i2c); +void I2C_DisableWakeup(I2C_T *i2c); +void I2C_SetData(I2C_T *i2c, uint8_t u8Data); +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Data); +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Data[], uint32_t u32wLen); +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t u8Data); +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Data[], uint32_t u32wLen); +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t u8Data); +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Data[], uint32_t u32wLen); +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr); +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Rdata[], uint32_t u32rLen); +uint32_t I2C_SMBusGetStatus(I2C_T *i2c); +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8ClrSMBusIntFlag); +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize); +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice); +void I2C_SMBusClose(I2C_T *i2c); +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn); +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c); +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t u32Us, uint32_t u32Hclk); +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); + +/**@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group I2C_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_i2s.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_i2s.h new file mode 100644 index 0000000000..f3130bbde3 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_i2s.h @@ -0,0 +1,355 @@ +/****************************************************************************//** + * @file i2s.h + * @version V3.00 + * @brief M2354 series I2S driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __I2S_H__ +#define __I2S_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants + @{ +*/ + +#define I2S_DATABIT_8 (0UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define I2S_DATABIT_16 (1UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define I2S_DATABIT_24 (2UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define I2S_DATABIT_32 (3UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* Audio Format */ +#define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */ +#define I2S_DISABLE_MONO (0UL) /*!< Stereo channel \hideinitializer */ + +/* I2S Data Format */ +#define I2S_FORMAT_I2S (0UL << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */ +#define I2S_FORMAT_I2S_MSB (1UL << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */ +#define I2S_FORMAT_I2S_LSB (2UL << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */ +#define I2S_FORMAT_PCM (4UL << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */ +#define I2S_FORMAT_PCM_MSB (5UL << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */ +#define I2S_FORMAT_PCM_LSB (6UL << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */ + +/* I2S Data Format */ +#define I2S_ORDER_AT_MSB 0UL /*!< Channel data is at MSB \hideinitializer */ +#define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */ + +/* I2S TDM Channel Number */ +#define I2S_TDM_2CH 0UL /*!< Use TDM 2 channel \hideinitializer */ +#define I2S_TDM_4CH 1UL /*!< Use TDM 4 channel \hideinitializer */ +#define I2S_TDM_6CH 2UL /*!< Use TDM 6 channel \hideinitializer */ +#define I2S_TDM_8CH 3UL /*!< Use TDM 8 channel \hideinitializer */ + +/* I2S TDM Channel Width */ +#define I2S_TDM_WIDTH_8BIT 0UL /*!< TDM channel witch is 8-bit \hideinitializer */ +#define I2S_TDM_WIDTH_16BIT 1UL /*!< TDM channel witch is 16-bit \hideinitializer */ +#define I2S_TDM_WIDTH_24BIT 2UL /*!< TDM channel witch is 24-bit \hideinitializer */ +#define I2S_TDM_WIDTH_32BIT 3UL /*!< TDM channel witch is 32-bit \hideinitializer */ + +/* I2S TDM Sync Width */ +#define I2S_TDM_SYNC_ONE_BCLK 0UL /*!< TDM sync widht is one BLCK period \hideinitializer */ +#define I2S_TDM_SYNC_ONE_CHANNEL 1UL /*!< TDM sync widht is one channel period \hideinitializer */ + +/* I2S Operation mode */ +#define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */ +#define I2S_MODE_MASTER 0UL /*!< As master mode \hideinitializer */ + +/* I2S FIFO Threshold */ +#define I2S_FIFO_TX_LEVEL_WORD_0 0UL /*!< TX threshold is 0 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_1 (1UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_2 (2UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_3 (3UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_4 (4UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_5 (5UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_6 (6UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_7 (7UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_8 (8UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_9 (9UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_10 (10UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_11 (11UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_12 (12UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_13 (13UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_14 (14UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_15 (15UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */ + +#define I2S_FIFO_RX_LEVEL_WORD_1 0UL /*!< RX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_2 (1UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_3 (2UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_4 (3UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_5 (4UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_6 (5UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_7 (6UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_8 (7UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_9 (8UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_10 (9UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_11 (10UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_12 (11UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_13 (12UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_14 (13UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_15 (14UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_16 (15UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */ + +/* I2S Record Channel */ +#define I2S_MONO_RIGHT 0UL /*!< Record mono right channel \hideinitializer */ +#define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */ + +/* I2S Channel */ +#define I2S_RIGHT 0UL /*!< Select right channel \hideinitializer */ +#define I2S_LEFT 1UL /*!< Select left channel \hideinitializer */ + +/**@}*/ /* end of group I2S_EXPORTED_CONSTANTS */ + + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ + + +/** + * @brief Enable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0UL) && (u32ChMask < 9UL)) + { + i2s->CTL1 |= (1UL << (u32ChMask - 1UL)); + } +} + +/** + * @brief Disable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0UL) && (u32ChMask < 9UL)) + { + i2s->CTL1 &= ~(1UL << (u32ChMask - 1UL)); + } +} + +/** + * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk ) + +/** + * @brief Disable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk ) + +/** + * @brief Enable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk ) + +/** + * @brief Disable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk ) + +/** + * @brief Enable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk ) + +/** + * @brief Disable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk ) + +/** + * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk ) + +/** + * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref I2S_MONO_LEFT + * - \ref I2S_MONO_RIGHT + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch) +{ + u32Ch == I2S_MONO_LEFT ? + (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) : + (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk); +} + +/** + * @brief Write data to I2S Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Data: The data written to FIFO. + * @return none + * \hideinitializer + */ +#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) ) + +/** + * @brief Read Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return Data in Rx FIFO. + * \hideinitializer + */ +#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO ) + +/** + * @brief This function gets the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) ) + +/** + * @brief This function clears the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) ) + +/** + * @brief This function gets the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) ) + +/** + * @brief This function clears the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF ) + +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat); +void I2S_Close(I2S_T *i2s); +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask); +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask); +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock); +void I2S_DisableMCLK(I2S_T *i2s); +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth); + + +/**@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group I2S_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2S_H__ */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_keystore.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_keystore.h new file mode 100644 index 0000000000..a0401a00dc --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_keystore.h @@ -0,0 +1,133 @@ +/**************************************************************************//** + * @file keystore.h + * @version V3.00 + * @brief Key Store Driver Header + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __KEYSTORE_H__ +#define __KEYSTORE_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup KS_Driver Key Store Driver + @{ +*/ + +/** @addtogroup KS_EXPORTED_CONSTANTS Key Store Exported Constants + @{ +*/ + +#define KS_TOMETAKEY(x) (((uint32_t)(x) << KS_METADATA_NUMBER_Pos) & KS_METADATA_NUMBER_Msk) +#define KS_TOKEYIDX(x) (((uint32_t)(x) & KS_METADATA_NUMBER_Msk) >> KS_METADATA_NUMBER_Pos) + +typedef enum KSMEM +{ + KS_SRAM = 0, /*!< Volatile Memory */ + KS_FLASH = 1, /*!< Non-volatile Memory */ + KS_OTP = 2 /*!< One-Time Programming Memory */ +}KS_MEM_Type; + +#define KS_OP_READ (0 << KS_CTL_OPMODE_Pos) +#define KS_OP_WRITE (1 << KS_CTL_OPMODE_Pos) +#define KS_OP_ERASE (2 << KS_CTL_OPMODE_Pos) +#define KS_OP_ERASE_ALL (3 << KS_CTL_OPMODE_Pos) +#define KS_OP_REVOKE (4 << KS_CTL_OPMODE_Pos) +#define KS_OP_REMAN (5 << KS_CTL_OPMODE_Pos) + +#define KS_OWNER_AES (0ul) +#define KS_OWNER_HMAC (1ul) +#define KS_OWNER_RSA_EXP (2ul) +#define KS_OWNER_RSA_MID (3ul) +#define KS_OWNER_ECC (4ul) +#define KS_OWNER_CPU (5ul) + +#define KS_META_AES (0ul << KS_METADATA_OWNER_Pos) /*!< AES Access Only */ +#define KS_META_HMAC (1ul << KS_METADATA_OWNER_Pos) /*!< HMAC Access Only */ +#define KS_META_RSA_EXP (2ul << KS_METADATA_OWNER_Pos) /*!< RSA_EXP Access Only */ +#define KS_META_RSA_MID (3ul << KS_METADATA_OWNER_Pos) /*!< RSA_MID Access Only */ +#define KS_META_ECC (4ul << KS_METADATA_OWNER_Pos) /*!< ECC Access Only */ +#define KS_META_CPU (5ul << KS_METADATA_OWNER_Pos) /*!< CPU Access Only */ + +#define KS_META_128 ( 0ul << KS_METADATA_SIZE_Pos) /*!< Key size 128 bits */ +#define KS_META_163 ( 1ul << KS_METADATA_SIZE_Pos) /*!< Key size 163 bits */ +#define KS_META_192 ( 2ul << KS_METADATA_SIZE_Pos) /*!< Key size 192 bits */ +#define KS_META_224 ( 3ul << KS_METADATA_SIZE_Pos) /*!< Key size 224 bits */ +#define KS_META_233 ( 4ul << KS_METADATA_SIZE_Pos) /*!< Key size 233 bits */ +#define KS_META_255 ( 5ul << KS_METADATA_SIZE_Pos) /*!< Key size 255 bits */ +#define KS_META_256 ( 6ul << KS_METADATA_SIZE_Pos) /*!< Key size 256 bits */ +#define KS_META_283 ( 7ul << KS_METADATA_SIZE_Pos) /*!< Key size 283 bits */ +#define KS_META_384 ( 8ul << KS_METADATA_SIZE_Pos) /*!< Key size 384 bits */ +#define KS_META_409 ( 9ul << KS_METADATA_SIZE_Pos) /*!< Key size 409 bits */ +#define KS_META_512 (10ul << KS_METADATA_SIZE_Pos) /*!< Key size 512 bits */ +#define KS_META_521 (11ul << KS_METADATA_SIZE_Pos) /*!< Key size 521 bits */ +#define KS_META_571 (12ul << KS_METADATA_SIZE_Pos) /*!< Key size 571 bits */ +#define KS_META_1024 (16ul << KS_METADATA_SIZE_Pos) /*!< Key size 1024 bits */ +#define KS_META_1536 (17ul << KS_METADATA_SIZE_Pos) /*!< Key size 1024 bits */ +#define KS_META_2048 (18ul << KS_METADATA_SIZE_Pos) /*!< Key size 2048 bits */ +#define KS_META_3072 (19ul << KS_METADATA_SIZE_Pos) /*!< Key size 1024 bits */ +#define KS_META_4096 (20ul << KS_METADATA_SIZE_Pos) /*!< Key size 4096 bits */ + +#define KS_META_BOOT ( 1ul << KS_METADATA_BS_Pos) /*!< Key only used for boot ROM only */ + +#define KS_META_READABLE (1ul << KS_METADATA_READABLE_Pos) /*!< Allow the key to be read by software */ + +#define KS_META_PRIV (1ul << KS_METADATA_PRIV_Pos) /*!< Privilege key */ +#define KS_META_NONPRIV (0ul << KS_METADATA_PRIV_Pos) /*!< Non-privilege key */ + +#define KS_META_SECURE (1ul << KS_METADATA_SEC_Pos) /*!< Secure key */ +#define KS_META_NONSECURE (0ul << KS_METADATA_SEC_Pos) /*!< Non-secure key */ + + +/** + * @brief Enable scramble function + * @details This function is used to enable scramle function of Key Store. + */ + +#define KS_SCRAMBLING() KS->CTL |= KS_CTL_SCMB_Msk + + + + +/**@}*/ /* end of group KS_EXPORTED_CONSTANTS */ + + +/** @addtogroup KS_EXPORTED_FUNCTIONS Key Store Exported Functions + @{ +*/ + +void KS_Open(void); +int32_t KS_Read(KS_MEM_Type type, int32_t i32KeyIdx, uint32_t au32Key[], uint32_t u32WordCnt); +int32_t KS_Write(KS_MEM_Type eType, uint32_t u32Meta, uint32_t au32Key[]); +int32_t KS_WriteOTP(int32_t i32KeyIdx, uint32_t u32Meta, uint32_t au32Key[]); +int32_t KS_EraseKey(int32_t i32KeyIdx); +int32_t KS_EraseAll(KS_MEM_Type eType); +int32_t KS_RevokeKey(KS_MEM_Type eType, int32_t i32KeyIdx); +uint32_t KS_GetRemainSize(KS_MEM_Type eType); +int32_t KS_ToggleSRAM(void); +uint32_t KS_GetKeyWordCnt(uint32_t u32Meta); +uint32_t KS_GetRemainKeyCount(KS_MEM_Type mem); + +/**@}*/ /* end of group KS_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group KS_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __KEYSTORE_H__ */ + + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_lcd.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_lcd.h new file mode 100644 index 0000000000..8323e2ba78 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_lcd.h @@ -0,0 +1,516 @@ +/**************************************************************************//** + * @file lcd.h + * @version V3.00 + * @brief Liquid-Crystal Display(LCD) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __LCD_H__ +#define __LCD_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup LCD_Driver LCD Driver + @{ +*/ + +/** @addtogroup LCD_EXPORTED_CONSTANTS LCD Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Bias Voltage Level Selection Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_BIAS_LV_1_2 (1ul << LCD_PCTL_BIAS_Pos) /*!< LCD bias voltage level selection - 1/2 Bias \hideinitializer */ +#define LCD_BIAS_LV_1_3 (2ul << LCD_PCTL_BIAS_Pos) /*!< LCD bias voltage level selection - 1/3 Bias \hideinitializer */ +#define LCD_BIAS_LV_1_4 (3ul << LCD_PCTL_BIAS_Pos) /*!< LCD bias voltage level selection - 1/4 Bias \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD COM Duty Ratio Selection Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_COM_DUTY_1_1 (0ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/1 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_2 (1ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/2 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_3 (2ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/3 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_4 (3ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/4 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_5 (4ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/5 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_6 (5ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/6 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_7 (6ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/7 Duty \hideinitializer */ +#define LCD_COM_DUTY_1_8 (7ul << LCD_PCTL_DUTY_Pos) /*!< LCD com duty ratio selection - 1/8 Duty \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Waveform Attribute Selection Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_WAVEFORM_TYPE_A_NORMAL (0ul << LCD_PCTL_TYPE_Pos) /*!< LCD waveform Type-A, no inverse \hideinitializer */ +#define LCD_WAVEFORM_TYPE_B_NORMAL (1ul << LCD_PCTL_TYPE_Pos) /*!< LCD waveform Type-B, no inverse \hideinitializer */ +#define LCD_WAVEFORM_TYPE_A_INVERSE (2ul << LCD_PCTL_TYPE_Pos) /*!< LCD waveform Type-A and inverse \hideinitializer */ +#define LCD_WAVEFORM_TYPE_B_INVERSE (3ul << LCD_PCTL_TYPE_Pos) /*!< LCD waveform Type-B and inverse \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Charge Pump Voltage Selection Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_CP_VOLTAGE_LV_0 (0ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 2.6 V \hideinitializer */ +#define LCD_CP_VOLTAGE_LV_1 (1ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 2.8 V \hideinitializer */ +#define LCD_CP_VOLTAGE_LV_2 (2ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 3.0 V \hideinitializer */ +#define LCD_CP_VOLTAGE_LV_3 (3ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 3.2 V \hideinitializer */ +#define LCD_CP_VOLTAGE_LV_4 (4ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 3.4 V \hideinitializer */ +#define LCD_CP_VOLTAGE_LV_5 (5ul << LCD_PCTL_CPVSEL_Pos) /*!< Select LCD charge pump voltage 3.6 V \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Interrupt Source Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_DISABLE_ALL_INT (0ul << LCD_INTEN_FCEIEN_Pos) /*!< Disable all LCD interrupt sources \hideinitializer */ +#define LCD_FRAME_COUNTING_END_INT (1ul << LCD_INTEN_FCEIEN_Pos) /*!< Indicate frame count end interrupt \hideinitializer */ +#define LCD_FRAME_END_INT (1ul << LCD_INTEN_FEIEN_Pos) /*!< Indicate frame end interrupt \hideinitializer */ +#define LCD_CPTOUT_INT (1ul << LCD_INTEN_CTOIEN_Pos) /*!< Indicate charge pump charging timeout interrupt \hideinitializer */ +#define LCD_ENABLE_ALL_INT (7ul << LCD_INTEN_FCEIEN_Pos) /*!< Enable all LCD interrupt sources \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Operation Voltage Source Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_VOLTAGE_SOURCE_VLCD (0ul << LCD_DCTL_VSRC_Pos) /*!< LCD voltage source from external VLCD power \hideinitializer */ +#define LCD_VOLTAGE_SOURCE_AVDD (1ul << LCD_DCTL_VSRC_Pos) /*!< LCD voltage source from internal VDD \hideinitializer */ +#define LCD_VOLTAGE_SOURCE_CP (2ul << LCD_DCTL_VSRC_Pos) /*!< LCD voltage source from built-in charge pump \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Driving Mode Selection Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_LOW_DRIVING_AND_BUF_OFF (0ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with low-drive and voltage buffer disabled \hideinitializer */ +#define LCD_HIGH_DRIVING_AND_BUF_OFF (1ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with high-drive and voltage buffer disabled \hideinitializer */ +#define LCD_LOW_DRIVING_AND_BUF_ON (2ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with low-drive and voltage buffer enabled \hideinitializer */ +#define LCD_HIGH_DRIVING_AND_BUF_OFF_AND_PWR_SAVING (5ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with high-drive, voltage buffer disabled and power saving \hideinitializer */ +#define LCD_LOW_DRIVING_AND_BUF_ON_AND_PWR_SAVING (6ul << LCD_DCTL_RESMODE_Pos) /*!< LCD operates with low-drive, voltage buffer enabled and power saving \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* LCD Power Saving Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define LCD_PWR_SAVING_NORMAL_MODE (0ul << LCD_DCTL_PSVREV_Pos) /*!< The timing of LCD power saving is normal \hideinitializer */ +#define LCD_PWR_SAVING_REVERSE_MODE (1ul << LCD_DCTL_PSVREV_Pos) /*!< The timing of LCD power saving is reverse \hideinitializer */ + +/**@}*/ /* end of group LCD_EXPORTED_CONSTANTS */ + + +/** @addtogroup LCD_EXPORTED_STRUCTS LCD Exported Structs + @{ +*/ +/** + * @details LCD Configuration Data Struct + */ +typedef struct +{ + uint32_t u32SrcFreq; /*!< LCD clock source frequency */ + uint32_t u32ComDuty; /*!< COM duty */ + uint32_t u32BiasLevel; /*!< Bias level */ + uint32_t u32Framerate; /*!< Operation frame rate */ + uint32_t u32WaveformType; /*!< Waveform type */ + uint32_t u32IntSrc; /*!< Interrupt source */ + uint32_t u32DrivingMode; /*!< Driving mode */ + uint32_t u32VSrc; /*!< Voltage source */ +} S_LCD_CFG_T; + +/**@}*/ /* end of group LCD_EXPORTED_STRUCTS */ + + +/** @addtogroup LCD_EXPORTED_FUNCTIONS LCD Exported Functions + @{ +*/ + +/** + * @brief Enable LCD Display + * + * @param None + * + * @return None + * + * @details This macro is used to enable LCD display. + */ +#define LCD_ENABLE_DISPLAY() do{ LCD->CTL |= LCD_CTL_EN_Msk; while(LCD->CTL & LCD_CTL_SYNC_Msk) {} }while(0) + +/** + * @brief Disable LCD Display + * + * @param None + * + * @return None + * + * @details This macro is used to disable LCD display. + */ +#define LCD_DISABLE_DISPLAY() do{ LCD->CTL &= ~LCD_CTL_EN_Msk; while(LCD->CTL & LCD_CTL_SYNC_Msk) {} }while(0) + +/** + * @brief Set LCD Waveform Type + * + * @param[in] type The LCD waveform type. It could be one of the following type + * - \ref LCD_WAVEFORM_TYPE_A_NORMAL + * - \ref LCD_WAVEFORM_TYPE_B_NORMAL + * - \ref LCD_WAVEFORM_TYPE_A_INVERSE + * - \ref LCD_WAVEFORM_TYPE_B_INVERSE + * + * @return None + * + * @details This macro is used to set the attribute of LCD output waveform. + */ +#define LCD_WAVEFORM_TYPE(type) (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_TYPE_Msk) | (type)) + +/** + * @brief Set LCD Source Clock Divider + * + * @param[in] div The frequency divider, valid value is between 1 to 1024. + * + * @return None + * + * @details This macro is used to set the LCD operarion frequency is (LCD source frequency / div). + */ +#define LCD_SET_FREQDIV(div) (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_FREQDIV_Msk) | (((div)-1) << LCD_PCTL_FREQDIV_Pos)) + +/** + * @brief Increase Charge Pump Voltage + * + * @param[in] unit The tuning units, valid value is between 0 to 7. + * One unit of voltage is about 0.03V, and the charge pump voltage is increased (unit * 0.03)V. + * + * @return None + * + * @details This macro is used to increase charge pump voltage by specific units. + */ +#define LCD_CP_VOLTAGE_INCREASE(unit) (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_CPVTUNE_Msk) | ((unit) << LCD_PCTL_CPVTUNE_Pos)) + +/** + * @brief Decrease Charge Pump Voltage + * + * @param[in] unit The tuning units, valid value is between 1 to 8. + * One unit of voltage is about 0.03V, and the charge pump voltage is decreased (unit * 0.03)V. + * + * @return None + * + * @details This macro is used to decrease charge pump voltage by specific units. + */ +#define LCD_CP_VOLTAGE_DECREASE(unit) (LCD->PCTL = (LCD->PCTL & ~LCD_PCTL_CPVTUNE_Msk) | ((16-(unit)) << LCD_PCTL_CPVTUNE_Pos)) + +/** + * @brief Set LCD Blinking ON + * + * @param None + * + * @return None + * + * @details This macro is used to enable LCD blinking. + */ +#define LCD_BLINKING_ON() (LCD->FCTL |= LCD_FCTL_BLINK_Msk) + +/** + * @brief Set LCD Blinking OFF + * + * @param None + * + * @return None + * + * @details This macro is used to disable LCD blinking. + */ +#define LCD_BLINKING_OFF() (LCD->FCTL &= ~LCD_FCTL_BLINK_Msk) + +/** + * @brief Set LCD Frame Counting Value + * + * @param[in] value Frame counting value. Valid value is between 1 to 1024. + * + * @return None + * + * @details This macro is used to set the LCD frame counting value to configure the blink interval. + * @note For type-B waveform, the frame counter increases at the end of odd frames, not even frames. + */ +#define LCD_SET_FRAME_COUNTING_VALUE(value) (LCD->FCTL = (LCD->FCTL & ~LCD_FCTL_FCV_Msk) | (((value)-1) << LCD_FCTL_FCV_Pos)) + +/** + * @brief Set Null Frame Time + * + * @param[in] unit The unit parameter is used to determine the null frame time, valid value is between 0 to 15. + * And one unit time is one LCD operation clock period. + * + * @return None + * + * @details This macro is used to set the one null frame time. + * @note All COM and SEG output voltages will keep at 0V during a null frame. + */ +#define LCD_SET_NULL_FRAME_TIME(unit) (LCD->FCTL = (LCD->FCTL & ~LCD_FCTL_NFTIME_Msk) | ((unit) << LCD_FCTL_NFTIME_Pos)) + +/** + * @brief Set Continuous Frames + * + * @param[in] frame The continuous frames, valid setting is between 1 to 16 frames. + * + * @return None + * + * @details This macro is used to specify the number of continuous frames reached to insert one null frame. + */ +#define LCD_SET_CONTINUOUS_FRAME(frame) (LCD->FCTL = (LCD->FCTL & ~LCD_FCTL_NFNUM_Msk) | (((frame)-1) << LCD_FCTL_NFNUM_Pos)) + +/** + * @brief Select LCD Voltage Source + * + * @param[in] mode The LCD operation voltage source. It could be one of the following source + * - \ref LCD_VOLTAGE_SOURCE_VLCD + * - \ref LCD_VOLTAGE_SOURCE_AVDD + * - \ref LCD_VOLTAGE_SOURCE_CP + * + * @return None + * + * @details This macro is used to select LCD operation voltage source. + */ +#define LCD_VOLTAGE_SOURCE(source) (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_VSRC_Msk) | (source)) + +/** + * @brief Set LCD Driving Mode + * + * @param[in] mode The LCD operation driving mode. It could be one of the following mode + * - \ref LCD_LOW_DRIVING_AND_BUF_OFF + * - \ref LCD_HIGH_DRIVING_AND_BUF_OFF + * - \ref LCD_LOW_DRIVING_AND_BUF_ON + * - \ref LCD_HIGH_DRIVING_AND_BUF_OFF_AND_PWR_SAVING + * - \ref LCD_LOW_DRIVING_AND_BUF_ON_AND_PWR_SAVING + * + * @return None + * + * @details This macro is used to set LCD operation drivig mode. + */ +#define LCD_DRIVING_MODE(mode) (LCD->DCTL = (LCD->DCTL & ~(LCD_DCTL_RESMODE_Msk | LCD_DCTL_BUFEN_Msk | LCD_DCTL_PSVEN_Msk)) | (mode)) + +/** + * @brief Select Power Saving Mode + * + * @param[in] mode The LCD power saving mode selection. It could be one of the following constant definition + * - \ref LCD_PWR_SAVING_NORMAL_MODE + * - \ref LCD_PWR_SAVING_REVERSE_MODE + * + * @return None + * + * @details This macro is used to set the LCD power saving mode. + * When the timing of power saving mode is reversed, the original power saving period becomes no power saving, + * and the original no power saving period becomes power saving. + */ +#define LCD_PWR_SAVING_MODE(mode) (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_PSVREV_Msk) | (mode)) + +/** + * @brief Set Power Saving T1 Period + * + * @param[in] t1 The number of t1 to determine T1 period, valid value is between 1 to 16. + * And one unit of t1 period is half of LCD operation clock period. + * + * @return None + * + * @details This macro is used to configure the T1 (Enable Time) period of power saving. + */ +#define LCD_PWR_SAVING_T1_PERIOD(t1) (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_PSVT1_Msk) | (((t1)-1) << LCD_DCTL_PSVT1_Pos)) + +/** + * @brief Set Power Saving T2 Period + * + * @param[in] t2 The number of t2 to determine T2 period, valid value is between 1 to 16. + * And one unit of t1 period is half of LCD operation clock period. + * + * @return None + * + * @details This macro is used to configure the T2 (On Time) period of power saving. + */ +#define LCD_PWR_SAVING_T2_PERIOD(t2) (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_PSVT2_Msk) | (((t2)-1) << LCD_DCTL_PSVT2_Pos)) + +/** + * @brief Set Charging Timeout Time + * + * @param[in] value The maximum timeout value, valid value is between 1 to 8192. + * And one unit of timeout value is one LCD operation clock period. + * + * @return None + * + * @details This macro is used to set maximum timeout time of charge pump charging timer. + */ +#define LCD_SET_CHARGE_TIMEOUT_TIME(value) (LCD->DCTL = (LCD->DCTL & ~LCD_DCTL_CTOTIME_Msk) | (((value)-1) << LCD_DCTL_CTOTIME_Pos)) + +/** + * @brief Select Device Package Type + * + * @param[in] pak Select device package type. + * 0 for 128-pin package, and 1 for 64-pin package. + * + * @return None + * + * @details This macro is used to select device output pins for LCD controller with different package type. + */ +#define LCD_SELECT_PACKAGE_TYPE(pkg) (LCD->PKGSEL = (LCD->PKGSEL & ~LCD_PKGSEL_PKG_Msk) | ((pkg) << LCD_PKGSEL_PKG_Pos)) + +/** + * @brief Enable LCD Frame Counting End Interrupt + * + * @param None + * + * @return None + * + * @details This macro is used to enable frame count end interrupt function. + */ +#define LCD_ENABLE_FRAME_COUNTING_END_INT() (LCD->INTEN |= LCD_INTEN_FCEIEN_Msk) + +/** + * @brief Disable LCD Frame Counting End Interrupt + * + * @param None + * + * @return None + * + * @details This macro is used to disable frame count end interrupt function. + */ +#define LCD_DISABLE_FRAME_COUNTING_END_INT() (LCD->INTEN &= ~LCD_INTEN_FCEIEN_Msk) + +/** + * @brief Enable LCD Frame End Interrupt + * + * @param None + * + * @return None + * + * @details This macro is used to enable frame end interrupt function. + */ +#define LCD_ENABLE_FRAME_END_INT() (LCD->INTEN |= LCD_INTEN_FEIEN_Msk) + +/** + * @brief Disable LCD Frame End Interrupt + * + * @param None + * + * @return None + * + * @details This macro is used to disable frame end interrupt function. + */ +#define LCD_DISABLE_FRAME_END_INT() (LCD->INTEN &= ~LCD_INTEN_FEIEN_Msk) + +/** + * @brief Enable Charging Timeout Interrupt + * + * @param None + * + * @return None + * + * @details This macro is used to enable charge pump charging timeout interrupt function. + */ +#define LCD_ENABLE_CHARGE_TIMEOUT_INT() (LCD->INTEN |= LCD_INTEN_CTOIEN_Msk) + +/** + * @brief Disable Charging Timeout Interrupt + * + * @param None + * + * @return None + * + * @details This macro is used to disable charge pump charging timeout interrupt function. + */ +#define LCD_DISABLE_CHARGE_TIMEOUT_INT() (LCD->INTEN &= ~LCD_INTEN_CTOIEN_Msk) + +/** + * @brief Get LCD Frame Counting End Flag + * + * @param None + * + * @retval 0 Frame count end flag did not occur + * @retval 1 Frame count end flag occurred + * + * @details This macro gets frame count end flag. + */ +#define LCD_GET_FRAME_COUNTING_END_FLAG() ((LCD->STS & LCD_STS_FCEF_Msk)? 1UL : 0UL) + +/** + * @brief Clear LCD Frame Counting End Flag + * + * @param None + * + * @return None + * + * @details This macro clears frame count end flag. + */ +#define LCD_CLEAR_FRAME_COUNTING_END_FLAG() (LCD->STS = LCD_STS_FCEF_Msk) + +/** + * @brief Get LCD Frame End Flag + * + * @param None + * + * @retval 0 Frame end flag did not occur + * @retval 1 Frame end flag occurred + * + * @details This macro gets frame end flag. + */ +#define LCD_GET_FRAME_END_FLAG() ((LCD->STS & LCD_STS_FEF_Msk)? 1UL : 0UL) + +/** + * @brief Clear LCD Frame End Flag + * + * @param None + * + * @return None + * + * @details This macro clears frame end flag. + */ +#define LCD_CLEAR_FRAME_END_FLAG() (LCD->STS = LCD_STS_FEF_Msk) + +/** + * @brief Get Charging Timeout Flag + * + * @param None + * + * @retval 0 Charge pump timer timeout flag did not occur + * @retval 1 Charge pump timer timeout flag occurred + * + * @details This macro gets charge pump charging timeout flag. + */ +#define LCD_GET_CHARGE_TIMEOUT_FLAG() ((LCD->STS & LCD_STS_CTOF_Msk)? 1UL : 0UL) + +/** + * @brief Clear Charging Timeout Flag + * + * @param None + * + * @return None + * + * @details This macro clears charge pump charging timeout flag. + */ +#define LCD_CLEAR_CHARGE_TIMEOUT_FLAG() (LCD->STS = LCD_STS_CTOF_Msk) + +/** + * @brief Get Charging Time + * + * @param None + * + * @return Current 13-bit charging timer value + * + * @details This macro gets charging timer value while stops charge pump charging. + */ +#define LCD_GET_CHARGE_TIME() ((LCD->STS & LCD_STS_CTIME_Msk) >> 16) + + +uint32_t LCD_Open(S_LCD_CFG_T *pLCDCfg); +void LCD_Close(void); +void LCD_SetPixel(uint32_t u32Com, uint32_t u32Seg, uint32_t u32OnFlag); +void LCD_SetAllPixels(uint32_t u32OnOff); +uint32_t LCD_EnableBlink(uint32_t u32ms); +void LCD_DisableBlink(void); +void LCD_EnableInt(uint32_t u32IntSrc); +void LCD_DisableInt(uint32_t u32IntSrc); + +/**@}*/ /* end of group LCD_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group LCD_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __LCD_H__ */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_otg.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_otg.h new file mode 100644 index 0000000000..dbc979d4c7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_otg.h @@ -0,0 +1,257 @@ +/**************************************************************************//** + * @file otg.h + * @version V3.00 + * @brief M2354 series OTG driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __OTG_H__ +#define __OTG_H__ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Include related headers */ +/*---------------------------------------------------------------------------------------------------------*/ +#include "M2354.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup OTG_Driver OTG Driver + @{ +*/ + + +/** @addtogroup OTG_EXPORTED_CONSTANTS OTG Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* OTG constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define OTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. */ +#define OTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. */ +#define OTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. */ +#define OTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. */ + + +/**@}*/ /* end of group OTG_EXPORTED_CONSTANTS */ + + +/** @addtogroup OTG_EXPORTED_FUNCTIONS OTG Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable OTG function + * @param None + * @return None + * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function. + */ +#define OTG_ENABLE() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL |= OTG_CTL_OTGEN_Msk):(OTG->CTL |= OTG_CTL_OTGEN_Msk)) + +/** + * @brief This macro is used to disable OTG function + * @param None + * @return None + * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function. + */ +#define OTG_DISABLE() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL &= ~OTG_CTL_OTGEN_Msk):(OTG->CTL &= ~OTG_CTL_OTGEN_Msk)) + +/** + * @brief This macro is used to enable USB PHY + * @param None + * @return None + * @details When the USB role is selected as OTG device, use this macro to enable USB PHY. + * This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY. + */ +#define OTG_ENABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk):(OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)) + +/** + * @brief This macro is used to disable USB PHY + * @param None + * @return None + * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY. + */ +#define OTG_DISABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk):(OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)) + +/** + * @brief This macro is used to enable ID detection function + * @param None + * @return None + * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function. + */ +#define OTG_ENABLE_ID_DETECT() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk):(OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)) + +/** + * @brief This macro is used to disable ID detection function + * @param None + * @return None + * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function. + */ +#define OTG_DISABLE_ID_DETECT() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk):(OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)) + +/** + * @brief This macro is used to enable OTG wake-up function + * @param None + * @return None + * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function. + */ +#define OTG_ENABLE_WAKEUP() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL |= OTG_CTL_WKEN_Msk):(OTG->CTL |= OTG_CTL_WKEN_Msk)) + +/** + * @brief This macro is used to disable OTG wake-up function + * @param None + * @return None + * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function. + */ +#define OTG_DISABLE_WAKEUP() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL &= ~OTG_CTL_WKEN_Msk):(OTG->CTL &= ~OTG_CTL_WKEN_Msk)) + +/** + * @brief This macro is used to set the polarity of USB_VBUS_EN pin + * @param[in] u32Pol The polarity selection. Valid values are listed below. + * - \ref OTG_VBUS_EN_ACTIVE_HIGH + * - \ref OTG_VBUS_EN_ACTIVE_LOW + * @return None + * @details This macro is used to set the polarity of external USB VBUS power switch enable signal. + */ +#define OTG_SET_VBUS_EN_POL(u32Pol) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<INTEN |= (u32Mask)):(OTG->INTEN |= (u32Mask))) + +/** + * @brief This macro is used to disable OTG related interrupts + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTEN_ROLECHGIEN_Msk + * - \ref OTG_INTEN_VBEIEN_Msk + * - \ref OTG_INTEN_SRPFIEN_Msk + * - \ref OTG_INTEN_HNPFIEN_Msk + * - \ref OTG_INTEN_GOIDLEIEN_Msk + * - \ref OTG_INTEN_IDCHGIEN_Msk + * - \ref OTG_INTEN_PDEVIEN_Msk + * - \ref OTG_INTEN_HOSTIEN_Msk + * - \ref OTG_INTEN_BVLDCHGIEN_Msk + * - \ref OTG_INTEN_AVLDCHGIEN_Msk + * - \ref OTG_INTEN_VBCHGIEN_Msk + * - \ref OTG_INTEN_SECHGIEN_Msk + * - \ref OTG_INTEN_SRPDETIEN_Msk + * @return None + * @details This macro will disable OTG related interrupts specified by u32Mask parameter. + */ +#define OTG_DISABLE_INT(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTEN &= ~(u32Mask)):(OTG->INTEN &= ~(u32Mask))) + +/** + * @brief This macro is used to get OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return Interrupt flags of selected sources. + * @details This macro will return OTG related interrupt flags specified by u32Mask parameter. + */ +#define OTG_GET_INT_FLAG(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTSTS & (u32Mask)):(OTG->INTSTS & (u32Mask))) + +/** + * @brief This macro is used to clear OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return None + * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter. + */ +#define OTG_CLR_INT_FLAG(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTSTS = (u32Mask)):(OTG->INTSTS = (u32Mask))) + +/** + * @brief This macro is used to get OTG related status + * @param[in] u32Mask The combination of user specified source. Valid values are listed below. + * - \ref OTG_STATUS_OVERCUR_Msk + * - \ref OTG_STATUS_IDSTS_Msk + * - \ref OTG_STATUS_SESSEND_Msk + * - \ref OTG_STATUS_BVLD_Msk + * - \ref OTG_STATUS_AVLD_Msk + * - \ref OTG_STATUS_VBUSVLD_Msk + * @return The user specified status. + * @details This macro will return OTG related status specified by u32Mask parameter. + */ +#define OTG_GET_STATUS(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->STATUS & (u32Mask)):(OTG->STATUS & (u32Mask))) + + + +/**@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group OTG_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __OTG_H__ */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_pdma.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_pdma.h new file mode 100644 index 0000000000..01e2ca4577 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_pdma.h @@ -0,0 +1,383 @@ +/**************************************************************************//** + * @file pdma.h + * @version V3.00 + * @brief M2354 series PDMA driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_H__ +#define __PDMA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + +/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants + @{ +*/ +#define PDMA_CH_MAX 8UL /*!< Specify Maximum Channels of PDMA \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Operation Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_OP_STOP 0x00000000UL /*!INTSTS)) + +/** + * @brief Get Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the transfer done Interrupt status. + */ +#define PDMA_GET_TD_STS(pdma) ((uint32_t)((pdma)->TDSTS)) + +/** + * @brief Clear Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the transfer done Interrupt status. + */ +#define PDMA_CLR_TD_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->TDSTS = (u32Mask))) + +/** + * @brief Get Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the target abort Interrupt status. + */ +#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)((pdma)->ABTSTS)) + +/** + * @brief Clear Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the target abort Interrupt status. + */ +#define PDMA_CLR_ABORT_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ABTSTS = (u32Mask))) + +/** + * @brief Get PDMA Transfer Alignment Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the PDMA transfer alignment status. + */ +#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)((pdma)->ALIGN)) + +/** + * @brief Clear PDMA Transfer Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the PDMA transfer alignment Interrupt status. + */ +#define PDMA_CLR_ALIGN_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ALIGN = (u32Mask))) + +/** + * @brief Clear Timeout Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details Clear the selected channel timeout interrupt status. + * @note This function is only supported in channel 0 and channel 1. + */ +#define PDMA_CLR_TMOUT_FLAG(pdma, u32Ch) ((uint32_t)((pdma)->INTSTS = (1UL << ((u32Ch) + 8UL)))) + +/** + * @brief Check Channel Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @retval 0 Idle state + * @retval 1 Busy state + * + * @details Check the selected channel is busy or not. + */ +#define PDMA_IS_CH_BUSY(pdma, u32Ch) ((uint32_t)((pdma)->TRGSTS & (1UL << (u32Ch)))? 1 : 0) + +/** + * @brief Set Source Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel source address. + */ +#define PDMA_SET_SRC_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].SA = (u32Addr))) + +/** + * @brief Set Destination Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel destination address. + */ +#define PDMA_SET_DST_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].DA = (u32Addr))) + +/** + * @brief Set Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32TransCount Transfer Count + * + * @return None + * + * @details This macro set the selected channel transfer count. + */ +#define PDMA_SET_TRANS_CNT(pdma, u32Ch, u32TransCount) ((uint32_t)((pdma)->DSCT[(u32Ch)].CTL=((pdma)->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1UL) << PDMA_DSCT_CTL_TXCNT_Pos))) + +/** + * @brief Set Scatter-gather descriptor Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The descriptor address + * + * @return None + * + * @details This macro set the selected channel scatter-gather descriptor address. + */ +#define PDMA_SET_SCATTER_DESC(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].NEXT = (u32Addr) - ((pdma)->SCATBA))) + +/** + * @brief Stop the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro stop the selected channel. + */ +#define PDMA_STOP(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) + +/** + * @brief Pause the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro pause the selected channel. + */ +#define PDMA_PAUSE(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) + +/** + * @brief Reset the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro reset the selected channel. + */ +#define PDMA_RESET(pdma, u32Ch) ((uint32_t)((pdma)->CHRST = (1UL << (u32Ch)))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define PWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_Close(PDMA_T *pdma); +void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); +void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount); +void PDMA_SetRepeat(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount); +void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); +void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr); +void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize); +void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); +void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch); +void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); +void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); + + +/**@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group PDMA_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PDMA_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_plm.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_plm.h new file mode 100644 index 0000000000..37c5ba2287 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_plm.h @@ -0,0 +1,97 @@ +/**************************************************************************//** + * @file plm.h + * @version V3.00 + * @brief Product life cycle management + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PLM_H__ +#define __PLM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PLM_Driver PLM Driver + @{ +*/ + +/** @addtogroup PLM_EXPORTED_CONSTANTS PLM Exported Constants + @{ +*/ + +typedef enum +{ + PLM_VENDOR = 0, + PLM_OEM = 1, + PLM_DEPLOYED = 3, + PLM_RMA = 7 +}PLM_STAGE_T; + +#define PLM_VCODE (0x475A0000ul) /*!< The key code for PLM_CTL write. */ + +/**@}*/ /* end of group FVC_EXPORTED_CONSTANTS */ + + +/** @addtogroup FVC_EXPORTED_FUNCTIONS FVC Exported Functions + @{ +*/ + + +/** + * @brief Get product life-cycle stage + * @return Current stage of PLM + * @details This function is used to Get PLM stage. + */ +#define PLM_GetStage() (PLM->STS & PLM_STS_STAGE_Msk) + + +/** + * @brief Set product life-cycle stage + * @param[in] stage Product life-cycle stage. It could be: + * \ref PLM_VENDOR + * \ref PLM_OEM + * \ref PLM_DEPLOYED + * \ref PLM_RMA + * @retval 0 Successful + * @retval -1 Failed + * @details This function is used to set PLM stage. It could be only be VENDOR, OEM, DEPLOYED and RMA. + * The setting of PLM cannot be rollback. + */ +__STATIC_INLINE int32_t PLM_SetStage(PLM_STAGE_T stage) +{ + + /* Do nothing when stage is not changed */ + if(PLM_GetStage() == stage) + return 0; + + PLM->CTL = PLM_VCODE | (stage); + + /* The dirty flag should be set when PLM stage set successfully. */ + if(PLM->STS & PLM_STS_DIRTY_Msk) + return -1; + + return 0; +} + +/**@}*/ /* end of group PLM_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group PLM_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PLM_H__ */ + + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_qei.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_qei.h new file mode 100644 index 0000000000..fb978e7e53 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_qei.h @@ -0,0 +1,391 @@ +/**************************************************************************//** + * @file qei.h + * @version V3.00 + * @brief Quadrature Encoder Interface (QEI) driver header file + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __QEI_H__ +#define __QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QEI_Driver QEI Driver + @{ +*/ + +/** @addtogroup QEI_EXPORTED_CONSTANTS QEI Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* QEI counting mode selection constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define QEI_CTL_X4_FREE_COUNTING_MODE (0x0<CTL &= (~QEI_CTL_CMPEN_Msk)) + +/** + * @brief Enable QEI compare function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI counter compare function. + * \hideinitializer + */ +#define QEI_ENABLE_CNT_CMP(qei) ((qei)->CTL |= QEI_CTL_CMPEN_Msk) + +/** + * @brief Disable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_LATCH(qei) ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk)) + +/** + * @brief Enable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_LATCH(qei) ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk) + +/** + * @brief Disable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_RELOAD(qei) ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk)) + +/** + * @brief Enable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_RELOAD(qei) ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk) + +/** + * @brief Disable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHAEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro disable specified QEI signal input. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHBEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro enable specified QEI signal input. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro disable specified QEI signal inverted input polarity. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro inverse specified QEI signal input polarity. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro disable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_DISABLE_INT(qei, u32IntSel) ((qei)->CTL &= ~(u32IntSel)) + +/** + * @brief Enable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro enable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_ENABLE_INT(qei, u32IntSel) ((qei)->CTL |= (u32IntSel)) + +/** + * @brief Disable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI noise filter function. + * \hideinitializer + */ +#define QEI_DISABLE_NOISE_FILTER(qei) ((qei)->CTL |= QEI_CTL_NFDIS_Msk) + +/** + * @brief Enable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32ClkSel The sampling frequency of the noise filter clock. + * - \ref QEI_CTL_NFCLKSEL_DIV1 + * - \ref QEI_CTL_NFCLKSEL_DIV2 + * - \ref QEI_CTL_NFCLKSEL_DIV4 + * - \ref QEI_CTL_NFCLKSEL_DIV16 + * - \ref QEI_CTL_NFCLKSEL_DIV32 + * - \ref QEI_CTL_NFCLKSEL_DIV64 + * @return None + * @details This macro enable QEI noise filter function and select noise filter clock. + * \hideinitializer + */ +#define QEI_ENABLE_NOISE_FILTER(qei, u32ClkSel) ((qei)->CTL = ((qei)->CTL & (~(QEI_CTL_NFDIS_Msk|QEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel)) + +/** + * @brief Get QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter register value. + * @details This macro get QEI pulse counter value. + * \hideinitializer + */ +#define QEI_GET_CNT_VALUE(qei) ((qei)->CNT) + +/** + * @brief Get QEI counting direction + * @param[in] qei The pointer of the specified QEI module. + * @retval 0 QEI counter is in down-counting. + * @retval 1 QEI counter is in up-counting. + * @details This macro get QEI counting direction. + * \hideinitializer + */ +#define QEI_GET_DIR(qei) (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0) + +/** + * @brief Get QEI counter hold value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter hold register value. + * @details This macro get QEI pulse counter hold value, which is updated with counter value in hold counter value control. + * \hideinitializer + */ +#define QEI_GET_HOLD_VALUE(qei) ((qei)->CNTHOLD) + +/** + * @brief Get QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter index latch value + * @details This macro get QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_GET_INDEX_LATCH_VALUE(qei) ((qei)->CNTLATCH) + +/** + * @brief Set QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Val The latch value. + * @return QEI pulse counter index latch value + * @details This macro set QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_SET_INDEX_LATCH_VALUE(qei,u32Val) ((qei)->CNTLATCH = (u32Val)) + +/** + * @brief Get QEI interrupt flag status + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. +* - \ref QEI_STATUS_DIRF_Msk : Counting direction flag + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @retval 0 QEI specified interrupt flag is not set. + * @retval 1 QEI specified interrupt flag is set. + * @details This macro get QEI specified interrupt flag status. + * \hideinitializer + */ +#define QEI_GET_INT_FLAG(qei, u32IntSel) (((qei)->STATUS & (u32IntSel))?1:0) + + +/** + * @brief Clear QEI interrupt flag + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @return None + * @details This macro clear QEI specified interrupt flag. + * \hideinitializer + */ +#define QEI_CLR_INT_FLAG(qei, u32IntSel) ((qei)->STATUS = (u32IntSel)) + +/** + * @brief Set QEI counter compare value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter compare value. + * \hideinitializer + */ +#define QEI_SET_CNT_CMP(qei, u32Value) ((qei)->CNTCMP = (u32Value)) + +/** + * @brief Set QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter value. + * \hideinitializer + */ +#define QEI_SET_CNT_VALUE(qei, u32Value) ((qei)->CNT = (u32Value)) + +/** + * @brief Enable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro enable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_ENABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL |= (u32Type)) + +/** + * @brief Disable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro disable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_DISABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL &= ~(u32Type)) + +/** + * @brief Set QEI maximum count value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter maximum value. + * @return QEI maximum count value + * @details This macro set QEI maximum count value. + * \hideinitializer + */ +#define QEI_SET_CNT_MAX(qei, u32Value) ((qei)->CNTMAX = (u32Value)) + +/** + * @brief Set QEI counting mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Mode QEI counting mode. + * - \ref QEI_CTL_X4_FREE_COUNTING_MODE + * - \ref QEI_CTL_X2_FREE_COUNTING_MODE + * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE + * @return None + * @details This macro set QEI counting mode. + * \hideinitializer + */ +#define QEI_SET_CNT_MODE(qei, u32Mode) ((qei)->CTL = ((qei)->CTL & (~QEI_CTL_MODE_Msk)) | (u32Mode)) + + +void QEI_Close(QEI_T* qei); +void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel); +void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel); +void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value); +void QEI_Start(QEI_T* qei); +void QEI_Stop(QEI_T* qei); + + +/**@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group QEI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__QEI_H__*/ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_qspi.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_qspi.h new file mode 100644 index 0000000000..9e3e194240 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_qspi.h @@ -0,0 +1,401 @@ +/****************************************************************************** + * @file qspi.h + * @version V3.00 + * @brief M2354 series QSPI driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __QSPI_H__ +#define __QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + +/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants + @{ +*/ + +#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */ +#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */ +#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */ +#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */ + +#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave */ +#define QSPI_MASTER (0x0UL) /*!< Set as master */ + +#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS */ +#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */ +#define QSPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low */ + +/* QSPI Interrupt Mask */ +#define QSPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask */ +#define QSPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask */ +#define QSPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask */ +#define QSPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask */ +#define QSPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask */ +#define QSPI_SLVTO_INT_MASK (0x020UL) /*!< Slave Mode Time-out interrupt mask */ +#define QSPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask */ +#define QSPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask */ +#define QSPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask */ +#define QSPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask */ +#define QSPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask */ + +/* QSPI Status Mask */ +#define QSPI_BUSY_MASK (0x01UL) /*!< Busy status mask */ +#define QSPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask */ +#define QSPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask */ +#define QSPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask */ +#define QSPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask */ +#define QSPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask */ +#define QSPI_SPIEN_STS_MASK (0x40UL) /*!< SPIEN status mask */ +#define QSPI_SSLINE_STS_MASK (0x80UL) /*!< QSPIx_SS line status mask */ + +/* QSPI Status2 Mask */ +#define QSPI_SLVBENUM_MASK (0x01UL) /*!< Effective bit number of uncompleted RX data status mask */ + +/**@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag. + */ +#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ( (qspi)->STATUS = QSPI_STATUS_UNITIF_Msk ) + +/** + * @brief Disable 2-bit Transfer mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TWOBIT bit of QSPI_CTL register to disable 2-bit Transfer mode. + */ +#define QSPI_DISABLE_2BIT_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TWOBIT_Msk ) + +/** + * @brief Disable Slave 3-wire mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear SLV3WIRE bit of QSPI_SSCTL register to disable Slave 3-wire mode. + */ +#define QSPI_DISABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL &= ~QSPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Disable Dual I/O mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear DUALIOEN bit of QSPI_CTL register to disable Dual I/O mode. + */ +#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Disable Quad I/O mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear QUADIOEN bit of QSPI_CTL register to disable Quad I/O mode. + */ +#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Disable TX DTR mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXDTREN bit of QSPI_CTL register to disable TX DTR mode. + */ +#define QSPI_DISABLE_TXDTR_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TXDTREN_Msk ) + +/** + * @brief Enable 2-bit Transfer mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TWOBIT bit of QSPI_CTL register to enable 2-bit Transfer mode. + */ +#define QSPI_ENABLE_2BIT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TWOBIT_Msk ) + +/** + * @brief Enable Slave 3-wire mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set SLV3WIRE bit of QSPI_SSCTL register to enable Slave 3-wire mode. + */ +#define QSPI_ENABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL |= QSPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable Dual input mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear DATDIR bit and set DUALIOEN bit of QSPI_CTL register to enable Dual input mode. + */ +#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual output mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set DATDIR bit and DUALIOEN bit of QSPI_CTL register to enable Dual output mode. + */ +#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk) ) + +/** + * @brief Enable Quad input mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear DATDIR bit and set QUADIOEN bit of QSPI_CTL register to enable Quad input mode. + */ +#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Enable Quad output mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set DATDIR bit and QUADIOEN bit of QSPI_CTL register to enable Quad output mode. + */ +#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk) ) + +/** + * @brief Enable TX DTR mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXDTREN bit of QSPI_CTL register to enable TX DTR mode. + */ +#define QSPI_ENABLE_TXDTR_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TXDTREN_Msk ) + +/** + * @brief Trigger RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function. + */ +#define QSPI_TRIGGER_RX_PDMA(qspi) ( (qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Trigger TX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function. + */ +#define QSPI_TRIGGER_TX_PDMA(qspi) ( (qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to enable TX and RX PDMA transfer function. + */ +#define QSPI_TRIGGER_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL |= (QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function. + */ +#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function. + */ +#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of QSPI_PDMACTL register to disable TX and RX PDMA transfer function. + */ +#define QSPI_DISABLE_TX_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~(QSPI_PDMACTL_TXPDMAEN_Msk | QSPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] qspi The pointer of the specified QSPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO. + */ +#define QSPI_GET_RX_FIFO_COUNT(qspi) ( ((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos ) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag. + */ +#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk) >> QSPI_STATUS_RXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag. + */ +#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk) >> QSPI_STATUS_TXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag. + */ +#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk) >> QSPI_STATUS_TXFULL_Pos ) + +/** + * @brief Get the datum read from RX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Data in RX register. + * @details Read QSPI_RX register to get the received datum. + */ +#define QSPI_READ_RX(qspi) ( (qspi)->RX ) + +/** + * @brief Write datum to TX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxData The datum which user attempt to transfer through QSPI bus. + * @return None. + * @details Write u32TxData to QSPI_TX register. + */ +#define QSPI_WRITE_TX(qspi, u32TxData) ( (qspi)->TX = (u32TxData) ) + +/** + * @brief Set QSPIx_SS pin to high state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to high state. + */ +#define QSPI_SET_SS_HIGH(qspi) ( (qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk) ) + +/** + * @brief Set QSPIx_SS pin to low state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to low state. + */ +#define QSPI_SET_SS_LOW(qspi) ( (qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk ) + +/** + * @brief Enable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]). + */ +#define QSPI_ENABLE_BYTE_REORDER(qspi) ( (qspi)->CTL |= QSPI_CTL_REORDER_Msk ) + +/** + * @brief Disable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function. + */ +#define QSPI_DISABLE_BYTE_REORDER(qspi) ( (qspi)->CTL &= ~QSPI_CTL_REORDER_Msk ) + +/** + * @brief Set the length of suspend interval. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle). + */ +#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos) ) + +/** + * @brief Set the QSPI transfer sequence with LSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first. + */ +#define QSPI_SET_LSB_FIRST(qspi) ( (qspi)->CTL |= QSPI_CTL_LSB_Msk ) + +/** + * @brief Set the QSPI transfer sequence with MSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first. + */ +#define QSPI_SET_MSB_FIRST(qspi) ( (qspi)->CTL &= ~QSPI_CTL_LSB_Msk ) + +/** + * @brief Set the data width of a QSPI transaction. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + */ +#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << QSPI_CTL_DWIDTH_Pos) ) + +/** + * @brief Get the QSPI busy state. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 QSPI controller is not busy. + * @retval 1 QSPI controller is busy. + * @details This macro will return the busy state of QSPI controller. + */ +#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk) >> QSPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set SPIEN (QSPI_CTL[0]) to enable QSPI controller. + */ +#define QSPI_ENABLE(qspi) ( (qspi)->CTL |= QSPI_CTL_SPIEN_Msk ) + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear SPIEN (QSPI_CTL[0]) to disable QSPI controller. + */ +#define QSPI_DISABLE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_SPIEN_Msk ) + +/* Function prototype declaration */ +uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void QSPI_Close(QSPI_T *qspi); +void QSPI_ClearRxFIFO(QSPI_T *qspi); +void QSPI_ClearTxFIFO(QSPI_T *qspi); +void QSPI_DisableAutoSS(QSPI_T *qspi); +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock); +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t QSPI_GetBusClock(QSPI_T *qspi); +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetStatus2(QSPI_T *qspi, uint32_t u32Mask); + + +/**@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group QSPI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __QSPI_H__ */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_rng.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_rng.h new file mode 100644 index 0000000000..227b0b39dd --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_rng.h @@ -0,0 +1,60 @@ +/**************************************************************************//** + * @file rng.h + * @version V3.00 + * @brief Random Number Generator Interface Controller (rng) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RNG_H__ +#define __RNG_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RNG_Driver RNG Driver + @{ +*/ + +/** @addtogroup RNG_EXPORTED_CONSTANTS RNG Exported Constants + @{ +*/ + +/**@}*/ /* end of group RNG_EXPORTED_CONSTANTS */ + + +/** @addtogroup RNG_EXPORTED_FUNCTIONS RNG Exported Functions + @{ +*/ + +int32_t RNG_Open(void); +int32_t RNG_Random(uint32_t *pu32Buf, int32_t nWords); + +int32_t RNG_ECDSA_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18]); +int32_t RNG_ECDSA(uint32_t u32KeySize); +int32_t RNG_ECDH_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18]); +int32_t RNG_ECDH(uint32_t u32KeySize); + +/**@}*/ /* end of group RNG_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group RNG_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RNG_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_rtc.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_rtc.h new file mode 100644 index 0000000000..873ba93319 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_rtc.h @@ -0,0 +1,398 @@ +/**************************************************************************//** + * @file rtc.h + * @version V3.00 + * @brief Real Time Clock(RTC) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_H__ +#define __RTC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Initial Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Time Attribute Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */ +#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */ +#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */ +#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Tick Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */ +#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */ +#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */ +#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */ +#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */ +#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */ +#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */ +#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Day of Week Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */ +#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */ +#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */ +#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */ +#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */ +#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */ +#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */ +#define RTC_FCR_REFERENCE 32752 /*!< RTC Reference for frequency compensation */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Tamper Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_TAMPER0_SELECT (0x1UL << 0) /*!< Select Tamper 0 \hideinitializer */ +#define RTC_TAMPER1_SELECT (0x1UL << 1) /*!< Select Tamper 1 \hideinitializer */ +#define RTC_TAMPER2_SELECT (0x1UL << 2) /*!< Select Tamper 2 \hideinitializer */ +#define RTC_TAMPER3_SELECT (0x1UL << 3) /*!< Select Tamper 3 \hideinitializer */ +#define RTC_TAMPER4_SELECT (0x1UL << 4) /*!< Select Tamper 4 \hideinitializer */ +#define RTC_TAMPER5_SELECT (0x1UL << 5) /*!< Select Tamper 5 \hideinitializer */ +#define RTC_MAX_TAMPER_PIN_NUM 6UL /*!< Tamper Pin number \hideinitializer */ + +#define RTC_TAMPER_LOW_LEVEL_DETECT 0UL /*!< Tamper pin detect voltage level is low \hideinitializer */ +#define RTC_TAMPER_HIGH_LEVEL_DETECT 1UL /*!< Tamper pin detect voltage level is high \hideinitializer */ + +#define RTC_TAMPER_DEBOUNCE_DISABLE 0UL /*!< Disable RTC tamper pin de-bounce function \hideinitializer */ +#define RTC_TAMPER_DEBOUNCE_ENABLE 1UL /*!< Enable RTC tamper pin de-bounce function \hideinitializer */ + +#define RTC_PAIR0_SELECT (0x1UL << 0) /*!< Select Pair 0 \hideinitializer */ +#define RTC_PAIR1_SELECT (0x1UL << 1) /*!< Select Pair 1 \hideinitializer */ +#define RTC_PAIR2_SELECT (0x1UL << 2) /*!< Select Pair 2 \hideinitializer */ +#define RTC_MAX_PAIR_NUM 3UL /*!< Pair number \hideinitializer */ + +#define RTC_2POW10_CLK (0x0UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 RTC clock cycles \hideinitializer */ +#define RTC_2POW11_CLK (0x1UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 2 RTC clock cycles \hideinitializer */ +#define RTC_2POW12_CLK (0x2UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 4 RTC clock cycles \hideinitializer */ +#define RTC_2POW13_CLK (0x3UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 6 RTC clock cycles \hideinitializer */ +#define RTC_2POW14_CLK (0x4UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 8 RTC clock cycles \hideinitializer */ +#define RTC_2POW15_CLK (0x5UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 16 RTC clock cycles \hideinitializer */ +#define RTC_2POW16_CLK (0x6UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 32 RTC clock cycles \hideinitializer */ +#define RTC_2POW17_CLK (0x7UL << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 64 RTC clock cycles \hideinitializer */ + +#define RTC_REF_RANDOM_PATTERN 0x0UL /*!< The new reference pattern is generated by random number generator when the reference pattern run out \hideinitializer */ +#define RTC_REF_SEED_VALUE 0x1UL /*!< The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Clock Source Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_CLOCK_SOURCE_LXT 0UL /*!< Set RTC clock source as external LXT \hideinitializer */ +#define RTC_CLOCK_SOURCE_LIRC 1UL /*!< Set RTC clock source as LIRC \hideinitializer */ +#define RTC_CLOCK_SOURCE_LIRC32K 2UL /*!< Set RTC clock source as LIRC32K \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC GPIO_MODE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_IO_MODE_INPUT 0x0UL /*!< Input Mode */ +#define RTC_IO_MODE_OUTPUT 0x1UL /*!< Output Mode */ +#define RTC_IO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */ +#define RTC_IO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */ + +#define RTC_IO_DIGITAL_ENABLE 0UL /*!< I/O digital path is enabled */ +#define RTC_IO_DIGITAL_DISABLE 1UL /*!< I/O digital path is disabled */ + +#define RTC_IO_PULL_UP_DOWN_DISABLE 0x0UL /*!< I/O pull-up and pull-down is disabled */ +#define RTC_IO_PULL_UP_ENABLE 0x1UL /*!< I/O pull-up is enabled */ +#define RTC_IO_PULL_DOWN_ENABLE 0x2UL /*!< I/O pull-down is enabled */ + + +/**@}*/ /* end of group RTC_EXPORTED_CONSTANTS */ + + +/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs + @{ +*/ +/** + * @details RTC define Time Data Struct + */ +typedef struct +{ + uint32_t u32Year; /*!< Year value */ + uint32_t u32Month; /*!< Month value */ + uint32_t u32Day; /*!< Day value */ + uint32_t u32DayOfWeek; /*!< Day of week value */ + uint32_t u32Hour; /*!< Hour value */ + uint32_t u32Minute; /*!< Minute value */ + uint32_t u32Second; /*!< Second value */ + uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */ + uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */ +} S_RTC_TIME_DATA_T; + +/**@}*/ /* end of group RTC_EXPORTED_STRUCTS */ + + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Indicate is Leap Year or not + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 This year is not a leap year + * @retval 1 This year is a leap year + * + * @details According to current date, return this year is leap year or not. + * \hideinitializer + */ +#define RTC_IS_LEAP_YEAR(rtc) (((rtc)->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk)? 1:0) + +/** + * @brief Clear RTC Alarm Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro is used to clear RTC alarm interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_ALARM_INT_FLAG(rtc) ((rtc)->INTSTS = RTC_INTSTS_ALMIF_Msk) + +/** + * @brief Clear RTC Tick Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro is used to clear RTC tick interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TICK_INT_FLAG(rtc) ((rtc)->INTSTS = RTC_INTSTS_TICKIF_Msk) + +/** + * @brief Clear RTC Tamper Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * @param[in] u32TamperFlag Tamper interrupt flag. It consists of: \n + * - \ref RTC_INTSTS_TAMP0IF_Msk \n + * - \ref RTC_INTSTS_TAMP1IF_Msk \n + * - \ref RTC_INTSTS_TAMP2IF_Msk \n + * - \ref RTC_INTSTS_TAMP3IF_Msk \n + * - \ref RTC_INTSTS_TAMP4IF_Msk \n + * - \ref RTC_INTSTS_TAMP5IF_Msk + * + * @return None + * + * @details This macro is used to clear RTC tamper pin interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TAMPER_INT_FLAG(rtc, u32TamperFlag) ((rtc)->INTSTS = (u32TamperFlag)) + +/** + * @brief Get RTC Alarm Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 RTC alarm interrupt did not occur + * @retval 1 RTC alarm interrupt occurred + * + * @details This macro indicates RTC alarm interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_ALARM_INT_FLAG(rtc) (((rtc)->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0) + +/** + * @brief Get RTC Time Tick Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 RTC time tick interrupt did not occur + * @retval 1 RTC time tick interrupt occurred + * + * @details This macro indicates RTC time tick interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TICK_INT_FLAG(rtc) (((rtc)->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0) + +/** + * @brief Set I/O Control By GPIO + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro sets the PF.4~11 pin I/O is controlled by GPIO module. + * \hideinitializer + */ +#define RTC_SET_IOCTL_BY_GPIO(rtc) ((rtc)->LXTCTL &= ~RTC_LXTCTL_IOCTLSEL_Msk) + +/** + * @brief Set I/O Control By RTC + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro sets the PF.4~11 pin I/O is controlled by RTC module. + * \hideinitializer + */ +#define RTC_SET_IOCTL_BY_RTC(rtc) ((rtc)->LXTCTL |= RTC_LXTCTL_IOCTLSEL_Msk) + +/** + * @brief Get I/O Control Property + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 PF.4~11 pin I/O is controlled by GPIO module + * @retval 1 PF.4~11 pin I/O is controlled by RTC module + * + * @details This macro indicates the PF.4~11 pin I/O control property. + * \hideinitializer + */ +#define RTC_GET_IOCTL_PROPERTY(rtc) (((rtc)->LXTCTL & RTC_LXTCTL_IOCTLSEL_Msk)? 1:0) + +/** + * @brief Get RTC Tamper Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 RTC tamper event interrupt did not occur + * @retval 1 RTC tamper event interrupt occurred + * + * @details This macro indicates RTC tamper event occurred or not. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_FLAG(rtc) (((rtc)->INTSTS & (0x3F00))? 1:0) + +/** + * @brief Get RTC Tamper Interrupt Status + * + * @param[in] rtc The pointer of RTC module. + * + * @retval RTC_INTSTS_TAMP0IF_Msk Tamper 0 interrupt flag is generated + * @retval RTC_INTSTS_TAMP1IF_Msk Tamper 1 interrupt flag is generated + * @retval RTC_INTSTS_TAMP2IF_Msk Tamper 2 interrupt flag is generated + * @retval RTC_INTSTS_TAMP3IF_Msk Tamper 3 interrupt flag is generated + * @retval RTC_INTSTS_TAMP4IF_Msk Tamper 4 interrupt flag is generated + * @retval RTC_INTSTS_TAMP5IF_Msk Tamper 5 interrupt flag is generated + * + * @details This macro indicates RTC tamper interrupt status. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_STATUS(rtc) (((rtc)->INTSTS & (0x3F00))) + +/** + * @brief Enable RTC Tick Wake-up Function + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro is used to enable RTC tick interrupt wake-up function. + * \hideinitializer + */ +#define RTC_ENABLE_TICK_WAKEUP(rtc) ((rtc)->INTEN |= RTC_INTEN_TICKIEN_Msk); + +/** + * @brief Disable RTC Tick Wake-up Function + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro is used to disable RTC tick interrupt wake-up function. + * \hideinitializer + */ +#define RTC_DISABLE_TICK_WAKEUP(rtc) ((rtc)->INTEN &= ~RTC_INTEN_TICKIEN_Msk); + +/** + * @brief Read Spare Register + * + * @param[in] rtc The pointer of RTC module. + * @param[in] u32RegNum The spare register number, 0~19. + * + * @return Spare register content + * + * @details Read the specify spare register content. + * \hideinitializer + */ +#define RTC_READ_SPARE_REGISTER(rtc, u32RegNum) ((rtc)->SPR[(u32RegNum)]) + +/** + * @brief Write Spare Register + * + * @param[in] rtc The pointer of RTC module. + * @param[in] u32RegNum The spare register number, 0~19. + * @param[in] u32RegValue The spare register value. + * + * @return None + * + * @details Write specify data to spare register. + * \hideinitializer + */ +#define RTC_WRITE_SPARE_REGISTER(rtc, u32RegNum, u32RegValue) ((rtc)->SPR[(u32RegNum)] = (u32RegValue)) + + +void RTC_Open(S_RTC_TIME_DATA_T *sPt); +void RTC_Close(void); +void RTC_32KCalibration(int32_t i32FrequencyX10000); +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek); +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day); +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk); +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk); +uint32_t RTC_GetDayOfWeek(void); +void RTC_SetTickPeriod(uint32_t u32TickSelection); +void RTC_EnableInt(uint32_t u32IntFlagMask); +void RTC_DisableInt(uint32_t u32IntFlagMask); +void RTC_EnableSpareAccess(void); +void RTC_DisableSpareRegister(void); +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn); +void RTC_StaticTamperDisable(uint32_t u32TamperSelect); +void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source); +void RTC_DynamicTamperDisable(uint32_t u32PairSel); +void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed); +uint32_t RTC_SetClockSource(uint32_t u32ClkSrc); +void RTC_SetGPIOMode(uint32_t u32PFPin, uint32_t u32Mode, uint32_t u32DigitalCtl, uint32_t u32PullCtl, uint32_t u32OutputLevel); +void RTC_SetGPIOLevel(uint32_t u32PFPin, uint32_t u32OutputLevel); + +/**@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group RTC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_H__ */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_sc.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_sc.h new file mode 100644 index 0000000000..82ad55722b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_sc.h @@ -0,0 +1,307 @@ +/**************************************************************************//** + * @file sc.h + * @version V3.00 + * @brief Smartcard(SC) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_H__ +#define __SC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants + @{ +*/ +#define SC_INTERFACE_NUM (3UL) /*!< Smartcard interface numbers \hideinitializer */ +#define SC_PIN_STATE_HIGH (1UL) /*!< Smartcard pin status high \hideinitializer */ +#define SC_PIN_STATE_LOW (0UL) /*!< Smartcard pin status low \hideinitializer */ +#define SC_PIN_STATE_IGNORE (0xFFFFFFFFUL) /*!< Ignore pin status \hideinitializer */ +#define SC_CLK_ON (1UL) /*!< Smartcard clock on \hideinitializer */ +#define SC_CLK_OFF (0UL) /*!< Smartcard clock off \hideinitializer */ + +#define SC_TMR_MODE_0 (0UL << SC_TMRCTL0_OPMODE_Pos) /*!INTEN |= (u32Mask)) + +/** + * @brief This macro disable smartcard interrupt + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Interrupt mask to be disabled. A combination of + * - \ref SC_INTEN_ACERRIEN_Msk + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_INITIEN_Msk + * - \ref SC_INTEN_CDIEN_Msk + * - \ref SC_INTEN_BGTIEN_Msk + * - \ref SC_INTEN_TMR2IEN_Msk + * - \ref SC_INTEN_TMR1IEN_Msk + * - \ref SC_INTEN_TMR0IEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * + * @return None + * + * @details The macro is used to disable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt, + * Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt, + * Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief This macro set VCC pin state of smartcard interface + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW. + * + * @return None + * + * @details User can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11]) to decide SC_PWR pin is in high or low level. + * \hideinitializer + */ +#define SC_SET_VCC_PIN(sc, u32State) \ + do {\ + while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\ + }while(0) + + +/** + * @brief This macro turns CLK output on or off + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF. + * + * @return None + * + * @details User can set CLKKEEP (SC_PINCTL[6]) to decide SC_CLK pin always keeps free running or not. + * \hideinitializer + */ +#define SC_SET_CLK_PIN(sc, u32OnOff)\ + do {\ + while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\ + if(u32OnOff)\ + (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\ + else\ + (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\ + }while(0) + +/** + * @brief This macro set I/O pin state of smartcard interface + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW. + * + * @return None + * + * @details User can set SCDATA (SC_PINCTL[9]) to decide SC_DATA pin to high or low. + * \hideinitializer + */ +#define SC_SET_IO_PIN(sc, u32State)\ + do {\ + while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\ + }while(0) + +/** + * @brief This macro set RST pin state of smartcard interface + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW. + * + * @return None + * + * @details User can set SCRST (SC_PINCTL[1]) to decide SC_RST pin to high or low. + * \hideinitializer + */ +#define SC_SET_RST_PIN(sc, u32State)\ + do {\ + while(((sc)->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\ + }while(0) + +/** + * @brief This macro read one byte from smartcard module receive FIFO + * + * @param[in] sc The pointer of smartcard module. + * + * @return One byte read from receive FIFO + * + * @details By reading DAT register, the SC will return an 8-bit received data. + * \hideinitializer + */ +#define SC_READ(sc) ((char)((sc)->DAT)) + +/** + * @brief This macro write one byte to smartcard module transmit FIFO + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u8Data Data to write to transmit FIFO. + * + * @return None + * + * @details By writing data to DAT register, the SC will send out an 8-bit data. + * \hideinitializer + */ +#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief This macro set smartcard stop bit length + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Len Stop bit length, ether 1 or 2. + * + * @return None + * + * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol. + * \hideinitializer + */ +#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | (((u32Len) == 1)? SC_CTL_NSB_Msk : 0)) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count); +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count); + + +/** + * @brief Enable/Disable Tx error retry, and set Tx error retry count + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry. + * + * @return None + * + * @details This function is used to enable/disable transmitter retry function when parity error has occurred, and set error retry count. + */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count) +{ + while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {} + + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk); + + if((u32Count) != 0UL) + { + while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {} + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk; + } +} + +/** + * @brief Enable/Disable Rx error retry, and set Rx error retry count + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry. + * + * @return None + * + * @details This function is used to enable/disable receiver retry function when parity error has occurred, and set error retry count. + */ +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count) +{ + while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {} + + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk); + + if((u32Count) != 0UL) + { + while(((sc)->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk){} + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk; + } +} + + +uint32_t SC_IsCardInserted(SC_T *sc); +void SC_ClearFIFO(SC_T *sc); +void SC_Close(SC_T *sc); +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR); +void SC_ResetReader(SC_T *sc); +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT); +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT); +void SC_StopAllTimer(SC_T *sc); +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount); +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum); +uint32_t SC_GetInterfaceClock(SC_T *sc); + +/**@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SC_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_scu.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_scu.h new file mode 100644 index 0000000000..09241b88be --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_scu.h @@ -0,0 +1,360 @@ +/**************************************************************************//** + * @file scu.h + * @version V3.00 + * @brief Secure Configuration Unit Driver Header + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SCU_H__ +#define __SCU_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCU_Driver SCU Driver + @{ +*/ + +/** @addtogroup SCU_EXPORTED_CONSTANTS SCU Exported Constants + @{ +*/ + + + + +/** + * @details Non-secure Attribution Definition. + */ +typedef enum NSATTR +{ + /****** PNNSET0 **********************************************************************************/ + USBH_Attr = 9, + SDH0_Attr = 13, + EBI_Attr = 16, + PDMA1_Attr = 24, + + /****** PNNSET1 **********************************************************************************/ + CRC_Attr = 32 + 17, + CRPT_Attr = 32 + 18, + + /****** PNNSET2 **********************************************************************************/ + EWDT_Attr = 64 + 2, + EADC_Attr = 64 + 3, + ACMP01_Attr = 64 + 5, + DAC_Attr = 64 + 7, + I2S0_Attr = 64 + 8, + OTG_Attr = 64 + 13, + TMR23_Attr = 64 + 17, + TMR45_Attr = 64 + 18, + EPWM0_Attr = 64 + 24, + EPWM1_Attr = 64 + 25, + BPWM0_Attr = 64 + 26, + BPWM1_Attr = 64 + 27, + /****** PNNSET3 **********************************************************************************/ + QSPI0_Attr = 96 + 0, + SPI0_Attr = 96 + 1, + SPI1_Attr = 96 + 2, + SPI2_Attr = 96 + 3, + SPI3_Attr = 96 + 4, + UART0_Attr = 96 + 16, + UART1_Attr = 96 + 17, + UART2_Attr = 96 + 18, + UART3_Attr = 96 + 19, + UART4_Attr = 96 + 20, + UART5_Attr = 96 + 21, + /****** PNNSET4 **********************************************************************************/ + I2C0_Attr = 128 + 0, + I2C1_Attr = 128 + 1, + I2C2_Attr = 128 + 2, + SC0_Attr = 128 + 16, + SC1_Attr = 128 + 17, + SC2_Attr = 128 + 18, + + + /****** PNNSET5 **********************************************************************************/ + CAN0_Attr = 160 + 0, + QEI0_Attr = 160 + 16, + QEI1_Attr = 160 + 17, + ECAP0_Attr = 160 + 20, + ECAP1_Attr = 160 + 21, + TRNG_Attr = 160 + 25, + LCD_Attr = 160 + 27, + + /****** PNNSET6 **********************************************************************************/ + USBD_Attr = 192 + 0, + USCI0_Attr = 192 + 16, + USCI1_Attr = 192 + 17 + + +} NSATTR_T; + + +/**@}*/ /* end of group SCU_EXPORTED_CONSTANTS */ + + +/** @addtogroup SCU_EXPORTED_FUNCTIONS SCU Exported Functions + @{ +*/ + +/** + * @brief Set peripheral non-secure attribution + * + * @param[in] nsattr The secure/non-secure attribution of specified module. + The possible value could be refer to \ref NSATTR. + * + * @return None + * + * @details This macro is used to set a peripheral to be non-secure peripheral. + * + */ +#define SCU_SET_PNSSET(nsattr) { SCU->PNSSET[(nsattr)/32] |= (1 << ((nsattr) & 0x1ful)); } + +/** + * @brief Get peripheral secure/non-secure attribution + * + * @param[in] nsattr The secure/non-secure attribution of specified module. + The possible value could be refer to \ref NSATTR. + * + * @return The secure/non-secure attribution of specified peripheral. + * @retval 0 The peripheral is secure + * @retval 1 The peripheral is non-secure + * + * @details This macro gets the peripheral secure/non-secure attribution. + */ +#define SCU_GET_PNSSET(nsattr) ((SCU->PNSSET[(nsattr)/32] >> ((nsattr) & 0x1ful)) & 1ul) + + +/** + * @brief Set secure/non-secure attribution of specified GPIO pin + * + * @param[in] port GPIO Port. It could be PA, PB, PC, PD, PE, PF, PG and PH. + * @param[in] bitmask Bit mask of each bit. 0 is non-secure. 1 is secure. + * + * @return None + * + * @details This macro sets GPIO pin secure/non-secure attribution. + */ +#define SCU_SET_IONSSET(port, mask) (SCU->IONSSET[((uint32_t)(port)-(GPIOA_BASE))/0x40] = (mask)) + + +/** + * @brief Get secure/non-secure attribution of specified GPIO port + * + * @param[in] port GPIO Port. It could be PA, PB, PC, PD, PE, PF, PG and PH. + * + * @return The secure/non-secure attribution of the port. + * @retval 0 The relative bit of specified IO port is secure + * @retval 1 The relative bit of specified IO port is non-secure + * + * @details This macro gets IO secure/non-secure attribution of specified IO port. + */ +#define SCU_GET_IONSSET(port) (SCU->IONSSET[((uint32_t)(port) - (GPIOA_BASE))/0x40]) + + +/** + * @brief Enable sercure violation interrupts + * + * @param[in] mask The mask of each secure violation interrupt source + * - \ref SCU_SVIOIEN_APB0IEN_Msk + * - \ref SCU_SVIOIEN_APB1IEN_Msk + * - \ref SCU_SVIOIEN_GPIOIEN_Msk + * - \ref SCU_SVIOIEN_EBIIEN_Msk + * - \ref SCU_SVIOIEN_USBHIEN_Msk + * - \ref SCU_SVIOIEN_CRCIEN_Msk + * - \ref SCU_SVIOIEN_SDH0IEN_Msk + * - \ref SCU_SVIOIEN_PDMA0IEN_Msk + * - \ref SCU_SVIOIEN_PDMA1IEN_Msk + * - \ref SCU_SVIOIEN_SRAM0IEN_Msk + * - \ref SCU_SVIOIEN_SRAM1IEN_Msk + * - \ref SCU_SVIOIEN_FMCIEN_Msk + * - \ref SCU_SVIOIEN_FLASHIEN_Msk + * - \ref SCU_SVIOIEN_SCUIEN_Msk + * - \ref SCU_SVIOIEN_SYSIEN_Msk + * - \ref SCU_SVIOIEN_CRPTIEN_Msk + * + * @return None + * + * @details This macro is used to enable secure violation interrupt of SCU. + * The secure violation interrupt could be used to detect attack of secure elements. + */ +#define SCU_ENABLE_INT(mask) (SCU->SVIOIEN |= (mask)) + + +/** + * @brief Disable sercure violation interrupts + * + * @param[in] mask The mask of each secure violation interrupt source + * - \ref SCU_SVIOIEN_APB0IEN_Msk + * - \ref SCU_SVIOIEN_APB1IEN_Msk + * - \ref SCU_SVIOIEN_GPIOIEN_Msk + * - \ref SCU_SVIOIEN_EBIIEN_Msk + * - \ref SCU_SVIOIEN_USBHIEN_Msk + * - \ref SCU_SVIOIEN_CRCIEN_Msk + * - \ref SCU_SVIOIEN_SDH0IEN_Msk + * - \ref SCU_SVIOIEN_PDMA0IEN_Msk + * - \ref SCU_SVIOIEN_PDMA1IEN_Msk + * - \ref SCU_SVIOIEN_SRAM0IEN_Msk + * - \ref SCU_SVIOIEN_SRAM1IEN_Msk + * - \ref SCU_SVIOIEN_FMCIEN_Msk + * - \ref SCU_SVIOIEN_FLASHIEN_Msk + * - \ref SCU_SVIOIEN_SCUIEN_Msk + * - \ref SCU_SVIOIEN_SYSIEN_Msk + * - \ref SCU_SVIOIEN_CRPTIEN_Msk + * + * @return None + * + * @details This macro is used to disable secure violation interrupt of SCU. + * + */ +#define SCU_DISABLE_INT(mask) (SCU->SVIOIEN &= (~(mask))) + + +/** + * @brief Get secure violation interrupt status + * + * @param mask The interrupt flag mask bit + * + * @return The value of SCU_SVINTSTS register + * + * @details Return interrupt flag of SCU_SVINTSTS register. + * + */ +#define SCU_GET_INT_FLAG(mask) (SCU->SVINTSTS&(mask)) + +/** + * @brief Clear secure violation interrupt flag + * + * @param[in] flag The combination of the specified interrupt flags. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. + * - \ref SCU_SVINTSTS_APB0IF_Msk + * - \ref SCU_SVINTSTS_APB1IF_Msk + * - \ref SCU_SVINTSTS_GPIOIF_Msk + * - \ref SCU_SVINTSTS_EBIIF_Msk + * - \ref SCU_SVINTSTS_USBHIF_Msk + * - \ref SCU_SVINTSTS_CRCIF_Msk + * - \ref SCU_SVINTSTS_SDH0IF_Msk + * - \ref SCU_SVINTSTS_PDMA0IF_Msk + * - \ref SCU_SVINTSTS_PDMA1IF_Msk + * - \ref SCU_SVINTSTS_SRAM0IF_Msk + * - \ref SCU_SVINTSTS_SRAM1IF_Msk + * - \ref SCU_SVINTSTS_FMCIF_Msk + * - \ref SCU_SVINTSTS_FLASHIF_Msk + * - \ref SCU_SVINTSTS_SCUIF_Msk + * - \ref SCU_SVINTSTS_SYSIF_Msk + * - \ref SCU_SVINTSTS_CRPTIF_Msk + * + * @return None + * + * @details Clear SCU related interrupt flags specified by flag parameter. + * + */ +#define SCU_CLR_INT_FLAG(flag) (SCU->SVINTSTS = (flag)) + + + +/** + * @brief Control the behavior of non-secure monitor when CPU is in idle state. + * + * @param[in] opt Option for behavior control of non-secure monitor when CPU in idle. + * - true The counter keeps counting when CPU is in idle. + - false The counter will stop when CPU is in idle. + * + * @return None + * + * @details To control non-secure monitor counter when CPU is in idle. + * + */ +#define SCU_NSM_IDLE_ON(opt) ((opt)?(SCU->NSMCTL |= SCU_NSMCTL_IDLEON_Msk):(SCU->NSMCTL &= ~SCU_NSMCTL_IDLEON_Msk)) + +/** + * @brief Control the behavior of non-secure monitor when CPU is in debug state. + * + * @param[in] opt Option for behavior control of non-secure monitor when CPU in debug. + * - true The counter keeps counting when CPU is in debug. + - false The counter will stop when CPU is in debug. + * + * @return None + * + * @details To control non-secure monitor counter when CPU is in debug. + * + */ +#define SCU_NSM_DBG_ON(opt) ((opt)?(SCU->NSMCTL |= SCU_NSMCTL_DBGON_Msk):(SCU->NSMCTL &= ~SCU_NSMCTL_DBGON_Msk)) + + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SCU_NSMConfig(uint32_t u32Ticks, uint32_t u32Prescale); +__STATIC_INLINE void SCU_TimerConfig(uint32_t u32Ticks, uint32_t u32Prescale); + + +/** + * @brief Config non-secure monitor to detect timeout in non-secure state. + * + * @param[in] u32Ticks A specified period for timeout in non-secure state + * @param[in] u32Prescale A pre-scale divider to non-secure monitor clock + + * + * @return None + * + * @details This function is used to configure non-secure monitor. If the CPU state stay in non-secure state for + * a specified period. The non-secure monitor will timeout and assert an interrupt. Otherwise, the + * non-secure monitor will auto clear whenever returning to secure state. This could be used to avoid + * CPU state in non-secure state too long time for security purpose. User must enable SCU_IRQn if interrupt + * is necessary. + * + */ +__STATIC_INLINE void SCU_NSMConfig(uint32_t u32Ticks, uint32_t u32Prescale) +{ + + SCU->NSMLOAD = u32Ticks; + SCU->NSMVAL = 0ul; + SCU->NSMCTL = SCU_NSMCTL_AUTORLD_Msk | SCU_NSMCTL_NSMIEN_Msk | (u32Prescale & 0xfful); +} + + +/** + * @brief Config non-secure monitor to be a timer. + * + * @param[in] u32Ticks A specified period for timer interrupt. + * @param[in] u32Prescale A pre-scale divider to timer clock source. + + * + * @return None + * + * @details This function is used to configure non-secure monitor as a timer. In other words, the timer counter + * keeps counting even CPU is in secure state. + * + */ +__STATIC_INLINE void SCU_TimerConfig(uint32_t u32Ticks, uint32_t u32Prescale) +{ + + SCU->NSMLOAD = u32Ticks; + SCU->NSMVAL = 0ul; + SCU->NSMCTL = SCU_NSMCTL_AUTORLD_Msk | SCU_NSMCTL_NSMIEN_Msk | SCU_NSMCTL_TMRMOD_Msk | (u32Prescale & 0xfful); +} + + + + +/**@}*/ /* end of group SCU_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SCU_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SCU_H__ */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_scuart.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_scuart.h new file mode 100644 index 0000000000..7ddf8f91f9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_scuart.h @@ -0,0 +1,355 @@ +/**************************************************************************//** + * @file scuart.h + * @version V3.00 + * @brief Smartcard UART mode (SCUART) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SCUART_H__ +#define __SCUART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + +/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants + @{ +*/ +#define SCUART_CHAR_LEN_5 (0x3UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */ +#define SCUART_CHAR_LEN_6 (0x2UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */ +#define SCUART_CHAR_LEN_7 (0x1UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */ +#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */ + +#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */ +#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */ +#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */ + +#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */ +#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */ + +/**@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */ + + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/* TX Macros */ +/** + * @brief Write Data to Tx data register + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details By writing data to DAT register, the SC will send out an 8-bit data. + * \hideinitializer + */ +#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief Get Tx FIFO empty flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty + * + * @details When the last byte of Tx buffer has been transferred to Transmitter Shift Register, hardware sets TXEMPTY (SC_STATUS[9]) high. + * It will be cleared when writing data into DAT (SC_DAT[7:0]). + * \hideinitializer + */ +#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk) + +/** + * @brief Get Tx FIFO full flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full + * + * @details TXFULL (SC_STATUS[10]) is set when Tx buffer counts equals to 4, otherwise is cleared by hardware. + * \hideinitializer + */ +#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk) + +/** + * @brief Wait specified smartcard port transmission complete + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @details TXACT (SC_STATUS[31]) is cleared automatically when Tx transfer is finished or the last byte transmission has completed. + * + * @note This macro blocks until transmit complete. + * \hideinitializer + */ +#define SCUART_WAIT_TX_EMPTY(sc) while(((sc)->STATUS & SC_STATUS_TXACT_Msk) == SC_STATUS_TXACT_Msk) + +/** + * @brief Check specified smartcard port transmit FIFO is full or not + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval 1 Transmit FIFO is full + * + * @details TXFULL (SC_STATUS[10]) indicates Tx buffer full or not. + * This bit is set when Tx buffer counts equals to 4, otherwise is cleared by hardware. + * \hideinitializer + */ +#define SCUART_IS_TX_FULL(sc) (((sc)->STATUS & SC_STATUS_TXFULL_Msk)? 1 : 0) + +/** + * @brief Check specified smartcard port transmission is over + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit complete status + * @retval 0 Transmit is not complete + * @retval 1 Transmit complete + * + * @details TXACT (SC_STATUS[31]) indicates Tx Transmit is complete or not. + * \hideinitializer + */ +#define SCUART_IS_TX_EMPTY(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 0 : 1) + +/** + * @brief Check specified smartcard port transmit FIFO empty status + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval 1 Transmit FIFO is empty + * + * @details TXEMPTY (SC_STATUS[9]) is set by hardware when the last byte of Tx buffer has been transferred to Transmitter Shift Register. + * \hideinitializer + */ +#define SCUART_IS_TX_FIFO_EMPTY(sc) (((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)? 1 : 0) + +/** + * @brief Check specified Smartcard port Transmission Status + * + * @param[in] sc The pointer of smartcard module. + * + * @retval 0 Transmit is completed + * @retval 1 Transmit is active + * + * @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted. + * \hideinitializer + */ +#define SCUART_IS_TX_ACTIVE(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0) + + +/* RX Macros */ +/** + * @brief Read Rx data register + * + * @param[in] sc The pointer of smartcard module. + * + * @return The oldest data byte in RX FIFO + * + * @details By reading DAT register, the SC will return an 8-bit received data. + * \hideinitializer + */ +#define SCUART_READ(sc) ((sc)->DAT) + +/** + * @brief Get Rx FIFO empty flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO empty status + * @retval 0 Receive FIFO is not empty + * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty + * + * @details When the last byte of Rx buffer has been read by CPU, hardware sets RXEMPTY (SC_STATUS[1]) high. + * It will be cleared when SC receives any new data. + * \hideinitializer + */ +#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk) + +/** + * @brief Get Rx FIFO full flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval SC_STATUS_TXFULL_Msk Receive FIFO is full + * + * @details RXFULL (SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware. + * \hideinitializer + */ +#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk) + +/** + * @brief Check if receive data number in FIFO reach FIFO trigger level or not + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO data status + * @retval 0 The number of bytes in receive FIFO is less than trigger level + * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level + * + * @details RDAIF (SC_INTSTS[0]) is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag. + * + * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO. + * \hideinitializer + */ +#define SCUART_IS_RX_READY(sc) (((sc)->INTSTS & SC_INTSTS_RDAIF_Msk)? 1 : 0) + +/** + * @brief Check specified smartcard port receive FIFO is full or not + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval 1 Receive FIFO is full + * + * @details RXFULLF( SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware. + * \hideinitializer + */ +#define SCUART_IS_RX_FULL(sc) (((sc)->STATUS & SC_STATUS_RXFULL_Msk)? 1 : 0) + + +/* Interrupt Macros */ +/** + * @brief Enable specified interrupts + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Interrupt masks to enable, a combination of following bits, + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * + * @return None + * + * @details The macro is used to enable receiver buffer time-out interrupt, transfer error interrupt, + * transmit buffer empty interrupt or receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask)) + +/** + * @brief Disable specified interrupts + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Interrupt masks to disable, a combination of following bits, + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * + * @return None + * + * @details The macro is used to disable receiver buffer time-out interrupt, transfer error interrupt, + * transmit buffer empty interrupt or receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Type Interrupt flag/status to check, could be one of following value + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * - \ref SC_INTSTS_RDAIF_Msk + * + * @return The status of specified interrupt + * @retval 0 Specified interrupt does not happened + * @retval 1 Specified interrupt happened + * + * @details The macro is used to get receiver buffer time-out interrupt status, transfer error interrupt status, + * transmit buffer empty interrupt status or receive data reach interrupt status. + * \hideinitializer + */ +#define SCUART_GET_INT_FLAG(sc, u32Type) (((sc)->INTSTS & (u32Type))? 1 : 0) + +/** + * @brief Clear specified interrupt flag/status + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Type Interrupt flag/status to clear, only \ref SC_INTSTS_TERRIF_Msk valid for this macro. + * + * @return None + * + * @details The macro is used to clear transfer error interrupt flag. + * \hideinitializer + */ +#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type)) + +/** + * @brief Get receive error flag/status + * + * @param[in] sc The pointer of smartcard module. + * + * @return Current receive error status, could one of following errors: + * @retval SC_STATUS_PEF_Msk Parity error + * @retval SC_STATUS_FEF_Msk Frame error + * @retval SC_STATUS_BEF_Msk Break error + * + * @details The macro is used to get receiver parity error status, frame error status or break error status. + * \hideinitializer + */ +#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk)) + +/** + * @brief Clear specified receive error flag/status + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Receive error flag/status to clear, combination following values + * - \ref SC_STATUS_PEF_Msk + * - \ref SC_STATUS_FEF_Msk + * - \ref SC_STATUS_BEF_Msk + * + * @return None + * + * @details The macro is used to clear receiver parity error flag, frame error flag or break error flag. + * \hideinitializer + */ +#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask)) + +void SCUART_Close(SC_T* sc); +uint32_t SCUART_Open(SC_T* sc, uint32_t u32Baudrate); +uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits); +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC); +void SCUART_Write(SC_T* sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + +/**@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SCUART_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SCUART_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_sdh.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_sdh.h new file mode 100644 index 0000000000..32b2554934 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_sdh.h @@ -0,0 +1,204 @@ +/**************************************************************************//** + * @file sdh.h + * @version V1.00 + * @brief M2354 SDH driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __SDH_H__ +#define __SDH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + + +/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants + @{ +*/ + +#define SDH_ERR_ID 0xFFFF0100UL /*!< SDH error ID \hideinitializer */ + +#define SDH_TIMEOUT (SDH_ERR_ID|0x01UL) /*!< Timeout \hideinitializer */ +#define SDH_NO_MEMORY (SDH_ERR_ID|0x02UL) /*!< OOM \hideinitializer */ + +/* -- function return value */ +#define Successful 0U /*!< Success \hideinitializer */ +#define Fail 1U /*!< Failed \hideinitializer */ + +/* --- define type of SD card or MMC */ +#define SDH_TYPE_UNKNOWN 0UL /*!< Unknown card type \hideinitializer */ +#define SDH_TYPE_SD_HIGH 1UL /*!< SDHC card \hideinitializer */ +#define SDH_TYPE_SD_LOW 2UL /*!< SD card \hideinitializer */ +#define SDH_TYPE_MMC 3UL /*!< MMC card \hideinitializer */ +#define SDH_TYPE_EMMC 4UL /*!< eMMC card \hideinitializer */ + +/* SD error */ +#define SDH_NO_SD_CARD (SDH_ERR_ID|0x10UL) /*!< Card removed \hideinitializer */ +#define SDH_ERR_DEVICE (SDH_ERR_ID|0x11UL) /*!< Device error \hideinitializer */ +#define SDH_INIT_TIMEOUT (SDH_ERR_ID|0x12UL) /*!< Card init timeout \hideinitializer */ +#define SDH_SELECT_ERROR (SDH_ERR_ID|0x13UL) /*!< Card select error \hideinitializer */ +#define SDH_WRITE_PROTECT (SDH_ERR_ID|0x14UL) /*!< Card write protect \hideinitializer */ +#define SDH_INIT_ERROR (SDH_ERR_ID|0x15UL) /*!< Card init error \hideinitializer */ +#define SDH_CRC7_ERROR (SDH_ERR_ID|0x16UL) /*!< CRC 7 error \hideinitializer */ +#define SDH_CRC16_ERROR (SDH_ERR_ID|0x17UL) /*!< CRC 16 error \hideinitializer */ +#define SDH_CRC_ERROR (SDH_ERR_ID|0x18UL) /*!< CRC error \hideinitializer */ +#define SDH_CMD8_ERROR (SDH_ERR_ID|0x19UL) /*!< Command 8 error \hideinitializer */ + +#define MMC_FREQ 20000UL /*!< output 20MHz to MMC \hideinitializer */ +#define SD_FREQ 25000UL /*!< output 25MHz to SD \hideinitializer */ +#define SDHC_FREQ 50000UL /*!< output 50MHz to SDH \hideinitializer */ + +#define CardDetect_From_GPIO (1UL << 8) /*!< Card detection pin is GPIO \hideinitializer */ +#define CardDetect_From_DAT3 (1UL << 9) /*!< Card detection pin is DAT3 \hideinitializer */ + +/**@}*/ /* end of group SDH_EXPORTED_CONSTANTS */ + +/** @addtogroup SDH_EXPORTED_TYPEDEF SDH Exported Type Defines + @{ +*/ +#if defined ( __ARMCC_VERSION ) +#pragma pack(push) +#pragma pack(1) +#endif +typedef struct SDH_info_t +{ + unsigned int CardType; /*!< SDHC, SD, or MMC */ + unsigned int RCA; /*!< Relative card address */ + unsigned char IsCardInsert; /*!< Card insert state */ + unsigned int totalSectorN; /*!< Total sector number */ + unsigned int diskSize; /*!< Disk size in K bytes */ + int sectorSize; /*!< Sector size in bytes */ +} SDH_INFO_T; /*!< Structure holds SD card info */ +#if defined ( __ARMCC_VERSION ) +#pragma pack(pop) +#endif +/**@}*/ /* end of group SDH_EXPORTED_TYPEDEF */ + +/** @cond HIDDEN_SYMBOLS */ +extern SDH_INFO_T SD0; +extern uint8_t volatile g_u8SDDataReadyFlag; +extern uint8_t g_u8R3Flag; + +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ + +/** + * @brief Enable specified interrupt. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_CDSRC_Msk / \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / + * \ref SDH_INTEN_WKIEN_Msk + * + * @return None. + * \hideinitializer + */ +#define SDH_ENABLE_INT(sdh, u32IntMask) ((sdh)->INTEN |= (u32IntMask)) + +/** + * @brief Disable specified interrupt. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC_Msk / + * + * @return None. + * \hideinitializer + */ +#define SDH_DISABLE_INT(sdh, u32IntMask) ((sdh)->INTEN &= ~(u32IntMask)) + +/** + * @brief Get specified interrupt flag/status. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk / + * \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk / + * \ref SDH_INTSTS_CDIF_Msk / \ref SDH_INTSTS_RTOIF_Msk / + * \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS_Msk / + * \ref SDH_INTSTS_DAT1STS_Msk + * + * + * @return 0 = The specified interrupt is not happened. + * 1 = The specified interrupt is happened. + * \hideinitializer + */ +#define SDH_GET_INT_FLAG(sdh, u32IntMask) (((sdh)->INTSTS & (u32IntMask))?1:0) + + +/** + * @brief Clear specified interrupt flag/status. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF_Msk / + * \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk + * + * + * @return None. + * \hideinitializer + */ +#define SDH_CLR_INT_FLAG(sdh, u32IntMask) ((sdh)->INTSTS = (u32IntMask)) + + +/** + * @brief Check SD Card inserted or removed. + * + * @param[in] sdh The pointer of the specified SDH module. + * + * @return 1: Card inserted. + * 0: Card removed. + * \hideinitializer + */ +#define SDH_IS_CARD_PRESENT(sdh) ((((sdh) == SDH0)||((sdh) == SDH0_NS))? SD0.IsCardInsert : 0) + +/** + * @brief Get SD Card capacity. + * + * @param[in] sdh The pointer of the specified SDH module. + * + * @return SD Card capacity. (unit: KByte) + * \hideinitializer + */ +#define SDH_GET_CARD_CAPACITY(sdh) ((((sdh) == SDH0)||((sdh) == SDH0_NS))? SD0.diskSize : 0) + + +void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc); +uint32_t SDH_Probe(SDH_T *sdh); +uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); +uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); + +uint32_t SDH_CardDetection(SDH_T *sdh); +void SDH_Open_Disk(SDH_T *sdh, uint32_t u32CardDetSrc); +void SDH_Close_Disk(SDH_T *sdh); + +/**@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SDH_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* end of __SDH_H__ */ +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_spi.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_spi.h new file mode 100644 index 0000000000..d4194ddaa6 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_spi.h @@ -0,0 +1,584 @@ +/****************************************************************************** + * @file spi.h + * @version V3.00 + * @brief M2354 series SPI driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants + @{ +*/ + +#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */ +#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */ +#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */ +#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */ + +#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */ +#define SPI_MASTER (0x0UL) /*!< Set as master */ + +#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS */ +#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */ +#define SPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low */ + +/* SPI Interrupt Mask */ +#define SPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask */ +#define SPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask */ +#define SPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask */ +#define SPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask */ +#define SPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask */ +#define SPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask */ +#define SPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask */ +#define SPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask */ +#define SPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask */ +#define SPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask */ + +/* SPI Status Mask */ +#define SPI_BUSY_MASK (0x01UL) /*!< Busy status mask */ +#define SPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask */ +#define SPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask */ +#define SPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask */ +#define SPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask */ +#define SPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask */ +#define SPI_SPIEN_STS_MASK (0x40UL) /*!< SPIEN status mask */ +#define SPI_SSLINE_STS_MASK (0x80UL) /*!< SPIx_SS line status mask */ + +/* SPI Status2 Mask */ +#define SPI_SLVBENUM_MASK (0x01UL) /*!< Effective bit number of uncompleted RX data status mask */ + + +/* I2S Data Width */ +#define SPII2S_DATABIT_8 (0UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit */ +#define SPII2S_DATABIT_16 (1UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit */ +#define SPII2S_DATABIT_24 (2UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit */ +#define SPII2S_DATABIT_32 (3UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit */ + +/* I2S Audio Format */ +#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel */ +#define SPII2S_STEREO (0UL) /*!< Stereo channel */ + +/* I2S Data Format */ +#define SPII2S_FORMAT_I2S (0UL << SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format */ +#define SPII2S_FORMAT_MSB (1UL << SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format */ +#define SPII2S_FORMAT_PCMA (2UL << SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format */ +#define SPII2S_FORMAT_PCMB (3UL << SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format */ + +/* I2S Operation mode */ +#define SPII2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode */ +#define SPII2S_MODE_MASTER (0UL) /*!< As master mode */ + +/* I2S TX FIFO Threshold */ +#define SPII2S_FIFO_TX_LEVEL_WORD_0 (0UL) /*!< TX threshold is 0 word */ +#define SPII2S_FIFO_TX_LEVEL_WORD_1 (1UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 1 word */ +#define SPII2S_FIFO_TX_LEVEL_WORD_2 (2UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 2 words */ +#define SPII2S_FIFO_TX_LEVEL_WORD_3 (3UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 3 words */ +/* I2S RX FIFO Threshold */ +#define SPII2S_FIFO_RX_LEVEL_WORD_1 (0UL) /*!< RX threshold is 1 word */ +#define SPII2S_FIFO_RX_LEVEL_WORD_2 (1UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 2 words */ +#define SPII2S_FIFO_RX_LEVEL_WORD_3 (2UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 3 words */ +#define SPII2S_FIFO_RX_LEVEL_WORD_4 (3UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 4 words */ + +/* I2S Record Channel */ +#define SPII2S_MONO_RIGHT (0UL) /*!< Record mono right channel */ +#define SPII2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel */ + +/* I2S Channel */ +#define SPII2S_RIGHT (0UL) /*!< Select right channel */ +#define SPII2S_LEFT (1UL) /*!< Select left channel */ + +/* I2S Interrupt Mask */ +#define SPII2S_FIFO_TXTH_INT_MASK (0x01UL) /*!< TX FIFO threshold interrupt mask */ +#define SPII2S_FIFO_RXTH_INT_MASK (0x02UL) /*!< RX FIFO threshold interrupt mask */ +#define SPII2S_FIFO_RXOV_INT_MASK (0x04UL) /*!< RX FIFO overrun interrupt mask */ +#define SPII2S_FIFO_RXTO_INT_MASK (0x08UL) /*!< RX FIFO time-out interrupt mask */ +#define SPII2S_TXUF_INT_MASK (0x10UL) /*!< TX FIFO underflow interrupt mask */ +#define SPII2S_RIGHT_ZC_INT_MASK (0x20UL) /*!< Right channel zero cross interrupt mask */ +#define SPII2S_LEFT_ZC_INT_MASK (0x40UL) /*!< Left channel zero cross interrupt mask */ +#define SPII2S_SLAVE_ERR_INT_MASK (0x80UL) /*!< Bit clock loss interrupt mask */ + +/**@}*/ /* end of group SPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag. + */ +#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk ) + +/** + * @brief Disable Slave 3-wire mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear SLV3WIRE bit of SPI_SSCTL register to disable Slave 3-wire mode. + */ +#define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable Slave 3-wire mode. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set SLV3WIRE bit of SPI_SSCTL register to enable Slave 3-wire mode. + */ +#define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Trigger RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function. + */ +#define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Trigger TX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function. + */ +#define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to enable TX and RX PDMA transfer function. + */ +#define SPI_TRIGGER_TX_RX_PDMA(spi) ( (spi)->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function. + */ +#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function. + */ +#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of SPI_PDMACTL register to disable TX and RX PDMA transfer function. + */ +#define SPI_DISABLE_TX_RX_PDMA(spi) ( (spi)->PDMACTL &= ~(SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk) ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] spi The pointer of the specified SPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO. + */ +#define SPI_GET_RX_FIFO_COUNT(spi) ( ((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos ) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag. + */ +#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) >> SPI_STATUS_RXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag. + */ +#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) >> SPI_STATUS_TXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag. + */ +#define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) >> SPI_STATUS_TXFULL_Pos ) + +/** + * @brief Get the datum read from RX register. + * @param[in] spi The pointer of the specified SPI module. + * @return Data in RX register. + * @details Read SPI_RX register to get the received datum. + */ +#define SPI_READ_RX(spi) ( (spi)->RX ) + +/** + * @brief Write datum to TX register. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through SPI bus. + * @return None. + * @details Write u32TxData to SPI_TX register. + */ +#define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = (u32TxData) ) + +/** + * @brief Set SPIx_SS pin to high state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to high state. + */ +#define SPI_SET_SS_HIGH(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk) ) + +/** + * @brief Set SPIx_SS pin to low state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to low state. + */ +#define SPI_SET_SS_LOW(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk ) + +/** + * @brief Enable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]). + */ +#define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk ) + +/** + * @brief Disable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function. + */ +#define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk ) + +/** + * @brief Set the length of suspend interval. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle). + */ +#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos) ) + +/** + * @brief Set the SPI transfer sequence with LSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first. + */ +#define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk ) + +/** + * @brief Set the SPI transfer sequence with MSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first. + */ +#define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk ) + +/** + * @brief Set the data width of a SPI transaction. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + */ +#define SPI_SET_DATA_WIDTH(spi, u32Width) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << SPI_CTL_DWIDTH_Pos) ) + +/** + * @brief Get the SPI busy state. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 SPI controller is not busy. + * @retval 1 SPI controller is busy. + * @details This macro will return the busy state of SPI controller. + */ +#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk) >> SPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller. + */ +#define SPI_ENABLE(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk ) + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller. + */ +#define SPI_DISABLE(spi) ( (spi)->CTL &= ~SPI_CTL_SPIEN_Msk ) + +/** + * @brief Enable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Disable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Enable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA. + */ +#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function. + */ +#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA. + */ +#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function. + */ +#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function. + */ +#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Disable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function. + */ +#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Enable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function. + */ +#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Disable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function. + */ +#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Enable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function. + */ +#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Disable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function. + */ +#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Clear TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point. + */ +#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk ) + +/** + * @brief Clear RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point. + */ +#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref SPII2S_MONO_LEFT + * - \ref SPII2S_MONO_RIGHT + * @return None + * @details This function selects the recording source channel of monaural mode. + */ +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch) +{ + u32Ch == SPII2S_MONO_LEFT ? + (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) : + (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk); +} + +/** + * @brief Write data to I2S TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Data The value written to TX FIFO. + * @return None + * @details This macro will write a value to TX FIFO. + */ +#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) ) + +/** + * @brief Read RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return The value read from RX FIFO. + * @details This function will return a value read from RX FIFO. + */ +#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX ) + +/** + * @brief Get the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return The interrupt flags specified by the u32mask parameter. + * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter. + */ +#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) ) + +/** + * @brief Clear the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return None + * @details This macro will clear the interrupt flags specified by the u32mask parameter. + * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself. + */ +#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return TX FIFO level + * @details This macro will return the number of available words in TX FIFO. + */ +#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return RX FIFO level + * @details This macro will return the number of available words in RX FIFO. + */ +#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos ) + +/* Function prototype declaration */ +uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void SPI_Close(SPI_T *spi); +void SPI_ClearRxFIFO(SPI_T *spi); +void SPI_ClearTxFIFO(SPI_T *spi); +void SPI_DisableAutoSS(SPI_T *spi); +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock); +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t SPI_GetBusClock(SPI_T *spi); +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask); +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask); +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetStatus2(SPI_T *spi, uint32_t u32Mask); + +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat); +void SPII2S_Close(SPI_T *i2s); +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask); +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask); +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock); +void SPII2S_DisableMCLK(SPI_T *i2s); +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); + + +/**@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SPI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPI_H__ */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_sys.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_sys.h new file mode 100644 index 0000000000..3a84003b19 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_sys.h @@ -0,0 +1,4316 @@ +/**************************************************************************//** + * @file sys.h + * @version V3 + * @brief M2354 series System Manager (SYS) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __SYS_H__ +#define __SYS_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + +/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Module Reset Control Resister constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA0_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA0RST_Pos) /*!< PDMA0 reset is one of the SYS_ResetModule parameter */ +#define EBI_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_EBIRST_Pos) /*!< EBI reset is one of the SYS_ResetModule parameter */ +#define USBH_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_USBHRST_Pos) /*!< USBH reset is one of the SYS_ResetModule parameter */ +#define SDH0_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_SDH0RST_Pos) /*!< SDH0 reset is one of the SYS_ResetModule parameter */ +#define CRC_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRCRST_Pos) /*!< CRC reset is one of the SYS_ResetModule parameter */ +#define CRPT_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRPTRST_Pos) /*!< CRPT reset is one of the SYS_ResetModule parameter */ +#define KS_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_KSRST_Pos) /*!< KS reset is one of the SYS_ResetModule parameter */ +#define PDMA1_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA1RST_Pos) /*!< PDMA1 reset is one of the SYS_ResetModule parameter */ + +#define GPIO_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_GPIORST_Pos) /*!< GPIO reset is one of the SYS_ResetModule parameter */ +#define TMR0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR0RST_Pos) /*!< TMR0 reset is one of the SYS_ResetModule parameter */ +#define TMR1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR1RST_Pos) /*!< TMR1 reset is one of the SYS_ResetModule parameter */ +#define TMR2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR2RST_Pos) /*!< TMR2 reset is one of the SYS_ResetModule parameter */ +#define TMR3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR3RST_Pos) /*!< TMR3 reset is one of the SYS_ResetModule parameter */ +#define TMR4_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_TMR4RST_Pos) /*!< TMR4 reset is one of the SYS_ResetModule parameter */ +#define TMR5_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_TMR5RST_Pos) /*!< TMR5 reset is one of the SYS_ResetModule parameter */ + +#define ACMP01_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_ACMP01RST_Pos) /*!< ACMP01 reset is one of the SYS_ResetModule parameter */ +#define I2C0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C0RST_Pos) /*!< I2C0 reset is one of the SYS_ResetModule parameter */ +#define I2C1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C1RST_Pos) /*!< I2C1 reset is one of the SYS_ResetModule parameter */ +#define I2C2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C2RST_Pos) /*!< I2C2 reset is one of the SYS_ResetModule parameter */ +#define QSPI0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_QSPI0RST_Pos) /*!< QSPI0 reset is one of the SYS_ResetModule parameter */ +#define SPI0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI0RST_Pos) /*!< SPI0 reset is one of the SYS_ResetModule parameter */ +#define SPI1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI1RST_Pos) /*!< SPI1 reset is one of the SYS_ResetModule parameter */ +#define SPI2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI2RST_Pos) /*!< SPI2 reset is one of the SYS_ResetModule parameter */ +#define UART0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART0RST_Pos) /*!< UART0 reset is one of the SYS_ResetModule parameter */ +#define UART1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART1RST_Pos) /*!< UART1 reset is one of the SYS_ResetModule parameter */ +#define UART2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART2RST_Pos) /*!< UART2 reset is one of the SYS_ResetModule parameter */ +#define UART3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART3RST_Pos) /*!< UART3 reset is one of the SYS_ResetModule parameter */ +#define UART4_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART4RST_Pos) /*!< UART4 reset is one of the SYS_ResetModule parameter */ +#define UART5_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART5RST_Pos) /*!< UART5 reset is one of the SYS_ResetModule parameter */ +#define CAN0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_CAN0RST_Pos) /*!< CAN0 reset is one of the SYS_ResetModule parameter */ +#define OTG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_OTGRST_Pos) /*!< OTG reset is one of the SYS_ResetModule parameter */ +#define USBD_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_USBDRST_Pos) /*!< USBD reset is one of the SYS_ResetModule parameter */ +#define EADC_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_EADCRST_Pos) /*!< EADC reset is one of the SYS_ResetModule parameter */ +#define I2S0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2S0RST_Pos) /*!< I2S0 reset is one of the SYS_ResetModule parameter */ +#define LCD_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_LCDRST_Pos) /*!< LCD reset is one of the SYS_ResetModule parameter */ +#define TRNG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TRNGRST_Pos) /*!< TRNG reset is one of the SYS_ResetModule parameter */ + +#define SC0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC0RST_Pos) /*!< SC0 reset is one of the SYS_ResetModule parameter */ +#define SC1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC1RST_Pos) /*!< SC1 reset is one of the SYS_ResetModule parameter */ +#define SC2_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC2RST_Pos) /*!< SC2 reset is one of the SYS_ResetModule parameter */ +#define SPI3_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SPI3RST_Pos) /*!< SPI3 reset is one of the SYS_ResetModule parameter */ +#define USCI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI0RST_Pos) /*!< USCI0 reset is one of the SYS_ResetModule parameter */ +#define USCI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI1RST_Pos) /*!< USCI1 reset is one of the SYS_ResetModule parameter */ +#define DAC_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_DACRST_Pos) /*!< DAC reset is one of the SYS_ResetModule parameter */ +#define EPWM0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM0RST_Pos) /*!< EPWM0 reset is one of the SYS_ResetModule parameter */ +#define EPWM1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM1RST_Pos) /*!< EPWM1 reset is one of the SYS_ResetModule parameter */ +#define BPWM0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM0RST_Pos) /*!< BPWM0 reset is one of the SYS_ResetModule parameter */ +#define BPWM1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM1RST_Pos) /*!< BPWM1 reset is one of the SYS_ResetModule parameter */ +#define QEI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI0RST_Pos) /*!< QEI0 reset is one of the SYS_ResetModule parameter */ +#define QEI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI1RST_Pos) /*!< QEI1 reset is one of the SYS_ResetModule parameter */ +#define ECAP0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP0RST_Pos) /*!< ECAP0 reset is one of the SYS_ResetModule parameter */ +#define ECAP1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP1RST_Pos) /*!< ECAP1 reset is one of the SYS_ResetModule parameter */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brown Out Detector Threshold Voltage Selection constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_BODCTL_BOD_RST_EN (1UL<GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk)) | SYS_GPA_MFPL_PA0MFP_UART0_RXD; + SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA1MFP_Msk)) | SYS_GPA_MFPL_PA1MFP_UART0_TXD; +*/ + + +/* PA.0 MFP */ +#define SYS_GPA_MFPL_PA0MFP_GPIO (0x0UL<GPB_MFPL = (SYS->GPB_MFPL & (~ACMP0_N_PB3_Msk)) | ACMP0_N_PB3 /*!< Set PB3 function to ACMP0_N */ +#define SET_ACMP0_O_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP0_O_PB7_Msk)) | ACMP0_O_PB7 /*!< Set PB7 function to ACMP0_O */ +#define SET_ACMP0_O_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~ACMP0_O_PC1_Msk)) | ACMP0_O_PC1 /*!< Set PC1 function to ACMP0_O */ +#define SET_ACMP0_O_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ACMP0_O_PC12_Msk)) | ACMP0_O_PC12 /*!< Set PC12 function to ACMP0_O */ +#define SET_ACMP0_P0_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ACMP0_P0_PA11_Msk)) | ACMP0_P0_PA11 /*!< Set PA11 function to ACMP0_P0 */ +#define SET_ACMP0_P1_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP0_P1_PB2_Msk)) | ACMP0_P1_PB2 /*!< Set PB2 function to ACMP0_P1 */ +#define SET_ACMP0_P2_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP0_P2_PB12_Msk)) | ACMP0_P2_PB12 /*!< Set PB12 function to ACMP0_P2 */ +#define SET_ACMP0_P3_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP0_P3_PB13_Msk)) | ACMP0_P3_PB13 /*!< Set PB13 function to ACMP0_P3 */ +#define SET_ACMP0_WLAT_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~ACMP0_WLAT_PA7_Msk)) | ACMP0_WLAT_PA7 /*!< Set PA7 function to ACMP0_WLAT */ +#define SET_ACMP1_N_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP1_N_PB5_Msk)) | ACMP1_N_PB5 /*!< Set PB5 function to ACMP1_N */ +#define SET_ACMP1_O_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP1_O_PB6_Msk)) | ACMP1_O_PB6 /*!< Set PB6 function to ACMP1_O */ +#define SET_ACMP1_O_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ACMP1_O_PC11_Msk)) | ACMP1_O_PC11 /*!< Set PC11 function to ACMP1_O */ +#define SET_ACMP1_O_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~ACMP1_O_PC0_Msk)) | ACMP1_O_PC0 /*!< Set PC0 function to ACMP1_O */ +#define SET_ACMP1_P0_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ACMP1_P0_PA10_Msk)) | ACMP1_P0_PA10 /*!< Set PA10 function to ACMP1_P0 */ +#define SET_ACMP1_P1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP1_P1_PB4_Msk)) | ACMP1_P1_PB4 /*!< Set PB4 function to ACMP1_P1 */ +#define SET_ACMP1_P2_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP1_P2_PB12_Msk)) | ACMP1_P2_PB12 /*!< Set PB12 function to ACMP1_P2 */ +#define SET_ACMP1_P3_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP1_P3_PB13_Msk)) | ACMP1_P3_PB13 /*!< Set PB13 function to ACMP1_P3 */ +#define SET_ACMP1_WLAT_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~ACMP1_WLAT_PA6_Msk)) | ACMP1_WLAT_PA6 /*!< Set PA6 function to ACMP1_WLAT */ +#define SET_BPWM0_CH0_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH0_PA0_Msk)) | BPWM0_CH0_PA0 /*!< Set PA0 function to BPWM0_CH0 */ +#define SET_BPWM0_CH0_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH0_PA11_Msk)) | BPWM0_CH0_PA11 /*!< Set PA11 function to BPWM0_CH0 */ +#define SET_BPWM0_CH0_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH0_PE2_Msk)) | BPWM0_CH0_PE2 /*!< Set PE2 function to BPWM0_CH0 */ +#define SET_BPWM0_CH0_PG14() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH0_PG14_Msk)) | BPWM0_CH0_PG14 /*!< Set PG14 function to BPWM0_CH0 */ +#define SET_BPWM0_CH1_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH1_PA1_Msk)) | BPWM0_CH1_PA1 /*!< Set PA1 function to BPWM0_CH1 */ +#define SET_BPWM0_CH1_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH1_PE3_Msk)) | BPWM0_CH1_PE3 /*!< Set PE3 function to BPWM0_CH1 */ +#define SET_BPWM0_CH1_PG13() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH1_PG13_Msk)) | BPWM0_CH1_PG13 /*!< Set PG13 function to BPWM0_CH1 */ +#define SET_BPWM0_CH1_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH1_PA10_Msk)) | BPWM0_CH1_PA10 /*!< Set PA10 function to BPWM0_CH1 */ +#define SET_BPWM0_CH2_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH2_PE4_Msk)) | BPWM0_CH2_PE4 /*!< Set PE4 function to BPWM0_CH2 */ +#define SET_BPWM0_CH2_PG12() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH2_PG12_Msk)) | BPWM0_CH2_PG12 /*!< Set PG12 function to BPWM0_CH2 */ +#define SET_BPWM0_CH2_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH2_PA2_Msk)) | BPWM0_CH2_PA2 /*!< Set PA2 function to BPWM0_CH2 */ +#define SET_BPWM0_CH2_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH2_PA9_Msk)) | BPWM0_CH2_PA9 /*!< Set PA9 function to BPWM0_CH2 */ +#define SET_BPWM0_CH3_PG11() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH3_PG11_Msk)) | BPWM0_CH3_PG11 /*!< Set PG11 function to BPWM0_CH3 */ +#define SET_BPWM0_CH3_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH3_PA3_Msk)) | BPWM0_CH3_PA3 /*!< Set PA3 function to BPWM0_CH3 */ +#define SET_BPWM0_CH3_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH3_PA8_Msk)) | BPWM0_CH3_PA8 /*!< Set PA8 function to BPWM0_CH3 */ +#define SET_BPWM0_CH3_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH3_PE5_Msk)) | BPWM0_CH3_PE5 /*!< Set PE5 function to BPWM0_CH3 */ +#define SET_BPWM0_CH4_PG10() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH4_PG10_Msk)) | BPWM0_CH4_PG10 /*!< Set PG10 function to BPWM0_CH4 */ +#define SET_BPWM0_CH4_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH4_PA4_Msk)) | BPWM0_CH4_PA4 /*!< Set PA4 function to BPWM0_CH4 */ +#define SET_BPWM0_CH4_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~BPWM0_CH4_PC13_Msk)) | BPWM0_CH4_PC13 /*!< Set PC13 function to BPWM0_CH4 */ +#define SET_BPWM0_CH4_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH4_PE6_Msk)) | BPWM0_CH4_PE6 /*!< Set PE6 function to BPWM0_CH4 */ +#define SET_BPWM0_CH4_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM0_CH4_PF5_Msk)) | BPWM0_CH4_PF5 /*!< Set PF5 function to BPWM0_CH4 */ +#define SET_BPWM0_CH5_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH5_PA5_Msk)) | BPWM0_CH5_PA5 /*!< Set PA5 function to BPWM0_CH5 */ +#define SET_BPWM0_CH5_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH5_PE7_Msk)) | BPWM0_CH5_PE7 /*!< Set PE7 function to BPWM0_CH5 */ +#define SET_BPWM0_CH5_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM0_CH5_PF4_Msk)) | BPWM0_CH5_PF4 /*!< Set PF4 function to BPWM0_CH5 */ +#define SET_BPWM0_CH5_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~BPWM0_CH5_PD12_Msk)) | BPWM0_CH5_PD12 /*!< Set PD12 function to BPWM0_CH5 */ +#define SET_BPWM0_CH5_PG9() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH5_PG9_Msk)) | BPWM0_CH5_PG9 /*!< Set PG9 function to BPWM0_CH5 */ +#define SET_BPWM1_CH0_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH0_PB11_Msk)) | BPWM1_CH0_PB11 /*!< Set PB11 function to BPWM1_CH0 */ +#define SET_BPWM1_CH0_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~BPWM1_CH0_PC7_Msk)) | BPWM1_CH0_PC7 /*!< Set PC7 function to BPWM1_CH0 */ +#define SET_BPWM1_CH0_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH0_PF0_Msk)) | BPWM1_CH0_PF0 /*!< Set PF0 function to BPWM1_CH0 */ +#define SET_BPWM1_CH0_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH0_PF3_Msk)) | BPWM1_CH0_PF3 /*!< Set PF3 function to BPWM1_CH0 */ +#define SET_BPWM1_CH1_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~BPWM1_CH1_PC6_Msk)) | BPWM1_CH1_PC6 /*!< Set PC6 function to BPWM1_CH1 */ +#define SET_BPWM1_CH1_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH1_PF1_Msk)) | BPWM1_CH1_PF1 /*!< Set PF1 function to BPWM1_CH1 */ +#define SET_BPWM1_CH1_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH1_PF2_Msk)) | BPWM1_CH1_PF2 /*!< Set PF2 function to BPWM1_CH1 */ +#define SET_BPWM1_CH1_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH1_PB10_Msk)) | BPWM1_CH1_PB10 /*!< Set PB10 function to BPWM1_CH1 */ +#define SET_BPWM1_CH2_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH2_PB9_Msk)) | BPWM1_CH2_PB9 /*!< Set PB9 function to BPWM1_CH2 */ +#define SET_BPWM1_CH2_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM1_CH2_PA7_Msk)) | BPWM1_CH2_PA7 /*!< Set PA7 function to BPWM1_CH2 */ +#define SET_BPWM1_CH2_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH2_PA12_Msk)) | BPWM1_CH2_PA12 /*!< Set PA12 function to BPWM1_CH2 */ +#define SET_BPWM1_CH3_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM1_CH3_PA6_Msk)) | BPWM1_CH3_PA6 /*!< Set PA6 function to BPWM1_CH3 */ +#define SET_BPWM1_CH3_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH3_PA13_Msk)) | BPWM1_CH3_PA13 /*!< Set PA13 function to BPWM1_CH3 */ +#define SET_BPWM1_CH3_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH3_PB8_Msk)) | BPWM1_CH3_PB8 /*!< Set PB8 function to BPWM1_CH3 */ +#define SET_BPWM1_CH4_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH4_PA14_Msk)) | BPWM1_CH4_PA14 /*!< Set PA14 function to BPWM1_CH4 */ +#define SET_BPWM1_CH4_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~BPWM1_CH4_PC8_Msk)) | BPWM1_CH4_PC8 /*!< Set PC8 function to BPWM1_CH4 */ +#define SET_BPWM1_CH4_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~BPWM1_CH4_PB7_Msk)) | BPWM1_CH4_PB7 /*!< Set PB7 function to BPWM1_CH4 */ +#define SET_BPWM1_CH5_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH5_PA15_Msk)) | BPWM1_CH5_PA15 /*!< Set PA15 function to BPWM1_CH5 */ +#define SET_BPWM1_CH5_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~BPWM1_CH5_PB6_Msk)) | BPWM1_CH5_PB6 /*!< Set PB6 function to BPWM1_CH5 */ +#define SET_BPWM1_CH5_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~BPWM1_CH5_PE13_Msk)) | BPWM1_CH5_PE13 /*!< Set PE13 function to BPWM1_CH5 */ +#define SET_CAN0_RXD_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~CAN0_RXD_PA13_Msk)) | CAN0_RXD_PA13 /*!< Set PA13 function to CAN0_RXD */ +#define SET_CAN0_RXD_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~CAN0_RXD_PD10_Msk)) | CAN0_RXD_PD10 /*!< Set PD10 function to CAN0_RXD */ +#define SET_CAN0_RXD_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~CAN0_RXD_PA4_Msk)) | CAN0_RXD_PA4 /*!< Set PA4 function to CAN0_RXD */ +#define SET_CAN0_RXD_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~CAN0_RXD_PC4_Msk)) | CAN0_RXD_PC4 /*!< Set PC4 function to CAN0_RXD */ +#define SET_CAN0_RXD_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~CAN0_RXD_PB10_Msk)) | CAN0_RXD_PB10 /*!< Set PB10 function to CAN0_RXD */ +#define SET_CAN0_RXD_PE15() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~CAN0_RXD_PE15_Msk)) | CAN0_RXD_PE15 /*!< Set PE15 function to CAN0_RXD */ +#define SET_CAN0_TXD_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~CAN0_TXD_PD11_Msk)) | CAN0_TXD_PD11 /*!< Set PD11 function to CAN0_TXD */ +#define SET_CAN0_TXD_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~CAN0_TXD_PC5_Msk)) | CAN0_TXD_PC5 /*!< Set PC5 function to CAN0_TXD */ +#define SET_CAN0_TXD_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~CAN0_TXD_PB11_Msk)) | CAN0_TXD_PB11 /*!< Set PB11 function to CAN0_TXD */ +#define SET_CAN0_TXD_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~CAN0_TXD_PA12_Msk)) | CAN0_TXD_PA12 /*!< Set PA12 function to CAN0_TXD */ +#define SET_CAN0_TXD_PE14() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~CAN0_TXD_PE14_Msk)) | CAN0_TXD_PE14 /*!< Set PE14 function to CAN0_TXD */ +#define SET_CAN0_TXD_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~CAN0_TXD_PA5_Msk)) | CAN0_TXD_PA5 /*!< Set PA5 function to CAN0_TXD */ +#define SET_CLKO_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~CLKO_PC13_Msk)) | CLKO_PC13 /*!< Set PC13 function to CLKO */ +#define SET_CLKO_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~CLKO_PB14_Msk)) | CLKO_PB14 /*!< Set PB14 function to CLKO */ +#define SET_CLKO_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~CLKO_PD12_Msk)) | CLKO_PD12 /*!< Set PD12 function to CLKO */ +#define SET_CLKO_PG15() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~CLKO_PG15_Msk)) | CLKO_PG15 /*!< Set PG15 function to CLKO */ +#define SET_DAC0_OUT_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC0_OUT_PB12_Msk)) | DAC0_OUT_PB12 /*!< Set PB12 function to DAC0_OUT */ +#define SET_DAC0_OUT_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC0_OUT_PB12_Msk)) | DAC0_OUT_PB12 /*!< Set PB12 function to DAC0_OUT */ +#define SET_DAC0_ST_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~DAC0_ST_PA0_Msk)) | DAC0_ST_PA0 /*!< Set PA0 function to DAC0_ST */ +#define SET_DAC0_ST_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~DAC0_ST_PA10_Msk)) | DAC0_ST_PA10 /*!< Set PA10 function to DAC0_ST */ +#define SET_DAC1_OUT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC1_OUT_PB13_Msk)) | DAC1_OUT_PB13 /*!< Set PB13 function to DAC1_OUT */ +#define SET_DAC1_OUT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC1_OUT_PB13_Msk)) | DAC1_OUT_PB13 /*!< Set PB13 function to DAC1_OUT */ +#define SET_DAC1_ST_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~DAC1_ST_PA1_Msk)) | DAC1_ST_PA1 /*!< Set PA1 function to DAC1_ST */ +#define SET_DAC1_ST_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~DAC1_ST_PA11_Msk)) | DAC1_ST_PA11 /*!< Set PA11 function to DAC1_ST */ +#define SET_EADC0_CH0_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH0_PB0_Msk)) | EADC0_CH0_PB0 /*!< Set PB0 function to EADC0_CH0 */ +#define SET_EADC0_CH1_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH1_PB1_Msk)) | EADC0_CH1_PB1 /*!< Set PB1 function to EADC0_CH1 */ +#define SET_EADC0_CH10_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH10_PB10_Msk)) | EADC0_CH10_PB10 /*!< Set PB10 function to EADC0_CH10 */ +#define SET_EADC0_CH11_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH11_PB11_Msk)) | EADC0_CH11_PB11 /*!< Set PB11 function to EADC0_CH11 */ +#define SET_EADC0_CH12_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH12_PB12_Msk)) | EADC0_CH12_PB12 /*!< Set PB12 function to EADC0_CH12 */ +#define SET_EADC0_CH13_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH13_PB13_Msk)) | EADC0_CH13_PB13 /*!< Set PB13 function to EADC0_CH13 */ +#define SET_EADC0_CH14_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH14_PB14_Msk)) | EADC0_CH14_PB14 /*!< Set PB14 function to EADC0_CH14 */ +#define SET_EADC0_CH15_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH15_PB15_Msk)) | EADC0_CH15_PB15 /*!< Set PB15 function to EADC0_CH15 */ +#define SET_EADC0_CH15_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EADC0_CH15_PD10_Msk)) | EADC0_CH15_PD10 /*!< Set PD10 function to EADC0_CH15 */ +#define SET_EADC0_CH2_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH2_PB2_Msk)) | EADC0_CH2_PB2 /*!< Set PB2 function to EADC0_CH2 */ +#define SET_EADC0_CH3_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH3_PB3_Msk)) | EADC0_CH3_PB3 /*!< Set PB3 function to EADC0_CH3 */ +#define SET_EADC0_CH4_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH4_PB4_Msk)) | EADC0_CH4_PB4 /*!< Set PB4 function to EADC0_CH4 */ +#define SET_EADC0_CH5_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH5_PB5_Msk)) | EADC0_CH5_PB5 /*!< Set PB5 function to EADC0_CH5 */ +#define SET_EADC0_CH6_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH6_PB6_Msk)) | EADC0_CH6_PB6 /*!< Set PB6 function to EADC0_CH6 */ +#define SET_EADC0_CH7_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH7_PB7_Msk)) | EADC0_CH7_PB7 /*!< Set PB7 function to EADC0_CH7 */ +#define SET_EADC0_CH8_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH8_PB8_Msk)) | EADC0_CH8_PB8 /*!< Set PB8 function to EADC0_CH8 */ +#define SET_EADC0_CH9_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH9_PB9_Msk)) | EADC0_CH9_PB9 /*!< Set PB9 function to EADC0_CH9 */ +#define SET_EADC0_ST_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EADC0_ST_PF5_Msk)) | EADC0_ST_PF5 /*!< Set PF5 function to EADC0_ST */ +#define SET_EADC0_ST_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EADC0_ST_PC13_Msk)) | EADC0_ST_PC13 /*!< Set PC13 function to EADC0_ST */ +#define SET_EADC0_ST_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EADC0_ST_PC1_Msk)) | EADC0_ST_PC1 /*!< Set PC1 function to EADC0_ST */ +#define SET_EADC0_ST_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EADC0_ST_PD12_Msk)) | EADC0_ST_PD12 /*!< Set PD12 function to EADC0_ST */ +#define SET_EADC0_ST_PG15() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EADC0_ST_PG15_Msk)) | EADC0_ST_PG15 /*!< Set PG15 function to EADC0_ST */ +#define SET_EBI_AD0_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD0_PC0_Msk)) | EBI_AD0_PC0 /*!< Set PC0 function to EBI_AD0 */ +#define SET_EBI_AD0_PG9() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD0_PG9_Msk)) | EBI_AD0_PG9 /*!< Set PG9 function to EBI_AD0 */ +#define SET_EBI_AD1_PG10() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD1_PG10_Msk)) | EBI_AD1_PG10 /*!< Set PG10 function to EBI_AD1 */ +#define SET_EBI_AD1_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD1_PC1_Msk)) | EBI_AD1_PC1 /*!< Set PC1 function to EBI_AD1 */ +#define SET_EBI_AD10_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_AD10_PE1_Msk)) | EBI_AD10_PE1 /*!< Set PE1 function to EBI_AD10 */ +#define SET_EBI_AD10_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD10_PD3_Msk)) | EBI_AD10_PD3 /*!< Set PD3 function to EBI_AD10 */ +#define SET_EBI_AD10_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_AD10_PD13_Msk)) | EBI_AD10_PD13 /*!< Set PD13 function to EBI_AD10 */ +#define SET_EBI_AD11_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_AD11_PE0_Msk)) | EBI_AD11_PE0 /*!< Set PE0 function to EBI_AD11 */ +#define SET_EBI_AD11_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD11_PD2_Msk)) | EBI_AD11_PD2 /*!< Set PD2 function to EBI_AD11 */ +#define SET_EBI_AD12_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD12_PD1_Msk)) | EBI_AD12_PD1 /*!< Set PD1 function to EBI_AD12 */ +#define SET_EBI_AD12_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD12_PB15_Msk)) | EBI_AD12_PB15 /*!< Set PB15 function to EBI_AD12 */ +#define SET_EBI_AD12_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD12_PH8_Msk)) | EBI_AD12_PH8 /*!< Set PH8 function to EBI_AD12 */ +#define SET_EBI_AD13_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD13_PD0_Msk)) | EBI_AD13_PD0 /*!< Set PD0 function to EBI_AD13 */ +#define SET_EBI_AD13_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD13_PB14_Msk)) | EBI_AD13_PB14 /*!< Set PB14 function to EBI_AD13 */ +#define SET_EBI_AD13_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD13_PH9_Msk)) | EBI_AD13_PH9 /*!< Set PH9 function to EBI_AD13 */ +#define SET_EBI_AD14_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD14_PB13_Msk)) | EBI_AD14_PB13 /*!< Set PB13 function to EBI_AD14 */ +#define SET_EBI_AD14_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD14_PH10_Msk)) | EBI_AD14_PH10 /*!< Set PH10 function to EBI_AD14 */ +#define SET_EBI_AD15_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD15_PB12_Msk)) | EBI_AD15_PB12 /*!< Set PB12 function to EBI_AD15 */ +#define SET_EBI_AD15_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD15_PH11_Msk)) | EBI_AD15_PH11 /*!< Set PH11 function to EBI_AD15 */ +#define SET_EBI_AD2_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD2_PC2_Msk)) | EBI_AD2_PC2 /*!< Set PC2 function to EBI_AD2 */ +#define SET_EBI_AD2_PG11() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD2_PG11_Msk)) | EBI_AD2_PG11 /*!< Set PG11 function to EBI_AD2 */ +#define SET_EBI_AD3_PG12() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD3_PG12_Msk)) | EBI_AD3_PG12 /*!< Set PG12 function to EBI_AD3 */ +#define SET_EBI_AD3_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD3_PC3_Msk)) | EBI_AD3_PC3 /*!< Set PC3 function to EBI_AD3 */ +#define SET_EBI_AD4_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD4_PC4_Msk)) | EBI_AD4_PC4 /*!< Set PC4 function to EBI_AD4 */ +#define SET_EBI_AD4_PG13() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD4_PG13_Msk)) | EBI_AD4_PG13 /*!< Set PG13 function to EBI_AD4 */ +#define SET_EBI_AD5_PG14() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD5_PG14_Msk)) | EBI_AD5_PG14 /*!< Set PG14 function to EBI_AD5 */ +#define SET_EBI_AD5_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD5_PC5_Msk)) | EBI_AD5_PC5 /*!< Set PC5 function to EBI_AD5 */ +#define SET_EBI_AD6_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_AD6_PD8_Msk)) | EBI_AD6_PD8 /*!< Set PD8 function to EBI_AD6 */ +#define SET_EBI_AD6_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EBI_AD6_PA6_Msk)) | EBI_AD6_PA6 /*!< Set PA6 function to EBI_AD6 */ +#define SET_EBI_AD7_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_AD7_PD9_Msk)) | EBI_AD7_PD9 /*!< Set PD9 function to EBI_AD7 */ +#define SET_EBI_AD7_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EBI_AD7_PA7_Msk)) | EBI_AD7_PA7 /*!< Set PA7 function to EBI_AD7 */ +#define SET_EBI_AD8_PE14() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_AD8_PE14_Msk)) | EBI_AD8_PE14 /*!< Set PE14 function to EBI_AD8 */ +#define SET_EBI_AD8_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD8_PC6_Msk)) | EBI_AD8_PC6 /*!< Set PC6 function to EBI_AD8 */ +#define SET_EBI_AD9_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD9_PC7_Msk)) | EBI_AD9_PC7 /*!< Set PC7 function to EBI_AD9 */ +#define SET_EBI_AD9_PE15() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_AD9_PE15_Msk)) | EBI_AD9_PE15 /*!< Set PE15 function to EBI_AD9 */ +#define SET_EBI_ADR0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR0_PB5_Msk)) | EBI_ADR0_PB5 /*!< Set PB5 function to EBI_ADR0 */ +#define SET_EBI_ADR0_PH7() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR0_PH7_Msk)) | EBI_ADR0_PH7 /*!< Set PH7 function to EBI_ADR0 */ +#define SET_EBI_ADR1_PH6() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR1_PH6_Msk)) | EBI_ADR1_PH6 /*!< Set PH6 function to EBI_ADR1 */ +#define SET_EBI_ADR1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR1_PB4_Msk)) | EBI_ADR1_PB4 /*!< Set PB4 function to EBI_ADR1 */ +#define SET_EBI_ADR10_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR10_PC13_Msk)) | EBI_ADR10_PC13 /*!< Set PC13 function to EBI_ADR10 */ +#define SET_EBI_ADR10_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR10_PE8_Msk)) | EBI_ADR10_PE8 /*!< Set PE8 function to EBI_ADR10 */ +#define SET_EBI_ADR11_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR11_PE9_Msk)) | EBI_ADR11_PE9 /*!< Set PE9 function to EBI_ADR11 */ +#define SET_EBI_ADR11_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~EBI_ADR11_PG2_Msk)) | EBI_ADR11_PG2 /*!< Set PG2 function to EBI_ADR11 */ +#define SET_EBI_ADR12_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR12_PE10_Msk)) | EBI_ADR12_PE10 /*!< Set PE10 function to EBI_ADR12 */ +#define SET_EBI_ADR12_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~EBI_ADR12_PG3_Msk)) | EBI_ADR12_PG3 /*!< Set PG3 function to EBI_ADR12 */ +#define SET_EBI_ADR13_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR13_PE11_Msk)) | EBI_ADR13_PE11 /*!< Set PE11 function to EBI_ADR13 */ +#define SET_EBI_ADR13_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~EBI_ADR13_PG4_Msk)) | EBI_ADR13_PG4 /*!< Set PG4 function to EBI_ADR13 */ +#define SET_EBI_ADR14_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR14_PF11_Msk)) | EBI_ADR14_PF11 /*!< Set PF11 function to EBI_ADR14 */ +#define SET_EBI_ADR14_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR14_PE12_Msk)) | EBI_ADR14_PE12 /*!< Set PE12 function to EBI_ADR14 */ +#define SET_EBI_ADR15_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR15_PE13_Msk)) | EBI_ADR15_PE13 /*!< Set PE13 function to EBI_ADR15 */ +#define SET_EBI_ADR15_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR15_PF10_Msk)) | EBI_ADR15_PF10 /*!< Set PF10 function to EBI_ADR15 */ +#define SET_EBI_ADR16_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR16_PC8_Msk)) | EBI_ADR16_PC8 /*!< Set PC8 function to EBI_ADR16 */ +#define SET_EBI_ADR16_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR16_PF9_Msk)) | EBI_ADR16_PF9 /*!< Set PF9 function to EBI_ADR16 */ +#define SET_EBI_ADR16_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR16_PB11_Msk)) | EBI_ADR16_PB11 /*!< Set PB11 function to EBI_ADR16 */ +#define SET_EBI_ADR17_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR17_PB10_Msk)) | EBI_ADR17_PB10 /*!< Set PB10 function to EBI_ADR17 */ +#define SET_EBI_ADR17_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR17_PF8_Msk)) | EBI_ADR17_PF8 /*!< Set PF8 function to EBI_ADR17 */ +#define SET_EBI_ADR18_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_ADR18_PF7_Msk)) | EBI_ADR18_PF7 /*!< Set PF7 function to EBI_ADR18 */ +#define SET_EBI_ADR18_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR18_PB9_Msk)) | EBI_ADR18_PB9 /*!< Set PB9 function to EBI_ADR18 */ +#define SET_EBI_ADR19_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR19_PB8_Msk)) | EBI_ADR19_PB8 /*!< Set PB8 function to EBI_ADR19 */ +#define SET_EBI_ADR19_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_ADR19_PF6_Msk)) | EBI_ADR19_PF6 /*!< Set PF6 function to EBI_ADR19 */ +#define SET_EBI_ADR2_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR2_PB3_Msk)) | EBI_ADR2_PB3 /*!< Set PB3 function to EBI_ADR2 */ +#define SET_EBI_ADR2_PH5() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR2_PH5_Msk)) | EBI_ADR2_PH5 /*!< Set PH5 function to EBI_ADR2 */ +#define SET_EBI_ADR3_PH4() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR3_PH4_Msk)) | EBI_ADR3_PH4 /*!< Set PH4 function to EBI_ADR3 */ +#define SET_EBI_ADR3_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR3_PB2_Msk)) | EBI_ADR3_PB2 /*!< Set PB2 function to EBI_ADR3 */ +#define SET_EBI_ADR4_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR4_PC12_Msk)) | EBI_ADR4_PC12 /*!< Set PC12 function to EBI_ADR4 */ +#define SET_EBI_ADR5_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR5_PC11_Msk)) | EBI_ADR5_PC11 /*!< Set PC11 function to EBI_ADR5 */ +#define SET_EBI_ADR6_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR6_PC10_Msk)) | EBI_ADR6_PC10 /*!< Set PC10 function to EBI_ADR6 */ +#define SET_EBI_ADR7_PC9() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR7_PC9_Msk)) | EBI_ADR7_PC9 /*!< Set PC9 function to EBI_ADR7 */ +#define SET_EBI_ADR8_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR8_PB1_Msk)) | EBI_ADR8_PB1 /*!< Set PB1 function to EBI_ADR8 */ +#define SET_EBI_ADR9_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR9_PB0_Msk)) | EBI_ADR9_PB0 /*!< Set PB0 function to EBI_ADR9 */ +#define SET_EBI_ALE_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_ALE_PE2_Msk)) | EBI_ALE_PE2 /*!< Set PE2 function to EBI_ALE */ +#define SET_EBI_ALE_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_ALE_PA8_Msk)) | EBI_ALE_PA8 /*!< Set PA8 function to EBI_ALE */ +#define SET_EBI_MCLK_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_MCLK_PA9_Msk)) | EBI_MCLK_PA9 /*!< Set PA9 function to EBI_MCLK */ +#define SET_EBI_MCLK_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_MCLK_PE3_Msk)) | EBI_MCLK_PE3 /*!< Set PE3 function to EBI_MCLK */ +#define SET_EBI_nCS0_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS0_PD12_Msk)) | EBI_nCS0_PD12 /*!< Set PD12 function to EBI_nCS0 */ +#define SET_EBI_nCS0_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS0_PD14_Msk)) | EBI_nCS0_PD14 /*!< Set PD14 function to EBI_nCS0 */ +#define SET_EBI_nCS0_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_nCS0_PF3_Msk)) | EBI_nCS0_PF3 /*!< Set PF3 function to EBI_nCS0 */ +#define SET_EBI_nCS0_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nCS0_PB7_Msk)) | EBI_nCS0_PB7 /*!< Set PB7 function to EBI_nCS0 */ +#define SET_EBI_nCS0_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_nCS0_PF6_Msk)) | EBI_nCS0_PF6 /*!< Set PF6 function to EBI_nCS0 */ +#define SET_EBI_nCS1_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_nCS1_PF2_Msk)) | EBI_nCS1_PF2 /*!< Set PF2 function to EBI_nCS1 */ +#define SET_EBI_nCS1_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nCS1_PB6_Msk)) | EBI_nCS1_PB6 /*!< Set PB6 function to EBI_nCS1 */ +#define SET_EBI_nCS1_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS1_PD11_Msk)) | EBI_nCS1_PD11 /*!< Set PD11 function to EBI_nCS1 */ +#define SET_EBI_nCS2_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS2_PD10_Msk)) | EBI_nCS2_PD10 /*!< Set PD10 function to EBI_nCS2 */ +#define SET_EBI_nRD_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_nRD_PE5_Msk)) | EBI_nRD_PE5 /*!< Set PE5 function to EBI_nRD */ +#define SET_EBI_nRD_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_nRD_PA11_Msk)) | EBI_nRD_PA11 /*!< Set PA11 function to EBI_nRD */ +#define SET_EBI_nWR_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_nWR_PE4_Msk)) | EBI_nWR_PE4 /*!< Set PE4 function to EBI_nWR */ +#define SET_EBI_nWR_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_nWR_PA10_Msk)) | EBI_nWR_PA10 /*!< Set PA10 function to EBI_nWR */ +#define SET_EBI_nWRH_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nWRH_PB6_Msk)) | EBI_nWRH_PB6 /*!< Set PB6 function to EBI_nWRH */ +#define SET_EBI_nWRL_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nWRL_PB7_Msk)) | EBI_nWRL_PB7 /*!< Set PB7 function to EBI_nWRL */ +#define SET_ECAP0_IC0_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP0_IC0_PE8_Msk)) | ECAP0_IC0_PE8 /*!< Set PE8 function to ECAP0_IC0 */ +#define SET_ECAP0_IC0_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ECAP0_IC0_PA10_Msk)) | ECAP0_IC0_PA10 /*!< Set PA10 function to ECAP0_IC0 */ +#define SET_ECAP0_IC1_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ECAP0_IC1_PA9_Msk)) | ECAP0_IC1_PA9 /*!< Set PA9 function to ECAP0_IC1 */ +#define SET_ECAP0_IC1_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP0_IC1_PE9_Msk)) | ECAP0_IC1_PE9 /*!< Set PE9 function to ECAP0_IC1 */ +#define SET_ECAP0_IC2_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP0_IC2_PE10_Msk)) | ECAP0_IC2_PE10 /*!< Set PE10 function to ECAP0_IC2 */ +#define SET_ECAP0_IC2_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ECAP0_IC2_PA8_Msk)) | ECAP0_IC2_PA8 /*!< Set PA8 function to ECAP0_IC2 */ +#define SET_ECAP1_IC0_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP1_IC0_PE13_Msk)) | ECAP1_IC0_PE13 /*!< Set PE13 function to ECAP1_IC0 */ +#define SET_ECAP1_IC0_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ECAP1_IC0_PC10_Msk)) | ECAP1_IC0_PC10 /*!< Set PC10 function to ECAP1_IC0 */ +#define SET_ECAP1_IC1_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ECAP1_IC1_PC11_Msk)) | ECAP1_IC1_PC11 /*!< Set PC11 function to ECAP1_IC1 */ +#define SET_ECAP1_IC1_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP1_IC1_PE12_Msk)) | ECAP1_IC1_PE12 /*!< Set PE12 function to ECAP1_IC1 */ +#define SET_ECAP1_IC2_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ECAP1_IC2_PC12_Msk)) | ECAP1_IC2_PC12 /*!< Set PC12 function to ECAP1_IC2 */ +#define SET_ECAP1_IC2_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP1_IC2_PE11_Msk)) | ECAP1_IC2_PE11 /*!< Set PE11 function to ECAP1_IC2 */ +#define SET_EPWM0_BRAKE0_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_BRAKE0_PE8_Msk)) | EPWM0_BRAKE0_PE8 /*!< Set PE8 function to EPWM0_BRAKE0 */ +#define SET_EPWM0_BRAKE0_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_BRAKE0_PB1_Msk)) | EPWM0_BRAKE0_PB1 /*!< Set PB1 function to EPWM0_BRAKE0 */ +#define SET_EPWM0_BRAKE1_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM0_BRAKE1_PB14_Msk)) | EPWM0_BRAKE1_PB14 /*!< Set PB14 function to EPWM0_BRAKE1 */ +#define SET_EPWM0_BRAKE1_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_BRAKE1_PE9_Msk)) | EPWM0_BRAKE1_PE9 /*!< Set PE9 function to EPWM0_BRAKE1 */ +#define SET_EPWM0_BRAKE1_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_BRAKE1_PB0_Msk)) | EPWM0_BRAKE1_PB0 /*!< Set PB0 function to EPWM0_BRAKE1 */ +#define SET_EPWM0_CH0_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EPWM0_CH0_PF5_Msk)) | EPWM0_CH0_PF5 /*!< Set PF5 function to EPWM0_CH0 */ +#define SET_EPWM0_CH0_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH0_PA5_Msk)) | EPWM0_CH0_PA5 /*!< Set PA5 function to EPWM0_CH0 */ +#define SET_EPWM0_CH0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH0_PB5_Msk)) | EPWM0_CH0_PB5 /*!< Set PB5 function to EPWM0_CH0 */ +#define SET_EPWM0_CH0_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH0_PE8_Msk)) | EPWM0_CH0_PE8 /*!< Set PE8 function to EPWM0_CH0 */ +#define SET_EPWM0_CH0_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH0_PE7_Msk)) | EPWM0_CH0_PE7 /*!< Set PE7 function to EPWM0_CH0 */ +#define SET_EPWM0_CH1_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH1_PA4_Msk)) | EPWM0_CH1_PA4 /*!< Set PA4 function to EPWM0_CH1 */ +#define SET_EPWM0_CH1_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH1_PE9_Msk)) | EPWM0_CH1_PE9 /*!< Set PE9 function to EPWM0_CH1 */ +#define SET_EPWM0_CH1_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH1_PE6_Msk)) | EPWM0_CH1_PE6 /*!< Set PE6 function to EPWM0_CH1 */ +#define SET_EPWM0_CH1_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EPWM0_CH1_PF4_Msk)) | EPWM0_CH1_PF4 /*!< Set PF4 function to EPWM0_CH1 */ +#define SET_EPWM0_CH1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH1_PB4_Msk)) | EPWM0_CH1_PB4 /*!< Set PB4 function to EPWM0_CH1 */ +#define SET_EPWM0_CH2_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH2_PE10_Msk)) | EPWM0_CH2_PE10 /*!< Set PE10 function to EPWM0_CH2 */ +#define SET_EPWM0_CH2_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH2_PE5_Msk)) | EPWM0_CH2_PE5 /*!< Set PE5 function to EPWM0_CH2 */ +#define SET_EPWM0_CH2_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH2_PA3_Msk)) | EPWM0_CH2_PA3 /*!< Set PA3 function to EPWM0_CH2 */ +#define SET_EPWM0_CH2_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH2_PB3_Msk)) | EPWM0_CH2_PB3 /*!< Set PB3 function to EPWM0_CH2 */ +#define SET_EPWM0_CH3_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH3_PA2_Msk)) | EPWM0_CH3_PA2 /*!< Set PA2 function to EPWM0_CH3 */ +#define SET_EPWM0_CH3_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH3_PB2_Msk)) | EPWM0_CH3_PB2 /*!< Set PB2 function to EPWM0_CH3 */ +#define SET_EPWM0_CH3_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH3_PE11_Msk)) | EPWM0_CH3_PE11 /*!< Set PE11 function to EPWM0_CH3 */ +#define SET_EPWM0_CH3_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH3_PE4_Msk)) | EPWM0_CH3_PE4 /*!< Set PE4 function to EPWM0_CH3 */ +#define SET_EPWM0_CH4_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH4_PE3_Msk)) | EPWM0_CH4_PE3 /*!< Set PE3 function to EPWM0_CH4 */ +#define SET_EPWM0_CH4_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EPWM0_CH4_PD14_Msk)) | EPWM0_CH4_PD14 /*!< Set PD14 function to EPWM0_CH4 */ +#define SET_EPWM0_CH4_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH4_PA1_Msk)) | EPWM0_CH4_PA1 /*!< Set PA1 function to EPWM0_CH4 */ +#define SET_EPWM0_CH4_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH4_PE12_Msk)) | EPWM0_CH4_PE12 /*!< Set PE12 function to EPWM0_CH4 */ +#define SET_EPWM0_CH4_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH4_PB1_Msk)) | EPWM0_CH4_PB1 /*!< Set PB1 function to EPWM0_CH4 */ +#define SET_EPWM0_CH5_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH5_PA0_Msk)) | EPWM0_CH5_PA0 /*!< Set PA0 function to EPWM0_CH5 */ +#define SET_EPWM0_CH5_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH5_PB0_Msk)) | EPWM0_CH5_PB0 /*!< Set PB0 function to EPWM0_CH5 */ +#define SET_EPWM0_CH5_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH5_PE13_Msk)) | EPWM0_CH5_PE13 /*!< Set PE13 function to EPWM0_CH5 */ +#define SET_EPWM0_CH5_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH5_PE2_Msk)) | EPWM0_CH5_PE2 /*!< Set PE2 function to EPWM0_CH5 */ +#define SET_EPWM0_CH5_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EPWM0_CH5_PH11_Msk)) | EPWM0_CH5_PH11 /*!< Set PH11 function to EPWM0_CH5 */ +#define SET_EPWM0_SYNC_IN_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EPWM0_SYNC_IN_PA15_Msk)) | EPWM0_SYNC_IN_PA15/*!< Set PA15 function to EPWM0_SYNC_IN */ +#define SET_EPWM0_SYNC_OUT_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EPWM0_SYNC_OUT_PA11_Msk)) | EPWM0_SYNC_OUT_PA11/*!< Set PA11 function to EPWM0_SYNC_OUT */ +#define SET_EPWM0_SYNC_OUT_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EPWM0_SYNC_OUT_PF5_Msk)) | EPWM0_SYNC_OUT_PF5/*!< Set PF5 function to EPWM0_SYNC_OUT */ +#define SET_EPWM1_BRAKE0_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_BRAKE0_PB7_Msk)) | EPWM1_BRAKE0_PB7 /*!< Set PB7 function to EPWM1_BRAKE0 */ +#define SET_EPWM1_BRAKE0_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM1_BRAKE0_PE10_Msk)) | EPWM1_BRAKE0_PE10 /*!< Set PE10 function to EPWM1_BRAKE0 */ +#define SET_EPWM1_BRAKE1_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_BRAKE1_PB6_Msk)) | EPWM1_BRAKE1_PB6 /*!< Set PB6 function to EPWM1_BRAKE1 */ +#define SET_EPWM1_BRAKE1_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM1_BRAKE1_PA3_Msk)) | EPWM1_BRAKE1_PA3 /*!< Set PA3 function to EPWM1_BRAKE1 */ +#define SET_EPWM1_BRAKE1_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM1_BRAKE1_PE11_Msk)) | EPWM1_BRAKE1_PE11 /*!< Set PE11 function to EPWM1_BRAKE1 */ +#define SET_EPWM1_CH0_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM1_CH0_PE13_Msk)) | EPWM1_CH0_PE13 /*!< Set PE13 function to EPWM1_CH0 */ +#define SET_EPWM1_CH0_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH0_PC12_Msk)) | EPWM1_CH0_PC12 /*!< Set PC12 function to EPWM1_CH0 */ +#define SET_EPWM1_CH0_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH0_PB15_Msk)) | EPWM1_CH0_PB15 /*!< Set PB15 function to EPWM1_CH0 */ +#define SET_EPWM1_CH0_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH0_PC5_Msk)) | EPWM1_CH0_PC5 /*!< Set PC5 function to EPWM1_CH0 */ +#define SET_EPWM1_CH1_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH1_PC8_Msk)) | EPWM1_CH1_PC8 /*!< Set PC8 function to EPWM1_CH1 */ +#define SET_EPWM1_CH1_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH1_PC11_Msk)) | EPWM1_CH1_PC11 /*!< Set PC11 function to EPWM1_CH1 */ +#define SET_EPWM1_CH1_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH1_PB14_Msk)) | EPWM1_CH1_PB14 /*!< Set PB14 function to EPWM1_CH1 */ +#define SET_EPWM1_CH1_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH1_PC4_Msk)) | EPWM1_CH1_PC4 /*!< Set PC4 function to EPWM1_CH1 */ +#define SET_EPWM1_CH2_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH2_PC7_Msk)) | EPWM1_CH2_PC7 /*!< Set PC7 function to EPWM1_CH2 */ +#define SET_EPWM1_CH2_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH2_PC3_Msk)) | EPWM1_CH2_PC3 /*!< Set PC3 function to EPWM1_CH2 */ +#define SET_EPWM1_CH2_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH2_PC10_Msk)) | EPWM1_CH2_PC10 /*!< Set PC10 function to EPWM1_CH2 */ +#define SET_EPWM1_CH2_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH2_PB13_Msk)) | EPWM1_CH2_PB13 /*!< Set PB13 function to EPWM1_CH2 */ +#define SET_EPWM1_CH3_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH3_PC6_Msk)) | EPWM1_CH3_PC6 /*!< Set PC6 function to EPWM1_CH3 */ +#define SET_EPWM1_CH3_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH3_PC2_Msk)) | EPWM1_CH3_PC2 /*!< Set PC2 function to EPWM1_CH3 */ +#define SET_EPWM1_CH3_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH3_PB12_Msk)) | EPWM1_CH3_PB12 /*!< Set PB12 function to EPWM1_CH3 */ +#define SET_EPWM1_CH3_PC9() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH3_PC9_Msk)) | EPWM1_CH3_PC9 /*!< Set PC9 function to EPWM1_CH3 */ +#define SET_EPWM1_CH4_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH4_PC1_Msk)) | EPWM1_CH4_PC1 /*!< Set PC1 function to EPWM1_CH4 */ +#define SET_EPWM1_CH4_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH4_PB1_Msk)) | EPWM1_CH4_PB1 /*!< Set PB1 function to EPWM1_CH4 */ +#define SET_EPWM1_CH4_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH4_PB7_Msk)) | EPWM1_CH4_PB7 /*!< Set PB7 function to EPWM1_CH4 */ +#define SET_EPWM1_CH4_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM1_CH4_PA7_Msk)) | EPWM1_CH4_PA7 /*!< Set PA7 function to EPWM1_CH4 */ +#define SET_EPWM1_CH5_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH5_PB6_Msk)) | EPWM1_CH5_PB6 /*!< Set PB6 function to EPWM1_CH5 */ +#define SET_EPWM1_CH5_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH5_PC0_Msk)) | EPWM1_CH5_PC0 /*!< Set PC0 function to EPWM1_CH5 */ +#define SET_EPWM1_CH5_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH5_PB0_Msk)) | EPWM1_CH5_PB0 /*!< Set PB0 function to EPWM1_CH5 */ +#define SET_EPWM1_CH5_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM1_CH5_PA6_Msk)) | EPWM1_CH5_PA6 /*!< Set PA6 function to EPWM1_CH5 */ +#define SET_I2C0_SCL_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2C0_SCL_PE13_Msk)) | I2C0_SCL_PE13 /*!< Set PE13 function to I2C0_SCL */ +#define SET_I2C0_SCL_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C0_SCL_PB9_Msk)) | I2C0_SCL_PB9 /*!< Set PB9 function to I2C0_SCL */ +#define SET_I2C0_SCL_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C0_SCL_PD7_Msk)) | I2C0_SCL_PD7 /*!< Set PD7 function to I2C0_SCL */ +#define SET_I2C0_SCL_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SCL_PA5_Msk)) | I2C0_SCL_PA5 /*!< Set PA5 function to I2C0_SCL */ +#define SET_I2C0_SCL_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C0_SCL_PB5_Msk)) | I2C0_SCL_PB5 /*!< Set PB5 function to I2C0_SCL */ +#define SET_I2C0_SCL_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SCL_PC1_Msk)) | I2C0_SCL_PC1 /*!< Set PC1 function to I2C0_SCL */ +#define SET_I2C0_SCL_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~I2C0_SCL_PC12_Msk)) | I2C0_SCL_PC12 /*!< Set PC12 function to I2C0_SCL */ +#define SET_I2C0_SCL_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C0_SCL_PF3_Msk)) | I2C0_SCL_PF3 /*!< Set PF3 function to I2C0_SCL */ +#define SET_I2C0_SDA_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C0_SDA_PB4_Msk)) | I2C0_SDA_PB4 /*!< Set PB4 function to I2C0_SDA */ +#define SET_I2C0_SDA_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C0_SDA_PD6_Msk)) | I2C0_SDA_PD6 /*!< Set PD6 function to I2C0_SDA */ +#define SET_I2C0_SDA_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C0_SDA_PB8_Msk)) | I2C0_SDA_PB8 /*!< Set PB8 function to I2C0_SDA */ +#define SET_I2C0_SDA_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~I2C0_SDA_PC11_Msk)) | I2C0_SDA_PC11 /*!< Set PC11 function to I2C0_SDA */ +#define SET_I2C0_SDA_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C0_SDA_PF2_Msk)) | I2C0_SDA_PF2 /*!< Set PF2 function to I2C0_SDA */ +#define SET_I2C0_SDA_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SDA_PC0_Msk)) | I2C0_SDA_PC0 /*!< Set PC0 function to I2C0_SDA */ +#define SET_I2C0_SDA_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~I2C0_SDA_PC8_Msk)) | I2C0_SDA_PC8 /*!< Set PC8 function to I2C0_SDA */ +#define SET_I2C0_SDA_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SDA_PA4_Msk)) | I2C0_SDA_PA4 /*!< Set PA4 function to I2C0_SDA */ +#define SET_I2C0_SMBAL_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SMBAL_PA3_Msk)) | I2C0_SMBAL_PA3 /*!< Set PA3 function to I2C0_SMBAL */ +#define SET_I2C0_SMBAL_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C0_SMBAL_PG2_Msk)) | I2C0_SMBAL_PG2 /*!< Set PG2 function to I2C0_SMBAL */ +#define SET_I2C0_SMBAL_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SMBAL_PC3_Msk)) | I2C0_SMBAL_PC3 /*!< Set PC3 function to I2C0_SMBAL */ +#define SET_I2C0_SMBSUS_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SMBSUS_PA2_Msk)) | I2C0_SMBSUS_PA2 /*!< Set PA2 function to I2C0_SMBSUS */ +#define SET_I2C0_SMBSUS_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SMBSUS_PC2_Msk)) | I2C0_SMBSUS_PC2 /*!< Set PC2 function to I2C0_SMBSUS */ +#define SET_I2C0_SMBSUS_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C0_SMBSUS_PG3_Msk)) | I2C0_SMBSUS_PG3 /*!< Set PG3 function to I2C0_SMBSUS */ +#define SET_I2C1_SCL_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SCL_PB1_Msk)) | I2C1_SCL_PB1 /*!< Set PB1 function to I2C1_SCL */ +#define SET_I2C1_SCL_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2C1_SCL_PE1_Msk)) | I2C1_SCL_PE1 /*!< Set PE1 function to I2C1_SCL */ +#define SET_I2C1_SCL_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C1_SCL_PF0_Msk)) | I2C1_SCL_PF0 /*!< Set PF0 function to I2C1_SCL */ +#define SET_I2C1_SCL_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C1_SCL_PA12_Msk)) | I2C1_SCL_PA12 /*!< Set PA12 function to I2C1_SCL */ +#define SET_I2C1_SCL_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SCL_PA7_Msk)) | I2C1_SCL_PA7 /*!< Set PA7 function to I2C1_SCL */ +#define SET_I2C1_SCL_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SCL_PB11_Msk)) | I2C1_SCL_PB11 /*!< Set PB11 function to I2C1_SCL */ +#define SET_I2C1_SCL_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C1_SCL_PG2_Msk)) | I2C1_SCL_PG2 /*!< Set PG2 function to I2C1_SCL */ +#define SET_I2C1_SCL_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SCL_PA3_Msk)) | I2C1_SCL_PA3 /*!< Set PA3 function to I2C1_SCL */ +#define SET_I2C1_SCL_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SCL_PC5_Msk)) | I2C1_SCL_PC5 /*!< Set PC5 function to I2C1_SCL */ +#define SET_I2C1_SCL_PD5() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C1_SCL_PD5_Msk)) | I2C1_SCL_PD5 /*!< Set PD5 function to I2C1_SCL */ +#define SET_I2C1_SCL_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SCL_PB3_Msk)) | I2C1_SCL_PB3 /*!< Set PB3 function to I2C1_SCL */ +#define SET_I2C1_SDA_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SDA_PA2_Msk)) | I2C1_SDA_PA2 /*!< Set PA2 function to I2C1_SDA */ +#define SET_I2C1_SDA_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SDA_PB10_Msk)) | I2C1_SDA_PB10 /*!< Set PB10 function to I2C1_SDA */ +#define SET_I2C1_SDA_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C1_SDA_PF1_Msk)) | I2C1_SDA_PF1 /*!< Set PF1 function to I2C1_SDA */ +#define SET_I2C1_SDA_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SDA_PB2_Msk)) | I2C1_SDA_PB2 /*!< Set PB2 function to I2C1_SDA */ +#define SET_I2C1_SDA_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C1_SDA_PD4_Msk)) | I2C1_SDA_PD4 /*!< Set PD4 function to I2C1_SDA */ +#define SET_I2C1_SDA_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C1_SDA_PA13_Msk)) | I2C1_SDA_PA13 /*!< Set PA13 function to I2C1_SDA */ +#define SET_I2C1_SDA_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SDA_PA6_Msk)) | I2C1_SDA_PA6 /*!< Set PA6 function to I2C1_SDA */ +#define SET_I2C1_SDA_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2C1_SDA_PE0_Msk)) | I2C1_SDA_PE0 /*!< Set PE0 function to I2C1_SDA */ +#define SET_I2C1_SDA_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C1_SDA_PG3_Msk)) | I2C1_SDA_PG3 /*!< Set PG3 function to I2C1_SDA */ +#define SET_I2C1_SDA_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SDA_PC4_Msk)) | I2C1_SDA_PC4 /*!< Set PC4 function to I2C1_SDA */ +#define SET_I2C1_SDA_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SDA_PB0_Msk)) | I2C1_SDA_PB0 /*!< Set PB0 function to I2C1_SDA */ +#define SET_I2C1_SMBAL_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SMBAL_PB9_Msk)) | I2C1_SMBAL_PB9 /*!< Set PB9 function to I2C1_SMBAL */ +#define SET_I2C1_SMBAL_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C1_SMBAL_PH8_Msk)) | I2C1_SMBAL_PH8 /*!< Set PH8 function to I2C1_SMBAL */ +#define SET_I2C1_SMBAL_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SMBAL_PC7_Msk)) | I2C1_SMBAL_PC7 /*!< Set PC7 function to I2C1_SMBAL */ +#define SET_I2C1_SMBSUS_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SMBSUS_PC6_Msk)) | I2C1_SMBSUS_PC6 /*!< Set PC6 function to I2C1_SMBSUS */ +#define SET_I2C1_SMBSUS_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SMBSUS_PB8_Msk)) | I2C1_SMBSUS_PB8 /*!< Set PB8 function to I2C1_SMBSUS */ +#define SET_I2C1_SMBSUS_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C1_SMBSUS_PH9_Msk)) | I2C1_SMBSUS_PH9 /*!< Set PH9 function to I2C1_SMBSUS */ +#define SET_I2C2_SCL_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SCL_PA14_Msk)) | I2C2_SCL_PA14 /*!< Set PA14 function to I2C2_SCL */ +#define SET_I2C2_SCL_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C2_SCL_PH8_Msk)) | I2C2_SCL_PH8 /*!< Set PH8 function to I2C2_SCL */ +#define SET_I2C2_SCL_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SCL_PA11_Msk)) | I2C2_SCL_PA11 /*!< Set PA11 function to I2C2_SCL */ +#define SET_I2C2_SCL_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SCL_PB13_Msk)) | I2C2_SCL_PB13 /*!< Set PB13 function to I2C2_SCL */ +#define SET_I2C2_SCL_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~I2C2_SCL_PD9_Msk)) | I2C2_SCL_PD9 /*!< Set PD9 function to I2C2_SCL */ +#define SET_I2C2_SCL_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C2_SCL_PA1_Msk)) | I2C2_SCL_PA1 /*!< Set PA1 function to I2C2_SCL */ +#define SET_I2C2_SCL_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C2_SCL_PD1_Msk)) | I2C2_SCL_PD1 /*!< Set PD1 function to I2C2_SCL */ +#define SET_I2C2_SDA_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~I2C2_SDA_PD8_Msk)) | I2C2_SDA_PD8 /*!< Set PD8 function to I2C2_SDA */ +#define SET_I2C2_SDA_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C2_SDA_PD0_Msk)) | I2C2_SDA_PD0 /*!< Set PD0 function to I2C2_SDA */ +#define SET_I2C2_SDA_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SDA_PA15_Msk)) | I2C2_SDA_PA15 /*!< Set PA15 function to I2C2_SDA */ +#define SET_I2C2_SDA_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C2_SDA_PH9_Msk)) | I2C2_SDA_PH9 /*!< Set PH9 function to I2C2_SDA */ +#define SET_I2C2_SDA_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SDA_PA10_Msk)) | I2C2_SDA_PA10 /*!< Set PA10 function to I2C2_SDA */ +#define SET_I2C2_SDA_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C2_SDA_PA0_Msk)) | I2C2_SDA_PA0 /*!< Set PA0 function to I2C2_SDA */ +#define SET_I2C2_SDA_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SDA_PB12_Msk)) | I2C2_SDA_PB12 /*!< Set PB12 function to I2C2_SDA */ +#define SET_I2C2_SMBAL_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SMBAL_PB15_Msk)) | I2C2_SMBAL_PB15 /*!< Set PB15 function to I2C2_SMBAL */ +#define SET_I2C2_SMBSUS_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SMBSUS_PB14_Msk)) | I2C2_SMBSUS_PB14 /*!< Set PB14 function to I2C2_SMBSUS */ +#define SET_I2S0_BCLK_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~I2S0_BCLK_PF10_Msk)) | I2S0_BCLK_PF10 /*!< Set PF10 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_BCLK_PB5_Msk)) | I2S0_BCLK_PB5 /*!< Set PB5 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2S0_BCLK_PE1_Msk)) | I2S0_BCLK_PE1 /*!< Set PE1 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_BCLK_PA12_Msk)) | I2S0_BCLK_PA12 /*!< Set PA12 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_BCLK_PC4_Msk)) | I2S0_BCLK_PC4 /*!< Set PC4 function to I2S0_BCLK */ +#define SET_I2S0_BCLK_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_BCLK_PE8_Msk)) | I2S0_BCLK_PE8 /*!< Set PE8 function to I2S0_BCLK */ +#define SET_I2S0_DI_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_DI_PC2_Msk)) | I2S0_DI_PC2 /*!< Set PC2 function to I2S0_DI */ +#define SET_I2S0_DI_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_DI_PE10_Msk)) | I2S0_DI_PE10 /*!< Set PE10 function to I2S0_DI */ +#define SET_I2S0_DI_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~I2S0_DI_PF8_Msk)) | I2S0_DI_PF8 /*!< Set PF8 function to I2S0_DI */ +#define SET_I2S0_DI_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2S0_DI_PH8_Msk)) | I2S0_DI_PH8 /*!< Set PH8 function to I2S0_DI */ +#define SET_I2S0_DI_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_DI_PB3_Msk)) | I2S0_DI_PB3 /*!< Set PB3 function to I2S0_DI */ +#define SET_I2S0_DI_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_DI_PA14_Msk)) | I2S0_DI_PA14 /*!< Set PA14 function to I2S0_DI */ +#define SET_I2S0_DO_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2S0_DO_PH9_Msk)) | I2S0_DO_PH9 /*!< Set PH9 function to I2S0_DO */ +#define SET_I2S0_DO_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_DO_PC1_Msk)) | I2S0_DO_PC1 /*!< Set PC1 function to I2S0_DO */ +#define SET_I2S0_DO_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_DO_PA15_Msk)) | I2S0_DO_PA15 /*!< Set PA15 function to I2S0_DO */ +#define SET_I2S0_DO_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_DO_PB2_Msk)) | I2S0_DO_PB2 /*!< Set PB2 function to I2S0_DO */ +#define SET_I2S0_DO_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2S0_DO_PF7_Msk)) | I2S0_DO_PF7 /*!< Set PF7 function to I2S0_DO */ +#define SET_I2S0_DO_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_DO_PE11_Msk)) | I2S0_DO_PE11 /*!< Set PE11 function to I2S0_DO */ +#define SET_I2S0_LRCK_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_LRCK_PC0_Msk)) | I2S0_LRCK_PC0 /*!< Set PC0 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_LRCK_PB1_Msk)) | I2S0_LRCK_PB1 /*!< Set PB1 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2S0_LRCK_PH10_Msk)) | I2S0_LRCK_PH10 /*!< Set PH10 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2S0_LRCK_PF6_Msk)) | I2S0_LRCK_PF6 /*!< Set PF6 function to I2S0_LRCK */ +#define SET_I2S0_LRCK_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_LRCK_PE12_Msk)) | I2S0_LRCK_PE12 /*!< Set PE12 function to I2S0_LRCK */ +#define SET_I2S0_MCLK_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_MCLK_PC3_Msk)) | I2S0_MCLK_PC3 /*!< Set PC3 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~I2S0_MCLK_PF9_Msk)) | I2S0_MCLK_PF9 /*!< Set PF9 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2S0_MCLK_PE0_Msk)) | I2S0_MCLK_PE0 /*!< Set PE0 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_MCLK_PB4_Msk)) | I2S0_MCLK_PB4 /*!< Set PB4 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_MCLK_PA13_Msk)) | I2S0_MCLK_PA13 /*!< Set PA13 function to I2S0_MCLK */ +#define SET_I2S0_MCLK_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_MCLK_PE9_Msk)) | I2S0_MCLK_PE9 /*!< Set PE9 function to I2S0_MCLK */ +#define SET_ICE_CLK_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~ICE_CLK_PF1_Msk)) | ICE_CLK_PF1 /*!< Set PF1 function to ICE_CLK */ +#define SET_ICE_DAT_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~ICE_DAT_PF0_Msk)) | ICE_DAT_PF0 /*!< Set PF0 function to ICE_DAT */ +#define SET_INT0_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~INT0_PA6_Msk)) | INT0_PA6 /*!< Set PA6 function to INT0 */ +#define SET_INT0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT0_PB5_Msk)) | INT0_PB5 /*!< Set PB5 function to INT0 */ +#define SET_INT1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT1_PB4_Msk)) | INT1_PB4 /*!< Set PB4 function to INT1 */ +#define SET_INT1_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~INT1_PA7_Msk)) | INT1_PA7 /*!< Set PA7 function to INT1 */ +#define SET_INT2_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT2_PB3_Msk)) | INT2_PB3 /*!< Set PB3 function to INT2 */ +#define SET_INT2_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~INT2_PC6_Msk)) | INT2_PC6 /*!< Set PC6 function to INT2 */ +#define SET_INT3_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT3_PB2_Msk)) | INT3_PB2 /*!< Set PB2 function to INT3 */ +#define SET_INT3_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~INT3_PC7_Msk)) | INT3_PC7 /*!< Set PC7 function to INT3 */ +#define SET_INT4_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~INT4_PA8_Msk)) | INT4_PA8 /*!< Set PA8 function to INT4 */ +#define SET_INT4_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT4_PB6_Msk)) | INT4_PB6 /*!< Set PB6 function to INT4 */ +#define SET_INT5_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT5_PB7_Msk)) | INT5_PB7 /*!< Set PB7 function to INT5 */ +#define SET_INT5_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~INT5_PD12_Msk)) | INT5_PD12 /*!< Set PD12 function to INT5 */ +#define SET_INT6_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~INT6_PD11_Msk)) | INT6_PD11 /*!< Set PD11 function to INT6 */ +#define SET_INT6_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~INT6_PB8_Msk)) | INT6_PB8 /*!< Set PB8 function to INT6 */ +#define SET_INT7_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~INT7_PB9_Msk)) | INT7_PB9 /*!< Set PB9 function to INT7 */ +#define SET_INT7_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~INT7_PD10_Msk)) | INT7_PD10 /*!< Set PD10 function to INT7 */ +#define SET_LCD_COM0_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM0_PC0_Msk)) | LCD_COM0_PC0 /*!< Set PC0 function to LCD_COM0 */ +#define SET_LCD_COM1_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM1_PC1_Msk)) | LCD_COM1_PC1 /*!< Set PC1 function to LCD_COM1 */ +#define SET_LCD_COM2_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM2_PC2_Msk)) | LCD_COM2_PC2 /*!< Set PC2 function to LCD_COM2 */ +#define SET_LCD_COM3_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM3_PC3_Msk)) | LCD_COM3_PC3 /*!< Set PC3 function to LCD_COM3 */ +#define SET_LCD_COM4_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM4_PC4_Msk)) | LCD_COM4_PC4 /*!< Set PC4 function to LCD_COM4 */ +#define SET_LCD_COM5_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM5_PC5_Msk)) | LCD_COM5_PC5 /*!< Set PC5 function to LCD_COM5 */ +#define SET_LCD_COM6_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_COM6_PA0_Msk)) | LCD_COM6_PA0 /*!< Set PA0 function to LCD_COM6 */ +#define SET_LCD_COM6_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_COM6_PD8_Msk)) | LCD_COM6_PD8 /*!< Set PD8 function to LCD_SEG41 */ +#define SET_LCD_COM7_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_COM7_PA1_Msk)) | LCD_COM7_PA1 /*!< Set PA1 function to LCD_COM7 */ +#define SET_LCD_COM7_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_COM7_PD9_Msk)) | LCD_COM7_PD9 /*!< Set PD9 function to LCD_COM7 */ +#define SET_LCD_SEG0_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_SEG0_PD14_Msk)) | LCD_SEG0_PD14 /*!< Set PD14 function to LCD_SEG0 */ +#define SET_LCD_SEG0_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG0_PD1_Msk)) | LCD_SEG0_PD1 /*!< Set PD1 function to LCD_SEG0 */ +#define SET_LCD_SEG1_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG1_PD2_Msk)) | LCD_SEG1_PD2 /*!< Set PD2 function to LCD_SEG1 */ +#define SET_LCD_SEG1_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG1_PH11_Msk)) | LCD_SEG1_PH11 /*!< Set PH11 function to LCD_SEG1 */ +#define SET_LCD_SEG10_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG10_PC7_Msk)) | LCD_SEG10_PC7 /*!< Set PC7 function to LCD_SEG10 */ +#define SET_LCD_SEG10_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG10_PE5_Msk)) | LCD_SEG10_PE5 /*!< Set PE5 function to LCD_SEG10 */ +#define SET_LCD_SEG11_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~LCD_SEG11_PA8_Msk)) | LCD_SEG11_PA8 /*!< Set PA8 function to LCD_SEG11 */ +#define SET_LCD_SEG11_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG11_PE6_Msk)) | LCD_SEG11_PE6 /*!< Set PE6 function to LCD_SEG11 */ +#define SET_LCD_SEG12_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~LCD_SEG12_PA9_Msk)) | LCD_SEG12_PA9 /*!< Set PA9 function to LCD_SEG12 */ +#define SET_LCD_SEG12_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG12_PE7_Msk)) | LCD_SEG12_PE7 /*!< Set PE7 function to LCD_SEG12 */ +#define SET_LCD_SEG13_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG13_PD6_Msk)) | LCD_SEG13_PD6 /*!< Set PD6 function to LCD_SEG13 */ +#define SET_LCD_SEG13_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG13_PA1_Msk)) | LCD_SEG13_PA1 /*!< Set PA1 function to LCD_SEG13 */ +#define SET_LCD_SEG14_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG14_PD7_Msk)) | LCD_SEG14_PD7 /*!< Set PD7 function to LCD_SEG14 */ +#define SET_LCD_SEG14_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG14_PA0_Msk)) | LCD_SEG14_PA0 /*!< Set PA0 function to LCD_SEG14 */ +#define SET_LCD_SEG15_PG15() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG15_PG15_Msk)) | LCD_SEG15_PG15 /*!< Set PG15 function to LCD_SEG15 */ +#define SET_LCD_SEG16_PG14() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG16_PG14_Msk)) | LCD_SEG16_PG14 /*!< Set PG14 function to LCD_SEG16 */ +#define SET_LCD_SEG17_PG13() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG17_PG13_Msk)) | LCD_SEG17_PG13 /*!< Set PG13 function to LCD_SEG17 */ +#define SET_LCD_SEG18_PG12() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG18_PG12_Msk)) | LCD_SEG18_PG12 /*!< Set PG12 function to LCD_SEG18 */ +#define SET_LCD_SEG19_PG11() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG19_PG11_Msk)) | LCD_SEG19_PG11 /*!< Set PG11 function to LCD_SEG19 */ +#define SET_LCD_SEG2_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG2_PH10_Msk)) | LCD_SEG2_PH10 /*!< Set PH10 function to LCD_SEG2 */ +#define SET_LCD_SEG2_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG2_PD3_Msk)) | LCD_SEG2_PD3 /*!< Set PD3 function to LCD_SEG2 */ +#define SET_LCD_SEG20_PG10() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG20_PG10_Msk)) | LCD_SEG20_PG10 /*!< Set PG10 function to LCD_SEG20 */ +#define SET_LCD_SEG21_PG9() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG21_PG9_Msk)) | LCD_SEG21_PG9 /*!< Set PG9 function to LCD_SEG21 */ +#define SET_LCD_SEG22_PE15() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG22_PE15_Msk)) | LCD_SEG22_PE15 /*!< Set PE15 function to LCD_SEG22 */ +#define SET_LCD_SEG23_PE14() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG23_PE14_Msk)) | LCD_SEG23_PE14 /*!< Set PE14 function to LCD_SEG23 */ +#define SET_LCD_SEG24_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG24_PA0_Msk)) | LCD_SEG24_PA0 /*!< Set PA0 function to LCD_SEG24 */ +#define SET_LCD_SEG25_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG25_PA1_Msk)) | LCD_SEG25_PA1 /*!< Set PA1 function to LCD_SEG25 */ +#define SET_LCD_SEG26_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG26_PA2_Msk)) | LCD_SEG26_PA2 /*!< Set PA2 function to LCD_SEG26 */ +#define SET_LCD_SEG27_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG27_PA3_Msk)) | LCD_SEG27_PA3 /*!< Set PA3 function to LCD_SEG27 */ +#define SET_LCD_SEG28_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG28_PA4_Msk)) | LCD_SEG28_PA4 /*!< Set PA4 function to LCD_SEG28 */ +#define SET_LCD_SEG29_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG29_PA5_Msk)) | LCD_SEG29_PA5 /*!< Set PA5 function to LCD_SEG29 */ +#define SET_LCD_SEG3_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG3_PA2_Msk)) | LCD_SEG3_PA2 /*!< Set PA2 function to LCD_SEG3 */ +#define SET_LCD_SEG3_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG3_PH9_Msk)) | LCD_SEG3_PH9 /*!< Set PH9 function to LCD_SEG3 */ +#define SET_LCD_SEG30_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG30_PE10_Msk)) | LCD_SEG30_PE10 /*!< Set PE10 function to LCD_SEG30 */ +#define SET_LCD_SEG31_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG31_PE9_Msk)) | LCD_SEG31_PE9 /*!< Set PE9 function to LCD_SEG31 */ +#define SET_LCD_SEG32_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG32_PE8_Msk)) | LCD_SEG32_PE8 /*!< Set PE8 function to LCD_SEG32 */ +#define SET_LCD_SEG33_PH7() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG33_PH7_Msk)) | LCD_SEG33_PH7 /*!< Set PH7 function to LCD_SEG33 */ +#define SET_LCD_SEG34_PH6() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG34_PH6_Msk)) | LCD_SEG34_PH6 /*!< Set PH6 function to LCD_SEG34 */ +#define SET_LCD_SEG35_PH5() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG35_PH5_Msk)) | LCD_SEG35_PH5 /*!< Set PH5 function to LCD_SEG35 */ +#define SET_LCD_SEG36_PH4() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG36_PH4_Msk)) | LCD_SEG36_PH4 /*!< Set PH4 function to LCD_SEG36 */ +#define SET_LCD_SEG37_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~LCD_SEG37_PG4_Msk)) | LCD_SEG37_PG4 /*!< Set PG4 function to LCD_SEG37 */ +#define SET_LCD_SEG38_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~LCD_SEG38_PG3_Msk)) | LCD_SEG38_PG3 /*!< Set PG3 function to LCD_SEG38 */ +#define SET_LCD_SEG39_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~LCD_SEG39_PG2_Msk)) | LCD_SEG39_PG2 /*!< Set PG2 function to LCD_SEG39 */ +#define SET_LCD_SEG4_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG4_PH8_Msk)) | LCD_SEG4_PH8 /*!< Set PH8 function to LCD_SEG4 */ +#define SET_LCD_SEG4_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG4_PA3_Msk)) | LCD_SEG4_PA3 /*!< Set PA3 function to LCD_SEG4 */ +#define SET_LCD_SEG40_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_SEG40_PD9_Msk)) | LCD_SEG40_PD9 /*!< Set PD9 function to LCD_SEG40 */ +#define SET_LCD_SEG41_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_SEG41_PD8_Msk)) | LCD_SEG41_PD8 /*!< Set PD8 function to LCD_SEG41 */ +#define SET_LCD_SEG42_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG42_PC5_Msk)) | LCD_SEG42_PC5 /*!< Set PC5 function to LCD_SEG42 */ +#define SET_LCD_SEG43_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG43_PC4_Msk)) | LCD_SEG43_PC4 /*!< Set PC4 function to LCD_SEG43 */ +#define SET_LCD_SEG5_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG5_PA4_Msk)) | LCD_SEG5_PA4 /*!< Set PA4 function to LCD_SEG5 */ +#define SET_LCD_SEG5_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG5_PE0_Msk)) | LCD_SEG5_PE0 /*!< Set PE0 function to LCD_SEG5 */ +#define SET_LCD_SEG6_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG6_PE1_Msk)) | LCD_SEG6_PE1 /*!< Set PE1 function to LCD_SEG6 */ +#define SET_LCD_SEG6_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG6_PA5_Msk)) | LCD_SEG6_PA5 /*!< Set PA5 function to LCD_SEG6 */ +#define SET_LCD_SEG7_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG7_PA6_Msk)) | LCD_SEG7_PA6 /*!< Set PA6 function to LCD_SEG7 */ +#define SET_LCD_SEG7_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG7_PE2_Msk)) | LCD_SEG7_PE2 /*!< Set PE2 function to LCD_SEG7 */ +#define SET_LCD_SEG8_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG8_PE3_Msk)) | LCD_SEG8_PE3 /*!< Set PE3 function to LCD_SEG8 */ +#define SET_LCD_SEG8_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG8_PA7_Msk)) | LCD_SEG8_PA7 /*!< Set PA7 function to LCD_SEG8 */ +#define SET_LCD_SEG9_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG9_PC6_Msk)) | LCD_SEG9_PC6 /*!< Set PC6 function to LCD_SEG9 */ +#define SET_LCD_SEG9_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG9_PE4_Msk)) | LCD_SEG9_PE4 /*!< Set PE4 function to LCD_SEG9 */ +#define SET_QEI0_A_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~QEI0_A_PD11_Msk)) | QEI0_A_PD11 /*!< Set PD11 function to QEI0_A */ +#define SET_QEI0_A_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QEI0_A_PA4_Msk)) | QEI0_A_PA4 /*!< Set PA4 function to QEI0_A */ +#define SET_QEI0_A_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI0_A_PE3_Msk)) | QEI0_A_PE3 /*!< Set PE3 function to QEI0_A */ +#define SET_QEI0_B_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI0_B_PE2_Msk)) | QEI0_B_PE2 /*!< Set PE2 function to QEI0_B */ +#define SET_QEI0_B_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~QEI0_B_PD10_Msk)) | QEI0_B_PD10 /*!< Set PD10 function to QEI0_B */ +#define SET_QEI0_B_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QEI0_B_PA3_Msk)) | QEI0_B_PA3 /*!< Set PA3 function to QEI0_B */ +#define SET_QEI0_INDEX_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI0_INDEX_PE4_Msk)) | QEI0_INDEX_PE4 /*!< Set PE4 function to QEI0_INDEX */ +#define SET_QEI0_INDEX_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QEI0_INDEX_PA5_Msk)) | QEI0_INDEX_PA5 /*!< Set PA5 function to QEI0_INDEX */ +#define SET_QEI0_INDEX_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~QEI0_INDEX_PD12_Msk)) | QEI0_INDEX_PD12 /*!< Set PD12 function to QEI0_INDEX */ +#define SET_QEI1_A_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_A_PA13_Msk)) | QEI1_A_PA13 /*!< Set PA13 function to QEI1_A */ +#define SET_QEI1_A_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI1_A_PE6_Msk)) | QEI1_A_PE6 /*!< Set PE6 function to QEI1_A */ +#define SET_QEI1_A_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_A_PA9_Msk)) | QEI1_A_PA9 /*!< Set PA9 function to QEI1_A */ +#define SET_QEI1_B_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI1_B_PE5_Msk)) | QEI1_B_PE5 /*!< Set PE5 function to QEI1_B */ +#define SET_QEI1_B_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_B_PA8_Msk)) | QEI1_B_PA8 /*!< Set PA8 function to QEI1_B */ +#define SET_QEI1_B_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_B_PA14_Msk)) | QEI1_B_PA14 /*!< Set PA14 function to QEI1_B */ +#define SET_QEI1_INDEX_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_INDEX_PA10_Msk)) | QEI1_INDEX_PA10 /*!< Set PA10 function to QEI1_INDEX */ +#define SET_QEI1_INDEX_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI1_INDEX_PE7_Msk)) | QEI1_INDEX_PE7 /*!< Set PE7 function to QEI1_INDEX */ +#define SET_QEI1_INDEX_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_INDEX_PA12_Msk)) | QEI1_INDEX_PA12 /*!< Set PA12 function to QEI1_INDEX */ +#define SET_QSPI0_CLK_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_CLK_PH8_Msk)) | QSPI0_CLK_PH8 /*!< Set PH8 function to QSPI0_CLK */ +#define SET_QSPI0_CLK_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~QSPI0_CLK_PF2_Msk)) | QSPI0_CLK_PF2 /*!< Set PF2 function to QSPI0_CLK */ +#define SET_QSPI0_CLK_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_CLK_PA2_Msk)) | QSPI0_CLK_PA2 /*!< Set PA2 function to QSPI0_CLK */ +#define SET_QSPI0_CLK_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_CLK_PC2_Msk)) | QSPI0_CLK_PC2 /*!< Set PC2 function to QSPI0_CLK */ +#define SET_QSPI0_MISO0_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MISO0_PC1_Msk)) | QSPI0_MISO0_PC1 /*!< Set PC1 function to QSPI0_MISO0 */ +#define SET_QSPI0_MISO0_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QSPI0_MISO0_PE1_Msk)) | QSPI0_MISO0_PE1 /*!< Set PE1 function to QSPI0_MISO0 */ +#define SET_QSPI0_MISO0_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MISO0_PA1_Msk)) | QSPI0_MISO0_PA1 /*!< Set PA1 function to QSPI0_MISO0 */ +#define SET_QSPI0_MISO1_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~QSPI0_MISO1_PB1_Msk)) | QSPI0_MISO1_PB1 /*!< Set PB1 function to QSPI0_MISO1 */ +#define SET_QSPI0_MISO1_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MISO1_PC5_Msk)) | QSPI0_MISO1_PC5 /*!< Set PC5 function to QSPI0_MISO1 */ +#define SET_QSPI0_MISO1_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_MISO1_PH10_Msk)) | QSPI0_MISO1_PH10 /*!< Set PH10 function to QSPI0_MISO1 */ +#define SET_QSPI0_MISO1_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MISO1_PA5_Msk)) | QSPI0_MISO1_PA5 /*!< Set PA5 function to QSPI0_MISO1 */ +#define SET_QSPI0_MOSI0_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MOSI0_PC0_Msk)) | QSPI0_MOSI0_PC0 /*!< Set PC0 function to QSPI0_MOSI0 */ +#define SET_QSPI0_MOSI0_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QSPI0_MOSI0_PE0_Msk)) | QSPI0_MOSI0_PE0 /*!< Set PE0 function to QSPI0_MOSI0 */ +#define SET_QSPI0_MOSI0_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MOSI0_PA0_Msk)) | QSPI0_MOSI0_PA0 /*!< Set PA0 function to QSPI0_MOSI0 */ +#define SET_QSPI0_MOSI1_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MOSI1_PC4_Msk)) | QSPI0_MOSI1_PC4 /*!< Set PC4 function to QSPI0_MOSI1 */ +#define SET_QSPI0_MOSI1_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_MOSI1_PH11_Msk)) | QSPI0_MOSI1_PH11 /*!< Set PH11 function to QSPI0_MOSI1 */ +#define SET_QSPI0_MOSI1_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~QSPI0_MOSI1_PB0_Msk)) | QSPI0_MOSI1_PB0 /*!< Set PB0 function to QSPI0_MOSI1 */ +#define SET_QSPI0_MOSI1_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MOSI1_PA4_Msk)) | QSPI0_MOSI1_PA4 /*!< Set PA4 function to QSPI0_MOSI1 */ +#define SET_QSPI0_SS_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_SS_PA3_Msk)) | QSPI0_SS_PA3 /*!< Set PA3 function to QSPI0_SS */ +#define SET_QSPI0_SS_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_SS_PC3_Msk)) | QSPI0_SS_PC3 /*!< Set PC3 function to QSPI0_SS */ +#define SET_QSPI0_SS_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_SS_PH9_Msk)) | QSPI0_SS_PH9 /*!< Set PH9 function to QSPI0_SS */ +#define SET_SC0_CLK_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_CLK_PA0_Msk)) | SC0_CLK_PA0 /*!< Set PA0 function to SC0_CLK */ +#define SET_SC0_CLK_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SC0_CLK_PF6_Msk)) | SC0_CLK_PF6 /*!< Set PF6 function to SC0_CLK */ +#define SET_SC0_CLK_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_CLK_PE2_Msk)) | SC0_CLK_PE2 /*!< Set PE2 function to SC0_CLK */ +#define SET_SC0_CLK_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_CLK_PB5_Msk)) | SC0_CLK_PB5 /*!< Set PB5 function to SC0_CLK */ +#define SET_SC0_DAT_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SC0_DAT_PF7_Msk)) | SC0_DAT_PF7 /*!< Set PF7 function to SC0_DAT */ +#define SET_SC0_DAT_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_DAT_PA1_Msk)) | SC0_DAT_PA1 /*!< Set PA1 function to SC0_DAT */ +#define SET_SC0_DAT_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_DAT_PE3_Msk)) | SC0_DAT_PE3 /*!< Set PE3 function to SC0_DAT */ +#define SET_SC0_DAT_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_DAT_PB4_Msk)) | SC0_DAT_PB4 /*!< Set PB4 function to SC0_DAT */ +#define SET_SC0_PWR_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SC0_PWR_PF9_Msk)) | SC0_PWR_PF9 /*!< Set PF9 function to SC0_PWR */ +#define SET_SC0_PWR_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_PWR_PE5_Msk)) | SC0_PWR_PE5 /*!< Set PE5 function to SC0_PWR */ +#define SET_SC0_PWR_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_PWR_PA3_Msk)) | SC0_PWR_PA3 /*!< Set PA3 function to SC0_PWR */ +#define SET_SC0_PWR_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_PWR_PB2_Msk)) | SC0_PWR_PB2 /*!< Set PB2 function to SC0_PWR */ +#define SET_SC0_RST_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_RST_PE4_Msk)) | SC0_RST_PE4 /*!< Set PE4 function to SC0_RST */ +#define SET_SC0_RST_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SC0_RST_PF8_Msk)) | SC0_RST_PF8 /*!< Set PF8 function to SC0_RST */ +#define SET_SC0_RST_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_RST_PA2_Msk)) | SC0_RST_PA2 /*!< Set PA2 function to SC0_RST */ +#define SET_SC0_RST_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_RST_PB3_Msk)) | SC0_RST_PB3 /*!< Set PB3 function to SC0_RST */ +#define SET_SC0_nCD_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SC0_nCD_PC12_Msk)) | SC0_nCD_PC12 /*!< Set PC12 function to SC0_nCD */ +#define SET_SC0_nCD_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_nCD_PA4_Msk)) | SC0_nCD_PA4 /*!< Set PA4 function to SC0_nCD */ +#define SET_SC0_nCD_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SC0_nCD_PF10_Msk)) | SC0_nCD_PF10 /*!< Set PF10 function to SC0_nCD */ +#define SET_SC0_nCD_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_nCD_PE6_Msk)) | SC0_nCD_PE6 /*!< Set PE6 function to SC0_nCD */ +#define SET_SC1_CLK_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_CLK_PB12_Msk)) | SC1_CLK_PB12 /*!< Set PB12 function to SC1_CLK */ +#define SET_SC1_CLK_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_CLK_PC0_Msk)) | SC1_CLK_PC0 /*!< Set PC0 function to SC1_CLK */ +#define SET_SC1_CLK_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_CLK_PD4_Msk)) | SC1_CLK_PD4 /*!< Set PD4 function to SC1_CLK */ +#define SET_SC1_DAT_PD5() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_DAT_PD5_Msk)) | SC1_DAT_PD5 /*!< Set PD5 function to SC1_DAT */ +#define SET_SC1_DAT_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_DAT_PC1_Msk)) | SC1_DAT_PC1 /*!< Set PC1 function to SC1_DAT */ +#define SET_SC1_DAT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_DAT_PB13_Msk)) | SC1_DAT_PB13 /*!< Set PB13 function to SC1_DAT */ +#define SET_SC1_PWR_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_PWR_PD7_Msk)) | SC1_PWR_PD7 /*!< Set PD7 function to SC1_PWR */ +#define SET_SC1_PWR_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_PWR_PC3_Msk)) | SC1_PWR_PC3 /*!< Set PC3 function to SC1_PWR */ +#define SET_SC1_PWR_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_PWR_PB15_Msk)) | SC1_PWR_PB15 /*!< Set PB15 function to SC1_PWR */ +#define SET_SC1_RST_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_RST_PD6_Msk)) | SC1_RST_PD6 /*!< Set PD6 function to SC1_RST */ +#define SET_SC1_RST_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_RST_PB14_Msk)) | SC1_RST_PB14 /*!< Set PB14 function to SC1_RST */ +#define SET_SC1_RST_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_RST_PC2_Msk)) | SC1_RST_PC2 /*!< Set PC2 function to SC1_RST */ +#define SET_SC1_nCD_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SC1_nCD_PD14_Msk)) | SC1_nCD_PD14 /*!< Set PD14 function to SC1_nCD */ +#define SET_SC1_nCD_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_nCD_PC4_Msk)) | SC1_nCD_PC4 /*!< Set PC4 function to SC1_nCD */ +#define SET_SC1_nCD_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_nCD_PD3_Msk)) | SC1_nCD_PD3 /*!< Set PD3 function to SC1_nCD */ +#define SET_SC2_CLK_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC2_CLK_PA6_Msk)) | SC2_CLK_PA6 /*!< Set PA6 function to SC2_CLK */ +#define SET_SC2_CLK_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_CLK_PD0_Msk)) | SC2_CLK_PD0 /*!< Set PD0 function to SC2_CLK */ +#define SET_SC2_CLK_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_CLK_PA15_Msk)) | SC2_CLK_PA15 /*!< Set PA15 function to SC2_CLK */ +#define SET_SC2_CLK_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_CLK_PA8_Msk)) | SC2_CLK_PA8 /*!< Set PA8 function to SC2_CLK */ +#define SET_SC2_CLK_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC2_CLK_PE0_Msk)) | SC2_CLK_PE0 /*!< Set PE0 function to SC2_CLK */ +#define SET_SC2_DAT_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_DAT_PA9_Msk)) | SC2_DAT_PA9 /*!< Set PA9 function to SC2_DAT */ +#define SET_SC2_DAT_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_DAT_PD1_Msk)) | SC2_DAT_PD1 /*!< Set PD1 function to SC2_DAT */ +#define SET_SC2_DAT_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC2_DAT_PA7_Msk)) | SC2_DAT_PA7 /*!< Set PA7 function to SC2_DAT */ +#define SET_SC2_DAT_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_DAT_PA14_Msk)) | SC2_DAT_PA14 /*!< Set PA14 function to SC2_DAT */ +#define SET_SC2_DAT_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC2_DAT_PE1_Msk)) | SC2_DAT_PE1 /*!< Set PE1 function to SC2_DAT */ +#define SET_SC2_PWR_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC2_PWR_PC7_Msk)) | SC2_PWR_PC7 /*!< Set PC7 function to SC2_PWR */ +#define SET_SC2_PWR_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SC2_PWR_PH8_Msk)) | SC2_PWR_PH8 /*!< Set PH8 function to SC2_PWR */ +#define SET_SC2_PWR_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_PWR_PD3_Msk)) | SC2_PWR_PD3 /*!< Set PD3 function to SC2_PWR */ +#define SET_SC2_PWR_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_PWR_PA11_Msk)) | SC2_PWR_PA11 /*!< Set PA11 function to SC2_PWR */ +#define SET_SC2_PWR_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_PWR_PA12_Msk)) | SC2_PWR_PA12 /*!< Set PA12 function to SC2_PWR */ +#define SET_SC2_RST_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_RST_PD2_Msk)) | SC2_RST_PD2 /*!< Set PD2 function to SC2_RST */ +#define SET_SC2_RST_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC2_RST_PC6_Msk)) | SC2_RST_PC6 /*!< Set PC6 function to SC2_RST */ +#define SET_SC2_RST_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SC2_RST_PH9_Msk)) | SC2_RST_PH9 /*!< Set PH9 function to SC2_RST */ +#define SET_SC2_RST_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_RST_PA13_Msk)) | SC2_RST_PA13 /*!< Set PA13 function to SC2_RST */ +#define SET_SC2_RST_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_RST_PA10_Msk)) | SC2_RST_PA10 /*!< Set PA10 function to SC2_RST */ +#define SET_SC2_nCD_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC2_nCD_PA5_Msk)) | SC2_nCD_PA5 /*!< Set PA5 function to SC2_nCD */ +#define SET_SC2_nCD_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SC2_nCD_PH10_Msk)) | SC2_nCD_PH10 /*!< Set PH10 function to SC2_nCD */ +#define SET_SC2_nCD_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SC2_nCD_PD13_Msk)) | SC2_nCD_PD13 /*!< Set PD13 function to SC2_nCD */ +#define SET_SC2_nCD_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SC2_nCD_PC13_Msk)) | SC2_nCD_PC13 /*!< Set PC13 function to SC2_nCD */ +#define SET_SD0_CLK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_CLK_PB1_Msk)) | SD0_CLK_PB1 /*!< Set PB1 function to SD0_CLK */ +#define SET_SD0_CLK_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_CLK_PE6_Msk)) | SD0_CLK_PE6 /*!< Set PE6 function to SD0_CLK */ +#define SET_SD0_CMD_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_CMD_PE7_Msk)) | SD0_CMD_PE7 /*!< Set PE7 function to SD0_CMD */ +#define SET_SD0_CMD_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_CMD_PB0_Msk)) | SD0_CMD_PB0 /*!< Set PB0 function to SD0_CMD */ +#define SET_SD0_DAT0_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT0_PE2_Msk)) | SD0_DAT0_PE2 /*!< Set PE2 function to SD0_DAT0 */ +#define SET_SD0_DAT0_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT0_PB2_Msk)) | SD0_DAT0_PB2 /*!< Set PB2 function to SD0_DAT0 */ +#define SET_SD0_DAT1_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT1_PE3_Msk)) | SD0_DAT1_PE3 /*!< Set PE3 function to SD0_DAT1 */ +#define SET_SD0_DAT1_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT1_PB3_Msk)) | SD0_DAT1_PB3 /*!< Set PB3 function to SD0_DAT1 */ +#define SET_SD0_DAT2_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT2_PE4_Msk)) | SD0_DAT2_PE4 /*!< Set PE4 function to SD0_DAT2 */ +#define SET_SD0_DAT2_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT2_PB4_Msk)) | SD0_DAT2_PB4 /*!< Set PB4 function to SD0_DAT2 */ +#define SET_SD0_DAT3_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT3_PE5_Msk)) | SD0_DAT3_PE5 /*!< Set PE5 function to SD0_DAT3 */ +#define SET_SD0_DAT3_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT3_PB5_Msk)) | SD0_DAT3_PB5 /*!< Set PB5 function to SD0_DAT3 */ +#define SET_SD0_nCD_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SD0_nCD_PD13_Msk)) | SD0_nCD_PD13 /*!< Set PD13 function to SD0_nCD */ +#define SET_SD0_nCD_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SD0_nCD_PB12_Msk)) | SD0_nCD_PB12 /*!< Set PB12 function to SD0_nCD */ +#define SET_SEG15_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SEG15_PC5_Msk)) | SEG15_PC5 /*!< Set PC5 function to SEG15 */ +#define SET_SEG16_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SEG16_PC4_Msk)) | SEG16_PC4 /*!< Set PC4 function to SEG16 */ +#define SET_SPI0_CLK_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_CLK_PD2_Msk)) | SPI0_CLK_PD2 /*!< Set PD2 function to SPI0_CLK */ +#define SET_SPI0_CLK_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_CLK_PB14_Msk)) | SPI0_CLK_PB14 /*!< Set PB14 function to SPI0_CLK */ +#define SET_SPI0_CLK_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI0_CLK_PF8_Msk)) | SPI0_CLK_PF8 /*!< Set PF8 function to SPI0_CLK */ +#define SET_SPI0_CLK_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_CLK_PA2_Msk)) | SPI0_CLK_PA2 /*!< Set PA2 function to SPI0_CLK */ +#define SET_SPI0_I2SMCLK_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_I2SMCLK_PB11_Msk)) | SPI0_I2SMCLK_PB11 /*!< Set PB11 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI0_I2SMCLK_PB0_Msk)) | SPI0_I2SMCLK_PB0 /*!< Set PB0 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI0_I2SMCLK_PF10_Msk)) | SPI0_I2SMCLK_PF10 /*!< Set PF10 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_I2SMCLK_PA4_Msk)) | SPI0_I2SMCLK_PA4 /*!< Set PA4 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI0_I2SMCLK_PD14_Msk)) | SPI0_I2SMCLK_PD14 /*!< Set PD14 function to SPI0_I2SMCLK */ +#define SET_SPI0_I2SMCLK_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI0_I2SMCLK_PD13_Msk)) | SPI0_I2SMCLK_PD13 /*!< Set PD13 function to SPI0_I2SMCLK */ +#define SET_SPI0_MISO_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_MISO_PA1_Msk)) | SPI0_MISO_PA1 /*!< Set PA1 function to SPI0_MISO */ +#define SET_SPI0_MISO_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SPI0_MISO_PF7_Msk)) | SPI0_MISO_PF7 /*!< Set PF7 function to SPI0_MISO */ +#define SET_SPI0_MISO_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_MISO_PD1_Msk)) | SPI0_MISO_PD1 /*!< Set PD1 function to SPI0_MISO */ +#define SET_SPI0_MISO_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_MISO_PB13_Msk)) | SPI0_MISO_PB13 /*!< Set PB13 function to SPI0_MISO */ +#define SET_SPI0_MOSI_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SPI0_MOSI_PF6_Msk)) | SPI0_MOSI_PF6 /*!< Set PF6 function to SPI0_MOSI */ +#define SET_SPI0_MOSI_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_MOSI_PD0_Msk)) | SPI0_MOSI_PD0 /*!< Set PD0 function to SPI0_MOSI */ +#define SET_SPI0_MOSI_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_MOSI_PB12_Msk)) | SPI0_MOSI_PB12 /*!< Set PB12 function to SPI0_MOSI */ +#define SET_SPI0_MOSI_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_MOSI_PA0_Msk)) | SPI0_MOSI_PA0 /*!< Set PA0 function to SPI0_MOSI */ +#define SET_SPI0_SS_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI0_SS_PF9_Msk)) | SPI0_SS_PF9 /*!< Set PF9 function to SPI0_SS */ +#define SET_SPI0_SS_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_SS_PA3_Msk)) | SPI0_SS_PA3 /*!< Set PA3 function to SPI0_SS */ +#define SET_SPI0_SS_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_SS_PB15_Msk)) | SPI0_SS_PB15 /*!< Set PB15 function to SPI0_SS */ +#define SET_SPI0_SS_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_SS_PD3_Msk)) | SPI0_SS_PD3 /*!< Set PD3 function to SPI0_SS */ +#define SET_SPI1_CLK_PD5() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_CLK_PD5_Msk)) | SPI1_CLK_PD5 /*!< Set PD5 function to SPI1_CLK */ +#define SET_SPI1_CLK_PH6() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_CLK_PH6_Msk)) | SPI1_CLK_PH6 /*!< Set PH6 function to SPI1_CLK */ +#define SET_SPI1_CLK_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_CLK_PC1_Msk)) | SPI1_CLK_PC1 /*!< Set PC1 function to SPI1_CLK */ +#define SET_SPI1_CLK_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_CLK_PB3_Msk)) | SPI1_CLK_PB3 /*!< Set PB3 function to SPI1_CLK */ +#define SET_SPI1_CLK_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SPI1_CLK_PH8_Msk)) | SPI1_CLK_PH8 /*!< Set PH8 function to SPI1_CLK */ +#define SET_SPI1_CLK_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI1_CLK_PA7_Msk)) | SPI1_CLK_PA7 /*!< Set PA7 function to SPI1_CLK */ +#define SET_SPI1_I2SMCLK_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_I2SMCLK_PC4_Msk)) | SPI1_I2SMCLK_PC4 /*!< Set PC4 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_I2SMCLK_PB1_Msk)) | SPI1_I2SMCLK_PB1 /*!< Set PB1 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI1_I2SMCLK_PA5_Msk)) | SPI1_I2SMCLK_PA5 /*!< Set PA5 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI1_I2SMCLK_PD13_Msk)) | SPI1_I2SMCLK_PD13 /*!< Set PD13 function to SPI1_I2SMCLK */ +#define SET_SPI1_I2SMCLK_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SPI1_I2SMCLK_PH10_Msk)) | SPI1_I2SMCLK_PH10 /*!< Set PH10 function to SPI1_I2SMCLK */ +#define SET_SPI1_MISO_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MISO_PC3_Msk)) | SPI1_MISO_PC3 /*!< Set PC3 function to SPI1_MISO */ +#define SET_SPI1_MISO_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MISO_PC7_Msk)) | SPI1_MISO_PC7 /*!< Set PC7 function to SPI1_MISO */ +#define SET_SPI1_MISO_PH4() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_MISO_PH4_Msk)) | SPI1_MISO_PH4 /*!< Set PH4 function to SPI1_MISO */ +#define SET_SPI1_MISO_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_MISO_PB5_Msk)) | SPI1_MISO_PB5 /*!< Set PB5 function to SPI1_MISO */ +#define SET_SPI1_MISO_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI1_MISO_PE1_Msk)) | SPI1_MISO_PE1 /*!< Set PE1 function to SPI1_MISO */ +#define SET_SPI1_MISO_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_MISO_PD7_Msk)) | SPI1_MISO_PD7 /*!< Set PD7 function to SPI1_MISO */ +#define SET_SPI1_MOSI_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI1_MOSI_PE0_Msk)) | SPI1_MOSI_PE0 /*!< Set PE0 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_MOSI_PB4_Msk)) | SPI1_MOSI_PB4 /*!< Set PB4 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MOSI_PC6_Msk)) | SPI1_MOSI_PC6 /*!< Set PC6 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_MOSI_PD6_Msk)) | SPI1_MOSI_PD6 /*!< Set PD6 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PH5() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_MOSI_PH5_Msk)) | SPI1_MOSI_PH5 /*!< Set PH5 function to SPI1_MOSI */ +#define SET_SPI1_MOSI_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MOSI_PC2_Msk)) | SPI1_MOSI_PC2 /*!< Set PC2 function to SPI1_MOSI */ +#define SET_SPI1_SS_PH7() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_SS_PH7_Msk)) | SPI1_SS_PH7 /*!< Set PH7 function to SPI1_SS */ +#define SET_SPI1_SS_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_SS_PB2_Msk)) | SPI1_SS_PB2 /*!< Set PB2 function to SPI1_SS */ +#define SET_SPI1_SS_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI1_SS_PA6_Msk)) | SPI1_SS_PA6 /*!< Set PA6 function to SPI1_SS */ +#define SET_SPI1_SS_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_SS_PD4_Msk)) | SPI1_SS_PD4 /*!< Set PD4 function to SPI1_SS */ +#define SET_SPI1_SS_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SPI1_SS_PH9_Msk)) | SPI1_SS_PH9 /*!< Set PH9 function to SPI1_SS */ +#define SET_SPI1_SS_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_SS_PC0_Msk)) | SPI1_SS_PC0 /*!< Set PC0 function to SPI1_SS */ +#define SET_SPI2_CLK_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_CLK_PE8_Msk)) | SPI2_CLK_PE8 /*!< Set PE8 function to SPI2_CLK */ +#define SET_SPI2_CLK_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_CLK_PA10_Msk)) | SPI2_CLK_PA10 /*!< Set PA10 function to SPI2_CLK */ +#define SET_SPI2_CLK_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_CLK_PA13_Msk)) | SPI2_CLK_PA13 /*!< Set PA13 function to SPI2_CLK */ +#define SET_SPI2_CLK_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~SPI2_CLK_PG3_Msk)) | SPI2_CLK_PG3 /*!< Set PG3 function to SPI2_CLK */ +#define SET_SPI2_I2SMCLK_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_I2SMCLK_PE12_Msk)) | SPI2_I2SMCLK_PE12 /*!< Set PE12 function to SPI2_I2SMCLK */ +#define SET_SPI2_I2SMCLK_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI2_I2SMCLK_PC13_Msk)) | SPI2_I2SMCLK_PC13 /*!< Set PC13 function to SPI2_I2SMCLK */ +#define SET_SPI2_I2SMCLK_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI2_I2SMCLK_PB0_Msk)) | SPI2_I2SMCLK_PB0 /*!< Set PB0 function to SPI2_I2SMCLK */ +#define SET_SPI2_MISO_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_MISO_PE9_Msk)) | SPI2_MISO_PE9 /*!< Set PE9 function to SPI2_MISO */ +#define SET_SPI2_MISO_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MISO_PA9_Msk)) | SPI2_MISO_PA9 /*!< Set PA9 function to SPI2_MISO */ +#define SET_SPI2_MISO_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MISO_PA14_Msk)) | SPI2_MISO_PA14 /*!< Set PA14 function to SPI2_MISO */ +#define SET_SPI2_MISO_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~SPI2_MISO_PG4_Msk)) | SPI2_MISO_PG4 /*!< Set PG4 function to SPI2_MISO */ +#define SET_SPI2_MOSI_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI2_MOSI_PF11_Msk)) | SPI2_MOSI_PF11 /*!< Set PF11 function to SPI2_MOSI */ +#define SET_SPI2_MOSI_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MOSI_PA15_Msk)) | SPI2_MOSI_PA15 /*!< Set PA15 function to SPI2_MOSI */ +#define SET_SPI2_MOSI_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_MOSI_PE10_Msk)) | SPI2_MOSI_PE10 /*!< Set PE10 function to SPI2_MOSI */ +#define SET_SPI2_MOSI_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MOSI_PA8_Msk)) | SPI2_MOSI_PA8 /*!< Set PA8 function to SPI2_MOSI */ +#define SET_SPI2_SS_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_SS_PE11_Msk)) | SPI2_SS_PE11 /*!< Set PE11 function to SPI2_SS */ +#define SET_SPI2_SS_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~SPI2_SS_PG2_Msk)) | SPI2_SS_PG2 /*!< Set PG2 function to SPI2_SS */ +#define SET_SPI2_SS_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_SS_PA11_Msk)) | SPI2_SS_PA11 /*!< Set PA11 function to SPI2_SS */ +#define SET_SPI2_SS_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_SS_PA12_Msk)) | SPI2_SS_PA12 /*!< Set PA12 function to SPI2_SS */ +#define SET_SPI3_CLK_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_CLK_PC10_Msk)) | SPI3_CLK_PC10 /*!< Set PC10 function to SPI3_CLK */ +#define SET_SPI3_CLK_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_CLK_PE4_Msk)) | SPI3_CLK_PE4 /*!< Set PE4 function to SPI3_CLK */ +#define SET_SPI3_CLK_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_CLK_PB11_Msk)) | SPI3_CLK_PB11 /*!< Set PB11 function to SPI3_CLK */ +#define SET_SPI3_I2SMCLK_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_I2SMCLK_PE6_Msk)) | SPI3_I2SMCLK_PE6 /*!< Set PE6 function to SPI3_I2SMCLK */ +#define SET_SPI3_I2SMCLK_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SPI3_I2SMCLK_PF6_Msk)) | SPI3_I2SMCLK_PF6 /*!< Set PF6 function to SPI3_I2SMCLK */ +#define SET_SPI3_I2SMCLK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI3_I2SMCLK_PB1_Msk)) | SPI3_I2SMCLK_PB1 /*!< Set PB1 function to SPI3_I2SMCLK */ +#define SET_SPI3_I2SMCLK_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI3_I2SMCLK_PD14_Msk)) | SPI3_I2SMCLK_PD14 /*!< Set PD14 function to SPI3_I2SMCLK */ +#define SET_SPI3_MISO_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_MISO_PE3_Msk)) | SPI3_MISO_PE3 /*!< Set PE3 function to SPI3_MISO */ +#define SET_SPI3_MISO_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_MISO_PC12_Msk)) | SPI3_MISO_PC12 /*!< Set PC12 function to SPI3_MISO */ +#define SET_SPI3_MISO_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_MISO_PB9_Msk)) | SPI3_MISO_PB9 /*!< Set PB9 function to SPI3_MISO */ +#define SET_SPI3_MOSI_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_MOSI_PC11_Msk)) | SPI3_MOSI_PC11 /*!< Set PC11 function to SPI3_MOSI */ +#define SET_SPI3_MOSI_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_MOSI_PE2_Msk)) | SPI3_MOSI_PE2 /*!< Set PE2 function to SPI3_MOSI */ +#define SET_SPI3_MOSI_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_MOSI_PB8_Msk)) | SPI3_MOSI_PB8 /*!< Set PB8 function to SPI3_MOSI */ +#define SET_SPI3_SS_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_SS_PE5_Msk)) | SPI3_SS_PE5 /*!< Set PE5 function to SPI3_SS */ +#define SET_SPI3_SS_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_SS_PB10_Msk)) | SPI3_SS_PB10 /*!< Set PB10 function to SPI3_SS */ +#define SET_SPI3_SS_PC9() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_SS_PC9_Msk)) | SPI3_SS_PC9 /*!< Set PC9 function to SPI3_SS */ +#define SET_TAMPER0_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~TAMPER0_PF6_Msk)) | TAMPER0_PF6 /*!< Set PF6 function to TAMPER0 */ +#define SET_TAMPER1_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~TAMPER1_PF7_Msk)) | TAMPER1_PF7 /*!< Set PF7 function to TAMPER1 */ +#define SET_TAMPER2_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER2_PF8_Msk)) | TAMPER2_PF8 /*!< Set PF8 function to TAMPER2 */ +#define SET_TAMPER3_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER3_PF9_Msk)) | TAMPER3_PF9 /*!< Set PF9 function to TAMPER3 */ +#define SET_TAMPER4_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER4_PF10_Msk)) | TAMPER4_PF10 /*!< Set PF10 function to TAMPER4 */ +#define SET_TAMPER5_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER5_PF11_Msk)) | TAMPER5_PF11 /*!< Set PF11 function to TAMPER5 */ +#define SET_TM0_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM0_PG2_Msk)) | TM0_PG2 /*!< Set PG2 function to TM0 */ +#define SET_TM0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM0_PB5_Msk)) | TM0_PB5 /*!< Set PB5 function to TM0 */ +#define SET_TM0_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~TM0_PC7_Msk)) | TM0_PC7 /*!< Set PC7 function to TM0 */ +#define SET_TM0_EXT_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM0_EXT_PB15_Msk)) | TM0_EXT_PB15 /*!< Set PB15 function to TM0_EXT */ +#define SET_TM0_EXT_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM0_EXT_PA11_Msk)) | TM0_EXT_PA11 /*!< Set PA11 function to TM0_EXT */ +#define SET_TM1_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~TM1_PC6_Msk)) | TM1_PC6 /*!< Set PC6 function to TM1 */ +#define SET_TM1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM1_PB4_Msk)) | TM1_PB4 /*!< Set PB4 function to TM1 */ +#define SET_TM1_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM1_PG3_Msk)) | TM1_PG3 /*!< Set PG3 function to TM1 */ +#define SET_TM1_EXT_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM1_EXT_PB14_Msk)) | TM1_EXT_PB14 /*!< Set PB14 function to TM1_EXT */ +#define SET_TM1_EXT_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM1_EXT_PA10_Msk)) | TM1_EXT_PA10 /*!< Set PA10 function to TM1_EXT */ +#define SET_TM2_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM2_PB3_Msk)) | TM2_PB3 /*!< Set PB3 function to TM2 */ +#define SET_TM2_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM2_PA7_Msk)) | TM2_PA7 /*!< Set PA7 function to TM2 */ +#define SET_TM2_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~TM2_PD0_Msk)) | TM2_PD0 /*!< Set PD0 function to TM2 */ +#define SET_TM2_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM2_PG4_Msk)) | TM2_PG4 /*!< Set PG4 function to TM2 */ +#define SET_TM2_EXT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM2_EXT_PB13_Msk)) | TM2_EXT_PB13 /*!< Set PB13 function to TM2_EXT */ +#define SET_TM2_EXT_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM2_EXT_PA9_Msk)) | TM2_EXT_PA9 /*!< Set PA9 function to TM2_EXT */ +#define SET_TM3_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM3_PB2_Msk)) | TM3_PB2 /*!< Set PB2 function to TM3 */ +#define SET_TM3_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM3_PA6_Msk)) | TM3_PA6 /*!< Set PA6 function to TM3 */ +#define SET_TM3_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TM3_PF11_Msk)) | TM3_PF11 /*!< Set PF11 function to TM3 */ +#define SET_TM3_EXT_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM3_EXT_PB12_Msk)) | TM3_EXT_PB12 /*!< Set PB12 function to TM3_EXT */ +#define SET_TM3_EXT_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM3_EXT_PA8_Msk)) | TM3_EXT_PA8 /*!< Set PA8 function to TM3_EXT */ +#define SET_TM4_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM4_PA7_Msk)) | TM4_PA7 /*!< Set PA7 function to TM4 */ +#define SET_TM4_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM4_PG4_Msk)) | TM4_PG4 /*!< Set PG4 function to TM4 */ +#define SET_TM4_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM4_PB3_Msk)) | TM4_PB3 /*!< Set PB3 function to TM4 */ +#define SET_TM4_EXT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM4_EXT_PB13_Msk)) | TM4_EXT_PB13 /*!< Set PB13 function to TM4_EXT */ +#define SET_TM4_EXT_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM4_EXT_PA9_Msk)) | TM4_EXT_PA9 /*!< Set PA9 function to TM4_EXT */ +#define SET_TM5_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TM5_PF11_Msk)) | TM5_PF11 /*!< Set PF11 function to TM5 */ +#define SET_TM5_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM5_PB2_Msk)) | TM5_PB2 /*!< Set PB2 function to TM5 */ +#define SET_TM5_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM5_PA6_Msk)) | TM5_PA6 /*!< Set PA6 function to TM5 */ +#define SET_TM5_EXT_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM5_EXT_PA8_Msk)) | TM5_EXT_PA8 /*!< Set PA8 function to TM5_EXT */ +#define SET_TM5_EXT_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM5_EXT_PB12_Msk)) | TM5_EXT_PB12 /*!< Set PB12 function to TM5_EXT */ +#define SET_TRACE_CLK_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_CLK_PE12_Msk)) | TRACE_CLK_PE12 /*!< Set PE12 function to TRACE_CLK */ +#define SET_TRACE_DATA0_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA0_PE11_Msk)) | TRACE_DATA0_PE11 /*!< Set PE11 function to TRACE_DATA0 */ +#define SET_TRACE_DATA1_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA1_PE10_Msk)) | TRACE_DATA1_PE10 /*!< Set PE10 function to TRACE_DATA1 */ +#define SET_TRACE_DATA2_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA2_PE9_Msk)) | TRACE_DATA2_PE9 /*!< Set PE9 function to TRACE_DATA2 */ +#define SET_TRACE_DATA3_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA3_PE8_Msk)) | TRACE_DATA3_PE8 /*!< Set PE8 function to TRACE_DATA3 */ +#define SET_UART0_RXD_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART0_RXD_PA15_Msk)) | UART0_RXD_PA15 /*!< Set PA15 function to UART0_RXD */ +#define SET_UART0_RXD_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART0_RXD_PD2_Msk)) | UART0_RXD_PD2 /*!< Set PD2 function to UART0_RXD */ +#define SET_UART0_RXD_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_RXD_PA4_Msk)) | UART0_RXD_PA4 /*!< Set PA4 function to UART0_RXD */ +#define SET_UART0_RXD_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_RXD_PB12_Msk)) | UART0_RXD_PB12 /*!< Set PB12 function to UART0_RXD */ +#define SET_UART0_RXD_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_RXD_PA0_Msk)) | UART0_RXD_PA0 /*!< Set PA0 function to UART0_RXD */ +#define SET_UART0_RXD_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_RXD_PF1_Msk)) | UART0_RXD_PF1 /*!< Set PF1 function to UART0_RXD */ +#define SET_UART0_RXD_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART0_RXD_PC11_Msk)) | UART0_RXD_PC11 /*!< Set PC11 function to UART0_RXD */ +#define SET_UART0_RXD_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_RXD_PB8_Msk)) | UART0_RXD_PB8 /*!< Set PB8 function to UART0_RXD */ +#define SET_UART0_RXD_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART0_RXD_PH11_Msk)) | UART0_RXD_PH11 /*!< Set PH11 function to UART0_RXD */ +#define SET_UART0_RXD_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_RXD_PA6_Msk)) | UART0_RXD_PA6 /*!< Set PA6 function to UART0_RXD */ +#define SET_UART0_RXD_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_RXD_PF2_Msk)) | UART0_RXD_PF2 /*!< Set PF2 function to UART0_RXD */ +#define SET_UART0_TXD_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_TXD_PA5_Msk)) | UART0_TXD_PA5 /*!< Set PA5 function to UART0_TXD */ +#define SET_UART0_TXD_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART0_TXD_PA14_Msk)) | UART0_TXD_PA14 /*!< Set PA14 function to UART0_TXD */ +#define SET_UART0_TXD_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_TXD_PF3_Msk)) | UART0_TXD_PF3 /*!< Set PF3 function to UART0_TXD */ +#define SET_UART0_TXD_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_TXD_PA1_Msk)) | UART0_TXD_PA1 /*!< Set PA1 function to UART0_TXD */ +#define SET_UART0_TXD_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART0_TXD_PH10_Msk)) | UART0_TXD_PH10 /*!< Set PH10 function to UART0_TXD */ +#define SET_UART0_TXD_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART0_TXD_PD3_Msk)) | UART0_TXD_PD3 /*!< Set PD3 function to UART0_TXD */ +#define SET_UART0_TXD_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_TXD_PB9_Msk)) | UART0_TXD_PB9 /*!< Set PB9 function to UART0_TXD */ +#define SET_UART0_TXD_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_TXD_PB13_Msk)) | UART0_TXD_PB13 /*!< Set PB13 function to UART0_TXD */ +#define SET_UART0_TXD_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_TXD_PA7_Msk)) | UART0_TXD_PA7 /*!< Set PA7 function to UART0_TXD */ +#define SET_UART0_TXD_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_TXD_PF0_Msk)) | UART0_TXD_PF0 /*!< Set PF0 function to UART0_TXD */ +#define SET_UART0_TXD_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART0_TXD_PC12_Msk)) | UART0_TXD_PC12 /*!< Set PC12 function to UART0_TXD */ +#define SET_UART0_nCTS_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nCTS_PB15_Msk)) | UART0_nCTS_PB15 /*!< Set PB15 function to UART0_nCTS */ +#define SET_UART0_nCTS_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nCTS_PB11_Msk)) | UART0_nCTS_PB11 /*!< Set PB11 function to UART0_nCTS */ +#define SET_UART0_nCTS_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART0_nCTS_PC7_Msk)) | UART0_nCTS_PC7 /*!< Set PC7 function to UART0_nCTS */ +#define SET_UART0_nCTS_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_nCTS_PA5_Msk)) | UART0_nCTS_PA5 /*!< Set PA5 function to UART0_nCTS */ +#define SET_UART0_nRTS_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART0_nRTS_PC6_Msk)) | UART0_nRTS_PC6 /*!< Set PC6 function to UART0_nRTS */ +#define SET_UART0_nRTS_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nRTS_PB14_Msk)) | UART0_nRTS_PB14 /*!< Set PB14 function to UART0_nRTS */ +#define SET_UART0_nRTS_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nRTS_PB10_Msk)) | UART0_nRTS_PB10 /*!< Set PB10 function to UART0_nRTS */ +#define SET_UART0_nRTS_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_nRTS_PA4_Msk)) | UART0_nRTS_PA4 /*!< Set PA4 function to UART0_nRTS */ +#define SET_UART1_RXD_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART1_RXD_PA8_Msk)) | UART1_RXD_PA8 /*!< Set PA8 function to UART1_RXD */ +#define SET_UART1_RXD_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_RXD_PB6_Msk)) | UART1_RXD_PB6 /*!< Set PB6 function to UART1_RXD */ +#define SET_UART1_RXD_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART1_RXD_PC8_Msk)) | UART1_RXD_PC8 /*!< Set PC8 function to UART1_RXD */ +#define SET_UART1_RXD_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_RXD_PA2_Msk)) | UART1_RXD_PA2 /*!< Set PA2 function to UART1_RXD */ +#define SET_UART1_RXD_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART1_RXD_PH9_Msk)) | UART1_RXD_PH9 /*!< Set PH9 function to UART1_RXD */ +#define SET_UART1_RXD_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART1_RXD_PD10_Msk)) | UART1_RXD_PD10 /*!< Set PD10 function to UART1_RXD */ +#define SET_UART1_RXD_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_RXD_PB2_Msk)) | UART1_RXD_PB2 /*!< Set PB2 function to UART1_RXD */ +#define SET_UART1_RXD_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART1_RXD_PD6_Msk)) | UART1_RXD_PD6 /*!< Set PD6 function to UART1_RXD */ +#define SET_UART1_RXD_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART1_RXD_PF1_Msk)) | UART1_RXD_PF1 /*!< Set PF1 function to UART1_RXD */ +#define SET_UART1_TXD_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART1_TXD_PA9_Msk)) | UART1_TXD_PA9 /*!< Set PA9 function to UART1_TXD */ +#define SET_UART1_TXD_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART1_TXD_PD11_Msk)) | UART1_TXD_PD11 /*!< Set PD11 function to UART1_TXD */ +#define SET_UART1_TXD_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART1_TXD_PF0_Msk)) | UART1_TXD_PF0 /*!< Set PF0 function to UART1_TXD */ +#define SET_UART1_TXD_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_TXD_PB3_Msk)) | UART1_TXD_PB3 /*!< Set PB3 function to UART1_TXD */ +#define SET_UART1_TXD_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART1_TXD_PH8_Msk)) | UART1_TXD_PH8 /*!< Set PH8 function to UART1_TXD */ +#define SET_UART1_TXD_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_TXD_PA3_Msk)) | UART1_TXD_PA3 /*!< Set PA3 function to UART1_TXD */ +#define SET_UART1_TXD_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART1_TXD_PD7_Msk)) | UART1_TXD_PD7 /*!< Set PD7 function to UART1_TXD */ +#define SET_UART1_TXD_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART1_TXD_PE13_Msk)) | UART1_TXD_PE13 /*!< Set PE13 function to UART1_TXD */ +#define SET_UART1_TXD_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_TXD_PB7_Msk)) | UART1_TXD_PB7 /*!< Set PB7 function to UART1_TXD */ +#define SET_UART1_nCTS_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART1_nCTS_PB9_Msk)) | UART1_nCTS_PB9 /*!< Set PB9 function to UART1_nCTS */ +#define SET_UART1_nCTS_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART1_nCTS_PE11_Msk)) | UART1_nCTS_PE11 /*!< Set PE11 function to UART1_nCTS */ +#define SET_UART1_nCTS_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_nCTS_PA1_Msk)) | UART1_nCTS_PA1 /*!< Set PA1 function to UART1_nCTS */ +#define SET_UART1_nRTS_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART1_nRTS_PB8_Msk)) | UART1_nRTS_PB8 /*!< Set PB8 function to UART1_nRTS */ +#define SET_UART1_nRTS_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_nRTS_PA0_Msk)) | UART1_nRTS_PA0 /*!< Set PA0 function to UART1_nRTS */ +#define SET_UART1_nRTS_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART1_nRTS_PE12_Msk)) | UART1_nRTS_PE12 /*!< Set PE12 function to UART1_nRTS */ +#define SET_UART2_RXD_PE15() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_RXD_PE15_Msk)) | UART2_RXD_PE15 /*!< Set PE15 function to UART2_RXD */ +#define SET_UART2_RXD_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_RXD_PC4_Msk)) | UART2_RXD_PC4 /*!< Set PC4 function to UART2_RXD */ +#define SET_UART2_RXD_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART2_RXD_PD12_Msk)) | UART2_RXD_PD12 /*!< Set PD12 function to UART2_RXD */ +#define SET_UART2_RXD_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_RXD_PF5_Msk)) | UART2_RXD_PF5 /*!< Set PF5 function to UART2_RXD */ +#define SET_UART2_RXD_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_RXD_PE9_Msk)) | UART2_RXD_PE9 /*!< Set PE9 function to UART2_RXD */ +#define SET_UART2_RXD_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_RXD_PC0_Msk)) | UART2_RXD_PC0 /*!< Set PC0 function to UART2_RXD */ +#define SET_UART2_RXD_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_RXD_PB0_Msk)) | UART2_RXD_PB0 /*!< Set PB0 function to UART2_RXD */ +#define SET_UART2_RXD_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_RXD_PB4_Msk)) | UART2_RXD_PB4 /*!< Set PB4 function to UART2_RXD */ +#define SET_UART2_TXD_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_TXD_PF4_Msk)) | UART2_TXD_PF4 /*!< Set PF4 function to UART2_TXD */ +#define SET_UART2_TXD_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_TXD_PC1_Msk)) | UART2_TXD_PC1 /*!< Set PC1 function to UART2_TXD */ +#define SET_UART2_TXD_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_TXD_PB5_Msk)) | UART2_TXD_PB5 /*!< Set PB5 function to UART2_TXD */ +#define SET_UART2_TXD_PE14() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_TXD_PE14_Msk)) | UART2_TXD_PE14 /*!< Set PE14 function to UART2_TXD */ +#define SET_UART2_TXD_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART2_TXD_PC13_Msk)) | UART2_TXD_PC13 /*!< Set PC13 function to UART2_TXD */ +#define SET_UART2_TXD_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_TXD_PC5_Msk)) | UART2_TXD_PC5 /*!< Set PC5 function to UART2_TXD */ +#define SET_UART2_TXD_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_TXD_PE8_Msk)) | UART2_TXD_PE8 /*!< Set PE8 function to UART2_TXD */ +#define SET_UART2_TXD_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_TXD_PB1_Msk)) | UART2_TXD_PB1 /*!< Set PB1 function to UART2_TXD */ +#define SET_UART2_nCTS_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_nCTS_PF5_Msk)) | UART2_nCTS_PF5 /*!< Set PF5 function to UART2_nCTS */ +#define SET_UART2_nCTS_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART2_nCTS_PD9_Msk)) | UART2_nCTS_PD9 /*!< Set PD9 function to UART2_nCTS */ +#define SET_UART2_nCTS_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_nCTS_PC2_Msk)) | UART2_nCTS_PC2 /*!< Set PC2 function to UART2_nCTS */ +#define SET_UART2_nRTS_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_nRTS_PC3_Msk)) | UART2_nRTS_PC3 /*!< Set PC3 function to UART2_nRTS */ +#define SET_UART2_nRTS_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART2_nRTS_PD8_Msk)) | UART2_nRTS_PD8 /*!< Set PD8 function to UART2_nRTS */ +#define SET_UART2_nRTS_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_nRTS_PF4_Msk)) | UART2_nRTS_PF4 /*!< Set PF4 function to UART2_nRTS */ +#define SET_UART3_RXD_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_RXD_PD0_Msk)) | UART3_RXD_PD0 /*!< Set PD0 function to UART3_RXD */ +#define SET_UART3_RXD_PC9() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART3_RXD_PC9_Msk)) | UART3_RXD_PC9 /*!< Set PC9 function to UART3_RXD */ +#define SET_UART3_RXD_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART3_RXD_PE0_Msk)) | UART3_RXD_PE0 /*!< Set PE0 function to UART3_RXD */ +#define SET_UART3_RXD_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART3_RXD_PC2_Msk)) | UART3_RXD_PC2 /*!< Set PC2 function to UART3_RXD */ +#define SET_UART3_RXD_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_RXD_PB14_Msk)) | UART3_RXD_PB14 /*!< Set PB14 function to UART3_RXD */ +#define SET_UART3_RXD_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART3_RXD_PE11_Msk)) | UART3_RXD_PE11 /*!< Set PE11 function to UART3_RXD */ +#define SET_UART3_TXD_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART3_TXD_PC10_Msk)) | UART3_TXD_PC10 /*!< Set PC10 function to UART3_TXD */ +#define SET_UART3_TXD_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_TXD_PB15_Msk)) | UART3_TXD_PB15 /*!< Set PB15 function to UART3_TXD */ +#define SET_UART3_TXD_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART3_TXD_PE10_Msk)) | UART3_TXD_PE10 /*!< Set PE10 function to UART3_TXD */ +#define SET_UART3_TXD_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART3_TXD_PC3_Msk)) | UART3_TXD_PC3 /*!< Set PC3 function to UART3_TXD */ +#define SET_UART3_TXD_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_TXD_PD1_Msk)) | UART3_TXD_PD1 /*!< Set PD1 function to UART3_TXD */ +#define SET_UART3_TXD_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART3_TXD_PE1_Msk)) | UART3_TXD_PE1 /*!< Set PE1 function to UART3_TXD */ +#define SET_UART3_nCTS_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_nCTS_PB12_Msk)) | UART3_nCTS_PB12 /*!< Set PB12 function to UART3_nCTS */ +#define SET_UART3_nCTS_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART3_nCTS_PH9_Msk)) | UART3_nCTS_PH9 /*!< Set PH9 function to UART3_nCTS */ +#define SET_UART3_nCTS_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_nCTS_PD2_Msk)) | UART3_nCTS_PD2 /*!< Set PD2 function to UART3_nCTS */ +#define SET_UART3_nRTS_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART3_nRTS_PH8_Msk)) | UART3_nRTS_PH8 /*!< Set PH8 function to UART3_nRTS */ +#define SET_UART3_nRTS_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_nRTS_PD3_Msk)) | UART3_nRTS_PD3 /*!< Set PD3 function to UART3_nRTS */ +#define SET_UART3_nRTS_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_nRTS_PB13_Msk)) | UART3_nRTS_PB13 /*!< Set PB13 function to UART3_nRTS */ +#define SET_UART4_RXD_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART4_RXD_PA2_Msk)) | UART4_RXD_PA2 /*!< Set PA2 function to UART4_RXD */ +#define SET_UART4_RXD_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART4_RXD_PA13_Msk)) | UART4_RXD_PA13 /*!< Set PA13 function to UART4_RXD */ +#define SET_UART4_RXD_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_RXD_PC4_Msk)) | UART4_RXD_PC4 /*!< Set PC4 function to UART4_RXD */ +#define SET_UART4_RXD_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART4_RXD_PH11_Msk)) | UART4_RXD_PH11 /*!< Set PH11 function to UART4_RXD */ +#define SET_UART4_RXD_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART4_RXD_PF6_Msk)) | UART4_RXD_PF6 /*!< Set PF6 function to UART4_RXD */ +#define SET_UART4_RXD_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART4_RXD_PB10_Msk)) | UART4_RXD_PB10 /*!< Set PB10 function to UART4_RXD */ +#define SET_UART4_RXD_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_RXD_PC6_Msk)) | UART4_RXD_PC6 /*!< Set PC6 function to UART4_RXD */ +#define SET_UART4_TXD_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART4_TXD_PA3_Msk)) | UART4_TXD_PA3 /*!< Set PA3 function to UART4_TXD */ +#define SET_UART4_TXD_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_TXD_PC5_Msk)) | UART4_TXD_PC5 /*!< Set PC5 function to UART4_TXD */ +#define SET_UART4_TXD_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_TXD_PC7_Msk)) | UART4_TXD_PC7 /*!< Set PC7 function to UART4_TXD */ +#define SET_UART4_TXD_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART4_TXD_PA12_Msk)) | UART4_TXD_PA12 /*!< Set PA12 function to UART4_TXD */ +#define SET_UART4_TXD_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART4_TXD_PF7_Msk)) | UART4_TXD_PF7 /*!< Set PF7 function to UART4_TXD */ +#define SET_UART4_TXD_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART4_TXD_PH10_Msk)) | UART4_TXD_PH10 /*!< Set PH10 function to UART4_TXD */ +#define SET_UART4_TXD_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART4_TXD_PB11_Msk)) | UART4_TXD_PB11 /*!< Set PB11 function to UART4_TXD */ +#define SET_UART4_nCTS_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART4_nCTS_PC8_Msk)) | UART4_nCTS_PC8 /*!< Set PC8 function to UART4_nCTS */ +#define SET_UART4_nCTS_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART4_nCTS_PE1_Msk)) | UART4_nCTS_PE1 /*!< Set PE1 function to UART4_nCTS */ +#define SET_UART4_nRTS_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART4_nRTS_PE0_Msk)) | UART4_nRTS_PE0 /*!< Set PE0 function to UART4_nRTS */ +#define SET_UART4_nRTS_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART4_nRTS_PE13_Msk)) | UART4_nRTS_PE13 /*!< Set PE13 function to UART4_nRTS */ +#define SET_UART5_RXD_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_RXD_PB4_Msk)) | UART5_RXD_PB4 /*!< Set PB4 function to UART5_RXD */ +#define SET_UART5_RXD_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_RXD_PF10_Msk)) | UART5_RXD_PF10 /*!< Set PF10 function to UART5_RXD */ +#define SET_UART5_RXD_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART5_RXD_PE6_Msk)) | UART5_RXD_PE6 /*!< Set PE6 function to UART5_RXD */ +#define SET_UART5_RXD_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART5_RXD_PA4_Msk)) | UART5_RXD_PA4 /*!< Set PA4 function to UART5_RXD */ +#define SET_UART5_TXD_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_TXD_PF11_Msk)) | UART5_TXD_PF11 /*!< Set PF11 function to UART5_TXD */ +#define SET_UART5_TXD_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_TXD_PB5_Msk)) | UART5_TXD_PB5 /*!< Set PB5 function to UART5_TXD */ +#define SET_UART5_TXD_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART5_TXD_PE7_Msk)) | UART5_TXD_PE7 /*!< Set PE7 function to UART5_TXD */ +#define SET_UART5_TXD_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART5_TXD_PA5_Msk)) | UART5_TXD_PA5 /*!< Set PA5 function to UART5_TXD */ +#define SET_UART5_nCTS_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_nCTS_PB2_Msk)) | UART5_nCTS_PB2 /*!< Set PB2 function to UART5_nCTS */ +#define SET_UART5_nCTS_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_nCTS_PF8_Msk)) | UART5_nCTS_PF8 /*!< Set PF8 function to UART5_nCTS */ +#define SET_UART5_nRTS_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_nRTS_PF9_Msk)) | UART5_nRTS_PF9 /*!< Set PF9 function to UART5_nRTS */ +#define SET_UART5_nRTS_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_nRTS_PB3_Msk)) | UART5_nRTS_PB3 /*!< Set PB3 function to UART5_nRTS */ +#define SET_USB_D_P_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_D_P_PA14_Msk)) | USB_D_P_PA14 /*!< Set PA14 function to USB_D_P */ +#define SET_USB_D_N_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_D_N_PA13_Msk)) | USB_D_N_PA13 /*!< Set PA13 function to USB_D_N */ +#define SET_USB_OTG_ID_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_OTG_ID_PA15_Msk)) | USB_OTG_ID_PA15 /*!< Set PA15 function to USB_OTG_ID */ +#define SET_USB_VBUS_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_VBUS_PA12_Msk)) | USB_VBUS_PA12 /*!< Set PA12 function to USB_VBUS */ +#define SET_USB_VBUS_EN_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USB_VBUS_EN_PB15_Msk)) | USB_VBUS_EN_PB15 /*!< Set PB15 function to USB_VBUS_EN */ +#define SET_USB_VBUS_EN_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USB_VBUS_EN_PB6_Msk)) | USB_VBUS_EN_PB6 /*!< Set PB6 function to USB_VBUS_EN */ +#define SET_USB_VBUS_ST_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USB_VBUS_ST_PB14_Msk)) | USB_VBUS_ST_PB14 /*!< Set PB14 function to USB_VBUS_ST */ +#define SET_USB_VBUS_ST_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USB_VBUS_ST_PB7_Msk)) | USB_VBUS_ST_PB7 /*!< Set PB7 function to USB_VBUS_ST */ +#define SET_USB_VBUS_ST_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USB_VBUS_ST_PD4_Msk)) | USB_VBUS_ST_PD4 /*!< Set PD4 function to USB_VBUS_ST */ +#define SET_USCI0_CLK_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_CLK_PA11_Msk)) | USCI0_CLK_PA11 /*!< Set PA11 function to USCI0_CLK */ +#define SET_USCI0_CLK_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_CLK_PD0_Msk)) | USCI0_CLK_PD0 /*!< Set PD0 function to USCI0_CLK */ +#define SET_USCI0_CLK_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_CLK_PB12_Msk)) | USCI0_CLK_PB12 /*!< Set PB12 function to USCI0_CLK */ +#define SET_USCI0_CLK_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_CLK_PE2_Msk)) | USCI0_CLK_PE2 /*!< Set PE2 function to USCI0_CLK */ +#define SET_USCI0_CTL0_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~USCI0_CTL0_PC13_Msk)) | USCI0_CTL0_PC13 /*!< Set PC13 function to USCI0_CTL0 */ +#define SET_USCI0_CTL0_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~USCI0_CTL0_PD14_Msk)) | USCI0_CTL0_PD14 /*!< Set PD14 function to USCI0_CTL0 */ +#define SET_USCI0_CTL0_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_CTL0_PE6_Msk)) | USCI0_CTL0_PE6 /*!< Set PE6 function to USCI0_CTL0 */ +#define SET_USCI0_CTL0_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_CTL0_PD4_Msk)) | USCI0_CTL0_PD4 /*!< Set PD4 function to USCI0_CTL0 */ +#define SET_USCI0_CTL1_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_CTL1_PD3_Msk)) | USCI0_CTL1_PD3 /*!< Set PD3 function to USCI0_CTL1 */ +#define SET_USCI0_CTL1_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_CTL1_PA8_Msk)) | USCI0_CTL1_PA8 /*!< Set PA8 function to USCI0_CTL1 */ +#define SET_USCI0_CTL1_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_CTL1_PE5_Msk)) | USCI0_CTL1_PE5 /*!< Set PE5 function to USCI0_CTL1 */ +#define SET_USCI0_CTL1_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_CTL1_PB15_Msk)) | USCI0_CTL1_PB15 /*!< Set PB15 function to USCI0_CTL1 */ +#define SET_USCI0_DAT0_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_DAT0_PB13_Msk)) | USCI0_DAT0_PB13 /*!< Set PB13 function to USCI0_DAT0 */ +#define SET_USCI0_DAT0_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_DAT0_PE3_Msk)) | USCI0_DAT0_PE3 /*!< Set PE3 function to USCI0_DAT0 */ +#define SET_USCI0_DAT0_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_DAT0_PA10_Msk)) | USCI0_DAT0_PA10 /*!< Set PA10 function to USCI0_DAT0 */ +#define SET_USCI0_DAT0_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_DAT0_PD1_Msk)) | USCI0_DAT0_PD1 /*!< Set PD1 function to USCI0_DAT0 */ +#define SET_USCI0_DAT1_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_DAT1_PA9_Msk)) | USCI0_DAT1_PA9 /*!< Set PA9 function to USCI0_DAT1 */ +#define SET_USCI0_DAT1_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_DAT1_PE4_Msk)) | USCI0_DAT1_PE4 /*!< Set PE4 function to USCI0_DAT1 */ +#define SET_USCI0_DAT1_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_DAT1_PB14_Msk)) | USCI0_DAT1_PB14 /*!< Set PB14 function to USCI0_DAT1 */ +#define SET_USCI0_DAT1_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_DAT1_PD2_Msk)) | USCI0_DAT1_PD2 /*!< Set PD2 function to USCI0_DAT1 */ +#define SET_USCI1_CLK_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_CLK_PE12_Msk)) | USCI1_CLK_PE12 /*!< Set PE12 function to USCI1_CLK */ +#define SET_USCI1_CLK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_CLK_PB1_Msk)) | USCI1_CLK_PB1 /*!< Set PB1 function to USCI1_CLK */ +#define SET_USCI1_CLK_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_CLK_PD7_Msk)) | USCI1_CLK_PD7 /*!< Set PD7 function to USCI1_CLK */ +#define SET_USCI1_CLK_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI1_CLK_PB8_Msk)) | USCI1_CLK_PB8 /*!< Set PB8 function to USCI1_CLK */ +#define SET_USCI1_CTL0_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_CTL0_PE9_Msk)) | USCI1_CTL0_PE9 /*!< Set PE9 function to USCI1_CTL0 */ +#define SET_USCI1_CTL0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_CTL0_PB5_Msk)) | USCI1_CTL0_PB5 /*!< Set PB5 function to USCI1_CTL0 */ +#define SET_USCI1_CTL0_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_CTL0_PD3_Msk)) | USCI1_CTL0_PD3 /*!< Set PD3 function to USCI1_CTL0 */ +#define SET_USCI1_CTL0_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI1_CTL0_PB10_Msk)) | USCI1_CTL0_PB10 /*!< Set PB10 function to USCI1_CTL0 */ +#define SET_USCI1_CTL1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_CTL1_PB4_Msk)) | USCI1_CTL1_PB4 /*!< Set PB4 function to USCI1_CTL1 */ +#define SET_USCI1_CTL1_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_CTL1_PD4_Msk)) | USCI1_CTL1_PD4 /*!< Set PD4 function to USCI1_CTL1 */ +#define SET_USCI1_CTL1_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_CTL1_PE8_Msk)) | USCI1_CTL1_PE8 /*!< Set PE8 function to USCI1_CTL1 */ +#define SET_USCI1_CTL1_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI1_CTL1_PB9_Msk)) | USCI1_CTL1_PB9 /*!< Set PB9 function to USCI1_CTL1 */ +#define SET_USCI1_DAT0_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT0_PB7_Msk)) | USCI1_DAT0_PB7 /*!< Set PB7 function to USCI1_DAT0 */ +#define SET_USCI1_DAT0_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_DAT0_PE10_Msk)) | USCI1_DAT0_PE10 /*!< Set PE10 function to USCI1_DAT0 */ +#define SET_USCI1_DAT0_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT0_PB2_Msk)) | USCI1_DAT0_PB2 /*!< Set PB2 function to USCI1_DAT0 */ +#define SET_USCI1_DAT0_PD5() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_DAT0_PD5_Msk)) | USCI1_DAT0_PD5 /*!< Set PD5 function to USCI1_DAT0 */ +#define SET_USCI1_DAT1_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_DAT1_PD6_Msk)) | USCI1_DAT1_PD6 /*!< Set PD6 function to USCI1_DAT1 */ +#define SET_USCI1_DAT1_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT1_PB6_Msk)) | USCI1_DAT1_PB6 /*!< Set PB6 function to USCI1_DAT1 */ +#define SET_USCI1_DAT1_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_DAT1_PE11_Msk)) | USCI1_DAT1_PE11 /*!< Set PE11 function to USCI1_DAT1 */ +#define SET_USCI1_DAT1_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT1_PB3_Msk)) | USCI1_DAT1_PB3 /*!< Set PB3 function to USCI1_DAT1 */ +#define SET_X32_IN_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~X32_IN_PF5_Msk)) | X32_IN_PF5 /*!< Set PF5 function to X32_IN */ +#define SET_X32_OUT_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~X32_OUT_PF4_Msk)) | X32_OUT_PF4 /*!< Set PF4 function to X32_OUT */ +#define SET_XT1_IN_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~XT1_IN_PF3_Msk)) | XT1_IN_PF3 /*!< Set PF3 function to XT1_IN */ +#define SET_XT1_OUT_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~XT1_OUT_PF2_Msk)) | XT1_OUT_PF2 /*!< Set PF2 function to XT1_OUT */ + + +/** + * @brief Clear Brown-out detector interrupt flag + * @param None + * @return None + * @details This macro clear Brown-out detector interrupt flag. + */ +#define SYS_CLEAR_BOD_INT_FLAG() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL |= SYS_BODCTL_BODIF_Msk; \ + }while(0) + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This macro disable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_DISABLE_BOD() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk; \ + }while(0) + +/** + * @brief Enable Brown-out detector function + * @param None + * @return None + * @details This macro enable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_ENABLE_BOD() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL |= SYS_BODCTL_BODEN_Msk; \ + }while(0) + +/** + * @brief Get Brown-out detector interrupt flag + * @param None + * @retval 0 Brown-out detect interrupt flag is not set. + * @retval >=1 Brown-out detect interrupt flag is set. + * @details This macro get Brown-out detector interrupt flag. + */ +#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk) + +/** + * @brief Get Brown-out detector status + * @param None + * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled. + * @retval >=1 System voltage is lower than BOD threshold voltage setting. + * @details This macro get Brown-out detector output status. + * If the BOD function is disabled, this function always return 0. + */ +#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) + +/** + * @brief Enable Brown-out detector interrupt function + * @param None + * @return None + * @details This macro enable Brown-out detector interrupt function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_DISABLE_BOD_RST() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk; \ + }while(0) + +/** + * @brief Enable Brown-out detector reset function + * @param None + * @return None + * @details This macro enable Brown-out detect reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_ENABLE_BOD_RST() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk; \ + }while(0) + +/** + * @brief Set Brown-out detector voltage level + * @param[in] u32Level is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_1_6V + * - \ref SYS_BODCTL_BODVL_1_8V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_2_2V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_6V + * - \ref SYS_BODCTL_BODVL_2_8V + * - \ref SYS_BODCTL_BODVL_3_0V + * @return None + * @details This macro set Brown-out detector voltage level. + * The write-protection function should be disabled before using this macro. + */ +#define SYS_SET_BOD_LEVEL(u32Level) \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level); \ + }while(0) + +/** + * @brief Get reset source is from Brown-out detector reset + * @param None + * @retval 0 Previous reset source is not from Brown-out detector reset + * @retval >=1 Previous reset source is from Brown-out detector reset + * @details This macro get previous reset source is from Brown-out detect reset or not. + */ +#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk) + +/** + * @brief Get reset source is from CPU reset + * @param None + * @retval 0 Previous reset source is not from CPU reset + * @retval >=1 Previous reset source is from CPU reset + * @details This macro get previous reset source is from CPU reset. + */ +#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk) + +/** + * @brief Get reset source is from LVR Reset + * @param None + * @retval 0 Previous reset source is not from Low-Voltage-Reset + * @retval >=1 Previous reset source is from Low-Voltage-Reset + * @details This macro get previous reset source is from Low-Voltage-Reset. + */ +#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk) + +/** + * @brief Get reset source is from Power-on Reset + * @param None + * @retval 0 Previous reset source is not from Power-on Reset + * @retval >=1 Previous reset source is from Power-on Reset + * @details This macro get previous reset source is from Power-on Reset. + */ +#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk) + +/** + * @brief Get reset source is from reset pin reset + * @param None + * @retval 0 Previous reset source is not from reset pin reset + * @retval >=1 Previous reset source is from reset pin reset + * @details This macro get previous reset source is from reset pin reset. + */ +#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk) + +/** + * @brief Get reset source is from system reset + * @param None + * @retval 0 Previous reset source is not from system reset + * @retval >=1 Previous reset source is from system reset + * @details This macro get previous reset source is from system reset. + */ +#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk) + +/** + * @brief Get reset source is from window watch dog reset + * @param None + * @retval 0 Previous reset source is not from window watch dog reset + * @retval >=1 Previous reset source is from window watch dog reset + * @details This macro get previous reset source is from window watch dog reset. + */ +#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk) + +/** + * @brief Disable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro disable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_DISABLE_LVR() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk; \ + }while(0) + +/** + * @brief Enable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro enable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_ENABLE_LVR() \ + do{ \ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ + SYS->BODCTL |= SYS_BODCTL_LVREN_Msk; \ + }while(0) + +/** + * @brief Disable Power-on Reset function + * @param None + * @return None + * @details This macro disable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_DISABLE_POR() (SYS->PORCTL0 = 0x5AA5) + +/** + * @brief Enable Power-on Reset function + * @param None + * @return None + * @details This macro enable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_ENABLE_POR() (SYS->PORCTL0 = 0) + +/** + * @brief Clear reset source flag + * @param[in] u32RstSrc is reset source. Including : + * - \ref SYS_RSTSTS_PORF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_SYSRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_CPULKRF_Msk + * @return None + * @details This macro clear reset source flag. + */ +#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) ) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SYS_UnlockReg(void); +__STATIC_INLINE void SYS_LockReg(void); + + +/** + * @brief Disable register write-protection function + * @param None + * @return None + * @details This function disable register write-protection function. + * To unlock the protected register to allow write access. + */ +__STATIC_INLINE void SYS_UnlockReg(void) +{ + do + { + SYS->REGLCTL = 0x59UL; + SYS->REGLCTL = 0x16UL; + SYS->REGLCTL = 0x88UL; + } + while(SYS->REGLCTL == 0UL); +} + +/** + * @brief Enable register write-protection function + * @param None + * @return None + * @details This function is used to enable register write-protection function. + * To lock the protected register to forbid write access. + */ +__STATIC_INLINE void SYS_LockReg(void) +{ + SYS->REGLCTL = 0UL; +} + + +void SYS_ClearResetSrc(uint32_t u32Src); +uint32_t SYS_GetBODStatus(void); +uint32_t SYS_GetResetSrc(void); +uint32_t SYS_IsRegLocked(void); +uint32_t SYS_ReadPDID(void); +void SYS_ResetChip(void); +void SYS_ResetCPU(void); +void SYS_ResetModule(uint32_t u32ModuleIndex); +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel); +void SYS_DisableBOD(void); +void SYS_SetPowerLevel(uint32_t u32PowerLevel); +uint32_t SYS_SetPowerRegulator(uint32_t u32PowerRegulator); +void SYS_SetSSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode); +void SYS_SetPSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode); +void SYS_SetVRef(uint32_t u32VRefCTL); + + +/**@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SYS_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYS_H__ */ + + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_tamper.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_tamper.h new file mode 100644 index 0000000000..77ded546c8 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_tamper.h @@ -0,0 +1,466 @@ +/**************************************************************************//** + * @file tamper.h + * @version V3.00 + * @brief M2354 series TAMPER driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TAMPER_H__ +#define __TAMPER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TAMPER_Driver Tamper Driver + @{ +*/ + +/** @addtogroup TAMPER_EXPORTED_CONSTANTS Tamper Exported Constants + @{ +*/ + +#define TAMPER_TAMPER0_SELECT (0x1UL << 0) /*!< Select Tamper 0 */ +#define TAMPER_TAMPER1_SELECT (0x1UL << 1) /*!< Select Tamper 1 */ +#define TAMPER_TAMPER2_SELECT (0x1UL << 2) /*!< Select Tamper 2 */ +#define TAMPER_TAMPER3_SELECT (0x1UL << 3) /*!< Select Tamper 3 */ +#define TAMPER_TAMPER4_SELECT (0x1UL << 4) /*!< Select Tamper 4 */ +#define TAMPER_TAMPER5_SELECT (0x1UL << 5) /*!< Select Tamper 5 */ +#define TAMPER_MAX_TAMPER_PIN_NUM 6UL /*!< Tamper Pin number */ + +#define TAMPER_TAMPER_HIGH_LEVEL_DETECT 1UL /*!< Tamper pin detect voltage level is high */ +#define TAMPER_TAMPER_LOW_LEVEL_DETECT 0UL /*!< Tamper pin detect voltage level is low */ + +#define TAMPER_TAMPER_DEBOUNCE_ENABLE 1UL /*!< Enable tamper pin de-bounce function */ +#define TAMPER_TAMPER_DEBOUNCE_DISABLE 0UL /*!< Disable tamper pin de-bounce function */ + +#define TAMPER_PAIR0_SELECT (0x1UL << 0) /*!< Select Pair 0 */ +#define TAMPER_PAIR1_SELECT (0x1UL << 1) /*!< Select Pair 1 */ +#define TAMPER_PAIR2_SELECT (0x1UL << 2) /*!< Select Pair 2 */ +#define TAMPER_MAX_PAIR_NUM 3UL /*!< Pair number */ + +#define TAMPER_2POW6_CLK (0x0UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 RTC clock cycles */ +#define TAMPER_2POW7_CLK (0x1UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 2 RTC clock cycles */ +#define TAMPER_2POW8_CLK (0x2UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 4 RTC clock cycles */ +#define TAMPER_2POW9_CLK (0x3UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 6 RTC clock cycles */ +#define TAMPER_2POW10_CLK (0x4UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 8 RTC clock cycles */ +#define TAMPER_2POW11_CLK (0x5UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 10 RTC clock cycles */ +#define TAMPER_2POW12_CLK (0x6UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 12 RTC clock cycles */ +#define TAMPER_2POW13_CLK (0x7UL << TAMPER_TIOCTL_DYNRATE_Pos) /*!< 64 x 14 RTC clock cycles */ + +#define TAMPER_ACTS_2POW10_CLK (0x0UL << 5) /*!< 1024 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW11_CLK (0x1UL << 5) /*!< 1024 x 2 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW12_CLK (0x2UL << 5) /*!< 1024 x 4 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW13_CLK (0x3UL << 5) /*!< 1024 x 6 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW14_CLK (0x4UL << 5) /*!< 1024 x 8 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW15_CLK (0x5UL << 5) /*!< 1024 x 16 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW16_CLK (0x6UL << 5) /*!< 1024 x 32 LIRC32K clock cycles */ +#define TAMPER_ACTS_2POW17_CLK (0x7UL << 5) /*!< 1024 x 64 LIRC32K clock cycles */ + +#define TAMPER_REF_RANDOM_PATTERN 0x0UL /*!< The new reference pattern is generated by random number generator when the reference pattern run out */ +#define TAMPER_REF_SEED 0x1UL /*!< The new reference pattern is repeated from SEED (TAMPER_SEED[31:0]) when the reference pattern run out */ + +#define TAMPER_VG_192M_SAMPLE 0x0UL /*!< Select voltage glitch 192M sampleing rate */ + +/**@}*/ /* end of group TAMPER_EXPORTED_CONSTANTS */ + + +/** @addtogroup TAMPER_EXPORTED_FUNCTIONS Tamper Exported Functions + @{ +*/ + +/** + * @brief Reset Tamper Coreblock + * + * @param None + * + * @return None + * + * @details To set TAMPER INIT control register to reset the tamper coreblock. + * + */ +#define TAMPER_CORE_RESET() ((uint32_t)(TAMPER->INIT = 0x55AA)) + +/** + * @brief Release Tamper Coreblock + * + * @param None + * + * @return None + * + * @details To set TAMPER INIT control register to release the tamper coreblock. + * + */ +#define TAMPER_CORE_RELEASE() ((uint32_t)(TAMPER->INIT = 0x5500)) + +/** + * @brief Get the Voltage Regulator Power Ready Status + * + * @param None + * + * @retval 0 The power status of voltage regulator is not ready. + * @retval 1 The power status of voltage regulator is ready. + * + * @details This macro will return the power status of voltage regulator. + * + */ +#define TAMPER_TLDO_IS_READY() (TAMPER->INIT & TAMPER_INIT_TLDORDY_Msk ? 1:0) + +/** + * @brief Enable LXT Clock Detection + * + * @param None + * + * @return None + * + * @details To set TAMPER FUNEN control register to enable LXT clock detection. + * + */ +#define TAMPER_ENABLE_LXTDET() ((uint32_t)(TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | 0x44)) + +/** + * @brief Disable LXT Clock Detection + * + * @param None + * + * @return None + * + * @details To set TAMPER FUNEN control register to disable LXT clock detection. + * + */ +#define TAMPER_DISABLE_LXTDET() ((uint32_t)(TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | 0x40)) + +/** + * @brief Tamper I/O TAMPER Block Detection Selection + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref TAMPER_TAMPER0_SELECT + * - \ref TAMPER_TAMPER1_SELECT + * - \ref TAMPER_TAMPER2_SELECT + * - \ref TAMPER_TAMPER3_SELECT + * - \ref TAMPER_TAMPER4_SELECT + * - \ref TAMPER_TAMPER5_SELECT + * + * @return None + * + * @details To set TAMPER FUNEN control register to select tamper I/O 0~5 and its function is detected through TAMPER block. + * + */ +__STATIC_INLINE void TAMPER_IOSEL_TAMPER(uint32_t u32TamperSelect) +{ + uint32_t i; + + for(i = 0UL; i < (uint32_t)TAMPER_MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1UL << i)) + { + TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | (0x94 + i * 0x10UL); + } + } +} + +/** + * @brief Tamper I/O RTC Block Detection Selection + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref TAMPER_TAMPER0_SELECT + * - \ref TAMPER_TAMPER1_SELECT + * - \ref TAMPER_TAMPER2_SELECT + * - \ref TAMPER_TAMPER3_SELECT + * - \ref TAMPER_TAMPER4_SELECT + * - \ref TAMPER_TAMPER5_SELECT + * + * @return None + * + * @details To set TAMPER FUNEN control register to select tamper I/O 0~5 and its function is detected through RTC block. + * + */ +__STATIC_INLINE void TAMPER_IOSEL_RTC(uint32_t u32TamperSelect) +{ + uint32_t i; + + for(i = 0UL; i < (uint32_t)TAMPER_MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1UL << i)) + { + TAMPER->FUNEN = (TAMPER->FUNEN & ~0xFFUL) | (0x90 + i * 0x10UL); + } + } +} + +/** + * @brief Enable HIRC48M + * + * @param None + * + * @return None + * + * @details To set TAMPER FUNEN control register to enable HIRC48M. + * + */ +#define TAMPER_ENABLE_HIRC48M() ((uint32_t)(TAMPER->FUNEN &= (~TAMPER_FUNEN_HIRC48MEN_Msk))) + +/** + * @brief Disable HIRC48M + * + * @param None + * + * @return None + * + * @details To set TAMPER FUNEN control register to disable HIRC48M. + * + */ +#define TAMPER_DISABLE_HIRC48M() ((uint32_t)(TAMPER->FUNEN = (TAMPER->FUNEN & (~TAMPER_FUNEN_HIRC48MEN_Msk)) | (0x5A << TAMPER_FUNEN_HIRC48MEN_Pos))) + +/** + * @brief Voltage Glitch Sampling Rate Selection + * + * @param[in] u32VGSampleRate Voltage Glitch sampling rate select. Possible option is + * - \ref TAMPER_VG_192M_SAMPLE + * + * @return None + * + * @details To set TAMPER FUNEN control register to enable voltage glitch channel 0~3 to select voltage glitch sampling rate. + * + */ +__STATIC_INLINE void TAMPER_VG_SAMPLE_SEL(uint32_t u32VGSampleRate) +{ + TAMPER->FUNEN &= ~0xF000000UL; + + if(u32VGSampleRate == TAMPER_VG_192M_SAMPLE) + { + TAMPER->FUNEN |= TAMPER_FUNEN_VGCHEN0_Msk | TAMPER_FUNEN_VGCHEN1_Msk | TAMPER_FUNEN_VGCHEN2_Msk | TAMPER_FUNEN_VGCHEN3_Msk; + } +} + +/** + * @brief Enable to Trigger Key Store + * + * @param None + * + * @return None + * + * @details Set KSTRIGEN bit of TAMPER TRIEN control register to trigger Key Store when Tamper event is detected. + * + */ +#define TAMPER_ENABLE_KS_TRIG() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_KSTRIGEN_Msk)) + +/** + * @brief Disable to Trigger Key Store + * + * @param None + * + * @return None + * + * @details Clear KSTRIGEN bit of TAMPER TRIEN control register to not trigger Key Store when Tamper event is detected. + * + */ +#define TAMPER_DISABLE_KS_TRIG() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_KSTRIGEN_Msk))) + +/** + * @brief Enable Wake-up Function + * + * @param None + * + * @return None + * + * @details Set WAKEUPEN bit of TAMPER TRIEN control register to wake-up the system when Tamper event is detected. + * + */ +#define TAMPER_ENABLE_WAKEUP() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_WAKEUPEN_Msk)) + +/** + * @brief Disable Wake-up Function + * + * @param None + * + * @return None + * + * @details Clear WAKEUPEN bit of TAMPER TRIEN control register to not wake-up the system when Tamper event is detected. + * + */ +#define TAMPER_DISABLE_WAKEUP() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_WAKEUPEN_Msk))) + +/** + * @brief Enable to Clear Crypto Function + * + * @param None + * + * @return None + * + * @details Set CRYPTOEN bit of TAMPER TRIEN control register to reset Crypto when Tamper event is detected. + * + */ +#define TAMPER_ENABLE_CRYPTO() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_CRYPTOEN_Msk)) + +/** + * @brief Disable to Clear Crypto Function + * + * @param None + * + * @return None + * + * @details Clear CRYPTOEN bit of TAMPER TRIEN control register to not reset Crypto when Tamper event is detected. + * + */ +#define TAMPER_DISABLE_CRYPTO() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_CRYPTOEN_Msk))) + +/** + * @brief Enable to Trigger Chip Reset + * + * @param None + * + * @return None + * + * @details Set CHIPRSTEN bit of TAMPER TRIEN control register to reset the system when Tamper event is detected. + * + */ +#define TAMPER_ENABLE_CHIPRST() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_CHIPRSTEN_Msk)) + +/** + * @brief Disable to Trigger Chip Reset + * + * @param None + * + * @return None + * + * @details Clear CHIPRSTEN bit of TAMPER TRIEN control register to not reset the system when Tamper event is detected. + * + */ +#define TAMPER_DISABLE_CHIPRST() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_CHIPRSTEN_Msk))) + +/** + * @brief Enable to Clear RTC Spare Register + * + * @param None + * + * @return None + * + * @details Set RTCSPCLREN bit of TAMPER TRIEN control register to reset RTC spare register when Tamper event is detected. + * + */ +#define TAMPER_ENABLE_RTCSPCLR() ((uint32_t)(TAMPER->TRIEN |= TAMPER_TRIEN_RTCSPCLREN_Msk)) + +/** + * @brief Disable to Clear RTC Spare Register + * + * @param None + * + * @return None + * + * @details Clear RTCSPCLREN bit of TAMPER TRIEN control register to not reset RTC spare register when Tamper event is detected. + * + */ +#define TAMPER_DISABLE_RTCSPCLR() ((uint32_t)(TAMPER->TRIEN &= (~TAMPER_TRIEN_RTCSPCLREN_Msk))) + +/** + * @brief Get Tamper Interrupt Flag + * + * @param None + * + * @retval 0 Tamper event Interrupt did not occur + * @retval 1 Tamper event Interrupt occurred + * + * @details This macro indicates Tamper event intertupt occurred or not. + * + */ +#define TAMPER_GET_INT_FLAG() ((TAMPER->INTSTS & (0xAA7FAFFF))? 1:0) + +/** + * @brief Clear Tamper Interrupt Status + * + * @param[in] u32TamperFlag Tamper event interrupt flag. It consists of: + * - \ref TAMPER_INTSTS_TAMP0IF_Msk + * - \ref TAMPER_INTSTS_TAMP1IF_Msk + * - \ref TAMPER_INTSTS_TAMP2IF_Msk + * - \ref TAMPER_INTSTS_TAMP3IF_Msk + * - \ref TAMPER_INTSTS_TAMP4IF_Msk + * - \ref TAMPER_INTSTS_TAMP5IF_Msk + * - \ref TAMPER_INTSTS_CLKFAILIF_Msk + * - \ref TAMPER_INTSTS_CLKSTOPIF_Msk + * - \ref TAMPER_INTSTS_OVPOUTIF_Msk + * - \ref TAMPER_INTSTS_VGPEVIF_Msk + * - \ref TAMPER_INTSTS_VGNEVIF_Msk + * - \ref TAMPER_INTSTS_ACTSEIF_Msk + * - \ref TAMPER_INTSTS_ACTST5IF_Msk + * - \ref TAMPER_INTSTS_ACTST25IF_Msk + * - \ref TAMPER_INTSTS_BODIF_Msk + * - \ref TAMPER_INTSTS_ACTST1IF_Msk + * - \ref TAMPER_INTSTS_ACTST3IF_Msk + * - \ref TAMPER_INTSTS_ACTST21IF_Msk + * - \ref TAMPER_INTSTS_ACTST23IF_Msk + * + * @return None + * + * @details This macro is used to clear Tamper event flag. + * + */ +#define TAMPER_CLR_INT_STATUS(u32TamperFlag) (TAMPER->INTSTS = (u32TamperFlag)) + +/** + * @brief Get Tamper Interrupt Status + * + * @param None + * + * @retval TAMPER_INTSTS_TAMP0IF_Msk + * @retval TAMPER_INTSTS_TAMP1IF_Msk + * @retval TAMPER_INTSTS_TAMP2IF_Msk + * @retval TAMPER_INTSTS_TAMP3IF_Msk + * @retval TAMPER_INTSTS_TAMP4IF_Msk + * @retval TAMPER_INTSTS_TAMP5IF_Msk + * @retval TAMPER_INTSTS_CLKFAILIF_Msk + * @retval TAMPER_INTSTS_CLKSTOPIF_Msk + * @retval TAMPER_INTSTS_OVPOUTIF_Msk + * @retval TAMPER_INTSTS_VGPEVIF_Msk + * @retval TAMPER_INTSTS_VGNEVIF_Msk + * @retval TAMPER_INTSTS_ACTSEFIF_Msk + * @retval TAMPER_INTSTS_ACTST5IF_Msk + * @retval TAMPER_INTSTS_ACTST25IF_Msk + * @retval TAMPER_INTSTS_RTCLVRIF_Msk + * @retval TAMPER_INTSTS_RIOTRIGIF_Msk + * @retval TAMPER_INTSTS_RCLKTRIGIF_Msk + * @retval TAMPER_INTSTS_BODIF_Msk + * @retval TAMPER_INTSTS_ACTST1IF_Msk + * @retval TAMPER_INTSTS_ACTST3IF_Msk + * @retval TAMPER_INTSTS_ACTST21IF_Msk + * @retval TAMPER_INTSTS_ACTST23IF_Msk + * + * @details This macro indicates Tamper event status. + * + */ +#define TAMPER_GET_INT_STATUS() ((TAMPER->INTSTS & (0xAA7FAFFF))) + +void TAMPER_EnableInt(uint32_t u32IntFlagMask); +void TAMPER_DisableInt(uint32_t u32IntFlagMask); +void TAMPER_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn); +void TAMPER_StaticTamperDisable(uint32_t u32TamperSelect); +void TAMPER_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source); +void TAMPER_DynamicTamperDisable(uint32_t u32PairSel); +void TAMPER_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed); +void TAMPER_ActiveShieldDynamicTamperEnable(uint32_t u32PairSel1, uint32_t u32Pair1Source1, uint32_t u32PairSel2, uint32_t u32Pair1Source2); +void TAMPER_ActiveShieldDynamicTamperDisable(uint32_t u32PairSel1, uint32_t u32PairSe2); +void TAMPER_ActiveShieldDynamicTamperConfig(uint32_t u32ChangeRate1, uint32_t u32SeedReload1, uint32_t u32RefPattern1, uint32_t u32Seed, + uint32_t u32ChangeRate2, uint32_t u32SeedReload2, uint32_t u32RefPattern2, uint32_t u32Seed2); + + +/**@}*/ /* end of group TAMPER_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group TAMPER_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TAMPER_H__ */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_timer.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_timer.h new file mode 100644 index 0000000000..1533879413 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_timer.h @@ -0,0 +1,543 @@ +/**************************************************************************//** + * @file timer.h + * @version V3.00 + * @brief Timer Controller(Timer) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode \hideinitializer */ +#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode \hideinitializer */ +#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode \hideinitializer */ +#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx pin \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx_EXT pin \hideinitializer */ + +#define TIMER_COUNTER_EVENT_FALLING (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection \hideinitializer */ +#define TIMER_COUNTER_EVENT_RISING (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection \hideinitializer */ +#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value \hideinitializer */ +#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter \hideinitializer */ + +#define TIMER_CAPTURE_EVENT_FALLING (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_FALLING_RISING (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING_FALLING (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD (6UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at falling edge, follows are at at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD (7UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at rising edge, follows are at at falling edge \hideinitializer */ + +#define TIMER_CAPTURE_SOURCE_FROM_PIN (0UL << TIMER_CTL_CAPSRC_Pos) /*!< The capture source is from TMx_EXT pin \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_FROM_INTERNAL (1UL << TIMER_CTL_CAPSRC_Pos) /*!< The capture source is from internal ACMPx signal or clock source \hideinitializer */ + +#define TIMER_CAPTURE_SOURCE_DIV_1 (0UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 1 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_2 (1UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 2 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_4 (2UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 4 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_8 (3UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 8 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_16 (4UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 16 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_32 (5UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 32 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_64 (6UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 64 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_128 (7UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 128 \hideinitializer */ +#define TIMER_CAPTURE_SOURCE_DIV_256 (8UL << TIMER_EXTCTL_CAPDIVSCL_Pos) /*!< Input capture source divide 256 \hideinitializer */ + +#define TIMER_INTER_CAPTURE_SOURCE_ACMP0 (0UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from internal ACMP0 output signal \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_ACMP1 (1UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from internal ACMP1 output signal \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_HXT (2UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from HXT \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_LXT (3UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from LXT \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_HIRC (4UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from HIRC \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_LIRC (5UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from LIRC \hideinitializer */ +#define TIMER_INTER_CAPTURE_SOURCE_MIRC (6UL << TIMER_EXTCTL_INTERCAPSEL_Pos) /*!< Capture source from MIRC. Only available on TIMER4 and TIMER5 \hideinitializer */ + +#define TIMER_TRGSRC_TIMEOUT_EVENT (0UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer time-out event \hideinitializer */ +#define TIMER_TRGSRC_CAPTURE_EVENT (1UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer capture event \hideinitializer */ +#define TIMER_TRG_TO_PWM (TIMER_TRGCTL_TRGPWM_Msk) /*!< Each timer event as EPWM and BPWM counter clock source. NOT supported on TIMER4 and TIMER5 \hideinitializer */ +#define TIMER_TRG_TO_EADC (TIMER_TRGCTL_TRGEADC_Msk) /*!< Each timer event to start ADC conversion \hideinitializer */ +#define TIMER_TRG_TO_DAC (TIMER_TRGCTL_TRGDAC_Msk) /*!< Each timer event to start DAC conversion. NOT supported on TIMER4 and TIMER5 \hideinitializer */ +#define TIMER_TRG_TO_PDMA (TIMER_TRGCTL_TRGPDMA_Msk) /*!< Each timer event to trigger PDMA transfer \hideinitializer */ + +/**@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */ + + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Set Timer Compared Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF. + * + * @return None + * + * @details This macro is used to set timer compared value to adjust timer time-out interval. + * @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n + * 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n + * But if timer is operating at other modes, the timer up counter will restart counting and start from 0. + * \hideinitializer + */ +#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value)) + +/** + * @brief Set Timer Prescale Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF. + * + * @return None + * + * @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n + * before it is fed into timer. + * \hideinitializer + */ +#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value)) + +/** + * @brief Check specify Timer Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Timer 24-bit up counter is inactive + * @retval 1 Timer 24-bit up counter is active + * + * @details This macro is used to check if specify Timer counter is inactive or active. + * \hideinitializer + */ +#define TIMER_IS_ACTIVE(timer) ((((timer)->CTL & TIMER_CTL_ACTSTS_Msk) == TIMER_CTL_ACTSTS_Msk)? 1 : 0) + +/** + * @brief Select Toggle-output Pin + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32ToutSel Toggle-output pin selection, valid values are: + * - \ref TIMER_TOUT_PIN_FROM_TMX + * - \ref TIMER_TOUT_PIN_FROM_TMX_EXT + * + * @return None + * + * @details This macro is used to select timer toggle-output pin is output on TMx or TMx_EXT pin. + * \hideinitializer + */ +#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel)) + +/** + * @brief Set Timer Operating Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32OpMode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * + * @return None + * \hideinitializer + */ +#define TIMER_SET_OPMODE(timer, u32OpMode) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_OPMODE_Msk) | (u32OpMode)) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer); +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer); +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer); + + +/** + * @brief Start Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to start Timer counting. + */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to stop/suspend Timer counting. + */ +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Enable Timer Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n + * counter event interrupt or capture trigger interrupt. + * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC. + */ +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Disable Timer Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to disable the timer interrupt wake-up function. + */ +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Start Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to start Timer capture function. + */ +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Stop Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to stop Timer capture function. + */ +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Disable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Enable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Disable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Enable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to enable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Disable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to disable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Enable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to enable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Disable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to disable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Get Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Timer time-out interrupt did not occur + * @retval 1 Timer time-out interrupt occurred + * + * @details This function indicates timer time-out interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer) +{ + return (((timer->INTSTS & TIMER_INTSTS_TIF_Msk) == TIMER_INTSTS_TIF_Msk)? 1UL : 0UL); +} + +/** + * @brief Clear Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function clears timer time-out interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TIF_Msk; +} + +/** + * @brief Get Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Timer capture interrupt did not occur + * @retval 1 Timer capture interrupt occurred + * + * @details This function indicates timer capture trigger interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer) +{ + return timer->EINTSTS; +} + +/** + * @brief Clear Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function clears timer capture trigger interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer) +{ + timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk; +} + +/** + * @brief Get Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Timer does not cause CPU wake-up + * @retval 1 Timer interrupt event cause CPU wake-up + * + * @details This function indicates timer interrupt event has waked up system or not. + */ +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer) +{ + return (((timer->INTSTS & TIMER_INTSTS_TWKF_Msk) == TIMER_INTSTS_TWKF_Msk)? 1UL : 0UL); +} + +/** + * @brief Clear Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function clears the timer wake-up system flag to 0. + */ +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TWKF_Msk; +} + +/** + * @brief Get Capture value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return 24-bit Capture Value + * + * @details This function reports the current 24-bit timer capture value. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer) +{ + return timer->CAP; +} + +/** + * @brief Get Counter value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return 24-bit Counter Value + * + * @details This function reports the current 24-bit timer counter value. + */ +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer) +{ + return timer->CNT; +} + +/** + * @brief Reset Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to reset current counter value and internal prescale counter value. + */ +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer) +{ + timer->CNT = 0UL; + while((timer->CNT & TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk) {} +} + + +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq); +void TIMER_Close(TIMER_T *timer); +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec); +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge); +void TIMER_DisableCapture(TIMER_T *timer); +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge); +void TIMER_DisableEventCounter(TIMER_T *timer); +uint32_t TIMER_GetModuleClock(TIMER_T *timer); +void TIMER_EnableFreqCounter(TIMER_T *timer, uint32_t u32DropCount, uint32_t u32Timeout, uint32_t u32EnableInt); +void TIMER_DisableFreqCounter(TIMER_T *timer); +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src); +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask); + +/**@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group TIMER_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_H__ */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_timer_pwm.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_timer_pwm.h new file mode 100644 index 0000000000..7229552db2 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_timer_pwm.h @@ -0,0 +1,879 @@ +/**************************************************************************//** + * @file timer.h + * @version V3.00 + * @brief Timer PWM Controller(Timer PWM) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_PWM_H__ +#define __TIMER_PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Channel Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CH0 (BIT0) /*!< Indicate PWMx_CH0 \hideinitializer */ +#define TPWM_CH1 (BIT1) /*!< Indicate PWMx_CH1 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_UP_COUNT (0UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up count type \hideinitializer */ +#define TPWM_DOWN_COUNT (1UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Down count type \hideinitializer */ +#define TPWM_UP_DOWN_COUNT (2UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up-Down count type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_AUTO_RELOAD_MODE (0UL) /*!< Auto-reload mode \hideinitializer */ +#define TPWM_ONE_SHOT_MODE (TIMER_PWMCTL_CNTMODE_Msk) /*!< One-shot mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_OUTPUT_TOGGLE (0UL) /*!< Timer PWM output toggle \hideinitializer */ +#define TPWM_OUTPUT_NOTHING (1UL) /*!< Timer PWM output nothing \hideinitializer */ +#define TPWM_OUTPUT_LOW (2UL) /*!< Timer PWM output low \hideinitializer */ +#define TPWM_OUTPUT_HIGH (3UL) /*!< Timer PWM output high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Trigger Event Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TRIGGER_EVENT_AT_ZERO_POINT (0UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger event while counter zero point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EVENT_AT_PERIOD_POINT (1UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger event while counter period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EVENT_AT_ZERO_OR_PERIOD_POINT (2UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger event while counter zero or period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EVENT_AT_COMPARE_UP_POINT (3UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger event while counter up count compare point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EVENT_AT_COMPARE_DOWN_POINT (4UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger event while counter down count compare point event occurred \hideinitializer */ +#define TPWM_TRIGGER_EVENT_AT_PERIOD_OR_COMPARE_UP_POINT (5UL << TIMER_PWMTRGCTL_TRGSEL_Pos) /*!< Timer PWM trigger event while counter period or up count compare point event occurred \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP0 (TIMER_PWMBRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP1 (TIMER_PWMBRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_BKPIN (TIMER_PWMBRKCTL_BRKPEEN_Msk) /*!< Brake pin as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_CSS (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_BOD (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_COR (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_RAM (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */ + +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP0 (TIMER_PWMBRKCTL_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP1 (TIMER_PWMBRKCTL_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_BKPIN (TIMER_PWMBRKCTL_BRKPLEN_Msk) /*!< Brake pin as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_COR (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */ + +#define TPWM_BRAKE_EDGE (TIMER_PWMSWBRK_BRKETRG_Msk) /*!< Edge-detect fault brake \hideinitializer */ +#define TPWM_BRAKE_LEVEL (TIMER_PWMSWBRK_BRKLTRG_Msk) /*!< Level-detect fault brake \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Load Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_LOAD_MODE_PERIOD (0UL) /*!< Timer PWM period load mode \hideinitializer */ +#define TPWM_LOAD_MODE_IMMEDIATE (TIMER_PWMCTL_IMMLDEN_Msk) /*!< Timer PWM immediately load mode \hideinitializer */ +#define TPWM_LOAD_MODE_CENTER (TIMER_PWMCTL_CTRLD_Msk) /*!< Timer PWM center load mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin De-bounce Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BKP_DBCLK_PCLK_DIV_1 (0UL) /*!< De-bounce clock is PCLK divide by 1 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_2 (1UL) /*!< De-bounce clock is PCLK divide by 2 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_4 (2UL) /*!< De-bounce clock is PCLK divide by 4 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_8 (3UL) /*!< De-bounce clock is PCLK divide by 8 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_16 (4UL) /*!< De-bounce clock is PCLK divide by 16 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_32 (5UL) /*!< De-bounce clock is PCLK divide by 32 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_64 (6UL) /*!< De-bounce clock is PCLK divide by 64 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_128 (7UL) /*!< De-bounce clock is PCLK divide by 128 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TM_BRAKE0 (0UL) /*!< Brake pin source comes from TM_BRAKE0 \hideinitializer */ +#define TPWM_TM_BRAKE1 (1UL) /*!< Brake pin source comes from TM_BRAKE1 \hideinitializer */ +#define TPWM_TM_BRAKE2 (2UL) /*!< Brake pin source comes from TM_BRAKE2 \hideinitializer */ +#define TPWM_TM_BRAKE3 (3UL) /*!< Brake pin source comes from TM_BRAKE3 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_CLKSRC_TMR_CLK (0UL) /*!< Timer PWM Clock source selects to TMR_CLK \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER0_INT (1UL) /*!< Timer PWM Clock source selects to TIMER0 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER1_INT (2UL) /*!< Timer PWM Clock source selects to TIMER1 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER2_INT (3UL) /*!< Timer PWM Clock source selects to TIMER2 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER3_INT (4UL) /*!< Timer PWM Clock source selects to TIMER3 interrupt event \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Synchronous Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_SYNC_DISABLE (0UL) /*!< Disable TIMER PWM synchronous function \hideinitializer */ +#define TPWM_CNTR_SYNC_START_BY_TIMER0 ((0<PWMCTL) & TMR45_BASE) == TMR45_BASE) { \ + (timer)->CTL |= TIMER_CTL_FUNCSEL_Msk; \ + while(((timer)->CTL & TIMER_CTL_FUNCSEL_Msk) == 0) {} \ + } else { \ + (timer)->ALTCTL = TIMER_ALTCTL_FUNCSEL_Msk; \ + while(((timer)->ALTCTL & TIMER_ALTCTL_FUNCSEL_Msk) == 0) {} \ + } \ + }while(0) + +/** + * @brief Disable PWM Counter Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available. + * @note All registers about PWM counter function will be cleared to 0 after executing this macro. + * \hideinitializer + */ +#define TPWM_DISABLE_PWM_MODE(timer) \ + do{ \ + if(((uint32_t)&((timer)->PWMCTL) & TMR45_BASE) == TMR45_BASE) { \ + (timer)->CTL &= ~TIMER_CTL_FUNCSEL_Msk; \ + while(((timer)->CTL & TIMER_CTL_FUNCSEL_Msk) == TIMER_CTL_FUNCSEL_Msk) {} \ + } else { \ + (timer)->ALTCTL &= ~TIMER_ALTCTL_FUNCSEL_Msk; \ + while(((timer)->ALTCTL & TIMER_ALTCTL_FUNCSEL_Msk) == TIMER_ALTCTL_FUNCSEL_Msk) {} \ + } \ + }while(0) + + +/** + * @brief Enable Independent Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable independent mode of TIMER PWM module and complementary mode will be disabled. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_ENABLE_INDEPENDENT_MODE(timer) ((timer)->PWMCTL &= ~(1ul << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Enable Complementary Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable complementary mode of Timer PWM module and independent mode will be disabled. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_ENABLE_COMPLEMENTARY_MODE(timer) ((timer)->PWMCTL |= (1 << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Set Counter Type + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] type Timer PWM count type, could be one of the following type + * - \ref TPWM_UP_COUNT + * - \ref TPWM_DOWN_COUNT + * - \ref TPWM_UP_DOWN_COUNT + * + * @return None + * + * @details This macro is used to set Timer PWM counter type. + * @note NOT available on TIMER4 and TIMER5. Both TIMER4 and TIMER5 are only support count up. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_TYPE(timer, type) ((timer)->PWMCTL = ((timer)->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (type)) + +/** + * @brief Start PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to enable PWM generator and start counter counting. + * \hideinitializer + */ +#define TPWM_START_COUNTER(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk) + +/** + * @brief Stop PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to stop PWM counter after current period is completed. + * \hideinitializer + */ +#define TPWM_STOP_COUNTER(timer) ((timer)->PWMPERIOD = 0x0) + +/** + * @brief Set Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @param[in] prescaler Clock prescaler of specified channel. + * Valid values are between 0x0~0xFFF for TIMER0, TIMER1, TIMER2, TIMER3, and + * valid values are between 0x0~0xFF for TIMER4 and TIMER5. + * + * @return None + * + * @details This macro is used to set the prescaler of specified TIMER PWM. + * @note If prescaler is 0, then there is no scaling in counter clock source. + * \hideinitializer + */ +#define TPWM_SET_PRESCALER(timer, prescaler) ((timer)->PWMCLKPSC = (prescaler)) + +/** + * @brief Get Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0]) + * + * @details Get the prescaler setting, the target counter clock divider is (CLKPSC + 1). + * \hideinitializer + */ +#define TPWM_GET_PRESCALER(timer) ((timer)->PWMCLKPSC) + +/** + * @brief Set Couner Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @param[in] period Period of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_PERIOD(timer, period) ((timer)->PWMPERIOD = (period)) + +/** + * @brief Get Couner Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0]) + * + * @details This macro is used to get the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_PERIOD(timer) ((timer)->PWMPERIOD) + +/** + * @brief Set Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @param[in] cmp Comparator of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_CMPDAT(timer, cmp) ((timer)->PWMCMPDAT = (cmp)) + +/** + * @brief Get Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0]) + * + * @details This macro is used to get the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_CMPDAT(timer) ((timer)->PWMCMPDAT) + +/** + * @brief Clear Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to clear counter of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_CLEAR_COUNTER(timer) ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk) + +/** + * @brief Software Trigger Brake Event + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] type Type of brake trigger. Valid values are: + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This macro is used to trigger brake event by writing PWMSWBRK register. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_SW_TRIGGER_BRAKE(timer, type) ((timer)->PWMSWBRK = (type)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @param[in] ch Enable specified channel output function. Valid values are: + * For TIMER0 ~ TIMER3, the valid value could be a combination of \ref TPWM_CH0 and \ref TPWM_CH1. + * For TIMER4, TIMER5, the valid value could be \ref TPWM_CH0 or \ref TPWM_CH1. + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * \hideinitializer + */ +#define TPWM_ENABLE_OUTPUT(timer, ch) \ + do{ \ + if(((uint32_t)&((timer)->PWMCTL) & TMR45_BASE) == TMR45_BASE) { \ + if((ch) == BIT0) \ + (timer)->PWMPOEN = BIT0; \ + else \ + (timer)->PWMPOEN = (BIT0 | BIT8); \ + } else { \ + (timer)->PWMPOEN = (ch); \ + } \ + }while(0) + +/** + * @brief Set Output Inverse + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @param[in] ch Set specified channel output is inversed or not. + * For TIMER0 ~ TIMER3, the valid value could be a combination of \ref TPWM_CH0 and \ref TPWM_CH1. + * But this parameter is no effect on TIMER4 and TIMER5. + * + * @return None + * + * @details This macro is used to enable output inverse of specified output pins. + * \hideinitializer + */ +#define TPWM_SET_OUTPUT_INVERSE(timer, ch) \ + do{ \ + if(((uint32_t)&((timer)->PWMCTL) & TMR45_BASE) == TMR45_BASE) { \ + (timer)->PWMPOLCTL = BIT0; \ + } else { \ + (timer)->PWMPOLCTL = (ch); \ + } \ + }while(0) + +/** + * @brief Enable Output Mask Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output mask function. Valid value could be a combination of \ref TPWM_CH0 and \ref TPWM_CH1. + * + * @param[in] level Output to high or low on specified mask channel. + * + * @return None + * + * @details This macro is used to enable output mask function of specified output pins. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_SET_MASK_OUTPUT(timer, ch, level) do {(timer)->PWMMSKEN = (ch); (timer)->PWMMSK = (level); }while(0) + +/** + * @brief Set Counter Synchronous Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] mode Synchronous mode. Possible options are: + * - \ref TPWM_CNTR_SYNC_DISABLE + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER2 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER2 + * + * @return None + * + * @details This macro is used to set counter synchronous mode of specified Timer PWM module. + * @note Only support all PWM counters are synchronous by TIMER0 PWM or TIMER0~1 PWM counter synchronous by TIMER0 PWM and + * TIMER2~3 PWM counter synchronous by TIMER2 PWM. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_SYNC_MODE(timer, mode) ((timer)->PWMSCTL = (mode)) + +/** + * @brief Trigger Counter Synchronous + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to trigger synchronous event by specified TIMER PWM. + * @note 1. This macro is only available for TIMER0 PWM and TIMER2 PWM. \n + * 2. STRGEN (PWMSTRG[0]) is write only and always read as 0. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_TRIGGER_COUNTER_SYNC(timer) ((timer)->PWMSTRG = TIMER_PWMSTRG_STRGEN_Msk) + +/** + * @brief Enable Timer PWM Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 or TIMER5. + * + * @return None + * + * @details This macro is used to enable the timer pwm interrupt wake-up function. + * @note Only available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_ENABLE_PWMINT_WAKEUP(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_WKEN_Msk) + +/** + * @brief Disable Timer PWM Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 or TIMER5. + * + * @return None + * + * @details This macro is used to disable the timer pwm interrupt wake-up function. + * @note Only available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_DISABLE_PWMINT_WAKEUP(timer) ((timer)->PWMCTL &= ~TIMER_PWMCTL_WKEN_Msk) + +/** + * @brief Enable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the zero event interrupt function. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_ENABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Disable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the zero event interrupt function. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_DISABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Get Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Zero event interrupt did not occur + * @retval 1 Zero event interrupt occurred + * + * @details This macro indicates zero event occurred or not. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_GET_ZERO_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_ZIF_Msk)? 1 : 0) + +/** + * @brief Clear Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears zero event interrupt flag. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_CLEAR_ZERO_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_ZIF_Msk) + +/** + * @brief Enable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to enable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Disable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to disable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Get Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Period event interrupt did not occur + * @retval 1 Period event interrupt occurred + * + * @details This macro indicates period event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_PERIOD_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0) + +/** + * @brief Clear Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro clears period event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_PERIOD_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk) + +/** + * @brief Enable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to enable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Disable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to disable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Get Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Compare up event interrupt did not occur + * @retval 1 Compare up event interrupt occurred + * + * @details This macro indicates compare up event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_UP_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro clears compare up event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk) + +/** + * @brief Enable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare down event interrupt function. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Disable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare down event interrupt function. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Get Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare down event interrupt did not occur + * @retval 1 Compare down event interrupt occurred + * + * @details This macro indicates compare down event occurred or not. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_GET_CMP_DOWN_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPDIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare down event interrupt flag. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_DOWN_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPDIF_Msk) + +/** + * @brief Get Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Timer PWM counter never counts to maximum value + * @retval 1 Timer PWM counter counts to maximum value, 0xFFFF + * + * @details This macro indicates Timer PWM counter has count to 0xFFFF or not. + * \hideinitializer + */ +#define TPWM_GET_REACH_MAX_CNT_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0) + +/** + * @brief Clear Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro clears reach maximum count status. + * \hideinitializer + */ +#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk) + +/** + * @brief Get Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @retval 0 Trigger ADC start conversion is not occur + * @retval 1 Specified counter compare event has trigger ADC start conversion + * + * @details This macro is used to indicate PWM counter compare event has triggered ADC start conversion. + * \hideinitializer + */ +#define TPWM_GET_TRG_ADC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0) + +/** + * @brief Clear Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This macro is used to clear PWM counter compare event trigger ADC status. + * \hideinitializer + */ +#define TPWM_CLEAR_TRG_ADC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk) + +/** + * @brief Get Trigger PDMA Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 ~ TIMER5. + * + * @retval 0 Trigger PDMA transfer data is not occur + * @retval 1 Specified counter compare event has trigger PDMA transfer data + * + * @details This macro is used to indicate PWM counter compare event has triggered PDMA start transfer data. + * @note Only available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_GET_TRG_PDMA_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_PDMATRGF_Msk)? 1 : 0) + +/** + * @brief Clear Trigger PDMA Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 ~ TIMER5. + * + * @return None + * + * @details This macro is used to clear PWM counter compare event trigger PDMA status. + * @note Only available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_CLEAR_TRG_PDMA_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_PDMATRGF_Msk) + +/** + * @brief Get PWM Interrupt Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 ~ TIMER5. + * + * @retval 0 PWM does not cause CPU wake-up + * @retval 1 PWM interrupt event cause CPU wake-up + * + * @details This function indicates PWM interrupt event has waked up system or not. + * @note Only available on TIMER4 and TIMER5. + */ +#define TPWM_GET_PWMINT_WAKEUP_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_WKF_Msk)? 1 : 0) + +/** + * @brief Clear PWM Interrupt Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 ~ TIMER5. + * + * @return None + * + * @details This macro is used to clear PWM interrupt wakeup status. + * @note Only available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_CLEAR_PWMINT_WAKEUP_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_WKF_Msk) + +/** + * @brief Set Brake Event at Brake Pin High or Low-to-High + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * @note The default brake pin detection is high level or from low to high. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_HIGH_DETECT(timer) ((timer)->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set Brake Event at Brake Pin Low or High-to-Low + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at low level or transfer from high to low. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_LOW_DETECT(timer) ((timer)->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set External Brake Pin Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] pin The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * @note NOT available on TIMER4 and TIMER5. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_SOURCE(timer, pin) ((timer)->PWMBNF = ((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | ((pin)<> 4ul)-2ul) + + +/** + * @brief Calculate UART baudrate mode2 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode2 divider + * + * @details This macro calculate UART baudrate mode2 divider. + */ +#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul) + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + */ +#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data)) + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module + * + * @return The oldest data byte in RX FIFO. + * + * @details This macro read Rx data register. + */ +#define UART_READ(uart) ((uart)->DAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not empty + * @retval >=1 Tx FIFO is empty + * + * @details This macro get Transmitter FIFO empty register value. + */ +#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not empty + * @retval >=1 Rx FIFO is empty + * + * @details This macro get Receiver FIFO empty register value. + */ +#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified uart port transmission is over. + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. + * It indicates if specified uart port transmission is over nor not. + */ +#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos) + + +/** + * @brief Wait specified uart port transmission is over + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro wait specified uart port transmission is over. + */ +#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)) + + +/** + * @brief Check RX is ready or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 The number of bytes in the RX FIFO is less than the RFITL + * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL + * + * @details This macro check receive data available interrupt flag is set or not. + */ +#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos) + + +/** + * @brief Check TX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 TX FIFO is full + * @retval 0 TX FIFO is not full + * + * @details This macro check TX FIFO is full or not. + */ +#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos) + + +/** + * @brief Check RX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 RX FIFO is full + * @retval 0 RX FIFO is not full + * + * @details This macro check RX FIFO is full or not. + */ +#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not full. + * @retval >=1 Tx FIFO is full. + * + * @details This macro get Tx full register value. + */ +#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not full. + * @retval >=1 Rx FIFO is full. + * + * @details This macro get Rx full register value. + */ +#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk) + +/** + * @brief Rx Idle Status register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx is busy. + * @retval 1 Rx is Idle(Default) + * + * @details This macro get Rx Idle Status register value. + * \hideinitializer + */ +#define UART_RX_IDLE(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXIDLE_Msk )>> UART_FIFOSTS_RXIDLE_Pos) + + +/** + * @brief Enable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter empty interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + */ +#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel)) + + +/** + * @brief Disable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt + * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + */ +#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel)) + + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be + * - \ref UART_INTSTS_ABRINT_Msk : Auto-baud Rate Interrupt Indicator + * - \ref UART_INTSTS_HWBUFEINT_Msk : PDMA Mode Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_HWTOINT_Msk : PDMA Mode Rx Time-out Interrupt Indicator + * - \ref UART_INTSTS_HWMODINT_Msk : PDMA Mode MODEM Status Interrupt Indicator + * - \ref UART_INTSTS_HWRLSINT_Msk : PDMA Mode Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt Indicator + * - \ref UART_INTSTS_HWBUFEIF_Msk : PDMA Mode Buffer Error Interrupt Flag + * - \ref UART_INTSTS_HWTOIF_Msk : PDMA Mode Time-out Interrupt Flag + * - \ref UART_INTSTS_HWMODIF_Msk : PDMA Mode MODEM Status Interrupt Flag + * - \ref UART_INTSTS_HWRLSIF_Msk : PDMA Mode Receive Line Status Flag + * - \ref UART_INTSTS_SWBEIF_Msk : Single-wire Bit Error Detect Interrupt Flag + * - \ref UART_INTSTS_TXENDINT_Msk : Transmitter Empty Interrupt Indicator + * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator + * - \ref UART_INTSTS_WKINT_Msk : Wake-up Interrupt Indicator + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_RXTOINT_Msk : Rx Time-out Interrupt Indicator + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator + * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator + * - \ref UART_INTSTS_TXENDIF_Msk : Transmitter Empty Interrupt Flag + * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Interrupt Flag + * - \ref UART_INTSTS_WKIF_Msk : Wake-up Interrupt Flag + * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag + * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag + * - \ref UART_INTSTS_MODEMIF_Msk : MODEM Status Interrupt Flag + * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag + * - \ref UART_INTSTS_THREIF_Msk : Transmit Holding Register Empty Interrupt Flag + * - \ref UART_INTSTS_RDAIF_Msk : Receive Data Available Interrupt Flag + * + * @retval 0 The specified interrupt is not happened. + * 1 The specified interrupt is happened. + * + * @details This macro get specified interrupt flag or interrupt indicator status. + */ +#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0) + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +static __INLINE void UART_CLEAR_RTS(UART_T* uart); +static __INLINE void UART_SET_RTS(UART_T* uart); + + +/** + * @brief Set RTS pin to low + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to low. + */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + uart->MODEM &= ~UART_MODEM_RTS_Msk; +} + + +/** + * @brief Set RTS pin to high + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to high. + */ +__STATIC_INLINE void UART_SET_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk; +} + + +/** + * @brief Clear RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro clear RS-485 address byte detection flag. + */ +#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk) + + +/** + * @brief Get RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Receiver detects a data that is not an address bit. + * @retval 1 Receiver detects a data that is an address bit. + * + * @details This macro get RS-485 address byte detection flag. + */ +#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos) + + +/** + * @brief Enable specified UART PDMA function + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UART_INTEN_TXPDMAEN_Msk + * - \ref UART_INTEN_RXPDMAEN_Msk + * + * @return None + * + * @details This macro enable specified UART PDMA function. + */ +#define UART_PDMA_ENABLE(uart, u32FuncSel) ((uart)->INTEN |= (u32FuncSel)) + + +/** + * @brief Disable specified UART PDMA function + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UART_INTEN_TXPDMAEN_Msk + * - \ref UART_INTEN_RXPDMAEN_Msk + * + * @return None + * + * @details This macro disable specified UART PDMA function. + */ +#define UART_PDMA_DISABLE(uart, u32FuncSel) ((uart)->INTEN &= ~(u32FuncSel)) + + +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Close(UART_T* uart); +void UART_DisableFlowCtrl(UART_T* uart); +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_EnableFlowCtrl(UART_T* uart); +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Open(UART_T* uart, uint32_t u32baudrate); +uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC); +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction); +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr); +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength); +uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); +void UART_SelectSingleWireMode(UART_T *uart); + + +/**@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group UART_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __UART_H__ */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_usbd.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_usbd.h new file mode 100644 index 0000000000..38d325d785 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_usbd.h @@ -0,0 +1,798 @@ +/****************************************************************************** + * @file usbd.h + * @version V3.00 + * @brief M2354 series USBD driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __USBD_H__ +#define __USBD_H__ + +#define SUPPORT_LPM // define to support LPM + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + +/** @addtogroup USBD_EXPORTED_STRUCTS USBD Exported Structs + @{ +*/ + +typedef struct s_usbd_info +{ + uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */ + uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */ + uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */ + uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */ + uint8_t *gu8BosDesc; /*!< Pointer for USB BOS Descriptor */ + uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */ + uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */ + +} S_USBD_INFO_T; /*!< Device description structure */ + +extern const S_USBD_INFO_T gsInfo; + +/**@}*/ /* end of group USBD_EXPORTED_STRUCTS */ + + +/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants + @{ +*/ + +#define USBD_BUF_BASE (uint32_t)(((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_BASE+NS_OFFSET+0x100UL):(USBD_BASE+0x100UL)) /*!< USBD buffer base address */ +#define USBD_MAX_EP 12UL /*!< Total EP number */ + +#define EP0 0UL /*!< Endpoint 0 */ +#define EP1 1UL /*!< Endpoint 1 */ +#define EP2 2UL /*!< Endpoint 2 */ +#define EP3 3UL /*!< Endpoint 3 */ +#define EP4 4UL /*!< Endpoint 4 */ +#define EP5 5UL /*!< Endpoint 5 */ +#define EP6 6UL /*!< Endpoint 6 */ +#define EP7 7UL /*!< Endpoint 7 */ +#define EP8 8UL /*!< Endpoint 8 */ +#define EP9 9UL /*!< Endpoint 9 */ +#define EP10 10UL /*!< Endpoint 10 */ +#define EP11 11UL /*!< Endpoint 11 */ + +/** @cond HIDDEN_SYMBOLS */ +/* USB Request Type */ +#define REQ_STANDARD 0x00UL +#define REQ_CLASS 0x20UL +#define REQ_VENDOR 0x40UL + +/* USB Standard Request */ +#define GET_STATUS 0x00UL +#define CLEAR_FEATURE 0x01UL +#define SET_FEATURE 0x03UL +#define SET_ADDRESS 0x05UL +#define GET_DESCRIPTOR 0x06UL +#define SET_DESCRIPTOR 0x07UL +#define GET_CONFIGURATION 0x08UL +#define SET_CONFIGURATION 0x09UL +#define GET_INTERFACE 0x0AUL +#define SET_INTERFACE 0x0BUL +#define SYNC_FRAME 0x0CUL + +/* USB Descriptor Type */ +#define DESC_DEVICE 0x01UL +#define DESC_CONFIG 0x02UL +#define DESC_STRING 0x03UL +#define DESC_INTERFACE 0x04UL +#define DESC_ENDPOINT 0x05UL +#define DESC_QUALIFIER 0x06UL +#define DESC_OTHERSPEED 0x07UL +#define DESC_IFPOWER 0x08UL +#define DESC_OTG 0x09UL +#define DESC_BOS 0x0FUL +#define DESC_CAPABILITY 0x10UL + +/* USB Device Capability Type */ +#define CAP_WIRELESS 0x01UL +#define CAP_USB20_EXT 0x02UL + +/*! b, then return a. Otherwise, return b. + */ +#define USBD_Maximum(a,b) ((a)>(b) ? (a) : (b)) + +/** + * @brief Compare two input numbers and return minimum one + * + * @param[in] a First number to be compared + * @param[in] b Second number to be compared + * + * @return Minimum value between a and b + * + * @details If a < b, then return a. Otherwise, return b. + */ +#define USBD_Minimum(a,b) ((a)<(b) ? (a) : (b)) + +/** + * @brief Enable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB and PHY. + * + */ +#define USBD_ENABLE_USB() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR |= 0x7D0)):((uint32_t)(USBD->ATTR |= 0x7D0))) + +/** + * @brief Disable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB. + * + */ +#define USBD_DISABLE_USB() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR &= ~USBD_USB_EN)):((uint32_t)(USBD->ATTR &= ~USBD_USB_EN))) + +/** + * @brief Enable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB PHY. + * + */ +#define USBD_ENABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR |= USBD_PHY_EN)):((uint32_t)(USBD->ATTR |= USBD_PHY_EN))) + +/** + * @brief Disable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB PHY. + * + */ +#define USBD_DISABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR &= ~USBD_PHY_EN)):((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN))) + +/** + * @brief Enable SE0. Force USB PHY transceiver to drive SE0. + * + * @param None + * + * @return None + * + * @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus. + * + */ +#define USBD_SET_SE0() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->SE0 |= USBD_DRVSE0)):((uint32_t)(USBD->SE0 |= USBD_DRVSE0))) + +/** + * @brief Disable SE0 + * + * @param None + * + * @return None + * + * @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function. + * + */ +#define USBD_CLR_SE0() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->SE0 &= ~USBD_DRVSE0)):((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0))) + +/** + * @brief Set USB device address + * + * @param[in] addr The USB device address. + * + * @return None + * + * @details Write USB device address to USB_FADDR register. + * + */ +#define USBD_SET_ADDR(addr) (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->FADDR = (addr)):(USBD->FADDR = (addr))) + +/** + * @brief Get USB device address + * + * @param None + * + * @return USB device address + * + * @details Read USB_FADDR register to get USB device address. + * + */ +#define USBD_GET_ADDR() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->FADDR)):((uint32_t)(USBD->FADDR))) + +/** + * @brief Enable USB interrupt function + * + * @param[in] intr The combination of the specified interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. + * (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS) + * + * @return None + * + * @details Enable USB related interrupt functions specified by intr parameter. + * + */ +#define USBD_ENABLE_INT(intr) (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->INTEN |= (intr)):(USBD->INTEN |= (intr))) + +/** + * @brief Get interrupt status + * + * @param None + * + * @return The value of USB_INTSTS register + * + * @details Return all interrupt flags of USB_INTSTS register. + * + */ +#define USBD_GET_INT_FLAG() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->INTSTS)):((uint32_t)(USBD->INTSTS))) + +/** + * @brief Clear USB interrupt flag + * + * @param[in] flag The combination of the specified interrupt flags. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. + * (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB) + * + * @return None + * + * @details Clear USB related interrupt flags specified by flag parameter. + * + */ +#define USBD_CLR_INT_FLAG(flag) (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->INTSTS = (flag)):(USBD->INTSTS = (flag))) + +/** + * @brief Get endpoint status + * + * @param None + * + * @return The value of USB_EPSTS register. + * + * @details Return all endpoint status. + * + */ +#define USBD_GET_EP_FLAG() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->EPSTS)):((uint32_t)(USBD->EPSTS))) + +/** + * @brief Get USB bus state + * + * @param None + * + * @return The value of USB_ATTR[13:12] and USB_ATTR[3:0]. + * Bit 0 indicates USB bus reset status. + * Bit 1 indicates USB bus suspend status. + * Bit 2 indicates USB bus resume status. + * Bit 3 indicates USB bus time-out status. + * Bit 12 indicates USB bus LPM L1 suspend status. + * Bit 13 indicates USB bus LPM L1 resume status. + * + * @details Return USB_ATTR[13:12] and USB_ATTR[3:0] for USB bus events. + * + */ +#define USBD_GET_BUS_STATE() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR & 0x300F)):((uint32_t)(USBD->ATTR & 0x300F))) + +/** + * @brief Check cable connection state + * + * @param None + * + * @retval 0 USB cable is not attached. + * @retval 1 USB cable is attached. + * + * @details Check the connection state by FLDET bit of USB_FLDET register. + * + */ +#define USBD_IS_ATTACHED() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)):((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk))) + +/** + * @brief Stop USB transaction of the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID. + * + */ +#define USBD_STOP_TRANSACTION(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk)) + +/** + * @brief Set USB DATA1 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions in single buffer mode. + * + */ +#define USBD_SET_DATA1(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk)) + +/** + * @brief Set USB DATA0 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions in single buffer mode. + * + */ +#define USBD_SET_DATA0(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk))) + +/** + * @brief Set USB payload size (IN data) + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] size The transfer length. + * + * @return None + * + * @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction. + * + */ +#define USBD_SET_PAYLOAD_LEN(ep, size) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))) + +/** + * @brief Get USB payload size (OUT data) + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return The value of USB_MXPLDx register. + * + * @details Get the data length of OUT data transaction by reading USB_MXPLDx register. + * + */ +#define USBD_GET_PAYLOAD_LEN(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].MXPLD + (uint32_t)((ep) << 4)))):((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))))) + +/** + * @brief Configure endpoint + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] config The USB configuration. + * + * @return None + * + * @details This macro will write config parameter to USB_CFGx register of specified endpoint ID. + * + */ +#define USBD_CONFIG_EP(ep, config) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))) + +/** + * @brief Set USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] offset The SRAM offset. + * + * @return None + * + * @details This macro will set the SRAM offset for the specified endpoint ID. + * + */ +#define USBD_SET_EP_BUF_ADDR(ep, offset) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))) + +/** + * @brief Get the offset of the specified USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return The offset of the specified endpoint buffer. + * + * @details This macro will return the SRAM offset of the specified endpoint ID. + * + */ +#define USBD_GET_EP_BUF_ADDR(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].BUFSEG + (uint32_t)((ep) << 4)))):((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))))) + +/** + * @brief Set USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + * + */ +#define USBD_SET_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk)) + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + * + */ +#define USBD_CLR_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk)) + +/** + * @brief Get USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state of the specified endpoint ID. + * + */ +#define USBD_GET_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk)) + +/** + * @brief Set USB double buffer mode for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set DBEN bit of USB_CFGx register to enable the double buffer mode of the specified endpoint ID. + * + */ +#define USBD_SET_DB_MODE(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBEN_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBEN_Msk)) + +/** + * @brief Set USB single buffer mode for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear DBEN bit of USB_CFGx register to enable the single buffer mode of the specified endpoint ID. + * + */ +#define USBD_SET_SB_MODE(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBEN_Msk)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBEN_Msk))) + +/** + * @brief Get the buffer mode of the specified USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @retval 0 USB is single buffer mode. + * @retval 1 USB is double buffer mode. + * + * @details This macro will return the buffer mode of the specified endpoint ID. + * + */ +#define USBD_IS_DB_MODE(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) & USBD_CFG_DBEN_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) & USBD_CFG_DBEN_Msk)) + +/** + * @brief Set to active in USB double buffer mode for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set DBTGACTIVE bit of USB_CFGx register for toggle active in the double buffer mode of the specified endpoint ID. + * + */ +#define USBD_SET_DB_ACTIVE(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBTGACTIVE_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DBTGACTIVE_Msk)) + +/** + * @brief Set to inactive in USB double buffer mode for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2354 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear DBTGACTIVE bit of USB_CFGx register for toggle inactive in the double buffer mode of the specified endpoint ID. + * + */ +#define USBD_SET_DB_INACTIVE(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBTGACTIVE_Msk)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DBTGACTIVE_Msk))) + +/** + * @brief To support byte access between USB SRAM and system SRAM + * + * @param[in] dest Destination pointer. + * + * @param[in] src Source pointer. + * + * @param[in] size Byte count. + * + * @return None + * + * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter. + * + */ +__STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size) +{ + uint32_t volatile i = 0UL; + + while(size--) + { + dest[i] = src[i]; + i++; + } +} + +/** + * @brief Set USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Set USB endpoint stall state. Endpoint will respond STALL token automatically. + * + */ +__STATIC_INLINE void USBD_SetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + USBD_T *pUSBD; + + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + for(i = 0UL; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xFUL) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token. + */ +__STATIC_INLINE void USBD_ClearStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + USBD_T *pUSBD; + + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + for(i = 0UL; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xFUL) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + * + */ +__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr = 0UL; + uint32_t u32Cfg; + uint32_t i; + USBD_T *pUSBD; + + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + for(i = 0UL; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xFUL) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */ + break; + } + } + + return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL); +} + +extern uint8_t g_USBD_au8SetupPacket[8]; +extern volatile uint8_t g_USBD_u8RemoteWakeupEn; + +typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */ +typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */ +typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!< Functional pointer type declaration for USB set interface request callback handler */ +typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */ + +extern const S_USBD_INFO_T *g_USBD_sInfo; + +extern VENDOR_REQ g_USBD_pfnVendorRequest; +extern CLASS_REQ g_USBD_pfnClassRequest; +extern SET_INTERFACE_REQ g_USBD_pfnSetInterface; +extern SET_CONFIG_CB g_USBD_pfnSetConfigCallback; +extern uint32_t g_USBD_u32EpStallLock; + +/*--------------------------------------------------------------------*/ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface); +void USBD_Start(void); +void USBD_GetSetupPacket(uint8_t *buf); +void USBD_ProcessSetupPacket(void); +void USBD_GetDescriptor(void); +void USBD_StandardRequest(void); +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size); +void USBD_CtrlIn(void); +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size); +void USBD_CtrlOut(void); +void USBD_SwReset(void); +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq); +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback); +void USBD_LockEpStall(uint32_t u32EpBitmap); + + +/**@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group USBD_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_H__ */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_usci_i2c.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_usci_i2c.h new file mode 100644 index 0000000000..fa6e50e172 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_usci_i2c.h @@ -0,0 +1,321 @@ +/**************************************************************************//** + * @file usci_i2c.h + * @version V3.0 + * $Revision: 1 $ + * $Date: 16/07/07 7:50p $ + * @brief M2355 series USCI I2C(UI2C) driver header file + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __USCI_I2C_H__ +#define __USCI_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + +/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C master event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_MASTER_EVENT +{ + MASTER_SEND_ADDRESS = 10u, /*!< Master send address to Slave */ + MASTER_SEND_H_WR_ADDRESS, /*!< Master send High address to Slave */ + MASTER_SEND_H_RD_ADDRESS, /*!< Master send address to Slave (Read ADDR) */ + MASTER_SEND_L_ADDRESS, /*!< Master send Low address to Slave */ + MASTER_SEND_DATA, /*!< Master Send Data to Slave */ + MASTER_SEND_REPEAT_START, /*!< Master send repeat start to Slave */ + MASTER_READ_DATA, /*!< Master Get Data from Slave */ + MASTER_STOP, /*!< Master send stop to Slave */ + MASTER_SEND_START /*!< Master send start to Slave */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C slave event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_SLAVE_EVENT +{ + SLAVE_ADDRESS_ACK = 100u, /*!< Slave send address ACK */ + SLAVE_H_WR_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_WR_ADDRESS_ACK, /*!< Slave send Low address ACK */ + SLAVE_GET_DATA, /*!< Slave Get Data from Master (Write CMD) */ + SLAVE_SEND_DATA, /*!< Slave Send Data to Master (Read CMD) */ + SLAVE_H_RD_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_RD_ADDRESS_ACK /*!< Slave send Low address ACK */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_CTL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_CTL_PTRG (0x20U) /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit */ +#define UI2C_CTL_STA (0x08U) /*!< USCI_CTL setting for I2C control bits. It would set STA bit */ +#define UI2C_CTL_STO (0x04U) /*!< USCI_CTL setting for I2C control bits. It would set STO bit */ +#define UI2C_CTL_AA (0x02U) /*!< USCI_CTL setting for I2C control bits. It would set AA bit */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C GCMode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_GCMODE_ENABLE (1U) /*!< Enable USCI_I2C GC Mode */ +#define UI2C_GCMODE_DISABLE (0U) /*!< Disable USCI_I2C GC Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C Wakeup Mode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_DATA_TOGGLE_WK (0x0U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according data toggle */ +#define UI2C_ADDR_MATCH_WK (0x1U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according address match */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_TO_INT_MASK (0x001U) /*!< Time-out interrupt mask */ +#define UI2C_STAR_INT_MASK (0x002U) /*!< Start condition received interrupt mask */ +#define UI2C_STOR_INT_MASK (0x004U) /*!< Stop condition received interrupt mask */ +#define UI2C_NACK_INT_MASK (0x008U) /*!< Non-acknowledge interrupt mask */ +#define UI2C_ARBLO_INT_MASK (0x010U) /*!< Arbitration lost interrupt mask */ +#define UI2C_ERR_INT_MASK (0x020U) /*!< Error interrupt mask */ +#define UI2C_ACK_INT_MASK (0x040U) /*!< Acknowledge interrupt mask */ + +/**@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This macro sets the USCI_I2C protocol control register at one time + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Ctrl Set the register value of USCI_I2C control register. + * + * @return None + * + * @details Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, PTRG, ACK. + */ +#define UI2C_SET_CONTROL_REG(ui2c, u8Ctrl) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2EU) | (u8Ctrl)) + +/** + * @brief This macro only set START bit to protocol control register of USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus START condition in UI2C_PROTCTL register. + */ +#define UI2C_START(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk) + +/** + * @brief This macro only set STOP bit to the control register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register. + */ +#define UI2C_STOP(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk)) + +/** + * @brief This macro returns the data stored in data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return Data + * + * @details Read a byte data value of UI2C_RXDAT register from USCI_I2C bus + */ +#define UI2C_GET_DATA(ui2c) ((ui2c)->RXDAT) + +/** + * @brief This macro writes the data to data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus + */ +#define UI2C_SET_DATA(ui2c, u8Data) ((ui2c)->TXDAT = (u8Data)) + +/** + * @brief This macro returns time-out flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 USCI_I2C bus time-out is not happened + * @retval 1 USCI_I2C bus time-out is happened + * + * @details USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared. + */ +#define UI2C_GET_TIMEOUT_FLAG(ui2c) (((ui2c)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0) + +/** + * @brief This macro returns wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep. + */ +#define UI2C_GET_WAKEUP_FLAG(ui2c) (((ui2c)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0) + +/** + * @brief This macro is used to clear USCI_I2C wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details If USCI_I2C wake-up flag is set, use this macro to clear it. + */ +#define UI2C_CLR_WAKEUP_FLAG(ui2c) ((ui2c)->WKSTS = UI2C_WKSTS_WKF_Msk) + +/** + * @brief This macro disables the USCI_I2C 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function. + */ +#define UI2C_DISABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk)) + +/** + * @brief This macro enables the 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To enable USCI_I2C 10-bit address match function. + */ +#define UI2C_ENABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk) + +/** + * @brief This macro gets USCI_I2C protocol interrupt flag or bus status + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return A word data of USCI_I2C_PROTSTS register + * + * @details Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status. + */ +#define UI2C_GET_PROT_STATUS(ui2c) ((ui2c)->PROTSTS) + +/** + * @brief This macro clears specified protocol interrupt flag + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UI2C_PROTSTS_ACKIF_Msk + * - \ref UI2C_PROTSTS_ERRIF_Msk + * - \ref UI2C_PROTSTS_ARBLOIF_Msk + * - \ref UI2C_PROTSTS_NACKIF_Msk + * - \ref UI2C_PROTSTS_STORIF_Msk + * - \ref UI2C_PROTSTS_STARIF_Msk + * - \ref UI2C_PROTSTS_TOIF_Msk + * @return None + * + * @details To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag. + */ +#define UI2C_CLR_PROT_INT_FLAG(ui2c,u32IntTypeFlag) ((ui2c)->PROTSTS = (u32IntTypeFlag)) + +/** + * @brief This macro enables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Set specified USCI_I2C protocol interrupt bits to enable interrupt function. + */ +#define UI2C_ENABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN |= (u32IntSel)) + +/** + * @brief This macro disables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Clear specified USCI_I2C protocol interrupt bits to disable interrupt funtion. + */ +#define UI2C_DISABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN &= ~ (u32IntSel)) + + +uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock); +void UI2C_Close(UI2C_T *ui2c); +void UI2C_ClearTimeoutFlag(UI2C_T *ui2c); +void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack); +void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask); +uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c); +uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock); +uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_ClearIntFlag(UI2C_T* ui2c, uint32_t u32Mask); +uint32_t UI2C_GetData(UI2C_T *ui2c); +void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data); +void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode); +void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask); +void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt); +void UI2C_DisableTimeout(UI2C_T *ui2c); +void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode); +void UI2C_DisableWakeup(UI2C_T *ui2c); +uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen); +uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr); +uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen); +/**@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group USCI_I2C_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_usci_spi.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_usci_spi.h new file mode 100644 index 0000000000..6a25bab178 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_usci_spi.h @@ -0,0 +1,422 @@ +/****************************************************************************//** + * @file usci_spi.h + * @version V3.00 + * @brief M2354 series USCI_SPI driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __USCI_SPI_H__ +#define __USCI_SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + +/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants + @{ +*/ + +#define USPI_MODE_0 (0x0UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with falling edge and receive with rising edge */ +#define USPI_MODE_1 (0x1UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with rising edge and receive with falling edge */ +#define USPI_MODE_2 (0x2UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with rising edge and receive with falling edge */ +#define USPI_MODE_3 (0x3UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with falling edge and receive with rising edge */ + +#define USPI_SLAVE (USPI_PROTCTL_SLAVE_Msk) /*!< Set as slave */ +#define USPI_MASTER (0x0UL) /*!< Set as master */ + +#define USPI_SS (USPI_PROTCTL_SS_Msk) /*!< Set SS */ +#define USPI_SS_ACTIVE_HIGH (0x0UL) /*!< SS active high */ +#define USPI_SS_ACTIVE_LOW (USPI_LINECTL_CTLOINV_Msk) /*!< SS active low */ + +/* USCI_SPI Interrupt Mask */ +#define USPI_SSINACT_INT_MASK (0x001UL) /*!< Slave Slave Inactive interrupt mask */ +#define USPI_SSACT_INT_MASK (0x002UL) /*!< Slave Slave Active interrupt mask */ +#define USPI_SLVTO_INT_MASK (0x004UL) /*!< Slave Mode Time-out interrupt mask */ +#define USPI_SLVBE_INT_MASK (0x008UL) /*!< Slave Mode Bit Count Error interrupt mask */ +#define USPI_TXUDR_INT_MASK (0x010UL) /*!< Slave Transmit Under Run interrupt mask */ +#define USPI_RXOV_INT_MASK (0x020UL) /*!< Receive Buffer Overrun interrupt mask */ +#define USPI_TXST_INT_MASK (0x040UL) /*!< Transmit Start interrupt mask */ +#define USPI_TXEND_INT_MASK (0x080UL) /*!< Transmit End interrupt mask */ +#define USPI_RXST_INT_MASK (0x100UL) /*!< Receive Start interrupt mask */ +#define USPI_RXEND_INT_MASK (0x200UL) /*!< Receive End interrupt mask */ + +/* USCI_SPI Status Mask */ +#define USPI_BUSY_MASK (0x01UL) /*!< Busy status mask */ +#define USPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask */ +#define USPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask */ +#define USPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask */ +#define USPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask */ +#define USPI_SSLINE_STS_MASK (0x20UL) /*!< USCI_SPI_SS line status mask */ + +/**@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief Disable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Get the Rx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Rx buffer flag + * @retval 0: Rx buffer is not empty + * @retval 1: Rx buffer is empty + * \hideinitializer + */ +#define USPI_GET_RX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not empty + * @retval 1: Tx buffer is empty + * \hideinitializer + */ +#define USPI_GET_TX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer full flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not full + * @retval 1: Tx buffer is full + * \hideinitializer + */ +#define USPI_GET_TX_FULL_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 ) + +/** + * @brief Get the datum read from RX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return data in Rx register + * \hideinitializer + */ +#define USPI_READ_RX(uspi) ( (uspi)->RXDAT ) + +/** + * @brief Write datum to TX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through USCI_SPI bus. + * @return None + * \hideinitializer + */ +#define USPI_WRITE_TX(uspi, u32TxData) ( (uspi)->TXDAT = (u32TxData) ) + +/** + * @brief Set USCI_SPI_SS pin to high state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_HIGH(uspi) \ + do{ \ + (uspi)->LINECTL &= ~USPI_LINECTL_CTLOINV_Msk; \ + (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \ + }while(0) + +/** + * @brief Set USCI_SPI_SS pin to low state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_LOW(uspi) \ + do{ \ + (uspi)->LINECTL |= USPI_LINECTL_CTLOINV_Msk; \ + (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \ + }while(0) + +/** + * @brief Set the length of suspend interval. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32SuspCycle Decide the length of suspend interval. + * @return None + * \hideinitializer + */ +#define USPI_SET_SUSPEND_CYCLE(uspi, u32SuspCycle) ( (uspi)->PROTCTL = ((uspi)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) ) + +/** + * @brief Set the USCI_SPI transfer sequence with LSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_LSB_FIRST(uspi) ( (uspi)->LINECTL |= USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the USCI_SPI transfer sequence with MSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_MSB_FIRST(uspi) ( (uspi)->LINECTL &= ~USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the data width of a USCI_SPI transaction. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Width The data width + * @return None + * \hideinitializer + */ +#define USPI_SET_DATA_WIDTH(uspi, u32Width) \ + do{ \ + if((u32Width) == 16ul){ \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \ + }else { \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \ + } \ + }while(0) + +/** + * @brief Get the USCI_SPI busy state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return USCI_SPI busy status + * @retval 0: USCI_SPI module is not busy + * @retval 1: USCI_SPI module is busy + * \hideinitializer + */ +#define USPI_IS_BUSY(uspi) ( ((uspi)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 ) + +/** + * @brief Get the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Wakeup status. + * @retval 0 Flag is not set. + * @retval 1 Flag is set. + * \hideinitializer + */ +#define USPI_GET_WAKEUP_FLAG(uspi) ( ((uspi)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0 ) + +/** + * @brief Clear the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_CLR_WAKEUP_FLAG(uspi) ( (uspi)->WKSTS |= USPI_WKSTS_WKF_Msk ) + +/** + * @brief Get protocol interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of protocol status register. + * \hideinitializer + */ +#define USPI_GET_PROT_STATUS(uspi) ( (uspi)->PROTSTS ) + +/** + * @brief Clear specified protocol interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_PROTSTS_SSACTIF_Msk + * - \ref USPI_PROTSTS_SSINAIF_Msk + * - \ref USPI_PROTSTS_SLVBEIF_Msk + * - \ref USPI_PROTSTS_SLVTOIF_Msk + * - \ref USPI_PROTSTS_RXENDIF_Msk + * - \ref USPI_PROTSTS_RXSTIF_Msk + * - \ref USPI_PROTSTS_TXENDIF_Msk + * - \ref USPI_PROTSTS_TXSTIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_PROT_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->PROTSTS = (u32IntTypeFlag) ) + +/** + * @brief Get buffer interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of buffer status register. + * \hideinitializer + */ +#define USPI_GET_BUF_STATUS(uspi) ( (uspi)->BUFSTS ) + +/** + * @brief Clear specified buffer interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_BUFSTS_TXUDRIF_Msk + * - \ref USPI_BUFSTS_RXOVIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_BUF_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->BUFSTS = (u32IntTypeFlag) ) + +/** + * @brief Enable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN |= (u32IntSel) ) + +/** + * @brief Disable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN &= ~ (u32IntSel) ) + +/** + * @brief Enable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL |= (u32IntSel) ) + +/** + * @brief Disable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL &= ~ (u32IntSel) ) + +/** + * @brief Enable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN |= (u32IntSel) ) + +/** + * @brief Disable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN &= ~ (u32IntSel) ) + +/** + * @brief Trigger RX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function. + */ +#define USPI_TRIGGER_RX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk ) + +/** + * @brief Trigger TX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function. + */ +#define USPI_TRIGGER_TX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk ) + +/** + * @brief Trigger TX and RX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to enable TX and RX PDMA transfer function. + */ +#define USPI_TRIGGER_TX_RX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_RXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk ) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function. + */ +#define USPI_DISABLE_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function. + */ +#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable TX and RX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear TXPDMAEN bit and RXPDMAEN bit of USPI_PDMACTL register to disable TX and RX PDMA transfer function. + */ +#define USPI_DISABLE_TX_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~(USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_RXPDMAEN_Msk) ) + +uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void USPI_Close(USPI_T *uspi); +void USPI_ClearRxBuf(USPI_T *uspi); +void USPI_ClearTxBuf(USPI_T *uspi); +void USPI_DisableAutoSS(USPI_T *uspi); +void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock); +uint32_t USPI_GetBusClock(USPI_T *uspi); +void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask); +void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask); +void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask); +void USPI_EnableWakeup(USPI_T *uspi); +void USPI_DisableWakeup(USPI_T *uspi); + + +/**@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group USCI_SPI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USCI_SPI_H__ */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_usci_uart.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_usci_uart.h new file mode 100644 index 0000000000..69f0d6f479 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_usci_uart.h @@ -0,0 +1,448 @@ +/****************************************************************************** + * @file usci_uart.h + * @version V3.00 + * @brief M2354 series USCI UART (UUART) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __USCI_UART_H__ +#define __USCI_UART_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_LINECTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_WORD_LEN_6 (6UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits */ +#define UUART_WORD_LEN_7 (7UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits */ +#define UUART_WORD_LEN_8 (8UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits */ +#define UUART_WORD_LEN_9 (9UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_PROTCTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_PARITY_NONE (0x0UL << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as no parity */ +#define UUART_PARITY_ODD (0x1UL << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as odd parity */ +#define UUART_PARITY_EVEN (0x3UL << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as even parity */ + +#define UUART_STOP_BIT_1 (0x0UL) /*!< UUART_PROTCTL setting for one stop bit */ +#define UUART_STOP_BIT_2 (0x1UL) /*!< UUART_PROTCTL setting for two stop bit */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI UART interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_ABR_INT_MASK (0x002UL) /*!< Auto-baud rate interrupt mask */ +#define UUART_RLS_INT_MASK (0x004UL) /*!< Receive line status interrupt mask */ +#define UUART_BUF_RXOV_INT_MASK (0x008UL) /*!< Buffer RX overrun interrupt mask */ +#define UUART_TXST_INT_MASK (0x010UL) /*!< TX start interrupt mask */ +#define UUART_TXEND_INT_MASK (0x020UL) /*!< Tx end interrupt mask */ +#define UUART_RXST_INT_MASK (0x040UL) /*!< RX start interrupt mask */ +#define UUART_RXEND_INT_MASK (0x080UL) /*!< RX end interrupt mask */ + + +/**@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + + +/** + * @brief Write USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + */ +#define UUART_WRITE(uuart, u8Data) ((uuart)->TXDAT = (u8Data)) + + +/** + * @brief Read USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The oldest data byte in RX buffer. + * + * @details This macro read Rx data register. + */ +#define UUART_READ(uuart) ((uuart)->RXDAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not empty + * @retval >=1 Tx buffer is empty + * + * @details This macro get Transmitter buffer empty register value. + */ +#define UUART_GET_TX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not empty + * @retval >=1 Rx buffer is empty + * + * @details This macro get Receiver buffer empty register value. + */ +#define UUART_GET_RX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified usci_uart port transmission is over. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. \n + * It indicates if specified usci_uart port transmission is over nor not. + */ +#define UUART_IS_TX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos) + + +/** + * @brief Check specified usci_uart port receiver is empty. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx receiver is not empty + * @retval 1 Rx receiver is empty + * + * @details This macro return Receive Empty Flag register bit value. \n + * It indicates if specified usci_uart port receiver is empty nor not. + */ +#define UUART_IS_RX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos) + + +/** + * @brief Wait specified usci_uart port transmission is over + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro wait specified usci_uart port transmission is over. + */ +#define UUART_WAIT_TX_EMPTY(uuart) while(!((((uuart)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)) + + +/** + * @brief Check TX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 TX buffer is full + * @retval 0 TX buffer is not full + * + * @details This macro check TX buffer is full or not. + */ +#define UUART_IS_TX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos) + + +/** + * @brief Check RX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 RX buffer is full + * @retval 0 RX buffer is not full + * + * @details This macro check RX buffer is full or not. + */ +#define UUART_IS_RX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not full. + * @retval >=1 Tx buffer is full. + * + * @details This macro get Tx full register value. + */ +#define UUART_GET_TX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not full. + * @retval >=1 Rx buffer is full. + * + * @details This macro get Rx full register value. + */ +#define UUART_GET_RX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk) + + +/** + * @brief Enable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART protocol interrupt. + */ +#define UUART_ENABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART protocol interrupt. + */ +#define UUART_DISABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN &= ~(u32IntSel)) + + +/** + * @brief Enable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART buffer interrupt. + */ +#define UUART_ENABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART buffer interrupt. + */ +#define UUART_DISABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL &= ~ (u32IntSel)) + + +/** + * @brief Enable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART transfer interrupt. + */ +#define UUART_ENABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART transfer interrupt. + */ +#define UUART_DISABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN &= ~(u32IntSel)) + + +/** + * @brief Get protocol interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of protocol status register. + * + * @details This macro get protocol status register value. + */ +#define UUART_GET_PROT_STATUS(uuart) ((uuart)->PROTSTS) + + +/** + * @brief Clear specified protocol interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator + * - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag + * - \ref UUART_PROTSTS_BREAK_Msk : Break Flag + * - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag + * - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag + * - \ref UUART_PROTSTS_RXENDIF_Msk : Receive End Interrupt Flag + * - \ref UUART_PROTSTS_RXSTIF_Msk : Receive Start Interrupt Flag + * - \ref UUART_PROTSTS_TXENDIF_Msk : Transmit End Interrupt Flag + * - \ref UUART_PROTSTS_TXSTIF_Msk : Transmit Start Interrupt Flag + * + * @return None + * + * @details This macro clear specified protocol interrupt flag. + */ +#define UUART_CLR_PROT_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->PROTSTS = (u32IntTypeFlag)) + + +/** + * @brief Get transmit/receive buffer interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of buffer status register. + * + * @details This macro get buffer status register value. + */ +#define UUART_GET_BUF_STATUS(uuart) ((uuart)->BUFSTS) + + +/** + * @brief Clear specified buffer interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error Interrupt Indicator + * + * @return None + * + * @details This macro clear specified buffer interrupt flag. + */ +#define UUART_CLR_BUF_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->BUFSTS = (u32IntTypeFlag)) + + +/** + * @brief Get wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Chip did not wake up from power-down mode. + * @retval 1 Chip waked up from power-down mode. + * + * @details This macro get wakeup flag. + */ +#define UUART_GET_WAKEUP_FLAG(uuart) ((uuart)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 ) + + +/** + * @brief Clear wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro clear wakeup flag. + */ +#define UUART_CLR_WAKEUP_FLAG(uuart) ((uuart)->WKSTS = UUART_WKSTS_WKF_Msk) + + +/** + * @brief Enable specified USCI_UART PDMA function + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UUART_PDMACTL_TXPDMAEN_Msk + * - \ref UUART_PDMACTL_RXPDMAEN_Msk + * - \ref UUART_PDMACTL_PDMAEN_Msk + * + * @return None + * + * @details This macro enable specified USCI_UART PDMA function. + */ +#define UUART_PDMA_ENABLE(uuart, u32FuncSel) ((uuart)->PDMACTL |= (u32FuncSel)) + +/** + * @brief Disable specified USCI_UART PDMA function + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32FuncSel Combination of following functions + * - \ref UUART_PDMACTL_TXPDMAEN_Msk + * - \ref UUART_PDMACTL_RXPDMAEN_Msk + * - \ref UUART_PDMACTL_PDMAEN_Msk + * + * @return None + * + * @details This macro disable specified USCI_UART PDMA function. + */ +#define UUART_PDMA_DISABLE(uuart, u32FuncSel) ((uuart)->PDMACTL &= ~(u32FuncSel)) + + +void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask); +void UUART_Close(UUART_T* uuart); +void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask); +void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate); +uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); +void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode); +void UUART_DisableWakeup(UUART_T* uuart); +void UUART_EnableFlowCtrl(UUART_T* uuart); +void UUART_DisableFlowCtrl(UUART_T* uuart); + + +/**@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group USCI_UART_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USCI_UART_H__ */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_wdt.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_wdt.h new file mode 100644 index 0000000000..e3f954b22f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_wdt.h @@ -0,0 +1,219 @@ +/**************************************************************************//** + * @file wdt.h + * @version V3.00 + * @brief Watchdog Timer(WDT) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_H__ +#define __WDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Time-out Interval Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW20 (8UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^20 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Reset Delay Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Free Reset Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_COUNTER_KEYWORD (0x00005AA5UL) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter \hideinitializer */ + +/**@}*/ /* end of group WDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Clear WDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out reset system flag. + * \hideinitializer + */ +#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk) + +/** + * @brief Clear WDT Time-out Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out interrupt flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk) + +/** + * @brief Clear WDT Wake-up Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out wake-up system flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk) + +/** + * @brief Get WDT Time-out Reset Flag + * + * @param None + * + * @retval 0 WDT time-out reset system did not occur + * @retval 1 WDT time-out reset system occurred + * + * @details This macro indicates system has been reset by WDT time-out reset or not. + * \hideinitializer + */ +#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Interrupt Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt did not occur + * @retval 1 WDT time-out interrupt occurred + * + * @details This macro indicates WDT time-out interrupt occurred or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Wake-up Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt does not cause CPU wake-up + * @retval 1 WDT time-out interrupt event cause CPU wake-up + * + * @details This macro indicates WDT time-out interrupt event has waked up system or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL) + +/** + * @brief Reset WDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reset the internal 20-bit WDT up counter value. + * @note If WDT is activated and time-out reset system function is enabled also, user should \n + * reset the 20-bit WDT up counter value to avoid generate WDT time-out reset signal to \n + * reset system before the WDT time-out reset delay period expires. + * \hideinitializer + */ +#define WDT_RESET_COUNTER() (WDT->RSTCNT = WDT_RESET_COUNTER_KEYWORD) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void WDT_Close(void); +__STATIC_INLINE void WDT_EnableInt(void); +__STATIC_INLINE void WDT_DisableInt(void); + +/** + * @brief Stop WDT Counting + * + * @param None + * + * @return None + * + * @details This function will stop WDT counting and disable WDT module. + */ +__STATIC_INLINE void WDT_Close(void) +{ + WDT->CTL = 0UL; + while(WDT->CTL & WDT_CTL_SYNC_Msk) {} /* Wait disable WDTEN bit completed, it needs 2 * WDT_CLK. */ +} + +/** + * @brief Enable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_EnableInt(void) +{ + WDT->CTL |= WDT_CTL_INTEN_Msk; +} + +/** + * @brief Disable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_DisableInt(void) +{ + /* Do not touch another write 1 clear bits */ + WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk); +} + +void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup); + +/**@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group WDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WDT_H__ */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_wwdt.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_wwdt.h new file mode 100644 index 0000000000..1f513c581e --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/inc/m2354_wwdt.h @@ -0,0 +1,152 @@ +/**************************************************************************//** + * @file wwdt.h + * @version V3.00 + * @brief Window Watchdog Timer(WWDT) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_H__ +#define __WWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Prescale Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Reload Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */ + +/**@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Clear WWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT time-out reset system flag. + * \hideinitializer + */ +#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk) + +/** + * @brief Clear WWDT Compared Match Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT compared match interrupt flag. + * \hideinitializer + */ +#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk) + +/** + * @brief Get WWDT Reset System Flag + * + * @param None + * + * @retval 0 WWDT time-out reset system did not occur + * @retval 1 WWDT time-out reset system occurred + * + * @details This macro is used to indicate system has been reset by WWDT time-out reset or not. + * \hideinitializer + */ +#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Compared Match Interrupt Flag + * + * @param None + * + * @retval 0 WWDT compare match interrupt did not occur + * @retval 1 WWDT compare match interrupt occurred + * + * @details This macro is used to indicate WWDT counter value matches CMPDAT value or not. + * \hideinitializer + */ +#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Counter + * + * @param None + * + * @return WWDT Counter Value + * + * @details This macro reflects the current WWDT counter value. + * \hideinitializer + */ +#define WWDT_GET_COUNTER() (WWDT->CNT) + +/** + * @brief Reload WWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reload the WWDT counter value to 0x3F. + * @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n + * between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n + * WWDT reset signal will generate immediately to reset system. + * \hideinitializer + */ +#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD) + +void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt); + +/**@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group WWDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WWDT_H__ */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_acmp.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_acmp.c new file mode 100644 index 0000000000..30eea878bc --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_acmp.c @@ -0,0 +1,85 @@ +/**************************************************************************//** + * @file acmp.c + * @version V3.00 + * @brief Analog Comparator(ACMP) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + + +/** + * @brief Configure the specified ACMP module + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * @param[in] u32NegSrc Comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * + * @return None + * + * @details Configure hysteresis function, select the source of negative input and enable analog comparator. + */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel) +{ + acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk); +} + +/** + * @brief Close analog comparator + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * + * @return None + * + * @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + */ +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum) +{ + acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk); +} + + + +/**@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group ACMP_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_bpwm.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_bpwm.c new file mode 100644 index 0000000000..4c39ef02e9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_bpwm.c @@ -0,0 +1,715 @@ +/**************************************************************************//** + * @file bpwm.c + * @version V1.00 + * @brief M2354 series BPWM driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + + +/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions + @{ +*/ + +/** + * @brief Configure BPWM capture and get the nearest unit time. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure BPWM capture and get the nearest unit time. + */ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32PWMClockSrc; + uint32_t u32NearestUnitTimeNsec = 0U; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + uint8_t u8BreakLoop = 0U; + + (void)u32ChannelNum; + (void)u32CaptureEdge; + + /* clock source is from PCLK */ + if((((uint32_t)bpwm) == BPWM0_BASE) || (((uint32_t)bpwm) == BPWM0_BASE + NS_OFFSET)) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else/* if((bpwm == BPWM1)||(bpwm == BPWM1_NS)) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + + u32PWMClockSrc /= 1000UL; + for(u32Prescale = 1U; u32Prescale <= 0x1000UL; u32Prescale++) + { + u32NearestUnitTimeNsec = (1000000UL * u32Prescale) / u32PWMClockSrc; + if(u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if(u32Prescale == 0x1000U) + { + /* limit to the maximum unit time(nano second) */ + u8BreakLoop = 1U; + } + if(!((1000000UL * (u32Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc)))) + { + u8BreakLoop = 1U; + } + } + else + { + u8BreakLoop = 1U; + } + if(u8BreakLoop) + { + break; + } + } + + /* convert to real register value */ + u32Prescale = u32Prescale - 1U; + /* all channels share a prescaler */ + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale); + + /* set BPWM to down count type(edge aligned) */ + (bpwm)->CTL1 = (1UL); + + BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure BPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect + * existing frequency of other channel. + * @note This function is used for initial stage. + * To change duty cycle later, it should get the configured period value and calculate the new comparator value. + */ +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32PWMClockSrc; + uint32_t i; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + /* clock source is from PCLK */ + if(((uint32_t)bpwm == BPWM0_BASE) || ((uint32_t)bpwm == BPWM0_BASE + NS_OFFSET)) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else/* if((bpwm == BPWM1)||(bpwm == BPWM1_NS)) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + + for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++)/* prescale could be 0~0xFFF */ + { + i = (u32PWMClockSrc / u32Frequency) / u32Prescale; + /* If target value is larger than CNR, need to use a larger prescaler */ + if(i <= (0x10000U)) + { + u32CNR = i; + break; + } + } + /* Store return value here 'cos we're gonna change u32Prescale & u32CNR to the real value to fill into register */ + i = u32PWMClockSrc / (u32Prescale * u32CNR); + + /* convert to real register value */ + u32Prescale = u32Prescale - 1U; + /* all channels share a prescaler */ + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale); + /* set BPWM to up counter type(edge aligned) */ + (bpwm)->CTL1 = BPWM_UP_COUNTER; + + u32CNR = u32CNR - 1U; + BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR); + BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL); + + + (bpwm)->WGCTL0 = ((bpwm)->WGCTL0 & ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \ + (BPWM_OUTPUT_HIGH << (u32ChannelNum << 1UL << BPWM_WGCTL0_ZPCTL0_Pos)); + (bpwm)->WGCTL1 = ((bpwm)->WGCTL1 & ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1))) | \ + (BPWM_OUTPUT_LOW << (u32ChannelNum << 1UL << BPWM_WGCTL1_CMPUCTL0_Pos)); + + return(i); +} + +/** + * @brief Start BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to start BPWM module. + * @note All channels share one counter. + */ +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (void)u32ChannelMask; + (bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Stop BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM module. + * @note All channels share one period. + */ +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (void)u32ChannelMask; + (bpwm)->PERIOD = 0UL; +} + +/** + * @brief Stop BPWM generation immediately by clear channel enable bit + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM generation immediately by clear channel enable bit. + * @note All channels share one counter. + */ +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (void)u32ChannelMask; + (bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable selected channel to trigger ADC + */ +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if(u32ChannelNum < 4UL) + { + (bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3)); + (bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3)); + } + else + { + (bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3)); + (bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~3 + * @return None + * @details This function is used to disable selected channel to trigger ADC + */ +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + if(u32ChannelNum < 4UL) + { + (bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3)); + } + else + { + (bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3)); + } +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag + */ +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (void)u32Condition; + (bpwm)->STATUS = (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get BPWM trigger ADC to start of conversion flag for specified channel + */ +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s) + */ +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN |= u32ChannelMask; + (bpwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s) + */ +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN &= ~u32ChannelMask; + (bpwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enables BPWM output generation of selected channel(s) + */ +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disables BPWM output generation of selected channel(s) + */ +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + uint32_t u32CapIf = 0UL; + + u32CapIf = ((((bpwm)->CAPIF & (BPWM_CAPIF_CAPFIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1); + u32CapIf |= (((bpwm)->CAPIF & (BPWM_CAPIF_CAPRIF0_Msk << u32ChannelNum)) ? 1UL : 0UL); + return u32CapIf; +} + +/** + * @brief Enable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel + */ +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN &= (uint32_t)(~((BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum)); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel + */ +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = (BPWM_INTSTS_CMPUIF0_Msk | BPWM_INTSTS_CMPDIF0_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel + */ +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return ((((bpwm)->INTSTS & ((BPWM_INTSTS_CMPDIF0_Msk | BPWM_INTSTS_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (void)u32ChannelNum; + (void)u32IntPeriodType; + (bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk; +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to enable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk; +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return zero interrupt flag of specified channel + * @retval 0 zero interrupt did not occur + * @retval 1 zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode BPWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode BPWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Set BPWM clock source + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32ClkSrcSel BPWM external clock source. + * - \ref BPWM_CLKSRC_BPWM_CLK + * - \ref BPWM_CLKSRC_TIMER0 + * - \ref BPWM_CLKSRC_TIMER1 + * - \ref BPWM_CLKSRC_TIMER2 + * - \ref BPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set BPWM clock source. + * @note All channels share channel 0's setting. + */ +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (void)u32ChannelNum; + (bpwm)->CLKSRC = (u32ClkSrcSel); +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk; +} + + +/**@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group BPWM_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_can.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_can.c new file mode 100644 index 0000000000..b4eaa17db2 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_can.c @@ -0,0 +1,1193 @@ +/**************************************************************************//** + * @file can.c + * @version V3.00 + * @brief CAN driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +#if defined(__ICCARM__) +# pragma diag_suppress=Pm073, Pm143 /* Misra C rule 14.7 */ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions + @{ +*/ + +/** @cond HIDDEN_SYMBOLS */ + +#if defined(CAN1) +static uint8_t gu8LockCanIf[2][2] = {{0U}}; /* The chip has two CANs. */ +#elif defined(CAN0) || defined(CAN) +static uint8_t gu8LockCanIf[1][2] = {{0U}}; /* The chip only has one CAN. */ +#endif + +#define RETRY_COUNTS (0x10000000UL) + +#define TSEG1_MIN 2 +#define TSEG1_MAX 16 +#define TSEG2_MIN 1 +#define TSEG2_MAX 8 +#define BRP_MIN 1 +#define BRP_MAX 1024 /* 6-bit BRP field + 4-bit BRPE field*/ +#define SJW_MAX 4UL +#define BRP_INC 1 + +/* #define DEBUG_PRINTF printf */ +#define DEBUG_PRINTF(...) + + +static uint32_t LockIF(CAN_T *tCAN); +static uint32_t LockIF_TL(CAN_T *tCAN); +static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo); +static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2); + +/** + * @brief Check if any interface is available then lock it for usage. + * @param[in] tCAN The pointer to CAN module base address. + * @retval 0 IF0 is free + * @retval 1 IF1 is free + * @retval 2 No IF is free + * @details Search the first free message interface, starting from 0. If a interface is + * available, set a flag to lock the interface. + */ +static uint32_t LockIF(CAN_T *tCAN) +{ + uint32_t u32CanNo; + uint32_t u32FreeIfNo; + uint32_t u32IntMask; + +#if defined(CAN1) + u32CanNo = (tCAN == CAN1) ? 1 : 0; +#else // defined(CAN0) || defined(CAN) + u32CanNo = 0U; +#endif + + u32FreeIfNo = 2U; + + /* Disable CAN interrupt */ + u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + + /* Check interface 1 is available or not */ + if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0U) + { + if(gu8LockCanIf[u32CanNo][0] == (uint8_t)FALSE) + { + gu8LockCanIf[u32CanNo][0] = (uint8_t)TRUE; + u32FreeIfNo = 0U; + } + } + + /* Or check interface 2 is available or not */ + if(u32FreeIfNo == 2U) + { + if((tCAN->IF[1].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0U) + { + if(gu8LockCanIf[u32CanNo][1] == (uint8_t)FALSE) + { + gu8LockCanIf[u32CanNo][1] = (uint8_t)TRUE; + u32FreeIfNo = 1U; + } + } + } + + /* Enable CAN interrupt */ + tCAN->CON |= u32IntMask; + + return u32FreeIfNo; +} + +/** + * @brief Check if any interface is available in a time limitation then lock it for usage. + * @param[in] tCAN The pointer to CAN module base address. + * @retval 0 IF0 is free + * @retval 1 IF1 is free + * @retval 2 No IF is free + * @details Search the first free message interface, starting from 0. If no interface is + * it will try again until time out. If a interface is available, set a flag to + * lock the interface. + */ +static uint32_t LockIF_TL(CAN_T *tCAN) +{ + uint32_t u32Count; + uint32_t u32FreeIfNo = 0; + + for(u32Count = 0U; u32Count < (uint32_t)RETRY_COUNTS; u32Count++) + { + if((u32FreeIfNo = LockIF(tCAN)) != 2U) + { + break; + } + } + + return u32FreeIfNo; +} + +/** + * @brief Release locked interface. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Info The interface number, 0 or 1. + * @return none + * @details Release the locked interface. + */ +static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo) +{ + uint32_t u32IntMask; + uint32_t u32CanNo; + + if(u32IfNo < 2U) + { + +#if defined(CAN1) + u32CanNo = (tCAN == CAN1) ? 1U : 0U; +#else // defined(CAN0) || defined(CAN) + u32CanNo = 0U; +#endif + + /* Disable CAN interrupt */ + u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + + gu8LockCanIf[u32CanNo][u32IfNo] = (uint8_t)FALSE; + + /* Enable CAN interrupt */ + tCAN->CON |= u32IntMask; + } +} + +/** + * @brief Enter initialization mode + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] Following values can be used. + * \ref CAN_CON_DAR_Msk Disable automatic retransmission. + * \ref CAN_CON_EIE_Msk Enable error interrupt. + * \ref CAN_CON_SIE_Msk Enable status interrupt. + * \ref CAN_CON_IE_Msk CAN interrupt. + * @return None + * @details This function is used to set CAN to enter initialization mode and enable access bit timing + * register. After bit timing configuration ready, user must call CAN_LeaveInitMode() + * to leave initialization mode and lock bit timing register to let new configuration + * take effect. + */ +void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask) +{ + tCAN->CON = u8Mask | (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk); +} + + +/** + * @brief Leave initialization mode + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to set CAN to leave initialization mode to let + * bit timing configuration take effect after configuration ready. + */ +void CAN_LeaveInitMode(CAN_T *tCAN) +{ + tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk)); + while(tCAN->CON & CAN_CON_INIT_Msk) {} /* Check INIT bit is released */ +} + +/** + * @brief Wait message into message buffer in basic mode. + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to wait message into message buffer in basic mode. Please notice the + * function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode. + */ +void CAN_WaitMsg(CAN_T *tCAN) +{ + tCAN->STATUS = 0x0U; /* clr status */ + + while(1) + { + if(tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) /* check new data */ + { + /* DEBUG_PRINTF("New Data IN\n"); */ + break; + } + + if(tCAN->STATUS & CAN_STATUS_RXOK_Msk) + { + /* DEBUG_PRINTF("Rx OK\n"); */ + } + + if(tCAN->STATUS & CAN_STATUS_LEC_Msk) + { + /* DEBUG_PRINTF("Error\n"); */ + } + } +} + +/** + * @brief Get current bit rate + * @param[in] tCAN The pointer to CAN module base address. + * @return Current Bit-Rate (kilo bit per second) + * @details Return current CAN bit rate according to the user bit-timing parameter settings + */ +uint32_t CAN_GetCANBitRate(CAN_T *tCAN) +{ + uint8_t u8Tseg1, u8Tseg2; + uint32_t u32Bpr; + + u8Tseg1 = (uint8_t)((tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos); + u8Tseg2 = (uint8_t)((tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos); + u32Bpr = (tCAN->BTIME & CAN_BTIME_BRP_Msk); + u32Bpr |= (tCAN->BRPE << 6); + + + return (SystemCoreClock / (u32Bpr + 1U) / ((uint32_t)u8Tseg1 + (uint32_t)u8Tseg2 + 3U)); +} + +/** + * @brief Switch the CAN into test mode. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8TestMask Specifies the configuration in test modes + * \ref CAN_TEST_BASIC_Msk Enable basic mode of test mode + * \ref CAN_TEST_SILENT_Msk Enable silent mode of test mode + * \ref CAN_TEST_LBACK_Msk Enable Loop Back Mode of test mode + * \ref CAN_TEST_TX0_Msk / \ref CAN_TEST_TX1_Msk Control CAN_TX pin bit field + * @return None + * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/ + * LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user + * must call CAN_LeaveInitMode() to let the setting take effect. + */ +void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask) +{ + tCAN->CON |= CAN_CON_TEST_Msk; + tCAN->TEST = u8TestMask; +} + + +/** + * @brief Leave the test mode + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to Leave the test mode (switch into normal mode). + */ +void CAN_LeaveTestMode(CAN_T *tCAN) +{ + tCAN->CON |= CAN_CON_TEST_Msk; + tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk); + tCAN->CON &= (~CAN_CON_TEST_Msk); +} + +/** + * @brief Get the waiting status of a received message. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @retval non-zero The corresponding message object has a new data bit is set. + * @retval 0 No message object has new data. + * @details This function is used to get the waiting status of a received message. + */ +uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj) +{ + uint32_t ret; + + if((uint32_t)u8MsgObj < 16U) + { + ret = tCAN->NDAT1 & (1UL << u8MsgObj); + } + else + { + ret = tCAN->NDAT2 & (1UL << (u8MsgObj - 16U)); + } + + return ret; +} + + +/** + * @brief Send CAN message in BASIC mode of test mode + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] pCanMsg Pointer to the message structure containing data to transmit. + * @return TRUE: Transmission OK + * FALSE: Check busy flag of interface 0 is timeout + * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API, + * the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter + * basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode. + */ +int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg) +{ + uint32_t i = 0UL; + while(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) {} + + + tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk); + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + tCAN->IF[0].ARB1 = 0UL; + tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x7FFUL) << 2) ; + } + else + { + /* extended ID*/ + tCAN->IF[0].ARB1 = (pCanMsg->Id) & 0xFFFFUL; + tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x1FFF0000UL) >> 16) | CAN_IF_ARB2_XTD_Msk; + + } + + if(pCanMsg->FrameType) + { + tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk; + } + else + { + tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk); + } + + tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC; + tCAN->IF[0].DAT_A1 = ((uint32_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]; + tCAN->IF[0].DAT_A2 = ((uint32_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]; + tCAN->IF[0].DAT_B1 = ((uint32_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]; + tCAN->IF[0].DAT_B2 = ((uint32_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]; + + /* request transmission*/ + tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk); + if(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /* DEBUG_PRINTF("Cannot clear busy for sending ...\n"); */ + return (int32_t)FALSE; + } + + tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk; /* sending */ + + for(i = 0UL; i < 0xFFFFFUL; i++) + { + if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0UL) + { + break; + } + } + + if(i >= 0xFFFFFUL) + { + /* DEBUG_PRINTF("Cannot send out...\n"); */ + return (int32_t)FALSE; + } + + + return (int32_t)TRUE; +} + +/** + * @brief Get a message information in BASIC mode. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @return FALSE No any message received. + * TRUE Receive a message success. + * + */ +int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg) +{ + + if((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0UL) /* In basic mode, receive data always save in IF2 */ + { + return (int32_t)FALSE; + } + + tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk); + + tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + if((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0UL) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FFUL; + + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (tCAN->IF[1].ARB2 & 0x1FFFUL) << 16; + pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1; + } + + /* + pCanMsg->FrameType = (uint32_t)(!(uint32_t)((tCAN->IF[1].ARB2 & (uint32_t)CAN_IF_ARB2_DIR_Msk) >> (uint32_t)CAN_IF_ARB2_DIR_Pos)); + */ + + pCanMsg->FrameType = (tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) ? 0UL : 1UL; + + pCanMsg->DLC = (uint8_t)(tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk); + pCanMsg->Data[0] = (uint8_t)(tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk); + pCanMsg->Data[1] = (uint8_t)((tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos); + pCanMsg->Data[2] = (uint8_t)(tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk); + pCanMsg->Data[3] = (uint8_t)((tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos); + pCanMsg->Data[4] = (uint8_t)(tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk); + pCanMsg->Data[5] = (uint8_t)((tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos); + pCanMsg->Data[6] = (uint8_t)(tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk); + pCanMsg->Data[7] = (uint8_t)((tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos); + + return (int32_t)TRUE; +} + +/** + * @brief Set Rx message object, include ID mask. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted + * This parameter can be one of the following values: + * \ref CAN_STD_ID (standard ID, 11-bit) + * \ref CAN_EXT_ID (extended ID, 29-bit) + * @param[in] u32id Specifies the identifier used for acceptance filtering. + * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator. + * This parameter can be one of the following values: + * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO. + * FALSE: for a FIFO receive object that is not the last one. + * @retval TRUE SUCCESS + * @retval FALSE No useful interface + * @details The function is used to configure a receive message object. + */ +int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast) +{ + uint8_t u8MsgIfNum; + + /* Get and lock a free interface */ + if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U) + { + return (int32_t)FALSE; + } + + /* Command Setting */ + tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + tCAN->IF[u8MsgIfNum].ARB1 = 0U; + tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFUL) << 2; + } + else + { + tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFFUL; + tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000UL) >> 16; + } + + tCAN->IF[u8MsgIfNum].MASK1 = (u32idmask & 0xFFFFUL); + tCAN->IF[u8MsgIfNum].MASK2 = (u32idmask >> 16) & 0xFFFFUL; + + + tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; + if(u8singleOrFifoLast) + { + tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk; + } + else + { + tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk); + } + + tCAN->IF[u8MsgIfNum].DAT_A1 = 0U; + tCAN->IF[u8MsgIfNum].DAT_A2 = 0U; + tCAN->IF[u8MsgIfNum].DAT_B1 = 0U; + tCAN->IF[u8MsgIfNum].DAT_B2 = 0U; + + tCAN->IF[u8MsgIfNum].CREQ = 1UL + u8MsgObj; + ReleaseIF(tCAN, (uint32_t)u8MsgIfNum); + + return (int32_t)TRUE; +} + +/** + * @brief Set Rx message object + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted + * This parameter can be one of the following values: + * \ref CAN_STD_ID (standard ID, 11-bit) + * \ref CAN_EXT_ID (extended ID, 29-bit) + * @param[in] u32id Specifies the identifier used for acceptance filtering. + * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator. + * This parameter can be one of the following values: + * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO. + * FALSE: for a FIFO receive object that is not the last one. + * @retval TRUE SUCCESS + * @retval FALSE No useful interface + * @details The function is used to configure a receive message object. + */ +int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast) +{ + uint8_t u8MsgIfNum; + + /* Get and lock a free interface */ + if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U) + { + return (int32_t)FALSE; + } + + /* Command Setting */ + tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + tCAN->IF[u8MsgIfNum].ARB1 = 0U; + tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFUL) << 2; + } + else + { + tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFFUL; + tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000UL) >> 16; + } + + + tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; + if(u8singleOrFifoLast) + { + tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk; + } + else + { + tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk); + } + + tCAN->IF[u8MsgIfNum].DAT_A1 = 0U; + tCAN->IF[u8MsgIfNum].DAT_A2 = 0U; + tCAN->IF[u8MsgIfNum].DAT_B1 = 0U; + tCAN->IF[u8MsgIfNum].DAT_B2 = 0U; + + tCAN->IF[u8MsgIfNum].CREQ = 1UL + u8MsgObj; + ReleaseIF(tCAN, (uint32_t)u8MsgIfNum); + + return (int32_t)TRUE; +} + +/** + * @brief Gets the message + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8Release Specifies the message release indicator. + * This parameter can be one of the following values: + * TRUE: the message object is released when getting the data. + * FALSE:the message object is not released. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * @retval TRUE Success + * @retval FALSE No any message received + * @details Gets the message, if received. + */ +int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg) +{ + uint8_t u8MsgIfNum; + uint32_t u32Tmp; + + if(!CAN_IsNewDataReceived(tCAN, u8MsgObj)) + { + return (int32_t)FALSE; + } + + /* Get and lock a free interface */ + if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U) + { + return (int32_t)FALSE; + } + + tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk); + + /* read the message contents*/ + tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_MASK_Msk + | CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_CLRINTPND_Msk + | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0UL) + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + tCAN->IF[u8MsgIfNum].CREQ = 1UL + u8MsgObj; + + while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + + if((tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0U) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + + u32Tmp = (((tCAN->IF[u8MsgIfNum].ARB2) & 0x1FFFUL) << 16); + u32Tmp |= tCAN->IF[u8MsgIfNum].ARB1; + + pCanMsg->Id = u32Tmp; + } + + pCanMsg->DLC = (uint8_t)(tCAN->IF[u8MsgIfNum].MCON & CAN_IF_MCON_DLC_Msk); + pCanMsg->Data[0] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk); + pCanMsg->Data[1] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos); + pCanMsg->Data[2] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk); + pCanMsg->Data[3] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos); + pCanMsg->Data[4] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk); + pCanMsg->Data[5] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos); + pCanMsg->Data[6] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk); + pCanMsg->Data[7] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos); + + ReleaseIF(tCAN, (uint32_t)u8MsgIfNum); + return (int32_t)TRUE; +} + +static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2) +{ + *tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000; + if(*tseg2 < TSEG2_MIN) + { + *tseg2 = TSEG2_MIN; + } + if(*tseg2 > TSEG2_MAX) + { + *tseg2 = TSEG2_MAX; + } + + *tseg1 = tseg - *tseg2; + + if(*tseg1 > TSEG1_MAX) + { + *tseg1 = TSEG1_MAX; + *tseg2 = tseg - *tseg1; + } + return 1000 * (tseg + 1 - *tseg2) / (tseg + 1); +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Set bus baud-rate. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * + * @return u32CurrentBitRate Real baud-rate value. + * + * @details The function is used to set bus timing parameter according current clock and target baud-rate. + */ +uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate) +{ + long rate; + long best_error = 1000000000, error = 0; + int best_tseg = 0, best_brp = 0, brp = 0; + int tsegall, tseg = 0, tseg1 = 0, tseg2 = 0; + int spt_error = 1000, spt = 0, sampl_pt; + int64_t clock_freq = 0; + uint32_t sjw = 1UL; + + CAN_EnterInitMode(tCAN, 0U); + + clock_freq = (int64_t)CLK_GetPCLK0Freq(); + + if(u32BaudRate >= 1000000UL) + { + u32BaudRate = 1000000UL; + } + + /* Use CIA recommended sample points */ + if(u32BaudRate > 800000UL) + { + sampl_pt = 750; + } + else if(u32BaudRate > 500000UL) + { + sampl_pt = 800; + } + else + { + sampl_pt = 875; + } + + /* tseg even = round down, odd = round up */ + for(tseg = (TSEG1_MAX + TSEG2_MAX) * 2 + 1; tseg >= (TSEG1_MIN + TSEG2_MIN) * 2; tseg--) + { + tsegall = 1 + tseg / 2; + /* Compute all possible tseg choices (tseg=tseg1+tseg2) */ + + /* brp = (int32_t)(clock_freq / (tsegall * u32BaudRate)) + (tseg % 2); */ + brp = (int32_t)(clock_freq / ((int64_t)tsegall * (int32_t)u32BaudRate)) + (tseg % 2); + + + /* chose brp step which is possible in system */ + brp = (brp / BRP_INC) * BRP_INC; + + if((brp >= BRP_MIN) && (brp <= BRP_MAX)) + { + rate = (int32_t)(clock_freq / ((int64_t)brp * tsegall)); + + error = (int32_t)u32BaudRate - rate; + + /* tseg brp biterror */ + if(error < 0) + { + error = -error; + } + + if(error <= best_error) + { + best_error = error; + if(error == 0) + { + spt = can_update_spt(sampl_pt, tseg / 2, &tseg1, &tseg2); + error = sampl_pt - spt; + if(error < 0) + { + error = -error; + } + if(error <= spt_error) + { + spt_error = error; + best_tseg = tseg / 2; + best_brp = brp; + if(error == 0) + { + break; + } + } + } + else + { + best_tseg = tseg / 2; + best_brp = brp; + } + } + } + } + + spt = can_update_spt(sampl_pt, best_tseg, &tseg1, &tseg2); + + /* check for sjw user settings */ + /* bt->sjw is at least 1 -> sanitize upper bound to sjw_max */ + if(sjw > SJW_MAX) + { + sjw = SJW_MAX; + } + /* bt->sjw must not be higher than tseg2 */ + if(tseg2 < (int32_t)sjw) + { + sjw = (uint32_t)tseg2; + } + + /* real bit-rate */ + u32BaudRate = (uint32_t)(int32_t)(clock_freq / (int32_t)(best_brp * (tseg1 + tseg2 + 1))); + + tCAN->BTIME = (((uint32_t)tseg2 - 1UL) << CAN_BTIME_TSEG2_Pos) | (((uint32_t)tseg1 - 1UL) << CAN_BTIME_TSEG1_Pos) | + (((uint32_t)best_brp - 1UL) & CAN_BTIME_BRP_Msk) | (sjw << CAN_BTIME_SJW_Pos); + + + tCAN->BRPE = (((uint32_t)best_brp - 1UL) >> 6) & 0x0FUL; + + /* DEBUG_PRINTF("\n bitrate = %d \n", CAN_GetCANBitRate(tCAN)); */ + + CAN_LeaveInitMode(tCAN); + + return u32BaudRate; +} + +/** + * @brief The function is used to disable all CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * + * @return None + * + * @details No Status Change Interrupt and Error Status Interrupt will be generated. + */ + + +void CAN_Close(CAN_T *tCAN) +{ + CAN_DisableInt(tCAN, (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)); +} + + + +/** + * @brief Set CAN operation mode and target baud-rate. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * @param[in] u32Mode The CAN operation mode. Valid values are: + * - \ref CAN_NORMAL_MODE Normal operation. + * - \ref CAN_BASIC_MODE Basic mode. + * @return u32CurrentBitRate Real baud-rate value. + * + * @details Set bus timing parameter according current clock and target baud-rate. + * In Basic mode, IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. + */ +uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode) +{ + uint32_t u32CurrentBitRate; + + u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate); + + if(u32Mode == CAN_BASIC_MODE) + { + CAN_EnterTestMode(tCAN, (uint8_t)CAN_TEST_BASIC_Msk); + } + + return u32CurrentBitRate; +} + +/** + * @brief The function is used to configure a transmit object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE No useful interface. + * @retval TRUE Config message object success. + * + * @details The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM. + * They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission. + */ +int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + uint8_t u8MsgIfNum; + + if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U) + { + return (int32_t)FALSE; + } + + /* update the contents needed for transmission*/ + tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + tCAN->IF[u8MsgIfNum].ARB1 = 0UL; + tCAN->IF[u8MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x7FFUL) << 2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk; + } + else + { + /* extended ID*/ + tCAN->IF[u8MsgIfNum].ARB1 = (pCanMsg->Id) & 0xFFFFUL; + tCAN->IF[u8MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x1FFF0000UL) >> 16) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk; + } + + if(pCanMsg->FrameType) + { + tCAN->IF[u8MsgIfNum].ARB2 |= CAN_IF_ARB2_DIR_Msk; + } + else + { + tCAN->IF[u8MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk); + } + + + tCAN->IF[u8MsgIfNum].DAT_A1 = ((uint32_t)pCanMsg->Data[1] << 8) | (uint32_t)pCanMsg->Data[0]; + tCAN->IF[u8MsgIfNum].DAT_A2 = ((uint32_t)pCanMsg->Data[3] << 8) | (uint32_t)pCanMsg->Data[2]; + tCAN->IF[u8MsgIfNum].DAT_B1 = ((uint32_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]; + tCAN->IF[u8MsgIfNum].DAT_B2 = ((uint32_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]; + + tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk; + tCAN->IF[u8MsgIfNum].CREQ = 1UL + u32MsgNum; + + ReleaseIF(tCAN, (uint32_t)u8MsgIfNum); + + return (int32_t)TRUE; +} + +/** + * @brief Set transmit request bit. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * + * @return TRUE: Start transmit message. + * + * @details If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst (IFn_MCON[8]) will be ignored. + */ +int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum) +{ + uint8_t u8MsgIfNum; + + if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U) + { + return (int32_t)FALSE; + } + + tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk); + + /* read the message contents*/ + tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk + | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + + tCAN->IF[u8MsgIfNum].CREQ = 1UL + u32MsgNum; + + while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + tCAN->IF[u8MsgIfNum].CREQ = 1UL + u32MsgNum; + + ReleaseIF(tCAN, (uint32_t)u8MsgIfNum); + + return (int32_t)TRUE; +} + +/** + * @brief Enable CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Mask Interrupt Mask. Valid values are: + * - \ref CAN_CON_IE_Msk Module interrupt enable. + * - \ref CAN_CON_SIE_Msk Status change interrupt enable. + * - \ref CAN_CON_EIE_Msk Error interrupt enable. + * + * @return None + * + * @details The application software has two possibilities to follow the source of a message interrupt. + * First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register. + */ +void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask) +{ + tCAN->CON = (tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)) | + (u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)); +} + +/** + * @brief Disable CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Mask Interrupt Mask. (CAN_CON_IE_Msk / CAN_CON_SIE_Msk / CAN_CON_EIE_Msk). + * + * @return None + * + * @details The interrupt remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset. + */ +void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask) +{ + tCAN->CON = tCAN->CON & ~((u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk))); +} + + +/** + * @brief The function is used to configure a receive message object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure a receive message object success. + * + * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13]) + * will be set when a received Data Frame is accepted and stored in the Message Object. + */ +int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID) +{ + uint32_t u32TimeOutCount = 0UL; + + while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)TRUE) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + return (int32_t)FALSE; + } + } + + return (int32_t)TRUE; +} + +/** + * @brief The function is used to configure a receive message object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * @param[in] u32IDMask Specifies the identifier mask used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure a receive message object success. + * + * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13]) + * will be set when a received Data Frame is accepted and stored in the Message Object. + */ +int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask) +{ + uint32_t u32TimeOutCount = 0UL; + + while(CAN_SetRxMsgObjAndMsk(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, u32IDMask, (uint8_t)TRUE) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + return (int32_t)FALSE; + } + } + + return (int32_t)TRUE; +} + +/** + * @brief The function is used to configure several receive message objects. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum The starting MSG RAM number(0 ~ 31). + * @param[in] u32MsgCount the number of MSG RAM of the FIFO. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure receive message objects success. + * + * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception + * and transmission by buffering the data to be transferred. + */ +int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID) +{ + uint32_t i = 0UL; + uint32_t u32TimeOutCount; + uint32_t u32EOB_Flag = 0UL; + + for(i = 1UL; i < u32MsgCount; i++) + { + u32TimeOutCount = 0UL; + + u32MsgNum += (i - 1UL); + + if(i == u32MsgCount) + { + u32EOB_Flag = 1UL; + } + + while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)u32EOB_Flag) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + return (int32_t)FALSE; + } + } + } + + return (int32_t)TRUE; +} + + +/** + * @brief Send CAN message. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE 1. When operation in basic mode: Transmit message time out. \n + * 2. When operation in normal mode: No useful interface. \n + * @retval TRUE Transmit Message success. + * + * @details The receive/transmit priority for the Message Objects is attached to the message number. + * Message Object 1 has the highest priority, while Message Object 32 has the lowest priority. + */ +int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + uint32_t cond0, cond1; + + cond0 = tCAN->CON & CAN_CON_TEST_Msk; + cond1 = tCAN->TEST & CAN_TEST_BASIC_Msk; + if(cond0 && cond1) + { + return (CAN_BasicSendMsg(tCAN, pCanMsg)); + } + else + { + if(CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == (int32_t)FALSE) + { + return (int32_t)FALSE; + } + CAN_TriggerTxMsg(tCAN, u32MsgNum); + } + + return (int32_t)TRUE; +} + + +/** + * @brief Gets the message, if received. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE No any message received. + * @retval TRUE Receive Message success. + * + * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception + * and transmission by buffering the data to be transferred. + */ +int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + uint32_t cond0, cond1; + + cond0 = tCAN->CON & CAN_CON_TEST_Msk; + cond1 = tCAN->TEST & CAN_TEST_BASIC_Msk; + + if(cond0 && cond1) + { + return (CAN_BasicReceiveMsg(tCAN, pCanMsg)); + } + else + { + return CAN_ReadMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)TRUE, pCanMsg); + } +} + +/** + * @brief Clear interrupt pending bit. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * + * @return None + * + * @details An interrupt remains pending until the application software has cleared it. + */ +void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum) +{ + uint32_t u32MsgIfNum; + + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2UL) + { + u32MsgIfNum = 0UL; + } + + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + tCAN->IF[u32MsgIfNum].CREQ = 1UL + u32MsgNum; + + ReleaseIF(tCAN, u32MsgIfNum); +} + +/**@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CAN_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_clk.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_clk.c new file mode 100644 index 0000000000..87018d13af --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_clk.c @@ -0,0 +1,1406 @@ +/**************************************************************************//** + * @file clk.c + * @version V3.00 + * @brief M2354 series Clock Controller (CLK) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + + +/** + * @brief Disable frequency output function + * @param None + * @return None + * @details This function disable frequency output function. + */ +void CLK_DisableCKO(void) +{ + /* Disable CKO clock source */ + CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk); +} + + +/** + * @brief This function enable frequency divider module clock. + * enable frequency divider clock function and configure frequency divider. + * @param[in] u32ClkSrc is frequency divider function clock source. Including : + * - \ref CLK_CLKSEL1_CLKOSEL_HXT + * - \ref CLK_CLKSEL1_CLKOSEL_LXT + * - \ref CLK_CLKSEL1_CLKOSEL_HCLK + * - \ref CLK_CLKSEL1_CLKOSEL_HIRC + * @param[in] u32ClkDiv is divider output frequency selection. + * @param[in] u32ClkDivBy1En is frequency divided by one enable. + * @return None + * + * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. + * The formula is: + * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) + * This function is just used to set CKO clock. + * User must enable I/O for CKO clock output pin by themselves. + */ +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) +{ + /* CKO = clock source / 2^(u32ClkDiv + 1) */ + CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos); + + /* Enable CKO clock source */ + CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk; + + /* Select CKO clock source */ + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | (u32ClkSrc); + +} + +/** + * @brief Enter to Power-down mode + * @param None + * @return None + * @details This function is used to let system enter to Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_PowerDown(void) +{ + /* Set the processor uses deep sleep as its low power mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Set system Power-down enabled*/ + CLK->PWRCTL |= CLK_PWRCTL_PDEN_Msk; + + /* Chip enter Power-down mode after CPU run WFI instruction */ + __WFI(); +} + + +/** + * @brief Enter to Idle mode + * @param None + * @return None + * @details This function let system enter to Idle mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_Idle(void) +{ + /* Set the processor uses sleep as its low power mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + /* Set chip in idle mode because of WFI command */ + CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk; + + /* Chip enter idle mode after CPU run WFI instruction */ + __WFI(); +} + + +/** + * @brief Get external high speed crystal clock frequency + * @param None + * @return External high frequency crystal frequency + * @details This function get external high frequency crystal frequency. The frequency unit is Hz. + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +uint32_t CLK_GetHXTFreq(void) +{ + uint32_t u32Freq = 0UL; + uint32_t u32HXTEN = CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk; + + if(u32HXTEN) + { + u32Freq = __HXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} +#endif + +/** + * @brief Get external low speed crystal clock frequency + * @param None + * @return External low speed crystal clock frequency + * @details This function get external low frequency crystal frequency. The frequency unit is Hz. + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +uint32_t CLK_GetLXTFreq(void) +{ + uint32_t u32Freq = 0UL; + uint32_t u32LXTEN = CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk; + + if(u32LXTEN) + { + u32Freq = __LXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} +#endif + +/** + * @brief Get HCLK frequency + * @param None + * @return HCLK frequency + * @details This function get HCLK frequency. The frequency unit is Hz. + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +uint32_t CLK_GetHCLKFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} +#endif + +/** + * @brief Get PCLK0 frequency + * @param None + * @return PCLK0 frequency + * @details This function get PCLK0 frequency. The frequency unit is Hz. + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +uint32_t CLK_GetPCLK0Freq(void) +{ + SystemCoreClockUpdate(); + return (SystemCoreClock); +} +#endif + +/** + * @brief Get PCLK1 frequency + * @param None + * @return PCLK1 frequency + * @details This function get PCLK1 frequency. The frequency unit is Hz. + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +uint32_t CLK_GetPCLK1Freq(void) +{ + SystemCoreClockUpdate(); + return (SystemCoreClock); +} +#endif + +/** + * @brief Get CPU frequency + * @param None + * @return CPU frequency + * @details This function get CPU frequency. The frequency unit is Hz. + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +uint32_t CLK_GetCPUFreq(void) +{ + uint32_t u32Freq, u32HclkSrc, u32HclkDiv; + uint32_t au32ClkTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, __HIRC48, __MIRC, __HIRC}; + uint32_t u32PllReg, u32FIN, u32NF, u32NR, u32NO; + uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U}; + uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk; + + /* Update PLL Clock */ + u32PllReg = CLK->PLLCTL; + + if(u32PllReg & CLK_PLLCTL_PD_Msk) + { + PllClock = 0UL; /* PLL is in power down mode */ + } + else /* PLL is in normal mode */ + { + + /* PLL source clock */ + if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk) + { + u32FIN = __HIRC; /* PLL source clock from HIRC */ + } + else + { + u32FIN = __HXT; /* PLL source clock from HXT */ + } + + /* Calculate PLL frequency */ + if(u32PllReg & CLK_PLLCTL_BP_Msk) + { + PllClock = u32FIN; /* PLL is in bypass mode */ + } + else + { + /* PLL is output enabled in normal work mode */ + u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)]; + u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL; + u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL; + + /* u32FIN is shifted 2 bits to avoid overflow */ + PllClock = (((u32FIN >> 2) * (u32NF << 1)) / (u32NR * u32NO) << 2); + } + } + + /* HCLK clock source */ + u32HclkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk; + + if(u32HclkSrc == CLK_CLKSEL0_HCLKSEL_LXT) + { + + if(u32RTCCKEN == 0UL) + { + CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */ + } + + if(RTC->LXTCTL & RTC_LXTCTL_C32KSEL_Msk) + { + u32Freq = __LIRC32; /* LXT clock source is LIRC32 */ + } + else + { + u32Freq = __LXT; /* LXT clock source is external LXT */ + } + + if(u32RTCCKEN == 0UL) + { + CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */ + } + + } + else if(u32HclkSrc == CLK_CLKSEL0_HCLKSEL_PLL) + { + u32Freq = PllClock;/* Use PLL clock */ + } + else + { + u32Freq = au32ClkTbl[u32HclkSrc]; /* Use the clock sources directly */ + } + + /* HCLK clock source divider */ + u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL; + + /* Update System Core Clock */ + SystemCoreClock = u32Freq / u32HclkDiv; + + /* Update Cycles per micro second */ + CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL; + + return SystemCoreClock; +} +#endif + +/** + * @brief Set HCLK frequency + * @param[in] u32Hclk is HCLK frequency. + * The range of u32Hclk is 24 MHz ~ 96 MHz. + * @return HCLK frequency + * @details This function is used to set HCLK frequency by using PLL. \n + * Power level is also set according to HCLK frequency. The frequency unit is Hz. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_SetCoreClock(uint32_t u32Hclk) +{ + uint32_t u32HIRCSTB; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + + /* Check HCLK frequency range */ + if(u32Hclk > FREQ_96MHZ) + { + u32Hclk = FREQ_96MHZ; + } + else if(u32Hclk < FREQ_24MHZ) + { + u32Hclk = FREQ_24MHZ; + } + + /* Switch HCLK clock source to HIRC clock for safe */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk; + CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk); + + /* Configure PLL setting if HXT clock is stable */ + if(CLK->STATUS & CLK_STATUS_HXTSTB_Msk) + { + u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk); + } + /* Configure PLL setting if HXT clock is not stable */ + else + { + u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk); + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + } + + /* Select HCLK clock source to PLL, + select HCLK clock source divider as 1, + adjust power level and update system core clock + */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL)); + + /* Disable HIRC if HIRC is disabled before setting core clock */ + if(u32HIRCSTB == 0UL) + { + CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; + } + + /* Return actually HCLK frequency is PLL frequency divide 1 */ + return u32Hclk; +} + + +/** + * @brief Set HCLK clock source and HCLK clock divider + * @param[in] u32ClkSrc is HCLK clock source. Including : + * - \ref CLK_CLKSEL0_HCLKSEL_HXT + * - \ref CLK_CLKSEL0_HCLKSEL_LXT + * - \ref CLK_CLKSEL0_HCLKSEL_PLL + * - \ref CLK_CLKSEL0_HCLKSEL_LIRC + * - \ref CLK_CLKSEL0_HCLKSEL_HIRC48 + * - \ref CLK_CLKSEL0_HCLKSEL_MIRC + * - \ref CLK_CLKSEL0_HCLKSEL_HIRC + * @param[in] u32ClkDiv is HCLK clock divider. Including : + * - \ref CLK_CLKDIV0_HCLK(x) + * @return None + * @details This function set HCLK clock source and HCLK clock divider. \n + * Power level and flash access cycle are also set according to HCLK operation frequency. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32HIRCSTB; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + + /* Switch to HIRC for safe. Avoid HCLK too high when applying new divider. */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk; + + /* Switch to power level 0 for safe */ + while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk); + SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL0; + while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk); + + /* Set Flash Access Cycle to 4 for safe */ + FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (4); + + /* Apply new Divider */ + CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv; + + /* Switch HCLK to new HCLK source */ + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc; + + /* Update System Core Clock */ + SystemCoreClockUpdate(); + + /* Set power level according to new HCLK source */ + while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk); + if( (SystemCoreClock>FREQ_48MHZ) && SystemCoreClock<=FREQ_84MHZ ) + { + SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL1; + } + else if( (SystemCoreClock>FREQ_4MHZ) && SystemCoreClock<=FREQ_48MHZ ) + { + SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL2; + } + if( SystemCoreClock<=FREQ_4MHZ ) + { + SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | SYS_PLCTL_PLSEL_PL3; + } + while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk); + + /* Set Flash Access Cycle */ + if( (SystemCoreClock>=FREQ_50MHZ) && SystemCoreClockCYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (3); + } + else if( (SystemCoreClock>=FREQ_25MHZ) && SystemCoreClockCYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (2); + } + if( SystemCoreClockCYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | (1); + } + + /* Disable HIRC if HIRC is disabled before switching HCLK source */ + if(u32HIRCSTB == 0UL) + { + CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; + } +} +/** + * @brief This function set selected module clock source and module clock divider + * @param[in] u32ModuleIdx is module index. + * @param[in] u32ClkSrc is module clock source. + * @param[in] u32ClkDiv is module clock divider. + * @return None + * @details Valid parameter combinations listed in following table: + * + * |Module index |Clock source |Divider | + * | :---------------- | :------------------------------------ | :----------------------- | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HXT |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_PLL |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HCLK |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HIRC |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x | + * |\ref LCD_MODULE |\ref CLK_CLKSEL1_LCDSEL_LIRC | x | + * |\ref LCD_MODULE |\ref CLK_CLKSEL1_LCDSEL_LXT | x | + * |\ref LCDCP_MODULE |\ref CLK_CLKSEL1_LCDCPSEL_HIRC | x | + * |\ref LCDCP_MODULE |\ref CLK_CLKSEL1_LCDCPSEL_MIRC | x | + * |\ref EWDT_MODULE |\ref CLK_CLKSEL1_EWDTSEL_LXT | x | + * |\ref EWDT_MODULE |\ref CLK_CLKSEL1_EWDTSEL_HCLK_DIV2048 | x | + * |\ref EWDT_MODULE |\ref CLK_CLKSEL1_EWDTSEL_LIRC | x | + * |\ref EWWDT_MODULE |\ref CLK_CLKSEL1_EWWDTSEL_HCLK_DIV2048 | x | + * |\ref EWWDT_MODULE |\ref CLK_CLKSEL1_EWWDTSEL_LIRC | x | + * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT_TRG | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT_TRG | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT_TRG | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT_TRG | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x | + * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_HXT | x | + * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_LXT | x | + * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_PCLK0 | x | + * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_EXT_TRG | x | + * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_MIRC | x | + * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_LIRC | x | + * |\ref TMR4_MODULE |\ref CLK_CLKSEL3_TMR4SEL_HIRC | x | + * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_HXT | x | + * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_LXT | x | + * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_PCLK0 | x | + * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_EXT_TRG | x | + * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_MIRC | x | + * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_LIRC | x | + * |\ref TMR5_MODULE |\ref CLK_CLKSEL3_TMR5SEL_HIRC | x | + * |\ref UART0_MODULE |\ref CLK_CLKSEL2_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL2_UART0SEL_PLL |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL2_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL2_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL2_UART0SEL_PCLK0 |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL2_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL2_UART1SEL_PLL |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL2_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL2_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL2_UART1SEL_PCLK1 |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL2_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL2_UART2SEL_PLL |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL2_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL2_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL2_UART2SEL_PCLK0 |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL2_UART3SEL_HXT |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL2_UART3SEL_PLL |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL2_UART3SEL_LXT |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL2_UART3SEL_HIRC |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL2_UART3SEL_PCLK1 |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HXT |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PLL |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LXT |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HIRC |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PCLK0 |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HXT |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PLL |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LXT |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HIRC |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PCLK1 |\ref CLK_CLKDIV4_UART5(x) | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x | + * |\ref RTC_MODULE |\ref RTC_LXTCTL_RTCCKSEL_LXT | x | + * |\ref RTC_MODULE |\ref RTC_LXTCTL_RTCCKSEL_LIRC | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PCLK0 | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HXT | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PLL | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0 | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HIRC | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK1 | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK0 | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK1 | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HXT | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PLL | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PCLK0 | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HIRC | x | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK1 |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK0 |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) | + * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) | + * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) | + * |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) | + * |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) | + * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) | + * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) | + */ +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32Sel = 0UL, u32Div = 0UL; + uint32_t au32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL}; + uint32_t au32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL}; + uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk; + + if( u32ModuleIdx == RTC_MODULE ) /* RTC clock source configuration */ + { + if(u32RTCCKEN == 0UL) + { + CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */ + } + + /* Select RTC clock source */ + RTC->LXTCTL = (RTC->LXTCTL & (~RTC_LXTCTL_RTCCKSEL_Msk)) | (u32ClkSrc); + + if(u32RTCCKEN == 0UL) + { + CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */ + } + + } + else /* Others clock source configuration */ + { + if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + u32Div = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); + /* Apply new divider */ + M32(u32Div) = (M32(u32Div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv; + } + + if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32Sel = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); + /* Set new clock selection setting */ + M32(u32Sel) = (M32(u32Sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc; + } + } +} + +/** + * @brief Set SysTick clock source + * @param[in] u32ClkSrc is module clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * @return None + * @details This function set SysTick clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc) +{ + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; +} + +/** + * @brief Enable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * - \ref CLK_PWRCTL_HIRC48EN_Msk + * - \ref CLK_PWRCTL_MIRC1P2MEN_Msk + * - \ref CLK_PWRCTL_MIRCEN_Msk + * @return None + * @details This function enable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL |= u32ClkMask; +} + +/** + * @brief Disable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * - \ref CLK_PWRCTL_HIRC48EN_Msk + * - \ref CLK_PWRCTL_MIRC1P2MEN_Msk + * - \ref CLK_PWRCTL_MIRCEN_Msk + * @return None + * @details This function disable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL &= ~u32ClkMask; +} + +/** + * @brief Enable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA0_MODULE + * - \ref PDMA1_MODULE + * - \ref ISP_MODULE + * - \ref EBI_MODULE + * - \ref SDH0_MODULE + * - \ref CRC_MODULE + * - \ref CRPT_MODULE + * - \ref KS_MODULE + * - \ref TRACE_MODULE + * - \ref USBH_MODULE + * - \ref SRAM0_MODULE + * - \ref SRAM1_MODULE + * - \ref SRAM2_MODULE + * - \ref GPA_MODULE + * - \ref GPB_MODULE + * - \ref GPC_MODULE + * - \ref GPD_MODULE + * - \ref GPE_MODULE + * - \ref GPF_MODULE + * - \ref GPG_MODULE + * - \ref GPH_MODULE + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref EWDT_MODULE + * - \ref EWWDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref TMR4_MODULE + * - \ref TMR5_MODULE + * - \ref CLKO_MODULE + * - \ref ACMP01_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref TAMPER_MODULE + * - \ref CAN0_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref EADC_MODULE + * - \ref I2S0_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref USCI0_MODULE + * - \ref USCI1_MODULE + * - \ref DAC_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref QEI0_MODULE + * - \ref LCD_MODULE + * - \ref LCDCP_MODULE + * - \ref TRNG_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * @return None + * @details This function is used to enable module clock. + */ +void CLK_EnableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + + u32TmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32TmpAddr = (uint32_t)&CLK->AHBCLK; + u32TmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); + + *(volatile uint32_t *)u32TmpAddr |= u32TmpVal; +} + +/** + * @brief Disable module clock + * @param[in] u32ModuleIdx is module index + * - \ref PDMA0_MODULE + * - \ref PDMA1_MODULE + * - \ref ISP_MODULE + * - \ref EBI_MODULE + * - \ref SDH0_MODULE + * - \ref CRC_MODULE + * - \ref CRPT_MODULE + * - \ref KS_MODULE + * - \ref TRACE_MODULE + * - \ref USBH_MODULE + * - \ref SRAM0_MODULE + * - \ref SRAM1_MODULE + * - \ref SRAM2_MODULE + * - \ref GPA_MODULE + * - \ref GPB_MODULE + * - \ref GPC_MODULE + * - \ref GPD_MODULE + * - \ref GPE_MODULE + * - \ref GPF_MODULE + * - \ref GPG_MODULE + * - \ref GPH_MODULE + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref EWDT_MODULE + * - \ref EWWDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref TMR4_MODULE + * - \ref TMR5_MODULE + * - \ref CLKO_MODULE + * - \ref ACMP01_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref TAMPER_MODULE + * - \ref CAN0_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref EADC_MODULE + * - \ref I2S0_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref USCI0_MODULE + * - \ref USCI1_MODULE + * - \ref DAC_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref QEI0_MODULE + * - \ref LCD_MODULE + * - \ref LCDCP_MODULE + * - \ref TRNG_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * @return None + * @details This function is used to disable module clock. + */ +void CLK_DisableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + + u32TmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32TmpAddr = (uint32_t)&CLK->AHBCLK; + u32TmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); + + *(uint32_t *)u32TmpAddr &= u32TmpVal; +} + + +/** + * @brief Set PLL frequency + * @param[in] u32PllClkSrc is PLL clock source. Including : + * - \ref CLK_PLLCTL_PLLSRC_HXT + * - \ref CLK_PLLCTL_PLLSRC_HIRC + * @param[in] u32PllFreq is PLL frequency. The range of u32PllFreq is 24 MHz ~ 200 MHz. + * @return PLL frequency + * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq) +{ + uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32PllClk; + uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR; + + /* Disable PLL first to avoid unstable when setting PLL */ + CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; + + /* PLL source clock is from HXT */ + if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) + { + /* Enable HXT clock */ + CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; + + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + + /* Select PLL source clock from HXT */ + u32PllSrcClk = __HXT; + } + + /* PLL source clock is from HIRC */ + else + { + /* Enable HIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + + /* Select PLL source clock from HIRC */ + u32PllSrcClk = __HIRC; + } + + /* Check PLL frequency range */ + /* Constraint 1: 24MHz < FOUT < 200MHz */ + if((u32PllFreq <= FREQ_200MHZ) && (u32PllFreq >= FREQ_24MHZ)) + { + + /* Select "NO" according to request frequency */ + if((u32PllFreq < FREQ_48MHZ) && (u32PllFreq >= FREQ_24MHZ)) + { + u32NO = 3UL; + u32PllFreq = u32PllFreq << 2; + } + else if((u32PllFreq < FREQ_96MHZ) && (u32PllFreq >= FREQ_48MHZ)) + { + u32NO = 1UL; + u32PllFreq = u32PllFreq << 1; + } + else + { + u32NO = 0UL; + } + + /* u32NR start from 3 to avoid calculation overflow */ + u32NR = 3UL; + + /* Find best solution */ + u32Min = (uint32_t) - 1; /* initial u32Min to max value of uint32_t (0xFFFFFFFF) */ + u32MinNR = 0UL; + u32MinNF = 0UL; + + for(; u32NR <= 32UL; u32NR++) /* max NR = 32 since NR = INDIV+1 and INDIV = 0~31 */ + { + u32Tmp = u32PllSrcClk / u32NR; /* FREF = FIN/NR */ + if((u32Tmp >= FREQ_2MHZ) && (u32Tmp <= FREQ_8MHZ)) /* Constraint 2: 2MHz < FREF < 8MHz. */ + { + for(u32NF = 2UL; u32NF <= 513UL; u32NF++) /* NF = 2~513 since NF = FBDIV+2 and FBDIV = 0~511 */ + { + u32Tmp2 = (u32Tmp * u32NF) << 1; /* FVCO = FREF*2*NF */ + if((u32Tmp2 >= FREQ_96MHZ) && (u32Tmp2 <= FREQ_200MHZ)) /* Constraint 3: 96MHz < FVCO < 200MHz */ + { + u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2; + if(u32Tmp3 < u32Min) + { + u32Min = u32Tmp3; + u32MinNR = u32NR; + u32MinNF = u32NF; + + /* Break when get good results */ + if(u32Min == 0UL) + { + break; + } + } + } + } + } + } + + /* Enable and apply new PLL setting. */ + CLK->PLLCTL = u32PllClkSrc | + (u32NO << CLK_PLLCTL_OUTDIV_Pos) | + ((u32MinNR - 1UL) << CLK_PLLCTL_INDIV_Pos) | + ((u32MinNF - 2UL) << CLK_PLLCTL_FBDIV_Pos); + + /* Actual PLL output clock frequency. FOUT = (FIN/NR)*2*NF*(1/NO) */ + u32PllClk = u32PllSrcClk / ((u32NO + 1UL) * u32MinNR) * (u32MinNF << 1); + + } + else + { + /* Apply default PLL setting and return */ + CLK->PLLCTL = u32PllClkSrc | CLK_PLLCTL_48MHz_HXT; + + /* Actual PLL output clock frequency */ + u32PllClk = FREQ_48MHZ; + } + + /* Wait for PLL clock stable */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + + /* Return actual PLL output clock frequency */ + return u32PllClk; +} + +/** + * @brief Disable PLL + * @param None + * @return None + * @details This function set PLL in Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisablePLL(void) +{ + CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; +} + +/** + * @brief This function check selected clock source status + * @param[in] u32ClkMask is selected clock source. Including : + * - \ref CLK_STATUS_HXTSTB_Msk + * - \ref CLK_STATUS_LXTSTB_Msk + * - \ref CLK_STATUS_HIRCSTB_Msk + * - \ref CLK_STATUS_LIRCSTB_Msk + * - \ref CLK_STATUS_PLLSTB_Msk + * - \ref CLK_STATUS_HIRC48STB_Msk + * - \ref CLK_STATUS_EXTLXTSTB_Msk + * - \ref CLK_STATUS_LIRC32STB_Msk + * - \ref CLK_STATUS_MIRCSTB_Msk + * @retval 0 clock is not stable + * @retval 1 clock is stable + * @details To wait for clock ready by specified clock source stable flag or timeout (~500ms) + */ +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask) +{ + int32_t i32TimeOutCnt = 2400000; + uint32_t u32Ret = 1U; + + while((CLK->STATUS & u32ClkMask) != u32ClkMask) + { + if(i32TimeOutCnt-- <= 0) + { + u32Ret = 0U; + break; + } + } + return u32Ret; +} + +/** + * @brief Enable System Tick counter + * @param[in] u32ClkSrc is System Tick clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK + * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF. + * @return None + * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; + + /* Set System Tick clock source */ + if(u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK) + { + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; + } + else + { + CLK->AHBCLK |= CLK_AHBCLK_EXSTCKEN_Msk; + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; + } + + /* Set System Tick reload value */ + SysTick->LOAD = u32Count; + + /* Clear System Tick current value and counter flag */ + SysTick->VAL = 0UL; + + /* Set System Tick interrupt enabled and counter enabled */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief Disable System Tick counter + * @param None + * @return None + * @details This function disable System Tick counter. + */ +void CLK_DisableSysTick(void) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; +} + +/** + * @brief Power-down mode selected + * @param[in] u32PDMode is power down mode index. Including : + * - \ref CLK_PMUCTL_PDMSEL_PD + * - \ref CLK_PMUCTL_PDMSEL_LLPD + * - \ref CLK_PMUCTL_PDMSEL_FWPD + * - \ref CLK_PMUCTL_PDMSEL_ULLPD + * - \ref CLK_PMUCTL_PDMSEL_SPD + * - \ref CLK_PMUCTL_PDMSEL_DPD + * @return None + * @details This function is used to set power-down mode. + */ +void CLK_SetPowerDownMode(uint32_t u32PDMode) +{ + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); + CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_PDMSEL_Msk)) | (u32PDMode); +} + +/** + * @brief Set Wake-up pin trigger type at Deep Power down mode + * @param[in] u32TriggerType Wake-up pin trigger type + * - \ref CLK_DPDWKPIN_RISING + * - \ref CLK_DPDWKPIN_FALLING + * - \ref CLK_DPDWKPIN_BOTHEDGE + * - \ref CLK_DPDWKPIN1_RISING + * - \ref CLK_DPDWKPIN1_FALLING + * - \ref CLK_DPDWKPIN1_BOTHEDGE + * - \ref CLK_DPDWKPIN2_RISING + * - \ref CLK_DPDWKPIN2_FALLING + * - \ref CLK_DPDWKPIN2_BOTHEDGE + * - \ref CLK_DPDWKPIN3_RISING + * - \ref CLK_DPDWKPIN3_FALLING + * - \ref CLK_DPDWKPIN3_BOTHEDGE + * - \ref CLK_DPDWKPIN4_RISING + * - \ref CLK_DPDWKPIN4_FALLING + * - \ref CLK_DPDWKPIN4_BOTHEDGE + * @return None + * @details This function is used to enable Wake-up pin trigger type. + */ + +void CLK_EnableDPDWKPin(uint32_t u32TriggerType) +{ + uint32_t u32Pin1, u32Pin2, u32Pin3, u32Pin4; + + u32Pin1 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN1_Pos); + u32Pin2 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN2_Pos); + u32Pin3 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN3_Pos); + u32Pin4 = (((u32TriggerType) & 0x03UL) >> CLK_PMUCTL_WKPINEN4_Pos); + + while(CLK->PMUCTL & CLK_PMUCTL_WRBUSY_Msk); + + if(u32Pin1) + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN1_Msk)) | u32TriggerType; + } + else if(u32Pin2) + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN2_Msk)) | u32TriggerType; + } + else if(u32Pin3) + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN3_Msk)) | u32TriggerType; + } + else if(u32Pin4) + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN4_Msk)) | u32TriggerType; + } + else + { + CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType; + } +} + +/** + * @brief Get power manager wake up source + * @param[in] None + * @return None + * @details This function get power manager wake up source. + */ + +uint32_t CLK_GetPMUWKSrc(void) +{ + return (CLK->PMUSTS); +} + +/** + * @brief Set specified GPIO as wake up source at Standby Power-down mode + * @param[in] u32Port GPIO port. It could be 0~3. + * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15. + * @param[in] u32TriggerType Wake-up pin trigger type + * - \ref CLK_SPDWKPIN_RISING + * - \ref CLK_SPDWKPIN_FALLING + * @param[in] u32DebounceEn Standby Power-down mode wake-up pin de-bounce function + * - \ref CLK_SPDWKPIN_DEBOUNCEEN + * - \ref CLK_SPDWKPIN_DEBOUNCEDIS + * @return None + * @details This function is used to set specified GPIO as wake up source at Standby Power-down mode. + */ + +void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn) +{ + uint32_t u32TmpAddr = 0UL; + uint32_t u32TmpVal = 0UL; + + /* GPx Stand-by Power-down Wake-up Pin Select */ + u32TmpAddr = (uint32_t)&CLK->PASWKCTL; + u32TmpAddr += (0x4UL * u32Port); + + u32TmpVal = inpw((uint32_t *)u32TmpAddr); + u32TmpVal = (u32TmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) | + (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE; + outpw((uint32_t *)u32TmpAddr, u32TmpVal); +} + +/** + * @brief Get PLL clock frequency + * @param None + * @return PLL frequency + * @details This function get PLL frequency. The frequency unit is Hz. + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +uint32_t CLK_GetPLLClockFreq(void) +{ + uint32_t u32PllFreq = 0UL, u32PllReg; + uint32_t u32FIN, u32NF, u32NR, u32NO; + uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U}; + + u32PllReg = CLK->PLLCTL; + + if(u32PllReg & CLK_PLLCTL_PD_Msk) + { + u32PllFreq = 0UL; /* PLL is in power down mode or fix low */ + } + else /* PLL is in normal mode */ + { + /* PLL source clock */ + if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk) + { + u32FIN = __HIRC; /* PLL source clock from HIRC */ + } + else + { + u32FIN = __HXT; /* PLL source clock from HXT */ + } + + /* Calculate PLL frequency */ + if(u32PllReg & CLK_PLLCTL_BP_Msk) + { + u32PllFreq = u32FIN; /* PLL is in bypass mode */ + } + else + { + /* PLL is output enabled in normal work mode */ + u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)]; + u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL; + u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL; + + /* u32FIN is shifted 2 bits to avoid overflow */ + u32PllFreq = (((u32FIN >> 2) * (u32NF << 1)) / (u32NR * u32NO) << 2); + } + } + + return u32PllFreq; +} +#endif + +/** + * @brief Get selected module clock source + * @param[in] u32ModuleIdx is module index. + * - \ref SDH0_MODULE + * - \ref USBH_MODULE + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref EWDT_MODULE + * - \ref EWWDT_MODULE + * - \ref LCD_MODULE + * - \ref LCDCP_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref TMR4_MODULE + * - \ref TMR5_MODULE + * - \ref CLKO_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref I2S0_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * @return Selected module clock source setting + * @details This function get selected module clock source. + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + uint32_t au32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL}; + uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk; + + /* Get clock source selection setting */ + if(u32ModuleIdx == RTC_MODULE) + { + if(u32RTCCKEN == 0UL) + { + CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */ + } + + u32TmpVal = ((RTC->LXTCTL & RTC_LXTCTL_RTCCKSEL_Msk) >> RTC_LXTCTL_RTCCKSEL_Pos); + + if(u32RTCCKEN == 0UL) + { + CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */ + } + + } + else if(u32ModuleIdx == EPWM0_MODULE) + { + u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos); + } + else if(u32ModuleIdx == EPWM1_MODULE) + { + u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos); + } + else if(u32ModuleIdx == BPWM0_MODULE) + { + u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos); + } + else if(u32ModuleIdx == BPWM1_MODULE) + { + u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos); + } + else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32TmpAddr = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); + + /* Get clock source selection setting */ + u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx)); + } + + return u32TmpVal; +} +#endif + +/** + * @brief Get selected module clock divider number + * @param[in] u32ModuleIdx is module index. + * - \ref SDH0_MODULE + * - \ref USBH_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref EADC_MODULE + * @return Selected module clock divider number setting + * @details This function get selected module clock divider number. + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + uint32_t au32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL}; + + if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + u32TmpAddr = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); + /* Get clock divider number setting */ + u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx)); + } + + return u32TmpVal; +} +#endif + + +/**@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CLK_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_crc.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_crc.c new file mode 100644 index 0000000000..3375ecf115 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_crc.c @@ -0,0 +1,98 @@ +/**************************************************************************//** + * @file crc.c + * @version V3.00 + * @brief Cyclic Redundancy Check(CRC) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions + @{ +*/ + +/** + * @brief CRC Open + * + * @param[in] u32Mode CRC operation polynomial mode. Valid values are: + * - \ref CRC_CCITT + * - \ref CRC_8 + * - \ref CRC_16 + * - \ref CRC_32 + * @param[in] u32Attribute CRC operation data attribute. Valid values are combined with: + * - \ref CRC_CHECKSUM_COM + * - \ref CRC_CHECKSUM_RVS + * - \ref CRC_WDATA_COM + * - \ref CRC_WDATA_RVS + * @param[in] u32Seed Seed value. + * @param[in] u32DataLen CPU Write Data Length. Valid values are: + * - \ref CRC_CPU_WDATA_8 + * - \ref CRC_CPU_WDATA_16 + * - \ref CRC_CPU_WDATA_32 + * + * @return None + * + * @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n + * After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly. + */ +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen) +{ + CRC->SEED = u32Seed; + CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk; + + /* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */ + CRC->CTL |= CRC_CTL_CHKSINIT_Msk; +} + +/** + * @brief Get CRC Checksum + * + * @param[in] None + * + * @return Checksum Result + * + * @details This function gets the CRC checksum result by current CRC polynomial mode. + */ +uint32_t CRC_GetChecksum(void) +{ + uint32_t u32Checksum = 0UL; + + switch(CRC->CTL & CRC_CTL_CRCMODE_Msk) + { + case CRC_CCITT: + case CRC_16: + u32Checksum = (CRC->CHECKSUM & 0xFFFFUL); + break; + + case CRC_32: + u32Checksum = CRC->CHECKSUM; + break; + + case CRC_8: + u32Checksum = (CRC->CHECKSUM & 0xFFUL); + break; + + default: + break; + } + + return u32Checksum; +} + +/**@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CRC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_crypto.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_crypto.c new file mode 100644 index 0000000000..7a95e42317 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_crypto.c @@ -0,0 +1,2972 @@ +/**************************************************************************//** + * @file crypto.c + * @version V3.00 + * @brief Cryptographic Accelerator driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include "NuMicro.h" + +#define ENABLE_DEBUG 0 + +#define ECC_SCA_PROTECT 1 // Enable Side-Channel Protecton + +#if ENABLE_DEBUG +#define CRPT_DBGMSG printf +#else +#define CRPT_DBGMSG(...) do { } while (0) /* disable debug */ +#endif + +#if defined(__ICCARM__) +# pragma diag_suppress=Pm073, Pm143 /* Misra C rule 14.7 */ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + +/* // @cond HIDDEN_SYMBOLS */ + + +static char hex_char_tbl[] = "0123456789abcdef"; + +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count); +static char get_Nth_nibble_char(uint32_t val32, uint32_t idx); +static void Hex2Reg(char input[], uint32_t volatile reg[]); +static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]); +static char ch2hex(char ch); +static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift); +static int get_nibble_value(char c); +int32_t ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[]); +void ECC_Complete(CRPT_T *crpt); + + +/* // @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Open PRNG function + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32KeySize it is PRNG key size, including: + * - \ref PRNG_KEY_SIZE_64 + * - \ref PRNG_KEY_SIZE_128 + * - \ref PRNG_KEY_SIZE_192 + * - \ref PRNG_KEY_SIZE_256 + * @param[in] u32SeedReload is PRNG seed reload or not, including: + * - \ref PRNG_SEED_CONT + * - \ref PRNG_SEED_RELOAD + * @param[in] u32Seed The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD. + * @return None + */ +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed) +{ + if(u32SeedReload) + { + crpt->PRNG_SEED = u32Seed; + } + + crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) | + (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos); +} + +/** + * @brief Start to generate one PRNG key. + * @param[in] crpt The pointer of CRYPTO module + * @return None + */ +void PRNG_Start(CRPT_T *crpt) +{ + crpt->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk; + + /* Waiting for PRNG Busy */ + while(crpt->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) {} + +} + +/** + * @brief Read the PRNG key. + * @param[in] crpt The pointer of CRYPTO module + * @param[out] u32RandKey The key buffer to store newly generated PRNG key. + * @return None + */ +void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]) +{ + uint32_t i, wcnt; + + wcnt = (((crpt->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk) >> CRPT_PRNG_CTL_KEYSZ_Pos) + 1U) * 2U; + + for(i = 0U; i < wcnt; i++) + { + u32RandKey[i] = crpt->PRNG_KEY[i]; + } + + crpt->PRNG_CTL &= ~CRPT_PRNG_CTL_SEEDRLD_Msk; +} + + +/** + * @brief Open AES encrypt/decrypt function. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32EncDec 1: AES encode; 0: AES decode + * @param[in] u32OpMode AES operation mode, including: + * - \ref AES_MODE_ECB + * - \ref AES_MODE_CBC + * - \ref AES_MODE_CFB + * - \ref AES_MODE_OFB + * - \ref AES_MODE_CTR + * - \ref AES_MODE_CBC_CS1 + * - \ref AES_MODE_CBC_CS2 + * - \ref AES_MODE_CBC_CS3 + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @param[in] u32SwapType is AES input/output data swap control, including: + * - \ref AES_NO_SWAP + * - \ref AES_OUT_SWAP + * - \ref AES_IN_SWAP + * - \ref AES_IN_OUT_SWAP + * @return None + */ +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, + uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType) +{ + (void)u32Channel; + + crpt->AES_CTL = (u32EncDec << CRPT_AES_CTL_ENCRPT_Pos) | + (u32OpMode << CRPT_AES_CTL_OPMODE_Pos) | + (u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) | + (u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos); + +} + +/** + * @brief Start AES encrypt/decrypt + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32DMAMode AES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shot AES encrypt/decrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous AES encrypt/decrypt. + * - \ref CRYPTO_DMA_LAST Last AES encrypt/decrypt of a series of AES_Start. + * @return None + */ +void AES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode) +{ + (void)u32Channel; + + crpt->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos); +} + +/** + * @brief Set AES keys + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] au32Keys An word array contains AES keys. + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @return None + */ +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize) +{ + uint32_t i, wcnt, key_reg_addr; + + (void) u32Channel; + + key_reg_addr = (uint32_t)&crpt->AES_KEY[0]; + wcnt = 4UL + u32KeySize * 2UL; + + for(i = 0U; i < wcnt; i++) + { + outpw(key_reg_addr, au32Keys[i]); + key_reg_addr += 4UL; + } +} + + + +/** + * @brief Set AES keys index of Key Store + * @param[in] crpt The pointer of CRYPTO module + * @param[in] mem Memory type of Key Store key. it could be: + * - \ref KS_SRAM + * - \ref KS_FLASH + * - \ref KS_OTP + * @param[in] i32KeyIdx Index of the key in Key Store. + * @details AES could use the key in Key Store. This function is used to set the key index of Key Store. + */ +void AES_SetKey_KS(CRPT_T *crpt, KS_MEM_Type mem, int32_t i32KeyIdx) +{ + /* Use key in key store */ + crpt->AES_KSCTL = CRPT_AES_KSCTL_RSRC_Msk /* use KS */ | + (uint32_t)((int)mem << CRPT_AES_KSCTL_RSSRC_Pos) /* KS Memory type */ | + (uint32_t)i32KeyIdx /* key num */ ; + +} + + +/** + * @brief Set AES initial vectors + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] au32IV A four entry word array contains AES initial vectors. + * @return None + */ +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]) +{ + uint32_t i, key_reg_addr; + + (void) u32Channel; + + key_reg_addr = (uint32_t)&crpt->AES_IV[0]; + + for(i = 0U; i < 4U; i++) + { + outpw(key_reg_addr, au32IV[i]); + key_reg_addr += 4UL; + } +} + +/** + * @brief Set AES DMA transfer configuration. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32SrcAddr AES DMA source address + * @param[in] u32DstAddr AES DMA destination address + * @param[in] u32TransCnt AES DMA transfer byte count + * @return None + */ +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, + uint32_t u32DstAddr, uint32_t u32TransCnt) +{ + (void) u32Channel; + + crpt->AES_SADDR = u32SrcAddr; + crpt->AES_DADDR = u32DstAddr; + crpt->AES_CNT = u32TransCnt; + +} + +/** + * @brief Open SHA encrypt function. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32OpMode SHA operation mode, including: + * - \ref SHA_MODE_SHA1 + * - \ref SHA_MODE_SHA224 + * - \ref SHA_MODE_SHA256 + * @param[in] u32SwapType is SHA input/output data swap control, including: + * - \ref SHA_NO_SWAP + * - \ref SHA_OUT_SWAP + * - \ref SHA_IN_SWAP + * - \ref SHA_IN_OUT_SWAP + * @param[in] hmac_key_len HMAC key byte count + * @return None + */ +void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len) +{ + crpt->HMAC_CTL = (u32OpMode << CRPT_HMAC_CTL_OPMODE_Pos) | + (u32SwapType << CRPT_HMAC_CTL_OUTSWAP_Pos); + + if(hmac_key_len != 0UL) + { + crpt->HMAC_KEYCNT = hmac_key_len; + } +} + +/** + * @brief Start SHA encrypt + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32DMAMode TDES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop SHA encrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous SHA encrypt. + * - \ref CRYPTO_DMA_LAST Last SHA encrypt of a series of SHA_Start. + * @return None + */ +void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode) +{ + crpt->HMAC_CTL &= ~(0x7UL << CRPT_HMAC_CTL_DMALAST_Pos); + crpt->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk | (u32DMAMode << CRPT_HMAC_CTL_DMALAST_Pos); +} + +/** + * @brief Set SHA DMA transfer + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32SrcAddr SHA DMA source address + * @param[in] u32TransCnt SHA DMA transfer byte count + * @return None + */ +void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt) +{ + crpt->HMAC_SADDR = u32SrcAddr; + crpt->HMAC_DMACNT = u32TransCnt; +} + +/** + * @brief Read the SHA digest. + * @param[in] crpt The pointer of CRYPTO module + * @param[out] u32Digest The SHA encrypt output digest. + * @return None + */ +void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]) +{ + uint32_t i, wcnt, reg_addr; + + i = (crpt->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos; + + if(i == SHA_MODE_SHA1) + { + wcnt = 5UL; + } + else if(i == SHA_MODE_SHA224) + { + wcnt = 7UL; + } + else if(i == SHA_MODE_SHA256) + { + wcnt = 8UL; + } + else if(i == SHA_MODE_SHA384) + { + wcnt = 12UL; + } + else + { + /* SHA_MODE_SHA512 */ + wcnt = 16UL; + } + + reg_addr = (uint32_t) & (crpt->HMAC_DGST[0]); + for(i = 0UL; i < wcnt; i++) + { + u32Digest[i] = inpw(reg_addr); + reg_addr += 4UL; + } +} + + +/*-----------------------------------------------------------------------------------------------*/ +/* */ +/* ECC */ +/* */ +/*-----------------------------------------------------------------------------------------------*/ + +#define ECCOP_POINT_MUL (0x0UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_MODULE (0x1UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_ADD (0x2UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_DOUBLE (0x0UL << CRPT_ECC_CTL_ECCOP_Pos) + +#define MODOP_DIV (0x0UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_MUL (0x1UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_ADD (0x2UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_SUB (0x3UL << CRPT_ECC_CTL_MODOP_Pos) + +#define OP_ECDSAS (0x1UL << CRPT_ECC_CTL_ECDSAS_Pos) +#define OP_ECDSAR (0x1UL << CRPT_ECC_CTL_ECDSAR_Pos) + +enum +{ + CURVE_GF_P, + CURVE_GF_2M, +}; + +/*-----------------------------------------------------*/ +/* Define elliptic curve (EC): */ +/*-----------------------------------------------------*/ +static const ECC_CURVE _Curve[] = +{ + { + /* NIST: Curve P-192 : y^2=x^3-ax+b (mod p) */ + CURVE_P_192, + 48, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFC", /* "000000000000000000000000000000000000000000000003" */ + "64210519e59c80e70fa7e9ab72243049feb8deecc146b9b1", + "188da80eb03090f67cbf20eb43a18800f4ff0afd82ff1012", + "07192b95ffc8da78631011ed6b24cdd573f977a11e794811", + 58, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF", /* "6277101735386680763835789423207666416083908700390324961279" */ + 58, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831", /* "6277101735386680763835789423176059013767194773182842284081" */ + 192, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* NIST: Curve P-224 : y^2=x^3-ax+b (mod p) */ + CURVE_P_224, + 56, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFE", /* "00000000000000000000000000000000000000000000000000000003" */ + "b4050a850c04b3abf54132565044b0b7d7bfd8ba270b39432355ffb4", + "b70e0cbd6bb4bf7f321390b94a03c1d356c21122343280d6115c1d21", + "bd376388b5f723fb4c22dfe6cd4375a05a07476444d5819985007e34", + 70, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "0026959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D", /* "0026959946667150639794667015087019625940457807714424391721682722368061" */ + 224, /* key_len */ + 9, + 8, + 3, + CURVE_GF_P + }, + { + /* NIST: Curve P-256 : y^2=x^3-ax+b (mod p) */ + CURVE_P_256, + 64, /* Echar */ + "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFC", /* "0000000000000000000000000000000000000000000000000000000000000003" */ + "5ac635d8aa3a93e7b3ebbd55769886bc651d06b0cc53b0f63bce3c3e27d2604b", + "6b17d1f2e12c4247f8bce6e563a440f277037d812deb33a0f4a13945d898c296", + "4fe342e2fe1a7f9b8ee7eb4a7c0f9e162bce33576b315ececbb6406837bf51f5", + 78, /* Epl */ + "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF", /* "115792089210356248762697446949407573530086143415290314195533631308867097853951" */ + 78, /* Eol */ + "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551", /* "115792089210356248762697446949407573529996955224135760342422259061068512044369" */ + 256, /* key_len */ + 10, + 5, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-384 : y^2=x^3-ax+b (mod p) */ + CURVE_P_384, + 96, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFC", /* "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */ + "b3312fa7e23ee7e4988e056be3f82d19181d9c6efe8141120314088f5013875ac656398d8a2ed19d2a85c8edd3ec2aef", + "aa87ca22be8b05378eb1c71ef320ad746e1d3b628ba79b9859f741e082542a385502f25dbf55296c3a545e3872760ab7", + "3617de4a96262c6f5d9e98bf9292dc29f8f41dbd289a147ce9da3113b5f0b8c00a60b1ce1d7e819d7a431d7c90ea0e5f", + 116, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF", /* "39402006196394479212279040100143613805079739270465446667948293404245721771496870329047266088258938001861606973112319" */ + 116, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973", /* "39402006196394479212279040100143613805079739270465446667946905279627659399113263569398956308152294913554433653942643" */ + 384, /* key_len */ + 12, + 3, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-521 : y^2=x^3-ax+b (mod p)*/ + CURVE_P_521, + 131, /* Echar */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC", /* "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */ + "051953eb9618e1c9a1f929a21a0b68540eea2da725b99b315f3b8b489918ef109e156193951ec7e937b1652c0bd3bb1bf073573df883d2c34f1ef451fd46b503f00", + "0c6858e06b70404e9cd9e3ecb662395b4429c648139053fb521f828af606b4d3dbaa14b5e77efe75928fe1dc127a2ffa8de3348b3c1856a429bf97e7e31c2e5bd66", + "11839296a789a3bc0045c8a5fb42c7d1bd998f54449579b446817afbd17273e662c97ee72995ef42640c550b9013fad0761353c7086a272c24088be94769fd16650", + 157, /* Epl */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397656052122559640661454554977296311391480858037121987999716643812574028291115057151" */ + 157, /* Eol */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397655394245057746333217197532963996371363321113864768612440380340372808892707005449" */ + 521, /* key_len */ + 32, + 32, + 32, + CURVE_GF_P + }, + { + /* NIST: Curve B-163 : y^2+xy=x^3+ax^2+b */ + CURVE_B_163, + 41, /* Echar */ + "00000000000000000000000000000000000000001", + "20a601907b8c953ca1481eb10512f78744a3205fd", + "3f0eba16286a2d57ea0991168d4994637e8343e36", + "0d51fbc6c71a0094fa2cdd545b11c5c0c797324f1", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 49, /* Eol */ + "40000000000000000000292FE77E70C12A4234C33", /* "5846006549323611672814742442876390689256843201587" */ + 163, /* key_len */ + 7, + 6, + 3, + CURVE_GF_2M + }, + { + /* NIST: Curve B-233 : y^2+xy=x^3+ax^2+b */ + CURVE_B_233, + 59, /* Echar 59 */ + "00000000000000000000000000000000000000000000000000000000001", + "066647ede6c332c7f8c0923bb58213b333b20e9ce4281fe115f7d8f90ad", + "0fac9dfcbac8313bb2139f1bb755fef65bc391f8b36f8f8eb7371fd558b", + "1006a08a41903350678e58528bebf8a0beff867a7ca36716f7e01f81052", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "1000000000000000000000000000013E974E72F8A6922031D2603CFE0D7", /* "6901746346790563787434755862277025555839812737345013555379383634485463" */ + 233, /* key_len */ + 74, + 74, + 74, + CURVE_GF_2M + }, + { + /* NIST: Curve B-283 : y^2+xy=x^3+ax^2+b */ + CURVE_B_283, + 71, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000001", + "27b680ac8b8596da5a4af8a19a0303fca97fd7645309fa2a581485af6263e313b79a2f5", + "5f939258db7dd90e1934f8c70b0dfec2eed25b8557eac9c80e2e198f8cdbecd86b12053", + "3676854fe24141cb98fe6d4b20d02b4516ff702350eddb0826779c813f0df45be8112f4", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 85, /* Eol */ + "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF90399660FC938A90165B042A7CEFADB307", /* "7770675568902916283677847627294075626569625924376904889109196526770044277787378692871" */ + 283, /* key_len */ + 12, + 7, + 5, + CURVE_GF_2M + }, + { + /* NIST: Curve B-409 : y^2+xy=x^3+ax^2+b */ + CURVE_B_409, + 103, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "021a5c2c8ee9feb5c4b9a753b7b476b7fd6422ef1f3dd674761fa99d6ac27c8a9a197b272822f6cd57a55aa4f50ae317b13545f", + "15d4860d088ddb3496b0c6064756260441cde4af1771d4db01ffe5b34e59703dc255a868a1180515603aeab60794e54bb7996a7", + "061b1cfab6be5f32bbfa78324ed106a7636b9c5a7bd198d0158aa4f5488d08f38514f1fdf4b4f40d2181b3681c364ba0273c706", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 123, /* Eol */ + "10000000000000000000000000000000000000000000000000001E2AAD6A612F33307BE5FA47C3C9E052F838164CD37D9A21173", /* "661055968790248598951915308032771039828404682964281219284648798304157774827374805208143723762179110965979867288366567526771" */ + 409, /* key_len */ + 87, + 87, + 87, + CURVE_GF_2M + }, + { + /* NIST: Curve B-571 : y^2+xy=x^3+ax^2+b */ + CURVE_B_571, + 143, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "2f40e7e2221f295de297117b7f3d62f5c6a97ffcb8ceff1cd6ba8ce4a9a18ad84ffabbd8efa59332be7ad6756a66e294afd185a78ff12aa520e4de739baca0c7ffeff7f2955727a", + "303001d34b856296c16c0d40d3cd7750a93d1d2955fa80aa5f40fc8db7b2abdbde53950f4c0d293cdd711a35b67fb1499ae60038614f1394abfa3b4c850d927e1e7769c8eec2d19", + "37bf27342da639b6dccfffeb73d69d78c6c27a6009cbbca1980f8533921e8a684423e43bab08a576291af8f461bb2a8b3531d2f0485c19b16e2f1516e23dd3c1a4827af1b8ac15b", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 172, /* Eol */ + "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE661CE18FF55987308059B186823851EC7DD9CA1161DE93D5174D66E8382E9BB2FE84E47", /* "3864537523017258344695351890931987344298927329706434998657235251451519142289560424536143999389415773083133881121926944486246872462816813070234528288303332411393191105285703" */ + 571, /* key_len */ + 10, + 5, + 2, + CURVE_GF_2M + }, + { + /* NIST: Curve K-163 : y^2+xy=x^3+ax^2+b */ + CURVE_K_163, + 41, /* Echar */ + "00000000000000000000000000000000000000001", + "00000000000000000000000000000000000000001", + "2fe13c0537bbc11acaa07d793de4e6d5e5c94eee8", + "289070fb05d38ff58321f2e800536d538ccdaa3d9", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 49, /* Eol */ + "4000000000000000000020108A2E0CC0D99F8A5EF", /* "5846006549323611672814741753598448348329118574063" */ + 163, /* key_len */ + 7, + 6, + 3, + CURVE_GF_2M + }, + { + /* NIST: Curve K-233 : y^2+xy=x^3+ax^2+b */ + CURVE_K_233, + 59, /* Echar 59 */ + "00000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000001", + "17232ba853a7e731af129f22ff4149563a419c26bf50a4c9d6eefad6126", + "1db537dece819b7f70f555a67c427a8cd9bf18aeb9b56e0c11056fae6a3", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "8000000000000000000000000000069D5BB915BCD46EFB1AD5F173ABDF", /* "3450873173395281893717377931138512760570940988862252126328087024741343" */ + 233, /* key_len */ + 74, + 74, + 74, + CURVE_GF_2M + }, + { + /* NIST: Curve K-283 : y^2+xy=x^3+ax^2+b */ + CURVE_K_283, + 71, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000000000000000001", + "503213f78ca44883f1a3b8162f188e553cd265f23c1567a16876913b0c2ac2458492836", + "1ccda380f1c9e318d90f95d07e5426fe87e45c0e8184698e45962364e34116177dd2259", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 85, /* Eol */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9AE2ED07577265DFF7F94451E061E163C61", /* "3885337784451458141838923813647037813284811733793061324295874997529815829704422603873" */ + 283, /* key_len */ + 12, + 7, + 5, + CURVE_GF_2M + }, + { + /* NIST: Curve K-409 : y^2+xy=x^3+ax^2+b */ + CURVE_K_409, + 103, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "060f05f658f49c1ad3ab1890f7184210efd0987e307c84c27accfb8f9f67cc2c460189eb5aaaa62ee222eb1b35540cfe9023746", + "1e369050b7c4e42acba1dacbf04299c3460782f918ea427e6325165e9ea10e3da5f6c42e9c55215aa9ca27a5863ec48d8e0286b", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 123, /* Eol */ + "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5F83B2D4EA20400EC4557D5ED3E3E7CA5B4B5C83B8E01E5FCF", /* "330527984395124299475957654016385519914202341482140609642324395022880711289249191050673258457777458014096366590617731358671" */ + 409, /* key_len */ + 87, + 87, + 87, + CURVE_GF_2M + }, + { + /* NIST: Curve K-571 : y^2+xy=x^3+ax^2+b */ + CURVE_K_571, + 143, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "26eb7a859923fbc82189631f8103fe4ac9ca2970012d5d46024804801841ca44370958493b205e647da304db4ceb08cbbd1ba39494776fb988b47174dca88c7e2945283a01c8972", + "349dc807f4fbf374f4aeade3bca95314dd58cec9f307a54ffc61efc006d8a2c9d4979c0ac44aea74fbebbb9f772aedcb620b01a7ba7af1b320430c8591984f601cd4c143ef1c7a3", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 172, /* Eol */ + "20000000000000000000000000000000000000000000000000000000000000000000000131850E1F19A63E4B391A8DB917F4138B630D84BE5D639381E91DEB45CFE778F637C1001", /* "1932268761508629172347675945465993672149463664853217499328617625725759571144780212268133978522706711834706712800825351461273674974066617311929682421617092503555733685276673" */ + 571, /* key_len */ + 10, + 5, + 2, + CURVE_GF_2M + }, + { + /* Koblitz: Curve secp192k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_192, + 48, /* Echar */ + "00000000000000000000000000000000000000000", + "00000000000000000000000000000000000000003", + "DB4FF10EC057E9AE26B07D0280B7F4341DA5D1B1EAE06C7D", + "9B2F2F6D9C5628A7844163D015BE86344082AA88D95E2F9D", + 58, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFEE37", /* p */ + 58, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFE26F2FC170F69466A74DEFD8D", /* n */ + 192, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Koblitz: Curve secp224k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_224, + 56, /* Echar */ + "00000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000005", + "A1455B334DF099DF30FC28A169A467E9E47075A90F7E650EB6B7A45C", + "7E089FED7FBA344282CAFBD6F7E319F7C0B0BD59E2CA4BDB556D61A5", + 70, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFE56D", /* p */ + 70, /* Eol */ + "0000000000000000000000000001DCE8D2EC6184CAF0A971769FB1F7", /* n */ + 224, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Koblitz: Curve secp256k1 : y2 = x3+ax+b over Fp */ + CURVE_KO_256, + 64, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000", + "0000000000000000000000000000000000000000000000000000000000000007", + "79BE667EF9DCBBAC55A06295CE870B07029BFCDB2DCE28D959F2815B16F81798", + "483ADA7726A3C4655DA4FBFC0E1108A8FD17B448A68554199C47D08FFB10D4B8", + 78, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFC2F", /* p */ + 78, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBAAEDCE6AF48A03BBFD25E8CD0364141", /* n */ + 256, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP256r1 */ + CURVE_BP_256, + 64, /* Echar */ + "7D5A0975FC2C3057EEF67530417AFFE7FB8055C126DC5C6CE94A4B44F330B5D9", /* A */ + "26DC5C6CE94A4B44F330B5D9BBD77CBF958416295CF7E1CE6BCCDC18FF8C07B6", /* B */ + "8BD2AEB9CB7E57CB2C4B482FFC81B7AFB9DE27E1E3BD23C23A4453BD9ACE3262", /* x */ + "547EF835C3DAC4FD97F8461A14611DC9C27745132DED8E545C1D54C72F046997", /* y */ + 78, /* Epl */ + "A9FB57DBA1EEA9BC3E660A909D838D726E3BF623D52620282013481D1F6E5377", /* p */ + 78, /* Eol */ + "A9FB57DBA1EEA9BC3E660A909D838D718C397AA3B561A6F7901E0E82974856A7", /* q */ + 256, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP384r1 */ + CURVE_BP_384, + 96, /* Echar */ + "7BC382C63D8C150C3C72080ACE05AFA0C2BEA28E4FB22787139165EFBA91F90F8AA5814A503AD4EB04A8C7DD22CE2826", /* A */ + "04A8C7DD22CE28268B39B55416F0447C2FB77DE107DCD2A62E880EA53EEB62D57CB4390295DBC9943AB78696FA504C11", /* B */ + "1D1C64F068CF45FFA2A63A81B7C13F6B8847A3E77EF14FE3DB7FCAFE0CBD10E8E826E03436D646AAEF87B2E247D4AF1E", /* x */ + "8ABE1D7520F9C2A45CB1EB8E95CFD55262B70B29FEEC5864E19C054FF99129280E4646217791811142820341263C5315", /* y */ + 116, /* Epl */ + "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B412B1DA197FB71123ACD3A729901D1A71874700133107EC53", /* p */ + 116, /* Eol */ + "8CB91E82A3386D280F5D6F7E50E641DF152F7109ED5456B31F166E6CAC0425A7CF3AB6AF6B7FC3103B883202E9046565", /* q */ + 384, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* Brainpool: Curve brainpoolP512r1 */ + CURVE_BP_512, + 128, /* Echar */ + "7830A3318B603B89E2327145AC234CC594CBDD8D3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CA", /* A */ + "3DF91610A83441CAEA9863BC2DED5D5AA8253AA10A2EF1C98B9AC8B57F1117A72BF2C7B9E7C1AC4D77FC94CADC083E67984050B75EBAE5DD2809BD638016F723", /* B */ + "81AEE4BDD82ED9645A21322E9C4C6A9385ED9F70B5D916C1B43B62EEF4D0098EFF3B1F78E2D0D48D50D1687B93B97D5F7C6D5047406A5E688B352209BCB9F822", /* x */ + "7DDE385D566332ECC0EABFA9CF7822FDF209F70024A57B1AA000C55B881F8111B2DCDE494A5F485E5BCA4BD88A2763AED1CA2B2FA8F0540678CD1E0F3AD80892", /* y */ + 156, /* Epl */ + "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA703308717D4D9B009BC66842AECDA12AE6A380E62881FF2F2D82C68528AA6056583A48F3", /* p */ + 156, /* Eol */ + "AADD9DB8DBE9C48B3FD4E6AE33C9FC07CB308DB3B3C9D20ED6639CCA70330870553E5C414CA92619418661197FAC10471DB1D381085DDADDB58796829CA90069", /* q */ + 512, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + CURVE_25519, + 64, // Echar + "0000000000000000000000000000000000000000000000000000000000076D06", // "0000000000000000000000000000000000000000000000000000000000000003", + "0000000000000000000000000000000000000000000000000000000000000001", + "0000000000000000000000000000000000000000000000000000000000000009", + "20ae19a1b8a086b4e01edd2c7748d14c923d4d7e6d7c61b229e9c5a27eced3d9", + 78, // Epl + "7fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffed", // "115792089210356248762697446949407573530086143415290314195533631308867097853951", + 78, // Eol + "1000000000000000000000000000000014def9dea2f79cd65812631a5cf5d3ed", // "115792089210356248762697446949407573529996955224135760342422259061068512044369", + 255, // key_len + 10, + 5, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-256 : y^2=x^3-ax+b (mod p) */ + CURVE_SM2_256, + 64, /* Echar */ + "FFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFC", /* a */ + "28E9FA9E9D9F5E344D5A9E4BCF6509A7F39789F515AB8F92DDBCBD414D940E93", /* b */ + "32C4AE2C1F1981195F9904466A39C9948FE30BBFF2660BE1715A4589334C74C7", /* x */ + "BC3736A2F4F6779C59BDCEE36B692153D0A9877CC62A474002DF32E52139F0A0", /* y */ + 78, /* Epl */ + "FFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFF", /* p */ + 78, /* Eol */ + "FFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFF7203DF6B21C6052B53BBF40939D54123", /* n */ + 256, /* key_len */ + 10, + 5, + 2, + CURVE_GF_P + }, + +}; + + +static ECC_CURVE *pCurve; +static ECC_CURVE Curve_Copy; + +static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve); +static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve); +static void run_ecc_codec(CRPT_T *crpt, uint32_t mode); + +static char temp_hex_str[160]; + +static volatile uint32_t g_ECC_done, g_ECCERR_done; + +void ECC_DriverISR(CRPT_T *crpt) +{ + if(crpt->INTSTS & CRPT_INTSTS_ECCIF_Msk) + { + g_ECC_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCIF_Msk; + /* printf("ECC done IRQ.\n"); */ + } + + if(crpt->INTSTS & CRPT_INTSTS_ECCEIF_Msk) + { + g_ECCERR_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCEIF_Msk; + /* printf("ECCERRIF is set!!\n"); */ + } +} + + +#if ENABLE_DEBUG +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) +{ + int32_t i; + + printf("%s => ", str); + for(i = 0; i < count; i++) + { + printf("0x%08x ", regs[i]); + } + printf("\n"); +} +#else +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) +{ + (void)str; + (void)regs; + (void)count; +} +#endif +static char ch2hex(char ch) +{ + if(ch <= '9') + { + return ch - '0'; + } + else if((ch <= 'z') && (ch >= 'a')) + { + return ch - 'a' + 10U; + } + else + { + return ch - 'A' + 10U; + } +} + +static void Hex2Reg(char input[], uint32_t volatile reg[]) +{ + char hex; + int si, ri; + uint32_t i, val32; + + si = (int)strlen(input) - 1; + ri = 0; + + while(si >= 0) + { + val32 = 0UL; + for(i = 0UL; (i < 8UL) && (si >= 0); i++) + { + hex = ch2hex(input[si]); + val32 |= (uint32_t)hex << (i * 4UL); + si--; + } + reg[ri++] = val32; + } +} + +static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift) +{ + uint32_t hex, carry; + int si, ri; + uint32_t i, val32; + + si = (int)strlen(input) - 1; + ri = 0; + carry = 0U; + while(si >= 0) + { + val32 = 0UL; + for(i = 0UL; (i < 8UL) && (si >= 0); i++) + { + hex = (uint32_t)ch2hex(input[si]); + hex <<= shift; + + val32 |= (uint32_t)((hex & 0xFU) | carry) << (i * 4UL); + carry = (hex >> 4) & 0xFU; + si--; + } + reg[ri++] = val32; + } + if(carry != 0U) + { + reg[ri] = carry; + } +} + +/** + * @brief Extract specified nibble from an unsigned word in character format. + * For example: + * Suppose val32 is 0x786543210, get_Nth_nibble_char(val32, 3) will return a '3'. + * @param[in] val32 The input unsigned word + * @param[in] idx The Nth nibble to be extracted. + * @return The nibble in character format. + */ +static char get_Nth_nibble_char(uint32_t val32, uint32_t idx) +{ + return hex_char_tbl[(val32 >> (idx * 4U)) & 0xfU ]; +} + + +static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]) +{ + int32_t idx, ri; + uint32_t i; + + output[count] = 0U; + idx = count - 1; + + for(ri = 0; idx >= 0; ri++) + { + for(i = 0UL; (i < 8UL) && (idx >= 0); i++) + { + output[idx] = get_Nth_nibble_char(reg[ri], i); + idx--; + } + } +} + +/** + * @brief Translate registers value into hex string + * @param[in] count The string length of ouptut hex string. + * @param[in] reg Register array. + * @param[in] output String buffer for output hex string. + */ +void CRPT_Reg2Hex(int32_t count,volatile uint32_t reg[], char output[]) +{ + Reg2Hex(count, reg, output); +} + +/** + * @brief Translate hex string to registers value + * @param[in] input hex string. + * @param[in] reg Register array. + */ +void CRPT_Hex2Reg(char input[], uint32_t volatile reg[]) +{ + Hex2Reg(input, reg); +} + + +static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve) +{ + int32_t i, ret = 0; + + pCurve = get_curve(ecc_curve); + if(pCurve == NULL) + { + CRPT_DBGMSG("Cannot find curve %d!!\n", ecc_curve); + ret = -1; + } + + if(ret == 0) + { + for(i = 0; i < 18; i++) + { + crpt->ECC_A[i] = 0UL; + crpt->ECC_B[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + crpt->ECC_N[i] = 0UL; + } + + Hex2Reg(pCurve->Ea, crpt->ECC_A); + Hex2Reg(pCurve->Eb, crpt->ECC_B); + Hex2Reg(pCurve->Px, crpt->ECC_X1); + Hex2Reg(pCurve->Py, crpt->ECC_Y1); + + CRPT_DBGMSG("Key length = %d\n", pCurve->key_len); + dump_ecc_reg("CRPT_ECC_CURVE_A", crpt->ECC_A, 10); + dump_ecc_reg("CRPT_ECC_CURVE_B", crpt->ECC_B, 10); + dump_ecc_reg("CRPT_ECC_POINT_X1", crpt->ECC_X1, 10); + dump_ecc_reg("CRPT_ECC_POINT_Y1", crpt->ECC_Y1, 10); + + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_N[0] = 0x1UL; + crpt->ECC_N[(pCurve->key_len) / 32] |= (1UL << ((pCurve->key_len) % 32)); + crpt->ECC_N[(pCurve->irreducible_k1) / 32] |= (1UL << ((pCurve->irreducible_k1) % 32)); + crpt->ECC_N[(pCurve->irreducible_k2) / 32] |= (1UL << ((pCurve->irreducible_k2) % 32)); + crpt->ECC_N[(pCurve->irreducible_k3) / 32] |= (1UL << ((pCurve->irreducible_k3) % 32)); + } + else + { + Hex2Reg(pCurve->Pp, crpt->ECC_N); + } + } + dump_ecc_reg("CRPT_ECC_CURVE_N", crpt->ECC_N, 10); + return ret; +} + + +static int get_nibble_value(char c) +{ + char ch; + + if((c >= '0') && (c <= '9')) + { + ch = '0'; + return ((int)c - (int)ch); + } + + if((c >= 'a') && (c <= 'f')) + { + ch = 'a'; + return ((int)c - (int)ch + 10); + } + + if((c >= 'A') && (c <= 'F')) + { + ch = 'A'; + return ((int)c - (int)ch + 10); + } + return 0; +} + + +/** + * @brief Check if the private key is located in valid range of curve. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k The input private key. + * @return 1 Is valid. + * @return 0 Is not valid. + * @return -1 Invalid curve. + */ +int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]) +{ + uint32_t i; + + (void)crpt; + pCurve = get_curve(ecc_curve); + if(pCurve == NULL) + { + return -1; + } + + if(strlen(private_k) < strlen(pCurve->Eorder)) + { + return 1; + } + + if(strlen(private_k) > strlen(pCurve->Eorder)) + { + return 0; + } + + for(i = 0U; i < strlen(private_k); i++) + { + if(get_nibble_value(private_k[i]) < get_nibble_value(pCurve->Eorder[i])) + { + return 1; + } + + if(get_nibble_value(private_k[i]) > get_nibble_value(pCurve->Eorder[i])) + { + return 0; + } + } + return 0; +} + + +/** + * @brief Given a private key and curve to generate the public key pair. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] private_k The input private key. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[out] public_k1 The output publick key 1. + * @param[out] public_k2 The output publick key 2. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]) +{ + int32_t ret = 0, i; + uint32_t u32Tmp; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + CRPT->ECC_KSCTL = 0; + + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + } + + Hex2Reg(private_k, crpt->ECC_K); + + /* set FSEL (Field selection) */ + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else /* CURVE_GF_P */ + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + do + { + u32Tmp = g_ECC_done; + u32Tmp |= g_ECCERR_done; + } + while(u32Tmp == 0UL); + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, public_k1); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, public_k2); + } + + return ret; +} + + + + +/** + * @brief Given a private key and curve to generate the public key pair. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] mem Memory type of Key Store. It could be KS_SRAM, KS_FLASH or KS_OTP. + * @param[in] i32KeyIdx Index of the key in Key Store. + * @param[out] public_k1 The output publick key 1. + * @param[out] public_k2 The output publick key 2. + * @param[in] u32ExtraOp Extra options for ECC_KSCTL register. + + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GeneratePublicKey_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[], uint32_t u32ExtraOp) +{ + int32_t ret = 0; + uint32_t u32Tmp; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + + // key from key store + crpt->ECC_KSCTL = (uint32_t)(mem << 6)/* KS Memory Type */ | + (CRPT_ECC_KSCTL_RSRCK_Msk)/* Key from KS */ | + u32ExtraOp | + (uint32_t)i32KeyIdx; + + /* set FSEL (Field selection) */ + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else /* CURVE_GF_P */ + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + do + { + u32Tmp = g_ECC_done; + u32Tmp |= g_ECCERR_done; + } + while(u32Tmp == 0UL); + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, public_k1); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, public_k2); + } + + return ret; +} + +/** + * @brief Given a private key and curve to generate the public key pair. + * @param[in] crpt Reference to Crypto module. + * @param[out] x1 The x-coordinate of input point. + * @param[out] y1 The y-coordinate of input point. + * @param[in] k The private key + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[out] x2 The x-coordinate of output point. + * @param[out] y2 The y-coordinate of output point. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_Mutiply(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char x1[], char y1[], char *k, char x2[], char y2[]) +{ + int32_t i, ret = 0; + + if (ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if (ret == 0) + { + for (i = 0; i < 9; i++) + { + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + crpt->ECC_K[i] = 0UL; + } + + Hex2Reg(x1, crpt->ECC_X1); + Hex2Reg(y1, crpt->ECC_Y1); + Hex2Reg(k, crpt->ECC_K); + + /* set FSEL (Field selection) */ + if (pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + + if (ecc_curve == CURVE_25519) + { + printf("!! Is curve-25519 !!\n"); + crpt->ECC_CTL |= CRPT_ECC_CTL_SCAP_Msk; + crpt->ECC_CTL |= CRPT_ECC_CTL_CSEL_Msk; + + /* If SCAP enabled, the curve order must be written to ECC_X2 */ + if(crpt->ECC_CTL & CRPT_ECC_CTL_SCAP_Msk) + { + Hex2Reg(pCurve->Eorder, crpt->ECC_X2); + } + } + + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + while ((g_ECC_done == 0UL) && (g_ECCERR_done == 0UL)) + { + } + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, x2); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, y2); + + } + + return ret; +} + + +/** + * @brief Given a curve parameter, the other party's public key, and one's own private key to generate the secret Z. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k One's own private key. + * @param[in] public_k1 The other party's publick key 1. + * @param[in] public_k2 The other party's publick key 2. + * @param[out] secret_z The ECC CDH secret Z. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]) +{ + int32_t i, ret = 0; + uint32_t u32Tmp; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + if((ecc_curve == CURVE_B_163) || (ecc_curve == CURVE_B_233) || (ecc_curve == CURVE_B_283) || + (ecc_curve == CURVE_B_409) || (ecc_curve == CURVE_B_571) || (ecc_curve == CURVE_K_163)) + { + Hex2RegEx(private_k, crpt->ECC_K, 1); + } + else if((ecc_curve == CURVE_K_233) || (ecc_curve == CURVE_K_283) || + (ecc_curve == CURVE_K_409) || (ecc_curve == CURVE_K_571)) + { + Hex2RegEx(private_k, crpt->ECC_K, 2); + } + else + { + Hex2Reg(private_k, crpt->ECC_K); + } + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* set FSEL (Field selection) */ + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else /* CURVE_GF_P */ + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + do + { + u32Tmp = g_ECC_done; + u32Tmp |= g_ECCERR_done; + } + while(u32Tmp == 0UL); + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, secret_z); + } + + return ret; +} + + +/** + * @brief Given a curve parameter, the other party's public key, and one's own private key to generate the secret Z. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k One's own private key. + * @param[in] public_k1 The other party's publick key 1. + * @param[in] public_k2 The other party's publick key 2. + * @param[out] secret_z The ECC CDH secret Z. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSecretZ_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, KS_MEM_Type mem, int32_t i32KeyIdx, char public_k1[], char public_k2[]) +{ + int32_t i; + uint32_t u32Tmp; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + return -1; + } + + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + crpt->ECC_KSCTL = CRPT_ECC_KSCTL_ECDH_Msk | CRPT_ECC_KSCTL_RSRCK_Msk | + (uint32_t)(mem << CRPT_ECC_KSCTL_RSSRCK_Pos)/* KS Memory Type */ | + (uint32_t)i32KeyIdx; + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* set FSEL (Field selection) */ + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else /* CURVE_GF_P */ + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + do + { + u32Tmp = g_ECC_done; + u32Tmp |= g_ECCERR_done; + } + while(u32Tmp == 0UL); + + if(g_ECCERR_done) + return -1; + + return (crpt->ECC_KSSTS & 0x1f); + +} + + +static void run_ecc_codec(CRPT_T *crpt, uint32_t mode) +{ + uint32_t u32Tmp; + uint32_t eccop; + + eccop = mode & CRPT_ECC_CTL_ECCOP_Msk; + if(eccop == ECCOP_MODULE) + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + else + { + if(pCurve->GF == (int)CURVE_GF_2M) + { + /* point */ + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + +#ifdef ECC_SCA_PROTECT + if(eccop == ECCOP_POINT_MUL) + { + /* Enable side-channel protection in some operation */ + crpt->ECC_CTL |= CRPT_ECC_CTL_SCAP_Msk; + /* If SCAP enabled, the curve order must be written to ECC_X2 */ + Hex2Reg(pCurve->Eorder, crpt->ECC_X2); + } +#endif + + } + + g_ECC_done = g_ECCERR_done = 0UL; + + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | mode | CRPT_ECC_CTL_START_Msk; + + do + { + u32Tmp = g_ECC_done; + u32Tmp |= g_ECCERR_done; + } + while(u32Tmp == 0UL); + + while(crpt->ECC_STS & CRPT_ECC_STS_BUSY_Msk) { } +} + +/** + * @brief ECDSA digital signature generation. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] d The private key. + * @param[in] k The selected random integer. + * @param[out] R R of the (R,S) pair digital signature + * @param[out] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, + char *d, char *k, char *R, char *S) +{ + uint32_t volatile temp_result1[18], temp_result2[18]; + int32_t i, ret = 0; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + CRPT->ECC_KSCTL = 0; + + /* + * 1. Calculate e = HASH(m), where HASH is a cryptographic hashing algorithm, (i.e. SHA-1) + * (1) Use SHA to calculate e + */ + + /* 2. Select a random integer k form [1, n-1] + * (1) Notice that n is order, not prime modulus or irreducible polynomial function + */ + + /* + * 3. Compute r = x1 (mod n), where (x1, y1) = k * G. If r = 0, go to step 2 + * (1) Write the curve parameter A, B, and curve length M to corresponding registers + * (2) Write the prime modulus or irreducible polynomial function to N registers according + * (3) Write the point G(x, y) to X1, Y1 registers + * (4) Write the random integer k to K register + * (5) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Write the curve order and curve length to N ,M registers according + * (10) Write 0x0 to Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 * + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Read X1 registers to get r + */ + + /* 3-(4) Write the random integer k to K register */ + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + } + Hex2Reg(k, crpt->ECC_K); + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* 3-(9) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(10) Write 0x0 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* 3-(15) Read X1 registers to get r */ + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result1, R); + + /* + * 4. Compute s = k^-1 * (e + d * r)(mod n). If s = 0, go to step 2 + * (1) Write the curve order to N registers according + * (2) Write 0x1 to Y1 registers + * (3) Write the random integer k to X1 registers according + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set START(CRPT_ECC_CTL[0]) to 1 + * (7) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (8) Read X1 registers to get k^-1 + * (9) Write the curve order and curve length to N ,M registers + * (10) Write r, d to X1, Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Write the curve order to N registers + * (16) Write e to Y1 registers + * (17) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (18) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (19) Set START(CRPT_ECC_CTL[0]) to 1 + * (20) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (21) Write the curve order and curve length to N ,M registers + * (22) Write k^-1 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get s + */ + + /* S/W: GFp_add_mod_order(pCurve->key_len+2, 0, x1, a, R); */ + + /* 4-(1) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write 0x1 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 4-(3) Write the random integer k to X1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(k, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(7) output = %s\n", temp_hex_str); +#endif + + /* 4-(8) Read X1 registers to get k^-1 */ + + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("k^-1 = %s\n", temp_hex_str); +#endif + + /* 4-(9) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(10) Write r, d to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + } + + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + Hex2Reg(d, crpt->ECC_Y1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(14) output = %s\n", temp_hex_str); +#endif + + /* 4-(15) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(16) Write e to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + + Hex2Reg(message, crpt->ECC_Y1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(20) output = %s\n", temp_hex_str); +#endif + + /* 4-(21) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(22) Write k^-1 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(27) Read X1 registers to get s */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result2, S); + + } /* ret == 0 */ + + return ret; +} + + + +/** + * @brief ECDSA digital signature generation. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] d The private key. + * @param[in] k The selected random integer. + * @param[out] R R of the (R,S) pair digital signature + * @param[out] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,KS_MEM_Type mem_d, int32_t i32KeyIdx_d,KS_MEM_Type mem_k, int32_t i32KeyIdx_k, char *R, char *S) +{ + uint32_t volatile temp_result1[18], temp_result2[18]; + int32_t i, ret = 0; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + CRPT->ECC_KSCTL = 0; + CRPT->ECC_KSXY = 0; + + /* + * 1. Calculate e = HASH(m), where HASH is a cryptographic hashing algorithm, (i.e. SHA-1) + * (1) Use SHA to calculate e + */ + + /* 2. Select a random integer k form [1, n-1] + * (1) Notice that n is order, not prime modulus or irreducible polynomial function + */ + + /* + * 3. Compute r = x1 (mod n), where (x1, y1) = k * G. If r = 0, go to step 2 + * (1) Write the curve parameter A, B, and curve length M to corresponding registers + * (2) Write the prime modulus or irreducible polynomial function to N registers according + * (3) Write the point G(x, y) to X1, Y1 registers + * (4) Write the random integer k to K register + * (5) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Write the curve order and curve length to N ,M registers according + * (10) Write 0x0 to Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 * + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Read X1 registers to get r + */ + + /* 3-(4) Use k in Key Store */ + crpt->ECC_KSCTL = (uint32_t)(mem_k << CRPT_ECC_KSCTL_RSSRCK_Pos)/* KS Memory Type */ | + CRPT_ECC_KSCTL_RSRCK_Msk/* Key from KS */ | + (uint32_t)i32KeyIdx_k; + + run_ecc_codec(crpt, ECCOP_POINT_MUL | OP_ECDSAR); + + /* 3-(9) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(10) Write 0x0 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* 3-(15) Read X1 registers to get r */ + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result1, R); + + + /* + * 4. Compute s = k ^-1 * (e + d * r)(mod n). If s = 0, go to step 2 + * (1) Write the curve order to N registers according + * (2) Write 0x1 to Y1 registers + * (3) Write the random integer k to X1 registers according + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set START(CRPT_ECC_CTL[0]) to 1 + * (7) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (8) Read X1 registers to get k^-1 + * (9) Write the curve order and curve length to N ,M registers + * (10) Write r, d to X1, Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Write the curve order to N registers + * (16) Write e to Y1 registers + * (17) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (18) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (19) Set START(CRPT_ECC_CTL[0]) to 1 + * (20) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (21) Write the curve order and curve length to N ,M registers + * (22) Write k^-1 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get s + */ + + /* S/W: GFp_add_mod_order(pCurve->key_len+2, 0, x1, a, R); */ + + /* 4-(1) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2)(3)(4)(5) Use d, k in Key Store */ + crpt->ECC_CTL = 0; + crpt->ECC_KSXY = CRPT_ECC_KSXY_RSRCXY_Msk | + (uint32_t)(mem_k << CRPT_ECC_KSXY_RSSRCX_Pos) | ((uint32_t)i32KeyIdx_k << CRPT_ECC_KSXY_NUMX_Pos) | // Key Store index of k + (uint32_t)(mem_d << CRPT_ECC_KSXY_RSSRCY_Pos) | ((uint32_t)i32KeyIdx_d << CRPT_ECC_KSXY_NUMY_Pos); // Key Store index of d + + // 4-5 + for(i=0; i<18; i++) + { + crpt->ECC_X2[i] = temp_result1[i]; + crpt->ECC_Y2[i] = 0; + } + Hex2Reg(message, crpt->ECC_Y2); + + run_ecc_codec(crpt, ECCOP_MODULE | OP_ECDSAS); + + /* 4-11 Read X1 registers to get s */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + Reg2Hex(pCurve->Echar, temp_result2, S); + + /* Clear KS Control */ + CRPT->ECC_KSCTL = 0; + CRPT->ECC_KSXY = 0; + + } /* ret == 0 */ + + return ret; +} + + +/** + * @brief ECDSA dogotal signature verification. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] public_k1 The public key 1. + * @param[in] public_k2 The public key 2. + * @param[in] R R of the (R,S) pair digital signature + * @param[in] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + * @return -2 Verification failed. + */ +int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, + char *public_k1, char *public_k2, char *R, char *S) +{ + uint32_t temp_result1[18], temp_result2[18]; + uint32_t temp_x[18], temp_y[18]; + int32_t i, ret = 0; + + /* + * 1. Verify that r and s are integers in the interval [1, n-1]. If not, the signature is invalid + * 2. Compute e = HASH (m), where HASH is the hashing algorithm in signature generation + * (1) Use SHA to calculate e + */ + + /* + * 3. Compute w = s^-1 (mod n) + * (1) Write the curve order to N registers + * (2) Write 0x1 to Y1 registers + * (3) Write s to X1 registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Read X1 registers to get w + */ + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + + /* 3-(1) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(2) Write 0x1 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 3-(3) Write s to X1 registers */ + for(i = 0; i < 18; i++) + { + CRPT->ECC_X1[i] = 0UL; + } + Hex2Reg(S, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + + /* 3-(9) Read X1 registers to get w */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + CRPT_DBGMSG("e = %s\n", message); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("w = %s\n", temp_hex_str); + CRPT_DBGMSG("o = %s (order)\n", pCurve->Eorder); +#endif + + /* + * 4. Compute u1 = e * w (mod n) and u2 = r * w (mod n) + * (1) Write the curve order and curve length to N ,M registers + * (2) Write e, w to X1, Y1 registers + * (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (4) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1 registers to get u1 + * (8) Write the curve order and curve length to N ,M registers + * (9) Write r, w to X1, Y1 registers + * (10) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (11) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Read X1 registers to get u2 + */ + + /* 4-(1) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write e, w to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(message, crpt->ECC_X1); + + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(7) Read X1 registers to get u1 */ + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("u1 = %s\n", temp_hex_str); +#endif + + /* 4-(8) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(9) Write r, w to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(R, crpt->ECC_X1); + + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(14) Read X1 registers to get u2 */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("u2 = %s\n", temp_hex_str); +#endif + + /* + * 5. Compute X * (x1', y1') = u1 * G + u2 * Q + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + * (3) Write u1 to K registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1, Y1 registers to get u1*G + * (8) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (9) Write the public key Q(x,y) to X1, Y1 registers + * (10) Write u2 to K registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (15) Write the result data u1*G to X2, Y2 registers + * (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10 + * (17) Set START(CRPT_ECC_CTL[0]) to 1 + * (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (19) Read X1, Y1 registers to get X *(x1', y1') + * (20) Write the curve order and curve length to N ,M registers + * (21) Write x1 * to X1 registers + * (22) Write 0x0 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get x1 * (mod n) + * + * 6. The signature is valid if x1 * = r, otherwise it is invalid + */ + + /* + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + */ + ecc_init_curve(crpt, ecc_curve); + + /* (3) Write u1 to K registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result1[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* (7) Read X1, Y1 registers to get u1*G */ + for(i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, y = %s\n", temp_hex_str); +#endif + + /* (8) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* (9) Write the public key Q(x,y) to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* (10) Write u2 to K registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + temp_result2[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, y = %s\n", temp_hex_str); +#endif + + /* (14) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* Write the result data u2*Q to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + crpt->ECC_Y1[i] = temp_result2[i]; + } + + /* (15) Write the result data u1*G to X2, Y2 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X2[i] = temp_x[i]; + crpt->ECC_Y2[i] = temp_y[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_ADD); + + /* (19) Read X1, Y1 registers to get X * (x1', y1') */ + for(i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(19) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(19) y' = %s\n", temp_hex_str); +#endif + + /* (20) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* + * (21) Write x1 * to X1 registers + * (22) Write 0x0 to Y1 registers + */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_x[i]; + crpt->ECC_Y1[i] = 0UL; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(21) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, temp_hex_str); + CRPT_DBGMSG("5-(22) y' = %s\n", temp_hex_str); +#endif + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* (27) Read X1 registers to get x1 * (mod n) */ + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str); + + /* 6. The signature is valid if x1 * = r, otherwise it is invalid */ + + /* Compare with test pattern to check if r is correct or not */ + if(strcasecmp(temp_hex_str, R) != 0) + { + CRPT_DBGMSG("x1' (mod n) != R Test filed!!\n"); + CRPT_DBGMSG("Signature R [%s] is not matched with expected R [%s]!\n", temp_hex_str, R); + ret = -2; + } + } /* ret == 0 */ + + return ret; +} + + + +/** + * @brief ECDSA signature verification with Key Store + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] public_k1 The public key 1. + * @param[in] public_k2 The public key 2. + * @param[in] R R of the (R,S) pair digital signature + * @param[in] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + * @return -2 Verification failed. + */ +int32_t ECC_VerifySignature_KS(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,KS_MEM_Type mem_pk1, int32_t i32KeyIdx_pk1,KS_MEM_Type mem_pk2, int32_t i32KeyIdx_pk2, char *R, char *S) +{ + uint32_t temp_result1[18], temp_result2[18]; + uint32_t temp_x[18], temp_y[18]; + int32_t i, ret = 0; + + /* + * 1. Verify that r and s are integers in the interval [1, n-1]. If not, the signature is invalid + * 2. Compute e = HASH (m), where HASH is the hashing algorithm in signature generation + * (1) Use SHA to calculate e + */ + + /* + * 3. Compute w = s^-1 (mod n) + * (1) Write the curve order to N registers + * (2) Write 0x1 to Y1 registers + * (3) Write s to X1 registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Read X1 registers to get w + */ + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + crpt->ECC_KSCTL = 0; + crpt->ECC_KSXY = 0; + + /* 3-(1) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(2) Write 0x1 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 3-(3) Write s to X1 registers */ + for(i = 0; i < 18; i++) + { + CRPT->ECC_X1[i] = 0UL; + } + Hex2Reg(S, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + + /* 3-(9) Read X1 registers to get w */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + CRPT_DBGMSG("e = %s\n", message); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("w = %s\n", temp_hex_str); + CRPT_DBGMSG("o = %s (order)\n", pCurve->Eorder); +#endif + + /* + * 4. Compute u1 = e * w (mod n) and u2 = r * w (mod n) + * (1) Write the curve order and curve length to N ,M registers + * (2) Write e, w to X1, Y1 registers + * (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (4) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1 registers to get u1 + * (8) Write the curve order and curve length to N ,M registers + * (9) Write r, w to X1, Y1 registers + * (10) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (11) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Read X1 registers to get u2 + */ + + /* 4-(1) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write e, w to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(message, crpt->ECC_X1); + + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(7) Read X1 registers to get u1 */ + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("u1 = %s\n", temp_hex_str); +#endif + + /* 4-(8) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(9) Write r, w to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(R, crpt->ECC_X1); + + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(14) Read X1 registers to get u2 */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("u2 = %s\n", temp_hex_str); +#endif + + /* + * 5. Compute X * (x1', y1') = u1 * G + u2 * Q + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + * (3) Write u1 to K registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1, Y1 registers to get u1*G + * (8) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (9) Write the public key Q(x,y) to X1, Y1 registers + * (10) Write u2 to K registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (15) Write the result data u1*G to X2, Y2 registers + * (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10 + * (17) Set START(CRPT_ECC_CTL[0]) to 1 + * (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (19) Read X1, Y1 registers to get X * (x1', y1') + * (20) Write the curve order and curve length to N ,M registers + * (21) Write x1 * to X1 registers + * (22) Write 0x0 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get x1 * (mod n) + * + * 6. The signature is valid if x1 * = r, otherwise it is invalid + */ + + /* + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + */ + ecc_init_curve(crpt, ecc_curve); + + /* (3) Write u1 to K registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result1[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* (7) Read X1, Y1 registers to get u1*G */ + for(i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, y = %s\n", temp_hex_str); +#endif + + /* (8) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* (9) Write the public key Q(x,y) to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + +#if 0 + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); +#else + + /* 5-(2) Get the public key from key store */ + crpt->ECC_KSCTL = 0ul; + crpt->ECC_KSXY = CRPT_ECC_KSXY_RSRCXY_Msk | + (uint32_t)(mem_pk1 << CRPT_ECC_KSXY_RSSRCX_Pos) | ((uint32_t)i32KeyIdx_pk1 << CRPT_ECC_KSXY_NUMX_Pos) | // Key Store index of pk1 + (uint32_t)(mem_pk2 << CRPT_ECC_KSXY_RSSRCY_Pos) | ((uint32_t)i32KeyIdx_pk2 << CRPT_ECC_KSXY_NUMY_Pos); // Key Store index of pk2 + +#endif + + /* (10) Write u2 to K registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + temp_result2[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, y = %s\n", temp_hex_str); +#endif + + /* (14) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* Write the result data u2*Q to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + crpt->ECC_Y1[i] = temp_result2[i]; + } + + /* (15) Write the result data u1*G to X2, Y2 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X2[i] = temp_x[i]; + crpt->ECC_Y2[i] = temp_y[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_ADD); + + /* (19) Read X1, Y1 registers to get X * (x1', y1') */ + for(i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(19) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(19) y' = %s\n", temp_hex_str); +#endif + + /* (20) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* + * (21) Write x1 * to X1 registers + * (22) Write 0x0 to Y1 registers + */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_x[i]; + crpt->ECC_Y1[i] = 0UL; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(21) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, temp_hex_str); + CRPT_DBGMSG("5-(22) y' = %s\n", temp_hex_str); +#endif + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* (27) Read X1 registers to get x1 * (mod n) */ + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str); + + /* 6. The signature is valid if x1 * = r, otherwise it is invalid */ + + /* Compare with test pattern to check if r is correct or not */ + if(strcasecmp(temp_hex_str, R) != 0) + { + CRPT_DBGMSG("x1' (mod n) != R Test filed!!\n"); + CRPT_DBGMSG("Signature R [%s] is not matched with expected R [%s]!\n", temp_hex_str, R); + ret = -2; + } + } /* ret == 0 */ + + return ret; +} + + +static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve) +{ + uint32_t i; + ECC_CURVE *ret = NULL; + + for(i = 0UL; i < sizeof(_Curve) / sizeof(ECC_CURVE); i++) + { + if(ecc_curve == _Curve[i].curve_id) + { + memcpy((char *)&Curve_Copy, &_Curve[i], sizeof(ECC_CURVE)); + ret = &Curve_Copy; /* (ECC_CURVE *)&_Curve[i]; */ + } + if(ret != NULL) + { + break; + } + } + return ret; +} + + +/** + * @brief ECC interrupt service routine. User application must invoke this function in + * his CRYPTO_IRQHandler() to let Crypto driver know ECC processing was done. + * @param[in] crpt Reference to Crypto module. + * @return none + */ +void ECC_Complete(CRPT_T *crpt) +{ + if (crpt->INTSTS & CRPT_INTSTS_ECCIF_Msk) + { + g_ECC_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCIF_Msk; + /* printf("ECC done IRQ.\n"); */ + } + + if (crpt->INTSTS & CRPT_INTSTS_ECCEIF_Msk) + { + g_ECCERR_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCEIF_Msk; + printf("ECCEIF flag is set!!\n"); + } +} + + +int32_t ECC_GetCurve(CRPT_T *crpt, E_ECC_CURVE ecc_curve, ECC_CURVE *curve) +{ + int32_t err; + + /* Update pCurve pointer */ + err = ecc_init_curve(crpt, ecc_curve); + if(err == 0) + { + /* get curve */ + memcpy(curve, pCurve, sizeof(ECC_CURVE)); + } + + return err; +} + + +/*-----------------------------------------------------------------------------------------------*/ +/* */ +/* RSA */ +/* */ +/*-----------------------------------------------------------------------------------------------*/ + +/** @cond HIDDEN_SYMBOLS */ + +static void *s_pRSABuf; +static uint32_t s_u32RsaOpMode; + +typedef enum +{ + BUF_NORMAL, + BUF_CRT, + BUF_CRTBYPASS, + BUF_SCAP, + BUF_CRT_SCAP, + BUF_CRTBYPASS_SCAP, + BUF_KS +} E_RSA_BUF_SEL; + +static int32_t CheckRsaBufferSize(uint32_t u32OpMode, uint32_t u32BufSize, uint32_t u32UseKS); + +/** @endcond HIDDEN_SYMBOLS */ + +/* Check the allocated buffer size for RSA operation. */ +static int32_t CheckRsaBufferSize(uint32_t u32OpMode, uint32_t u32BufSize, uint32_t u32UseKS) +{ + /* RSA buffer size for MODE_NORMAL, MODE_CRT, MODE_CRTBYPASS, MODE_SCAP, MODE_CRT_SCAP, MODE_CRTBYPASS_SCAP */ + uint32_t s_au32RsaBufSizeTbl[] = {sizeof(RSA_BUF_NORMAL_T), sizeof(RSA_BUF_CRT_T), sizeof(RSA_BUF_CRT_T), \ + sizeof(RSA_BUF_SCAP_T), sizeof(RSA_BUF_CRT_SCAP_T), sizeof(RSA_BUF_CRT_SCAP_T), \ + sizeof(RSA_BUF_KS_T)}; + + if (u32UseKS) + { + if (u32BufSize != s_au32RsaBufSizeTbl[BUF_KS]) + return (-1); + } + else + { + switch(u32OpMode) + { + case RSA_MODE_NORMAL: + if (u32BufSize != s_au32RsaBufSizeTbl[BUF_NORMAL]) + return (-1); + break; + case RSA_MODE_CRT: + if (u32BufSize != s_au32RsaBufSizeTbl[BUF_CRT]) + return (-1); + break; + case RSA_MODE_CRTBYPASS: + if (u32BufSize != s_au32RsaBufSizeTbl[BUF_CRTBYPASS]) + return (-1); + break; + case RSA_MODE_SCAP: + if (u32BufSize != s_au32RsaBufSizeTbl[BUF_SCAP]) + return (-1); + break; + case RSA_MODE_CRT_SCAP: + if (u32BufSize != s_au32RsaBufSizeTbl[BUF_CRT_SCAP]) + return (-1); + break; + case RSA_MODE_CRTBYPASS_SCAP: + if (u32BufSize != s_au32RsaBufSizeTbl[BUF_CRTBYPASS_SCAP]) + return (-1); + break; + default: + return (-1); + } + } + + return 0; +} + +/** + * @brief Open RSA encrypt/decrypt function. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32OpMode RSA operation mode, including: + * - \ref RSA_MODE_NORMAL + * - \ref RSA_MODE_CRT + * - \ref RSA_MODE_CRTBYPASS + * - \ref RSA_MODE_SCAP + * - \ref RSA_MODE_CRT_SCAP + * - \ref RSA_MODE_CRTBYPASS_SCAP + * @param[in] u32KeySize is RSA key size, including: + * - \ref RSA_KEY_SIZE_1024 + * - \ref RSA_KEY_SIZE_2048 + * - \ref RSA_KEY_SIZE_3072 + * - \ref RSA_KEY_SIZE_4096 + * @param[in] psRSA_Buf The pointer of RSA buffer struct. User should declare correct RSA buffer for specific operation mode first. + * - \ref RSA_BUF_NORMAL_T The struct for normal mode + * - \ref RSA_BUF_CRT_T The struct for CRT ( + CRT bypass) mode + * - \ref RSA_BUF_SCAP_T The struct for SCAP mode + * - \ref RSA_BUF_CRT_SCAP_T The struct for CRT ( + CRT bypass) +SCAP mode + * - \ref RSA_BUF_KS_T The struct for using key store + * @param[in] u32BufSize is RSA buffer size. + * @param[in] u32UseKS is use key store function. + * - \ref 0 No use key store function + * - \ref 1 Use key store function + * @return 0 Success. + * @return -1 The value of pointer of RSA buffer struct is null. + */ +int32_t RSA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32KeySize, \ + void *psRSA_Buf, uint32_t u32BufSize, uint32_t u32UseKS) +{ + if(psRSA_Buf == 0) + { + return (-1); + } + if (CheckRsaBufferSize(u32OpMode, u32BufSize, u32UseKS) != 0) + { + return (-1); + } + + s_u32RsaOpMode = u32OpMode; + s_pRSABuf = psRSA_Buf; + crpt->RSA_CTL = (u32OpMode) | (u32KeySize << CRPT_RSA_CTL_KEYLENG_Pos); + + return 0; +} + +/** + * @brief Set the RSA key + * @param[in] crpt The pointer of CRYPTO module + * @param[in] Key The private or public key. + * @return 0 Success. + * @return -1 The value of pointer of RSA buffer struct is null. + */ +int32_t RSA_SetKey(CRPT_T *crpt, char *Key) +{ + if(s_pRSABuf == 0) + { + return (-1); + } + Hex2Reg(Key, ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaE); + crpt->RSA_SADDR[2] = (uint32_t)&((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaE; /* the public key or private key */ + + return 0; +} + +/** + * @brief Set RSA DMA transfer configuration. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] Src RSA DMA source data + * @param[in] n The modulus for both the public and private keys + * @param[in] P The factor of modulus operation(P) for CRT/SCAP mode + * @param[in] Q The factor of modulus operation(Q) for CRT/SCAP mode + * @return 0 Success. + * @return -1 The value of pointer of RSA buffer struct is null. + */ +int32_t RSA_SetDMATransfer(CRPT_T *crpt, char *Src, char *n, char *P, char *Q) +{ + if(s_pRSABuf == 0) + { + return (-1); + } + Hex2Reg(Src, ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaM); + Hex2Reg(n, ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaN); + + /* Assign the data to DMA */ + crpt->RSA_SADDR[0] = (uint32_t)&((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaM; /* plaintext / encrypt data */ + crpt->RSA_SADDR[1] = (uint32_t)&((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaN; /* the base of modulus operation */ + crpt->RSA_DADDR = (uint32_t)&((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaOutput; /* encrypt data / decrypt data */ + + if ((s_u32RsaOpMode & CRPT_RSA_CTL_CRT_Msk) && (s_u32RsaOpMode & CRPT_RSA_CTL_SCAP_Msk)) + { + /* For RSA CRT/SCAP mode, two primes of private key */ + Hex2Reg(P, ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaP); + Hex2Reg(Q, ((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaQ); + + crpt->RSA_SADDR[3] = (uint32_t)&((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaP; /* prime P */ + crpt->RSA_SADDR[4] = (uint32_t)&((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaQ; /* prime Q */ + + crpt->RSA_MADDR[0] = (uint32_t)&((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpCp; /* for storing the intermediate temporary value(Cp) */ + crpt->RSA_MADDR[1] = (uint32_t)&((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpCq; /* for storing the intermediate temporary value(Cq) */ + crpt->RSA_MADDR[2] = (uint32_t)&((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpDp; /* for storing the intermediate temporary value(Dp) */ + crpt->RSA_MADDR[3] = (uint32_t)&((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpDq; /* for storing the intermediate temporary value(Dq) */ + crpt->RSA_MADDR[4] = (uint32_t)&((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpRp; /* for storing the intermediate temporary value(Rp) */ + crpt->RSA_MADDR[5] = (uint32_t)&((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpRq; /* for storing the intermediate temporary value(Rq) */ + + /* For SCAP mode to store the intermediate temporary value(blind key) */ + crpt->RSA_MADDR[6] = (uint32_t)&((RSA_BUF_CRT_SCAP_T *)s_pRSABuf)->au32RsaTmpBlindKey; + } + else if (s_u32RsaOpMode & CRPT_RSA_CTL_CRT_Msk) + { + /* For RSA CRT/SCAP mode, two primes of private key */ + Hex2Reg(P, ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaP); + Hex2Reg(Q, ((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaQ); + + crpt->RSA_SADDR[3] = (uint32_t)&((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaP; /* prime P */ + crpt->RSA_SADDR[4] = (uint32_t)&((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaQ; /* prime Q */ + + crpt->RSA_MADDR[0] = (uint32_t)&((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpCp; /* for storing the intermediate temporary value(Cp) */ + crpt->RSA_MADDR[1] = (uint32_t)&((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpCq; /* for storing the intermediate temporary value(Cq) */ + crpt->RSA_MADDR[2] = (uint32_t)&((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpDp; /* for storing the intermediate temporary value(Dp) */ + crpt->RSA_MADDR[3] = (uint32_t)&((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpDq; /* for storing the intermediate temporary value(Dq) */ + crpt->RSA_MADDR[4] = (uint32_t)&((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpRp; /* for storing the intermediate temporary value(Rp) */ + crpt->RSA_MADDR[5] = (uint32_t)&((RSA_BUF_CRT_T *)s_pRSABuf)->au32RsaTmpRq; /* for storing the intermediate temporary value(Rq) */ + } + else if (s_u32RsaOpMode & CRPT_RSA_CTL_SCAP_Msk) + { + /* For RSA CRT/SCAP mode, two primes of private key */ + Hex2Reg(P, ((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaP); + Hex2Reg(Q, ((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaQ); + + crpt->RSA_SADDR[3] = (uint32_t)&((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaP; /* prime P */ + crpt->RSA_SADDR[4] = (uint32_t)&((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaQ; /* prime Q */ + + /* For SCAP mode to store the intermediate temporary value(blind key) */ + crpt->RSA_MADDR[6] = (uint32_t)&((RSA_BUF_SCAP_T *)s_pRSABuf)->au32RsaTmpBlindKey; + } + + return 0; +} + +/** + * @brief Start RSA encrypt/decrypt + * @param[in] crpt The pointer of CRYPTO module + * @return None + */ +void RSA_Start(CRPT_T *crpt) +{ + crpt->RSA_CTL |= CRPT_RSA_CTL_START_Msk; +} + +/** + * @brief Read the RSA output. + * @param[in] crpt The pointer of CRYPTO module + * @param[out] Output The RSA operation output data. + * @return 0 Success. + * @return -1 The value of pointer of RSA buffer struct is null. + */ +int32_t RSA_Read(CRPT_T *crpt, char *Output) +{ + if(s_pRSABuf == 0) + { + return (-1); + } + uint32_t au32CntTbl[4] = {256, 512, 768, 1024}; /* count is key length divided by 4 */ + uint32_t u32CntIdx = 0; + + u32CntIdx = (crpt->RSA_CTL & CRPT_RSA_CTL_KEYLENG_Msk) >> CRPT_RSA_CTL_KEYLENG_Pos; + Reg2Hex((int32_t)au32CntTbl[u32CntIdx], ((RSA_BUF_NORMAL_T *)s_pRSABuf)->au32RsaOutput, Output); + + return 0; +} + +/** + * @brief Set the RSA key is read from key store + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32KeyNum The number of private or public key in key store. + * @param[in] u32KSMemType The key is read from selected memory type of key store. It could be: + \ref KS_SRAM + \ref KS_FLASH + \ref KS_OTP + * @param[in] u32BlindKeyNum The number of blind key in SRAM of key store for SCAP mode. This key is un-readable. + * @return 0 Success. + * @return -1 The value of pointer of RSA buffer struct is null. + */ +int32_t RSA_SetKey_KS(CRPT_T *crpt, uint32_t u32KeyNum, uint32_t u32KSMemType, uint32_t u32BlindKeyNum) +{ + if (s_u32RsaOpMode & CRPT_RSA_CTL_SCAP_Msk) + { + crpt->RSA_KSCTL = (u32BlindKeyNum << 8) | (u32KSMemType << CRPT_RSA_KSCTL_RSSRC_Pos) | CRPT_RSA_KSCTL_RSRC_Msk | u32KeyNum; + } + else + { + crpt->RSA_KSCTL = (u32KSMemType << CRPT_RSA_KSCTL_RSSRC_Pos) | CRPT_RSA_KSCTL_RSRC_Msk | u32KeyNum; + } + return 0; +} + +/** + * @brief Set RSA DMA transfer configuration while using key store. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32OpMode RSA operation mode, including: + * - \ref RSA_MODE_NORMAL + * - \ref RSA_MODE_CRT + * - \ref RSA_MODE_CRTBYPASS + * - \ref RSA_MODE_SCAP + * - \ref RSA_MODE_CRT_SCAP + * - \ref RSA_MODE_CRTBYPASS_SCAP + * @param[in] Src RSA DMA source data + * @param[in] n The modulus for both the public and private keys + * @param[in] u32PNum The number of the factor of modulus operation(P) in SRAM of key store for CRT/SCAP mode + * @param[in] u32QNum The number of the factor of modulus operation(Q) in SRAM of key store for CRT/SCAP mode + * @param[in] u32CpNum The number of Cp in SRAM of key store for CRT mode + * @param[in] u32CqNum The number of Cq in SRAM of key store for CRT mode + * @param[in] u32DpNum The number of Dp in SRAM of key store for CRT mode + * @param[in] u32DqNum The number of Dq in SRAM of key store for CRT mode + * @param[in] u32RpNum The number of Rp in SRAM of key store for CRT mode + * @param[in] u32RqNum The number of Rq in SRAM of key store for CRT mode + * @return 0 Success. + * @return -1 The value of pointer of RSA buffer struct is null. + * @note P, Q, Dp, Dq are equal to half key length. Cp, Cq, Rp, Rq, Blind key are equal to key length. + */ +int32_t RSA_SetDMATransfer_KS(CRPT_T *crpt, char *Src, char *n, uint32_t u32PNum, + uint32_t u32QNum, uint32_t u32CpNum, uint32_t u32CqNum, uint32_t u32DpNum, + uint32_t u32DqNum, uint32_t u32RpNum, uint32_t u32RqNum) +{ + if(s_pRSABuf == 0) + { + return (-1); + } + Hex2Reg(Src, ((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaM); + Hex2Reg(n, ((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaN); + + /* Assign the data to DMA */ + crpt->RSA_SADDR[0] = (uint32_t)&((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaM; /* plaintext / encrypt data */ + crpt->RSA_SADDR[1] = (uint32_t)&((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaN; /* the base of modulus operation */ + crpt->RSA_DADDR = (uint32_t)&((RSA_BUF_KS_T *)s_pRSABuf)->au32RsaOutput; /* encrypt data / decrypt data */ + + if ((s_u32RsaOpMode & CRPT_RSA_CTL_CRT_Msk) || (s_u32RsaOpMode & CRPT_RSA_CTL_SCAP_Msk)) + { + /* For RSA CRT/SCAP mode, two primes of private key */ + crpt->RSA_KSSTS[0] = (crpt->RSA_KSSTS[0] & (~(CRPT_RSA_KSSTS0_NUM0_Msk | CRPT_RSA_KSSTS0_NUM1_Msk))) | \ + (u32PNum << CRPT_RSA_KSSTS0_NUM0_Pos) | (u32QNum << CRPT_RSA_KSSTS0_NUM1_Pos); + + } + if (s_u32RsaOpMode & CRPT_RSA_CTL_CRT_Msk) + { + /* For RSA CRT mode, Cp, Cq, Dp, Dq, Rp, Rq */ + crpt->RSA_KSSTS[0] = (crpt->RSA_KSSTS[0] & (~(CRPT_RSA_KSSTS0_NUM2_Msk | CRPT_RSA_KSSTS0_NUM3_Msk))) | \ + (u32CpNum << CRPT_RSA_KSSTS0_NUM2_Pos) | (u32CqNum << CRPT_RSA_KSSTS0_NUM3_Pos); + crpt->RSA_KSSTS[1] = (u32DpNum << CRPT_RSA_KSSTS1_NUM4_Pos) | (u32DqNum << CRPT_RSA_KSSTS1_NUM5_Pos) | \ + (u32RpNum << CRPT_RSA_KSSTS1_NUM6_Pos) | (u32RqNum << CRPT_RSA_KSSTS1_NUM7_Pos); + } + + return 0; +} + + +/**@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group CRYPTO_Driver */ + +/**@}*/ /* end of group Standard_Driver */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_dac.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_dac.c new file mode 100644 index 0000000000..6007ce667a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_dac.c @@ -0,0 +1,94 @@ +/**************************************************************************//** + * @file dac.c + * @version V1.00 + * @brief M2354 series DAC driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + +/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions + @{ +*/ + +/** + * @brief This function make DAC module be ready to convert. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2354 Series DAC. + * @param[in] u32TrgSrc Decides the trigger source. Valid values are: + * - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger + * - \ref DAC_SOFTWARE_TRIGGER :Software trigger + * - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger + * - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger + * - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger + * - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger + * - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger + * - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger + * - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger + * - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger + * - \ref DAC_EPWM0_TRIGGER :EPWM0 trigger + * - \ref DAC_EPWM1_TRIGGER :EPWM1 trigger + * @return None + * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger. + * When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register. + * When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1, + * external STDAC pin, timer event, or EPWM event. + */ +void DAC_Open(DAC_T *dac, + uint32_t u32Ch, + uint32_t u32TrgSrc) +{ + (void)u32Ch; + dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk); + + dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk); +} + +/** + * @brief Disable DAC analog power. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2354 Series DAC. + * @return None + * @details Disable DAC analog power for saving power consumption. + */ +void DAC_Close(DAC_T *dac, uint32_t u32Ch) +{ + (void)u32Ch; + dac->CTL &= (~DAC_CTL_DACEN_Msk); +} + +/** + * @brief Set delay time for DAC to become stable. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds. + * @return Real DAC conversion settling time (micro second). + * @details For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0x40. + * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed. + */ +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay) +{ + + dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL); + + return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq()); +} + + + +/**@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group DAC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_dpm.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_dpm.c new file mode 100644 index 0000000000..628b222467 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_dpm.c @@ -0,0 +1,410 @@ +/**************************************************************************//** + * @file dpm.c + * @version V3.00 + * @brief Debug Protection Mechanism (DPM) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DPM_Driver DPM Driver + @{ +*/ + +/** @addtogroup DPM_EXPORTED_FUNCTIONS DPM Exported Functions + @{ +*/ + +/** + * @brief Set Debug Disable + * @param[in] u32dpm The pointer of the specified DPM module + * - \ref SECURE_DPM + * - \ref NONSECURE_DPM + * @return None + * @details This macro sets Secure or Non-secure DPM debug disable. + * The debug disable function works after reset (chip reset or pin reset). + */ +void DPM_SetDebugDisable(uint32_t u32dpm) +{ + DPM_T *dpm; + + if(__PC()&NS_OFFSET) dpm = DPM_NS; + else dpm = DPM; + + if(u32dpm==SECURE_DPM) /* Secure DPM */ + { + while(dpm->STS & DPM_STS_BUSY_Msk); + dpm->CTL = (DPM->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE|DPM_CTL_DBGDIS_Msk); + } + else /* Non-secure DPM */ + { + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + dpm->NSCTL = (dpm->NSCTL & (~DPM_NSCTL_WVCODE_Msk)) | (DPM_NSCTL_WVCODE|DPM_NSCTL_DBGDIS_Msk); + } +} + +/** + * @brief Set Debug Lock + * @param[in] u32dpm Select DPM module. Valid values are: + * - \ref SECURE_DPM + * - \ref NONSECURE_DPM + * @return None + * @details This macro sets Secure or Non-secure DPM debug lock. + * The debug lock function works after reset (chip reset or pin reset). + */ +void DPM_SetDebugLock(uint32_t u32dpm) +{ + DPM_T *dpm; + + if(__PC()&NS_OFFSET) dpm = DPM_NS; + else dpm = DPM; + + if(u32dpm==SECURE_DPM) /* Secure DPM */ + { + while(dpm->STS & DPM_STS_BUSY_Msk); + dpm->CTL = (dpm->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE|DPM_CTL_LOCK_Msk); + } + else /* Non-secure DPM */ + { + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + dpm->NSCTL = (dpm->NSCTL & (~DPM_NSCTL_WVCODE_Msk)) | (DPM_NSCTL_WVCODE|DPM_NSCTL_LOCK_Msk); + } +} + +/** + * @brief Get Debug Disable + * @param[in] u32dpm Select DPM module. Valid values are: + * - \ref SECURE_DPM + * - \ref NONSECURE_DPM + * @retval 0 Debug is not in disable status + * @retval 1 Debug is in disable status + * @details This macro gets Secure or Non-secure DPM debug disable status. + * If Secure debug is disabled, debugger cannot access Secure region and can access Non-secure region only. + * If Non-secure debug is disabled, debugger cannot access all Secure and Non-secure region. + */ +uint32_t DPM_GetDebugDisable(uint32_t u32dpm) +{ + uint32_t u32RetVal = 0; + DPM_T *dpm; + + if(__PC()&NS_OFFSET) dpm = DPM_NS; + else dpm = DPM; + + if(u32dpm==SECURE_DPM) /* Secure DPM */ + { + while(dpm->STS & DPM_STS_BUSY_Msk); + u32RetVal = (dpm->STS & DPM_STS_DBGDIS_Msk)>>DPM_STS_DBGDIS_Pos; + } + else /* Non-secure DPM */ + { + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + u32RetVal = (dpm->NSSTS & DPM_NSSTS_DBGDIS_Msk)>>DPM_NSSTS_DBGDIS_Pos; + } + + return u32RetVal; +} + +/** + * @brief Get Debug Lock + * @param[in] u32dpm Select DPM module. Valid values are: + * - \ref SECURE_DPM + * - \ref NONSECURE_DPM + * @retval 0 Debug is not in lock status + * @retval 1 Debug is in lock status + * @details This macro gets Secure or Non-secure DPM debug disable status. + * If Secure debug is locked, debugger cannot access Secure region and can access Non-secure region only. + * If Non-secure debug is locked, debugger cannot access all Secure and Non-secure region. + */ +uint32_t DPM_GetDebugLock(uint32_t u32dpm) +{ + uint32_t u32RetVal = 0; + DPM_T *dpm; + + if(__PC()&NS_OFFSET) dpm = DPM_NS; + else dpm = DPM; + + if(u32dpm==SECURE_DPM) /* Secure DPM */ + { + while(dpm->STS & DPM_STS_BUSY_Msk); + u32RetVal = (dpm->STS & DPM_STS_LOCK_Msk)>>DPM_STS_LOCK_Pos; + } + else /* Non-secure DPM */ + { + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + u32RetVal = (dpm->NSSTS & DPM_NSSTS_LOCK_Msk)>>DPM_NSSTS_LOCK_Pos; + } + + return u32RetVal; +} + +/** + * @brief Update DPM Password + * @param[in] u32dpm Select DPM module. Valid values are: + * - \ref SECURE_DPM + * - \ref NONSECURE_DPM + * @param[in] au32Password Password length is 256 bits. + * @retval 0 No password is updated. The password update count has reached the maximum value. + * @retval 1 Password update is successful. + * @details This macro updates Secure or Non-secure DPM password. + */ +uint32_t DPM_SetPasswordUpdate(uint32_t u32dpm, uint32_t au32Pwd[]) +{ + uint32_t u32i, u32RetVal=0; + DPM_T *dpm; + + if(__PC()&NS_OFFSET) dpm = DPM_NS; + else dpm = DPM; + + if(u32dpm==SECURE_DPM) /* Secure DPM */ + { + /* Set Secure DPM password */ + for(u32i=0; u32i<4; u32i++) + { + while(dpm->STS & DPM_STS_BUSY_Msk); + dpm->SPW[u32i] = au32Pwd[u32i]; + } + + /* Set Secure DPM password update */ + while(dpm->STS & DPM_STS_BUSY_Msk); + dpm->CTL = (dpm->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE|DPM_CTL_PWUPD_Msk); + + /* Check Secure DPM password update flag */ + while(dpm->STS & DPM_STS_BUSY_Msk); + u32RetVal = (dpm->STS & DPM_STS_PWUOK_Msk)>>DPM_STS_PWUOK_Pos; + + /* Clear Secure DPM password update flag */ + if(u32RetVal) dpm->STS = DPM_STS_PWUOK_Msk; + } + else /* Non-secure DPM */ + { + /* Set Non-secure DPM password */ + for(u32i=0; u32i<4; u32i++) + { + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + dpm->NSPW[u32i] = au32Pwd[u32i]; + } + + /* Set Non-secure DPM password update */ + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + dpm->NSCTL = (dpm->NSCTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE|DPM_NSCTL_PWUPD_Msk); + + /* Check Non-secure DPM password update flag */ + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + u32RetVal = (dpm->NSSTS & DPM_NSSTS_PWUOK_Msk)>>DPM_NSSTS_PWUOK_Pos; + + /* Clear Non-secure DPM password update flag */ + if(u32RetVal) dpm->NSSTS = DPM_NSSTS_PWUOK_Msk; + } + + return u32RetVal; +} + +/** + * @brief Compare DPM Password + * @param[in] u32dpm Select DPM module. Valid values are: + * - \ref SECURE_DPM + * - \ref NONSECURE_DPM + * @retval 0 The password comparison can be proccessed. + * @retval 1 No more password comparison can be proccessed. \n + * The password comparison fail times has reached the maximum value. + * @details This macro sets Secure or Non-secure DPM password comparison. \n + * The comparison result is checked by DPM_GetPasswordErrorFlag(). + */ +uint32_t DPM_SetPasswordCompare(uint32_t u32dpm, uint32_t au32Pwd[]) +{ + uint32_t u32i, u32RetVal=0; + DPM_T *dpm; + + if(__PC()&NS_OFFSET) dpm = DPM_NS; + else dpm = DPM; + + if(u32dpm==SECURE_DPM) /* Secure DPM */ + { + /* Check Secure DPM password compare fail times maximum flag */ + while(dpm->STS & DPM_STS_BUSY_Msk); + if(dpm->STS & DPM_STS_PWFMAX_Msk) + { + u32RetVal=1; + } + else + { + /* Set Secure DPM password */ + for(u32i=0; u32i<4; u32i++) + { + while(dpm->STS & DPM_STS_BUSY_Msk); + dpm->SPW[u32i] = au32Pwd[u32i]; + } + + /* Set Secure DPM password cpmpare */ + while(dpm->STS & DPM_STS_BUSY_Msk); + dpm->CTL = (dpm->CTL & (~DPM_CTL_WVCODE_Msk)) | (DPM_CTL_WVCODE|DPM_CTL_PWCMP_Msk); + } + } + else /* Non-secure DPM */ + { + /* Check Non-secure DPM password compare fail times maximum flag */ + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + if(dpm->NSSTS & DPM_NSSTS_PWFMAX_Msk) + { + u32RetVal=1; + } + else + { + /* Set Non-secure DPM password */ + for(u32i=0; u32i<4; u32i++) + { + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + dpm->NSPW[u32i] = au32Pwd[u32i]; + } + + /* Set Non-secure DPM password compare */ + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + dpm->NSCTL = (dpm->NSCTL & (~DPM_NSCTL_WVCODE_Msk)) | (DPM_NSCTL_WVCODE|DPM_NSCTL_PWCMP_Msk); + } + } + + return u32RetVal; +} + +/** + * @brief Get DPM Password Error Flag + * @param[in] u32dpm Select DPM module. Valid values are: + * - \ref SECURE_DPM + * - \ref NONSECURE_DPM + * @return Specified DPM module password compare error flag. + * @details This macro returns Secure or Non-secure DPM password compare error flag. + */ +uint32_t DPM_GetPasswordErrorFlag(uint32_t u32dpm) +{ + uint32_t u32RetVal=0; + DPM_T *dpm; + + if(__PC()&NS_OFFSET) dpm = DPM_NS; + else dpm = DPM; + + if(u32dpm==SECURE_DPM) /* Secure DPM */ + { + /* Check Secure DPM password compare error flag */ + while(dpm->STS & DPM_STS_BUSY_Msk); + u32RetVal = (dpm->STS & DPM_STS_PWCERR_Msk)>>DPM_STS_PWCERR_Pos; + } + else /* Non-secure DPM */ + { + /* Check Non-secure DPM password compare error flag */ + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + u32RetVal = (dpm->NSSTS & DPM_NSSTS_PWCERR_Msk)>>DPM_NSSTS_PWCERR_Pos; + } + + return u32RetVal; +} + +/** + * @brief Get DPM Interrupt Flag + * @param None + * @return Secure DPM interrupt flag. + * @details This macro returns Secure DPM interrupt flag. + * Secure DPM interrupt flag includes Secure and Non-secure DPM password compare error flag. + * This macro is for Secure DPM and Secure region only. + */ +uint32_t DPM_GetIntFlag(void) +{ + while(DPM->STS & DPM_STS_BUSY_Msk); + return (DPM->STS & DPM_STS_INT_Msk)>>DPM_STS_INT_Pos; +} + + +/** + * @brief Clear DPM Password Error Flag + * @param[in] u32dpm Select DPM module. Valid values are: + * - \ref SECURE_DPM + * - \ref NONSECURE_DPM + * @return Specified DPM module interrupt flag. + * @details This macro clears Secure or Non-secure DPM password compare error flag. + */ +void DPM_ClearPasswordErrorFlag(uint32_t u32dpm) +{ + DPM_T *dpm; + + if(__PC()&NS_OFFSET) dpm = DPM_NS; + else dpm = DPM; + + if(u32dpm==SECURE_DPM) /* Secure DPM */ + { + while(dpm->STS & DPM_STS_BUSY_Msk); + dpm->STS = DPM_STS_PWCERR_Msk; + } + else /* Non-secure DPM */ + { + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + dpm->NSSTS = DPM_NSSTS_PWCERR_Msk; + } +} + +/** + * @brief Enable Debugger Write Access + * @param[in] u32dpm Select DPM module. Valid values are: + * - \ref SECURE_DPM + * - \ref NONSECURE_DPM + * @return None. + * @details This macro enables external debugger to write Secure or Non-secure DPM registers. + */ +void DPM_EnableDebuggerWriteAccess(uint32_t u32dpm) +{ + DPM_T *dpm; + + if(__PC()&NS_OFFSET) dpm = DPM_NS; + else dpm = DPM; + + if(u32dpm==SECURE_DPM) /* Secure DPM */ + { + while(dpm->STS & DPM_STS_BUSY_Msk); + dpm->CTL = (dpm->CTL & (~(DPM_CTL_RVCODE_Msk|DPM_CTL_DACCWDIS_Msk))) | DPM_CTL_WVCODE; + } + else /* Non-secure DPM */ + { + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + dpm->NSCTL = (dpm->NSCTL & (~(DPM_NSCTL_RVCODE_Msk|DPM_NSCTL_DACCWDIS_Msk))) | DPM_NSCTL_WVCODE; + } +} + +/** + * @brief Disable Debugger Write Access + * @param[in] u32dpm Select DPM module. Valid values are: + * - \ref SECURE_DPM + * - \ref NONSECURE_DPM + * @return None. + * @details This macro disables external debugger to write Secure or Non-secure DPM registers. + */ +void DPM_DisableDebuggerWriteAccess(uint32_t u32dpm) +{ + DPM_T *dpm; + + if(__PC()&NS_OFFSET) dpm = DPM_NS; + else dpm = DPM; + + if(u32dpm==SECURE_DPM) /* Secure DPM */ + { + while(dpm->STS & DPM_STS_BUSY_Msk); + dpm->CTL = (dpm->CTL & (~DPM_CTL_RVCODE_Msk)) | (DPM_CTL_WVCODE|DPM_CTL_DACCWDIS_Msk); + } + else /* Non-secure DPM */ + { + while(dpm->NSSTS & DPM_NSSTS_BUSY_Msk); + dpm->NSCTL = (dpm->NSCTL & (~DPM_NSCTL_RVCODE_Msk)) | (DPM_NSCTL_WVCODE|DPM_NSCTL_DACCWDIS_Msk); + } +} + + +/**@}*/ /* end of group DPM_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group DPM_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_eadc.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_eadc.c new file mode 100644 index 0000000000..149a00a032 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_eadc.c @@ -0,0 +1,145 @@ +/**************************************************************************//** + * @file eadc.c + * @version V2.00 + * @brief M2354 series EADC driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions + @{ +*/ + +/** + * @brief This function make EADC_module be ready to convert. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32InputMode Decides the input mode. + * - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode. + * - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type. + * @return None + * @details This function is used to set analog input mode and enable A/D Converter. + * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1. + * @note + */ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode) +{ + eadc->CTL &= (~(EADC_CTL_DIFFEN_Msk)); + + eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk); + + while(!(eadc->PWRM & EADC_PWRM_PWUPRDY_Msk)) {} +} + +/** + * @brief Disable EADC_module. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption. + */ +void EADC_Close(EADC_T *eadc) +{ + eadc->CTL &= ~EADC_CTL_ADCEN_Msk; +} + +/** + * @brief Configure the sample control logic module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerSrc Decides the trigger source. Valid values are: + * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger + * - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger + * - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger + * - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger + * - \ref EADC_ADINT0_TRIGGER : ADC ADINT0 interrupt EOC pulse trigger + * - \ref EADC_ADINT1_TRIGGER : ADC ADINT1 interrupt EOC pulse trigger + * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger + * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger + * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger + * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger + * - \ref EADC_PWM0TG0_TRIGGER : EPWM0TG0 trigger + * - \ref EADC_PWM0TG1_TRIGGER : EPWM0TG1 trigger + * - \ref EADC_PWM0TG2_TRIGGER : EPWM0TG2 trigger + * - \ref EADC_PWM0TG3_TRIGGER : EPWM0TG3 trigger + * - \ref EADC_PWM0TG4_TRIGGER : EPWM0TG4 trigger + * - \ref EADC_PWM0TG5_TRIGGER : EPWM0TG5 trigger + * - \ref EADC_PWM1TG0_TRIGGER : EPWM1TG0 trigger + * - \ref EADC_PWM1TG1_TRIGGER : EPWM1TG1 trigger + * - \ref EADC_PWM1TG2_TRIGGER : EPWM1TG2 trigger + * - \ref EADC_PWM1TG3_TRIGGER : EPWM1TG3 trigger + * - \ref EADC_PWM1TG4_TRIGGER : EPWM1TG4 trigger + * - \ref EADC_PWM1TG5_TRIGGER : EPWM1TG5 trigger + * - \ref EADC_BPWM0TG_TRIGGER : BPWM0TG trigger + * - \ref EADC_BPWM1TG_TRIGGER : BPWM1TG trigger + * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15. + * @return None + * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source. + * sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT). + */ +void EADC_ConfigSampleModule(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerSrc, \ + uint32_t u32Channel) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk); + eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel); +} + + +/** + * @brief Set trigger delay time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF. + * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are: + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16 + * @return None + * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15). + * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period. + */ +void EADC_SetTriggerDelayTime(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerDelayTime, \ + uint32_t u32DelayClockDivider) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk); + eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider); +} + +/** + * @brief Set ADC extend sample time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF. + * @return None + * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, + * user can extend A/D sampling time after trigger source is coming to get enough sampling time. + */ +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime) +{ + eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk; + + eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos); + +} + +/**@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EADC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_ebi.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_ebi.c new file mode 100644 index 0000000000..0702610182 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_ebi.c @@ -0,0 +1,235 @@ +/**************************************************************************//** + * @file ebi.c + * @version V3.00 + * @brief External Bus Interface(EBI) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Initialize EBI for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32DataWidth Data bus width. Valid values are: + * - \ref EBI_BUSWIDTH_8BIT + * - \ref EBI_BUSWIDTH_16BIT + * @param[in] u32TimingClass Default timing configuration. Valid values are: + * - \ref EBI_TIMING_FASTEST + * - \ref EBI_TIMING_VERYFAST + * - \ref EBI_TIMING_FAST + * - \ref EBI_TIMING_NORMAL + * - \ref EBI_TIMING_SLOW + * - \ref EBI_TIMING_VERYSLOW + * - \ref EBI_TIMING_SLOWEST + * @param[in] u32BusMode Set EBI bus operate mode. Valid values are: + * - \ref EBI_OPMODE_NORMAL + * - \ref EBI_OPMODE_CACCESS + * - \ref EBI_OPMODE_ADSEPARATE + * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are: + * - \ref EBI_CS_ACTIVE_HIGH + * - \ref EBI_CS_ACTIVE_LOW + * + * @return None + * + * @details This function is used to open specify EBI bank with different bus width, timing setting and \n + * active level of CS pin to access EBI device. + * @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register. + */ +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (u32Bank * 0x10UL); + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (u32Bank * 0x10UL); + volatile uint32_t *pu32EBICTL, *pu32EBITCTL; + uint32_t pu32Index0, pu32Index1; + + if((__PC()&NS_OFFSET) == NS_OFFSET) + { + pu32Index0 = (u32Index0 | NS_OFFSET); + pu32Index1 = (u32Index1 | NS_OFFSET); + } + else + { + pu32Index0 = u32Index0; + pu32Index1 = u32Index1; + } + + pu32EBICTL = (uint32_t *)(pu32Index0); + pu32EBITCTL = (uint32_t *)(pu32Index1); + + if(u32DataWidth == EBI_BUSWIDTH_8BIT) + { + *pu32EBICTL &= ~EBI_CTL_DW16_Msk; + } + else + { + *pu32EBICTL |= EBI_CTL_DW16_Msk; + } + + *pu32EBICTL |= u32BusMode; + + switch(u32TimingClass) + { + case EBI_TIMING_FASTEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0UL; + break; + + case EBI_TIMING_VERYFAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318UL; + break; + + case EBI_TIMING_FAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0UL; + break; + + case EBI_TIMING_NORMAL: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3UL << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318UL; + break; + + case EBI_TIMING_SLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7UL << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738UL; + break; + + case EBI_TIMING_VERYSLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7UL << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738UL; + break; + + case EBI_TIMING_SLOWEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7UL << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738UL; + break; + + default: + *pu32EBICTL &= ~EBI_CTL_EN_Msk; + break; + } +} + +/** + * @brief Disable EBI on specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * + * @return None + * + * @details This function is used to close specify EBI function. + */ +void EBI_Close(uint32_t u32Bank) +{ + uint32_t u32Index = (uint32_t)&EBI->CTL0 + (u32Bank * 0x10UL); + volatile uint32_t *pu32EBICTL; + uint32_t pu32Index; + + if((__PC()&NS_OFFSET) == NS_OFFSET) + { + pu32Index = (u32Index | NS_OFFSET); + } + else + { + pu32Index = u32Index; + } + + pu32EBICTL = (uint32_t *)(pu32Index); + + *pu32EBICTL &= ~EBI_CTL_EN_Msk; +} + +/** + * @brief Set EBI Bus Timing for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting. + * @param[in] u32MclkDiv Divider for MCLK. Valid values are: + * - \ref EBI_MCLKDIV_1 + * - \ref EBI_MCLKDIV_2 + * - \ref EBI_MCLKDIV_4 + * - \ref EBI_MCLKDIV_8 + * - \ref EBI_MCLKDIV_16 + * - \ref EBI_MCLKDIV_32 + * - \ref EBI_MCLKDIV_64 + * - \ref EBI_MCLKDIV_128 + * + * @return None + * + * @details This function is used to configure specify EBI bus timing for access EBI device. + */ +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (u32Bank * 0x10UL); + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (u32Bank * 0x10UL); + volatile uint32_t *pu32EBICTL, *pu32EBITCTL; + uint32_t pu32Index0, pu32Index1; + + if((__PC()&NS_OFFSET) == NS_OFFSET) + { + pu32Index0 = (u32Index0 | NS_OFFSET); + pu32Index1 = (u32Index1 | NS_OFFSET); + } + else + { + pu32Index0 = u32Index0; + pu32Index1 = u32Index1; + } + + pu32EBICTL = (uint32_t *)(pu32Index0); + pu32EBITCTL = (uint32_t *)(pu32Index1); + + *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos); + *pu32EBITCTL = u32TimingConfig; +} + +/**@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EBI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_ecap.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_ecap.c new file mode 100644 index 0000000000..131c2ba016 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_ecap.c @@ -0,0 +1,122 @@ +/**************************************************************************//** + * @file ecap.c + * @version V3.00 + + * @brief Enhanced Input Capture Timer (ECAP) driver source file + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions + @{ +*/ + +/** + * @brief Enable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @param[in] u32FuncMask Input capture function select + * - \ref ECAP_DISABLE_COMPARE + * - \ref ECAP_COMPARE_FUNCTION + * @return None + * @details This macro enable input capture function and select compare and reload function. + */ +void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask) +{ + /* Clear Input capture mode*/ + ecap->CTL0 = ecap->CTL0 & ~(ECAP_CTL0_CMPEN_Msk); + + /* Enable Input Capture and set mode */ + ecap->CTL0 |= ECAP_CTL0_CAPEN_Msk | (u32FuncMask); +} + + + +/** + * @brief Disable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @return None + * @details This macro disable input capture function. + */ +void ECAP_Close(ECAP_T* ecap) +{ + /* Disable Input Capture*/ + ecap->CTL0 &= ~ECAP_CTL0_CAPEN_Msk; +} + +/** + * @brief This macro is used to enable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel Mask + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will enable the input channel_n interrupt. + */ +void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask) +{ + /* Enable input channel interrupt */ + ecap->CTL0 |= (u32Mask); + + /* Enable NVIC ECAP IRQ */ + if((ecap == ECAP0) || (ecap == ECAP0_NS)) + { + NVIC_EnableIRQ(ECAP0_IRQn); + } + else + { + NVIC_EnableIRQ(ECAP1_IRQn); + } +} + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel number + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will disable the input channel_n interrupt. + */ +void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask) +{ + /* Disable input channel interrupt */ + (ecap->CTL0) &= ~(u32Mask); + + /* Disable NVIC ECAP IRQ */ + if((ecap == ECAP0) || (ecap == ECAP0_NS)) + { + NVIC_DisableIRQ(ECAP0_IRQn); + } + else + { + NVIC_DisableIRQ(ECAP1_IRQn); + } +} + +/**@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group ECAP_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_epwm.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_epwm.c new file mode 100644 index 0000000000..8c6fe5b779 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_epwm.c @@ -0,0 +1,1681 @@ +/**************************************************************************//** + * @file epwm.c + * @version V3.00 + * @brief M2354 series EPWM driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + + +/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions + @{ +*/ + +/** + * @brief Configure EPWM capture and get the nearest unit time. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure EPWM capture and get the nearest unit time. + */ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32PWMClockSrc; + uint32_t u32NearestUnitTimeNsec = 0; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + uint8_t u8BreakLoop = 0U; + + (void)u32CaptureEdge; + + /* clock source is from PCLK */ + if((epwm == EPWM0) || (epwm == EPWM0_NS)) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* if((epwm == EPWM1)||(epwm == EPWM1_NS)) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + + u32PWMClockSrc /= 1000UL; + for(u32Prescale = 1U; u32Prescale <= 0x1000U; u32Prescale++) + { + u32NearestUnitTimeNsec = (1000000UL * u32Prescale) / u32PWMClockSrc; + if(u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if(u32Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */ + { + u8BreakLoop = 1U; + } + if(!((1000000UL * (u32Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc)))) + { + u8BreakLoop = 1U; + } + } + else + { + u8BreakLoop = 1U; + } + if(u8BreakLoop) + { + break; + } + } + + /* convert to real register value */ + u32Prescale = u32Prescale - 1U; + /* every two channels share a prescaler */ + EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale); + + /* set EPWM to down count type(edge aligned) */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~(EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1))) | (1UL << (u32ChannelNum << 1)); + /* set EPWM to auto-reload mode */ + (epwm)->CTL1 &= ~(EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum); + EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect + * existing frequency of other channel. + * @note This function is used for initial stage. + * To change duty cycle later, it should get the configured period value and calculate the new comparator value. + */ +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + return EPWM_ConfigOutputChannel2(epwm, u32ChannelNum, u32Frequency, u32DutyCycle * 100, 1); +} + +/** + * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32HighDutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 10000. 1000 means 10%, 2000 means 20%... + * @param[in] u32Frequency2 Target generator frequency = u32Frequency / u32Frequency2 + * @return Nearest frequency clock in nano second + * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect + * existing frequency of other channel. + * @note This function is used for initial stage. + * To change duty cycle later, it should get the configured period value and calculate the new comparator value. + */ +uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32HighDutyCycle, uint32_t u32Frequency2) +{ + uint32_t u32PWMClockSrc; + uint32_t i; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + /* clock source is from PCLK */ + if((epwm == EPWM0) || (epwm == EPWM0_NS)) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* if((epwm == EPWM1)||(epwm == EPWM1_NS)) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + + for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++)/* prescale could be 0~0xFFF */ + { + i = (uint64_t) u32PWMClockSrc * u32Frequency2 / u32Frequency / u32Prescale; + /* If target value is larger than CNR, need to use a larger prescaler */ + if(i <= (0x10000U)) + { + u32CNR = i; + break; + } + } + /* Store return value here 'cos we're gonna change u32Prescale & u32CNR to the real value to fill into register */ + i = u32PWMClockSrc / (u32Prescale * u32CNR); + + /* convert to real register value */ + u32Prescale = u32Prescale - 1U; + /* every two channels share a prescaler */ + EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale); + /* set EPWM to up counter type(edge aligned) and auto-reload mode */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~((EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1)) | (EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum))); + + u32CNR = u32CNR - 1U; + EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR); + EPWM_SET_CMR(epwm, u32ChannelNum, u32HighDutyCycle * (u32CNR + 1UL) / 10000UL); + + (epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~((EPWM_WGCTL0_PRDPCTL0_Msk | EPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \ + (EPWM_OUTPUT_HIGH << (u32ChannelNum << 1UL << EPWM_WGCTL0_ZPCTL0_Pos)); + (epwm)->WGCTL1 = ((epwm)->WGCTL1 & ~((EPWM_WGCTL1_CMPDCTL0_Msk | EPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1))) | \ + (EPWM_OUTPUT_LOW << (u32ChannelNum << 1UL << EPWM_WGCTL1_CMPUCTL0_Pos)); + + return(i); +} + +/** + * @brief Start EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to start EPWM module. + */ +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN |= u32ChannelMask; +} + +/** + * @brief Stop EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM module. + */ +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0UL; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->PERIOD[i] = 0UL; + } + } +} + +/** + * @brief Stop EPWM generation immediately by clear channel enable bit + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM generation immediately by clear channel enable bit. + */ +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN &= ~u32ChannelMask; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref EPWM_TRG_ADC_EVEN_ZERO + * - \ref EPWM_TRG_ADC_EVEN_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_UP + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_ODD_ZERO + * - \ref EPWM_TRG_ADC_ODD_PERIOD + * - \ref EPWM_TRG_ADC_ODD_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_ODD_COMPARE_UP + * - \ref EPWM_TRG_ADC_ODD_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN + * @return None + * @details This function is used to enable selected channel to trigger ADC. + */ +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if(u32ChannelNum < 4UL) + { + (epwm)->EADCTS0 &= ~((EPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3)); + (epwm)->EADCTS0 |= ((EPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3)); + } + else + { + (epwm)->EADCTS1 &= ~((EPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3)); + (epwm)->EADCTS1 |= ((EPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger ADC. + */ +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + if(u32ChannelNum < 4UL) + { + (epwm)->EADCTS0 &= ~(EPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3)); + } + else + { + (epwm)->EADCTS1 &= ~(EPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3)); + } +} + +/** + * @brief Enable and configure trigger ADC prescale + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32Prescale ADC prescale. Valid values are between 0 to 0xF. + * @param[in] u32PrescaleCnt ADC prescale counter. Valid values are between 0 to 0xF. + * @retval 0 Success. + * @retval -1 Failed. + * @details This function is used to enable and configure trigger ADC prescale. + * @note User can configure only when ADC trigger prescale is disabled. + * @note ADC prescale counter must less than ADC prescale. + */ +int32_t EPWM_EnableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Prescale, uint32_t u32PrescaleCnt) +{ + /* User can write only when PSCENn(n = 0 ~ 5) is 0 */ + if ((epwm)->EADCPSCCTL & (1UL << u32ChannelNum)) + return (-1); + + if(u32ChannelNum < 4UL) + { + (epwm)->EADCPSC0 = ((epwm)->EADCPSC0 & ~((EPWM_EADCPSC0_EADCPSC0_Msk) << (u32ChannelNum << 3))) | \ + (u32Prescale << (u32ChannelNum << 3)); + (epwm)->EADCPSCNT0 = ((epwm)->EADCPSCNT0 & ~((EPWM_EADCPSCNT0_PSCNT0_Msk) << (u32ChannelNum << 3))) | \ + (u32PrescaleCnt << (u32ChannelNum << 3)); + } + else + { + (epwm)->EADCPSC1 = ((epwm)->EADCPSC1 & ~((EPWM_EADCPSC1_EADCPSC4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \ + (u32Prescale << ((u32ChannelNum - 4UL) << 3)); + (epwm)->EADCPSCNT1 = ((epwm)->EADCPSCNT1 & ~((EPWM_EADCPSCNT1_PSCNT4_Msk) << ((u32ChannelNum - 4UL) << 3))) | \ + (u32PrescaleCnt << ((u32ChannelNum - 4UL) << 3)); + } + + (epwm)->EADCPSCCTL |= EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum; + + return 0; +} + +/** + * @brief Disable Trigger ADC prescale function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable trigger ADC prescale. + */ +void EPWM_DisableADCTriggerPrescale(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->EADCPSCCTL &= ~(EPWM_EADCPSCCTL_PSCEN0_Msk << u32ChannelNum); +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag. + */ +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (void)u32Condition; + (epwm)->STATUS = (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get EPWM trigger ADC to start of conversion flag for specified channel. + */ +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Enable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions: + * - \ref EPWM_TRIGGER_DAC_ZERO + * - \ref EPWM_TRIGGER_DAC_PERIOD + * - \ref EPWM_TRIGGER_DAC_COMPARE_UP + * - \ref EPWM_TRIGGER_DAC_COMPARE_DOWN + * @return None + * @details This function is used to enable selected channel to trigger DAC. + */ +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->DACTRGEN |= (u32Condition << u32ChannelNum); +} + +/** + * @brief Disable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger DAC. + */ +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum); +} + +/** + * @brief Clear selected channel trigger DAC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. This parameter is not used + * @param[in] u32Condition The condition to trigger DAC. This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger DAC flag. + */ +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (void)u32ChannelNum; + (void)u32Condition; + (epwm)->STATUS = EPWM_STATUS_DACTRGF_Msk; +} + +/** + * @brief Get selected channel trigger DAC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. This parameter is not used + * @retval 0 The specified channel trigger DAC to start of conversion flag is not set + * @retval 1 The specified channel trigger DAC to start of conversion flag is set + * @details This function is used to get selected channel trigger DAC flag. + */ +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + return (((epwm)->STATUS & EPWM_STATUS_DACTRGF_Msk) ? 1UL : 0UL); +} + +/** + * @brief This function enable fault brake of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel + * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32BrakeSource Fault brake source, could be one of following source + * - \ref EPWM_FB_EDGE_ADCRM + * - \ref EPWM_FB_EDGE_ACMP0 + * - \ref EPWM_FB_EDGE_ACMP1 + * - \ref EPWM_FB_EDGE_BKP0 + * - \ref EPWM_FB_EDGE_BKP1 + * - \ref EPWM_FB_EDGE_SYS_CSS + * - \ref EPWM_FB_EDGE_SYS_BOD + * - \ref EPWM_FB_EDGE_SYS_RAM + * - \ref EPWM_FB_EDGE_SYS_COR + * - \ref EPWM_FB_LEVEL_ADCRM + * - \ref EPWM_FB_LEVEL_ACMP0 + * - \ref EPWM_FB_LEVEL_ACMP1 + * - \ref EPWM_FB_LEVEL_BKP0 + * - \ref EPWM_FB_LEVEL_BKP1 + * - \ref EPWM_FB_LEVEL_SYS_CSS + * - \ref EPWM_FB_LEVEL_SYS_BOD + * - \ref EPWM_FB_LEVEL_SYS_RAM + * - \ref EPWM_FB_LEVEL_SYS_COR + * @return None + * @details This function is used to enable fault brake of selected channel(s). + * The write-protection function should be disabled before using this function. + */ +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource) +{ + uint32_t i; + + for(i = 0UL; i < EPWM_CHANNEL_NUM; i++) + { + if(u32ChannelMask & (1UL << i)) + { + if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR)) + { + (epwm)->BRKCTL[i >> 1] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_Msk)); + (epwm)->FAILBRK |= (u32BrakeSource & 0xFUL); + } + else + { + (epwm)->BRKCTL[i >> 1] |= u32BrakeSource; + } + } + + if(u32LevelMask & (1UL << i)) + { + if((i & 0x1UL) == 0UL) + { + /* set brake action as high level for even channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3UL) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as high level for odd channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3UL) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + else + { + if((i & 0x1UL) == 0UL) + { + /* set brake action as low level for even channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1] |= ((2UL) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as low level for odd channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1] |= ((2UL) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + } +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s). + */ +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN |= u32ChannelMask; + (epwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s). + */ +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN &= ~u32ChannelMask; + (epwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enable EPWM output generation of selected channel(s). + */ +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disable EPWM output generation of selected channel(s). + */ +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE. + * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either + * - \ref EPWM_CAPTURE_PDMA_RISING_LATCH + * - \ref EPWM_CAPTURE_PDMA_FALLING_LATCH + * - \ref EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + * @note This function can only selects even or odd channel of pairs to do PDMA transfer. + */ +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode) +{ + uint32_t u32IsOddCh; + u32IsOddCh = u32ChannelNum & 0x1UL; + (epwm)->PDMACTL = ((epwm)->PDMACTL & ~((EPWM_PDMACTL_CHSEL0_1_Msk | EPWM_PDMACTL_CAPORD0_1_Msk | EPWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1) << 3))) | \ + (((u32IsOddCh << EPWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << EPWM_PDMACTL_CAPORD0_1_Pos) | \ + u32Mode | EPWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1) << 3)); +} + +/** + * @brief Disables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + */ +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->PDMACTL &= ~(EPWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1) << 3)); +} + +/** + * @brief Enable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Duration Dead zone length in EPWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone. + * @return None + * @details This function is used to enable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration) +{ + /* every two channels share the same setting */ + (epwm)->DTCTL[(u32ChannelNum) >> 1] &= ~EPWM_DTCTL0_1_DTCNT_Msk; + (epwm)->DTCTL[(u32ChannelNum) >> 1] |= EPWM_DTCTL0_1_DTEN_Msk | u32Duration; +} + +/** + * @brief Disable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + */ +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + /* every two channels shares the same setting */ + (epwm)->DTCTL[(u32ChannelNum) >> 1] &= ~EPWM_DTCTL0_1_DTEN_Msk; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + uint32_t u32CapIf = 0UL; + + u32CapIf = ((((epwm)->CAPIF & (EPWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1); + u32CapIf |= (((epwm)->CAPIF & (EPWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL); + return u32CapIf; +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref EPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (epwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel. + */ +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel. + */ +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = (EPWM_INTSTS0_CMPUIF0_Msk | EPWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((EPWM_INTSTS0_CMPDIF0_Msk | EPWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief This function enable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to enable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 |= (0x7UL << u32BrakeSource); +} + +/** + * @brief This function disable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to disable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource); +} + +/** + * @brief This function clear fault brake interrupt of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to clear fault brake interrupt of selected source. + * The write-protection function should be disabled before using this function. + */ +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource); +} + +/** + * @brief This function get fault brake interrupt flag of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source, could be either + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * @details This function is used to get fault brake interrupt flag of selected source. + */ +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + */ +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (void)u32IntPeriodType; + (epwm)->INTEN0 |= (EPWM_INTEN0_PIEN0_Msk << u32ChannelNum); +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable period interrupt of selected channel. + */ +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~(EPWM_INTEN0_PIEN0_Msk << u32ChannelNum); +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear period interrupt of selected channel. + */ +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = (EPWM_INTSTS0_PIF0_Msk << u32ChannelNum); +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel. + */ +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & (EPWM_INTSTS0_PIF0_Msk << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable zero interrupt of selected channel. + */ +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 |= (EPWM_INTEN0_ZIEN0_Msk << u32ChannelNum); +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable zero interrupt of selected channel. + */ +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~(EPWM_INTEN0_ZIEN0_Msk << u32ChannelNum); +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear zero interrupt of selected channel. + */ +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = (EPWM_INTSTS0_ZIF0_Msk << u32ChannelNum); +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Zero interrupt flag of specified channel + * @retval 0 Zero interrupt did not occur + * @retval 1 Zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + */ +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & (EPWM_INTSTS0_ZIF0_Msk << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~65535. + * @param[in] u32IntAccSrc Interrupt flag accumulator source selection. + * - \ref EPWM_IFA_ZERO_POINT + * - \ref EPWM_IFA_PERIOD_POINT + * - \ref EPWM_IFA_COMPARE_UP_COUNT_POINT + * - \ref EPWM_IFA_COMPARE_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable interrupt flag accumulator of selected channel. + */ +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc) +{ + (epwm)->IFA[u32ChannelNum] = (((epwm)->IFA[u32ChannelNum] & ~((EPWM_IFA0_IFACNT_Msk | EPWM_IFA0_IFASEL_Msk))) | \ + (EPWM_IFA0_IFAEN_Msk | (u32IntAccSrc << EPWM_IFA0_IFASEL_Pos) | u32IntFlagCnt)); +} + +/** + * @brief Disable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to Disable interrupt flag accumulator of selected channel. + */ +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] = ((epwm)->IFA[u32ChannelNum] & ~(EPWM_IFA0_IFAEN_Msk)); +} + +/** + * @brief Enable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Clear interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTSTS = (1UL << (u32ChannelNum)); +} + +/** + * @brief Get interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 Accumulator interrupt did not occur + * @retval 1 Accumulator interrupt occurred + * @details This function is used to Get interrupt flag accumulator interrupt of selected channel. + */ +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->AINTSTS & (1UL << (u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Enable interrupt flag accumulator stop mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable interrupt flag accumulator stop mode of selected channel. + */ +void EPWM_EnableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] |= EPWM_IFA0_STPMOD_Msk; +} + +/** + * @brief Disable interrupt flag accumulator stop mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable interrupt flag accumulator stop mode of selected channel. + */ +void EPWM_DisableAccStopMode(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] &= ~EPWM_IFA0_STPMOD_Msk; +} + +/** + * @brief Clear free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear free trigger duty interrupt flag of selected channel. + */ +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FTCI = ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1)); +} + +/** + * @brief Get free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Free trigger duty interrupt did not occur + * @retval 1 Free trigger duty interrupt occurred + * @details This function is used to get free trigger duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->FTCI & ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1))) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Configure synchronization phase of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32SyncSrc EPWM synchronize source selection. + * - \ref EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR + * - \ref EPWM_SYNC_OUT_DISABLE + * @param[in] u32Direction Phase direction. Control EPWM counter count decrement or increment after synchronizing. + * - \ref EPWM_PHS_DIR_DECREMENT + * - \ref EPWM_PHS_DIR_INCREMENT + * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535. + * @return None + * @details This function is used to configure synchronization phase of selected channel. + * @note Every two channels share the same setting. + */ +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase) +{ + /* every two channels shares the same setting */ + u32ChannelNum >>= 1; + (epwm)->SYNC = (((epwm)->SYNC & ~((EPWM_SYNC_SINSRC0_Msk << (u32ChannelNum << 1)) | (EPWM_SYNC_PHSDIR0_Msk << u32ChannelNum))) | \ + (u32Direction << EPWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | (u32SyncSrc << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1)); + (epwm)->PHS[(u32ChannelNum)] = u32StartPhase; +} + + +/** + * @brief Enable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0UL; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC |= (EPWM_SYNC_PHSEN0_Msk << (i >> 1)); + } + } +} + +/** + * @brief Disable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0UL; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC &= ~(EPWM_SYNC_PHSEN0_Msk << (i >> 1)); + } + } +} + +/** + * @brief Enable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector. + * The valid value is 0~7. + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM SYNC_IN noise filter function. + */ +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->SYNC = ((epwm)->SYNC & ~(EPWM_SYNC_SFLTCNT_Msk | EPWM_SYNC_SFLTCSEL_Msk)) | \ + ((u32ClkCnt << EPWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << EPWM_SYNC_SFLTCSEL_Pos) | EPWM_SYNC_SNFLTEN_Msk); +} + +/** + * @brief Disable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC_IN noise filter function. + */ +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm) +{ + (epwm)->SYNC &= ~EPWM_SYNC_SNFLTEN_Msk; +} + +/** + * @brief Enable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to enable EPWM SYNC input pin inverse function. + */ +void EPWM_EnableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC |= EPWM_SYNC_SINPINV_Msk; +} + +/** + * @brief Disable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC input pin inverse function. + */ +void EPWM_DisableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC &= (~EPWM_SYNC_SINPINV_Msk); +} + +/** + * @brief Set EPWM clock source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32ClkSrcSel EPWM external clock source. + * - \ref EPWM_CLKSRC_EPWM_CLK + * - \ref EPWM_CLKSRC_TIMER0 + * - \ref EPWM_CLKSRC_TIMER1 + * - \ref EPWM_CLKSRC_TIMER2 + * - \ref EPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set EPWM clock source. + * @note Every two channels share the same setting. + * @note If the clock source of EPWM counter is selected from TIMERn interrupt events, the TRGEPWM(TIMERn_TRGCTL[1], n=0,1..3) bit must be set as 1. + */ +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (epwm)->CLKSRC = ((epwm)->CLKSRC & ~(EPWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1) << 3))) | \ + (u32ClkSrcSel << ((u32ChannelNum >> 1) << 3)); +} + +/** + * @brief Enable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM brake noise filter function. + */ +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->BNF = ((epwm)->BNF & ~((EPWM_BNF_BRK0FCNT_Msk | EPWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum << 3))) | \ + (((u32ClkCnt << EPWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << EPWM_BNF_BRK0NFSEL_Pos) | EPWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum << 3)); +} + +/** + * @brief Disable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake noise filter function. + */ +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum << 3)); +} + +/** + * @brief Enable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to enable EPWM brake pin inverse function. + */ +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF |= (EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum << 3)); +} + +/** + * @brief Disable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake pin inverse function. + */ +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * (uint32_t)EPWM_BNF_BRK1NFEN_Pos)); +} + +/** + * @brief Set EPWM brake pin source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE. + * @return None + * @details This function is used to set EPWM brake pin source. + */ +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule) +{ + (epwm)->BNF = ((epwm)->BNF & ~(EPWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3))) | (u32SelAnotherModule << ((uint32_t)EPWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3))); +} + +/** + * @brief Set EPWM leading edge blanking function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32TrigSrcSel Leading edge blanking source selection. + * - \ref EPWM_LEBCTL_SRCEN0 + * - \ref EPWM_LEBCTL_SRCEN2 + * - \ref EPWM_LEBCTL_SRCEN4 + * - \ref EPWM_LEBCTL_SRCEN0_2 + * - \ref EPWM_LEBCTL_SRCEN0_4 + * - \ref EPWM_LEBCTL_SRCEN2_4 + * - \ref EPWM_LEBCTL_SRCEN0_2_4 + * @param[in] u32TrigType Leading edge blanking trigger type. + * - \ref EPWM_LEBCTL_TRGTYPE_RISING + * - \ref EPWM_LEBCTL_TRGTYPE_FALLING + * - \ref EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING + * @param[in] u32BlankingCnt Leading Edge Blanking Counter. Valid values are between 1~512. + This counter value decides leading edge blanking window size, and this counter clock base is ECLK. + * @param[in] u32BlankingEnable Enable EPWM leading edge blanking function. Valid values are TRUE (ENABLE) or FALSE (DISABLE). + * - \ref FALSE + * - \ref TRUE + * @return None + * @details This function is used to configure EPWM leading edge blanking function that blank the false trigger from ACMP brake source which may cause by EPWM output transition. + * @note EPWM leading edge blanking function is only used for brake source from ACMP. + */ +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable) +{ + (epwm)->LEBCTL = (u32TrigType) | (u32TrigSrcSel) | (u32BlankingEnable); + /* Blanking window size = LEBCNT + 1, so LEBCNT = u32BlankingCnt - 1 */ + (epwm)->LEBCNT = (u32BlankingCnt) - 1UL; +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + */ +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + */ +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->STATUS = (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum); +} + +/** + * @brief Enable fault detect of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32AfterPrescaler Fault Detect Clock Source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). + * @param[in] u32ClkSel Fault Detect Clock Select. + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_1 + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_2 + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_4 + * - \ref EPWM_FDCTL_FDCKSEL_CLK_DIV_8 + * @return None + * @details This function is used to enable fault detect of selected channel. + */ +void EPWM_EnableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32AfterPrescaler, uint32_t u32ClkSel) +{ + (epwm)->FDEN = ((epwm)->FDEN & ~(EPWM_FDEN_FDCKS0_Msk << (u32ChannelNum))) | \ + ((EPWM_FDEN_FDEN0_Msk | ((u32AfterPrescaler) << EPWM_FDEN_FDCKS0_Pos)) << (u32ChannelNum)); + (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & ~EPWM_FDCTL0_FDCKSEL_Msk) | (u32ClkSel); +} + +/** + * @brief Disable fault detect of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect of selected channel. + */ +void EPWM_DisableFaultDetect(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDEN &= ~(EPWM_FDEN_FDEN0_Msk << (u32ChannelNum)); +} + +/** + * @brief Enable fault detect output of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to enable fault detect output of selected channel. + */ +void EPWM_EnableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDEN &= ~(EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum)); +} + +/** + * @brief Disable fault detect output of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect output of selected channel. + */ +void EPWM_DisableFaultDetectOutput(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDEN |= (EPWM_FDEN_FDODIS0_Msk << (u32ChannelNum)); +} + +/** + * @brief Enable fault detect deglitch function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32DeglitchSmpCycle Deglitch Sampling Cycle. Valid values are between 0~7. + * @return None + * @details This function is used to enable fault detect deglitch function of selected channel. + */ +void EPWM_EnableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32DeglitchSmpCycle) +{ + (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_DGSMPCYC_Msk)) | \ + (EPWM_FDCTL0_FDDGEN_Msk | ((u32DeglitchSmpCycle) << EPWM_FDCTL0_DGSMPCYC_Pos)); +} + +/** + * @brief Disable fault detect deglitch function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect deglitch function of selected channel. + */ +void EPWM_DisableFaultDetectDeglitch(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDDGEN_Msk; +} + +/** + * @brief Enable fault detect mask function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @param[in] u32MaskCnt Transition mask counter. Valid values are between 0~0x7F. + * @return None + * @details This function is used to enable fault detect mask function of selected channel. + */ +void EPWM_EnableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32MaskCnt) +{ + (epwm)->FDCTL[(u32ChannelNum)] = ((epwm)->FDCTL[(u32ChannelNum)] & (~EPWM_FDCTL0_TRMSKCNT_Msk)) | (EPWM_FDCTL0_FDMSKEN_Msk | (u32MaskCnt)); +} + +/** + * @brief Disable fault detect mask function of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect mask function of selected channel. + */ +void EPWM_DisableFaultDetectMask(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDCTL[(u32ChannelNum)] &= ~EPWM_FDCTL0_FDMSKEN_Msk; +} + +/** + * @brief Enable fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to enable fault detect interrupt of selected channel. + */ +void EPWM_EnableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDIEN |= (EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum)); +} + +/** + * @brief Disable fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to disable fault detect interrupt of selected channel. + */ +void EPWM_DisableFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDIEN &= ~(EPWM_FDIEN_FDIEN0_Msk << (u32ChannelNum)); +} + +/** + * @brief Clear fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @return None + * @details This function is used to clear fault detect interrupt of selected channel. + */ +void EPWM_ClearFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FDSTS = (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum)); +} + +/** + * @brief Get fault detect interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module. + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5. + * @retval 0 Fault detect interrupt did not occur. + * @retval 1 Fault detect interrupt occurred. + * @details This function is used to Get fault detect interrupt of selected channel. + */ +uint32_t EPWM_GetFaultDetectInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->FDSTS & (EPWM_FDSTS_FDIF0_Msk << (u32ChannelNum))) ? 1UL : 0UL); +} + +/**@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EPWM_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_ewdt.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_ewdt.c new file mode 100644 index 0000000000..06aa8aca75 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_ewdt.c @@ -0,0 +1,71 @@ +/**************************************************************************//** + * @file ewdt.c + * @version V3.00 + * @brief Extra Watchdog Timer(EWDT) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EWDT_Driver EWDT Driver + @{ +*/ + +/** @addtogroup EWDT_EXPORTED_FUNCTIONS EWDT Exported Functions + @{ +*/ + +/** + * @brief Initialize EWDT and start counting + * + * @param[in] u32TimeoutInterval Time-out interval period of EWDT module. Valid values are: + * - \ref EWDT_TIMEOUT_2POW4 + * - \ref EWDT_TIMEOUT_2POW6 + * - \ref EWDT_TIMEOUT_2POW8 + * - \ref EWDT_TIMEOUT_2POW10 + * - \ref EWDT_TIMEOUT_2POW12 + * - \ref EWDT_TIMEOUT_2POW14 + * - \ref EWDT_TIMEOUT_2POW16 + * - \ref EWDT_TIMEOUT_2POW18 + * - \ref EWDT_TIMEOUT_2POW20 + * @param[in] u32ResetDelay Configure EWDT time-out reset delay period. Valid values are: + * - \ref EWDT_RESET_DELAY_1026CLK + * - \ref EWDT_RESET_DELAY_130CLK + * - \ref EWDT_RESET_DELAY_18CLK + * - \ref EWDT_RESET_DELAY_3CLK + * @param[in] u32EnableReset Enable EWDT time-out reset system function. Valid values are TRUE and FALSE. + * @param[in] u32EnableWakeup Enable EWDT time-out wake-up system function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes EWDT module start counting with different time-out interval, reset delay period and choose to \n + * enable or disable EWDT time-out reset system or wake-up system. + * @note Please make sure that Register Write-Protection Function has been disabled before using this function. + */ +void EWDT_Open(uint32_t u32TimeoutInterval, + uint32_t u32ResetDelay, + uint32_t u32EnableReset, + uint32_t u32EnableWakeup) +{ + EWDT->ALTCTL = u32ResetDelay; + + EWDT->CTL = u32TimeoutInterval | EWDT_CTL_WDTEN_Msk | + (u32EnableReset << EWDT_CTL_RSTEN_Pos) | + (u32EnableWakeup << EWDT_CTL_WKEN_Pos); + + while((EWDT->CTL & EWDT_CTL_SYNC_Msk) == EWDT_CTL_SYNC_Msk) {} /* Wait enable WDTEN bit completed, it needs 2 * EWDT_CLK. */ +} + +/**@}*/ /* end of group EWDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EWDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_ewwdt.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_ewwdt.c new file mode 100644 index 0000000000..ab3b76128b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_ewwdt.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file ewwdt.c + * @version V3.00 + * @brief Extra Window Watchdog Timer(EWWDT) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EWWDT_Driver EWWDT Driver + @{ +*/ + +/** @addtogroup EWWDT_EXPORTED_FUNCTIONS EWWDT Exported Functions + @{ +*/ + +/** + * @brief Open EWWDT and start counting + * + * @param[in] u32PreScale Pre-scale setting of EWWDT counter. Valid values are: + * - \ref EWWDT_PRESCALER_1 + * - \ref EWWDT_PRESCALER_2 + * - \ref EWWDT_PRESCALER_4 + * - \ref EWWDT_PRESCALER_8 + * - \ref EWWDT_PRESCALER_16 + * - \ref EWWDT_PRESCALER_32 + * - \ref EWWDT_PRESCALER_64 + * - \ref EWWDT_PRESCALER_128 + * - \ref EWWDT_PRESCALER_192 + * - \ref EWWDT_PRESCALER_256 + * - \ref EWWDT_PRESCALER_384 + * - \ref EWWDT_PRESCALER_512 + * - \ref EWWDT_PRESCALER_768 + * - \ref EWWDT_PRESCALER_1024 + * - \ref EWWDT_PRESCALER_1536 + * - \ref EWWDT_PRESCALER_2048 + * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F. + * @param[in] u32EnableInt Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes EWWDT module start counting with different counter period by pre-scale setting and compared window value. + * @note Application can call this function only once after boot up. + */ +void EWWDT_Open(uint32_t u32PreScale, + uint32_t u32CmpValue, + uint32_t u32EnableInt) +{ + EWWDT->CTL = u32PreScale | + (u32CmpValue << EWWDT_CTL_CMPDAT_Pos) | + ((u32EnableInt == (uint32_t)TRUE) ? EWWDT_CTL_INTEN_Msk : 0UL) | + EWWDT_CTL_WWDTEN_Msk; +} + +/**@}*/ /* end of group EWWDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group EWWDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_fmc.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_fmc.c new file mode 100644 index 0000000000..aee8701e49 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_fmc.c @@ -0,0 +1,914 @@ +/**************************************************************************//** + * @file fmc.c + * @version V3.00 + * $Revision: 1 $ + * $Date: 19/11/27 7:50p $ + * @brief M2355 Series Flash Memory Controller(FMC) driver source file + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +/** + * @brief Run flash all one verification and get result. + * + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes. + * + * @retval READ_ALLONE_YES The contents of verified flash area are 0xA11FFFFF. + * @retval READ_ALLONE_NOT Some contents of verified flash area are not 0xA1100000. + * @retval READ_ALLONE_CMD_FAIL Unexpected error occurred. + * + * @details Run ISP check all one command to check specify area is all one or not. + */ +uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret = READ_ALLONE_CMD_FAIL; + + FMC_ISP->ISPSTS = 0x80UL; /* clear check all one bit */ + + FMC_ISP->ISPCMD = FMC_ISPCMD_RUN_ALL1; + FMC_ISP->ISPADDR = u32addr; + FMC_ISP->ISPDAT = u32count; + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC_ISP->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + do + { + FMC_ISP->ISPCMD = FMC_ISPCMD_READ_ALL1; + FMC_ISP->ISPADDR = u32addr; + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC_ISP->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + } + while(FMC_ISP->ISPDAT == 0UL); + + if(FMC_ISP->ISPDAT == READ_ALLONE_YES) + { + ret = FMC_ISP->ISPDAT; + } + + if(FMC_ISP->ISPDAT == READ_ALLONE_NOT) + { + ret = FMC_ISP->ISPDAT; + } + + return ret; +} + + +/** + * @brief Disable ISP Functions + * + * @param None + * + * @return None + * + * @details This function will clear ISPEN bit of ISPCON to disable ISP function + * + */ +void FMC_Close(void) +{ + FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk; +} + +/** + * @brief Config XOM Region + * @param[in] u32XomNum The XOM number(0~3) + * @param[in] u32XomBase The XOM region base address. + * @param[in] u8XomPage The XOM page number of region size. + * + * @retval 0 Success + * @retval 1 XOM is has already actived. + * @retval -1 Program failed. + * @retval -2 Invalid XOM number. + * + * @details Program XOM base address and XOM size(page) + */ +int32_t FMC_ConfigXOM(uint32_t u32XomNum, uint32_t u32XomBase, uint8_t u8XomPage) +{ + int32_t ret = 0; + + if(u32XomNum >= 4UL) + { + ret = -2; + } + + if(ret == 0) + { + ret = FMC_GetXOMState(u32XomNum); + } + + if(ret == 0) + { + FMC_ISP->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC_ISP->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u); + FMC_ISP->ISPDAT = u32XomBase; + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if(FMC_ISP->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC_ISP->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + if(ret == 0) + { + FMC_ISP->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC_ISP->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x04u); + FMC_ISP->ISPDAT = u8XomPage; + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if(FMC_ISP->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC_ISP->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + if(ret == 0) + { + FMC_ISP->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC_ISP->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x08u); + FMC_ISP->ISPDAT = 0u; + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if(FMC_ISP->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC_ISP->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + return ret; +} + +/** + * @brief Execute Flash Page erase + * + * @param[in] u32PageAddr Address of the flash page to be erased. + * It must be a 2048 bytes aligned address. + * + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + * + * @details Execute FMC_ISPCMD_PAGE_ERASE command to erase a flash page. The page size is 2048 bytes. + */ +int32_t FMC_Erase(uint32_t u32PageAddr) +{ + int32_t ret = 0; + + if(ret == 0) + { + FMC_ISP->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC_ISP->ISPADDR = u32PageAddr; + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if(FMC_ISP->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC_ISP->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + } + return ret; +} + +/** + * @brief Execute Flash Bank erase + * + * @param[in] u32BankAddr Base address of the flash bank to be erased. + * + * @return ISP bank erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + * + * @details Execute FMC_ISPCMD_BANK_ERASE command to erase a flash block. + */ +int32_t FMC_EraseBank(uint32_t u32BankAddr) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_BANK_ERASE; + FMC->ISPADDR = u32BankAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + return ret; +} + + +/** + * @brief Execute Erase XOM Region + * + * @param[in] u32XomNum The XOMRn(n=0~3) + * + * @return XOM erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + * @retval -2 Invalid XOM number. + * + * @details Execute FMC_ISPCMD_PAGE_ERASE command to erase XOM. + */ +int32_t FMC_EraseXOM(uint32_t u32XomNum) +{ + uint32_t u32Addr; + int32_t i32Active, err = 0; + + if(u32XomNum >= 4UL) + { + err = -2; + } + + if(err == 0) + { + i32Active = FMC_GetXOMState(u32XomNum); + + if(i32Active) + { + u32Addr = ( ( (uint32_t)(&FMC->XOMR0STS)[u32XomNum] ) & 0xFFFFFF00u ) >> 8u; + + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = u32Addr; + FMC->ISPDAT = 0x55aa03u; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + while(FMC->ISPTRG) {} + + /* Check ISPFF flag to know whether erase OK or fail. */ + if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + err = -1; + } + } + else + { + err = -1; + } + } + return err; +} + +/** + * @brief Get the current boot source + * + * @param None + * + * @return The current boot source. + * @retval 0 This chip is currently booting from APROM + * @retval 1 This chip is currently booting from LDROM + * + * @note This function only show the boot source. + * User need to read ISPSTA register to know if IAP mode supported or not in relative boot. + */ +int32_t FMC_GetBootSource(void) +{ + int32_t ret = 0; + + if(FMC->ISPCTL & FMC_ISPCTL_BS_Msk) + { + ret = 1; + } + + return ret; +} + +/** + * @brief Run CRC32 checksum calculation and get result. + * + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 2048bytes. + * + * @return Success or not. + * @retval 0 Success. + * @retval 0xFFFFFFFF Invalid parameter. + * + * @details Run ISP CRC32 checksum command to calculate checksum then get and return checksum data. + */ +uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret; + + if((u32addr % 2048UL) || (u32count % 2048UL)) + { + ret = 0xFFFFFFFF; + } + else + { + FMC_ISP->ISPCMD = FMC_ISPCMD_RUN_CKS; + FMC_ISP->ISPADDR = u32addr; + FMC_ISP->ISPDAT = u32count; + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + FMC_ISP->ISPCMD = FMC_ISPCMD_READ_CKS; + FMC_ISP->ISPADDR = u32addr; + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC_ISP->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + ret = FMC_ISP->ISPDAT; + } + + return ret; +} + +/** + * @brief Check the OTP is locked or not. + * + * @param[in] u32OtpNum The OTP number. + * + * @retval 1 OTP is locked. + * @retval 0 OTP is not locked. + * @retval -1 Failed to read OTP lock bits. + * @retval -2 Invalid OTP number. + * + * @details To get specify OTP lock status + */ +int32_t FMC_IsOTPLocked(uint32_t u32OtpNum) +{ + int32_t ret = 0; + + if(u32OtpNum > 255UL) + { + ret = -2; + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_READ; + FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + u32OtpNum * 4UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + if(FMC->ISPDAT != 0xFFFFFFFFUL) + { + ret = 1; /* Lock work was progrmmed. OTP was locked. */ + } + } + } + return ret; +} + +/** + * @brief Check the XOM is actived or not. + * + * @param[in] u32XomNum The xom number(0~3). + * + * @retval 1 XOM is actived. + * @retval 0 XOM is not actived. + * @retval -2 Invalid XOM number. + * + * @details To get specify XOMRn(n=0~3) active status + */ +int32_t FMC_GetXOMState(uint32_t u32XomNum) +{ + uint32_t u32act; + int32_t ret = 0; + + if(u32XomNum >= 4UL) + { + ret = -2; + } + + if(ret >= 0) + { + u32act = (((FMC_ISP->XOMSTS) & 0xful) & (1ul << u32XomNum)) >> u32XomNum; + ret = (int32_t)u32act; + } + return ret; +} + +/** + * @brief Lock the specified OTP. + * + * @param[in] u32OtpNum The OTP number. + * + * @retval 0 Success + * @retval -1 Failed to write OTP lock bits. + * @retval -2 Invalid OTP number. + * + * @details To lock specified OTP number + */ +int32_t FMC_LockOTP(uint32_t u32OtpNum) +{ + int32_t ret = 0; + + if(u32OtpNum > 255UL) + { + ret = -2; + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + u32OtpNum * 4UL; + FMC->ISPDAT = 0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + return ret; +} + +/** + * @brief Enable FMC ISP function + * + * @param None + * + * @return None + * + * @details ISPEN bit of ISPCON must be set before we can use ISP commands. + * Therefore, To use all FMC function APIs, user needs to call FMC_Open() first to enable ISP functions. + * + * @note ISP functions are write-protected. user also needs to unlock it by calling SYS_UnlockReg() before using all ISP functions. + * + */ +void FMC_Open(void) +{ + FMC_ISP->ISPCTL |= FMC_ISPCTL_ISPEN_Msk; +} + + +/** + * @brief Read a word bytes from flash + * + * @param[in] u32Addr Address of the flash location to be read. + * It must be a word aligned address. + * + * @return The word data read from specified flash address. + * + * @details Execute FMC_ISPCMD_READ command to read a word from flash. + */ +uint32_t FMC_Read(uint32_t u32Addr) +{ + FMC_ISP->ISPCMD = FMC_ISPCMD_READ; + FMC_ISP->ISPADDR = u32Addr; + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + return FMC_ISP->ISPDAT; +} + +/** + * @brief Read a double-word bytes from flash + * + * @param[in] u32addr Address of the flash location to be read. + * It must be a double-word aligned address. + * + * @param[out] u32data0 Place holder of word 0 read from flash address u32addr. + * @param[out] u32data1 Place holder of word 0 read from flash address u32addr+4. + * + * @return 0 Success + * @return -1 Failed + * + * @details Execute FMC_ISPCMD_READ_64 command to read a double-word from flash. + */ +int32_t FMC_Read64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_READ_64; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = 0x0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + *u32data0 = FMC->MPDAT0; + *u32data1 = FMC->MPDAT1; + } + return ret; +} + +/** + * @brief Read data from OTP + * + * @param[in] u32OtpNum The OTP number(0~255). + * @param[in] u32LowWord Low word of the 64-bits data. + * @param[in] u32HighWord High word of the 64-bits data. + * + * @retval 0 Success + * @retval -1 Read failed. + * @retval -2 Invalid OTP number. + * + * @details Read the 64-bits data from the specified OTP. + */ +int32_t FMC_ReadOTP(uint32_t u32OtpNum, uint32_t *u32LowWord, uint32_t *u32HighWord) +{ + int32_t ret = 0; + + if(u32OtpNum > 255UL) + { + ret = -2; + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_READ_64; + FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL ; + FMC->ISPDAT = 0x0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) {} + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + *u32LowWord = FMC->MPDAT0; + *u32HighWord = FMC->MPDAT1; + } + } + return ret; +} + +/** + * @brief Read the User Configuration words. + * + * @param[out] u32Config[] The word buffer to store the User Configuration data. + * @param[in] u32Count The word count to be read. + * + * @return Success or not. + * @retval 0 Success + * @retval -1 Failed + * + * @details This function is used to read the settings of user configuration. + * if u32Count = 1, Only CONFIG0 will be returned to the buffer specified by u32Config. + * if u32Count = 2, Both CONFIG0 and CONFIG1 will be returned. + */ +int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count) +{ + uint32_t i; + + for(i = 0u; i < u32Count; i++) + { + u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4u); + } + return 0; +} + +/** + * @brief Set boot source from LDROM or APROM after next software reset + * + * @param[in] i32BootSrc + * 1: Boot from LDROM + * 0: Boot from APROM + * + * @return None + * + * @details This function is used to switch APROM boot or LDROM boot. User need to call + * FMC_SetBootSource to select boot source first, then use CPU reset or + * System Reset Request to reset system. + * + */ +void FMC_SetBootSource(int32_t i32BootSrc) +{ + if(i32BootSrc) + { + FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */ + } + else + { + FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */ + } +} + + +/** + * @brief Write a word bytes to flash. + * + * @param[in] u32Addr Address of the flash location to be programmed. + * It must be a word aligned address. + * @param[in] u32Data The word data to be programmed. + * + * @return None + * + * @ details Execute ISP FMC_ISPCMD_PROGRAM to program a word to flash. + */ +void FMC_Write(uint32_t u32Addr, uint32_t u32Data) +{ + FMC_ISP->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC_ISP->ISPADDR = u32Addr; + FMC_ISP->ISPDAT = u32Data; + FMC_ISP->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC_ISP->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } +} + +/** + * @brief Write a double-word bytes to flash + * + * @param[in] u32addr Address of the flash location to be programmed. + * It must be a double-word aligned address. + * @param[in] u32data0 The word data to be programmed to flash address u32addr. + * @param[in] u32data1 The word data to be programmed to flash address u32addr+4. + * + * @return 0 Success + * @return -1 Failed + * + * @ details Execute ISP FMC_ISPCMD_PROGRAM_64 to program a double-word to flash. + */ +int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_PROGRAM_64; + FMC->ISPADDR = u32addr; + FMC->MPDAT0 = u32data0; + FMC->MPDAT1 = u32data1; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/** + * @brief Write User Configuration + * + * @param[in] au32Config[] The word buffer to store the User Configuration data. + * @param[in] u32Count The word count to program to User Configuration. + * + * @retval 0 Success + * @retval -1 Failed + * + * @details User must enable User Configuration update before writing it. + * User must erase User Configuration before writing it. + * User Configuration is also be page erase. User needs to backup necessary data + * before erase User Configuration. + */ +int32_t FMC_WriteConfig(uint32_t au32Config[], uint32_t u32Count) +{ + int32_t ret = 0; + uint32_t i; + + FMC_ENABLE_CFG_UPDATE(); + for(i = 0u; i < u32Count; i++) + { + FMC_Write(FMC_CONFIG_BASE + i * 4u, au32Config[i]); + if(FMC_Read(FMC_CONFIG_BASE + i * 4u) != au32Config[i]) + { + ret = -1; + } + } + FMC_DISABLE_CFG_UPDATE(); + return ret; +} + +/** + * @brief Write Multi-Word bytes to flash + * + * @param[in] u32Addr Start flash address in APROM where the data chunk to be programmed into. + * This address must be 8-bytes aligned to flash address. + * @param[in] pu32Buf Buffer that carry the data chunk. + * @param[in] u32Len Length of the data chunk in bytes. + * + * @retval >=0 Number of data bytes were programmed. + * @return -1 Invalid address. + * + * @details Program Multi-Word data into specified address of flash. + */ + +int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len) +{ + + uint32_t i, idx, u32OnProg; + int32_t err, retval = 0; + + if((u32Addr >= FMC_APROM_END) || ((u32Addr % 8) != 0)) + { + return -1; + } + + idx = 0u; + FMC->ISPCMD = FMC_ISPCMD_PROGRAM_MUL; + FMC->ISPADDR = u32Addr; + retval += 16; + do + { + err = 0; + u32OnProg = 1u; + FMC->MPDAT0 = pu32Buf[idx + 0u]; + FMC->MPDAT1 = pu32Buf[idx + 1u]; + FMC->MPDAT2 = pu32Buf[idx + 2u]; + FMC->MPDAT3 = pu32Buf[idx + 3u]; + FMC->ISPTRG = 0x1u; + idx += 4u; + + for(i = idx; i < (u32Len / 4u); i += 4u) /* Max data length is 256 bytes (512/4 words)*/ + { + __set_PRIMASK(1u); /* Mask interrupt to avoid status check coherence error*/ + do + { + if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u) + { + __set_PRIMASK(0u); + + FMC->ISPADDR = FMC->MPADDR & (~0xful); + idx = (FMC->ISPADDR - u32Addr) / 4u; + err = -1; + } + } + while((FMC->MPSTS & (3u << FMC_MPSTS_D0_Pos)) && (err == 0)); + + if(err == 0) + { + retval += 8; + + /* Update new data for D0 */ + FMC->MPDAT0 = pu32Buf[i]; + FMC->MPDAT1 = pu32Buf[i + 1u]; + do + { + if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u) + { + __set_PRIMASK(0u); + FMC->ISPADDR = FMC->MPADDR & (~0xful); + idx = (FMC->ISPADDR - u32Addr) / 4u; + err = -1; + } + } + while((FMC->MPSTS & (3u << FMC_MPSTS_D2_Pos)) && (err == 0)); + + if(err == 0) + { + retval += 8; + + /* Update new data for D2*/ + FMC->MPDAT2 = pu32Buf[i + 2u]; + FMC->MPDAT3 = pu32Buf[i + 3u]; + __set_PRIMASK(0u); + } + } + + if(err < 0) + { + break; + } + } + if(err == 0) + { + u32OnProg = 0u; + while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) {} + } + } + while(u32OnProg); + + return retval; +} + +/** + * @brief Write data to OTP + * + * @param[in] u32OtpNum The OTP number(0~255). + * @param[in] u32LowWord Low word of the 64-bits data. + * @param[in] u32HighWord High word of the 64-bits data. + * + * @retval 0 Success + * @retval -1 Program failed. + * @retval -2 Invalid OTP number. + * + * @details Program a 64-bits data to the specified OTP. + */ +int32_t FMC_WriteOTP(uint32_t u32OtpNum, uint32_t u32LowWord, uint32_t u32HighWord) +{ + int32_t ret = 0; + + if(u32OtpNum > 255UL) + { + ret = -2; + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL; + FMC->ISPDAT = u32LowWord; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL + 4UL; + FMC->ISPDAT = u32HighWord; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + return ret; +} + +/** + * @brief Swap Bank0/Bank1 + * + * @param[in] u32Bank Bank Num which will swap to. + * + * @retval 0 Success + * @retval -1 Program failed. + * + * @details Swap Bank0/Bank1 + */ +int32_t FMC_SwapBank(uint32_t u32Bank) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_BANK_SWAP; + FMC->ISPADDR = u32Bank; + FMC->ISPDAT = 0x5AA55AA5UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/**@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group FMC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2019 Nuvoton Technology Corp. ***/ + + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_fvc.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_fvc.c new file mode 100644 index 0000000000..67e4a0ae38 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_fvc.c @@ -0,0 +1,167 @@ +/**************************************************************************//** + * @file fvc.c + * @version V3.00 + * @brief FVC driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FVC_Driver FVC Driver + @{ +*/ + + +/** @addtogroup FVC_EXPORTED_FUNCTIONS FVC Exported Functions + @{ +*/ + + + + +/** + * @brief Initial firmware version counter + * @param None + * @retval 0 Successful + * @retval -1 Failed + * @details FVC needs to be initialed before using it. This function is used to initial the FVC. + * + */ +int32_t FVC_Open(void) +{ + int32_t timeout; + + /* Just return when it is ready */ + if(FVC->STS & FVC_STS_RDY_Msk) + return 0; + + /* Init FVC */ + FVC->CTL = FVC_VCODE | FVC_CTL_INIT_Msk; + + /* Waiting for ready */ + timeout = 0x100000; + while((FVC->STS & FVC_STS_RDY_Msk) == 0) + { + if(timeout-- < 0) + { + /* Init timeout. */ + return -1; + } + } + + return 0; +} + + + +/** + * @brief Enable anti version rollback + * @details FVC can limit the version number to be increased only to avoid version rollback. + * This function is used to enable it. + * + */ +void FVC_EnableMonotone(void) +{ + FVC->CTL = FVC_VCODE | FVC_CTL_MONOEN_Msk; + /* Waiting if FVC is in busy */ + while(FVC->STS & FVC->STS & FVC_STS_BUSY_Msk) {} +} + +/** + * @brief Set BL2 version + * @param[in] ver Version Number. It could be 0~63. + * @retval 0 Successful + * @retval -1 Failed + * @details Set version number of BL2 + * + */ +int32_t FVC_SetBL2Ver(uint32_t u32Ver) +{ + if(u32Ver >= 64) + return -1; + + FVC->BL2 = (FVC->BL2 << 16) | (u32Ver & 0x3ful); + while(FVC->STS & FVC_STS_BUSY_Msk) {} + if(FVC->BL2 != u32Ver) + return -1; + + return 0; +} + +/** + * @brief Set BL32 version + * @param[in] ver Version Number. It could be 0~63. + * @retval 0 Successful + * @retval -1 Failed + * @details Set version number of BL32 + * + */ +int32_t FVC_SetBL32Ver(uint32_t u32Ver) +{ + if(u32Ver >= 64) + return -1; + + FVC->BL32 = (FVC->BL32 << 16) | (u32Ver & 0x3ful); + while(FVC->STS & FVC_STS_BUSY_Msk) {} + if(FVC->BL32 != u32Ver) + return -1; + + return 0; +} + + +/** + * @brief Set BL33 version + * @param[in] ver Version Number. It could be 0~255. + * @retval 0 Successful + * @retval -1 Failed + * @details Set version number of BL33 + * + */ +int32_t FVC_SetBL33Ver(uint32_t u32Ver) +{ + if(u32Ver >= 256) + return -1; + + FVC->BL33 = (FVC->BL33 << 16) | (u32Ver & 0xfful); + while(FVC->STS & FVC_STS_BUSY_Msk) {} + if(FVC->BL33 != u32Ver) + return -1; + + return 0; +} + + +/** + * @brief Set version for user firmware + * @param[in] ver Version Number. It could be 0~255. + * @retval 0 Successful + * @retval -1 Failed + * @details Set version number of user firmware + * + */ +int32_t FVC_SetUDFVer(uint32_t u32Ver) +{ + if(u32Ver >= 256) + return -1; + + FVC->UDF = (FVC->UDF << 16) | (u32Ver & 0xfful); + while(FVC->STS & FVC_STS_BUSY_Msk) {} + if(FVC->UDF != u32Ver) + return -1; + + return 0; +} + + +/**@}*/ /* end of group FVC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group FVC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_gpio.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_gpio.c new file mode 100644 index 0000000000..b4003c2cf9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_gpio.c @@ -0,0 +1,191 @@ +/**************************************************************************//** + * @file gpio.c + * @version V3.00 + * @brief M2354 series General Purpose I/O (GPIO) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Set GPIO operation mode + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * @param[in] u32Mode Operation mode. It could be + * - \ref GPIO_MODE_INPUT + * - \ref GPIO_MODE_OUTPUT + * - \ref GPIO_MODE_OPEN_DRAIN + * - \ref GPIO_MODE_QUASI + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t u32Idx; + + for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++) + { + if((u32PinMask & (1ul << u32Idx)) == (1ul << u32Idx)) + { + port->MODE = (port->MODE & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1)); + } + } +} + +/** + * @brief Enable GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB and PE. \n + * It could be 0 ~ 13 for PC GPIO port. \n + * It could be 0 ~ 12, 14 for PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n + * It could be 4 ~ 11 for PH GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be + * - \ref GPIO_INT_RISING + * - \ref GPIO_INT_FALLING + * - \ref GPIO_INT_BOTH_EDGE + * - \ref GPIO_INT_HIGH + * - \ref GPIO_INT_LOW + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs) +{ + /* Configure interrupt mode of specified pin */ + port->INTTYPE = (port->INTTYPE & ~(1ul << u32Pin)) | (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin); + + /* Enable interrupt function of specified pin */ + port->INTEN = (port->INTEN & ~(0x00010001ul << u32Pin)) | ((u32IntAttribs & 0xFFFFFFUL) << u32Pin); +} + + +/** + * @brief Disable GPIO interrupt + * + + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB and PE. \n + * It could be 0 ~ 13 for PC GPIO port. \n + * It could be 0 ~ 12, 14 for PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n + * It could be 4 ~ 11 for PH GPIO port. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin) +{ + /* Configure interrupt mode of specified pin */ + port->INTTYPE &= ~(1UL << u32Pin); + + /* Disable interrupt function of specified pin */ + port->INTEN &= ~((0x00010001UL) << u32Pin); +} + +/** + * @brief Set GPIO slew rate control + * + + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * @param[in] u32Mode Slew rate mode. It could be + * - \ref GPIO_SLEWCTL_NORMAL (maximum 40 MHz at 2.7V) + * - \ref GPIO_SLEWCTL_HIGH (maximum 80 MHz at 2.7V) + * - \ref GPIO_SLEWCTL_FAST (maximum 100 MHz at 2.7V) + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t u32Idx; + + for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++) + { + if(u32PinMask & (1ul << u32Idx)) + { + port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1)); + } + } +} + +/** + * @brief Set GPIO Pull-up and Pull-down control + * + + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT12, BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * @param[in] u32Mode The pin mode of specified GPIO pin. It could be + * - \ref GPIO_PUSEL_DISABLE + * - \ref GPIO_PUSEL_PULL_UP + * - \ref GPIO_PUSEL_PULL_DOWN + * + * @return None + * + * @details Set the pin mode of specified GPIO pin. + */ +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t u32Idx; + + for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++) + { + if(u32PinMask & (1ul << u32Idx)) + { + port->PUSEL = (port->PUSEL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1)); + } + } +} + +/**@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group GPIO_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_i2c.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_i2c.c new file mode 100644 index 0000000000..f73d4d10a4 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_i2c.c @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file i2c.c + * @version V3.00 + * $Revision: 2 $ + * $Date: 16/08/02 6:02p $ + * @brief M2355 series I2C Serial Interface Controller(I2C) driver source file + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ + +/** + * @brief Enable specify I2C Controller and set Clock Divider + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C bus clock in Hz + * + * @return Actual I2C bus clock frequency + * + * @details The function enable the specify I2C Controller and set proper Clock Divider + * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock. + * I2C Bus clock = PCLK / (4*(divider+1). + * + */ +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if((i2c == I2C1) || (i2c == I2C1_NS)) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10u) / (u32BusClock * 4u) + 5u) / 10u - 1u); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + /* Enable I2C */ + i2c->CTL0 |= I2C_CTL0_I2CEN_Msk; + + return (u32Pclk / ((u32Div + 1u) << 2u)); +} + +/** + * @brief Disable specify I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Reset I2C Controller and disable specify I2C port. + * + */ + +void I2C_Close(I2C_T *i2c) +{ + /* Disable I2C */ + i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk; +} + +/** + * @brief Clear Time-out Counter flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag . + * + */ +void I2C_ClearTimeoutFlag(I2C_T *i2c) +{ + i2c->TOCTL |= I2C_TOCTL_TOIF_Msk; +} + +/** + * @brief Set Control bit of I2C Controller + * + * @param[in] i2c Specify I2C port + * @param[in] u8Start Set I2C START condition + * @param[in] u8Stop Set I2C STOP condition + * @param[in] u8Si Clear SI flag + * @param[in] u8Ack Set I2C ACK bit + * + * @return None + * + * @details The function set I2C Control bit of I2C Bus protocol. + * + */ +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack) +{ + uint32_t u32Reg = 0u; + + if(u8Start) + { + u32Reg |= I2C_CTL_STA; + } + if(u8Stop) + { + u32Reg |= I2C_CTL_STO; + } + if(u8Si) + { + u32Reg |= I2C_CTL_SI; + } + if(u8Ack) + { + u32Reg |= I2C_CTL_AA; + } + + i2c->CTL0 = (i2c->CTL0 & ~0x3Cu) | u32Reg; +} + +/** + * @brief Disable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for disable I2C interrupt + * + */ +void I2C_DisableInt(I2C_T *i2c) +{ + i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Enable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for enable I2C interrupt + * + */ +void I2C_EnableInt(I2C_T *i2c) +{ + i2c->CTL0 |= I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Get I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * + * @return The actual I2C Bus clock in Hz + * + * @details To get the actual I2C Bus Clock frequency. + */ +uint32_t I2C_GetBusClockFreq(I2C_T *i2c) +{ + uint32_t u32Divider = i2c->CLKDIV; + uint32_t u32Pclk; + + if((i2c == I2C1) || (i2c == I2C1_NS)) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + return (u32Pclk / ((u32Divider + 1u) << 2u)); +} + +/** + * @brief Set I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C Bus Clock in Hz + * + * @return The actual I2C Bus Clock in Hz + * + * @details To set the actual I2C Bus Clock frequency. + */ +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if((i2c == I2C1) || (i2c == I2C1_NS)) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10u) / (u32BusClock * 4u) + 5u) / 10u - 1u); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + return (u32Pclk / ((u32Div + 1u) << 2u)); +} + +/** + * @brief Get Interrupt Flag + * + * @param[in] i2c Specify I2C port + * + * @return I2C interrupt flag status + * + * @details To get I2C Bus interrupt flag. + */ +uint32_t I2C_GetIntFlag(I2C_T *i2c) +{ + return ((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk ? 1ul : 0ul); +} + +/** + * @brief Get I2C Bus Status Code + * + * @param[in] i2c Specify I2C port + * + * @return I2C Status Code + * + * @details To get I2C Bus Status Code. + */ +uint32_t I2C_GetStatus(I2C_T *i2c) +{ + return (i2c->STATUS0); +} + +/** + * @brief Read a Byte from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return I2C Data + * + * @details To read a bytes data from specify I2C port. + */ +uint8_t I2C_GetData(I2C_T *i2c) +{ + return (uint8_t)(i2c->DAT); +} + +/** + * @brief Send a byte to I2C Bus + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data The data to send to I2C bus + * + * @return None + * + * @details This function is used to write a byte to specified I2C port + */ +void I2C_SetData(I2C_T *i2c, uint8_t u8Data) +{ + i2c->DAT = u8Data; +} + +/** + * @brief Set 7-bit Slave Address and GC Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address register (0~3) + * @param[in] u8SlaveAddr 7-bit slave address + * @param[in] u8GCMode Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE) + * + * @return None + * + * @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3) + * and enable GC Mode. + * + */ +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode) +{ + switch(u8SlaveNo) + { + case 1: + i2c->ADDR1 = ((uint32_t)u8SlaveAddr << 1) | u8GCMode; + break; + case 2: + i2c->ADDR2 = ((uint32_t)u8SlaveAddr << 1) | u8GCMode; + break; + case 3: + i2c->ADDR3 = ((uint32_t)u8SlaveAddr << 1) | u8GCMode; + break; + case 0: + default: + i2c->ADDR0 = ((uint32_t)u8SlaveAddr << 1) | u8GCMode; + break; + } +} + +/** + * @brief Configure the mask bits of 7-bit Slave Address + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3) + * @param[in] u8SlaveAddrMask A byte for slave address mask + * + * @return None + * + * @details This function is used to set 7-bit slave addresses. + * + */ +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask) +{ + switch(u8SlaveNo) + { + case 1: + i2c->ADDRMSK1 = (uint32_t)u8SlaveAddrMask << 1; + break; + case 2: + i2c->ADDRMSK2 = (uint32_t)u8SlaveAddrMask << 1; + break; + case 3: + i2c->ADDRMSK3 = (uint32_t)u8SlaveAddrMask << 1; + break; + case 0: + default: + i2c->ADDRMSK0 = (uint32_t)u8SlaveAddrMask << 1; + break; + } +} + +/** + * @brief Enable Time-out Counter Function and support Long Time-out + * + * @param[in] i2c Specify I2C port + * @param[in] u8LongTimeout Configure DIV4 to enable Long Time-out (0/1) + * + * @return None + * + * @details This function enable Time-out Counter function and configure DIV4 to support Long + * Time-out. + * + */ +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout) +{ + if(u8LongTimeout) + { + i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk; + } + else + { + i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk; + } + + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Disable Time-out Counter Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Time-out Counter function in I2CTOC register. + * + */ +void I2C_DisableTimeout(I2C_T *i2c) +{ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Enable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To enable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_EnableWakeup(I2C_T *i2c) +{ + i2c->WKCTL |= I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_DisableWakeup(I2C_T *i2c) +{ + i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * + */ +uint32_t I2C_SMBusGetStatus(I2C_T *i2c) +{ + return (i2c->BUSSTS); +} + +/** + * @brief Clear SMBus Interrupt Flag + * + * @param[in] i2c Specify I2C port + * @param[in] u8SMBusIntFlag Specify SMBus interrupt flag + * + * @return None + * + * @details To clear flags of I2C_BUSSTS status register if interrupt set. + * + */ +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag) +{ + i2c->BUSSTS = u8SMBusIntFlag; +} + +/** + * @brief Set SMBus Bytes Counts of Transmission or Reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * + */ +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize) +{ + i2c->PKTSIZE = u32PktSize; +} + +/** + * @brief Init SMBus Host/Device Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8HostDevice Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0)) + * + * @return None + * + * @details Using SMBus communication must specify the port is a Host or a Device. + * + */ +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice) +{ + /* Clear BMHEN, BMDEN of BUSCTL Register */ + i2c->BUSCTL &= ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk); + + /* Set SMBus Host/Device Mode, and enable Bus Management*/ + if(u8HostDevice == (uint8_t)I2C_SMBH_ENABLE) + { + i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } + else + { + i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } +} + +/** + * @brief Disable SMBus function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode. + * + */ +void I2C_SMBusClose(I2C_T *i2c) +{ + + i2c->BUSCTL = 0x00U; +} + +/** + * @brief Enable SMBus PEC Transmit Function + * + * @param[in] i2c Specify I2C port + * @param[in] u8PECTxEn CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE) + * + * @return None + * + * @details When enable CRC check function, the Host or Device needs to transmit CRC byte. + * + */ +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn) +{ + i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk; + + if(u8PECTxEn) + { + i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk); + } + else + { + i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk; + } +} + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return A byte is packet error check value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * + */ +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c) +{ + return (uint8_t)i2c->PKTCRC; +} + +/** + * @brief Calculate Time-out of SMBus idle period + * + * @param[in] i2c Specify I2C port + * @param[in] u32Us Time-out length(us) + * @param[in] u32Hclk I2C peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Idle state. + * + */ + +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t u32Us, uint32_t u32Hclk) +{ + uint32_t u32Div, u32HclkKHz; + + i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk; + u32HclkKHz = u32Hclk / 1000U; + u32Div = (((u32Us * u32HclkKHz) / 1000U) >> 2U) - 1U; + if(u32Div > 255U) + { + i2c->BUSTOUT = 0xFFU; + } + else + { + i2c->BUSTOUT = u32Div; + } + +} + +/** + * @brief Calculate Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in active state. + * Time-out length is calculate the SCL line "one clock" pull low timing. + * + */ + +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + if(u32Div <= 0xFFU) + { + i2c->BUSTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } +} + +/** + * @brief Calculate Cumulative Clock low Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Active state. + * Time-out length is calculate the SCL line "clocks" low cumulative timing. + * + */ + +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + if(u32Div <= 0xFFU) + { + i2c->CLKTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } +} + +/** + * @brief Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8Data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master write a byte data to Slave. + * + */ + +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + + I2C_START(i2c); + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint32_t)(u8SlaveAddr << 1u | (uint8_t)0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8Data); /* Write data to I2CDAT */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *au8Data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master write multi bytes data to Slave. + * + */ + +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + case 0x28u: + if(u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, au8Data[u32txLen++]); /* Write Data to I2CDAT */ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] u8Data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify a address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t u8Data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u)); /* Send Slave address with write bit */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u32txLen < 1u) + { + I2C_SET_DATA(i2c, u8Data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *au8Data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data bytes write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, au8Data[u32txLen++]); + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] u8Data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify two bytes address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t u8Data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if((u32txLen < 1u) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, u8Data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] au8Data[] A data array for write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if((u32txLen < u32wLen) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, au8Data[u32txLen++]); /* Write data to Register I2CDAT*/ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master to read a byte data from Slave. + * + */ +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | (uint8_t)0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] au8Rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master to read multi data bytes from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | (uint8_t)0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify a byte address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Rdata = 0u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | (uint8_t)0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + u8Rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + u8Rdata = 0u; /* If occurs error, return 0 */ + } + return u8Rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] au8Rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify a byte address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | (uint8_t)0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + au8Rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + au8Rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify an address(2 bytes) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify two bytes address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Rdata = 0u, u8Addr = 1u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | (uint8_t)0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + u8Rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + u8Rdata = 0u; /* If occurs error, return 0 */ + } + return u8Rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] au8Rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify two bytes address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | (uint8_t)0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | (uint8_t)0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + +/**@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group I2C_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_i2s.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_i2s.c new file mode 100644 index 0000000000..8f4d45a8dc --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_i2s.c @@ -0,0 +1,265 @@ +/**************************************************************************//** + * @file i2s.c + * @version V3.00 + * @brief M2354 series I2S driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ + +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s); + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s The base address of I2S module. + * @return I2S source clock frequency (Hz). + * @details Return the source clock frequency according to the setting of I2S0SEL (CLK_CLKSEL3[17:16]). + */ +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s) +{ + (void)i2s; + uint32_t u32Freq, u32ClkSrcSel; + + u32ClkSrcSel = CLK_GetModuleClockSource(I2S0_MODULE) << CLK_CLKSEL3_I2S0SEL_Pos; + + switch(u32ClkSrcSel) + { + case CLK_CLKSEL3_I2S0SEL_HXT: + u32Freq = __HXT; + break; + + case CLK_CLKSEL3_I2S0SEL_PLL: + u32Freq = CLK_GetPLLClockFreq(); + break; + + case CLK_CLKSEL3_I2S0SEL_HIRC: + u32Freq = __HIRC; + break; + + case CLK_CLKSEL3_I2S0SEL_PCLK0: + u32Freq = CLK_GetPCLK0Freq(); + break; + + default: + u32Freq = CLK_GetPCLK0Freq(); + break; + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * @param[in] i2s The base address of I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are: + * - \ref I2S_MODE_MASTER + * - \ref I2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are: + * - \ref I2S_DATABIT_8 + * - \ref I2S_DATABIT_16 + * - \ref I2S_DATABIT_24 + * - \ref I2S_DATABIT_32 + * @param[in] u32MonoData Set audio data to mono or not. Valid values are: + * - \ref I2S_ENABLE_MONO + * - \ref I2S_DISABLE_MONO + * @param[in] u32DataFormat Data format. This is also used to select I2S or PCM(TDM) function. Valid values are: + * - \ref I2S_FORMAT_I2S + * - \ref I2S_FORMAT_I2S_MSB + * - \ref I2S_FORMAT_I2S_LSB + * - \ref I2S_FORMAT_PCM + * - \ref I2S_FORMAT_PCM_MSB + * - \ref I2S_FORMAT_PCM_LSB + * @return Real sample rate. + * @details Set TX and RX FIFO threshold to middle value. + * The sample rate may not be used from the parameter, it depends on system's clock settings, + * but real sample rate used by system will be returned for reference. + * @note I2S will be reset in initialization only for Secure. + */ +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat) +{ + uint16_t u16Divider; + uint32_t u32BitRate, u32SrcClk; + + if(!(__PC() & NS_OFFSET)) + { + /* Reset I2S */ + SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk; + } + + /* Configure I2S controller according to input parameters. */ + i2s->CTL0 = u32MasterSlave | u32WordWidth | u32MonoData | u32DataFormat; + i2s->CTL1 = I2S_FIFO_TX_LEVEL_WORD_8 | I2S_FIFO_RX_LEVEL_WORD_8; + + /* Get I2S source clock frequency */ + u32SrcClk = I2S_GetSourceClockFreq(i2s); + + /* Calculate bit clock rate */ + u32BitRate = u32SampleRate * (((u32WordWidth >> 4UL) & 0x3UL) + 1UL) * 16UL; + u16Divider = (uint16_t)((((((u32SrcClk * 10UL) / u32BitRate) >> 1UL) + 5UL) / 10UL) - 1UL); /* Round to the nearest integer */ + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | ((uint32_t)u16Divider << 8UL); + + /* Calculate real sample rate */ + u32BitRate = u32SrcClk / (((uint32_t)u16Divider + 1UL) * 2UL); + u32SampleRate = u32BitRate / ((((u32WordWidth >> 4UL) & 0x3UL) + 1UL) * 16UL); + + /* Enable I2S controller */ + i2s->CTL0 |= I2S_CTL0_I2SEN_Msk; + + return u32SampleRate; +} + +/** + * @brief Disable I2S function. + * @param[in] i2s The base address of I2S module. + * @return None + * @details Clear I2SEN (I2S_CTL0[0]) to disable I2S function. + */ +void I2S_Close(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_I2SEN_Msk; +} + +/** + * @brief Enable interrupt function. + * @param[in] i2s The base address of I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return None + * @details This function enables the interrupt according to the mask parameter. + */ +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN |= u32Mask; +} + +/** + * @brief Disable interrupt function. + * @param[in] i2s The base address of I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return None + * @details This function disables the interrupt according to the mask parameter. + */ +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN &= ~u32Mask; +} + +/** + * @brief Enable master clock (MCLK). + * @param[in] i2s The base address of I2S module. + * @param[in] u32BusClock The target MCLK clock. + * @return Actual MCLK clock + * @details Set the master clock rate according to u32BusClock parameter and enable master clock output. + * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference. + */ +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock) +{ + uint8_t u8Divider; + uint32_t u32SrcClk, u32Reg, u32Clock; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + if(u32BusClock == u32SrcClk) + { + u8Divider = (uint8_t)0UL; + } + else + { + u8Divider = (uint8_t)(u32SrcClk / u32BusClock) >> 1UL; + } + + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider; + + i2s->CTL0 |= I2S_CTL0_MCLKEN_Msk; + + u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk; + + if(u32Reg == 0UL) + { + u32Clock = u32SrcClk; + } + else + { + u32Clock = ((u32SrcClk >> 1UL) / u32Reg); + } + + return u32Clock; +} + +/** + * @brief Disable master clock (MCLK). + * @param[in] i2s The base address of I2S module. + * @return None + * @details Disable master clock output. + */ +void I2S_DisableMCLK(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 15. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 15. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->CTL1 = (i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) | + (u32TxThreshold << I2S_CTL1_TXTH_Pos) | + (u32RxThreshold << I2S_CTL1_RXTH_Pos); +} + +/** + * @brief Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChannelWidth Channel width. Valid values are: + * - \ref I2S_TDM_WIDTH_8BIT + * - \ref I2S_TDM_WIDTH_16BIT + * - \ref I2S_TDM_WIDTH_24BIT + * - \ref I2S_TDM_WIDTH_32BIT + * @param[in] u32ChannelNum Channel number. Valid values are: + * - \ref I2S_TDM_2CH + * - \ref I2S_TDM_4CH + * - \ref I2S_TDM_6CH + * - \ref I2S_TDM_8CH + * @param[in] u32SyncWidth Width for sync pulse. Valid values are: + * - \ref I2S_TDM_SYNC_ONE_BCLK + * - \ref I2S_TDM_SYNC_ONE_CHANNEL + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth) +{ + i2s->CTL0 = (i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) | + (u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) | + (u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) | + (u32SyncWidth << I2S_CTL0_PCMSYNC_Pos); +} + +/**@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group I2S_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_keystore.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_keystore.c new file mode 100644 index 0000000000..f4f9e8af32 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_keystore.c @@ -0,0 +1,561 @@ +/**************************************************************************//** + * @file keystore.c + * @version V3.00 + * @brief Key store driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2019 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup KS_Driver Key Store Driver + @{ +*/ + + +/** @addtogroup KS_EXPORTED_FUNCTIONS Key Store Exported Functions + @{ +*/ + +/** + * @brief Initial key store + * @return None + * @details This function is used to initial the key store. + * It is necessary to be called before using other APIs of Key Store. + */ +void KS_Open(void) +{ + if((KS->STS & KS_STS_INITDONE_Msk) == 0) + { + /* Waiting for busy */ + while(KS->STS & KS_STS_BUSY_Msk) {} + + /* Start Key Store Initial */ + KS->CTL = KS_CTL_INIT_Msk | KS_CTL_START_Msk; + + /* Waiting for initilization */ + while((KS->STS & KS_STS_INITDONE_Msk) == 0); + + } + + /* Waiting busy to make sure KS is ready. */ + while(KS->STS & KS_STS_BUSY_Msk); + +} + + +/** + * @brief Read key from key store + * @param[in] eType The memory type. It could be: + \ref KS_SRAM + \ref KS_FLASH + \ref KS_OTP + * @param[in] i32KeyIdx The key index to read + * @param[out] au32Key The buffer to store the key + * @param[in] u32WordCnt The word (32-bit) count of the key buffer size + * @retval 0 Successful + * @retval -1 Fail + * @details This function is used to read the key. + */ + +int32_t KS_Read(KS_MEM_Type eType, int32_t i32KeyIdx, uint32_t au32Key[], uint32_t u32WordCnt) +{ + int32_t i32Cnt; + uint32_t u32Cont; + int32_t offset, i, cnt; + + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Specify the key address */ + KS->METADATA = ((uint32_t)eType << KS_METADATA_DST_Pos) | KS_TOMETAKEY(i32KeyIdx); + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + offset = 0; + u32Cont = 0; + i32Cnt = (int32_t)u32WordCnt; + do + { + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Trigger to read the key */ + KS->CTL = u32Cont | KS_OP_READ | KS_CTL_START_Msk | (KS->CTL & (KS_CTL_SILENT_Msk|KS_CTL_SCMB_Msk)); + /* Waiting for key store processing */ + while(KS->STS & KS_STS_BUSY_Msk); + + /* Read the key to key buffer */ + cnt = i32Cnt; + if(cnt > 8) + cnt = 8; + for(i=0; iKEY[i]; + //printf("R[%d]:0x%08x\n", i, au32Key[offset+i]); + } + + u32Cont = KS_CTL_CONT_Msk; + i32Cnt -= 8; + offset += 8; + } while(i32Cnt > 0); + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + return -1; + + + return 0; +} + +/** + * @brief Get the word count of the specified Metadata key length + * @param[in] u32Meta The metadata define of the key length. It could be + \ref KS_META_128 + \ref KS_META_163 + \ref KS_META_192 + \ref KS_META_224 + \ref KS_META_233 + \ref KS_META_255 + \ref KS_META_256 + \ref KS_META_283 + \ref KS_META_384 + \ref KS_META_409 + \ref KS_META_512 + \ref KS_META_521 + \ref KS_META_571 + \ref KS_META_1024 + \ref KS_META_2048 + \ref KS_META_4096 + * @return The word (32-bit) count of the key + * @details This function is used to get word counts of the specified metadata key length. + * It could be used to know how may words needs to allocate for the key. + */ + +uint32_t KS_GetKeyWordCnt(uint32_t u32Meta) +{ + const uint16_t au8CntTbl[21] = { 4,6,6,7,8,8,8,9,12,13,16,17,18,0,0,0,32,48,64,96,128 }; + return au8CntTbl[((u32Meta & KS_METADATA_SIZE_Msk) >> KS_METADATA_SIZE_Pos)]; +} + +/** + * @brief Write key to key store +* @param[in] eType The memory type. It could be: + \ref KS_SRAM + \ref KS_FLASH + * @param[in] u32Meta The metadata of the key. It could be the combine of + \ref KS_META_AES + \ref KS_META_HMAC + \ref KS_META_RSA_EXP + \ref KS_META_RSA_MID + \ref KS_META_ECC + \ref KS_META_CPU + \ref KS_META_128 + \ref KS_META_163 + \ref KS_META_192 + \ref KS_META_224 + \ref KS_META_233 + \ref KS_META_255 + \ref KS_META_256 + \ref KS_META_283 + \ref KS_META_384 + \ref KS_META_409 + \ref KS_META_512 + \ref KS_META_521 + \ref KS_META_571 + \ref KS_META_1024 + \ref KS_META_2048 + \ref KS_META_4096 + \ref KS_META_BOOT + \ref KS_META_READABLE + \ref KS_META_PRIV + \ref KS_META_NONPRIV + \ref KS_META_SECURE + \ref KS_META_NONSECUR + + * @param[out] au32Key The buffer to store the key + * @param[in] u32WordCnt The word (32-bit) count of the key buffer size + * @return Index of the key. Failed when index < 0. + * @details This function is used to write a key to key store. + */ + +int32_t KS_Write(KS_MEM_Type eType, uint32_t u32Meta, uint32_t au32Key[]) +{ + int32_t i32Cnt; + uint32_t u32Cont; + int32_t offset, i, cnt; + + + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Specify the key address */ + KS->METADATA = (eType << KS_METADATA_DST_Pos) | u32Meta; + + /* Get size index */ + i32Cnt = (int32_t)KS_GetKeyWordCnt(u32Meta); + + /* Invalid key length */ + if(i32Cnt == 0) + return -1; + + /* OTP only support maximum 256 bits */ + if((eType == KS_OTP) && (i32Cnt > 8)) + return -1; + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + offset = 0; + u32Cont = 0; + do + { + /* Prepare the key to write */ + cnt = i32Cnt; + if(cnt > 8) + cnt = 8; + for(i=0; iKEY[i] = au32Key[offset+i]; + } + + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Write the key */ + KS->CTL = u32Cont | KS_OP_WRITE | KS_CTL_START_Msk | (KS->CTL & (KS_CTL_SILENT_Msk|KS_CTL_SCMB_Msk)); + + u32Cont = KS_CTL_CONT_Msk; + i32Cnt -= 8; + offset += 8; + + /* Waiting for key store processing */ + while(KS->STS & KS_STS_BUSY_Msk); + + } while(i32Cnt > 0); + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + { + //printf("KS_Write. EIF!\n"); + return -1; + } + + return KS_TOKEYIDX(KS->METADATA); +} + +/** + * @brief Erase a key from key store + * @param[in] i32KeyIdx The key index to read + * @retval 0 Successful + * @retval -1 Fail + * @details This function is used to erase a key from SRAM of key store. + */ +int32_t KS_EraseKey(int32_t i32KeyIdx) +{ + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + + /* Specify the key address */ + KS->METADATA = (KS_SRAM << KS_METADATA_DST_Pos) | KS_TOMETAKEY(i32KeyIdx); + + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Erase the key */ + KS->CTL = KS_OP_ERASE | KS_CTL_START_Msk | (KS->CTL & (KS_CTL_SILENT_Msk|KS_CTL_SCMB_Msk)); + + /* Waiting for processing */ + while(KS->STS & KS_STS_BUSY_Msk); + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + return -1; + + return 0; + +} + + +/** + * @brief Erase all keys from key store + * @param[in] eType The memory type. It could be: + \ref KS_SRAM + \ref KS_FLASH + \ref KS_OTP + * @param[in] i32KeyIdx The key index to read + * @retval 0 Successful + * @retval -1 Fail + * @details This function is used to erase all keys in SRAM or Flash of key store. + */ +int32_t KS_EraseAll(KS_MEM_Type eType) +{ + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + + /* Specify the key address */ + KS->METADATA = (eType << KS_METADATA_DST_Pos); + + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Erase the key */ + KS->CTL = KS_OP_ERASE_ALL | KS_CTL_START_Msk | (KS->CTL & (KS_CTL_SILENT_Msk|KS_CTL_SCMB_Msk)); + + /* Waiting for processing */ + while(KS->STS & KS_STS_BUSY_Msk); + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + return -1; + + return 0; + +} + + + +/** + * @brief Revoke a key in key store + * @param[in] eType The memory type. It could be: + \ref KS_SRAM + \ref KS_FLASH + \ref KS_OTP + * @param[in] i32KeyIdx The key index to read + * @retval 0 Successful + * @retval -1 Fail + * @details This function is used to revoke a key in key store. + */ +int32_t KS_RevokeKey(KS_MEM_Type eType, int32_t i32KeyIdx) +{ + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + + /* Specify the key address */ + KS->METADATA = (eType << KS_METADATA_DST_Pos) | KS_TOMETAKEY(i32KeyIdx); + + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Erase the key */ + KS->CTL = KS_OP_REVOKE | KS_CTL_START_Msk | (KS->CTL & (KS_CTL_SILENT_Msk|KS_CTL_SCMB_Msk)); + + /* Waiting for processing */ + while(KS->STS & KS_STS_BUSY_Msk); + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + return -1; + + return 0; + +} + + +/** + * @brief Get remain size of specified Key Store memory + * @param[in] eType The memory type. It could be: + \ref KS_SRAM + \ref KS_FLASH + * @retval remain size of specified Key Store memory + * @details This function is used to get remain size of Key Store. + */ +uint32_t KS_GetRemainSize(KS_MEM_Type mem) +{ + uint32_t u32Reg; + uint32_t u32SramRemain, u32FlashRemain; + + u32Reg = KS->REMAIN; + //printf("KS Remain 0x%08x\n", u32Reg); + //printf("SRAM remain %lu bytes, Flash remain %lu bytes\n",(u32Reg&KS_REMAIN_RRMNG_Msk) >> KS_REMAIN_RRMNG_Pos, (u32Reg&KS_REMAIN_FRMNG_Msk) >> KS_REMAIN_FRMNG_Pos); + u32SramRemain = (u32Reg&KS_REMAIN_RRMNG_Msk) >> KS_REMAIN_RRMNG_Pos; + u32FlashRemain = (u32Reg&KS_REMAIN_FRMNG_Msk) >> KS_REMAIN_FRMNG_Pos; + + if(mem == KS_SRAM) + return u32SramRemain; + else + return u32FlashRemain; +} + + + +/** + * @brief Get remain key count of specified Key Store memory + * @param[in] eType The memory type. It could be: + \ref KS_SRAM + \ref KS_FLASH + * @retval Remain key count in the specified key store memory + * @details This function is used to get remain key count in specified key store memory. + */ +uint32_t KS_GetRemainKeyCount(KS_MEM_Type mem) +{ + uint32_t u32Reg; + uint32_t u32SramRemain, u32FlashRemain; + + u32Reg = KS->REMKCNT; + u32SramRemain = (u32Reg & KS_REMKCNT_RRMKCNT_Msk) >> KS_REMKCNT_RRMKCNT_Pos; + u32FlashRemain = (u32Reg & KS_REMKCNT_FRMKCNT_Msk) >> KS_REMKCNT_FRMKCNT_Pos; + + if(mem == KS_SRAM) + return u32SramRemain; + else + return u32FlashRemain; +} + + + +/** + * @brief Write OTP key to key store + * @param[in] i32KeyIdx The OTP key index to store the key. It could be 0~7. + OTP key index 0 is default for ROTPK. + * @param[in] u32Meta The metadata of the key. It could be the combine of + \ref KS_META_AES + \ref KS_META_HMAC + \ref KS_META_RSA_EXP + \ref KS_META_RSA_MID + \ref KS_META_ECC + \ref KS_META_CPU + \ref KS_META_128 + \ref KS_META_163 + \ref KS_META_192 + \ref KS_META_224 + \ref KS_META_233 + \ref KS_META_255 + \ref KS_META_256 + \ref KS_META_BOOT + \ref KS_META_READABLE + \ref KS_META_PRIV + \ref KS_META_NONPRIV + \ref KS_META_SECURE + \ref KS_META_NONSECUR + + * @param[out] au32Key The buffer to store the key + * @param[in] u32WordCnt The word (32-bit) count of the key buffer size + * @retval 0 Successful + * @retval -1 Fail + * @details This function is used to write a key to OTP key store. + */ +int32_t KS_WriteOTP(int32_t i32KeyIdx, uint32_t u32Meta, uint32_t au32Key[]) +{ + const uint16_t au8CntTbl[7] = {4,6,6,7,8,8,8}; + int32_t i32Cnt; + uint32_t u32Cont; + int32_t offset, i, cnt, sidx; + + + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + /* Specify the key address */ + KS->METADATA = ((uint32_t)KS_OTP << KS_METADATA_DST_Pos) | u32Meta | KS_TOMETAKEY(i32KeyIdx); + + /* Get size index */ + sidx = (u32Meta >> KS_METADATA_SIZE_Pos) & 0xful; + + /* OTP only support maximum 256 bits */ + if(sidx >= 7) + return -1; + + i32Cnt = au8CntTbl[sidx]; + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk; + offset = 0; + u32Cont = 0; + do + { + /* Prepare the key to write */ + cnt = i32Cnt; + if(cnt > 8) + cnt = 8; + for(i=0; iKEY[i] = au32Key[offset+i]; + } + + /* Clear Status */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + + /* Write the key */ + KS->CTL = u32Cont | KS_OP_WRITE | KS_CTL_START_Msk | (KS->CTL & (KS_CTL_SILENT_Msk|KS_CTL_SCMB_Msk)); + + u32Cont = KS_CTL_CONT_Msk; + i32Cnt -= 8; + offset += 8; + + /* Waiting for key store processing */ + while(KS->STS & KS_STS_BUSY_Msk); + + } while(i32Cnt > 0); + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + { + //printf("KS_WriteOTP. EIF!\n"); + return -1; + } + + return i32KeyIdx; +} + + +/** + * @brief Trigger to inverse the date in KS_SRAM. + * @retval 1 The data in KS SRAM is inverted. + * @retval 0 The data in KS SRAM is non-inverted. + * @retval -1 Fail to invert the date in KS SRAM. + * @details This function is used to trigger anti-remanence procedure by inverse the data in SRAM. + * This won't change the reading key. + */ + +int32_t KS_ToggleSRAM(void) +{ + /* Just return when key store is in busy */ + if(KS->STS & KS_STS_BUSY_Msk) + return -1; + + + /* Specify the key address */ + KS->METADATA = ((uint32_t)KS_SRAM << KS_METADATA_DST_Pos); + + /* Clear error flag */ + KS->STS = KS_STS_EIF_Msk | KS_STS_IF_Msk; + /* Trigger to do anti-remanence procedure */ + KS->CTL = KS_OP_REMAN | KS_CTL_START_Msk; + + /* Waiting for key store processing */ + while(KS->STS & KS_STS_BUSY_Msk); + + /* Check error flag */ + if(KS->STS & KS_STS_EIF_Msk) + return -1; + + return ((KS->STS & KS_STS_RAMINV_Msk) > 0); +} + + +/**@}*/ /* end of group KS_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group KS_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_lcd.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_lcd.c new file mode 100644 index 0000000000..4ff0006452 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_lcd.c @@ -0,0 +1,339 @@ +/**************************************************************************//** + * @file lcd.c + * @version V3.00 + * @brief Liquid-Crystal Display(LCD) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup LCD_Driver LCD Driver + @{ +*/ + + +/// @cond HIDDEN_SYMBOLS + +/** @addtogroup LCD_EXPORTED_VARIABLES LCD Exported Variables + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Global file scope (static) variables */ +/*---------------------------------------------------------------------------------------------------------*/ +static uint32_t g_LCDFrameRate; + +/**@}*/ /* end of group LCD_EXPORTED_VARIABLES */ + +/// @endcond /* HIDDEN_SYMBOLS */ + + +/** @addtogroup LCD_EXPORTED_FUNCTIONS LCD Exported Functions + @{ +*/ + +/** + * @brief LCD Initialization routine + * + * @param[in] pLCDCfg Specify the LCD property. It includes: + * u32SrcFreq: Clock source frequency of LCD controller. + * u32ComDuty: LCD COM duty ratio selection. Valid values are: + * - \ref LCD_COM_DUTY_1_1 + * - \ref LCD_COM_DUTY_1_2 + * - \ref LCD_COM_DUTY_1_3 + * - \ref LCD_COM_DUTY_1_4 + * - \ref LCD_COM_DUTY_1_5 + * - \ref LCD_COM_DUTY_1_6 + * - \ref LCD_COM_DUTY_1_7 + * - \ref LCD_COM_DUTY_1_8 + * u32BiasLevel: LCD Bias level selection. Valid values are: + * - \ref LCD_BIAS_LV_1_2 + * - \ref LCD_BIAS_LV_1_3 + * - \ref LCD_BIAS_LV_1_4 + * u32Framerate: Specify the target LCD operating frame rate (Hz). + * u32WaveformType: Specify the LCD waveform type. Valid values are: + * - \ref LCD_WAVEFORM_TYPE_A_NORMAL + * - \ref LCD_WAVEFORM_TYPE_B_NORMAL + * - \ref LCD_WAVEFORM_TYPE_A_INVERSE + * - \ref LCD_WAVEFORM_TYPE_B_INVERSE + * u32IntSrc: Interrupt source selection. Valid values are: + * - \ref LCD_DISABLE_ALL_INT + * - \ref LCD_FRAME_COUNTING_END_INT + * - \ref LCD_FRAME_END_INT + * - \ref LCD_CPTOUT_INT + * - \ref LCD_ENABLE_ALL_INT + * u32DrivingMode: LCD operation driving mode selection. Valid values are: + * - \ref LCD_LOW_DRIVING_AND_BUF_OFF + * - \ref LCD_HIGH_DRIVING_AND_BUF_OFF + * - \ref LCD_HIGH_DRIVING_AND_BUF_OFF_AND_PWR_SAVING + * - \ref LCD_HIGH_DRIVING_AND_BUF_OFF_AND_PWR_SAVING + * - \ref LCD_LOW_DRIVING_AND_BUF_ON_AND_PWR_SAVING + * u32VSrc: Voltage source selection. Valid values are: + * - \ref LCD_VOLTAGE_SOURCE_VLCD + * - \ref LCD_VOLTAGE_SOURCE_AVDD + * - \ref LCD_VOLTAGE_SOURCE_CP + * + * @return The real LCD operating frame rate. Or 0 means LCD_Open failed. + * + * @details This function will configure the LCD properties for driving the LCD display well. + * After that, user can perform \ref LCD_ENABLE_DISPLAY() to enable LCD controller for LCD display. + */ +uint32_t LCD_Open(S_LCD_CFG_T *pLCDCfg) +{ + uint32_t u32ComNum, u32FreqLCD, u32FreqDiv; + + /* Display LCD display first */ + LCD_DISABLE_DISPLAY(); + + /* Turn all segments off */ + LCD_SetAllPixels(0); + + /* Set com and bias */ + LCD->PCTL = (pLCDCfg->u32ComDuty | pLCDCfg->u32BiasLevel); + + /* Set waveform type */ + LCD_WAVEFORM_TYPE(pLCDCfg->u32WaveformType); + + /* Configure interrupt source */ + LCD->INTEN = pLCDCfg->u32IntSrc; + + /* Set driving mode */ + LCD_DRIVING_MODE(pLCDCfg->u32DrivingMode); + + /* Select voltage source */ + LCD_VOLTAGE_SOURCE(pLCDCfg->u32VSrc); + + /* + An example for specify frame rate. + If LCD source clock is 32768Hz, COM duty 4. + In type-A: + One frame rate 32Hz, frame end event rate 32Hz. + 32 = (1/4) * F_LCD * (1/2) + F_LCD = 32 * 4 * 2 = 256 = (32768 / F_Div) + F_Div = (32768 / F_LCD) = 128 + In type-B: + Each even/odd frame rate 32Hz, frame end event rate 16Hz. + 32 = (1/4) * F_LCD + F_LCD = 32 * 4 = (32768 / F_Div) + F_Div = (32768 / F_LCD) = 256 + */ + u32ComNum = ((pLCDCfg->u32ComDuty & LCD_PCTL_DUTY_Msk) >> LCD_PCTL_DUTY_Pos) + 1; + if((pLCDCfg->u32WaveformType & LCD_PCTL_TYPE_Msk) == LCD_PCTL_TYPE_Msk) + { + /* In type-B */ + + /* Calculate LCD operation frequency */ + u32FreqLCD = (pLCDCfg->u32Framerate * u32ComNum); + + /* Calculate possible freq. divider */ + u32FreqDiv = (pLCDCfg->u32SrcFreq / u32FreqLCD); + + if(u32FreqDiv > 1024) + { + /* Invalid frame rate */ + g_LCDFrameRate = 0ul; + } + else + { + /* Set freq. divider */ + LCD_SET_FREQDIV(u32FreqDiv); + + /* Calculate target frame rate */ + g_LCDFrameRate = pLCDCfg->u32SrcFreq / (u32ComNum * u32FreqDiv); + } + } + else + { + /* In type-A */ + + /* Calculate LCD operation frequency */ + u32FreqLCD = (pLCDCfg->u32Framerate * u32ComNum) * 2; + + /* Calculate possible freq. divider */ + u32FreqDiv = (pLCDCfg->u32SrcFreq / u32FreqLCD); + + if(u32FreqDiv > 1024) + { + /* Invalid frame rate */ + g_LCDFrameRate = 0ul; + } + else + { + /* Set freq. divider */ + LCD_SET_FREQDIV(u32FreqDiv); + + /* Calculate target frame rate */ + g_LCDFrameRate = (pLCDCfg->u32SrcFreq / (u32ComNum * u32FreqDiv)) / 2; + } + } + + return g_LCDFrameRate; +} + +/** + * @brief Disable LCD Display + * + * @param[in] None + * + * @return None + * + * @details This function is used to disable LCD display. + */ +void LCD_Close(void) +{ + LCD_DISABLE_DISPLAY(); +} + +/** + * @brief Enables a Segment Display + * + * @param[in] u32Com Specify COM number. Valid values are from 0~7. + * @param[in] u32Seg Specify Segment number. Valid values are from 0~43. + * @param[in] u32OnFlag 0 : Segment not display + * 1 : Segment display + * + * @return None + * + * @details This function is used to enable specified segment display on the LCD. + */ +void LCD_SetPixel(uint32_t u32Com, uint32_t u32Seg, uint32_t u32OnFlag) +{ + uint32_t seg_num = (u32Seg / 4); + uint32_t seg_shift = (8 * (u32Seg - (4 * seg_num))); + + if (seg_num < 11) + { + if(u32OnFlag) + { + LCD->DATA[seg_num] |= ((uint32_t)(1<DATA[seg_num] &= (~((uint32_t)(1<DATA[i] = u32Value; +} + +/** + * @brief Enable LCD Blinking + * + * @param[in] u32ms Blinking period time(unit: ms) + * + * @return Real blinking period time(ms) + * + * @details This function is used to enable blink display with specified period. + */ +uint32_t LCD_EnableBlink(uint32_t u32ms) +{ + uint32_t u32OneCountPeriod, u32TargetCounts; + + if((LCD->PCTL & LCD_PCTL_TYPE_Msk) == LCD_PCTL_TYPE_Msk) + { + /* In type-B */ + u32OneCountPeriod = (1000 * 2) / g_LCDFrameRate; // ms + } + else + { + /* In type-A */ + u32OneCountPeriod = 1000 / g_LCDFrameRate; // ms + } + + u32TargetCounts = (u32ms / u32OneCountPeriod); + if(u32TargetCounts == 0) + u32TargetCounts = 1; + if(u32TargetCounts > 1024) + u32TargetCounts = 1024; + + LCD_SET_FRAME_COUNTING_VALUE(u32TargetCounts); + + /* Enable blink display */ + LCD_BLINKING_ON(); + + return (u32OneCountPeriod * u32TargetCounts); +} + +/** + * @brief Disable LCD Blinking + * + * @param[in] None + * + * @return None + * + * @details This function is used to disable LCD blink display. + */ +void LCD_DisableBlink(void) +{ + /* Disable blink display */ + LCD_BLINKING_OFF(); +} + +/** + * @brief Enable LCD Interrupt + * + * @param[in] IntSrc Interrupt Source. It could be a combination of + * \ref LCD_FRAME_COUNTING_END_INT, \ref LCD_FRAME_END_INT and \ref LCD_CPTOUT_INT. + * + * @return None + * + * @details This function is used to enable the specific LCD interrupt. + */ +void LCD_EnableInt(uint32_t u32IntSrc) +{ + LCD->INTEN |= (u32IntSrc); +} + +/** + * @brief Disable LCD Interrupt + * + * @param[in] IntSrc Interrupt Source. It could be a combination of + * \ref LCD_FRAME_COUNTING_END_INT, \ref LCD_FRAME_END_INT and \ref LCD_CPTOUT_INT. + * + * @return None + * + * @details This function is used to disable the specific LCD interrupt. + */ +void LCD_DisableInt(uint32_t u32IntSrc) +{ + LCD->INTEN &= ~(u32IntSrc); +} + + +/**@}*/ /* end of group LCD_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group LCD_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_pdma.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_pdma.c new file mode 100644 index 0000000000..089428fa22 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_pdma.c @@ -0,0 +1,468 @@ +/**************************************************************************//** + * @file pdma.c + * @version V3.00 + * @brief M2354 series PDMA driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +static uint8_t au8ChSelect[PDMA_CH_MAX]; + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + + +/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions + @{ +*/ + +/** + * @brief PDMA Open + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable the PDMA channels. + */ +void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask) +{ + uint32_t i; + + for(i = 0UL; i < (int)PDMA_CH_MAX; i++) + { + if((1 << i) & u32Mask) + { + (pdma)->DSCT[i].CTL = 0UL; + au8ChSelect[i] = (uint8_t)PDMA_MEM; + } + } + + (pdma)->CHCTL |= u32Mask; +} + +/** + * @brief PDMA Close + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details This function disable all PDMA channels. + */ +void PDMA_Close(PDMA_T *pdma) +{ + (pdma)->CHCTL = 0UL; +} + +/** + * @brief Set PDMA Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Width Data width. Valid values are + * - \ref PDMA_WIDTH_8 + * - \ref PDMA_WIDTH_16 + * - \ref PDMA_WIDTH_32 + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected channel data width and transfer count. + */ +void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount) +{ + (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk); + (pdma)->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos)); +} + +/** + * @brief Set PDMA Stride Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32DestLen Destination stride count + * @param[in] u32SrcLen Source stride count + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected stride mode. + */ +void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount) +{ + (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk; + (pdma)->STRIDE[u32Ch].ASOCR = (u32DestLen << 16) | u32SrcLen; + (pdma)->STRIDE[u32Ch].STCR = u32TransCount; +} + +/** + * @brief Set PDMA Repeat + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32DestInterval Destination address interval count + * @param[in] u32SrcInterval Source address interval count + * @param[in] u32RepeatCount Repeat count + * + * @return None + * + * @details This function set the selected repeat. + */ +void PDMA_SetRepeat(PDMA_T * pdma,uint32_t u32Ch, uint32_t u32DestInterval, uint32_t u32SrcInterval, uint32_t u32RepeatCount) +{ + pdma->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk; + pdma->REPEAT[u32Ch].AICTL =((u32DestInterval)<<16) | (u32SrcInterval); + pdma->REPEAT[u32Ch].RCNT = u32RepeatCount; +} + +/** + * @brief Set PDMA Transfer Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32SrcAddr Source address + * @param[in] u32SrcCtrl Source control attribute. Valid values are + * - \ref PDMA_SAR_INC + * - \ref PDMA_SAR_FIX + * @param[in] u32DstAddr destination address + * @param[in] u32DstCtrl destination control attribute. Valid values are + * - \ref PDMA_DAR_INC + * - \ref PDMA_DAR_FIX + * + * @return None + * + * @details This function set the selected channel source/destination address and attribute. + */ +void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl) +{ + (pdma)->DSCT[u32Ch].SA = u32SrcAddr; + (pdma)->DSCT[u32Ch].DA = u32DstAddr; + (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk); + (pdma)->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl); +} + +/** + * @brief Set PDMA Transfer Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Peripheral The selected peripheral. Valid values are + * - \ref PDMA_MEM + * - \ref PDMA_USB_TX + * - \ref PDMA_USB_RX + * - \ref PDMA_UART0_TX + * - \ref PDMA_UART0_RX + * - \ref PDMA_UART1_TX + * - \ref PDMA_UART1_RX + * - \ref PDMA_UART2_TX + * - \ref PDMA_UART2_RX + * - \ref PDMA_UART3_TX + * - \ref PDMA_UART3_RX + * - \ref PDMA_UART4_TX + * - \ref PDMA_UART4_RX + * - \ref PDMA_UART5_TX + * - \ref PDMA_UART5_RX + * - \ref PDMA_USCI0_TX + * - \ref PDMA_USCI0_RX + * - \ref PDMA_USCI1_TX + * - \ref PDMA_USCI1_RX + * - \ref PDMA_QSPI0_TX + * - \ref PDMA_QSPI0_RX + * - \ref PDMA_SPI0_TX + * - \ref PDMA_SPI0_RX + * - \ref PDMA_SPI1_TX + * - \ref PDMA_SPI1_RX + * - \ref PDMA_SPI2_TX + * - \ref PDMA_SPI2_RX + * - \ref PDMA_SPI3_TX + * - \ref PDMA_SPI3_RX + * - \ref PDMA_EPWM0_P1_RX + * - \ref PDMA_EPWM0_P2_RX + * - \ref PDMA_EPWM0_P3_RX + * - \ref PDMA_EPWM1_P1_RX + * - \ref PDMA_EPWM1_P2_RX + * - \ref PDMA_EPWM1_P3_RX + * - \ref PDMA_I2C0_TX + * - \ref PDMA_I2C0_RX + * - \ref PDMA_I2C1_TX + * - \ref PDMA_I2C1_RX + * - \ref PDMA_I2C2_TX + * - \ref PDMA_I2C2_RX + * - \ref PDMA_I2S0_TX + * - \ref PDMA_I2S0_RX + * - \ref PDMA_TMR0 + * - \ref PDMA_TMR1 + * - \ref PDMA_TMR2 + * - \ref PDMA_TMR3 + * - \ref PDMA_ADC_RX + * - \ref PDMA_DAC0_TX + * - \ref PDMA_DAC1_TX + * - \ref PDMA_EPWM0_CH0_TX + * - \ref PDMA_EPWM0_CH1_TX + * - \ref PDMA_EPWM0_CH2_TX + * - \ref PDMA_EPWM0_CH3_TX + * - \ref PDMA_EPWM0_CH4_TX + * - \ref PDMA_EPWM0_CH5_TX + * - \ref PDMA_EPWM1_CH0_TX + * - \ref PDMA_EPWM1_CH1_TX + * - \ref PDMA_EPWM1_CH2_TX + * - \ref PDMA_EPWM1_CH3_TX + * - \ref PDMA_EPWM1_CH4_TX + * - \ref PDMA_EPWM1_CH5_TX + * @param[in] u32ScatterEn Scatter-gather mode enable + * @param[in] u32DescAddr Scatter-gather descriptor address + * + * @return None + * + * @details This function set the selected channel transfer mode. Include peripheral setting. + */ +void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr) +{ + au8ChSelect[u32Ch] = (uint8_t)u32Peripheral; + switch(u32Ch) + { + case 0UL: + (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral; + break; + case 1UL: + (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos); + break; + case 2UL: + (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos); + break; + case 3UL: + (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos); + break; + case 4UL: + (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral; + break; + case 5UL: + (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos); + break; + case 6UL: + (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos); + break; + case 7UL: + (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos); + break; + default: + break; + } + + if(u32ScatterEn) + { + (pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; + (pdma)->DSCT[u32Ch].NEXT = u32DescAddr - ((pdma)->SCATBA); + } + else + { + (pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC; + } +} + +/** + * @brief Set PDMA Burst Type and Size + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32BurstType Burst mode or single mode. Valid values are + * - \ref PDMA_REQ_SINGLE + * - \ref PDMA_REQ_BURST + * @param[in] u32BurstSize Set the size of burst mode. Valid values are + * - \ref PDMA_BURST_128 + * - \ref PDMA_BURST_64 + * - \ref PDMA_BURST_32 + * - \ref PDMA_BURST_16 + * - \ref PDMA_BURST_8 + * - \ref PDMA_BURST_4 + * - \ref PDMA_BURST_2 + * - \ref PDMA_BURST_1 + * + * @return None + * + * @details This function set the selected channel burst type and size. + */ +void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize) +{ + (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk); + (pdma)->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize); +} + +/** + * @brief Enable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable timeout function of the selected channel(s). + * @note This function is only supported in channel 0 and channel 1. + */ +void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask) +{ + (pdma)->TOUTEN |= u32Mask; +} + +/** + * @brief Disable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function disable timeout function of the selected channel(s). + * @note This function is only supported in channel 0 and channel 1. + */ +void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask) +{ + (pdma)->TOUTEN &= ~u32Mask; +} + +/** + * @brief Set PDMA Timeout Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32OnOff Enable/disable timeout function + * @param[in] u32TimeOutCnt Timeout count + * + * @return None + * + * @details This function set the timeout count. + * @note This function is only supported in channel 0 and channel 1. + */ +void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt) +{ + switch(u32Ch) + { + case 0UL: + (pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt; + break; + case 1UL: + (pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos); + break; + + default: + break; + } + if(u32OnOff) + { + (pdma)->TOUTEN |= (1UL << u32Ch); + } + else + { + (pdma)->TOUTEN &= ~(1UL << u32Ch); + } +} + +/** + * @brief Trigger PDMA + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This function trigger the selected channel. + */ +void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch) +{ + if(au8ChSelect[u32Ch] == PDMA_MEM) + { + (pdma)->SWREQ = (1UL << u32Ch); + } +} + +/** + * @brief Enable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TABLE + * - \ref PDMA_INT_TIMEOUT + * - \ref PDMA_INT_ALIGN + * + * @return None + * + * @details This function enable the selected channel interrupt. + * @note PDMA_INT_TIMEOUT is only supported in channel 0 and channel 1. + */ +void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask) +{ + switch(u32Mask) + { + case PDMA_INT_TRANS_DONE: + case PDMA_INT_ALIGN: + (pdma)->INTEN |= (1UL << u32Ch); + break; + case PDMA_INT_TABLE: + (pdma)->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + (pdma)->TOUTIEN |= (1UL << u32Ch); + break; + + default: + break; + } +} + +/** + * @brief Disable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TABLE + * - \ref PDMA_INT_TIMEOUT + * - \ref PDMA_INT_ALIGN + * + * @return None + * + * @details This function disable the selected channel interrupt. + * @note PDMA_INT_TIMEOUT is only supported in channel 0 and channel 1. + * @note The transfer done interrupt is disabled when table empty interrupt is disabled(PDMA_INT_TEMPTY). + */ +void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask) +{ + switch(u32Mask) + { + case PDMA_INT_TRANS_DONE: + case PDMA_INT_ALIGN: + (pdma)->INTEN &= ~(1UL << u32Ch); + break; + case PDMA_INT_TABLE: + (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + (pdma)->TOUTIEN &= ~(1UL << u32Ch); + break; + + default: + break; + } +} + +/**@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group PDMA_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_qei.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_qei.c new file mode 100644 index 0000000000..5076800571 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_qei.c @@ -0,0 +1,147 @@ +/**************************************************************************//** + * @file qei.c + * @version V3.00 + * $Revision: 2 $ + * $Date: 17/09/20 9:33a $ + * @brief Quadrature Encoder Interface (QEI) driver source file + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QEI_Driver QEI Driver + @{ +*/ + +/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions + @{ +*/ + +/** + * @brief Close QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function reset QEI configuration and stop QEI counting. + */ +void QEI_Close(QEI_T* qei) +{ + /* Reset QEI configuration */ + qei->CTL = 0UL; +} + +/** + * @brief Disable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function disable QEI specified interrupt. + */ +void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel) +{ + /* Disable QEI specified interrupt */ + QEI_DISABLE_INT(qei, u32IntSel); + + /* Disable NVIC QEI IRQ */ + if((qei == QEI0) || (qei == QEI0_NS)) + { + NVIC_DisableIRQ(QEI0_IRQn); + } + else + { + NVIC_DisableIRQ(QEI1_IRQn); + } +} + +/** + * @brief Enable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function enable QEI specified interrupt. + */ +void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel) +{ + /* Enable QEI specified interrupt */ + QEI_ENABLE_INT(qei, u32IntSel); + + /* Enable NVIC QEI IRQ */ + if((qei == QEI0) || (qei == QEI0_NS)) + { + NVIC_EnableIRQ(QEI0_IRQn); + } + else + { + NVIC_EnableIRQ(QEI1_IRQn); + } +} + +/** + * @brief Open QEI in specified mode and enable input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Mode QEI counting mode. + * - \ref QEI_CTL_X4_FREE_COUNTING_MODE + * - \ref QEI_CTL_X2_FREE_COUNTING_MODE + * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE + * @param[in] u32Value The counter maximum value in compare-counting mode. + * @return None + * @details This function set QEI in specified mode and enable input. + */ +void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value) +{ + /* Set QEI function configuration */ + /* Set QEI counting mode */ + /* Enable IDX, QEA and QEB input to QEI controller */ + qei->CTL = (qei->CTL & (~QEI_CTL_MODE_Msk)) | ((u32Mode) | QEI_CTL_CHAEN_Msk | QEI_CTL_CHBEN_Msk | QEI_CTL_IDXEN_Msk); + + /* Set QEI maximum count value in in compare-counting mode */ + qei->CNTMAX = u32Value; +} + +/** + * @brief Start QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function enable QEI function and start QEI counting. + */ +void QEI_Start(QEI_T* qei) +{ + /* Enable QEI controller function */ + qei->CTL |= QEI_CTL_QEIEN_Msk; +} + +/** + * @brief Stop QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function disable QEI function and stop QEI counting. + */ +void QEI_Stop(QEI_T* qei) +{ + /* Disable QEI controller function */ + qei->CTL &= (~QEI_CTL_QEIEN_Msk); +} + + +/**@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group QEI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_qspi.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_qspi.c new file mode 100644 index 0000000000..30baee2c85 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_qspi.c @@ -0,0 +1,859 @@ +/**************************************************************************//** + * @file qspi.c + * @version V3.00 + * @brief M2354 series QSPI driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief This function make QSPI module be ready to transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER) + * @param[in] u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a QSPI transaction. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI peripheral clock. + * @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0. + * The actual clock rate may be different from the target QSPI clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the + * actual QSPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency for Secure, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of + * QSPI bus clock cannot be faster than the system clock rate. User should set up carefully. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode for Secure, the QSPI peripheral clock rate will equal to APB clock rate. + * @note In slave mode for Non-Secure, the QSPI peripheral clock rate will equal to the clock rate set in secure mode. + */ +uint32_t QSPI_Open(QSPI_T *qspi, + uint32_t u32MasterSlave, + uint32_t u32QSPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0UL, u32Div, u32HCLKFreq, u32PCLK0Freq, u32RetValue = 0UL; + + if(u32DataWidth == 32UL) + { + u32DataWidth = 0UL; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + /* Get APB0 clock frequency */ + u32PCLK0Freq = CLK_GetPCLK0Freq(); + + if(u32MasterSlave == QSPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk; + + if(u32BusClock >= u32HCLKFreq) + { + if(!(__PC() & NS_OFFSET)) + { + /* Select PCLK as the clock source of QSPI */ + if((qspi == QSPI0) || (qspi == QSPI0_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + } + } + } + + /* Check clock source of QSPI */ + if((qspi == QSPI0) || (qspi == QSPI0_NS)) + { + if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0UL) + { + /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + if(u32Div > 0x1FFUL) + { + u32Div = 0x1FFUL; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1UL)); + } + } + } + else /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk; + + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + + if(!(__PC() & NS_OFFSET)) + { + /* Select PCLK as the clock source of QSPI */ + if((qspi == QSPI0) || (qspi == QSPI0_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK0Freq; + } + } + else + { + /* Check clock source of QSPI */ + if((qspi == QSPI0) || (qspi == QSPI0_NS)) + { + if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + u32RetValue = u32PCLK0Freq; /* Clock source is PCLK0 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + } + } + + return u32RetValue; +} + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details Clear SPIEN bit of QSPI_CTL register to disable QSPI transfer control. + */ +void QSPI_Close(QSPI_T *qspi) +{ + qspi->CTL &= ~QSPI_CTL_SPIEN_Msk; +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1. + */ +void QSPI_ClearRxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void QSPI_ClearTxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void QSPI_DisableAutoSS(QSPI_T *qspi) +{ + qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (QSPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the QSPI bus clock. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency for Secure, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of + * QSPI bus clock cannot be faster than the system clock rate. User should set up carefully. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Check if valid QSPI exist */ + if(!((qspi == QSPI0) || (qspi == QSPI0_NS))) + { + return 0UL; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32BusClock >= u32HCLKFreq) + { + if(!(__PC() & NS_OFFSET)) + { + /* Select PCLK as the clock source of QSPI */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + } + } + + /* Check clock source of QSPI */ + if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0UL) + { + /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + if(u32Div > 0x1FFUL) + { + u32Div = 0x1FFUL; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1UL)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of QSPI bus clock. Only available in Master mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Actual QSPI bus clock frequency in Hz. + * @details This function will calculate the actual QSPI bus clock rate according to the QQSPISEL/QSPIxSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t QSPI_GetBusClock(QSPI_T *qspi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Check if valid QSPI exist */ + if(!((qspi == QSPI0) || (qspi == QSPI0_NS))) + { + return 0UL; + } + + /* Get DIVIDER setting */ + u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of QSPI */ + if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + + /* Return QSPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1UL)); +} + +/** + * @brief Enable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL |= QSPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave mode time-out interrupt flag */ + if((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVTOIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave mode time-out interrupt flag */ + if((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVTOIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get QSPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32IntStatus; + uint32_t u32IntFlag = 0UL; + + u32IntStatus = qspi->STATUS; + + /* Check unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) && (u32IntStatus & QSPI_STATUS_UNITIF_Msk)) + { + u32IntFlag |= QSPI_UNIT_INT_MASK; + } + + /* Check slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) && (u32IntStatus & QSPI_STATUS_SSACTIF_Msk)) + { + u32IntFlag |= QSPI_SSACT_INT_MASK; + } + + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) && (u32IntStatus & QSPI_STATUS_SSINAIF_Msk)) + { + u32IntFlag |= QSPI_SSINACT_INT_MASK; + } + + /* Check slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) && (u32IntStatus & QSPI_STATUS_SLVURIF_Msk)) + { + u32IntFlag |= QSPI_SLVUR_INT_MASK; + } + + /* Check slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) && (u32IntStatus & QSPI_STATUS_SLVBEIF_Msk)) + { + u32IntFlag |= QSPI_SLVBE_INT_MASK; + } + + /* Check slave mode time-out interrupt flag */ + if((u32Mask & QSPI_SLVTO_INT_MASK) && (u32IntStatus & QSPI_STATUS_SLVTOIF_Msk)) + { + u32IntFlag |= QSPI_SLVTO_INT_MASK; + } + + /* Check slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) && (u32IntStatus & QSPI_STATUS_TXUFIF_Msk)) + { + u32IntFlag |= QSPI_TXUF_INT_MASK; + } + + /* Check TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32IntStatus & QSPI_STATUS_TXTHIF_Msk)) + { + u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK; + } + + /* Check RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32IntStatus & QSPI_STATUS_RXTHIF_Msk)) + { + u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK; + } + + /* Check RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32IntStatus & QSPI_STATUS_RXOVIF_Msk)) + { + u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK; + } + + /* Check RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32IntStatus & QSPI_STATUS_RXTOIF_Msk)) + { + u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear QSPI related interrupt flags specified by u32Mask parameter. + */ +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + if(u32Mask & QSPI_UNIT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if(u32Mask & QSPI_SSACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if(u32Mask & QSPI_SSINACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if(u32Mask & QSPI_SLVUR_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if(u32Mask & QSPI_SLVBE_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if(u32Mask & QSPI_SLVTO_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVTOIF_Msk; /* Clear slave mode time-out interrupt flag */ + } + + if(u32Mask & QSPI_TXUF_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if(u32Mask & QSPI_FIFO_RXOV_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if(u32Mask & QSPI_FIFO_RXTO_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get QSPI status. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref QSPI_BUSY_MASK + * - \ref QSPI_RX_EMPTY_MASK + * - \ref QSPI_RX_FULL_MASK + * - \ref QSPI_TX_EMPTY_MASK + * - \ref QSPI_TX_FULL_MASK + * - \ref QSPI_TXRX_RESET_MASK + * - \ref QSPI_SPIEN_STS_MASK + * - \ref QSPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get QSPI related status specified by u32Mask parameter. + */ +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32TmpStatus; + uint32_t u32Flag = 0UL; + + u32TmpStatus = qspi->STATUS; + + /* Check busy status */ + if((u32Mask & QSPI_BUSY_MASK) && (u32TmpStatus & QSPI_STATUS_BUSY_Msk)) + { + u32Flag |= QSPI_BUSY_MASK; + } + + /* Check RX empty flag */ + if((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpStatus & QSPI_STATUS_RXEMPTY_Msk)) + { + u32Flag |= QSPI_RX_EMPTY_MASK; + } + + /* Check RX full flag */ + if((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpStatus & QSPI_STATUS_RXFULL_Msk)) + { + u32Flag |= QSPI_RX_FULL_MASK; + } + + /* Check TX empty flag */ + if((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpStatus & QSPI_STATUS_TXEMPTY_Msk)) + { + u32Flag |= QSPI_TX_EMPTY_MASK; + } + + /* Check TX full flag */ + if((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpStatus & QSPI_STATUS_TXFULL_Msk)) + { + u32Flag |= QSPI_TX_FULL_MASK; + } + + /* Check TX/RX reset flag */ + if((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpStatus & QSPI_STATUS_TXRXRST_Msk)) + { + u32Flag |= QSPI_TXRX_RESET_MASK; + } + + /* Check SPIEN flag */ + if((u32Mask & QSPI_SPIEN_STS_MASK) && (u32TmpStatus & QSPI_STATUS_SPIENSTS_Msk)) + { + u32Flag |= QSPI_SPIEN_STS_MASK; + } + + /* Check QSPIx_SS line status */ + if((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpStatus & QSPI_STATUS_SSLINE_Msk)) + { + u32Flag |= QSPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + +/** + * @brief Get QSPI status2. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref QSPI_SLVBENUM_MASK + * + * @return Flags of selected sources. + * @details Get QSPI related status specified by u32Mask parameter. + */ +uint32_t QSPI_GetStatus2(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32TmpStatus; + uint32_t u32Number = 0UL; + + u32TmpStatus = qspi->STATUS2; + + /* Check effective bit number of uncompleted RX data status */ + if(u32Mask & QSPI_SLVBENUM_MASK) + { + u32Number = (u32TmpStatus & QSPI_STATUS2_SLVBENUM_Msk) >> QSPI_STATUS2_SLVBENUM_Pos; + } + + return u32Number; +} + +/**@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group QSPI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_rng.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_rng.c new file mode 100644 index 0000000000..6c009fc7b7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_rng.c @@ -0,0 +1,475 @@ +/**************************************************************************//** + * @file rng.c + * @version V3.00 + * @brief Show how to get true random number. + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RNG_Driver RNG Driver + @{ +*/ + + +/** @addtogroup RNG_EXPORTED_FUNCTIONS RNG Exported Functions + @{ +*/ + +typedef enum _RNG_KEY_SIZE { + KEY_128 = 0, + KEY_192 = 2, + KEY_224 = 3, + KEY_233 = 4, + KEY_255 = 5, + KEY_256 = 6, + KEY_283 = 7, + KEY_384 = 8, + KEY_409 = 9, + KEY_512 = 10, + KEY_521 = 11, + KEY_571 = 12 + +} eRNG_SZ; + + +/** + * @brief Open random number generator + * + * @return 0 Successful + * -1 Failed + * + * @details The function is used to disable rng interrupt. + */ +int32_t RNG_Open(void) +{ + int32_t i; + int32_t timeout = 0x1000000; + + /* Basic Configuration */ + CLK->AHBCLK |= CLK_AHBCLK_CRPTCKEN_Msk; + CLK->APBCLK1 |= CLK_APBCLK1_TRNGCKEN_Msk; + CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; + + RTC->LXTCTL |= (RTC_LXTCTL_C32KSEL_Msk | RTC_LXTCTL_LIRC32KEN_Msk); //To use LIRC32K + + TRNG->ACT |= TRNG_ACT_ACT_Msk; + /* Waiting for ready */ + i = 0; + while((TRNG->CTL & TRNG_CTL_READY_Msk) == 0) + { + if(i++ > timeout) + { + /* TRNG ready timeout */ + return -1; + } + } + + TRNG->CTL = (0 << TRNG_CTL_CLKPSC_Pos); + + + /* Enable SEEDGEN */ + TRNG->CTL |= (1 << 8); + + /* Waiting for seed ready */ + i = 0; + while((TRNG->CTL & (1 << 9)) == 0) + { + if(i++ > timeout) + { + /* seed ready timeout */ + return -1; + } + } + + // Waiting for PRNG busy + i = 0; + while(CRPT->PRNG_CTL & (1 << 8)) + { + if(i++ > timeout) + { + /* PRNG busy timeout */ + return -1; + } + } + + /* Set seed select to TRNG */ + CRPT->PRNG_CTL = CRPT_PRNG_CTL_SEEDSEL_Msk; + + /* Waiting for seed src ok */ + i = 0; + while((CRPT->PRNG_CTL & CRPT_PRNG_CTL_SEEDSRC_Msk) == 0) + { + if(i++ > timeout) + { + /* PRNG src timeout */ + return -1; // Timeout + } + } + + /* Reload seed only at first time */ + CRPT->PRNG_CTL |= (PRNG_KEY_SIZE_256 << CRPT_PRNG_CTL_KEYSZ_Pos) | CRPT_PRNG_CTL_START_Msk | CRPT_PRNG_CTL_SEEDRLD_Msk; + + i = 0; + while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) + { + if(i++ > timeout) + { + /* busy timeout */ + return -1; + } + } + + return 0; +} + + +/** + * @brief Get random words + * + * @param[in] pu32Buf Buffer pointer to store the random number + * + * @param[in] nWords Buffer size in word count. nWords must <= 8 + * + * @return Word count of random number in buffer + * + * @details The function is used to generate random numbers + */ +int32_t RNG_Random(uint32_t *pu32Buf, int32_t nWords) +{ + int32_t i; + int32_t timeout = 0x10000; + + /* Waiting for Busy */ + while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) {} + + if(nWords > 8) + nWords = 8; + + /* Trig to generate seed 256 bits random number */ + CRPT->PRNG_CTL = (6 << CRPT_PRNG_CTL_KEYSZ_Pos) | CRPT_PRNG_CTL_START_Msk; + + while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) + { + if(timeout-- < 0) + return 0; + } + + for(i=0; iPRNG_KEY[i]; + } + + return nWords; +} + + + +/** + * @brief To generate a key to KS SRAM for ECDSA. + * + * @param[in] u32KeySize It could be PRNG_KEY_SIZE_128 ~ PRNG_KEY_SIZE_571 + * + * @param[in] au32ECC_N The N value of specified ECC curve. + * + * @return -1 Failed + * Others The key number in KS SRAM + * + * @details The function is used to generate a key to KS SRAM for ECDSA. + * This key is necessary for ECDSA+Key Store function of ECC. + */ +int32_t RNG_ECDSA_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18]) +{ + int32_t i; + int32_t timeout = 0x1000000; + + /* Basic Configuration */ + CLK->AHBCLK |= CLK_AHBCLK_CRPTCKEN_Msk; + CLK->APBCLK1 |= CLK_APBCLK1_TRNGCKEN_Msk; + CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; + + RTC->LXTCTL |= (RTC_LXTCTL_C32KSEL_Msk | RTC_LXTCTL_LIRC32KEN_Msk); //To use LIRC32K + + TRNG->ACT |= TRNG_ACT_ACT_Msk; + /* Waiting for ready */ + i = 0; + while((TRNG->CTL & TRNG_CTL_READY_Msk) == 0) + { + if(i++ > timeout) + { + return -1; // Timeout + } + } + + TRNG->CTL = (0 << TRNG_CTL_CLKPSC_Pos); + + /* Reset seed select of PRNG */ + CRPT->PRNG_CTL = 0; + + + /* Enable SEEDGEN */ + TRNG->CTL |= TRNG_CTL_SEEDGEN_Msk; + + /* Waiting for seed ready */ + i = 0; + while((TRNG->CTL & TRNG_CTL_SEEDRDY_Msk) == 0) + { + if(i++ > timeout) + { + return -1; // Timeout + } + } + + // Waiting for PRNG busy + i = 0; + while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) + { + if(i++ > timeout) + { + return -1; // Timeout + } + } + + + // Set seed select to TRNG + CRPT->PRNG_CTL = 1 << CRPT_PRNG_CTL_SEEDSEL_Pos; + + // Waiting for seed src ok + i = 0; + while((CRPT->PRNG_CTL & CRPT_PRNG_CTL_SEEDSRC_Msk) == 0) + { + if(i++ > timeout) + { + return -1; // Timeout + } + } + + /* It is necessary to set ECC_N for ECDSA */ + for(i=0; i<18; i++) + CRPT->ECC_N[i] = au32ECC_N[i]; + + CRPT->PRNG_KSCTL = 0; + + /* Reload seed only at first time */ + CRPT->PRNG_CTL |= (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) | + CRPT_PRNG_CTL_START_Msk | CRPT_PRNG_CTL_SEEDRLD_Msk; + + + i = 0; + while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) + { + if(i++ > timeout) + { + return -1; // Timeout + } + } + + + CRPT->PRNG_KSCTL = (KS_OWNER_ECC << CRPT_PRNG_KSCTL_OWNER_Pos) | + CRPT_PRNG_KSCTL_ECDSA_Msk | + (CRPT_PRNG_KSCTL_WDST_Msk) | + (KS_SRAM << CRPT_PRNG_KSCTL_WSDST_Pos); + + return 0; +} + + +/** + * @brief To generate a key to KS SRAM for ECDSA. + * + * @return -1 Failed + * Others The key number in KS SRAM + * + * @details The function is used to generate a key to KS SRAM for ECDSA. + * This key is necessary for ECDSA+Key Store function of ECC. + */ +int32_t RNG_ECDSA(uint32_t u32KeySize) +{ + int32_t timeout; + int32_t i; + + /* Reload seed only at first time */ + CRPT->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) | + 0xc0 | + CRPT_PRNG_CTL_START_Msk; + + timeout = 0x10000; + i = 0; + while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) + { + if(i++ > timeout) + { + //printf("busy timeout\n"); + return -1; // Timeout + } + } + + if(CRPT->PRNG_KSSTS & CRPT_PRNG_KSSTS_KCTLERR_Msk) + { + //printf("KCTLERR!\n"); + return -1; + } + + return (CRPT->PRNG_KSSTS & CRPT_PRNG_KSCTL_NUM_Msk); +} + + + +/** + * @brief To generate a key to KS SRAM for ECDH. + * + * @param[in] u32KeySize It could be PRNG_KEY_SIZE_128 ~ PRNG_KEY_SIZE_571 + * + * @param[in] au32ECC_N The N value of specified ECC curve. + * + * @return -1 Failed + * Others The key number in KS SRAM + * + * @details The function is used to generate a key to KS SRAM for ECDH. + * This key is necessary for ECDH+Key Store function of ECC. + */ +int32_t RNG_ECDH_Init(uint32_t u32KeySize, uint32_t au32ECC_N[18]) +{ + int32_t i; + int32_t timeout = 0x1000000; + + /* Basic Configuration */ + CLK->AHBCLK |= CLK_AHBCLK_CRPTCKEN_Msk; + CLK->APBCLK1 |= CLK_APBCLK1_TRNGCKEN_Msk; + CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; + + RTC->LXTCTL |= (RTC_LXTCTL_C32KSEL_Msk | RTC_LXTCTL_LIRC32KEN_Msk); //To use LIRC32K + + TRNG->ACT |= TRNG_ACT_ACT_Msk; + /* Waiting for ready */ + i = 0; + while((TRNG->CTL & TRNG_CTL_READY_Msk) == 0) + { + if(i++ > timeout) + { + /* TRNG ready timeout */ + return -1; + } + } + + TRNG->CTL = (0 << TRNG_CTL_CLKPSC_Pos); + + + /* Enable SEEDGEN */ + TRNG->CTL |= TRNG_CTL_SEEDGEN_Msk; + + /* Waiting for seed ready */ + i = 0; + while((TRNG->CTL & TRNG_CTL_SEEDRDY_Msk) == 0) + { + if(i++ > timeout) + { + /* seed ready timeout */ + return -1; + } + } + + /* Waiting for PRNG busy */ + i = 0; + while(CRPT->PRNG_CTL & TRNG_CTL_SEEDGEN_Msk) + { + if(i++ > timeout) + { + /* PRNG busy timeout */ + return -1; + } + } + + + + /* Set seed select to TRNG */ + CRPT->PRNG_CTL = (1 << 6); + + // Waiting for seed src ok + i = 0; + while((CRPT->PRNG_CTL & (1 << 7)) == 0) + { + if(i++ > timeout) + { + /* PRNG src timeout */ + return -1; + } + } + + /* It is necessary to set ECC_N for ECDSA */ + for(i=0; i<18; i++) + CRPT->ECC_N[i] = au32ECC_N[i]; + + CRPT->PRNG_KSCTL = 0; + + /* Reload seed only at first time */ + CRPT->PRNG_CTL |= (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) | + CRPT_PRNG_CTL_START_Msk | CRPT_PRNG_CTL_SEEDRLD_Msk; + + + i = 0; + while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) + { + if(i++ > timeout) + { + /* busy timeout */ + return -1; + } + } + + CRPT->PRNG_KSCTL = (KS_OWNER_ECC << CRPT_PRNG_KSCTL_OWNER_Pos) | + (CRPT_PRNG_KSCTL_ECDH_Msk) | + (CRPT_PRNG_KSCTL_WDST_Msk) | + (KS_SRAM << CRPT_PRNG_KSCTL_WSDST_Pos); + + return 0; +} + + +/** + * @brief To generate a key to KS SRAM for ECDH. + * + * @return -1 Failed + * Others The key number in KS SRAM + * + * @details The function is used to generate a key to KS SRAM for ECDH. + * This key is necessary for ECDH+Key Store function of ECC. + */ +int32_t RNG_ECDH(uint32_t u32KeySize) +{ + int32_t timeout; + int32_t i; + + /* Reload seed only at first time */ + CRPT->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) | + 0xc0 | + CRPT_PRNG_CTL_START_Msk; + + timeout = 0x10000; + i = 0; + while(CRPT->PRNG_CTL & CRPT_PRNG_CTL_BUSY_Msk) + { + if(i++ > timeout) + return -1; + } + + if(CRPT->PRNG_KSSTS & CRPT_PRNG_KSSTS_KCTLERR_Msk) + return -1; + + return (CRPT->PRNG_KSSTS & CRPT_PRNG_KSCTL_NUM_Msk); +} + +/**@}*/ /* end of group RNG_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group RNG_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_rtc.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_rtc.c new file mode 100644 index 0000000000..7685a19ffe --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_rtc.c @@ -0,0 +1,1174 @@ +/**************************************************************************//** + * @file rtc.c + * @version V3.00 + * @brief Real Time Clock(RTC) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @cond HIDDEN_SYMBOLS */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Global file scope (static) variables */ +/*---------------------------------------------------------------------------------------------------------*/ +static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay; +static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec; + +/** @endcond HIDDEN_SYMBOLS */ + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Initialize RTC module and start counting + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This function is used to: \n + * 1. Write initial key to let RTC start count. \n + * 2. Input parameter indicates start date/time. \n + * 3. User has to make sure that parameters of RTC date/time are reasonable. \n + * 4. Enable frequency dynamic compensation function. \n + * @note Null pointer for using default starting date/time. + */ +void RTC_Open(S_RTC_TIME_DATA_T *sPt) +{ + RTC->INIT = RTC_INIT_KEY; + + if(RTC->INIT != RTC_INIT_ACTIVE_Msk) + { + RTC->INIT = RTC_INIT_KEY; + while(RTC->INIT != RTC_INIT_ACTIVE_Msk) {} + } + + if(sPt != 0) + { + /* Enable frequency dynamic compensation function */ + RTC->CLKFMT |= RTC_CLKFMT_DCOMPEN_Msk; + + /* Set RTC date and time */ + RTC_SetDateAndTime(sPt); + } +} + +/** + * @brief Disable RTC Clock + * + * @param None + * + * @return None + * + * @details This API will disable RTC peripheral clock. + */ +void RTC_Close(void) +{ + if((__PC()&NS_OFFSET) != NS_OFFSET) + { + /* Only available in Secure code */ + CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; + } +} + +/** + * @brief Set 32K Frequency Compensation Data + * + * @param[in] i32FrequencyX10000 Specify the RTC clock X10000, ex: 327736512 means 32773.6512. + * + * @return None + * + * @details This API is used to compensate the 32 kHz frequency by current LXT frequency for RTC application. + */ +void RTC_32KCalibration(int32_t i32FrequencyX10000) +{ + int32_t i32RegInt, i32RegFra; + + /* Compute integer and fraction for RTC FCR register */ + i32RegInt = (i32FrequencyX10000 / 10000) - RTC_FCR_REFERENCE; + i32RegFra = ((((i32FrequencyX10000 % 10000)) * 64) + 5000) / 10000; + + if(i32RegFra >= 0x40) + { + i32RegFra = 0x0; + i32RegInt++; + } + + /* Judge Integer part is reasonable */ + if((i32RegInt >= 0) && (i32RegInt <= 31)) + { + while((RTC->FREQADJ & RTC_FREQADJ_FCRBUSY_Msk) == RTC_FREQADJ_FCRBUSY_Msk) {} + RTC->FREQADJ = (uint32_t)((i32RegInt << 8) | i32RegFra); + while((RTC->FREQADJ & RTC_FREQADJ_FCRBUSY_Msk) == RTC_FREQADJ_FCRBUSY_Msk) {} + } +} + +/** + * @brief Get Current RTC Date and Time + * + * @param[out] sPt The returned pointer is specified the current RTC value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the current RTC date and time value. + */ +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get [Date digit] data */ + g_u32hiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos; + g_u32loYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos; + g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos; + g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos; + g_u32hiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos; + g_u32loDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos; + + /* Get [Time digit] data */ + g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos; + g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos; + g_u32hiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos; + g_u32loMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos; + g_u32hiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos; + g_u32loSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10UL); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + (uint32_t)RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10UL); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10UL); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10UL); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21UL) + { + sPt->u32AmPm = (uint32_t)RTC_PM; + sPt->u32Hour -= 20UL; + } + else + { + sPt->u32AmPm = (uint32_t)RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10UL); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10UL); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } + else + { + u32Tmp = (g_u32hiHour * 10UL); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10UL); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10UL); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Get RTC Alarm Date and Time + * + * @param[out] sPt The returned pointer is specified the RTC alarm value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the RTC alarm date and time setting. + */ +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get alarm [Date digit] data */ + g_u32hiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos; + g_u32loYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos; + g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos; + g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos; + g_u32hiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos; + g_u32loDay = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos; + + /* Get alarm [Time digit] data */ + g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos; + g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos; + g_u32hiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos; + g_u32loMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos; + g_u32hiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos; + g_u32loSec = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10UL); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + (uint32_t)RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10UL); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10UL); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10UL); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21UL) + { + sPt->u32AmPm = (uint32_t)RTC_PM; + sPt->u32Hour -= 20UL; + } + else + { + sPt->u32AmPm = (uint32_t)RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10UL); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10UL); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } + else + { + u32Tmp = (g_u32hiHour * 10UL); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10UL); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10UL); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Update Current RTC Date and Time + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update current date and time to RTC. + */ +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCAL, u32RegTIME; + + if(sPt != 0) + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == (uint32_t)RTC_PM) + { + sPt->u32Hour += 20UL; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set Day of the Week */ + RTC->WEEKDAY = sPt->u32DayOfWeek; + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Current Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCAL = ((sPt->u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20; + u32RegCAL |= (((sPt->u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16); + u32RegCAL |= ((sPt->u32Month / 10UL) << 12); + u32RegCAL |= ((sPt->u32Month % 10UL) << 8); + u32RegCAL |= ((sPt->u32Day / 10UL) << 4); + u32RegCAL |= (sPt->u32Day % 10UL); + + u32RegTIME = ((sPt->u32Hour / 10UL) << 20); + u32RegTIME |= ((sPt->u32Hour % 10UL) << 16); + u32RegTIME |= ((sPt->u32Minute / 10UL) << 12); + u32RegTIME |= ((sPt->u32Minute % 10UL) << 8); + u32RegTIME |= ((sPt->u32Second / 10UL) << 4); + u32RegTIME |= (sPt->u32Second % 10UL); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Calender and Time Loading */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC->CAL = (uint32_t)u32RegCAL; + RTC->TIME = (uint32_t)u32RegTIME; + } +} + +/** + * @brief Update RTC Alarm Date and Time + * + * @param[in] sPt Specify the time property and alarm date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update alarm date and time setting to RTC. + */ +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCALM, u32RegTALM; + + if(sPt != 0) + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == (uint32_t)RTC_PM) + { + sPt->u32Hour += 20UL; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Alarm Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCALM = ((sPt->u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20; + u32RegCALM |= (((sPt->u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16); + u32RegCALM |= ((sPt->u32Month / 10UL) << 12); + u32RegCALM |= ((sPt->u32Month % 10UL) << 8); + u32RegCALM |= ((sPt->u32Day / 10UL) << 4); + u32RegCALM |= (sPt->u32Day % 10UL); + + u32RegTALM = ((sPt->u32Hour / 10UL) << 20); + u32RegTALM |= ((sPt->u32Hour % 10UL) << 16); + u32RegTALM |= ((sPt->u32Minute / 10UL) << 12); + u32RegTALM |= ((sPt->u32Minute % 10UL) << 8); + u32RegTALM |= ((sPt->u32Second / 10UL) << 4); + u32RegTALM |= (sPt->u32Second % 10UL); + + RTC->CALM = (uint32_t)u32RegCALM; + RTC->TALM = (uint32_t)u32RegTALM; + } +} + +/** + * @brief Update RTC Current Date + * + * @param[in] u32Year The year calendar digit of current RTC setting. + * @param[in] u32Month The month calendar digit of current RTC setting. + * @param[in] u32Day The day calendar digit of current RTC setting. + * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] + * + * @return None + * + * @details This API is used to update current date to RTC. + */ +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek) +{ + uint32_t u32RegCAL; + + u32RegCAL = ((u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20; + u32RegCAL |= (((u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16); + u32RegCAL |= ((u32Month / 10UL) << 12); + u32RegCAL |= ((u32Month % 10UL) << 8); + u32RegCAL |= ((u32Day / 10UL) << 4); + u32RegCAL |= (u32Day % 10UL); + + + /* Set Day of the Week */ + RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk; + + /* Set RTC Calender Loading */ + RTC->CAL = (uint32_t)u32RegCAL; +} + +/** + * @brief Update RTC Current Time + * + * @param[in] u32Hour The hour time digit of current RTC setting. + * @param[in] u32Minute The minute time digit of current RTC setting. + * @param[in] u32Second The second time digit of current RTC setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update current time to RTC. + */ +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTIME; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == (uint32_t)RTC_CLOCK_12) && (u32AmPm == (uint32_t)RTC_PM)) + { + u32Hour += 20UL; + } + + u32RegTIME = ((u32Hour / 10UL) << 20); + u32RegTIME |= ((u32Hour % 10UL) << 16); + u32RegTIME |= ((u32Minute / 10UL) << 12); + u32RegTIME |= ((u32Minute % 10UL) << 8); + u32RegTIME |= ((u32Second / 10UL) << 4); + u32RegTIME |= (u32Second % 10UL); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + if(u32TimeMode == (uint32_t)RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + RTC->TIME = (uint32_t)u32RegTIME; +} + +/** + * @brief Update RTC Alarm Date + * + * @param[in] u32Year The year calendar digit of RTC alarm setting. + * @param[in] u32Month The month calendar digit of RTC alarm setting. + * @param[in] u32Day The day calendar digit of RTC alarm setting. + * + * @return None + * + * @details This API is used to update alarm date setting to RTC. + */ +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day) +{ + uint32_t u32RegCALM; + + u32RegCALM = ((u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20; + u32RegCALM |= (((u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16); + u32RegCALM |= ((u32Month / 10UL) << 12); + u32RegCALM |= ((u32Month % 10UL) << 8); + u32RegCALM |= ((u32Day / 10UL) << 4); + u32RegCALM |= (u32Day % 10UL); + + + /* Set RTC Alarm Date */ + RTC->CALM = (uint32_t)u32RegCALM; +} + +/** + * @brief Update RTC Alarm Time + * + * @param[in] u32Hour The hour time digit of RTC alarm setting. + * @param[in] u32Minute The minute time digit of RTC alarm setting. + * @param[in] u32Second The second time digit of RTC alarm setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update alarm time setting to RTC. + */ +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTALM; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == (uint32_t)RTC_CLOCK_12) && (u32AmPm == (uint32_t)RTC_PM)) + { + u32Hour += 20UL; + } + + u32RegTALM = ((u32Hour / 10UL) << 20); + u32RegTALM |= ((u32Hour % 10UL) << 16); + u32RegTALM |= ((u32Minute / 10UL) << 12); + u32RegTALM |= ((u32Minute % 10UL) << 8); + u32RegTALM |= ((u32Second / 10UL) << 4); + u32RegTALM |= (u32Second % 10UL); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + if(u32TimeMode == (uint32_t)RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set RTC Alarm Time */ + RTC->TALM = (uint32_t)u32RegTALM; +} + +/** + * @brief Set RTC Alarm Date Mask Function + * + * @param[in] u8IsTenYMsk 1: enable 10-Year digit alarm mask; 0: disabled. + * @param[in] u8IsYMsk 1: enable 1-Year digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsTenDMsk 1: enable 10-Day digit alarm mask; 0: disabled. + * @param[in] u8IsDMsk 1: enable 1-Day digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm date mask function. + */ +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk) +{ + RTC->CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) | + ((uint32_t)u8IsYMsk << RTC_CAMSK_MYEAR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) | + ((uint32_t)u8IsMMsk << RTC_CAMSK_MMON_Pos) | + ((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) | + ((uint32_t)u8IsDMsk << RTC_CAMSK_MDAY_Pos); +} + +/** + * @brief Set RTC Alarm Time Mask Function + * + * @param[in] u8IsTenHMsk 1: enable 10-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsHMsk 1: enable 1-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Min digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Min digit alarm mask; 0: disabled. + * @param[in] u8IsTenSMsk 1: enable 10-Sec digit alarm mask; 0: disabled. + * @param[in] u8IsSMsk 1: enable 1-Sec digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm time mask function. + */ +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk) +{ + RTC->TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) | + ((uint32_t)u8IsHMsk << RTC_TAMSK_MHR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) | + ((uint32_t)u8IsMMsk << RTC_TAMSK_MMIN_Pos) | + ((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) | + ((uint32_t)u8IsSMsk << RTC_TAMSK_MSEC_Pos); +} + +/** + * @brief Get Day of the Week + * + * @param None + * + * @retval 0 Sunday + * @retval 1 Monday + * @retval 2 Tuesday + * @retval 3 Wednesday + * @retval 4 Thursday + * @retval 5 Friday + * @retval 6 Saturday + * + * @details This API is used to get day of the week of current RTC date. + */ +uint32_t RTC_GetDayOfWeek(void) +{ + return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk); +} + +/** + * @brief Set RTC Tick Period Time + * + * @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n + * It consists of: + * - \ref RTC_TICK_1_SEC : Time tick is 1 second + * - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second + * - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second + * - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second + * - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second + * - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second + * - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second + * - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second + * + * @return None + * + * @details This API is used to set RTC tick period time for each tick interrupt. + */ +void RTC_SetTickPeriod(uint32_t u32TickSelection) +{ + RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection; +} + +/** + * @brief Enable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 or Pair 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 or Pair 1 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 or Pair 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_CLKFIEN_Msk : LXT Clock Frequency Monitor Fail interrupt + * - \ref RTC_INTEN_CLKSTIEN_Msk : LXT Clock Frequency Monitor Stop interrupt + * + * @return None + * + * @details This API is used to enable the specify RTC interrupt function. + */ +void RTC_EnableInt(uint32_t u32IntFlagMask) +{ + RTC->INTEN |= u32IntFlagMask; +} + +/** + * @brief Disable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 or Pair 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 or Pair 1 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 or Pair 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_CLKFIEN_Msk : LXT Clock Frequency Monitor Fail interrupt + * - \ref RTC_INTEN_CLKSTIEN_Msk : LXT Clock Frequency Monitor Stop interrupt + * + * @return None + * + * @details This API is used to disable the specify RTC interrupt function. + */ +void RTC_DisableInt(uint32_t u32IntFlagMask) +{ + RTC->INTEN &= ~u32IntFlagMask; + RTC->INTSTS = u32IntFlagMask; +} + +/** + * @brief Enable Spare Registers Access + * + * @param None + * + * @return None + * + * @details This API is used to enable the spare registers 0~19 can be accessed. + */ +void RTC_EnableSpareAccess(void) +{ + RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk; +} + +/** + * @brief Disable Spare Register + * + * @param None + * + * @return None + * + * @details This API is used to disable the spare register 0~19 cannot be accessed. + */ +void RTC_DisableSpareRegister(void) +{ + RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk; +} + +/** + * @brief Static Tamper Detect + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER5_SELECT + * - \ref RTC_TAMPER4_SELECT + * - \ref RTC_TAMPER3_SELECT + * - \ref RTC_TAMPER2_SELECT + * - \ref RTC_TAMPER1_SELECT + * - \ref RTC_TAMPER0_SELECT + * + * @param[in] u32DetecLevel Tamper pin detection level select. Possible options are + * - \ref RTC_TAMPER_HIGH_LEVEL_DETECT + * - \ref RTC_TAMPER_LOW_LEVEL_DETECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref RTC_TAMPER_DEBOUNCE_ENABLE + * - \ref RTC_TAMPER_DEBOUNCE_DISABLE + * + * @return None + * + * @details This API is used to enable the tamper pin detect function with specify trigger condition. + * User need disable dynamic tamper function before use this API. + */ +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + u32Reg = RTC->TAMPCTL; + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) | + (u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos)); + + for(i = 0UL; i < (uint32_t)RTC_MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1UL << i)) + { + u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP0LV_Msk | RTC_TAMPCTL_TAMP0DBEN_Msk) << (i * 4UL)); + u32Reg |= (u32TmpReg << (i * 4UL)); + } + } + + RTC->TAMPCTL = u32Reg; + +} + +/** + * @brief Static Tamper Disable + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER5_SELECT + * - \ref RTC_TAMPER4_SELECT + * - \ref RTC_TAMPER3_SELECT + * - \ref RTC_TAMPER2_SELECT + * - \ref RTC_TAMPER1_SELECT + * - \ref RTC_TAMPER0_SELECT + * + * @return None + * + * @details This API is used to disable the static tamper pin detect. + */ +void RTC_StaticTamperDisable(uint32_t u32TamperSelect) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + u32Reg = RTC->TAMPCTL; + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk); + + for(i = 0UL; i < (uint32_t)RTC_MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1UL << i)) + { + u32Reg &= ~(u32TmpReg << (i * 4UL)); + } + } + + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Detect + * + * @param[in] u32PairSel Tamper pin detection enable. Possible options are + * - \ref RTC_PAIR0_SELECT + * - \ref RTC_PAIR1_SELECT + * - \ref RTC_PAIR2_SELECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref RTC_TAMPER_DEBOUNCE_ENABLE + * - \ref RTC_TAMPER_DEBOUNCE_DISABLE + * + * @param[in] u32Pair1Source Dynamic Pair 1 Input Source Select + * 0: Pair 1 source select tamper 2 + * 1: Pair 1 source select tamper 0 + * + * @param[in] u32Pair2Source Dynamic Pair 2 Input Source Select + * 0: Pair 2 source select tamper 4 + * 1: Pair 2 source select tamper 0 + * + * @return None + * + * @details This API is used to enable the dynamic tamper. + */ +void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2Debounce, u32Tamper4Debounce; + + u32Reg = RTC->TAMPCTL; + u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk | + RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk); + + u32Tamper2Debounce = u32Reg & RTC_TAMPCTL_TAMP2DBEN_Msk; + u32Tamper4Debounce = u32Reg & RTC_TAMPCTL_TAMP4DBEN_Msk; + + u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk | + RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk); + u32Reg &= ~(RTC_TAMPCTL_DYN1ISS_Msk | RTC_TAMPCTL_DYN2ISS_Msk); + u32Reg |= ((u32Pair1Source & 0x1UL) << RTC_TAMPCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1UL) << RTC_TAMPCTL_DYN2ISS_Pos); + + if(u32DebounceEn) + { + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | + RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + } + else + { + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + } + + for(i = 0UL; i < (uint32_t)RTC_MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1UL << i)) + { + u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i * 8UL)); + u32Reg |= (u32TmpReg << (i * 8UL)); + } + } + + if((u32Pair1Source) && (u32PairSel & (uint32_t)RTC_PAIR1_SELECT)) + { + u32Reg &= ~RTC_TAMPCTL_TAMP2EN_Msk; + u32Reg |= u32Tamper2Debounce; + } + + if((u32Pair2Source) && (u32PairSel & (uint32_t)RTC_PAIR2_SELECT)) + { + u32Reg &= ~RTC_TAMPCTL_TAMP4EN_Msk; + u32Reg |= u32Tamper4Debounce; + } + + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Disable + * + * @param[in] u32PairSel Tamper pin detection enable. Possible options are + * - \ref RTC_PAIR0_SELECT + * - \ref RTC_PAIR1_SELECT + * - \ref RTC_PAIR2_SELECT + * + * @return None + * + * @details This API is used to disable the dynamic tamper. + */ +void RTC_DynamicTamperDisable(uint32_t u32PairSel) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2En = 0UL, u32Tamper4En = 0UL; + + u32Reg = RTC->TAMPCTL; + + if((u32Reg & (uint32_t)RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & (uint32_t)RTC_PAIR1_SELECT)) + { + u32Tamper2En = u32Reg & RTC_TAMPCTL_TAMP2EN_Msk; + } + + if((u32Reg & (uint32_t)RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & (uint32_t)RTC_PAIR2_SELECT)) + { + u32Tamper4En = u32Reg & RTC_TAMPCTL_TAMP4EN_Msk; + } + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + + for(i = 0UL; i < (uint32_t)RTC_MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1UL << i)) + { + u32Reg &= ~(u32TmpReg << ((i * 8UL))); + } + } + + u32Reg |= (u32Tamper2En | u32Tamper4En); + + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Config Dynamic Tamper + * + * @param[in] u32ChangeRate The dynamic tamper output change rate + * - \ref RTC_2POW10_CLK + * - \ref RTC_2POW11_CLK + * - \ref RTC_2POW12_CLK + * - \ref RTC_2POW13_CLK + * - \ref RTC_2POW14_CLK + * - \ref RTC_2POW15_CLK + * - \ref RTC_2POW16_CLK + * - \ref RTC_2POW17_CLK + * + * @param[in] u32SeedReload Reload new seed or not + * 0: not reload new seed + * 1: reload new seed + * + * @param[in] u32RefPattern Reference pattern + * - \ref RTC_REF_RANDOM_PATTERN + * - \ref RTC_REF_SEED_VALUE + * + * @param[in] u32Seed Seed Value (0x0 ~ 0xFFFFFFFF) + * + * @return None + * + * @details This API is used to config dynamic tamper setting. + */ +void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed) +{ + uint32_t u32Reg; + + u32Reg = RTC->TAMPCTL; + + u32Reg &= ~(RTC_TAMPCTL_DYNSRC_Msk | RTC_TAMPCTL_SEEDRLD_Msk | RTC_TAMPCTL_DYNRATE_Msk); + + u32Reg |= (u32ChangeRate) | ((u32SeedReload & 0x1UL) << RTC_TAMPCTL_SEEDRLD_Pos) | + (u32RefPattern << RTC_TAMPCTL_DYNSRC_Pos); + + RTC->TAMPSEED = u32Seed; /* need set seed value before re-loade seed */ + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Set RTC Clock Source + * + * @param[in] u32ClkSrc u32ClkSrc is the RTC clock source. It could be + * - \ref RTC_CLOCK_SOURCE_LXT + * - \ref RTC_CLOCK_SOURCE_LIRC + * - \ref RTC_CLOCK_SOURCE_LIRC32K + * + * @retval RTC_CLOCK_SOURCE_LXT + * @retval RTC_CLOCK_SOURCE_LIRC + * @retval RTC_CLOCK_SOURCE_LIRC32K + * + * @details This API is used to get the setting of RTC clock source. + * User must to enable the selected clock source by themselves executing perform this API. + */ +uint32_t RTC_SetClockSource(uint32_t u32ClkSrc) +{ + if(u32ClkSrc == RTC_CLOCK_SOURCE_LXT) + { + /* RTC clock source is external LXT */ + RTC->LXTCTL &= ~RTC_LXTCTL_RTCCKSEL_Msk; + RTC->LXTCTL &= ~RTC_LXTCTL_C32KSEL_Msk; + + return RTC_CLOCK_SOURCE_LXT; + } + else if(u32ClkSrc == RTC_CLOCK_SOURCE_LIRC32K) + { + /* Load LIRC32 trim setting */ + RTC->LXTCTL = ((RTC->LXTCTL & ~(0x1FFul << 16)) | ((inpw(SYS_BASE+0x14Cul) & 0x1FFul) << 16)); + + /* RTC clock source is LIRC32K */ + RTC->LXTCTL |= RTC_LXTCTL_LIRC32KEN_Msk; + RTC->LXTCTL &= ~RTC_LXTCTL_RTCCKSEL_Msk; + RTC->LXTCTL |= RTC_LXTCTL_C32KSEL_Msk; + + return RTC_CLOCK_SOURCE_LIRC32K; + } + else if(u32ClkSrc == RTC_CLOCK_SOURCE_LIRC) + { + /* RTC clock source is LIRC */ + RTC->LXTCTL |= RTC_LXTCTL_RTCCKSEL_Msk; + + return RTC_CLOCK_SOURCE_LIRC; + } + else + { + /* Set the default RTC clock source is LIRC */ + RTC->LXTCTL |= RTC_LXTCTL_RTCCKSEL_Msk; + + return RTC_CLOCK_SOURCE_LIRC; + } +} + +/** + * @brief Set RTC GPIO Operation Mode + * + * @param[in] u32Pin The single pin of GPIO-F port. + * It could be 4~11, which means PF.4~PF.11. + * @param[in] u32Mode Operation mode. It could be + * - \ref RTC_IO_MODE_INPUT + * - \ref RTC_IO_MODE_OUTPUT + * - \ref RTC_IO_MODE_OPEN_DRAIN + * - \ref RTC_IO_MODE_QUASI + * @param[in] u32DigitalCtl The digital input path control of specified pin. It could be + * - \ref RTC_IO_DIGITAL_ENABLE + * - \ref RTC_IO_DIGITAL_DISABLE + * @param[in] u32PullCtl The pull-up or pull-down control of specified pin. It could be + * - \ref RTC_IO_PULL_UP_DOWN_DISABLE + * - \ref RTC_IO_PULL_UP_ENABLE + * - \ref RTC_IO_PULL_DOWN_ENABLE + * @param[in] u32OutputLevel The I/O output level. 0: output low; 1: output high. + * + * @return None + * + * @details This function is used to set specified GPIO operation mode controlled by RTC module. + */ +void RTC_SetGPIOMode(uint32_t u32PFPin, uint32_t u32Mode, uint32_t u32DigitalCtl, uint32_t u32PullCtl, uint32_t u32OutputLevel) +{ + uint32_t u32Offset; + + if((u32PFPin == 4) || (u32PFPin == 5) || (u32PFPin == 6) || (u32PFPin == 7)) + { + u32Offset = u32PFPin - 4; + + RTC_SET_IOCTL_BY_RTC(RTC); + + RTC->GPIOCTL0 = (RTC->GPIOCTL0 & ~(0x3FUL << (u32Offset*8))) | + (u32Mode << (u32Offset*8)) | + (u32OutputLevel << ((u32Offset*8) + 2)) | + (u32DigitalCtl << ((u32Offset*8) + 3)) | + (u32PullCtl << ((u32Offset*8) + 4)); + } + + if((u32PFPin == 8) || (u32PFPin == 9) || (u32PFPin == 10) || (u32PFPin == 11)) + { + u32Offset = u32PFPin - 8; + + RTC_SET_IOCTL_BY_RTC(RTC); + + RTC->GPIOCTL1 = (RTC->GPIOCTL1 & ~(0x3FUL << (u32Offset*8))) | + (u32Mode << (u32Offset*8)) | + (u32OutputLevel << ((u32Offset*8) + 2)) | + (u32DigitalCtl << ((u32Offset*8) + 3)) | + (u32PullCtl << ((u32Offset*8) + 4)); + } +} + +/** + * @brief Set RTC GPIO Output Level + * + * @param[in] u32Pin The single pin of GPIO-F port. + * It could be 4~11, which means PF.4~PF.11. + * @param[in] u32OutputLevel The I/O output level. 0: output low; 1: output high. + * + * @return None + * + * @details This function is used to set GPIO output level by RTC module. + */ +void RTC_SetGPIOLevel(uint32_t u32PFPin, uint32_t u32OutputLevel) +{ + uint32_t u32Offset; + + if((u32PFPin == 4) || (u32PFPin == 5) || (u32PFPin == 6) || (u32PFPin == 7)) + { + u32Offset = u32PFPin - 4; + + RTC->GPIOCTL0 = (RTC->GPIOCTL0 & ~(0x4UL << (u32Offset*8))) | + (u32OutputLevel << ((u32Offset*8) + 2)); + } + + if((u32PFPin == 8) || (u32PFPin == 9) || (u32PFPin == 10) || (u32PFPin == 11)) + { + u32Offset = u32PFPin - 8; + + RTC->GPIOCTL1 = (RTC->GPIOCTL1 & ~(0x4UL << (u32Offset*8))) | + (u32OutputLevel << ((u32Offset*8) + 2)); + } +} + +/**@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group RTC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_sc.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_sc.c new file mode 100644 index 0000000000..3eed83dd88 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_sc.c @@ -0,0 +1,427 @@ +/**************************************************************************//** + * @file sc.c + * @version V3.00 + * @brief Smartcard(SC) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + + +/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */ +/** @cond HIDDEN_SYMBOLS */ +static uint32_t g_u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL, 0UL, 0UL}; + +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions + @{ +*/ + +/** + * @brief Indicates specified smartcard slot status + * + * @param[in] sc The pointer of smartcard module. + * + * @return Card insert status + * @retval TRUE Card insert + * @retval FALSE Card remove + * + * @details This function is used to check if specified smartcard slot is presented. + */ +uint32_t SC_IsCardInserted(SC_T *sc) +{ + uint32_t u32Ret; + + /* put conditions into two variable to remove IAR compilation warning */ + uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos); + uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos); + + if(((sc == SC0) || (sc == SC0_NS)) && (g_u32CardStateIgnore[0] == 1UL)) + { + u32Ret = (uint32_t)TRUE; + } + else if(((sc == SC1) || (sc == SC1_NS)) && (g_u32CardStateIgnore[1] == 1UL)) + { + u32Ret = (uint32_t)TRUE; + } + else if(((sc == SC2) || (sc == SC2_NS)) && (g_u32CardStateIgnore[2] == 1UL)) + { + u32Ret = (uint32_t)TRUE; + } + else if(cond1 != cond2) + { + u32Ret = (uint32_t)FALSE; + } + else + { + u32Ret = (uint32_t)TRUE; + } + + return u32Ret; +} + +/* + * @brief Reset the Tx and Rx FIFO of smartcard module + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @details This function reset both transmit and receive FIFO of specified smartcard module. + */ +void SC_ClearFIFO(SC_T *sc) +{ + while((sc->ALTCTL & SC_ALTCTL_SYNC_Msk) == SC_ALTCTL_SYNC_Msk) {} + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk); +} + +/** + * @brief Disable specified smartcard module + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @details This function disable specified smartcard module, and force all transition to IDLE state. + */ +void SC_Close(SC_T *sc) +{ + sc->INTEN = 0UL; + + while((sc->PINCTL & SC_PINCTL_SYNC_Msk) == SC_PINCTL_SYNC_Msk) {} + sc->PINCTL = 0UL; + sc->ALTCTL = 0UL; + + while((sc->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {} + sc->CTL = 0UL; +} + +/** + * @brief Initialized smartcard module + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32CardDet Card detect polarity, select the SC_CD pin state which indicates card absent. Could be: + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present. + * @param[in] u32PWR Power off polarity, select the SC_PWR pin state which could set smartcard VCC to high level. Could be: + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * + * @return None + * + * @details This function initialized smartcard module. + */ +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR) +{ + uint32_t u32Reg = 0UL, u32Intf; + + if((sc == SC0) || (sc == SC0_NS)) + { + u32Intf = 0UL; + } + else if((sc == SC1) || (sc == SC1_NS)) + { + u32Intf = 1UL; + } + else + { + u32Intf = 2UL; + } + + if(u32CardDet != SC_PIN_STATE_IGNORE) + { + u32Reg = u32CardDet ? 0UL : SC_CTL_CDLV_Msk; + g_u32CardStateIgnore[u32Intf] = 0UL; + } + else + { + g_u32CardStateIgnore[u32Intf] = 1UL; + } + sc->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk; + + while((sc->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {} + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_TMRSEL_Msk | u32Reg; +} + +/** + * @brief Reset specified smartcard module + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @details This function reset specified smartcard module to its default state for activate smartcard. + */ +void SC_ResetReader(SC_T *sc) +{ + uint32_t u32Intf; + + if((sc == SC0) || (sc == SC0_NS)) + { + u32Intf = 0UL; + } + else if((sc == SC1) || (sc == SC1_NS)) + { + u32Intf = 1UL; + } + else + { + u32Intf = 2UL; + } + + /* Reset FIFO, enable auto de-activation while card removal */ + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk); + /* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */ + while((sc->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {} + sc->CTL &= ~(SC_CTL_RXTRGLV_Msk | + SC_CTL_CDDBSEL_Msk | + SC_CTL_TXRTY_Msk | + SC_CTL_TXRTYEN_Msk | + SC_CTL_RXRTY_Msk | + SC_CTL_RXRTYEN_Msk); + while((sc->CTL & SC_CTL_SYNC_Msk) == SC_CTL_SYNC_Msk) {} + /* Enable auto convention, and all three smartcard internal timers */ + sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk; + /* Disable Rx timeout */ + sc->RXTOUT = 0UL; + /* 372 clocks per ETU by default */ + sc->ETUCTL = 371UL; + + /* Enable necessary interrupt for smartcard operation */ + if(g_u32CardStateIgnore[u32Intf]) /* Do not enable card detect interrupt if card present state ignore */ + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_ACERRIEN_Msk); + } + else + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_ACERRIEN_Msk | + SC_INTEN_CDIEN_Msk); + } + + return; +} + +/** + * @brief Set Block Guard Time (BGT) + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32. + * + * @return None + * + * @details This function is used to configure block guard time (BGT) of specified smartcard module. + */ +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT) +{ + sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos); +} + +/** + * @brief Set Character Guard Time (CGT) + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267. + * + * @return None + * + * @details This function is used to configure character guard time (CGT) of specified smartcard module. + * @note Before using this API, user should set the correct stop bit length first. + */ +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT) +{ + /* CGT is "START bit" + "8-bits" + "Parity bit" + "STOP bit(s)" + "EGT counts" */ + u32CGT -= ((sc->CTL & SC_CTL_NSB_Msk) == SC_CTL_NSB_Msk)? 11UL : 12UL; + sc->EGT = u32CGT; +} + +/** + * @brief Stop all smartcard timer + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @note This function stop the timers within specified smartcard module, \b not timer module. + */ +void SC_StopAllTimer(SC_T *sc) +{ + while((sc->ALTCTL & SC_ALTCTL_SYNC_Msk) == SC_ALTCTL_SYNC_Msk) {} + sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk); +} + +/** + * @brief Configure and start smartcard timer + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32TimerNum Timer to start. Valid values are 0, 1, 2. + * @param[in] u32Mode Timer operating mode, valid values are: + * - \ref SC_TMR_MODE_0 + * - \ref SC_TMR_MODE_1 + * - \ref SC_TMR_MODE_2 + * - \ref SC_TMR_MODE_3 + * - \ref SC_TMR_MODE_4 + * - \ref SC_TMR_MODE_5 + * - \ref SC_TMR_MODE_6 + * - \ref SC_TMR_MODE_7 + * - \ref SC_TMR_MODE_8 + * - \ref SC_TMR_MODE_F + * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1 ~ 0x1000000 ETUs. + * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs. + * + * @return None + * + * @note This function start the timer within specified smartcard module, \b not timer module. + * @note Depend on the timer operating mode, timer may not start counting immediately and starts when condition match. + */ +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount) +{ + uint32_t u32Reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL)); + while((sc->ALTCTL & SC_ALTCTL_SYNC_Msk) == SC_ALTCTL_SYNC_Msk) {} + if(u32TimerNum == 0UL) + { + while((sc->TMRCTL0 & SC_TMRCTL0_SYNC_Msk) == SC_TMRCTL0_SYNC_Msk) {} + sc->TMRCTL0 = u32Reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk; + } + else if(u32TimerNum == 1UL) + { + while((sc->TMRCTL1 & SC_TMRCTL1_SYNC_Msk) == SC_TMRCTL1_SYNC_Msk) {} + sc->TMRCTL1 = u32Reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + while((sc->TMRCTL2 & SC_TMRCTL2_SYNC_Msk) == SC_TMRCTL2_SYNC_Msk) {} + sc->TMRCTL2 = u32Reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief Stop a smartcard timer + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32TimerNum Timer to stop. Valid values are 0, 1, 2. + * + * @return None + * + * @note This function stop the timer within specified smartcard module, \b not timer module. + */ +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum) +{ + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) {} + + if(u32TimerNum == 0UL) /* timer 0 */ + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk; + } + else if(u32TimerNum == 1UL) /* timer 1 */ + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief Get smartcard clock frequency + * + * @param[in] sc The pointer of smartcard module. + * + * @return Smartcard frequency in kHZ + * + * @details This function is used to get specified smartcard module clock frequency in kHz. + */ +uint32_t SC_GetInterfaceClock(SC_T *sc) +{ + uint32_t u32ClkSrc = 0, u32Num = 0, u32ClkFreq = __HIRC, u32Div = 0; + + /* Get smartcard module clock source and divider */ + if((sc == SC0) || (sc == SC0_NS)) + { + u32Num = 0UL; + u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE); + u32Div = CLK_GetModuleClockDivider(SC0_MODULE); + } + else if((sc == SC1) || (sc == SC1_NS)) + { + u32Num = 1UL; + u32ClkSrc = CLK_GetModuleClockSource(SC1_MODULE); + u32Div = CLK_GetModuleClockDivider(SC1_MODULE); + } + else if((sc == SC2) || (sc == SC2_NS)) + { + u32Num = 2UL; + u32ClkSrc = CLK_GetModuleClockSource(SC2_MODULE); + u32Div = CLK_GetModuleClockDivider(SC2_MODULE); + } + else + { + u32ClkFreq = 0UL; + } + + if(u32ClkFreq != 0UL) + { + /* Get smartcard module clock */ + if(u32ClkSrc == 0UL) + { + u32ClkFreq = __HXT; + } + else if(u32ClkSrc == 1UL) + { + u32ClkFreq = CLK_GetPLLClockFreq(); + } + else if(u32ClkSrc == 2UL) + { + if(u32Num == 1UL) + { + u32ClkFreq = CLK_GetPCLK1Freq(); + } + else + { + u32ClkFreq = CLK_GetPCLK0Freq(); + } + } + else + { + u32ClkFreq = __HIRC; + } + + u32ClkFreq /= (u32Div + 1UL) * 1000UL; + } + + return u32ClkFreq; +} + +/**@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SC_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_scuart.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_scuart.c new file mode 100644 index 0000000000..a75ddc244b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_scuart.c @@ -0,0 +1,273 @@ +/**************************************************************************//** + * @file scuart.c + * @version V3.00 + * @brief Smartcard UART mode (SCUART) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/** + * @brief Disable smartcard interface + * + * @param sc The pointer of smartcard module. + * + * @return None + * + * @details The function is used to disable smartcard interface UART mode. + */ +void SCUART_Close(SC_T* sc) +{ + sc->INTEN = 0UL; + sc->UARTCTL = 0UL; + sc->CTL = 0UL; +} + +/** @cond HIDDEN_SYMBOLS */ +/** + * @brief Returns module clock of specified SC interface + * + * @param[in] sc The pointer of smartcard module. + * + * @return Module clock of specified SC interface. + */ +static uint32_t SCUART_GetClock(SC_T *sc) +{ + uint32_t u32ClkSrc = 0, u32Num = 0, u32ClkFreq = __HIRC, u32Div = 0; + + /* Get smartcard module clock source and divider */ + if((sc == SC0) || (sc == SC0_NS)) + { + u32Num = 0UL; + u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE); + u32Div = CLK_GetModuleClockDivider(SC0_MODULE); + } + else if((sc == SC1) || (sc == SC1_NS)) + { + u32Num = 1UL; + u32ClkSrc = CLK_GetModuleClockSource(SC1_MODULE); + u32Div = CLK_GetModuleClockDivider(SC1_MODULE); + } + else if((sc == SC2) || (sc == SC2_NS)) + { + u32Num = 2UL; + u32ClkSrc = CLK_GetModuleClockSource(SC2_MODULE); + u32Div = CLK_GetModuleClockDivider(SC2_MODULE); + } + else + { + u32ClkFreq = 0UL; + } + + if(u32ClkFreq != 0UL) + { + /* Get smartcard module clock */ + if(u32ClkSrc == 0UL) + { + u32ClkFreq = __HXT; + } + else if(u32ClkSrc == 1UL) + { + u32ClkFreq = CLK_GetPLLClockFreq(); + } + else if(u32ClkSrc == 2UL) + { + if(u32Num == 1UL) + { + u32ClkFreq = CLK_GetPCLK1Freq(); + } + else + { + u32ClkFreq = CLK_GetPCLK0Freq(); + } + } + else + { + u32ClkFreq = __HIRC; + } + + u32ClkFreq /= (u32Div + 1UL); + } + + return u32ClkFreq; +} +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Enable smartcard module UART mode and set baudrate + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Baudrate Target baudrate of smartcard UART module. + * + * @return Actual baudrate of smartcard UART mode + * + * @details This function use to enable smartcard module UART mode and set baudrate. + * + * @note This function configures character width to 8 bits, 1 stop bit, and no parity. + * And can use \ref SCUART_SetLineConfig function to update these settings. + * The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_Open(SC_T* sc, uint32_t u32Baudrate) +{ + uint32_t u32ClkFreq = SCUART_GetClock(sc), u32Div; + + /* Calculate divider for target baudrate */ + u32Div = (u32ClkFreq + (u32Baudrate >> 1) - 1UL) / u32Baudrate - 1UL; + + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk; /* Enable smartcard interface and stop bit = 1 */ + sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; /* Enable UART mode, disable parity and 8 bit per character */ + sc->ETUCTL = u32Div; + + return (u32ClkFreq / (u32Div + 1UL)); +} + +/** + * @brief Read Rx data from Rx FIFO + * + * @param[in] sc The pointer of smartcard module. + * @param[in] pu8RxBuf The buffer to store receive the data. + * @param[in] u32ReadBytes Target number of characters to receive + * + * @return Actual character number reads to buffer + * + * @details The function is used to read data from Rx FIFO. + * + * @note This function does not block and return immediately if there's no data available. + */ +uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count; + + for(u32Count = 0UL; u32Count < u32ReadBytes; u32Count++) + { + if(SCUART_GET_RX_EMPTY(sc) == SC_STATUS_RXEMPTY_Msk) + { + /* No data available */ + break; + } + /* Get data from FIFO */ + pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc); + } + + return u32Count; +} + +/** + * @brief Configure smartcard UART mode line setting + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Baudrate Target baudrate of smartcard UART mode. If this value is 0, SC UART baudrate will not change. + * @param[in] u32DataWidth The data length, could be: + * - \ref SCUART_CHAR_LEN_5 + * - \ref SCUART_CHAR_LEN_6 + * - \ref SCUART_CHAR_LEN_7 + * - \ref SCUART_CHAR_LEN_8 + * @param[in] u32Parity The parity setting, could be: + * - \ref SCUART_PARITY_NONE + * - \ref SCUART_PARITY_ODD + * - \ref SCUART_PARITY_EVEN + * @param[in] u32StopBits The stop bit length, could be: + * - \ref SCUART_STOP_BIT_1 + * - \ref SCUART_STOP_BIT_2 + * + * @return Actual baudrate of smartcard UART mode + * + * @details The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits) +{ + uint32_t u32ClkFreq = SCUART_GetClock(sc), u32Div; + + if(u32Baudrate == 0UL) + { + /* Keep original baudrate setting */ + u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk; + } + else + { + /* Calculate divider for target baudrate */ + u32Div = ((u32ClkFreq + (u32Baudrate >> 1) - 1UL) / u32Baudrate) - 1UL; + sc->ETUCTL = u32Div; + } + + sc->CTL = u32StopBits | SC_CTL_SCEN_Msk; /* Set stop bit */ + sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk; /* Set character width and parity */ + + return (u32ClkFreq / (u32Div + 1UL)); +} + +/** + * @brief Set receive timeout count + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32TOC Rx time-out counter, using baudrate as counter unit. Valid range are 0~0x1FF, + * set this value to 0 will disable time-out counter. + * + * @return None + * + * @details The time-out counter resets and starts counting whenever the Rx buffer received a + * new data word. Once the counter decrease to 1 and no new data is received or CPU + * does not read any data from FIFO, a receiver time-out interrupt will be generated. + */ +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC) +{ + sc->RXTOUT = u32TOC; +} + +/** + * @brief Write data into transmit FIFO to send data out + * + * @param[in] sc The pointer of smartcard module. + * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO. + * @param[in] u32WriteBytes Number of data to send. + * + * @return None + * + * @details This function is used to write data into Tx FIFO to send data out. + * + * @note This function blocks until all data write into FIFO. + */ +void SCUART_Write(SC_T* sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count; + + for(u32Count = 0UL; u32Count != u32WriteBytes; u32Count++) + { + /* Wait 'til FIFO not full */ + while(SCUART_GET_TX_FULL(sc) == SC_STATUS_TXFULL_Msk) {} + + /* Write 1 byte to FIFO */ + sc->DAT = pu8TxBuf[u32Count]; /* Write 1 byte to FIFO */ + } +} + + +/**@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SCUART_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_sdh.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_sdh.c new file mode 100644 index 0000000000..e13edde378 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_sdh.c @@ -0,0 +1,1140 @@ +/**************************************************************************//** + * @file sdh.c + * @version V1.00 + * @brief M2354 SDH driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include +#include +#include "NuMicro.h" + +#if defined (__ICCARM__) +# pragma diag_suppress=Pm073, Pm143 /* Misra C 2004 rule 14.7 */ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ + +#define SDH_BLOCK_SIZE 512UL + +/* #define DEBUG_PRINTF printf */ +#define DEBUG_PRINTF(...) + +/** @cond HIDDEN_SYMBOLS */ + +/* global variables */ +/* For response R3 (such as ACMD41, CRC-7 is invalid; but SD controller will still */ +/* calculate CRC-7 and get an error result, software should ignore this error and clear SDISR [CRC_IF] flag */ +/* _sd_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error */ +uint8_t g_u8R3Flag = 0UL; +uint8_t volatile g_u8SDDataReadyFlag = (uint8_t)FALSE; + +static uint32_t _SDH_uR7_CMD = 0UL; +static uint32_t _SDH_ReferenceClock; + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment = 4 +static uint8_t _SDH_ucSDHCBuffer[512]; +#else +static __attribute__((aligned)) uint8_t _SDH_ucSDHCBuffer[512]; +#endif + +/* Declare these functions here to avoid MISRA C 2004 rule 8.1 error */ +void SDH_CheckRB(SDH_T *sdh); +uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg); +uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t u32TickCount); +uint32_t SDH_Swap32(uint32_t u32Val); +uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t pu32R2ptr[]); +uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg); +void SDH_Set_clock(SDH_T *sdh, uint32_t u32SDClockKhz); +uint32_t SDH_CardDetection(SDH_T *sdh); +uint32_t SDH_Init(SDH_T *sdh); +uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD); +uint32_t SDH_SelectCardType(SDH_T *sdh); +void SDH_Get_SD_info(SDH_T *sdh); + +SDH_INFO_T SD0; + +void SDH_CheckRB(SDH_T *sdh) +{ + while(1) + { + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {} + if(sdh->INTSTS & SDH_INTSTS_DAT0STS_Msk) + { + break; + } + } +} + + +uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg) +{ + SDH_INFO_T *pSD; + volatile uint32_t u32Status = Successful; + + /* M2354 is only support SDH0 */ + pSD = &SD0; + + sdh->CMDARG = u32Arg; + sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (u32Cmd << 8) | (SDH_CTL_COEN_Msk); + + while(sdh->CTL & SDH_CTL_COEN_Msk) + { + if(pSD->IsCardInsert == (uint32_t)FALSE) + { + u32Status = SDH_NO_SD_CARD; + } + } + return u32Status; +} + + +uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t u32TickCount) +{ + SDH_INFO_T *pSD; + + /* M2354 is only support SDH0 */ + pSD = &SD0; + + sdh->CMDARG = u32Arg; + sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (u32Cmd << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk); + + if(u32TickCount > 0UL) + { + while(sdh->CTL & SDH_CTL_RIEN_Msk) + { + if(u32TickCount-- == 0UL) + { + sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */ + return 2UL; + } + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + } + else + { + while(sdh->CTL & SDH_CTL_RIEN_Msk) + { + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + } + + if(_SDH_uR7_CMD) + { + if((sdh->RESP1 & 0xffUL) != 0x55UL) + { + if((sdh->RESP0 & 0xfUL) != 0x01UL) + { + _SDH_uR7_CMD = 0UL; + return SDH_CMD8_ERROR; + } + } + } + + if(!g_u8R3Flag) + { + if(sdh->INTSTS & SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return Successful; + } + else + { + return SDH_CRC7_ERROR; + } + } + else /* ignore CRC error for R3 case */ + { + g_u8R3Flag = 0UL; + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return Successful; + } +} + + +uint32_t SDH_Swap32(uint32_t u32Val) +{ + uint32_t u32Buf; + + u32Buf = u32Val; + u32Val <<= 24; + u32Val |= (u32Buf << 8) & 0xff0000UL; + u32Val |= (u32Buf >> 8) & 0xff00UL; + u32Val |= (u32Buf >> 24) & 0xffUL; + return u32Val; +} + +/* Get 16 bytes CID or CSD */ +uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t pu32R2ptr[]) +{ + uint32_t i; + uint32_t au32TmpBuf[5]; + SDH_INFO_T *pSD; + + /* M2354 is only support SDH0 */ + pSD = &SD0; + + sdh->CMDARG = u32Arg; + sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (u32Cmd << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_R2EN_Msk); + + while(sdh->CTL & SDH_CTL_R2EN_Msk) + { + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if(sdh->INTSTS & SDH_INTSTS_CRC7_Msk) + { + for(i = 0UL; i < 5UL; i++) + { + au32TmpBuf[i] = SDH_Swap32(sdh->FB[i]); + } + for(i = 0UL; i < 4UL; i++) + { + pu32R2ptr[i] = ((au32TmpBuf[i] & 0x00ffffffUL) << 8) | ((au32TmpBuf[i + 1UL] & 0xff000000UL) >> 24); + } + return Successful; + } + else + { + return SDH_CRC7_ERROR; + } +} + + +uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg) +{ + SDH_INFO_T *pSD; + + /* M2354 is only support SDH0 */ + pSD = &SD0; + + sdh->CMDARG = u32Arg; + sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | ((uint32_t)u32Cmd << 8) | + (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + + while(sdh->CTL & SDH_CTL_RIEN_Msk) + { + if(pSD->IsCardInsert == (uint32_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + while(sdh->CTL & SDH_CTL_DIEN_Msk) + { + if(pSD->IsCardInsert == (uint32_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if(!(sdh->INTSTS & SDH_INTSTS_CRC7_Msk)) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if(!(sdh->INTSTS & SDH_INTSTS_CRC16_Msk)) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + + return Successful; +} + +/* there are 8 bits for divider0, maximum is 256 */ +#define SDH_CLK_DIV0_MAX 256UL + +void SDH_Set_clock(SDH_T *sdh, uint32_t u32SDClockKhz) +{ + (void)sdh; + if(!(__PC() & (1UL << 28))) + { + uint32_t u32Rate, u32Div1; + static uint32_t u32SDClkSrc = 0UL; + + /* M2354 is only support SDH0 */ + u32SDClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH0SEL_Msk); + if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_HXT) + { + _SDH_ReferenceClock = (CLK_GetHXTFreq() / 1000UL); + } + else if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_HIRC) + { + _SDH_ReferenceClock = (__HIRC / 1000UL); + } + else if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_PLL) + { + _SDH_ReferenceClock = (CLK_GetPLLClockFreq() / 1000UL); + } + else if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_HCLK) + { + _SDH_ReferenceClock = (CLK_GetHCLKFreq() / 1000UL); + } + + if(u32SDClockKhz >= 50000UL) + { + u32SDClockKhz = 50000UL; + } + u32Rate = _SDH_ReferenceClock / u32SDClockKhz; + + /* choose slower clock if system clock cannot divisible by wanted clock */ + if(_SDH_ReferenceClock % u32SDClockKhz != 0UL) + { + u32Rate++; + } + + if(u32Rate >= SDH_CLK_DIV0_MAX) + { + u32Rate = SDH_CLK_DIV0_MAX; + } + + /* --- calculate the second divider CLKDIV0[SDHOST_N] */ + if(u32Rate == 0UL) + { + u32Div1 = 0UL; + } + else + { + u32Div1 = ((u32Rate - 1UL) & 0xFFUL); + } + + /* --- setup register */ + /* M2354 is only support SDH0 */ + CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk; + CLK->CLKDIV0 |= (u32Div1 << CLK_CLKDIV0_SDH0DIV_Pos); + } +} + +uint32_t SDH_CardDetection(SDH_T *sdh) +{ + uint32_t i, u32Status = (uint32_t)TRUE; + SDH_INFO_T *pSD; + + /* M2354 is only support SDH0 */ + pSD = &SD0; + + if(sdh->INTEN & SDH_INTEN_CDSRC_Msk) /* Card detect pin from GPIO */ + { + if(sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) /* Card remove */ + { + pSD->IsCardInsert = (uint8_t)FALSE; + u32Status = (uint32_t)FALSE; + } + else + { + pSD->IsCardInsert = (uint8_t)TRUE; + } + } + else if(!(sdh->INTEN & SDH_INTEN_CDSRC_Msk)) + { + sdh->CTL |= SDH_CTL_CLKKEEP_Msk; + for(i = 0UL; i < 5000UL; i++) {} + + if(sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) /* Card insert */ + { + pSD->IsCardInsert = (uint8_t)TRUE; + } + else + { + pSD->IsCardInsert = (uint8_t)FALSE; + u32Status = (uint32_t)FALSE; + } + + sdh->CTL &= ~SDH_CTL_CLKKEEP_Msk; + } + + return u32Status; +} + + +/* Initial */ +uint32_t SDH_Init(SDH_T *sdh) +{ + uint32_t volatile i, u32Status; + uint32_t u32Resp; + uint32_t au32CIDBuffer[4]; + uint32_t volatile u32CmdTimeOut; + SDH_INFO_T *pSD; + + /* M2354 is only support SDH0 */ + pSD = &SD0; + + /* set the clock to 300KHz */ + SDH_Set_clock(sdh, 300UL); + + /* power ON 74 clock */ + sdh->CTL |= SDH_CTL_CLK74OEN_Msk; + + while(sdh->CTL & SDH_CTL_CLK74OEN_Msk) + { + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + SDH_SDCommand(sdh, 0UL, 0UL); /* reset all cards */ + for(i = 0x1000UL; i > 0UL; i--) {} + + /* initial SDHC */ + _SDH_uR7_CMD = 1UL; + u32CmdTimeOut = 0xFFFFFUL; + + i = SDH_SDCmdAndRsp(sdh, 8UL, 0x00000155UL, u32CmdTimeOut); + if(i == Successful) + { + /* SD 2.0 */ + SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut); + g_u8R3Flag = 1UL; + SDH_SDCmdAndRsp(sdh, 41UL, 0x40ff8000UL, u32CmdTimeOut); /* 2.7v-3.6v */ + u32Resp = sdh->RESP0; + + while(!(u32Resp & 0x00800000UL)) /* check if card is ready */ + { + SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut); + g_u8R3Flag = 1UL; + SDH_SDCmdAndRsp(sdh, 41UL, 0x40ff8000UL, u32CmdTimeOut); /* 3.0v-3.4v */ + u32Resp = sdh->RESP0; + } + if(u32Resp & 0x00400000UL) + { + pSD->CardType = SDH_TYPE_SD_HIGH; + } + else + { + pSD->CardType = SDH_TYPE_SD_LOW; + } + } + else + { + /* SD 1.1 */ + SDH_SDCommand(sdh, 0UL, 0UL); /* reset all cards */ + for(i = 0x100UL; i > 0UL; i--) {} + + i = SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut); + if(i == 2UL) /* MMC memory */ + { + SDH_SDCommand(sdh, 0UL, 0UL); /* reset */ + for(i = 0x100UL; i > 0UL; i--) {} + + g_u8R3Flag = 1UL; + + if(SDH_SDCmdAndRsp(sdh, 1UL, 0x40ff8000UL, u32CmdTimeOut) != 2UL) /* eMMC memory */ + { + u32Resp = sdh->RESP0; + while(!(u32Resp & 0x00800000UL)) /* check if card is ready */ + { + g_u8R3Flag = 1UL; + + SDH_SDCmdAndRsp(sdh, 1UL, 0x40ff8000UL, u32CmdTimeOut); /* high voltage */ + u32Resp = sdh->RESP0; + } + + if(u32Resp & 0x00400000UL) + { + pSD->CardType = SDH_TYPE_EMMC; + } + else + { + pSD->CardType = SDH_TYPE_MMC; + } + } + else + { + pSD->CardType = SDH_TYPE_UNKNOWN; + return SDH_ERR_DEVICE; + } + } + else if(i == 0UL) /* SD Memory */ + { + g_u8R3Flag = 1UL; + SDH_SDCmdAndRsp(sdh, 41UL, 0x00ff8000UL, u32CmdTimeOut); /* 3.0v-3.4v */ + u32Resp = sdh->RESP0; + while(!(u32Resp & 0x00800000UL)) /* check if card is ready */ + { + SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut); + g_u8R3Flag = 1UL; + SDH_SDCmdAndRsp(sdh, 41UL, 0x00ff8000UL, u32CmdTimeOut); /* 3.0v-3.4v */ + u32Resp = sdh->RESP0; + } + pSD->CardType = SDH_TYPE_SD_LOW; + } + else + { + pSD->CardType = SDH_TYPE_UNKNOWN; + return SDH_INIT_ERROR; + } + } + + /* CMD2, CMD3 */ + if(pSD->CardType != SDH_TYPE_UNKNOWN) + { + SDH_SDCmdAndRsp2(sdh, 2UL, 0x00UL, au32CIDBuffer); + if((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + if((u32Status = SDH_SDCmdAndRsp(sdh, 3UL, 0x10000UL, 0UL)) != Successful) /* set RCA */ + { + return u32Status; + } + pSD->RCA = 0x10000UL; + } + else + { + if((u32Status = SDH_SDCmdAndRsp(sdh, 3UL, 0x00UL, 0UL)) != Successful) /* get RCA */ + { + return u32Status; + } + else + { + pSD->RCA = (sdh->RESP0 << 8) & 0xffff0000UL; + } + } + } + + return Successful; +} + + +uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD) +{ + uint32_t volatile u32Status = 0UL; + uint16_t u16CurrentComsumption, u16BusyStatus0; + + (void)pSD; + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; /* set DMA transfer starting address */ + sdh->BLEN = 63UL; /* 512 bit */ + + if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 6UL, 0x00ffff01UL)) != Successful) + { + return Fail; + } + + u16CurrentComsumption = (uint16_t)(_SDH_ucSDHCBuffer[0] << 8); + u16CurrentComsumption |= (uint16_t)_SDH_ucSDHCBuffer[1]; + if(!u16CurrentComsumption) + { + return Fail; + } + + u16BusyStatus0 = (uint16_t)(_SDH_ucSDHCBuffer[28] << 8); + u16BusyStatus0 |= (uint16_t)_SDH_ucSDHCBuffer[29]; + + if(!u16BusyStatus0) /* function ready */ + { + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; /* set DMA transfer starting address */ + sdh->BLEN = 63UL; /* 512 bit */ + + if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 6UL, 0x80ffff01UL)) != Successful) + { + return Fail; + } + + /* function change timing: 8 clocks */ + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {} + + u16CurrentComsumption = (uint16_t)(_SDH_ucSDHCBuffer[0] << 8); + u16CurrentComsumption |= (uint16_t)_SDH_ucSDHCBuffer[1]; + if(!u16CurrentComsumption) + { + return Fail; + } + + return Successful; + } + else + { + return Fail; + } +} + + +uint32_t SDH_SelectCardType(SDH_T *sdh) +{ + uint32_t volatile u32Status = 0UL; + uint32_t u32Param; + SDH_INFO_T *pSD; + + /* M2354 is only support SDH0 */ + pSD = &SD0; + + if((u32Status = SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + + SDH_CheckRB(sdh); + + /* if SD card set 4bit */ + if(pSD->CardType == SDH_TYPE_SD_HIGH) + { + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; /* set DMA transfer starting address */ + sdh->BLEN = 0x07UL; /* 64 bit */ + + if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + + sdh->DMACTL |= 0x2; + while(sdh->DMACTL & 0x2) {} + + if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 51UL, 0x00UL)) != Successful) + { + return u32Status; + } + + if((_SDH_ucSDHCBuffer[0] & 0xfUL) == 0xfUL) + { + u32Status = SDH_SwitchToHighSpeed(sdh, pSD); + if(u32Status == Successful) + { + /* divider */ + SDH_Set_clock(sdh, SDHC_FREQ); + } + } + + if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + if((u32Status = SDH_SDCmdAndRsp(sdh, 6UL, 0x02UL, 0UL)) != Successful) /* set bus width */ + { + return u32Status; + } + + sdh->CTL |= SDH_CTL_DBW_Msk; + } + else if(pSD->CardType == SDH_TYPE_SD_LOW) + { + sdh->DMASA = (uint32_t) _SDH_ucSDHCBuffer; /* set DMA transfer starting address */ + sdh->BLEN = 0x07UL; /* 64 bit */ + + if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 51UL, 0x00UL)) != Successful) + { + return u32Status; + } + + /* set data bus width. ACMD6 for SD card, SDCR_DBW for host. */ + if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + + if((u32Status = SDH_SDCmdAndRsp(sdh, 6UL, 0x02UL, 0UL)) != Successful) /* set bus width */ + { + return u32Status; + } + + sdh->CTL |= SDH_CTL_DBW_Msk; + } + else if((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + + if(pSD->CardType == SDH_TYPE_MMC) + { + sdh->CTL &= ~SDH_CTL_DBW_Msk; + } + + /* --- sent CMD6 to MMC card to set bus width to 4 bits mode */ + /* set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode) */ + u32Param = (3UL << 24) | (183UL << 16) | (1UL << 8); + if((u32Status = SDH_SDCmdAndRsp(sdh, 6UL, u32Param, 0UL)) != Successful) + { + return u32Status; + } + SDH_CheckRB(sdh); + + sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */ + } + + if((u32Status = SDH_SDCmdAndRsp(sdh, 16UL, SDH_BLOCK_SIZE, 0UL)) != Successful) /* set block length */ + { + return u32Status; + } + sdh->BLEN = SDH_BLOCK_SIZE - 1UL; /* set the block size */ + + SDH_SDCommand(sdh, 7UL, 0UL); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {} + + sdh->INTEN |= SDH_INTEN_BLKDIEN_Msk; + + return Successful; +} + +void SDH_Get_SD_info(SDH_T *sdh) +{ + uint32_t u32RLen, u32CSize, u32Mult, u32Size; + uint32_t au32Buffer[4]; + SDH_INFO_T *pSD; + + /* M2354 is only support SDH0 */ + pSD = &SD0; + + SDH_SDCmdAndRsp2(sdh, 9UL, pSD->RCA, au32Buffer); + + if((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + /* for MMC/eMMC card */ + if((au32Buffer[0] & 0xc0000000UL) == 0xc0000000UL) + { + /* CSD_STRUCTURE [127:126] is 3 */ + /* CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB */ + SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL); + + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; /* set DMA transfer starting address */ + sdh->BLEN = 511UL; /* read 512 bytes for EXT_CSD */ + + if(SDH_SDCmdAndRspDataIn(sdh, 8UL, 0x00UL) != Successful) + { + return; + } + + SDH_SDCommand(sdh, 7UL, 0UL); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {} + + pSD->totalSectorN = (uint32_t)_SDH_ucSDHCBuffer[215] << 24; + pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[214] << 16; + pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[213] << 8; + pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[212]; + pSD->diskSize = pSD->totalSectorN / 2UL; + } + else + { + /* CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB */ + u32RLen = (au32Buffer[1] & 0x000f0000UL) >> 16; + u32CSize = ((au32Buffer[1] & 0x000003ffUL) << 2) | ((au32Buffer[2] & 0xc0000000UL) >> 30); + u32Mult = (au32Buffer[2] & 0x00038000UL) >> 15; + u32Size = (u32CSize + 1UL) * (1UL << (u32Mult + 2UL)) * (1UL << u32RLen); + + pSD->diskSize = u32Size / 1024UL; + pSD->totalSectorN = u32Size / 512UL; + } + } + else + { + if(au32Buffer[0] & 0xc0000000UL) + { + u32CSize = ((au32Buffer[1] & 0x0000003fUL) << 16) | ((au32Buffer[2] & 0xffff0000UL) >> 16); + u32Size = (u32CSize + 1UL) * 512UL; /* Kbytes */ + + pSD->diskSize = u32Size; + pSD->totalSectorN = u32Size << 1; + } + else + { + u32RLen = (au32Buffer[1] & 0x000f0000UL) >> 16; + u32CSize = ((au32Buffer[1] & 0x000003ffUL) << 2) | ((au32Buffer[2] & 0xc0000000UL) >> 30); + u32Mult = (au32Buffer[2] & 0x00038000UL) >> 15; + u32Size = (u32CSize + 1UL) * (1UL << (u32Mult + 2UL)) * (1UL << u32RLen); + + pSD->diskSize = u32Size / 1024UL; + pSD->totalSectorN = u32Size / 512UL; + } + } + pSD->sectorSize = (int)512UL; +} + +/** @endcond HIDDEN_SYMBOLS */ + + +/** + * @brief This function use to reset SD function and select card detection source and pin. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32CardDetSrc Select card detection pin from GPIO or DAT3 pin. ( \ref CardDetect_From_GPIO / \ref CardDetect_From_DAT3) + * + * @return None + */ +void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc) +{ + /* enable DMAC */ + sdh->DMACTL = SDH_DMACTL_DMARST_Msk; + while(sdh->DMACTL & SDH_DMACTL_DMARST_Msk) {} + + sdh->DMACTL = SDH_DMACTL_DMAEN_Msk; + + /* Reset FMI */ + sdh->GCTL = SDH_GCTL_GCTLRST_Msk | SDH_GCTL_SDEN_Msk; /* Start reset FMI controller. */ + while(sdh->GCTL & SDH_GCTL_GCTLRST_Msk) {} + + memset(&SD0, 0, sizeof(SDH_INFO_T)); + + /* enable SD */ + sdh->GCTL = SDH_GCTL_SDEN_Msk; + + if(u32CardDetSrc & CardDetect_From_DAT3) + { + sdh->INTEN &= ~SDH_INTEN_CDSRC_Msk; + } + else + { + sdh->INTEN |= SDH_INTEN_CDSRC_Msk; + } + sdh->INTEN |= SDH_INTEN_CDIEN_Msk; + + sdh->CTL |= SDH_CTL_CTLRST_Msk; /* SD software reset */ + while(sdh->CTL & SDH_CTL_CTLRST_Msk) {} + +} + +/** + * @brief This function use to initial SD card. + * + * @param[in] sdh The pointer of the specified SDH module. + * + * @return None + * + * @details This function is used to initial SD card. + * SD initial state needs 400KHz clock output, driver will use HIRC for SD initial clock source. + * And then switch back to the user's setting. + */ +uint32_t SDH_Probe(SDH_T *sdh) +{ + uint32_t u32Val; + + /* Disable FMI/SD host interrupt */ + sdh->GINTEN = 0UL; + + sdh->CTL &= ~SDH_CTL_SDNWR_Msk; + sdh->CTL |= 0x09UL << SDH_CTL_SDNWR_Pos; /* set SDNWR = 9 */ + sdh->CTL &= ~SDH_CTL_BLKCNT_Msk; + sdh->CTL |= 0x01UL << SDH_CTL_BLKCNT_Pos; /* set BLKCNT = 1 */ + sdh->CTL &= ~SDH_CTL_DBW_Msk; /* SD 1-bit data bus */ + + if(!(SDH_CardDetection(sdh))) + { + return SDH_NO_SD_CARD; + } + + if((u32Val = SDH_Init(sdh)) != 0UL) + { + return u32Val; + } + + /* divider */ + if(SD0.CardType == SDH_TYPE_MMC) + { + SDH_Set_clock(sdh, MMC_FREQ); + } + else + { + SDH_Set_clock(sdh, SD_FREQ); + } + SDH_Get_SD_info(sdh); + + if((u32Val = SDH_SelectCardType(sdh)) != 0UL) + { + return u32Val; + } + + return 0UL; +} + +/** + * @brief This function use to read data from SD card. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[out] pu8BufAddr The buffer to receive the data from SD card. + * @param[in] u32StartSec The start read sector address. + * @param[in] u32SecCount The the read sector number of data + * + * @return None + */ +uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount) +{ + uint32_t volatile u32IsSendCmd = (uint32_t)FALSE; + uint32_t volatile u32Reg; + uint32_t volatile u32Loop, u32Status; + uint32_t u32BlkSize = SDH_BLOCK_SIZE; + + SDH_INFO_T *pSD; + + /* M2354 is only support SDH0 */ + pSD = &SD0; + + /* --- check input parameters */ + if(u32SecCount == 0UL) + { + return SDH_SELECT_ERROR; + } + + if((u32Status = SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + SDH_CheckRB(sdh); + + sdh->BLEN = u32BlkSize - 1UL; /* the actual byte count is equal to (SDBLEN+1) */ + + if((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC)) + { + sdh->CMDARG = u32StartSec; + } + else + { + sdh->CMDARG = u32StartSec * u32BlkSize; + } + + sdh->DMASA = (uint32_t)pu8BufAddr; + + u32Loop = u32SecCount / 255UL; + while(u32Loop > 0UL) + { + g_u8SDDataReadyFlag = (uint8_t)FALSE; + u32Reg = sdh->CTL & ~SDH_CTL_CMDCODE_Msk; + u32Reg = u32Reg | 0xff0000UL; /* set BLK_CNT to 255 */ + if(u32IsSendCmd == (uint32_t)FALSE) + { + sdh->CTL = u32Reg | (18UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + u32IsSendCmd = (uint32_t)TRUE; + } + else + { + sdh->CTL = u32Reg | SDH_CTL_DIEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if(g_u8SDDataReadyFlag) + { + break; + } + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if(!(sdh->INTSTS & SDH_INTSTS_CRC7_Msk)) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if(!(sdh->INTSTS & SDH_INTSTS_CRC16_Msk)) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + u32Loop--; + } + + u32Loop = u32SecCount % 255UL; + if(u32Loop != 0UL) + { + uint32_t u32RegTmp; + g_u8SDDataReadyFlag = (uint8_t)FALSE; + u32Reg = sdh->CTL & (~SDH_CTL_CMDCODE_Msk); + u32Reg = u32Reg & (~SDH_CTL_BLKCNT_Msk); + u32RegTmp = (u32Loop << 16); + u32Reg |= u32RegTmp; /* setup SDCR_BLKCNT */ + + if(u32IsSendCmd == (uint32_t)FALSE) + { + sdh->CTL = u32Reg | (18UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + u32IsSendCmd = (uint32_t)TRUE; + } + else + { + sdh->CTL = u32Reg | SDH_CTL_DIEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if(!(sdh->INTSTS & SDH_INTSTS_CRC7_Msk)) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if(!(sdh->INTSTS & SDH_INTSTS_CRC16_Msk)) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + } + + if(SDH_SDCmdAndRsp(sdh, 12UL, 0UL, 0UL)) /* stop command */ + { + return SDH_CRC7_ERROR; + } + SDH_CheckRB(sdh); + + SDH_SDCommand(sdh, 7UL, 0UL); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {} + + return Successful; +} + +/** + * @brief This function use to write data to SD card. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] pu8BufAddr The buffer to send the data to SD card. + * @param[in] u32StartSec The start write sector address. + * @param[in] u32SecCount The the write sector number of data. + * + * @return \ref SDH_SELECT_ERROR : u32SecCount is zero. \n + * \ref SDH_NO_SD_CARD : SD card be removed. \n + * \ref SDH_CRC_ERROR : CRC error happen. \n + * \ref SDH_CRC7_ERROR : CRC7 error happen. \n + * \ref Successful : Write data to SD card success. + */ +uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount) +{ + uint32_t volatile u32IsSendCmd = (uint32_t)FALSE; + uint32_t volatile u32Reg; + uint32_t volatile u32Loop, u32Status; + + SDH_INFO_T *pSD; + + /* M2354 is only support SDH0 */ + pSD = &SD0; + + /* --- check input parameters */ + if(u32SecCount == 0UL) + { + return SDH_SELECT_ERROR; + } + + if((u32Status = SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + + SDH_CheckRB(sdh); + + /* According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n. */ + sdh->BLEN = SDH_BLOCK_SIZE - 1UL; /* set the block size */ + + if((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC)) + { + sdh->CMDARG = u32StartSec; + } + else + { + sdh->CMDARG = u32StartSec * SDH_BLOCK_SIZE; /* set start address for SD CMD */ + } + + sdh->DMASA = (uint32_t)pu8BufAddr; + u32Loop = u32SecCount / 255UL; /* the maximum block count is 0xFF=255 for register SDCR[BLK_CNT] */ + while(u32Loop > 0UL) + { + g_u8SDDataReadyFlag = (uint8_t)FALSE; + u32Reg = sdh->CTL & 0xff00c080UL; + u32Reg = u32Reg | 0xff0000UL; /* set BLK_CNT to 0xFF=255 */ + if(!u32IsSendCmd) + { + sdh->CTL = u32Reg | (25UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk); + u32IsSendCmd = (uint32_t)TRUE; + } + else + { + sdh->CTL = u32Reg | SDH_CTL_DOEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0UL) /* check CRC */ + { + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return SDH_CRC_ERROR; + } + u32Loop--; + } + + u32Loop = u32SecCount % 255UL; + if(u32Loop != 0UL) + { + uint32_t u32RegTmp; + g_u8SDDataReadyFlag = (uint8_t)FALSE; + u32RegTmp = (u32Loop << 16); + u32Reg = (sdh->CTL & 0xff00c080UL) | u32RegTmp; + if(!u32IsSendCmd) + { + sdh->CTL = u32Reg | (25UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk); + u32IsSendCmd = (uint32_t)TRUE; + } + else + { + sdh->CTL = u32Reg | SDH_CTL_DOEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0UL) /* check CRC */ + { + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return SDH_CRC_ERROR; + } + } + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + + if(SDH_SDCmdAndRsp(sdh, 12UL, 0UL, 0UL)) /* stop command */ + { + return SDH_CRC7_ERROR; + } + SDH_CheckRB(sdh); + + SDH_SDCommand(sdh, 7UL, 0UL); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {} + + return Successful; +} + + +/**@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SDH_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_spi.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_spi.c new file mode 100644 index 0000000000..8c687a7347 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_spi.c @@ -0,0 +1,1651 @@ +/**************************************************************************//** + * @file spi.c + * @version V3.00 + * @brief M2354 series SPI driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + + +/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ + +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s); + +/** + * @brief This function make SPI module be ready to transfer. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER) + * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a SPI transaction. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI peripheral clock. + * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0. + * The actual clock rate may be different from the target SPI clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the + * actual SPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency for Secure, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of + * SPI bus clock cannot be faster than the system clock rate. User should set up carefully. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode for Secure, the SPI peripheral clock rate will equal to APB clock rate. + * @note In slave mode for Non-Secure, the SPI peripheral clock rate will equal to the clock rate set in secure mode. + */ +uint32_t SPI_Open(SPI_T *spi, + uint32_t u32MasterSlave, + uint32_t u32SPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0UL, u32Div, u32HCLKFreq, u32PCLK0Freq, u32PCLK1Freq, u32RetValue = 0UL; + + /* Disable I2S mode */ + spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; + + if(u32DataWidth == 32UL) + { + u32DataWidth = 0UL; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + /* Get APB0 clock frequency */ + u32PCLK0Freq = CLK_GetPCLK0Freq(); + /* Get APB1 clock frequency */ + u32PCLK1Freq = CLK_GetPCLK1Freq(); + + if(u32MasterSlave == SPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + if(u32BusClock >= u32HCLKFreq) + { + if(!(__PC() & NS_OFFSET)) + { + /* Select PCLK as the clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + } + else + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + } + } + } + + /* Check clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0UL) + { + /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + if(u32Div > 0x1FFUL) + { + u32Div = 0x1FFUL; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1UL)); + } + } + } + else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + + if(!(__PC() & NS_OFFSET)) + { + /* Select PCLK as the clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK1Freq; + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK0Freq; + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK1Freq; + } + else + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK0Freq; + } + } + else + { + /* Check clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32RetValue = u32PCLK1Freq; /* Clock source is PCLK1 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32RetValue = u32PCLK0Freq; /* Clock source is PCLK0 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32RetValue = u32PCLK1Freq; /* Clock source is PCLK1 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + u32RetValue = u32PCLK0Freq; /* Clock source is PCLK0 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + } + } + + return u32RetValue; +} + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details Clear SPIEN bit of SPI_CTL register to disable SPI transfer control. + */ +void SPI_Close(SPI_T *spi) +{ + spi->CTL &= ~SPI_CTL_SPIEN_Msk; +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1. + */ +void SPI_ClearRxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void SPI_ClearTxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void SPI_DisableAutoSS(SPI_T *spi) +{ + spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the SPI bus clock. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the actual SPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency for Secure, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of + * SPI bus clock cannot be faster than the system clock rate. User should set up carefully. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32BusClock >= u32HCLKFreq) + { + if(!(__PC() & NS_OFFSET)) + { + /* Select PCLK as the clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + } + else + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + } + } + } + + /* Check clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0UL) + { + /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + if(u32Div > 0x1FFUL) + { + u32Div = 0x1FFUL; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1UL)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. If data width is 8 ~ 16 bits, it could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. If data width is 8 ~ 16 bits, it could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of SPI bus clock. Only available in Master mode. + * @param[in] spi The pointer of the specified SPI module. + * @return Actual SPI bus clock frequency in Hz. + * @details This function will calculate the actual SPI bus clock rate according to the SPIxSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t SPI_GetBusClock(SPI_T *spi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Get DIVIDER setting */ + u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + /* Return SPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1UL)); +} + +/** + * @brief Enable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL |= SPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL &= ~SPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get SPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32IntStatus; + uint32_t u32IntFlag = 0UL; + + u32IntStatus = spi->STATUS; + + /* Check unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) && (u32IntStatus & SPI_STATUS_UNITIF_Msk)) + { + u32IntFlag |= SPI_UNIT_INT_MASK; + } + + /* Check slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) && (u32IntStatus & SPI_STATUS_SSACTIF_Msk)) + { + u32IntFlag |= SPI_SSACT_INT_MASK; + } + + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) && (u32IntStatus & SPI_STATUS_SSINAIF_Msk)) + { + u32IntFlag |= SPI_SSINACT_INT_MASK; + } + + /* Check slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) && (u32IntStatus & SPI_STATUS_SLVURIF_Msk)) + { + u32IntFlag |= SPI_SLVUR_INT_MASK; + } + + /* Check slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) && (u32IntStatus & SPI_STATUS_SLVBEIF_Msk)) + { + u32IntFlag |= SPI_SLVBE_INT_MASK; + } + + /* Check slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) && (u32IntStatus & SPI_STATUS_TXUFIF_Msk)) + { + u32IntFlag |= SPI_TXUF_INT_MASK; + } + + /* Check TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (u32IntStatus & SPI_STATUS_TXTHIF_Msk)) + { + u32IntFlag |= SPI_FIFO_TXTH_INT_MASK; + } + + /* Check RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (u32IntStatus & SPI_STATUS_RXTHIF_Msk)) + { + u32IntFlag |= SPI_FIFO_RXTH_INT_MASK; + } + + /* Check RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (u32IntStatus & SPI_STATUS_RXOVIF_Msk)) + { + u32IntFlag |= SPI_FIFO_RXOV_INT_MASK; + } + + /* Check RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32IntStatus & SPI_STATUS_RXTOIF_Msk)) + { + u32IntFlag |= SPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear SPI related interrupt flags specified by u32Mask parameter. + */ +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + if(u32Mask & SPI_UNIT_INT_MASK) + { + spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if(u32Mask & SPI_SSACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if(u32Mask & SPI_SSINACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if(u32Mask & SPI_SLVUR_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if(u32Mask & SPI_SLVBE_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if(u32Mask & SPI_TXUF_INT_MASK) + { + spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if(u32Mask & SPI_FIFO_RXOV_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if(u32Mask & SPI_FIFO_RXTO_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get SPI status. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref SPI_BUSY_MASK + * - \ref SPI_RX_EMPTY_MASK + * - \ref SPI_RX_FULL_MASK + * - \ref SPI_TX_EMPTY_MASK + * - \ref SPI_TX_FULL_MASK + * - \ref SPI_TXRX_RESET_MASK + * - \ref SPI_SPIEN_STS_MASK + * - \ref SPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get SPI related status specified by u32Mask parameter. + */ +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32TmpStatus; + uint32_t u32Flag = 0UL; + + u32TmpStatus = spi->STATUS; + + /* Check busy status */ + if((u32Mask & SPI_BUSY_MASK) && (u32TmpStatus & SPI_STATUS_BUSY_Msk)) + { + u32Flag |= SPI_BUSY_MASK; + } + + /* Check RX empty flag */ + if((u32Mask & SPI_RX_EMPTY_MASK) && (u32TmpStatus & SPI_STATUS_RXEMPTY_Msk)) + { + u32Flag |= SPI_RX_EMPTY_MASK; + } + + /* Check RX full flag */ + if((u32Mask & SPI_RX_FULL_MASK) && (u32TmpStatus & SPI_STATUS_RXFULL_Msk)) + { + u32Flag |= SPI_RX_FULL_MASK; + } + + /* Check TX empty flag */ + if((u32Mask & SPI_TX_EMPTY_MASK) && (u32TmpStatus & SPI_STATUS_TXEMPTY_Msk)) + { + u32Flag |= SPI_TX_EMPTY_MASK; + } + + /* Check TX full flag */ + if((u32Mask & SPI_TX_FULL_MASK) && (u32TmpStatus & SPI_STATUS_TXFULL_Msk)) + { + u32Flag |= SPI_TX_FULL_MASK; + } + + /* Check TX/RX reset flag */ + if((u32Mask & SPI_TXRX_RESET_MASK) && (u32TmpStatus & SPI_STATUS_TXRXRST_Msk)) + { + u32Flag |= SPI_TXRX_RESET_MASK; + } + + /* Check SPIEN flag */ + if((u32Mask & SPI_SPIEN_STS_MASK) && (u32TmpStatus & SPI_STATUS_SPIENSTS_Msk)) + { + u32Flag |= SPI_SPIEN_STS_MASK; + } + + /* Check SPIx_SS line status */ + if((u32Mask & SPI_SSLINE_STS_MASK) && (u32TmpStatus & SPI_STATUS_SSLINE_Msk)) + { + u32Flag |= SPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + +/** + * @brief Get SPI status2. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref SPI_SLVBENUM_MASK + * + * @return Flags of selected sources. + * @details Get SPI related status specified by u32Mask parameter. + */ +uint32_t SPI_GetStatus2(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32TmpStatus; + uint32_t u32Number = 0UL; + + u32TmpStatus = spi->STATUS2; + + /* Check effective bit number of uncompleted RX data status */ + if(u32Mask & SPI_SLVBENUM_MASK) + { + u32Number = (u32TmpStatus & SPI_STATUS2_SLVBENUM_Msk) >> SPI_STATUS2_SLVBENUM_Pos; + } + + return u32Number; +} + + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s The pointer of the specified I2S module. + * @return I2S source clock frequency (Hz). + * @details Return the source clock frequency according to the setting of SPI0SEL (CLK_CLKSEL2[5:4]) or SPI1SEL (CLK_CLKSEL2[7:6]) or SPI2SEL (CLK_CLKSEL2[11:10]) or SPI3SEL (CLK_CLKSEL2[13:12]). + */ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s) +{ + uint32_t u32Freq; + + if((i2s == SPI0) || (i2s == SPI0_NS)) + { + if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32Freq = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else if((i2s == SPI1) || (i2s == SPI1_NS)) + { + if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32Freq = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else if((i2s == SPI2) || (i2s == SPI2_NS)) + { + if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32Freq = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + u32Freq = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below. + * - \ref SPII2S_MODE_MASTER + * - \ref SPII2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are listed below. + * - \ref SPII2S_DATABIT_8 + * - \ref SPII2S_DATABIT_16 + * - \ref SPII2S_DATABIT_24 + * - \ref SPII2S_DATABIT_32 + * @param[in] u32Channels Audio format. Valid values are listed below. + * - \ref SPII2S_MONO + * - \ref SPII2S_STEREO + * @param[in] u32DataFormat Data format. Valid values are listed below. + * - \ref SPII2S_FORMAT_I2S + * - \ref SPII2S_FORMAT_MSB + * - \ref SPII2S_FORMAT_PCMA + * - \ref SPII2S_FORMAT_PCMB + * @return Real sample rate of master mode or peripheral clock rate of slave mode. + * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters. + * Set TX FIFO threshold to 2 and RX FIFO threshold to 1. Both the TX and RX functions will be enabled. + * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference. + * @note In slave mode for Secure, the SPI peripheral clock rate will equal to APB clock rate. + * @note In slave mode for Non-Secure, the SPI peripheral clock rate will equal to the clock rate set in secure mode. + */ +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat) +{ + uint32_t u32Divider; + uint32_t u32BitRate, u32SrcClk, u32RetValue; + uint32_t u32PCLK0Freq, u32PCLK1Freq; + + if(!(__PC() & NS_OFFSET)) + { + /* Reset SPI/I2S */ + if((i2s == SPI0) || (i2s == SPI0_NS)) + { + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } + else if((i2s == SPI1) || (i2s == SPI1_NS)) + { + SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; + } + else if((i2s == SPI2) || (i2s == SPI2_NS)) + { + SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; + } + else + { + SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk; + } + } + + /* Configure I2S controller */ + i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat; + /* Set TX FIFO threshold to 2 and RX FIFO threshold to 1 */ + i2s->FIFOCTL = SPII2S_FIFO_TX_LEVEL_WORD_2 | SPII2S_FIFO_RX_LEVEL_WORD_2; + + if(u32MasterSlave == SPII2S_MODE_MASTER) + { + /* Get the source clock rate */ + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + + /* Calculate the bit clock rate */ + u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1UL) * 16UL; + u32Divider = (((((u32SrcClk * 10UL) / u32BitRate) >> 1UL) + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + /* Set BCLKDIV setting */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos); + /* Enable I2S mode for the frequency of peripheral clock. */ + i2s->I2SCLK |= SPI_I2SCLK_I2SMODE_Msk; + + /* Calculate bit clock rate */ + u32BitRate = u32SrcClk / ((u32Divider + 1UL) * 2UL); + /* Calculate real sample rate */ + u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1UL) * 16UL); + + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + + /* Return the real sample rate */ + u32RetValue = u32SampleRate; + } + else + { + /* Set BCLKDIV = 0 */ + i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk; + /* Get APB0 clock frequency */ + u32PCLK0Freq = CLK_GetPCLK0Freq(); + /* Get APB1 clock frequency */ + u32PCLK1Freq = CLK_GetPCLK1Freq(); + + if((i2s == SPI0) || (i2s == SPI0_NS)) + { + if(!(__PC() & NS_OFFSET)) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK1Freq; + } + else + { + /* Check clock source of I2S */ + if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32RetValue = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + /* Enable I2S slave mode and I2S mode for the frequency of peripheral clock. */ + i2s->I2SCLK |= (SPI_I2SCLK_I2SSLAVE_Msk | SPI_I2SCLK_I2SMODE_Msk); + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + } + else if((i2s == SPI1) || (i2s == SPI1_NS)) + { + if(!(__PC() & NS_OFFSET)) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK0Freq; + } + else + { + /* Check clock source of I2S */ + if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32RetValue = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + /* Enable I2S slave mode and I2S mode for the frequency of peripheral clock. */ + i2s->I2SCLK |= (SPI_I2SCLK_I2SSLAVE_Msk | SPI_I2SCLK_I2SMODE_Msk); + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + } + else if((i2s == SPI2) || (i2s == SPI2_NS)) + { + if(!(__PC() & NS_OFFSET)) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK1Freq; + } + else + { + /* Check clock source of I2S */ + if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32RetValue = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + /* Enable I2S slave mode and I2S mode for the frequency of peripheral clock. */ + i2s->I2SCLK |= (SPI_I2SCLK_I2SSLAVE_Msk | SPI_I2SCLK_I2SMODE_Msk); + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + } + else + { + if(!(__PC() & NS_OFFSET)) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK0Freq; + } + else + { + /* Check clock source of I2S */ + if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + u32RetValue = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + /* Enable I2S slave mode and I2S mode for the frequency of peripheral clock. */ + i2s->I2SCLK |= (SPI_I2SCLK_I2SSLAVE_Msk | SPI_I2SCLK_I2SMODE_Msk); + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + } + } + + return u32RetValue; +} + +/** + * @brief Disable I2S function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Disable I2S function. + */ +void SPII2S_Close(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; +} + +/** + * @brief Enable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * - \ref SPII2S_SLAVE_ERR_INT_MASK + * @return None + * @details This function enables the interrupt according to the u32Mask parameter. + */ +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Enable TX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Enable TX underflow interrupt flag */ + if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable right channel zero cross interrupt flag */ + if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk; + } + + /* Enable left channel zero cross interrupt flag */ + if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk; + } + + /* Enable bit clock loss interrupt flag */ + if((u32Mask & SPII2S_SLAVE_ERR_INT_MASK) == SPII2S_SLAVE_ERR_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_SLVERRIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * - \ref SPII2S_SLAVE_ERR_INT_MASK + * @return None + * @details This function disables the interrupt according to the u32Mask parameter. + */ +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Disable TX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Disable TX underflow interrupt flag */ + if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable right channel zero cross interrupt flag */ + if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk; + } + + /* Disable left channel zero cross interrupt flag */ + if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk; + } + + /* Disable bit clock loss interrupt flag */ + if((u32Mask & SPII2S_SLAVE_ERR_INT_MASK) == SPII2S_SLAVE_ERR_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_SLVERRIEN_Msk; + } +} + +/** + * @brief Enable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32BusClock The target MCLK clock rate. + * @return Actual MCLK clock rate + * @details Set the master clock rate according to u32BusClock parameter and enable master clock output. + * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference. + */ +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock) +{ + uint32_t u32Divider; + uint32_t u32SrcClk, u32RetValue; + + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + if(u32BusClock == u32SrcClk) + { + u32Divider = 0UL; + } + else + { + u32Divider = (u32SrcClk / u32BusClock) >> 1UL; + /* MCLKDIV is a 7-bit width configuration. The maximum value is 0x7F. */ + if(u32Divider > 0x7FUL) + { + u32Divider = 0x7FUL; + } + } + + /* Write u32Divider to MCLKDIV (SPI_I2SCLK[6:0]) */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos); + + /* Enable MCLK output */ + i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk; + + if(u32Divider == 0UL) + { + u32RetValue = u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */ + } + else + { + u32RetValue = ((u32SrcClk >> 1UL) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */ + } + + return u32RetValue; +} + +/** + * @brief Disable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output. + */ +void SPII2S_DisableMCLK(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 3. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 3. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/**@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SPI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_sys.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_sys.c new file mode 100644 index 0000000000..c5c7fb55c8 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_sys.c @@ -0,0 +1,446 @@ +/**************************************************************************//** + * @file sys.c + * @version V3.00 + * @brief M2354 series System Manager (SYS) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + + +/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions + @{ +*/ + +/** + * @brief Clear reset source + * @param[in] u32Src is system reset source. Including : + * - \ref SYS_RSTSTS_CPULKRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_SYSRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_PORF_Msk + * @return None + * @details This function clear the selected system reset source. + */ +void SYS_ClearResetSrc(uint32_t u32Src) +{ + SYS->RSTSTS = u32Src; +} + +/** + * @brief Get Brown-out detector output status + * @param None + * @retval 0 System voltage is higher than BODVL setting or BODEN is 0. + * @retval 1 System voltage is lower than BODVL setting. + * @details This function get Brown-out detector output status. + */ +uint32_t SYS_GetBODStatus(void) +{ + return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos); +} + +/** + * @brief Get reset status register value + * @param None + * @return Reset source + * @details This function get the system reset status register value. + */ +uint32_t SYS_GetResetSrc(void) +{ + return (SYS->RSTSTS); +} + +/** + * @brief Check if register is locked nor not + * @param None + * @retval 0 Write-protection function is disabled. + * 1 Write-protection function is enabled. + * @details This function check register write-protection bit setting. + */ +uint32_t SYS_IsRegLocked(void) +{ + return SYS->REGLCTL & 1UL ? 0UL : 1UL; +} + +/** + * @brief Get product ID + * @param None + * @return Product ID + * @details This function get product ID. + */ +uint32_t SYS_ReadPDID(void) +{ + return SYS->PDID; +} + +/** + * @brief Reset chip with chip reset + * @param None + * @return None + * @details This function reset chip with chip reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetChip(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk; +} + +/** + * @brief Reset chip with CPU reset + * @param None + * @return None + * @details This function reset CPU with CPU reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetCPU(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk; +} + +/** + * @brief Reset selected module + * @param[in] u32ModuleIndex is module index. Including : + * - \ref PDMA0_RST + * - \ref PDMA1_RST + * - \ref EBI_RST + * - \ref USBH_RST + * - \ref SDH0_RST + * - \ref CRC_RST + * - \ref CRPT_RST + * - \ref KS_RST + * - \ref GPIO_RST + * - \ref TMR0_RST + * - \ref TMR1_RST + * - \ref TMR2_RST + * - \ref TMR3_RST + * - \ref TMR4_RST + * - \ref TMR5_RST + * - \ref ACMP01_RST + * - \ref I2C0_RST + * - \ref I2C1_RST + * - \ref I2C2_RST + * - \ref QSPI0_RST + * - \ref SPI0_RST + * - \ref SPI1_RST + * - \ref SPI2_RST + * - \ref SPI3_RST + * - \ref UART0_RST + * - \ref UART1_RST + * - \ref UART2_RST + * - \ref UART3_RST + * - \ref UART4_RST + * - \ref UART5_RST + * - \ref CAN0_RST + * - \ref OTG_RST + * - \ref USBD_RST + * - \ref EADC_RST + * - \ref I2S0_RST + * - \ref LCD_RST + * - \ref TRNG_RST + * - \ref SC0_RST + * - \ref SC1_RST + * - \ref SC2_RST + * - \ref USCI0_RST + * - \ref USCI1_RST + * - \ref DAC_RST + * - \ref EPWM0_RST + * - \ref EPWM1_RST + * - \ref BPWM0_RST + * - \ref BPWM1_RST + * - \ref QEI0_RST + * - \ref QEI1_RST + * - \ref ECAP0_RST + * - \ref ECAP1_RST + * @return None + * @details This function reset selected module. + */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +void SYS_ResetModule(uint32_t u32ModuleIndex) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + + /* Generate reset signal to the corresponding module */ + u32TmpVal = (1UL << (u32ModuleIndex & 0x00ffffffUL)); + u32TmpAddr = (uint32_t)&SYS->IPRST0 + ((u32ModuleIndex >> 24UL)); + *(uint32_t *)u32TmpAddr |= u32TmpVal; + + /* Release corresponding module from reset state */ + u32TmpVal = ~(1UL << (u32ModuleIndex & 0x00ffffffUL)); + *(uint32_t *)u32TmpAddr &= u32TmpVal; +} +#endif + +/** + * @brief Enable and configure Brown-out detector function + * @param[in] i32Mode is reset or interrupt mode. Including : + * - \ref SYS_BODCTL_BOD_RST_EN + * - \ref SYS_BODCTL_BOD_INTERRUPT_EN + * @param[in] u32BODLevel is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_1_6V + * - \ref SYS_BODCTL_BODVL_1_8V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_2_2V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_6V + * - \ref SYS_BODCTL_BODVL_2_8V + * - \ref SYS_BODCTL_BODVL_3_0V + * @return None + * @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level. + * The register write-protection function should be disabled before using this function. + */ +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel) +{ + /* Enable Brown-out Detector function */ + /* Enable Brown-out interrupt or reset function */ + /* Select Brown-out Detector threshold voltage */ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); + SYS->BODCTL = (SYS->BODCTL & ~(SYS_BODCTL_BODRSTEN_Msk|SYS_BODCTL_BODVL_Msk)) | + ((uint32_t)i32Mode) | (u32BODLevel) | (SYS_BODCTL_BODEN_Msk); +} + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This function disable Brown-out detector function. + * The register write-protection function should be disabled before using this function. + */ +void SYS_DisableBOD(void) +{ + while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); + SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk; +} + + +/** + * @brief Set Power Level + * @param[in] u32PowerLevel is power level setting. Including : + * - \ref SYS_PLCTL_PLSEL_PL0 : Supports system clock up to 96MHz. + * - \ref SYS_PLCTL_PLSEL_PL1 : Supports system clock up to 84MHz. + * - \ref SYS_PLCTL_PLSEL_PL2 : Supports system clock up to 48MHz. + * - \ref SYS_PLCTL_PLSEL_PL3 : Supports system clock up to 4MHz. + * @return None + * @details This function select power level. + * The register write-protection function should be disabled before using this function. + */ +void SYS_SetPowerLevel(uint32_t u32PowerLevel) +{ + /* Set power voltage level */ + while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk); + SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | (u32PowerLevel); + while(SYS->PLSTS & SYS_PLSTS_PLCBUSY_Msk); +} + + +/** + * @brief Set Main Voltage Regulator Type + * @param[in] u32PowerRegulator is main voltage regulator type. Including : + * - \ref SYS_PLCTL_MVRS_LDO + * - \ref SYS_PLCTL_MVRS_DCDC + * @retval 0 main voltage regulator type setting is not finished + * @retval 1 main voltage regulator type setting is finished + * @details This function set main voltage regulator type. + * The main voltage regulator type setting to DCDC cannot finished if the inductor is not detected. + * The register write-protection function should be disabled before using this function. + */ +uint32_t SYS_SetPowerRegulator(uint32_t u32PowerRegulator) +{ + int32_t i32TimeOutCnt = 400; + uint32_t u32Ret = 1U; + uint32_t u32PowerRegStatus; + + /* Get main voltage regulator type status */ + u32PowerRegStatus = SYS->PLSTS & SYS_PLSTS_CURMVR_Msk; + + /* Set main voltage regulator type */ + if((u32PowerRegulator == SYS_PLCTL_MVRS_DCDC) && (u32PowerRegStatus == SYS_PLSTS_CURMVR_LDO)) + { + + /* Set main voltage regulator type to DCDC if status is LDO */ + while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk); + SYS->PLCTL |= SYS_PLCTL_MVRS_Msk; + + /* Wait inductor detection and main voltage regulator type change ready */ + while((SYS->PLSTS & SYS_PLSTS_CURMVR_Msk) != SYS_PLSTS_CURMVR_DCDC) + { + if(i32TimeOutCnt-- <= 0) + { + u32Ret = 0U; /* Main voltage regulator type change time-out */ + break; + } + } + + } + else if(u32PowerRegulator == SYS_PLCTL_MVRS_LDO) + { + + /* Set main voltage regulator type to LDO if status is DCDC */ + while(SYS->PLCTL & SYS_PLCTL_WRBUSY_Msk); + SYS->PLCTL &= (~SYS_PLCTL_MVRS_Msk); + + /* Wait main voltage regulator type change ready */ + while((SYS->PLSTS & SYS_PLSTS_CURMVR_Msk) != SYS_PLSTS_CURMVR_LDO) + { + if(i32TimeOutCnt-- <= 0) + { + u32Ret = 0U; /* Main voltage regulator type change time-out */ + break; + } + } + + } + + /* Clear main voltage regulator type change error flag */ + if(SYS->PLSTS & SYS_PLSTS_MVRCERR_Msk) + { + SYS->PLSTS = SYS_PLSTS_MVRCERR_Msk; + u32Ret = 0U; + } + + return u32Ret; +} + +/** + * @brief Set System SRAM Power Mode + * @param[in] u32SRAMSel is SRAM region selection. Including : + * - \ref SYS_SRAMPC0_SRAM0PM0_Msk : 0x2000_0000 - 0x2000_0FFF + * - \ref SYS_SRAMPC0_SRAM0PM1_Msk : 0x2000_1000 - 0x2000_1FFF + * - \ref SYS_SRAMPC0_SRAM0PM2_Msk : 0x2000_2000 - 0x2000_3FFF + * - \ref SYS_SRAMPC0_SRAM0PM3_Msk : 0x2000_4000 - 0x2000_5FFF + * - \ref SYS_SRAMPC0_SRAM0PM4_Msk : 0x2000_6000 - 0x2000_7FFF + * - \ref SYS_SRAMPC0_SRAM1PM0_Msk : 0x2000_8000 - 0x2000_BFFF + * - \ref SYS_SRAMPC0_SRAM1PM1_Msk : 0x2000_C000 - 0x2000_FFFF + * - \ref SYS_SRAMPC0_SRAM1PM2_Msk : 0x2001_0000 - 0x2001_3FFF + * - \ref SYS_SRAMPC0_SRAM1PM3_Msk : 0x2001_4000 - 0x2001_7FFF + * - \ref SYS_SRAMPC0_SRAM1PM4_Msk : 0x2001_8000 - 0x2001_BFFF + * - \ref SYS_SRAMPC0_SRAM1PM5_Msk : 0x2001_C000 - 0x2001_FFFF + * - \ref SYS_SRAMPC0_SRAM1PM6_Msk : 0x2002_0000 - 0x2002_3FFF + * - \ref SYS_SRAMPC0_SRAM1PM7_Msk : 0x2002_4000 - 0x2002_7FFF + * - \ref SYS_SRAMPC0_SRAM2PM0_Msk : 0x2002_8000 - 0x2002_BFFF + * - \ref SYS_SRAMPC0_SRAM2PM1_Msk : 0x2002_C000 - 0x2002_FFFF + * - \ref SYS_SRAMPC1_SRAM2PM2_Msk : 0x2003_0000 - 0x2003_3FFF + * - \ref SYS_SRAMPC1_SRAM2PM3_Msk : 0x2003_4000 - 0x2003_7FFF + * - \ref SYS_SRAMPC1_SRAM2PM4_Msk : 0x2003_8000 - 0x2003_BFFF + * - \ref SYS_SRAMPC1_SRAM2PM5_Msk : 0x2003_C000 - 0x2003_FFFF + * @param[in] u32PowerMode is SRAM power mode. Including : + * - \ref SYS_SRAMPC0_SRAM_NORMAL + * - \ref SYS_SRAMPC0_SRAM_RETENTION + * - \ref SYS_SRAMPC0_SRAM_POWER_SHUT_DOWN + * - \ref SYS_SRAMPC1_SRAM_NORMAL + * - \ref SYS_SRAMPC1_SRAM_RETENTION + * - \ref SYS_SRAMPC1_SRAM_POWER_SHUT_DOWN + * @return None + * @details This function set system SRAM power mode. + * The register write-protection function should be disabled before using this function. + */ +void SYS_SetSSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode) +{ + uint32_t u32SRAMSelPos = 0UL; + + /* Get system SRAM power mode setting position */ + while(u32SRAMSelPos < 30UL) + { + if(u32SRAMSel & (1 << u32SRAMSelPos)) + { + break; + } + else + { + u32SRAMSelPos++; + } + } + + /* Set system SRAM power mode setting */ + if(u32PowerMode & BIT31) + { + while(SYS->SRAMPC1 & SYS_SRAMPC1_PCBUSY_Msk); + SYS->SRAMPC1 = (SYS->SRAMPC1 & (~u32SRAMSel)) | (u32PowerMode << u32SRAMSelPos); + } + else + { + while(SYS->SRAMPC0 & SYS_SRAMPC0_PCBUSY_Msk); + SYS->SRAMPC0 = (SYS->SRAMPC0 & (~u32SRAMSel)) | (u32PowerMode << u32SRAMSelPos); + + } +} + +/** + * @brief Set Peripheral SRAM Power Mode + * @param[in] u32SRAMSel is SRAM region selection. Including : + * - \ref SYS_SRAMPC1_CAN_Msk + * - \ref SYS_SRAMPC1_USBD_Msk + * - \ref SYS_SRAMPC1_PDMA0_Msk + * - \ref SYS_SRAMPC1_PDMA1_Msk + * - \ref SYS_SRAMPC1_FMCCACHE_Msk + * - \ref SYS_SRAMPC1_RSA_Msk + * - \ref SYS_SRAMPC1_KS_Msk + * @param[in] u32PowerMode is SRAM power mode. Including : + * - \ref SYS_SRAMPC1_SRAM_NORMAL + * - \ref SYS_SRAMPC1_SRAM_RETENTION + * - \ref SYS_SRAMPC1_SRAM_POWER_SHUT_DOWN + * @return None + * @details This function set peripheral SRAM power mode. + * The register write-protection function should be disabled before using this function. + */ +void SYS_SetPSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode) +{ + uint32_t u32SRAMSelPos = 16UL; + + /* Get peripheral SRAM power mode setting position */ + while(u32SRAMSelPos < 30UL) + { + if(u32SRAMSel & (1 << u32SRAMSelPos)) + { + break; + } + else + { + u32SRAMSelPos++; + } + } + + /* Set peripheral SRAM power mode setting */ + while(SYS->SRAMPC1 & SYS_SRAMPC1_PCBUSY_Msk); + SYS->SRAMPC1 = (SYS->SRAMPC1 & (~u32SRAMSel)) | (u32PowerMode << u32SRAMSelPos); +} + +/** + * @brief Set Reference Voltage + * @param[in] u32VRefCTL is reference voltage setting. Including : + * - \ref SYS_VREFCTL_VREF_PIN + * - \ref SYS_VREFCTL_VREF_1_6V + * - \ref SYS_VREFCTL_VREF_2_0V + * - \ref SYS_VREFCTL_VREF_2_5V + * - \ref SYS_VREFCTL_VREF_3_0V + * - \ref SYS_VREFCTL_VREF_AVDD + * @return None + * @details This function select reference voltage. + * The register write-protection function should be disabled before using this function. + */ +void SYS_SetVRef(uint32_t u32VRefCTL) +{ + /* Set reference voltage */ + SYS->VREFCTL = (SYS->VREFCTL & (~SYS_VREFCTL_VREFCTL_Msk)) | (u32VRefCTL); +} + + +/**@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group SYS_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_tamper.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_tamper.c new file mode 100644 index 0000000000..38851f383f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_tamper.c @@ -0,0 +1,506 @@ +/**************************************************************************//** + * @file tamper.c + * @version V3.00 + * @brief M2354 series TAMPER driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TAMPER_Driver Tamper Driver + @{ +*/ + +/** @addtogroup TAMPER_EXPORTED_FUNCTIONS Tamper Exported Functions + @{ +*/ + +/** + * @brief Enable Tamper Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref TAMPER_INTEN_TAMP0IEN_Msk + * - \ref TAMPER_INTEN_TAMP1IEN_Msk + * - \ref TAMPER_INTEN_TAMP2IEN_Msk + * - \ref TAMPER_INTEN_TAMP3IEN_Msk + * - \ref TAMPER_INTEN_TAMP4IEN_Msk + * - \ref TAMPER_INTEN_TAMP5IEN_Msk + * - \ref TAMPER_INTEN_CLKFIEN_Msk + * - \ref TAMPER_INTEN_CLKSTOPIEN_Msk + * - \ref TAMPER_INTEN_OVPIEN_Msk + * - \ref TAMPER_INTEN_VGPIEN_Msk + * - \ref TAMPER_INTEN_VGNIEN_Msk + * - \ref TAMPER_INTEN_ACTSIEN_Msk + * - \ref TAMPER_INTEN_RTCLVRIEN_Msk + * - \ref TAMPER_INTEN_RTCIOIEN_Msk + * - \ref TAMPER_INTEN_RTCLKIEN_Msk + * - \ref TAMPER_INTEN_BODIEN_Msk + * + * @return None + * + * @details This API is used to enable the specify tamper interrupt function. + */ +void TAMPER_EnableInt(uint32_t u32IntFlagMask) +{ + TAMPER->INTEN |= u32IntFlagMask; +} + +/** + * @brief Disable Tamper Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref TAMPER_INTEN_TAMP0IEN_Msk + * - \ref TAMPER_INTEN_TAMP1IEN_Msk + * - \ref TAMPER_INTEN_TAMP2IEN_Msk + * - \ref TAMPER_INTEN_TAMP3IEN_Msk + * - \ref TAMPER_INTEN_TAMP4IEN_Msk + * - \ref TAMPER_INTEN_TAMP5IEN_Msk + * - \ref TAMPER_INTEN_CLKFIEN_Msk + * - \ref TAMPER_INTEN_CLKSTOPIEN_Msk + * - \ref TAMPER_INTEN_OVPIEN_Msk + * - \ref TAMPER_INTEN_VGPIEN_Msk + * - \ref TAMPER_INTEN_VGNIEN_Msk + * - \ref TAMPER_INTEN_ACTSIEN_Msk + * - \ref TAMPER_INTEN_RTCLVRIEN_Msk + * - \ref TAMPER_INTEN_RTCIOIEN_Msk + * - \ref TAMPER_INTEN_RTCLKIEN_Msk + * - \ref TAMPER_INTEN_BODIEN_Msk + * + * @return None + * + * @details This API is used to disable the specify tamper interrupt function. + */ +void TAMPER_DisableInt(uint32_t u32IntFlagMask) +{ + TAMPER->INTEN &= ~u32IntFlagMask; +} + +/** + * @brief Static Tamper Detect + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref TAMPER_TAMPER0_SELECT + * - \ref TAMPER_TAMPER1_SELECT + * - \ref TAMPER_TAMPER2_SELECT + * - \ref TAMPER_TAMPER3_SELECT + * - \ref TAMPER_TAMPER4_SELECT + * - \ref TAMPER_TAMPER5_SELECT + * + * @param[in] u32DetecLevel Tamper pin detection level select. Possible options are + * - \ref TAMPER_TAMPER_HIGH_LEVEL_DETECT + * - \ref TAMPER_TAMPER_LOW_LEVEL_DETECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref TAMPER_TAMPER_DEBOUNCE_ENABLE + * - \ref TAMPER_TAMPER_DEBOUNCE_DISABLE + * + * @return None + * + * @details This API is used to enable the tamper pin detect function with specify trigger condition. + * User needs to disable dynamic tamper function before use this API. + */ +void TAMPER_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + u32Reg = TAMPER->TIOCTL; + + u32TmpReg = (TAMPER_TIOCTL_TAMP0EN_Msk | (u32DetecLevel << TAMPER_TIOCTL_TAMP0LV_Pos) | + (u32DebounceEn << TAMPER_TIOCTL_TAMP0DBEN_Pos)); + + for(i = 0UL; i < (uint32_t)TAMPER_MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1UL << i)) + { + u32Reg &= ~((TAMPER_TIOCTL_TAMP0EN_Msk | TAMPER_TIOCTL_TAMP0LV_Msk | TAMPER_TIOCTL_TAMP0DBEN_Msk) << (i * 4UL)); + u32Reg |= (u32TmpReg << (i * 4UL)); + } + } + + TAMPER->TIOCTL = u32Reg; +} + +/** + * @brief Static Tamper Disable + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref TAMPER_TAMPER0_SELECT + * - \ref TAMPER_TAMPER1_SELECT + * - \ref TAMPER_TAMPER2_SELECT + * - \ref TAMPER_TAMPER3_SELECT + * - \ref TAMPER_TAMPER4_SELECT + * - \ref TAMPER_TAMPER5_SELECT + * + * @return None + * + * @details This API is used to disable the static tamper pin detect. + */ +void TAMPER_StaticTamperDisable(uint32_t u32TamperSelect) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + u32Reg = TAMPER->TIOCTL; + + u32TmpReg = TAMPER_TIOCTL_TAMP0EN_Msk; + + for(i = 0UL; i < (uint32_t)TAMPER_MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1UL << i)) + { + u32Reg &= ~(u32TmpReg << (i * 4UL)); + } + } + + TAMPER->TIOCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Detect + * + * @param[in] u32PairSel Tamper pin detection enable. Possible options are + * - \ref TAMPER_PAIR0_SELECT + * - \ref TAMPER_PAIR1_SELECT + * - \ref TAMPER_PAIR2_SELECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref TAMPER_TAMPER_DEBOUNCE_ENABLE + * - \ref TAMPER_TAMPER_DEBOUNCE_DISABLE + * + * @param[in] u32Pair1Source Dynamic pair 1 input source select + * 0: Pair 1 source select tamper 2 + * 1: Pair 1 source select tamper 0 + * + * @param[in] u32Pair2Source Dynamic pair 2 input source select + * 0: Pair 2 source select tamper 4 + * 1: Pair 2 source select tamper 0 + * + * @return None + * + * @details This API is used to enable the dynamic tamper. + */ +void TAMPER_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2Debounce, u32Tamper4Debounce; + + u32Reg = TAMPER->TIOCTL; + u32Reg &= ~(TAMPER_TIOCTL_TAMP0EN_Msk | TAMPER_TIOCTL_TAMP1EN_Msk | TAMPER_TIOCTL_TAMP2EN_Msk | + TAMPER_TIOCTL_TAMP3EN_Msk | TAMPER_TIOCTL_TAMP4EN_Msk | TAMPER_TIOCTL_TAMP5EN_Msk); + + u32Tamper2Debounce = u32Reg & TAMPER_TIOCTL_TAMP2DBEN_Msk; + u32Tamper4Debounce = u32Reg & TAMPER_TIOCTL_TAMP4DBEN_Msk; + + u32Reg &= ~(TAMPER_TIOCTL_TAMP0EN_Msk | TAMPER_TIOCTL_TAMP1EN_Msk | TAMPER_TIOCTL_TAMP2EN_Msk | + TAMPER_TIOCTL_TAMP3EN_Msk | TAMPER_TIOCTL_TAMP4EN_Msk | TAMPER_TIOCTL_TAMP5EN_Msk); + u32Reg &= ~(TAMPER_TIOCTL_DYN1ISS_Msk | TAMPER_TIOCTL_DYN2ISS_Msk); + u32Reg |= ((u32Pair1Source & 0x1UL) << TAMPER_TIOCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1UL) << TAMPER_TIOCTL_DYN2ISS_Pos); + + if(u32DebounceEn) + { + u32TmpReg = (TAMPER_TIOCTL_TAMP0EN_Msk | TAMPER_TIOCTL_TAMP1EN_Msk | + TAMPER_TIOCTL_TAMP0DBEN_Msk | TAMPER_TIOCTL_TAMP1DBEN_Msk | TAMPER_TIOCTL_DYNPR0EN_Msk); + } + else + { + u32TmpReg = (TAMPER_TIOCTL_TAMP0EN_Msk | TAMPER_TIOCTL_TAMP1EN_Msk | TAMPER_TIOCTL_DYNPR0EN_Msk); + } + + for(i = 0UL; i < (uint32_t)TAMPER_MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1UL << i)) + { + u32Reg &= ~((TAMPER_TIOCTL_TAMP0DBEN_Msk | TAMPER_TIOCTL_TAMP1DBEN_Msk) << (i * 8UL)); + u32Reg |= (u32TmpReg << (i * 8UL)); + } + } + + if((u32Pair1Source) && (u32PairSel & (uint32_t)TAMPER_PAIR1_SELECT)) + { + u32Reg &= ~TAMPER_TIOCTL_TAMP2EN_Msk; + u32Reg |= u32Tamper2Debounce; + } + + if((u32Pair2Source) && (u32PairSel & (uint32_t)TAMPER_PAIR2_SELECT)) + { + u32Reg &= ~TAMPER_TIOCTL_TAMP4EN_Msk; + u32Reg |= u32Tamper4Debounce; + } + + TAMPER->TIOCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Disable + * + * @param[in] u32PairSel Tamper pin detection disable. Possible options are + * - \ref TAMPER_PAIR0_SELECT + * - \ref TAMPER_PAIR1_SELECT + * - \ref TAMPER_PAIR2_SELECT + * + * @return None + * + * @details This API is used to disable the dynamic tamper. + */ +void TAMPER_DynamicTamperDisable(uint32_t u32PairSel) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2En = 0UL, u32Tamper4En = 0UL; + + u32Reg = TAMPER->TIOCTL; + + if((u32Reg & (uint32_t)TAMPER_TIOCTL_DYN1ISS_Msk) && (u32PairSel & (uint32_t)TAMPER_PAIR1_SELECT)) + { + u32Tamper2En = u32Reg & TAMPER_TIOCTL_TAMP2EN_Msk; + } + + if((u32Reg & (uint32_t)TAMPER_TIOCTL_DYN2ISS_Msk) && (u32PairSel & (uint32_t)TAMPER_PAIR2_SELECT)) + { + u32Tamper4En = u32Reg & TAMPER_TIOCTL_TAMP4EN_Msk; + } + + u32TmpReg = (TAMPER_TIOCTL_TAMP0EN_Msk | TAMPER_TIOCTL_TAMP1EN_Msk | TAMPER_TIOCTL_DYNPR0EN_Msk); + + for(i = 0UL; i < (uint32_t)TAMPER_MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1UL << i)) + { + u32Reg &= ~(u32TmpReg << ((i * 8UL))); + } + } + + u32Reg |= (u32Tamper2En | u32Tamper4En); + + TAMPER->TIOCTL = u32Reg; +} + +/** + * @brief Config Dynamic Tamper + * + * @param[in] u32ChangeRate The dynamic tamper output change rate + * - \ref TAMPER_2POW6_CLK + * - \ref TAMPER_2POW7_CLK + * - \ref TAMPER_2POW8_CLK + * - \ref TAMPER_2POW9_CLK + * - \ref TAMPER_2POW10_CLK + * - \ref TAMPER_2POW11_CLK + * - \ref TAMPER_2POW12_CLK + * - \ref TAMPER_2POW13_CLK + * + * @param[in] u32SeedReload Reload new seed or not + * 0: not reload new seed + * 1: reload new seed + * + * @param[in] u32RefPattern Reference pattern + * - \ref TAMPER_REF_RANDOM_PATTERN + * - \ref TAMPER_REF_SEED + * + * @param[in] u32Seed Seed Value (0x0 ~ 0xFFFFFFFF) + * + * @return None + * + * @details This API is used to config dynamic tamper setting. + */ +void TAMPER_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed) +{ + uint32_t u32Reg; + + u32Reg = TAMPER->TIOCTL; + + u32Reg &= ~(TAMPER_TIOCTL_DYNSRC_Msk | TAMPER_TIOCTL_SEEDRLD_Msk | TAMPER_TIOCTL_DYNRATE_Msk); + + u32Reg |= (u32ChangeRate) | ((u32SeedReload & 0x1UL) << TAMPER_TIOCTL_SEEDRLD_Pos) | + ((u32RefPattern & 0x1UL) << TAMPER_TIOCTL_DYNSRC_Pos); + + TAMPER->SEED = u32Seed; /* Need to set seed value before reloaded seed */ + TAMPER->TIOCTL = u32Reg; +} + +/** + * @brief Active Shield Dynamic Tamper Detect + * + * @param[in] u32PairSel1/2 Active shield 1/2 tamper pin detection enable. Possible options are + * - \ref TAMPER_PAIR0_SELECT + * - \ref TAMPER_PAIR1_SELECT + * - \ref TAMPER_PAIR2_SELECT + * + * @param[in] u32Pair1Source1/2 Active shield 1/2 dynamic pair 1 input source select + * 0: Pair 1 source select tamper 2 + * 1: Pair 1 source select tamper 0 + * + * @return None + * + * @details This API is used to enable the active shield dynamic tamper. + */ +void TAMPER_ActiveShieldDynamicTamperEnable(uint32_t u32PairSel1, uint32_t u32Pair1Source1, uint32_t u32PairSel2, uint32_t u32Pair1Source2) +{ + uint32_t i; + uint32_t u32Reg1, u32Reg2; + uint32_t u32TmpReg1, u32TmpReg2; + + u32Reg1 = TAMPER->ACTSTIOCTL1; + u32Reg1 &= ~(TAMPER_ACTSTIOCTL1_ATAMP0EN_Msk | TAMPER_ACTSTIOCTL1_ATAMP1EN_Msk | TAMPER_ACTSTIOCTL1_ATAMP2EN_Msk | + TAMPER_ACTSTIOCTL1_ATAMP3EN_Msk | TAMPER_ACTSTIOCTL1_ATAMP4EN_Msk | TAMPER_ACTSTIOCTL1_ATAMP5EN_Msk); + u32Reg2 = TAMPER->ACTSTIOCTL2; + u32Reg2 &= ~(TAMPER_ACTSTIOCTL2_ATAMP0EN2_Msk | TAMPER_ACTSTIOCTL2_ATAMP1EN2_Msk | TAMPER_ACTSTIOCTL2_ATAMP2EN2_Msk | + TAMPER_ACTSTIOCTL2_ATAMP3EN2_Msk | TAMPER_ACTSTIOCTL2_ATAMP4EN2_Msk | TAMPER_ACTSTIOCTL2_ATAMP5EN2_Msk); + + u32Reg1 &= ~(TAMPER_ACTSTIOCTL1_ADYN1ISS_Msk); + u32Reg1 |= ((u32Pair1Source1 & 0x1UL) << TAMPER_ACTSTIOCTL1_ADYN1ISS_Pos); + u32Reg2 &= ~(TAMPER_ACTSTIOCTL2_ADYN1ISS2_Msk); + u32Reg2 |= ((u32Pair1Source2 & 0x1UL) << TAMPER_ACTSTIOCTL2_ADYN1ISS2_Pos); + + u32TmpReg1 = (TAMPER_ACTSTIOCTL1_ATAMP0EN_Msk | TAMPER_ACTSTIOCTL1_ATAMP1EN_Msk | TAMPER_ACTSTIOCTL1_ADYNPR0EN_Msk); + u32TmpReg2 = (TAMPER_ACTSTIOCTL2_ATAMP0EN2_Msk | TAMPER_ACTSTIOCTL2_ATAMP1EN2_Msk | TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Msk); + + for(i = 0UL; i < (uint32_t)TAMPER_MAX_PAIR_NUM; i++) + { + if(u32PairSel1 & (0x1UL << i)) + { + u32Reg1 |= (u32TmpReg1 << (i * 8UL)); + } + + if(u32PairSel2 & (0x1UL << i)) + { + u32Reg2 |= (u32TmpReg2 << (i * 8UL)); + } + } + + if((u32Pair1Source1) && (u32PairSel1 & (uint32_t)TAMPER_PAIR1_SELECT)) + { + u32Reg1 &= ~TAMPER_ACTSTIOCTL1_ATAMP2EN_Msk; + } + + if((u32Pair1Source2) && (u32PairSel2 & (uint32_t)TAMPER_PAIR1_SELECT)) + { + u32Reg2 &= ~TAMPER_ACTSTIOCTL2_ATAMP2EN2_Msk; + } + + TAMPER->ACTSTIOCTL1 = u32Reg1; + TAMPER->ACTSTIOCTL2 = u32Reg2; +} + +/** + * @brief Active Shield Dynamic Tamper Disable + * + * @param[in] u32PairSel1/2 Active shield 1/2 tamper pin detection disable. Possible options are + * - \ref TAMPER_PAIR0_SELECT + * - \ref TAMPER_PAIR1_SELECT + * - \ref TAMPER_PAIR2_SELECT + * + * @return None + * + * @details This API is used to disable the active shield dynamic tamper. + */ +void TAMPER_ActiveShieldDynamicTamperDisable(uint32_t u32PairSel1, uint32_t u32PairSel2) +{ + uint32_t i; + uint32_t u32Reg1, u32Reg2; + uint32_t u32TmpReg1, u32TmpReg2; + uint32_t u32Tamper2En1 = 0UL, u32Tamper2En2 = 0UL; + + u32Reg1 = TAMPER->ACTSTIOCTL1; + u32Reg2 = TAMPER->ACTSTIOCTL2; + + if((u32Reg1 & (uint32_t)TAMPER_ACTSTIOCTL1_ADYN1ISS_Msk) && (u32PairSel1 & (uint32_t)TAMPER_PAIR1_SELECT)) + { + u32Tamper2En1 = u32Reg1 & TAMPER_ACTSTIOCTL1_ATAMP2EN_Msk; + } + + if((u32Reg2 & (uint32_t)TAMPER_ACTSTIOCTL2_ADYN1ISS2_Msk) && (u32PairSel2 & (uint32_t)TAMPER_PAIR1_SELECT)) + { + u32Tamper2En2 = u32Reg2 & TAMPER_ACTSTIOCTL2_ATAMP2EN2_Msk; + } + + u32TmpReg1 = (TAMPER_ACTSTIOCTL1_ATAMP0EN_Msk | TAMPER_ACTSTIOCTL1_ATAMP1EN_Msk | TAMPER_ACTSTIOCTL1_ADYNPR0EN_Msk); + u32TmpReg2 = (TAMPER_ACTSTIOCTL2_ATAMP0EN2_Msk | TAMPER_ACTSTIOCTL2_ATAMP1EN2_Msk | TAMPER_ACTSTIOCTL2_ADYNPR0EN2_Msk); + + for(i = 0UL; i < (uint32_t)TAMPER_MAX_PAIR_NUM; i++) + { + if(u32PairSel1 & (0x1UL << i)) + { + u32Reg1 &= ~(u32TmpReg1 << ((i * 8UL))); + } + + if(u32PairSel2 & (0x1UL << i)) + { + u32Reg2 &= ~(u32TmpReg2 << ((i * 8UL))); + } + } + + u32Reg1 |= u32Tamper2En1; + u32Reg2 |= u32Tamper2En2; + + TAMPER->ACTSTIOCTL1 = u32Reg1; + TAMPER->ACTSTIOCTL2 = u32Reg2; +} + +/** + * @brief Config Active Shield Dynamic Tamper + * + * @param[in] u32ChangeRate1/2 The dynamic tamper output change rate + * - \ref TAMPER_ACTS_2POW10_CLK + * - \ref TAMPER_ACTS_2POW11_CLK + * - \ref TAMPER_ACTS_2POW12_CLK + * - \ref TAMPER_ACTS_2POW13_CLK + * - \ref TAMPER_ACTS_2POW14_CLK + * - \ref TAMPER_ACTS_2POW15_CLK + * - \ref TAMPER_ACTS_2POW16_CLK + * - \ref TAMPER_ACTS_2POW17_CLK + * + * @param[in] u32SeedReload1/2 Reload new seed or not + * 0: not reload new seed + * 1: reload new seed + * + * @param[in] u32RefPattern1/2 Reference pattern + * - \ref TAMPER_REF_RANDOM_PATTERN + * - \ref TAMPER_REF_SEED + * + * @param[in] u32Seed/2 Seed Value (0x0 ~ 0xFFFFFFFF) + * + * @return None + * + * @details This API is used to config active shield dynamic tamper setting. + */ +void TAMPER_ActiveShieldDynamicTamperConfig(uint32_t u32ChangeRate1, uint32_t u32SeedReload1, uint32_t u32RefPattern1, uint32_t u32Seed, + uint32_t u32ChangeRate2, uint32_t u32SeedReload2, uint32_t u32RefPattern2, uint32_t u32Seed2) +{ + uint32_t u32Reg1, u32Reg2; + + u32Reg1 = TAMPER->ACTSTIOCTL1; + u32Reg2 = TAMPER->ACTSTIOCTL2; + + u32Reg1 &= ~(TAMPER_ACTSTIOCTL1_ADYNSRC_Msk | TAMPER_ACTSTIOCTL1_ADYNRATE_Msk); + u32Reg2 &= ~(TAMPER_ACTSTIOCTL2_ADYNSRC2_Msk | TAMPER_ACTSTIOCTL2_SEEDRLD2_Msk | TAMPER_ACTSTIOCTL2_ADYNRATE2_Msk); + + u32Reg1 |= (u32ChangeRate1) | ((u32RefPattern1 & 0x1UL) << TAMPER_ACTSTIOCTL1_ADYNSRC_Pos); + u32Reg2 |= (u32ChangeRate2) | ((u32SeedReload2 & 0x1UL) << TAMPER_ACTSTIOCTL2_SEEDRLD2_Pos) | + ((u32RefPattern2 & 0x1UL) << TAMPER_ACTSTIOCTL2_ADYNSRC2_Pos); + + TAMPER->SEED = u32Seed; /* Need to set seed value before reloaded seed */ + TAMPER->SEED2 = u32Seed2; /* Need to set seed value before reloaded seed */ + + TAMPER->ACTSTIOCTL1 = u32Reg1; + TAMPER->TIOCTL |= ((u32SeedReload1 & 0x1UL) << TAMPER_TIOCTL_SEEDRLD_Pos); + TAMPER->ACTSTIOCTL2 = u32Reg2; +} + +/**@}*/ /* end of group TAMPER_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group TAMPER_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_timer.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_timer.c new file mode 100644 index 0000000000..8a099c89d7 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_timer.c @@ -0,0 +1,410 @@ +/**************************************************************************//** + * @file timer.c + * @version V3.00 + * @brief Timer Controller(Timer) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Open Timer with Operate Mode and Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32Mode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * @param[in] u32Freq Target working frequency + * + * @return Real timer working frequency + * + * @details This API is used to configure timer to operate in specified mode and frequency. + * If timer cannot work in target frequency, a closest frequency will be chose and returned. + * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling + * \ref TIMER_Start macro or program registers directly. + */ +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq) +{ + uint32_t u32ClkFreq = TIMER_GetModuleClock(timer); + uint32_t u32Cmpr = 0UL, u32Prescale = 0UL; + + /* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, prescaler = 0. */ + if(u32Freq > (u32ClkFreq / 2UL)) + { + u32Cmpr = 2UL; + } + else + { + u32Cmpr = u32ClkFreq / u32Freq; + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CTL = u32Mode | u32Prescale; + timer->CMP = u32Cmpr; + + return (u32ClkFreq / (u32Cmpr * (u32Prescale + 1UL))); +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This API stops timer counting and disable all timer interrupt function. + */ +void TIMER_Close(TIMER_T *timer) +{ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; +} + +/** + * @brief Create a specify Delay Time + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second). + * + * @return None + * + * @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode. + * @note This API overwrites the register setting of the timer used to count the delay time. + * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay. + */ +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec) +{ + uint32_t u32ClkFreq = TIMER_GetModuleClock(timer); + uint32_t u32Prescale = 0UL, u32Delay = (SystemCoreClock / u32ClkFreq) + 1UL; + uint32_t u32Cmpr, u32NsecPerTick; + + /* Clear current timer configuration */ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; + + if(u32ClkFreq <= 1000000UL) /* min delay is 1000 us if timer clock source is <= 1 MHz */ + { + if(u32Usec < 1000UL) + { + u32Usec = 1000UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + else + { + if(u32Usec < 100UL) + { + u32Usec = 100UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + + if(u32ClkFreq <= 1000000UL) + { + u32Prescale = 0UL; + u32NsecPerTick = 1000000000UL / u32ClkFreq; + u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick; + } + else + { + u32Cmpr = u32Usec * (u32ClkFreq / 1000000UL); + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CMP = u32Cmpr; + timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale; + + /* + When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it. + And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag. + */ + for(; u32Delay > 0UL; u32Delay--) + { + __NOP(); + } + + while((timer->CTL & TIMER_CTL_ACTSTS_Msk) == TIMER_CTL_ACTSTS_Msk) {} +} + +/** + * @brief Enable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32CapMode Timer capture mode. Could be + * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE + * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE + * @param[in] u32Edge Timer capture trigger edge. Possible values are + * - \ref TIMER_CAPTURE_EVENT_FALLING + * - \ref TIMER_CAPTURE_EVENT_RISING + * - \ref TIMER_CAPTURE_EVENT_FALLING_RISING + * - \ref TIMER_CAPTURE_EVENT_RISING_FALLING + * - \ref TIMER_CAPTURE_EVENT_GET_LOW_PERIOD + * - \ref TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD + * + * @return None + * + * @details This API is used to enable timer capture function with specify capture trigger edge \n + * to get current counter value or reset counter value to 0. + * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly. + */ +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) | + u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Disable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This API is used to disable the timer capture function. + */ +void TIMER_DisableCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32Edge Detection edge of counter pin. Could be ether + * - \ref TIMER_COUNTER_EVENT_FALLING, or + * - \ref TIMER_COUNTER_EVENT_RISING + * + * @return None + * + * @details This function is used to enable the timer counter function with specify detection edge. + * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly. + * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode. + */ +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge; + timer->CTL |= TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Disable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This API is used to disable the timer event counter function. + */ +void TIMER_DisableEventCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Get Timer Clock Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return Timer clock frequency + * + * @details This API is used to get the timer clock frequency. + * @note This API cannot return correct clock rate if timer source is from external clock input. + */ +uint32_t TIMER_GetModuleClock(TIMER_T *timer) +{ + uint32_t u32Src, u32ClkFreq = __HIRC; + const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, __MIRC, __LIRC, 0UL, __HIRC}; + + if(timer == TIMER0) + { + u32Src = CLK_GetModuleClockSource(TMR0_MODULE); + } + else if(timer == TIMER1) + { + u32Src = CLK_GetModuleClockSource(TMR1_MODULE); + } + else if((timer == TIMER2) || (timer == TIMER2_NS)) + { + u32Src = CLK_GetModuleClockSource(TMR2_MODULE); + } + else if((timer == TIMER3) || (timer == TIMER3_NS)) + { + u32Src = CLK_GetModuleClockSource(TMR3_MODULE); + } + else if((timer == TIMER4) || (timer == TIMER4_NS)) + { + u32Src = CLK_GetModuleClockSource(TMR4_MODULE); + } + else if((timer == TIMER5) || (timer == TIMER5_NS)) + { + u32Src = CLK_GetModuleClockSource(TMR5_MODULE); + } + else + { + return 0UL; + } + + if(u32Src == 2UL) + { + if((timer == TIMER0) || (timer == TIMER1) || + (timer == TIMER4) || (timer == TIMER4_NS) || (timer == TIMER5) || (timer == TIMER5_NS)) + { + u32ClkFreq = CLK_GetPCLK0Freq(); + } + else + { + u32ClkFreq = CLK_GetPCLK1Freq(); + } + } + else + { + u32ClkFreq = au32Clk[u32Src]; + } + + return u32ClkFreq; +} + +/** + * @brief Enable Timer Frequency Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER2, TIMER4. + * @param[in] u32DropCount This parameter has no effect in this BSP + * @param[in] u32Timeout This parameter has no effect in this BSP + * @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE + * + * @return None + * + * @details This function is used to calculate input event frequency. After enable + * this function, a pair of timers, TIMER0 and TIMER1, TIMER2 and TIMER3, or TIMER4 and TIMER5 + * will be configured for this function. The mode used to calculate input + * event frequency is mentioned as "Inter Timer Trigger Mode" in Technical + * Reference Manual. + */ +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt) +{ + TIMER_T *t; /* store the timer base to configure compare value */ + + (void)u32DropCount; + (void)u32Timeout; + + if(timer == TIMER0) + { + t = TIMER1; + } + else if(timer == TIMER2) + { + t = TIMER3; + } + else if(timer == TIMER2_NS) + { + t = TIMER3_NS; + } + else if(timer == TIMER4) + { + t = TIMER5; + } + else if(timer == TIMER4_NS) + { + t = TIMER5_NS; + } + else + { + t = 0; + } + + if(t != 0) + { + t->CMP = 0xFFFFFFUL; + t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0UL; + timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk; + } +} + +/** + * @brief Disable Timer Frequency Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @brief This function is used to disable the Timer frequency counter function. + */ +void TIMER_DisableFreqCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTRGEN_Msk; +} + +/** + * @brief Select Interrupt Source to Trigger others Module + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32Src Selects the interrupt source to trigger other modules. Could be: + * - \ref TIMER_TRGSRC_TIMEOUT_EVENT + * - \ref TIMER_TRGSRC_CAPTURE_EVENT + * + * @return None + * + * @brief This function is used to select the interrupt source used to trigger other modules. + */ +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src) +{ + timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src; +} + +/** + * @brief Set Modules Trigger by Timer Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32Mask The mask of modules (EPWM, EADC, DAC and PDMA) trigger by timer. It could the combination of + * - \ref TIMER_TRG_TO_PWM, + * - \ref TIMER_TRG_TO_EADC, + * - \ref TIMER_TRG_TO_DAC and + * - \ref TIMER_TRG_TO_PDMA + * + * @return None + * + * @details This function is used to set EPWM, EADC, DAC and PDMA module triggered by timer interrupt event. + * @note The \ref TIMER_TRG_TO_PWM and \ref TIMER_TRG_TO_DAC are only available on TIMER0 ~ TIMER3. + */ +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask) +{ + timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGPWM_Msk | TIMER_TRGCTL_TRGDAC_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask; +} + +/**@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group TIMER_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_timer_pwm.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_timer_pwm.c new file mode 100644 index 0000000000..bc3de028a6 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_timer_pwm.c @@ -0,0 +1,579 @@ +/**************************************************************************//** + * @file timer.c + * @version V3.00 + * @brief Timer PWM Controller(Timer PWM) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions + @{ +*/ + +/** + * @brief Set PWM Counter Clock Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CntClkSrc PWM counter clock source, could be one of following source + * - \ref TPWM_CNTR_CLKSRC_TMR_CLK + * - \ref TPWM_CNTR_CLKSRC_TIMER0_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER1_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER2_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER3_INT + * + * @return None + * + * @details This function is used to set PWM counter clock source. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc) +{ + (timer)->PWMCLKSRC = ((timer)->PWMCLKSRC & ~TIMER_PWMCLKSRC_CLKSRC_Msk) | u32CntClkSrc; +} + +/** @cond HIDDEN_SYMBOLS */ +/** + * @brief Get Timer PWM Clock Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return Timer clock frequency + * + * @details This API is used to get the timer pwm clock frequency. + * @note This API cannot return correct clock rate if timer source is from external clock input. + */ +static uint32_t TPWM_GetModuleClockFreq(TIMER_T *timer) +{ + uint32_t u32Src, u32ClkFreq = __HIRC; + const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, __MIRC, __LIRC, 0UL, __HIRC}; + + if(timer == TIMER0) + { + u32Src = CLK_GetModuleClockSource(TMR0_MODULE); + } + else if(timer == TIMER1) + { + u32Src = CLK_GetModuleClockSource(TMR1_MODULE); + } + else if((timer == TIMER2) || (timer == TIMER2_NS)) + { + u32Src = CLK_GetModuleClockSource(TMR2_MODULE); + } + else if((timer == TIMER3) || (timer == TIMER3_NS)) + { + u32Src = CLK_GetModuleClockSource(TMR3_MODULE); + } + else if((timer == TIMER4) || (timer == TIMER4_NS)) + { + u32Src = CLK_GetModuleClockSource(TMR4_MODULE); + } + else if((timer == TIMER5) || (timer == TIMER5_NS)) + { + u32Src = CLK_GetModuleClockSource(TMR5_MODULE); + } + else + { + return 0UL; + } + + if(u32Src == 2UL) + { + if((timer == TIMER0) || (timer == TIMER1) || + (timer == TIMER4) || (timer == TIMER4_NS) || (timer == TIMER5) || (timer == TIMER5_NS)) + { + u32ClkFreq = CLK_GetPCLK0Freq(); + } + else + { + u32ClkFreq = CLK_GetPCLK1Freq(); + } + } + else + { + u32ClkFreq = au32Clk[u32Src]; + } + + return u32ClkFreq; +} +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Configure PWM Output Frequency and Duty Cycle + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32Frequency Target generator frequency. + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%... + * + * @return Nearest frequency clock in nano second + * + * @details This API is used to configure PWM output frequency and duty cycle in up count type and auto-reload operation mode. + * @note This API is only available if Timer PWM counter clock source is from TMRx_CLK. + */ +uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32PWMClockFreq, u32TargetFreq; + uint32_t u32Prescaler = 0x1000UL, u32Period = 1UL, u32CMP, u32MaxCLKPSC = 0x1000UL; + + if((timer == TIMER0) || (timer == TIMER1)) + { + u32PWMClockFreq = CLK_GetPCLK0Freq(); + } + else if((timer == TIMER4) || (timer == TIMER4_NS) || (timer == TIMER5) || (timer == TIMER5_NS)) + { + u32PWMClockFreq = TPWM_GetModuleClockFreq(timer); + } + else + { + u32PWMClockFreq = CLK_GetPCLK1Freq(); + } + + if((timer == TIMER4) || (timer == TIMER4_NS) || (timer == TIMER5) || (timer == TIMER5_NS)) + u32MaxCLKPSC = 0x100UL; // 8-bit clock prescale on TIMER4 and TIMER5 PWM + else + u32MaxCLKPSC = 0x1000UL; // 12-bit clock prescale on TIMER0 ~ TIMER3 PWM + + /* Calculate u16PERIOD and u16PSC */ + for(u32Prescaler = 1UL; u32Prescaler <= u32MaxCLKPSC; u32Prescaler++) + { + u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency; + + /* If target u32Period is larger than 0x10000, need to use a larger prescaler */ + if(u32Period <= 0x10000UL) + { + break; + } + } + /* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */ + u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period; + + /* Set PWM to up count type */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (TPWM_UP_COUNT << TIMER_PWMCTL_CNTTYPE_Pos); + + /* Set PWM to auto-reload mode */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | (TPWM_AUTO_RELOAD_MODE << TIMER_PWMCTL_CNTMODE_Pos); + + /* Convert to real register value */ + TPWM_SET_PERIOD(timer, (u32Period - 1UL)); + if(u32DutyCycle) + { + u32CMP = (u32DutyCycle * u32Period) / 100UL; + } + else + { + u32CMP = 0UL; + } + + TPWM_SET_CMPDAT(timer, u32CMP); + + TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL)); + + return (u32TargetFreq); +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the same as Timer PWM clock source. + * @note The register write-protection function should be disabled before using this function. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the Timer PWM clock source with prescale. + * @note The register write-protection function should be disabled before using this function. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTCKSEL_Msk | TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Disable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable Dead-time of selected channel. + * @note The register write-protection function should be disabled before using this function. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_DisableDeadTime(TIMER_T *timer) +{ + timer->PWMDTCTL = 0x0UL; +} + +/** + * @brief Enable PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to enable PWM generator and start counter counting. + */ +void TPWM_EnableCounter(TIMER_T *timer) +{ + timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Disable PWM Generator + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to disable PWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit. + */ +void TPWM_DisableCounter(TIMER_T *timer) +{ + timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Enable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * @param[in] u32Condition The condition to trigger ADC. It could be one of following conditions: + * - \ref TPWM_TRIGGER_EVENT_AT_ZERO_POINT + * - \ref TPWM_TRIGGER_EVENT_AT_PERIOD_POINT + * - \ref TPWM_TRIGGER_EVENT_AT_ZERO_OR_PERIOD_POINT + * - \ref TPWM_TRIGGER_EVENT_AT_COMPARE_UP_POINT + * - \ref TPWM_TRIGGER_EVENT_AT_COMPARE_DOWN_POINT + * - \ref TPWM_TRIGGER_EVENT_AT_PERIOD_OR_COMPARE_UP_POINT + * + * @return None + * + * @details This function is used to enable specified counter compare event to trigger ADC. + * @note TIMER4 and TIMER5 only supports \ref TPWM_TRIGGER_EVENT_AT_PERIOD_POINT, \ref TPWM_TRIGGER_EVENT_AT_COMPARE_UP_POINT, + * and \ref TPWM_TRIGGER_EVENT_AT_PERIOD_OR_COMPARE_UP_POINT. + */ +void TPWM_EnableTriggerADC(TIMER_T *timer, uint32_t u32Condition) +{ + timer->PWMTRGCTL = ((timer->PWMTRGCTL & ~TIMER_PWMTRGCTL_TRGSEL_Msk) | (u32Condition)) | TIMER_PWMTRGCTL_TRGEADC_Msk; +} + +/** + * @brief Disable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0 ~ TIMER5. + * + * @return None + * + * @details This function is used to disable counter compare event to trigger ADC. + */ +void TPWM_DisableTriggerADC(TIMER_T *timer) +{ + timer->PWMTRGCTL &= ~TIMER_PWMTRGCTL_TRGEADC_Msk; +} + +/** + * @brief Enable Trigger PDMA + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 or TIMER5. + * @param[in] u32Condition The condition to trigger PDMA. It could be one of following conditions: + * - \ref TPWM_TRIGGER_EVENT_AT_PERIOD_POINT + * - \ref TPWM_TRIGGER_EVENT_AT_COMPARE_UP_POINT + * - \ref TPWM_TRIGGER_EVENT_AT_PERIOD_OR_COMPARE_UP_POINT + * + * @return None + * + * @details This function is used to enable specified counter compare event to trigger PDMA. + * @note Only available on TIMER4 and TIMER5. + */ +void TPWM_EnableTriggerPDMA(TIMER_T *timer, uint32_t u32Condition) +{ + timer->PWMTRGCTL = ((timer->PWMTRGCTL & ~TIMER_PWMTRGCTL_TRGSEL_Msk) | (u32Condition)) | TIMER_PWMTRGCTL_TRGPDMA_Msk; +} + +/** + * @brief Disable Trigger PDMA + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER4 or TIMER5. + * + * @return None + * + * @details This function is used to disable counter compare event to trigger ADC. + * @note Only available on TIMER4 and TIMER5. + */ +void TPWM_DisableTriggerPDMA(TIMER_T *timer) +{ + timer->PWMTRGCTL &= ~TIMER_PWMTRGCTL_TRGPDMA_Msk; +} + +/** + * @brief Enable Fault Brake Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CH0Level PWMx_CH0 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32CH1Level PWMx_CH1 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32BrakeSource Fault brake source, combination of following source + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_EDGE_BKPIN + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_RAM + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_BKPIN + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM + * + * @return None + * + * @details This function is used to enable fault brake function. + * @note The register write-protection function should be disabled before using this function. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource) +{ + timer->PWMFAILBRK |= ((u32BrakeSource >> 16) & 0xFUL); + timer->PWMBRKCTL = (timer->PWMBRKCTL & ~(TIMER_PWMBRKCTL_BRKAEVEN_Msk | TIMER_PWMBRKCTL_BRKAODD_Msk)) | + (u32BrakeSource & 0xFFFFUL) | (u32CH0Level << TIMER_PWMBRKCTL_BRKAEVEN_Pos) | (u32CH1Level << TIMER_PWMBRKCTL_BRKAODD_Pos); +} + +/** + * @brief Enable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to enable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 |= u32IntSource; +} + +/** + * @brief Disable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to disable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 &= ~u32IntSource; +} + +/** + * @brief Indicate Fault Brake Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * + * @details This function is used to indicate fault brake interrupt flag occurred or not of selected source. + * @note NOT available on TIMER4 and TIMER5. + */ +uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + return ((timer->PWMINTSTS1 & (0x3UL << u32IntSource)) ? 1UL : 0UL); +} + +/** + * @brief Clear Fault Brake Interrupt Flags + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to clear fault brake interrupt flags of selected source. + * @note The register write-protection function should be disabled before using this function. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTSTS1 = (0x3UL << u32IntSource); +} + +/** + * @brief Enable Load Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32LoadMode Timer PWM counter loading mode, could be one of following mode + * - \ref TPWM_LOAD_MODE_PERIOD + * - \ref TPWM_LOAD_MODE_IMMEDIATE + * - \ref TPWM_LOAD_MODE_CENTER + * + * @return None + * + * @details This function is used to enable load mode of selected channel. + * @note The default loading mode is period loading mode. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode) +{ + timer->PWMCTL = (timer->PWMCTL & ~(TIMER_PWMCTL_IMMLDEN_Msk | TIMER_PWMCTL_CTRLD_Msk)) | u32LoadMode; +} + +/** + * @brief Enable Brake Pin Noise Filter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32BrakePinSrc The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * @param[in] u32DebounceCnt This value controls the real debounce sample time. + * The target debounce sample time is (debounce sample clock period) * (u32DebounceCnt). + * @param[in] u32ClkSrcSel Brake pin detector debounce clock source, could be one of following source + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_1 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_2 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_4 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_8 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_16 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_32 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_64 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_128 + * + * @return None + * + * @details This function is used to enable external brake pin detector noise filter function. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel) +{ + timer->PWMBNF = (timer->PWMBNF & ~(TIMER_PWMBNF_BKPINSRC_Msk | TIMER_PWMBNF_BRKFCNT_Msk | TIMER_PWMBNF_BRKNFSEL_Msk)) | + (u32BrakePinSrc << TIMER_PWMBNF_BKPINSRC_Pos) | + (u32DebounceCnt << TIMER_PWMBNF_BRKFCNT_Pos) | + (u32ClkSrcSel << TIMER_PWMBNF_BRKNFSEL_Pos) | TIMER_PWMBNF_BRKNFEN_Msk; +} + +/** + * @brief Disable Brake Pin Noise Filter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable external brake pin detector noise filter function. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_DisableBrakePinDebounce(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKNFEN_Msk; +} + +/** + * @brief Enable Brake Pin Inverse Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable PWM brake pin inverse function. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_EnableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Disable Brake Pin Inverse Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable PWM brake pin inverse function. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_DisableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Set Brake Pin Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32BrakePinNum Brake pin selection. One of the following: + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * + * @return None + * + * @details This function is used to set PWM brake pin source. + * @note NOT available on TIMER4 and TIMER5. + */ +void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum) +{ + timer->PWMBNF = (((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | (u32BrakePinNum << TIMER_PWMBNF_BKPINSRC_Pos)); +} + + +/**@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group TIMER_PWM_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_uart.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_uart.c new file mode 100644 index 0000000000..8f3dea8e7c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_uart.c @@ -0,0 +1,690 @@ +/**************************************************************************//** + * @file uart.c + * @version V3.00 + * @brief M2354 series UART Interface Controller (UART) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup UART_Driver UART Driver + @{ +*/ + + +/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ + +/** + * @brief Clear UART specified interrupt flag + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTSTS_SWBEINT_Msk : Single-wire Bit Error Detect Interrupt + * - \ref UART_INTSTS_LININT_Msk : LIN Bus interrupt + * - \ref UART_INTSTS_WKINT_Msk : Wake-up interrupt + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt + * - \ref UART_INTSTS_MODEMINT_Msk : MODEM Status Interrupt + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt + * + * @return None + * + * @details The function is used to clear UART specified interrupt flag. + */ +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag) +{ + if (u32InterruptFlag & UART_INTSTS_SWBEINT_Msk) /* Clear Bit Error Detection Interrupt */ + { + uart->FIFOSTS = UART_INTSTS_SWBEIF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_ADDRDETF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear MODEM Status Interrupt */ + { + uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */ + { + uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk | + UART_WKSTS_RFRTWKF_Msk | UART_WKSTS_RS485WKF_Msk | + UART_WKSTS_TOUTWKF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */ + { + uart->INTSTS = UART_INTSTS_LINIF_Msk; + uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk | + UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk | + UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ; + } + +} + + +/** + * @brief Disable UART interrupt + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART interrupt. + */ +void UART_Close(UART_T* uart) +{ + uart->INTEN = 0ul; +} + + +/** + * @brief Disable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART auto flow control. + */ +void UART_DisableFlowCtrl(UART_T* uart) +{ + uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk); +} + + +/** + * @brief Disable UART specified interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt + * - \ref UART_INTEN_SWBEIEN_Msk : Single-wire Bit Error Detect Interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt + * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt + * + * @return None + * + * @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ. + */ +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + /* Disable UART specified interrupt */ + UART_DISABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Enable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to Enable UART auto flow control. + */ +/** + * @brief Enable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to Enable UART auto flow control. + */ +void UART_EnableFlowCtrl(UART_T* uart) +{ + /* Set RTS pin output is low level active */ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + + /* Set CTS pin input is low level active */ + uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk; + + /* Set RTS and CTS auto flow control enable */ + uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk; +} + + +/** + * @brief Enable UART specified interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module: + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt + * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt + * + * @return None + * + * @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ. + */ +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + + /* Enable UART specified interrupt */ + UART_ENABLE_INT(uart, u32InterruptFlag); +} + + +/** + * @brief Open and set UART function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The baudrate of UART module. + * + * @return None + * + * @details This function use to enable UART function and set baud-rate. + */ +void UART_Open(UART_T* uart, uint32_t u32baudrate) +{ + uint32_t u32UartClkSrcSel, u32UartClkDivNum; + uint32_t au32ClkTbl[8] = { __HXT, 0ul, __LXT, __HIRC, 0ul, 0ul, 0ul, 0ul}; + uint32_t u32BaudDiv = 0ul; + + /* Get UART clock source selection and UART clock divider number */ + switch((uint32_t)uart) + { + case UART0_BASE: + case UART0_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK0Freq(); + break; + case UART1_BASE: + case UART1_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK1Freq(); + break; + case UART2_BASE: + case UART2_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK0Freq(); + break; + case UART3_BASE: + case UART3_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK1Freq(); + break; + case UART4_BASE: + case UART4_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK0Freq(); + break; + case UART5_BASE: + case UART5_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK1Freq(); + break; + default: + return; + } + + /* Select UART function */ + uart->FUNCSEL = UART_FUNCSEL_UART; + + /* Set UART line configuration */ + uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1; + + /* Set UART Rx and RTS trigger level */ + uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk); + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + + /* Set UART baud rate */ + if(u32baudrate != 0ul) + { + u32BaudDiv = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate); + + if(u32BaudDiv > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32BaudDiv); + } + } +} + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO. + * @param[in] u32ReadBytes The the read bytes number of data. + * + * @return u32Count Receive byte count + * + * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf. + */ +uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0ul; + + while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if(u32Exit == 1ul) + { + break; + } + else + { + pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */ + } + } + + return u32Count; +} + + +/** + * @brief Set UART line configuration + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The register value of baudrate of UART module. + * If u32baudrate = 0, UART baudrate will not change. + * @param[in] u32data_width The data length of UART module. + * - \ref UART_WORD_LEN_5 + * - \ref UART_WORD_LEN_6 + * - \ref UART_WORD_LEN_7 + * - \ref UART_WORD_LEN_8 + * @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module. + * - \ref UART_PARITY_NONE + * - \ref UART_PARITY_ODD + * - \ref UART_PARITY_EVEN + * - \ref UART_PARITY_MARK + * - \ref UART_PARITY_SPACE + * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module. + * - \ref UART_STOP_BIT_1 + * - \ref UART_STOP_BIT_1_5 + * - \ref UART_STOP_BIT_2 + * + * @return None + * + * @details This function use to config UART line setting. + */ +void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint32_t u32UartClkSrcSel, u32UartClkDivNum; + uint32_t au32ClkTbl[8] = { __HXT, 0ul, __LXT, __HIRC, 0ul, 0ul, 0ul, 0ul}; + uint32_t u32BaudDiv = 0ul; + + /* Get UART clock source selection and UART clock divider number */ + switch((uint32_t)uart) + { + case UART0_BASE: + case UART0_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK0Freq(); + break; + case UART1_BASE: + case UART1_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK1Freq(); + break; + case UART2_BASE: + case UART2_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK0Freq(); + break; + case UART3_BASE: + case UART3_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK1Freq(); + break; + case UART4_BASE: + case UART4_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK0Freq(); + break; + case UART5_BASE: + case UART5_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK1Freq(); + break; + default: + return; + } + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + au32ClkTbl[1] = CLK_GetPLLClockFreq(); + } + + /* Set UART baud rate */ + if(u32baudrate != 0ul) + { + u32BaudDiv = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate); + + if(u32BaudDiv > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32BaudDiv); + } + } + + /* Set UART line configuration */ + uart->LINE = u32data_width | u32parity | u32stop_bits; +} + + +/** + * @brief Set Rx timeout count + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32TOC Rx timeout counter. + * + * @return None + * + * @details This function use to set Rx timeout count. + */ +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC) +{ + /* Set time-out interrupt comparator */ + uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC); + + /* Set time-out counter enable */ + uart->INTEN |= UART_INTEN_TOCNTEN_Msk; +} + + +/** + * @brief Select and configure IrDA function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Buadrate The baudrate of UART module. + * @param[in] u32Direction The direction of UART module in IrDA mode: + * - \ref UART_IRDA_TXEN + * - \ref UART_IRDA_RXEN + * + * @return None + * + * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate. + */ +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction) +{ + uint32_t u32UartClkSrcSel = 0UL, u32UartClkDivNum = 1UL; + uint32_t au32ClkTbl[8] = { __HXT, 0ul, __LXT, __HIRC, 0ul, 0ul, 0ul, 0ul}; + uint32_t u32BaudDiv; + + /* Select IrDA function mode */ + uart->FUNCSEL = UART_FUNCSEL_IrDA; + + /* Get UART clock source selection and UART clock divider number */ + switch((uint32_t)uart) + { + case UART0_BASE: + case UART0_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK0Freq(); + break; + case UART1_BASE: + case UART1_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK1Freq(); + break; + case UART2_BASE: + case UART2_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK0Freq(); + break; + case UART3_BASE: + case UART3_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK1Freq(); + break; + case UART4_BASE: + case UART4_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK0Freq(); + break; + case UART5_BASE: + case UART5_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE); + if(u32UartClkSrcSel == 4ul) + au32ClkTbl[4] = CLK_GetPCLK1Freq(); + break; + default: + return; + } + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + au32ClkTbl[1] = CLK_GetPLLClockFreq(); + } + + /* Set UART IrDA baud rate in mode 0 */ + if(u32Buadrate != 0ul) + { + u32BaudDiv = UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate); + + if(u32BaudDiv < 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | u32BaudDiv); + } + } + + /* Configure IrDA relative settings */ + if(u32Direction == UART_IRDA_RXEN) + { + uart->IRDA |= UART_IRDA_RXINV_Msk; /* Rx signal is inverse */ + uart->IRDA &= ~UART_IRDA_TXEN_Msk; + } + else + { + uart->IRDA &= ~UART_IRDA_TXINV_Msk; /* Tx signal is not inverse */ + uart->IRDA |= UART_IRDA_TXEN_Msk; + } + +} + + +/** + * @brief Select and configure RS485 function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The operation mode(NMM/AUD/AAD). + * - \ref UART_ALTCTL_RS485NMM_Msk + * - \ref UART_ALTCTL_RS485AUD_Msk + * - \ref UART_ALTCTL_RS485AAD_Msk + * @param[in] u32Addr The RS485 address. + * + * @return None + * + * @details The function is used to set RS485 relative setting. + */ +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr) +{ + /* Select UART RS485 function mode */ + uart->FUNCSEL = UART_FUNCSEL_RS485; + + /* Set RS585 configuration */ + uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk); + uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos)); +} + + +/** + * @brief Select and configure LIN function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The LIN direction : + * - \ref UART_ALTCTL_LINTXEN_Msk + * - \ref UART_ALTCTL_LINRXEN_Msk + * @param[in] u32BreakLength The breakfield length. + * + * @return None + * + * @details The function is used to set LIN relative setting. + */ +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength) +{ + /* Select LIN function mode */ + uart->FUNCSEL = UART_FUNCSEL_LIN; + + /* Select LIN function setting : Tx enable, Rx enable and break field length */ + uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk); + uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos)); +} + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO. + * @param[out] u32WriteBytes The byte number of data. + * + * @return u32Count transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by UART. + */ +uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0ul; + while( UART_IS_TX_FULL(uart) ) /* Wait Tx not full and Time-out manner */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if(u32Exit == 1ul) + { + break; + } + else + { + uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */ + } + } + + return u32Count; +} + +/** + * @brief Select Single Wire mode function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to select Single Wire mode. + */ +void UART_SelectSingleWireMode(UART_T *uart) +{ + /* Select UART SingleWire function mode */ + uart->FUNCSEL = ((uart->FUNCSEL & (~UART_FUNCSEL_FUNCSEL_Msk)) | UART_FUNCSEL_SINGLE_WIRE); +} + + +/**@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group UART_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_usbd.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_usbd.c new file mode 100644 index 0000000000..c9a88c53ee --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_usbd.c @@ -0,0 +1,780 @@ +/**************************************************************************//** + * @file usbd.c + * @version V3.00 + * @brief M2354 series USBD driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + + +/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions + @{ +*/ + +/* Global variables for Control Pipe */ +uint8_t g_USBD_au8SetupPacket[8] = {0UL}; /*!< Setup packet buffer */ +volatile uint8_t g_USBD_u8RemoteWakeupEn = 0UL; /*!< Remote wake up function enable flag */ + +/** + * @cond HIDDEN_SYMBOLS + */ +static uint8_t *s_USBD_pu8CtrlInPointer = 0; +static uint8_t *s_USBD_pu8CtrlOutPointer = 0; +static volatile uint32_t s_USBD_u32CtrlInSize = 0UL; +static volatile uint32_t s_USBD_u32CtrlOutSize = 0UL; +static volatile uint32_t s_USBD_u32CtrlOutSizeLimit = 0UL; +static volatile uint32_t s_USBD_u32UsbAddr = 0UL; +static volatile uint32_t s_USBD_u32UsbConfig = 0UL; +static volatile uint32_t s_USBD_u32CtrlMaxPktSize = 8UL; +static volatile uint32_t s_USBD_u32UsbAltInterface = 0UL; +static volatile uint8_t s_USBD_u8CtrlInZeroFlag = 0UL; +/** + * @endcond + */ + +const S_USBD_INFO_T *g_USBD_sInfo; /*!< A pointer for USB information structure */ + +VENDOR_REQ g_USBD_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */ +CLASS_REQ g_USBD_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */ +SET_INTERFACE_REQ g_USBD_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */ +SET_CONFIG_CB g_USBD_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */ +uint32_t g_USBD_u32EpStallLock = 0UL; /*!< Bit map flag to lock specified EP when SET_FEATURE */ + +/** + * @brief This function makes USBD module to be ready to use + * + * @param[in] param The structure of USBD information. + * @param[in] pfnClassReq USB Class request callback function. + * @param[in] pfnSetInterface USB Set Interface request callback function. + * + * @return None + * + * @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus. + */ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface) +{ + USBD_T *pUSBD; + + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + g_USBD_sInfo = param; + g_USBD_pfnClassRequest = pfnClassReq; + g_USBD_pfnSetInterface = pfnSetInterface; + + /* get EP0 maximum packet size */ + s_USBD_u32CtrlMaxPktSize = g_USBD_sInfo->gu8DevDesc[7]; + + /* Initial USB engine */ +#ifdef SUPPORT_LPM + pUSBD->ATTR = 0x7D0UL | USBD_LPMACK; +#else + pUSBD->ATTR = 0x7D0UL; +#endif + /* Force SE0 */ + USBD_SET_SE0(); +} + +/** + * @brief This function makes USB host to recognize the device + * + * @param None + * + * @return None + * + * @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer. + */ +void USBD_Start(void) +{ + /* Disable software-disconnect function */ + USBD_CLR_SE0(); + + /* Clear USB-related interrupts before enable interrupt */ + USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); + + /* Enable USB-related interrupts. */ + USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); +} + +/** + * @brief Get the received SETUP packet + * + * @param[in] buf A buffer pointer used to store 8-byte SETUP packet. + * + * @return None + * + * @details Store SETUP packet to a user-specified buffer. + * + */ +void USBD_GetSetupPacket(uint8_t *buf) +{ + USBD_MemCopy(buf, g_USBD_au8SetupPacket, 8UL); +} + +/** + * @brief Process SETUP packet + * + * @param None + * + * @return None + * + * @details Parse SETUP packet and perform the corresponding action. + * + */ +void USBD_ProcessSetupPacket(void) +{ + /* Get SETUP packet from USB buffer */ + USBD_MemCopy(g_USBD_au8SetupPacket, (uint8_t *)USBD_BUF_BASE, 8UL); + + /* Check the request type */ + switch(g_USBD_au8SetupPacket[0] & 0x60UL) + { + case REQ_STANDARD: /* Standard */ + { + USBD_StandardRequest(); + break; + } + case REQ_CLASS: /* Class */ + { + if(g_USBD_pfnClassRequest != NULL) + { + g_USBD_pfnClassRequest(); + } + break; + } + case REQ_VENDOR: /* Vendor */ + { + if(g_USBD_pfnVendorRequest != NULL) + { + g_USBD_pfnVendorRequest(); + } + break; + } + default: /* reserved */ + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } +} + +/** + * @brief Process GetDescriptor request + * + * @param None + * + * @return None + * + * @details Parse GetDescriptor request and perform the corresponding action. + * + */ +void USBD_GetDescriptor(void) +{ + uint32_t u32Len; + + s_USBD_u8CtrlInZeroFlag = (uint8_t)0UL; + u32Len = 0UL; + u32Len = g_USBD_au8SetupPacket[7]; + u32Len <<= 8UL; + u32Len += g_USBD_au8SetupPacket[6]; + + switch(g_USBD_au8SetupPacket[3]) + { + /* Get Device Descriptor */ + case DESC_DEVICE: + { + u32Len = USBD_Minimum(u32Len, (uint32_t)LEN_DEVICE); + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8DevDesc, u32Len); + break; + } + /* Get Configuration Descriptor */ + case DESC_CONFIG: + { + uint32_t u32TotalLen; + + u32TotalLen = g_USBD_sInfo->gu8ConfigDesc[3]; + u32TotalLen = g_USBD_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8UL); + + if(u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if((u32Len % s_USBD_u32CtrlMaxPktSize) == 0UL) + { + s_USBD_u8CtrlInZeroFlag = (uint8_t)1UL; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8ConfigDesc, u32Len); + break; + } + /* Get BOS Descriptor */ + case DESC_BOS: + { + if(g_USBD_sInfo->gu8BosDesc == 0) + { + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + } + else + { + u32Len = USBD_Minimum(u32Len, LEN_BOS + LEN_BOSCAP); + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8BosDesc, u32Len); + } + break; + } + /* Get HID Descriptor */ + case DESC_HID: + { + /* CV3.0 HID Class Descriptor Test, + Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */ + uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */ + u32Len = USBD_Minimum(u32Len, LEN_HID); + u32ConfigDescOffset = g_USBD_sInfo->gu32ConfigHidDescIdx[g_USBD_au8SetupPacket[4]]; + USBD_PrepareCtrlIn((uint8_t *)&g_USBD_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len); + break; + } + /* Get Report Descriptor */ + case DESC_HID_RPT: + { + if(u32Len > g_USBD_sInfo->gu32HidReportSize[g_USBD_au8SetupPacket[4]]) + { + u32Len = g_USBD_sInfo->gu32HidReportSize[g_USBD_au8SetupPacket[4]]; + if((u32Len % s_USBD_u32CtrlMaxPktSize) == 0UL) + { + s_USBD_u8CtrlInZeroFlag = (uint8_t)1UL; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8HidReportDesc[g_USBD_au8SetupPacket[4]], u32Len); + break; + } + /* Get String Descriptor */ + case DESC_STRING: + { + /* Get String Descriptor */ + if(g_USBD_au8SetupPacket[2] < 4UL) + { + if(u32Len > g_USBD_sInfo->gu8StringDesc[g_USBD_au8SetupPacket[2]][0]) + { + u32Len = g_USBD_sInfo->gu8StringDesc[g_USBD_au8SetupPacket[2]][0]; + if((u32Len % s_USBD_u32CtrlMaxPktSize) == 0UL) + { + s_USBD_u8CtrlInZeroFlag = (uint8_t)1UL; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8StringDesc[g_USBD_au8SetupPacket[2]], u32Len); + break; + } + else + { + /* Not support. Reply STALL. */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + default: + /* Not support. Reply STALL. */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } +} + +/** + * @brief Process standard request + * + * @param None + * + * @return None + * + * @details Parse standard request and perform the corresponding action. + * + */ +void USBD_StandardRequest(void) +{ + uint32_t u32Addr; + USBD_T *pUSBD; + OTG_T *pOTG; + + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + pOTG = OTG_NS; + } + else + { + pUSBD = USBD; + pOTG = OTG; + } + + /* clear global variables for new request */ + s_USBD_pu8CtrlInPointer = 0; + s_USBD_u32CtrlInSize = 0UL; + + if((g_USBD_au8SetupPacket[0] & 0x80UL) == 0x80UL) /* request data transfer direction */ + { + /* Device to host */ + switch(g_USBD_au8SetupPacket[1]) + { + case GET_CONFIGURATION: + { + /* Return current configuration setting */ + /* Data stage */ + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(u32Addr) = (uint8_t)s_USBD_u32UsbConfig; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1UL); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0UL); + break; + } + case GET_DESCRIPTOR: + { + USBD_GetDescriptor(); + USBD_PrepareCtrlOut(0, 0UL); /* For status stage */ + break; + } + case GET_INTERFACE: + { + /* Return current interface setting */ + /* Data stage */ + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(u32Addr) = (uint8_t)s_USBD_u32UsbAltInterface; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1UL); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0UL); + break; + } + case GET_STATUS: + { + /* Device */ + if(g_USBD_au8SetupPacket[0] == 0x80UL) + { + uint8_t u8Tmp; + + u8Tmp = (uint8_t)0UL; + if((g_USBD_sInfo->gu8ConfigDesc[7] & 0x40UL) == 0x40UL) + { + u8Tmp |= (uint8_t)1UL; /* Self-Powered/Bus-Powered. */ + } + if((g_USBD_sInfo->gu8ConfigDesc[7] & 0x20UL) == 0x20UL) + { + u8Tmp |= (uint8_t)(g_USBD_u8RemoteWakeupEn << 1UL); /* Remote wake up */ + } + + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(u32Addr) = u8Tmp; + + } + /* Interface */ + else if(g_USBD_au8SetupPacket[0] == 0x81UL) + { + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(u32Addr) = (uint8_t)0UL; + } + /* Endpoint */ + else if(g_USBD_au8SetupPacket[0] == 0x82UL) + { + uint8_t ep = (uint8_t)(g_USBD_au8SetupPacket[4] & 0xFUL); + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(u32Addr) = (uint8_t)(USBD_GetStall(ep) ? 1UL : 0UL); + } + + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1UL; + M8(u32Addr) = (uint8_t)0UL; + /* Data stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 2UL); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0UL); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } + else + { + /* Host to device */ + switch(g_USBD_au8SetupPacket[1]) + { + case CLEAR_FEATURE: + { + if(g_USBD_au8SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + uint32_t epNum, i; + + /* EP number stall is not allow to be clear in MSC class "Error Recovery Test". + a flag: g_USBD_u32EpStallLock is added to support it */ + epNum = (uint8_t)(g_USBD_au8SetupPacket[4] & 0xFUL); + for(i = 0UL; i < USBD_MAX_EP; i++) + { + if(((pUSBD->EP[i].CFG & 0xFUL) == epNum) && ((g_USBD_u32EpStallLock & (1UL << i)) == 0UL)) + { + pUSBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk; + pUSBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + } + } + } + else if(g_USBD_au8SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_USBD_u8RemoteWakeupEn = (uint8_t)0UL; + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0UL); + break; + } + case SET_ADDRESS: + { + s_USBD_u32UsbAddr = g_USBD_au8SetupPacket[2]; + + /* DATA IN for end of setup */ + /* Status Stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0UL); + break; + } + case SET_CONFIGURATION: + { + s_USBD_u32UsbConfig = g_USBD_au8SetupPacket[2]; + + if(g_USBD_pfnSetConfigCallback) + { + g_USBD_pfnSetConfigCallback(); + } + + /* DATA IN for end of setup */ + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0UL); + break; + } + case SET_FEATURE: + { + if((g_USBD_au8SetupPacket[0] & 0xFUL) == 0UL) /* 0: device */ + { + if((g_USBD_au8SetupPacket[2] == 3UL) && (g_USBD_au8SetupPacket[3] == 0UL)) /* 3: HNP enable */ + { + pOTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk); + } + } + if(g_USBD_au8SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + USBD_SetStall((uint8_t)(g_USBD_au8SetupPacket[4] & 0xFUL)); + } + else if(g_USBD_au8SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_USBD_u8RemoteWakeupEn = (uint8_t)1UL; + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0UL); + break; + } + case SET_INTERFACE: + { + s_USBD_u32UsbAltInterface = g_USBD_au8SetupPacket[2]; + if(g_USBD_pfnSetInterface != NULL) + { + g_USBD_pfnSetInterface(s_USBD_u32UsbAltInterface); + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0UL); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } +} + +/** + * @brief Prepare the first Control IN pipe + * + * @param[in] pu8Buf The pointer of data sent to USB host. + * @param[in] u32Size The IN transfer size. + * + * @return None + * + * @details Prepare data for Control IN transfer. + * + */ +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size) +{ + uint32_t u32Addr; + + if(u32Size > s_USBD_u32CtrlMaxPktSize) + { + /* Data size > MXPLD */ + s_USBD_pu8CtrlInPointer = pu8Buf + s_USBD_u32CtrlMaxPktSize; + s_USBD_u32CtrlInSize = u32Size - s_USBD_u32CtrlMaxPktSize; + USBD_SET_DATA1(EP0); + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)u32Addr, pu8Buf, s_USBD_u32CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, s_USBD_u32CtrlMaxPktSize); + } + else + { + /* Data size <= MXPLD */ + s_USBD_pu8CtrlInPointer = 0; + s_USBD_u32CtrlInSize = 0UL; + USBD_SET_DATA1(EP0); + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)u32Addr, pu8Buf, u32Size); + USBD_SET_PAYLOAD_LEN(EP0, u32Size); + } +} + +/** + * @brief Repeat Control IN pipe + * + * @param None + * + * @return None + * + * @details This function processes the remained data of Control IN transfer. + * + */ +void USBD_CtrlIn(void) +{ + uint32_t u32Addr; + + if(s_USBD_u32CtrlInSize) + { + /* Process remained data */ + if(s_USBD_u32CtrlInSize > s_USBD_u32CtrlMaxPktSize) + { + /* Data size > MXPLD */ + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)u32Addr, (uint8_t *)s_USBD_pu8CtrlInPointer, s_USBD_u32CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, s_USBD_u32CtrlMaxPktSize); + s_USBD_pu8CtrlInPointer += s_USBD_u32CtrlMaxPktSize; + s_USBD_u32CtrlInSize -= s_USBD_u32CtrlMaxPktSize; + } + else + { + /* Data size <= MXPLD */ + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)u32Addr, (uint8_t *)s_USBD_pu8CtrlInPointer, s_USBD_u32CtrlInSize); + USBD_SET_PAYLOAD_LEN(EP0, s_USBD_u32CtrlInSize); + s_USBD_pu8CtrlInPointer = 0; + s_USBD_u32CtrlInSize = 0UL; + } + } + else /* No more data for IN token */ + { + /* In ACK for Set address */ + if((g_USBD_au8SetupPacket[0] == REQ_STANDARD) && (g_USBD_au8SetupPacket[1] == SET_ADDRESS)) + { + u32Addr = USBD_GET_ADDR(); + if((u32Addr != s_USBD_u32UsbAddr) && (u32Addr == 0UL)) + { + USBD_SET_ADDR(s_USBD_u32UsbAddr); + } + } + + /* For the case of data size is integral times maximum packet size */ + if(s_USBD_u8CtrlInZeroFlag) + { + USBD_SET_PAYLOAD_LEN(EP0, 0UL); + s_USBD_u8CtrlInZeroFlag = (uint8_t)0UL; + } + } +} + +/** + * @brief Prepare the first Control OUT pipe + * + * @param[in] pu8Buf The pointer of data received from USB host. + * @param[in] u32Size The OUT transfer size. + * + * @return None + * + * @details This function is used to prepare the first Control OUT transfer. + * + */ +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size) +{ + s_USBD_pu8CtrlOutPointer = pu8Buf; + s_USBD_u32CtrlOutSize = 0UL; + s_USBD_u32CtrlOutSizeLimit = u32Size; + USBD_SET_PAYLOAD_LEN(EP1, s_USBD_u32CtrlMaxPktSize); +} + +/** + * @brief Repeat Control OUT pipe + * + * @param None + * + * @return None + * + * @details This function processes the successive Control OUT transfer. + * + */ +void USBD_CtrlOut(void) +{ + uint32_t u32Size; + uint32_t u32Addr; + + if(s_USBD_u32CtrlOutSize < s_USBD_u32CtrlOutSizeLimit) + { + u32Size = USBD_GET_PAYLOAD_LEN(EP1); + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1); + USBD_MemCopy((uint8_t *)s_USBD_pu8CtrlOutPointer, (uint8_t *)u32Addr, u32Size); + s_USBD_pu8CtrlOutPointer += u32Size; + s_USBD_u32CtrlOutSize += u32Size; + + if(s_USBD_u32CtrlOutSize < s_USBD_u32CtrlOutSizeLimit) + { + USBD_SET_PAYLOAD_LEN(EP1, s_USBD_u32CtrlMaxPktSize); + } + } +} + +/** + * @brief Reset software flags + * + * @param None + * + * @return None + * + * @details This function resets all variables for protocol and resets USB device address to 0. + * + */ +void USBD_SwReset(void) +{ + uint32_t i, u32CFG; + USBD_T *pUSBD; + + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + /* Reset all variables for protocol */ + s_USBD_pu8CtrlInPointer = 0; + s_USBD_u32CtrlInSize = 0UL; + s_USBD_pu8CtrlOutPointer = 0; + s_USBD_u32CtrlOutSize = 0UL; + s_USBD_u32CtrlOutSizeLimit = 0UL; + g_USBD_u32EpStallLock = 0UL; + memset(g_USBD_au8SetupPacket, 0, 8UL); + + for(i = 0UL; i < USBD_MAX_EP; i++) + { + if(!USBD_IS_DB_MODE(i)) + { + /* Reset PID DATA0 */ + pUSBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + } + else + { + /* Reset double buffer setting */ + u32CFG = pUSBD->EP[i].CFG; + pUSBD->EP[i].CFG = u32CFG; + } + } + + /* Reset USB device address */ + USBD_SET_ADDR(0UL); +} + +/** + * @brief USBD Set Vendor Request + * + * @param[in] pfnVendorReq Vendor Request Callback Function + * + * @return None + * + * @details This function is used to set USBD vendor request callback function + */ +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq) +{ + g_USBD_pfnVendorRequest = pfnVendorReq; +} + +/** + * @brief The callback function which called when get SET CONFIGURATION request + * + * @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request + * + * @return None + * + * @details This function is used to set the callback function which will be called at SET CONFIGURATION request. + */ +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback) +{ + g_USBD_pfnSetConfigCallback = pfnSetConfigCallback; +} + + +/** + * @brief EP stall lock function to avoid stall clear by USB SET FEATURE request. + * + * @param[in] u32EpBitmap Use bitmap to select which endpoints will be locked + * + * @return None + * + * @details This function is used to lock relative endpoint to avoid stall clear by SET FEATURE request. + * If ep stall locked, user needs to reset USB device or re-configure device to clear it. + */ +void USBD_LockEpStall(uint32_t u32EpBitmap) +{ + g_USBD_u32EpStallLock = u32EpBitmap; +} + +/**@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group USBD_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_usci_i2c.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_usci_i2c.c new file mode 100644 index 0000000000..505c723e9c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_usci_i2c.c @@ -0,0 +1,1661 @@ +/****************************************************************************//** + * @file usci_i2c.c + * @version V3.00 + * $Revision: 1 $ + * $Date: 16/07/07 7:50p $ + * @brief M2355 series USCI I2C(UI2C) driver source file + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This function makes USCI_I2C module be ready and set the wanted bus clock + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Enable USCI_I2C module and configure USCI_I2C module(bus clock, data format). + */ +uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if((ui2c == UI2C1) || (ui2c == UI2C1_NS)) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32ClkDiv = (uint32_t)((((((u32Pclk / 2u) * 10u) / (u32BusClock)) + 5u) / 10u) - 1u); /* Compute proper divider for USCI_I2C clock */ + + /* Enable USCI_I2C protocol */ + ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk; + ui2c->CTL = 4u << UI2C_CTL_FUNMODE_Pos; + + /* Data format configuration */ + /* 8 bit data length */ + ui2c->LINECTL &= ~UI2C_LINECTL_DWIDTH_Msk; + ui2c->LINECTL |= 8u << UI2C_LINECTL_DWIDTH_Pos; + + /* MSB data format */ + ui2c->LINECTL &= ~UI2C_LINECTL_LSB_Msk; + + /* Set USCI_I2C bus clock */ + ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + ui2c->PROTCTL |= UI2C_PROTCTL_PROTEN_Msk; + + return (u32Pclk / ((u32ClkDiv + 1u) << 1u)); +} + +/** + * @brief This function closes the USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Close USCI_I2C protocol function. + */ +void UI2C_Close(UI2C_T *ui2c) +{ + /* Disable USCI_I2C function */ + ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk; +} + +/** + * @brief This function clears the time-out flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Clear time-out flag when time-out flag is set. + */ +void UI2C_ClearTimeoutFlag(UI2C_T *ui2c) +{ + ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk; +} + +/** + * @brief This function sets the control bit of the USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Start Set START bit to USCI_I2C module. + * @param[in] u8Stop Set STOP bit to USCI_I2C module. + * @param[in] u8Ptrg Set PTRG bit to USCI_I2C module. + * @param[in] u8Ack Set ACK bit to USCI_I2C module. + * + * @return None + * + * @details The function set USCI_I2C control bit of USCI_I2C bus protocol. + */ +void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack) +{ + uint32_t u32Reg = 0u; + uint32_t u32Val = ui2c->PROTCTL & ~(UI2C_PROTCTL_STA_Msk | UI2C_PROTCTL_STO_Msk | UI2C_PROTCTL_AA_Msk); + + if(u8Start) + { + u32Reg |= UI2C_PROTCTL_STA_Msk; + } + if(u8Stop) + { + u32Reg |= UI2C_PROTCTL_STO_Msk; + } + if(u8Ptrg) + { + u32Reg |= UI2C_PROTCTL_PTRG_Msk; + } + if(u8Ack) + { + u32Reg |= UI2C_PROTCTL_AA_Msk; + } + ui2c->PROTCTL = u32Val | u32Reg; +} + +/** + * @brief This function disables the interrupt of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to an interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details The function is used to disable USCI_I2C bus interrupt events. + */ +void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Disable time-out interrupt flag */ + if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_TOIEN_Msk; + } + /* Disable start condition received interrupt flag */ + if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_STARIEN_Msk; + } + /* Disable stop condition received interrupt flag */ + if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_STORIEN_Msk; + } + /* Disable non-acknowledge interrupt flag */ + if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_NACKIEN_Msk; + } + /* Disable arbitration lost interrupt flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ARBLOIEN_Msk; + } + + /* Disable error interrupt flag */ + if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ERRIEN_Msk; + } + /* Disable acknowledge interrupt flag */ + if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function enables the interrupt of USCI_I2C module. + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * @return None + * + * @details The function is used to enable USCI_I2C bus interrupt events. + */ +void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Enable time-out interrupt flag */ + if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_TOIEN_Msk; + } + /* Enable start condition received interrupt flag */ + if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_STARIEN_Msk; + } + /* Enable stop condition received interrupt flag */ + if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_STORIEN_Msk; + } + /* Enable non-acknowledge interrupt flag */ + if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_NACKIEN_Msk; + } + /* Enable arbitration lost interrupt flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ARBLOIEN_Msk; + } + /* Enable error interrupt flag */ + if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ERRIEN_Msk; + } + /* Enable acknowledge interrupt flag */ + if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function returns the real bus clock of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details The function returns the actual USCI_I2C module bus clock. + */ +uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c) +{ + uint32_t u32Divider; + uint32_t u32Pclk; + + if((ui2c == UI2C1) || (ui2c == UI2C1_NS)) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + u32Divider = (ui2c->BRGEN & UI2C_BRGEN_CLKDIV_Msk) >> UI2C_BRGEN_CLKDIV_Pos; + + return (u32Pclk / ((u32Divider + 1u) << 1u)); +} + +/** + * @brief This function sets bus clock frequency of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Use this function set USCI_I2C bus clock frequency and return actual bus clock. + */ +uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if((ui2c == UI2C1) || (ui2c == UI2C1_NS)) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + u32ClkDiv = (uint32_t)((((((u32Pclk / 2u) * 10u) / (u32BusClock)) + 5u) / 10u) - 1u); /* Compute proper divider for USCI_I2C clock */ + + /* Set USCI_I2C bus clock */ + ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + + return (u32Pclk / ((u32ClkDiv + 1u) << 1u)); +} + +/** + * @brief This function gets the interrupt flag of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details Use this function to get USCI_I2C interrupt flag when module occurs interrupt event. + */ +uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U; + uint32_t u32TmpValue; + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_TOIF_Msk; + /* Check Time-out Interrupt Flag */ + if((u32Mask & UI2C_TO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_TO_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STARIF_Msk; + /* Check Start Condition Received Interrupt Flag */ + if((u32Mask & UI2C_STAR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STAR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STORIF_Msk; + /* Check Stop Condition Received Interrupt Flag */ + if((u32Mask & UI2C_STOR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STOR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_NACKIF_Msk; + /* Check Non-Acknowledge Interrupt Flag */ + if((u32Mask & UI2C_NACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_NACK_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ARBLOIF_Msk; + /* Check Arbitration Lost Interrupt Flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ARBLO_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ERRIF_Msk; + /* Check Error Interrupt Flag */ + if((u32Mask & UI2C_ERR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ERR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ACKIF_Msk; + /* Check Acknowledge Interrupt Flag */ + if((u32Mask & UI2C_ACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ACK_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief This function clears the interrupt flag of USCI_I2C module. + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details Use this function to clear USCI_I2C interrupt flag when module occurs interrupt event and set flag. + */ +void UI2C_ClearIntFlag(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Clear Time-out Interrupt Flag */ + if(u32Mask & UI2C_TO_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk; + } + /* Clear Start Condition Received Interrupt Flag */ + if(u32Mask & UI2C_STAR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_STARIF_Msk; + } + /* Clear Stop Condition Received Interrupt Flag */ + if(u32Mask & UI2C_STOR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_STORIF_Msk; + } + /* Clear Non-Acknowledge Interrupt Flag */ + if(u32Mask & UI2C_NACK_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_NACKIF_Msk; + } + /* Clear Arbitration Lost Interrupt Flag */ + if(u32Mask & UI2C_ARBLO_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ARBLOIF_Msk; + } + /* Clear Error Interrupt Flag */ + if(u32Mask & UI2C_ERR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ERRIF_Msk; + } + /* Clear Acknowledge Interrupt Flag */ + if(u32Mask & UI2C_ACK_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ACKIF_Msk; + } +} + +/** + * @brief This function returns the data stored in data register of USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return USCI_I2C data. + * + * @details To read a byte data from USCI_I2C module receive data register. + */ +uint32_t UI2C_GetData(UI2C_T *ui2c) +{ + return (ui2c->RXDAT); +} + +/** + * @brief This function writes a byte data to data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details To write a byte data to transmit data register to transmit data. + */ +void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data) +{ + ui2c->TXDAT = u8Data; +} + +/** + * @brief Configure slave address and enable GC mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channel number [0/1] + * @param[in] u16SlaveAddr The slave address. + * @param[in] u8GCMode GC mode enable or not. Valid values are: + * - \ref UI2C_GCMODE_ENABLE + * - \ref UI2C_GCMODE_DISABLE + * + * @return None + * + * @details To configure USCI_I2C module slave address and GC mode. + */ +void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode) +{ + if(u8SlaveNo) + { + ui2c->DEVADDR1 = u16SlaveAddr; + } + else + { + ui2c->DEVADDR0 = u16SlaveAddr; + } + ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_GCFUNC_Msk) | u8GCMode; +} + +/** + * @brief Configure the mask bit of slave address. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channle number [0/1] + * @param[in] u16SlaveAddrMask The slave address mask. + * + * @return None + * + * @details To configure USCI_I2C module slave address mask bit. + * @note The corresponding address bit is "Don't Care". + */ +void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask) +{ + if(u8SlaveNo) + { + ui2c->ADDRMSK1 = u16SlaveAddrMask; + } + else + { + ui2c->ADDRMSK0 = u16SlaveAddrMask; + } +} + +/** + * @brief This function enables time-out function and configures timeout counter + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32TimeoutCnt Timeout counter. Valid values are between 0~0x3FF. + * + * @return None + * + * @details To enable USCI_I2C bus time-out function and set time-out counter. + */ +void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt) +{ + ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_TOCNT_Msk) | (u32TimeoutCnt << UI2C_PROTCTL_TOCNT_Pos); + ui2c->BRGEN = (ui2c->BRGEN & ~UI2C_BRGEN_TMCNTSRC_Msk) | UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function disables time-out function + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C bus time-out function. + */ +void UI2C_DisableTimeout(UI2C_T *ui2c) +{ + ui2c->PROTCTL &= ~UI2C_PROTCTL_TOCNT_Msk; + ui2c->BRGEN &= ~UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function enables the wakeup function of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8WakeupMode The wake-up mode selection. Valid values are: + * - \ref UI2C_DATA_TOGGLE_WK + * - \ref UI2C_ADDR_MATCH_WK + * + * @return None + * + * @details To enable USCI_I2C module wake-up function. + */ +void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode) +{ + ui2c->WKCTL = (ui2c->WKCTL & ~UI2C_WKCTL_WKADDREN_Msk) | (u8WakeupMode | UI2C_WKCTL_WKEN_Msk); +} + +/** + * @brief This function disables the wakeup function of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C module wake-up function. + */ +void UI2C_DisableWakeup(UI2C_T *ui2c) +{ + ui2c->WKCTL &= ~UI2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master write a byte data to Slave. + * + */ + +uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U ); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master write multi bytes data to Slave. + * + */ + +uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(u32txLen < u32wLen) + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify a address that data write to in Slave. + * + */ + +uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(u32txLen == 0U) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */ + u32txLen++; + } + else if(u32txLen == 1U) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + u32txLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes write to in Slave. + * + */ + +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + if(u32txLen < u32wLen) + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify two bytes address that data write to in Slave. + * + */ + +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(u32txLen == 0U) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte data address to UI2C_TXDAT */ + u32txLen++; + } + else if(u32txLen == 1U) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u32txLen++; + } + else if(u32txLen == 2U) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + u32txLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data write to in Slave. + * + */ + +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else if(eEvent == MASTER_SEND_DATA) + { + if(u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u8Addr = 0; + } + else + { + if(u32txLen < u32wLen) + { + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master to read a byte data from Slave. + * + */ +uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + eEvent = MASTER_READ_DATA; + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if(eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Err = 1U; + } + else + { + rdata = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if(u8Err) + rdata = 0U; + + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master to read multi data bytes from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if(u32rxLen < (u32rLen - 1U)) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if(eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify a byte address that a data byte read from Slave. + * + * + */ +uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if(eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if(eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if(eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if(eEvent == MASTER_READ_DATA) + { + rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if(u8Err) + rdata = 0U; /* If occurs error, return 0 */ + + return rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes read from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if(eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if(eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if(eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else if(eEvent == MASTER_SEND_H_RD_ADDRESS) + { + /* SLA+R ACK */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if(u32rxLen < u32rLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if(eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address(2 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify two bytes address that a data byte read from Slave. + * + * + */ +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Addr = 1U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if(eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if(eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if(eEvent == MASTER_SEND_DATA) + { + if(u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if(eEvent == MASTER_READ_DATA) + { + rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if(u8Err) + rdata = 0U; /* If occurs error, return 0 */ + + return rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify two bytes address that multi data bytes read from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if(eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x00U); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if(eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, (uint16_t)(u8SlaveAddr << 1U) | 0x01U); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if(eEvent == MASTER_SEND_DATA) + { + if(u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else if(eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if(u32rxLen < u32rLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if(eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + +/**@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group USCI_I2C_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_usci_spi.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_usci_spi.c new file mode 100644 index 0000000000..d67b9b5262 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_usci_spi.c @@ -0,0 +1,636 @@ +/****************************************************************************//** + * @file usci_spi.c + * @version V3.00 + * @brief M2354 series USCI_SPI driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief This function make USCI_SPI module be ready to transfer. + * By default, the USCI_SPI transfer sequence is MSB first, the slave selection + * signal is active low and the automatic slave select function is disabled. In + * Slave mode, the u32BusClock must be NULL and the USCI_SPI clock + * divider setting will be 0. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are: + * - \ref USPI_SLAVE + * - \ref USPI_MASTER + * @param[in] u32SPIMode Decide the transfer timing. Valid values are: + * - \ref USPI_MODE_0 + * - \ref USPI_MODE_1 + * - \ref USPI_MODE_2 + * - \ref USPI_MODE_3 + * @param[in] u32DataWidth The data width of a USCI_SPI transaction. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock in Hz. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv = 0UL; + uint32_t u32Pclk; + uint32_t u32RetValue = 0UL; + + if((uspi == USPI0) || (uspi == USPI0_NS)) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + if(u32BusClock != 0UL) + { + u32ClkDiv = (uint32_t)((((((u32Pclk / 2UL) * 10UL) / (u32BusClock)) + 5UL) / 10UL) - 1UL); /* Compute proper divider for USCI_SPI clock */ + } + + /* Enable USCI_SPI protocol */ + uspi->CTL &= ~USPI_CTL_FUNMODE_Msk; + uspi->CTL = 1UL << USPI_CTL_FUNMODE_Pos; + + /* Data format configuration */ + if(u32DataWidth == 16UL) + { + u32DataWidth = 0UL; + } + uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk; + uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos); + + /* MSB data format */ + uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk; + + /* Set slave selection signal active low */ + if(u32MasterSlave == USPI_MASTER) + { + uspi->LINECTL |= USPI_LINECTL_CTLOINV_Msk; + } + else + { + uspi->CTLIN0 |= USPI_CTLIN0_ININV_Msk; + } + + /* Set operating mode and transfer timing */ + uspi->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk); + uspi->PROTCTL |= (u32MasterSlave | u32SPIMode); + + /* Set USCI_SPI bus clock */ + uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + uspi->PROTCTL |= USPI_PROTCTL_PROTEN_Msk; + + if(u32BusClock != 0UL) + { + u32RetValue = (u32Pclk / ((u32ClkDiv + 1UL) << 1UL)); + } + else + { + u32RetValue = 0UL; + } + + return u32RetValue; +} + +/** + * @brief Disable USCI_SPI function mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_Close(USPI_T *uspi) +{ + uspi->CTL &= ~USPI_CTL_FUNMODE_Msk; +} + +/** + * @brief Clear Rx buffer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearRxBuf(USPI_T *uspi) +{ + uspi->BUFCTL |= USPI_BUFCTL_RXCLR_Msk; +} + +/** + * @brief Clear Tx buffer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearTxBuf(USPI_T *uspi) +{ + uspi->BUFCTL |= USPI_BUFCTL_TXCLR_Msk; +} + +/** + * @brief Disable the automatic slave select function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableAutoSS(USPI_T *uspi) +{ + uspi->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave select function. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32SSPinMask This parameter is not used. + * @param[in] u32ActiveLevel The active level of slave select signal. Valid values are: + * - \ref USPI_SS_ACTIVE_HIGH + * - \ref USPI_SS_ACTIVE_LOW + * @return None + */ +void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + (void)u32SSPinMask; + uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel; + uspi->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk; +} + +/** + * @brief Set the USCI_SPI bus clock. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if((uspi == USPI0) || (uspi == USPI0_NS)) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t)((((((u32Pclk / 2UL) * 10UL) / (u32BusClock)) + 5UL) / 10UL) - 1UL); /* Compute proper divider for USCI_SPI clock */ + + /* Set USCI_SPI bus clock */ + uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + + return (u32Pclk / ((u32ClkDiv + 1UL) << 1UL)); +} + +/** + * @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Actual USCI_SPI bus clock frequency. + */ +uint32_t USPI_GetBusClock(USPI_T *uspi) +{ + uint32_t u32ClkDiv, u32BusClk; + + u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos; + + if((uspi == USPI0) || (uspi == USPI0_NS)) + { + u32BusClk = (CLK_GetPCLK0Freq() / ((u32ClkDiv + 1UL) << 1UL)); + } + else + { + u32BusClk = (CLK_GetPCLK1Freq() / ((u32ClkDiv + 1UL) << 1UL)); + } + + return u32BusClk; +} + +/** + * @brief Enable related interrupts specified by u32Mask parameter. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be enabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask) +{ + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk; + } + + /* Enable slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk; + } + + /* Enable TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + uspi->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + uspi->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk; + } + + /* Enable TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_TXSTIEN_Msk; + } + + /* Enable TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_TXENDIEN_Msk; + } + + /* Enable RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_RXSTIEN_Msk; + } + + /* Enable RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_RXENDIEN_Msk; + } +} + +/** + * @brief Disable related interrupts specified by u32Mask parameter. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask) +{ + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk; + } + + /* Disable slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk; + } + + /* Disable TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk; + } + + /* Disable TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk; + } + + /* Disable TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk; + } + + /* Disable RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk; + } + + /* Disable RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return Interrupt flags of selected sources. + */ +uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask) +{ + uint32_t u32ProtStatus, u32BufStatus; + uint32_t u32IntFlag = 0UL; + + u32ProtStatus = uspi->PROTSTS; + u32BufStatus = uspi->BUFSTS; + + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SSINAIF_Msk)) + { + u32IntFlag |= USPI_SSINACT_INT_MASK; + } + + /* Check slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SSACTIF_Msk)) + { + u32IntFlag |= USPI_SSACT_INT_MASK; + } + + /* Check slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SLVTOIF_Msk)) + { + u32IntFlag |= USPI_SLVTO_INT_MASK; + } + + /* Check slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SLVBEIF_Msk)) + { + u32IntFlag |= USPI_SLVBE_INT_MASK; + } + + /* Check TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) && (u32BufStatus & USPI_BUFSTS_TXUDRIF_Msk)) + { + u32IntFlag |= USPI_TXUDR_INT_MASK; + } + + /* Check RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) && (u32BufStatus & USPI_BUFSTS_RXOVIF_Msk)) + { + u32IntFlag |= USPI_RXOV_INT_MASK; + } + + /* Check TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_TXSTIF_Msk)) + { + u32IntFlag |= USPI_TXST_INT_MASK; + } + + /* Check TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_TXENDIF_Msk)) + { + u32IntFlag |= USPI_TXEND_INT_MASK; + } + + /* Check RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_RXSTIF_Msk)) + { + u32IntFlag |= USPI_RXST_INT_MASK; + } + + /* Check RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_RXENDIF_Msk)) + { + u32IntFlag |= USPI_RXEND_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask) +{ + /* Clear slave selection signal inactive interrupt flag */ + if(u32Mask & USPI_SSINACT_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SSINAIF_Msk; + } + + /* Clear slave selection signal active interrupt flag */ + if(u32Mask & USPI_SSACT_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SSACTIF_Msk; + } + + /* Clear slave time-out interrupt flag */ + if(u32Mask & USPI_SLVTO_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk; + } + + /* Clear slave bit count error interrupt flag */ + if(u32Mask & USPI_SLVBE_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk; + } + + /* Clear TX under run interrupt flag */ + if(u32Mask & USPI_TXUDR_INT_MASK) + { + uspi->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk; + } + + /* Clear RX overrun interrupt flag */ + if(u32Mask & USPI_RXOV_INT_MASK) + { + uspi->BUFSTS = USPI_BUFSTS_RXOVIF_Msk; + } + + /* Clear TX start interrupt flag */ + if(u32Mask & USPI_TXST_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_TXSTIF_Msk; + } + + /* Clear TX end interrupt flag */ + if(u32Mask & USPI_TXEND_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_TXENDIF_Msk; + } + + /* Clear RX start interrupt flag */ + if(u32Mask & USPI_RXST_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_RXSTIF_Msk; + } + + /* Clear RX end interrupt flag */ + if(u32Mask & USPI_RXEND_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_RXENDIF_Msk; + } +} + +/** + * @brief Get USCI_SPI status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref USPI_BUSY_MASK + * - \ref USPI_RX_EMPTY_MASK + * - \ref USPI_RX_FULL_MASK + * - \ref USPI_TX_EMPTY_MASK + * - \ref USPI_TX_FULL_MASK + * - \ref USPI_SSLINE_STS_MASK + * @return Flags of selected sources. + */ +uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask) +{ + uint32_t u32ProtStatus, u32BufStatus; + uint32_t u32Flag = 0UL; + + u32ProtStatus = uspi->PROTSTS; + u32BufStatus = uspi->BUFSTS; + + /* Check busy status */ + if((u32Mask & USPI_BUSY_MASK) && (u32ProtStatus & USPI_PROTSTS_BUSY_Msk)) + { + u32Flag |= USPI_BUSY_MASK; + } + + /* Check RX empty flag */ + if((u32Mask & USPI_RX_EMPTY_MASK) && (u32BufStatus & USPI_BUFSTS_RXEMPTY_Msk)) + { + u32Flag |= USPI_RX_EMPTY_MASK; + } + + /* Check RX full flag */ + if((u32Mask & USPI_RX_FULL_MASK) && (u32BufStatus & USPI_BUFSTS_RXFULL_Msk)) + { + u32Flag |= USPI_RX_FULL_MASK; + } + + /* Check TX empty flag */ + if((u32Mask & USPI_TX_EMPTY_MASK) && (u32BufStatus & USPI_BUFSTS_TXEMPTY_Msk)) + { + u32Flag |= USPI_TX_EMPTY_MASK; + } + + /* Check TX full flag */ + if((u32Mask & USPI_TX_FULL_MASK) && (u32BufStatus & USPI_BUFSTS_TXFULL_Msk)) + { + u32Flag |= USPI_TX_FULL_MASK; + } + + /* Check USCI_SPI_SS line status */ + if((u32Mask & USPI_SSLINE_STS_MASK) && (u32ProtStatus & USPI_PROTSTS_SSLINE_Msk)) + { + u32Flag |= USPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + +/** + * @brief Enable USCI_SPI Wake-up Function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_EnableWakeup(USPI_T *uspi) +{ + uspi->WKCTL |= USPI_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable USCI_SPI Wake-up Function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableWakeup(USPI_T *uspi) +{ + uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk; +} + +/**@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group USCI_SPI_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_usci_uart.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_usci_uart.c new file mode 100644 index 0000000000..4a2cb15120 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_usci_uart.c @@ -0,0 +1,732 @@ +/**************************************************************************//** + * @file usci_uart.c + * @version V3.00 + * @brief M2354 series USCI UART (UUART) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + +/** + * @brief Clear USCI_UART specified interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to clear USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask) +{ + + if(u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_ABRDETIF_Msk; + } + + if(u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */ + { + uuart->PROTSTS = (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk); + } + + if(u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */ + { + uuart->BUFSTS = UUART_BUFSTS_RXOVIF_Msk; + } + + if(u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_TXSTIF_Msk; + } + + if(u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_TXENDIF_Msk; + } + + if(u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_RXSTIF_Msk; + } + + if(u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_RXENDIF_Msk; + } + +} + + +/** + * @brief Get USCI_UART specified interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details The function is used to get USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0ul; + uint32_t u32Tmp1, u32Tmp2; + + /* Check Auto-baud Rate Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_ABRDETIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_ABR_INT_MASK; + } + + /* Check Receive Line Status Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RLS_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk)); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RLS_INT_MASK; + } + + /* Check Receive Buffer Over-run Error Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_BUF_RXOV_INT_MASK); + u32Tmp2 = (uuart->BUFSTS & UUART_BUFSTS_RXOVIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_BUF_RXOV_INT_MASK; + } + + /* Check Transmit Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXST_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXSTIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXST_INT_MASK; + } + + /* Check Transmit End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXEND_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXENDIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXEND_INT_MASK; + } + + /* Check Receive Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXST_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXSTIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXST_INT_MASK; + } + + /* Check Receive End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXEND_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXENDIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXEND_INT_MASK; + } + + return u32IntFlag; +} + + +/** + * @brief Disable USCI_UART function mode + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART function mode. + */ +void UUART_Close(UUART_T* uuart) +{ + uuart->CTL = 0UL; +} + + +/** + * @brief Disable interrupt function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to disabled USCI_UART related interrupts specified by u32Mask parameter. + */ +void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask) +{ + + /* Disable Auto-baud rate interrupt flag */ + if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + uuart->PROTIEN &= ~UUART_PROTIEN_ABRIEN_Msk; + } + + /* Disable receive line status interrupt flag */ + if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + uuart->PROTIEN &= ~UUART_PROTIEN_RLSIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + uuart->BUFCTL &= ~UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Disable TX start interrupt flag */ + if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_TXSTIEN_Msk; + } + + /* Disable TX end interrupt flag */ + if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_TXENDIEN_Msk; + } + + /* Disable RX start interrupt flag */ + if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_RXSTIEN_Msk; + } + + /* Disable RX end interrupt flag */ + if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Enable interrupt function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to enable USCI_UART related interrupts specified by u32Mask parameter.. + */ +void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask) +{ + /* Enable Auto-baud rate interrupt flag */ + if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + uuart->PROTIEN |= UUART_PROTIEN_ABRIEN_Msk; + } + + /* Enable receive line status interrupt flag */ + if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + uuart->PROTIEN |= UUART_PROTIEN_RLSIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + uuart->BUFCTL |= UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Enable TX start interrupt flag */ + if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_TXSTIEN_Msk; + } + + /* Enable TX end interrupt flag */ + if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_TXENDIEN_Msk; + } + + /* Enable RX start interrupt flag */ + if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_RXSTIEN_Msk; + } + + /* Enable RX end interrupt flag */ + if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Open and set USCI_UART function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32baudrate The baud rate of USCI_UART module. + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to enable USCI_UART function and set baud-rate. + */ +uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt; + uint32_t u32Div; + + /* Get PCLK frequency */ + if((uuart == UUART0) || (uuart == UUART0_NS)) + { + u32PCLKFreq = CLK_GetPCLK0Freq(); + } + else + { + u32PCLKFreq = CLK_GetPCLK1Freq(); + } + + /* Calculate baud rate divider */ + u32Div = u32PCLKFreq / u32baudrate; + u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate; + u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div + 1ul)); + + if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul; + + if(u32Div >= 65536ul) + { + + /* Set the smallest baud rate that USCI_UART can generate */ + u32PDSCnt = 0x4ul; + u32MinDSCnt = 0x10ul; + u32MinClkDiv = 0x400ul; + + } + else + { + + u32Tmp = 0x400ul * 0x10ul; + for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) + { + if(u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul; + + u32Div = u32Div / u32PDSCnt; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0ul; + u32MinClkDiv = 0ul; + u32Tmp = 0ul; + + for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + + u32ClkDiv = u32Div / u32DSCnt; + + if(u32ClkDiv > 0x400ul) + { + u32ClkDiv = 0x400ul; + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = u32Tmp + 1ul; + } + else + { + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = ((u32ClkDiv + 1ul) * u32DSCnt) - u32Div; + } + + if(u32Tmp >= u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1ul; + } + else u32Tmp2 = u32Tmp; + + if(u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if(u32Min == 0ul) + { + break; + } + } + } + + } + + /* Enable USCI_UART protocol */ + uuart->CTL &= ~UUART_CTL_FUNMODE_Msk; + uuart->CTL = 2ul << UUART_CTL_FUNMODE_Pos; + + /* Set USCI_UART line configuration */ + uuart->LINECTL = UUART_WORD_LEN_8 | UUART_LINECTL_LSB_Msk; + uuart->DATIN0 = (2ul << UUART_DATIN0_EDGEDET_Pos); /* Set falling edge detection */ + + /* Set USCI_UART baud rate */ + uuart->BRGEN = ((u32MinClkDiv - 1ul) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt - 1ul) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt - 1ul) << UUART_BRGEN_PDSCNT_Pos); + + uuart->PROTCTL |= UUART_PROTCTL_PROTEN_Msk; + + return (u32PCLKFreq / u32PDSCnt / u32MinDSCnt / u32MinClkDiv); +} + + +/** + * @brief Read USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive buffer. + * @param[in] u32ReadBytes The read bytes number of data. + * + * @return Receive byte count + * + * @details The function is used to read Rx data from RX buffer and the data will be stored in pu8RxBuf. + */ +uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0ul; + + while(uuart->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + break; + } + } + + if(u32delayno >= 0x40000000ul) + { + break; + } + + pu8RxBuf[u32Count] = (uint8_t)uuart->RXDAT; /* Get Data from USCI RX */ + } + + return u32Count; + +} + + +/** + * @brief Set USCI_UART line configuration + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32baudrate The register value of baud rate of USCI_UART module. + * If u32baudrate = 0, USCI_UART baud rate will not change. + * @param[in] u32data_width The data length of USCI_UART module. + * - \ref UUART_WORD_LEN_6 + * - \ref UUART_WORD_LEN_7 + * - \ref UUART_WORD_LEN_8 + * - \ref UUART_WORD_LEN_9 + * @param[in] u32parity The parity setting (none/odd/even) of USCI_UART module. + * - \ref UUART_PARITY_NONE + * - \ref UUART_PARITY_ODD + * - \ref UUART_PARITY_EVEN + * @param[in] u32stop_bits The stop bit length (1/2 bit) of USCI_UART module. + * - \ref UUART_STOP_BIT_1 + * - \ref UUART_STOP_BIT_2 + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to config USCI_UART line setting. + */ +uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt; + uint32_t u32Div; + + /* Get PCLK frequency */ + if((uuart == UUART0) || (uuart == UUART0_NS)) + { + u32PCLKFreq = CLK_GetPCLK0Freq(); + } + else /* UUART1 */ + { + u32PCLKFreq = CLK_GetPCLK1Freq(); + } + + if(u32baudrate != 0ul) + { + + /* Calculate baud rate divider */ + u32Div = u32PCLKFreq / u32baudrate; + u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate; + u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div + 1ul)); + + if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul; + + if(u32Div >= 65536ul) + { + + /* Set the smallest baud rate that USCI_UART can generate */ + u32PDSCnt = 0x4ul; + u32MinDSCnt = 0x10ul; + u32MinClkDiv = 0x400ul; + + } + else + { + + u32Tmp = 0x400ul * 0x10ul; + for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) + { + if(u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul; + + u32Div = u32Div / u32PDSCnt; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0ul; + u32MinClkDiv = 0ul; + + for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + u32ClkDiv = u32Div / u32DSCnt; + + if(u32ClkDiv > 0x400ul) + { + u32ClkDiv = 0x400ul; + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = u32Tmp + 1ul; + } + else + { + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = ((u32ClkDiv + 1ul) * u32DSCnt) - u32Div; + } + + if(u32Tmp >= u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1ul; + } + else u32Tmp2 = u32Tmp; + + if(u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if(u32Min == 0ul) + { + break; + } + } + } + + } + + /* Set USCI_UART baud rate */ + uuart->BRGEN = ((u32MinClkDiv - 1ul) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt - 1ul) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt - 1ul) << UUART_BRGEN_PDSCNT_Pos); + } + else + { + u32PDSCnt = ((uuart->BRGEN & UUART_BRGEN_PDSCNT_Msk) >> UUART_BRGEN_PDSCNT_Pos) + 1ul; + u32MinDSCnt = ((uuart->BRGEN & UUART_BRGEN_DSCNT_Msk) >> UUART_BRGEN_DSCNT_Pos) + 1ul; + u32MinClkDiv = ((uuart->BRGEN & UUART_BRGEN_CLKDIV_Msk) >> UUART_BRGEN_CLKDIV_Pos) + 1ul; + } + + /* Set USCI_UART line configuration */ + uuart->LINECTL = (uuart->LINECTL & ~UUART_LINECTL_DWIDTH_Msk) | u32data_width; + uuart->PROTCTL = (uuart->PROTCTL & ~(UUART_PROTCTL_STICKEN_Msk | UUART_PROTCTL_EVENPARITY_Msk | + UUART_PROTCTL_PARITYEN_Msk)) | u32parity; + uuart->PROTCTL = (uuart->PROTCTL & ~UUART_PROTCTL_STOPB_Msk) | u32stop_bits; + + return (u32PCLKFreq / u32PDSCnt / u32MinDSCnt / u32MinClkDiv); +} + + +/** + * @brief Write USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] pu8TxBuf The buffer to send the data to USCI transmission buffer. + * @param[out] u32WriteBytes The byte number of data. + * + * @return Transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by USCI_UART. + */ +uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0ul; + while((uuart->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) == 0ul) /* Wait Tx empty */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + break; + } + } + + if(u32delayno >= 0x40000000ul) + { + break; + } + + uuart->TXDAT = (uint8_t)pu8TxBuf[u32Count]; /* Send USCI_UART Data to buffer */ + } + + return u32Count; +} + + +/** + * @brief Enable USCI_UART Wake-up Function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32WakeupMode The wakeup mode of USCI_UART module. +* - \ref UUART_PROTCTL_DATWKEN_Msk : Data wake-up Mode +* - \ref UUART_PROTCTL_CTSWKEN_Msk : nCTS wake-up Mode + * + * @return None + * + * @details The function is used to enable Wake-up function of USCI_UART. + */ +void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode) +{ + uuart->PROTCTL |= u32WakeupMode; + uuart->WKCTL |= UUART_WKCTL_WKEN_Msk; +} + + +/** + * @brief Disable USCI_UART Wake-up Function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable Wake-up function of USCI_UART. + */ +void UUART_DisableWakeup(UUART_T* uuart) +{ + uuart->PROTCTL &= ~(UUART_PROTCTL_DATWKEN_Msk | UUART_PROTCTL_CTSWKEN_Msk); + uuart->WKCTL &= ~UUART_WKCTL_WKEN_Msk; +} + +/** + * @brief Enable USCI_UART auto flow control + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to enable USCI_UART auto flow control. + */ +void UUART_EnableFlowCtrl(UUART_T* uuart) +{ + /* Set RTS signal is low level active */ + uuart->LINECTL &= ~UUART_LINECTL_CTLOINV_Msk; + + /* Set CTS signal is low level active */ + uuart->CTLIN0 &= ~UUART_CTLIN0_ININV_Msk; + + /* Enable CTS and RTS auto flow control function */ + uuart->PROTCTL |= UUART_PROTCTL_RTSAUTOEN_Msk | UUART_PROTCTL_CTSAUTOEN_Msk; +} + +/** + * @brief Disable USCI_UART auto flow control + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART auto flow control. + */ +void UUART_DisableFlowCtrl(UUART_T* uuart) +{ + /* Disable CTS and RTS auto flow control function */ + uuart->PROTCTL &= ~(UUART_PROTCTL_RTSAUTOEN_Msk | UUART_PROTCTL_CTSAUTOEN_Msk); +} + + + + +/**@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group USCI_UART_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_wdt.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_wdt.c new file mode 100644 index 0000000000..0b2bb87e22 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_wdt.c @@ -0,0 +1,71 @@ +/**************************************************************************//** + * @file wdt.c + * @version V3.00 + * @brief Watchdog Timer(WDT) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Initialize WDT and start counting + * + * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are: + * - \ref WDT_TIMEOUT_2POW4 + * - \ref WDT_TIMEOUT_2POW6 + * - \ref WDT_TIMEOUT_2POW8 + * - \ref WDT_TIMEOUT_2POW10 + * - \ref WDT_TIMEOUT_2POW12 + * - \ref WDT_TIMEOUT_2POW14 + * - \ref WDT_TIMEOUT_2POW16 + * - \ref WDT_TIMEOUT_2POW18 + * - \ref WDT_TIMEOUT_2POW20 + * @param[in] u32ResetDelay Configure WDT time-out reset delay period. Valid values are: + * - \ref WDT_RESET_DELAY_1026CLK + * - \ref WDT_RESET_DELAY_130CLK + * - \ref WDT_RESET_DELAY_18CLK + * - \ref WDT_RESET_DELAY_3CLK + * @param[in] u32EnableReset Enable WDT time-out reset system function. Valid values are TRUE and FALSE. + * @param[in] u32EnableWakeup Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n + * enable or disable WDT time-out reset system or wake-up system. + * @note Please make sure that Register Write-Protection Function has been disabled before using this function. + */ +void WDT_Open(uint32_t u32TimeoutInterval, + uint32_t u32ResetDelay, + uint32_t u32EnableReset, + uint32_t u32EnableWakeup) +{ + WDT->ALTCTL = u32ResetDelay; + + WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk | + (u32EnableReset << WDT_CTL_RSTEN_Pos) | + (u32EnableWakeup << WDT_CTL_WKEN_Pos); + + while((WDT->CTL & WDT_CTL_SYNC_Msk) == WDT_CTL_SYNC_Msk) {} /* Wait enable WDTEN bit completed, it needs 2 * WDT_CLK. */ +} + +/**@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group WDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_wwdt.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_wwdt.c new file mode 100644 index 0000000000..8f3b1fbd7c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/StdDriver/src/m2354_wwdt.c @@ -0,0 +1,68 @@ +/**************************************************************************//** + * @file wwdt.c + * @version V3.00 + * @brief Window Watchdog Timer(WWDT) driver source file + * + * @copyright SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2019-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Open WWDT and start counting + * + * @param[in] u32PreScale Pre-scale setting of WWDT counter. Valid values are: + * - \ref WWDT_PRESCALER_1 + * - \ref WWDT_PRESCALER_2 + * - \ref WWDT_PRESCALER_4 + * - \ref WWDT_PRESCALER_8 + * - \ref WWDT_PRESCALER_16 + * - \ref WWDT_PRESCALER_32 + * - \ref WWDT_PRESCALER_64 + * - \ref WWDT_PRESCALER_128 + * - \ref WWDT_PRESCALER_192 + * - \ref WWDT_PRESCALER_256 + * - \ref WWDT_PRESCALER_384 + * - \ref WWDT_PRESCALER_512 + * - \ref WWDT_PRESCALER_768 + * - \ref WWDT_PRESCALER_1024 + * - \ref WWDT_PRESCALER_1536 + * - \ref WWDT_PRESCALER_2048 + * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F. + * @param[in] u32EnableInt Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value. + * @note Application can call this function only once after boot up. + */ +void WWDT_Open(uint32_t u32PreScale, + uint32_t u32CmpValue, + uint32_t u32EnableInt) +{ + WWDT->CTL = u32PreScale | + (u32CmpValue << WWDT_CTL_CMPDAT_Pos) | + ((u32EnableInt == (uint32_t)TRUE) ? WWDT_CTL_INTEN_Msk : 0UL) | + WWDT_CTL_WWDTEN_Msk; +} + +/**@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/**@}*/ /* end of group WWDT_Driver */ + +/**@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2019-2020 Nuvoton Technology Corp. ***/ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/TOOLCHAIN_ARMC6/M2354.sct b/targets/TARGET_NUVOTON/TARGET_M2354/device/TOOLCHAIN_ARMC6/M2354.sct new file mode 100644 index 0000000000..1cf085a9da --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/TOOLCHAIN_ARMC6/M2354.sct @@ -0,0 +1,60 @@ +#! armclang --target=arm-arm-none-eabi -march=armv8-m.base -E -xc + +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "../partition_M2354_mem.h" + +#if !defined(MBED_BOOT_STACK_SIZE) +#define MBED_BOOT_STACK_SIZE 0x400 +#endif + +LR_IROM1 MBED_APP_START +{ + /* load address = execution address */ + ER_IROM1 +0 + { + *(RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + + ARM_LIB_STACK MBED_RAM_APP_START EMPTY MBED_BOOT_STACK_SIZE + { + } + + /* Reserve for vectors + * + * Vector table base address is required to be 128-byte aligned at a minimum. + * A PE might impose further restrictions on it. */ + ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 116)) + { + } + + RW_IRAM1 AlignExpr(+0, 16) + { + .ANY (+RW +ZI) + } + + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) + { + } +} + +ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE)) +ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_APP_START + MBED_RAM_APP_SIZE) diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/TOOLCHAIN_GCC_ARM/M2354.ld b/targets/TARGET_NUVOTON/TARGET_M2354/device/TOOLCHAIN_GCC_ARM/M2354.ld new file mode 100644 index 0000000000..51d47e4729 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/TOOLCHAIN_GCC_ARM/M2354.ld @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * Nuvoton M2354 GCC linker script file + */ + +#include "../partition_M2354_mem.h" + +#if !defined(MBED_BOOT_STACK_SIZE) +#define MBED_BOOT_STACK_SIZE 0x400 +#endif + +StackSize = MBED_BOOT_STACK_SIZE; + +MEMORY +{ + VECTORS (rx) : ORIGIN = MBED_APP_START, LENGTH = 0x00000400 + FLASH (rx) : ORIGIN = MBED_APP_START + 0x400, LENGTH = MBED_APP_SIZE - 0x400 + RAM_INTERN (rwx) : ORIGIN = MBED_RAM_APP_START, LENGTH = MBED_RAM_APP_SIZE +} + +/** + * Must match cmsis_nvic.h + */ +__vector_size = 4 * (16 + 116); + + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .isr_vector : + { + __vector_table = .; + KEEP(*(.vector_table)) + . = ALIGN(8); + } > VECTORS + + .copy.table : ALIGN(4) + { + __copy_table_start__ = .; + LONG (LOADADDR(.data)) + LONG (ADDR(.data)) + LONG (SIZEOF(.data)) + __copy_table_end__ = .; + } > FLASH + + .zero.table : ALIGN(4) + { + __zero_table_start__ = .; + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss)) + __zero_table_end__ = .; + } > FLASH + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* Stack Pointer (SP) configuration with GCC_ARM + * + * SP would go through the following configuration sequence: + * (1) SP(MSP) <- Entry 0 of vector table (on H/W reset) + * (2) Switch SP from MSP to PSP in startup file (as TFM requests) + * (3) SP(PSP) <- __stack (in _start(), C/C++ runtime initialization) + * + * S(3) may cause SP(PSP) incorrectly configured. To avoid this error, __stack + * is assigned conditionally according to Secure PSA or not. + */ + + .stack (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . += StackSize; + __StackTop = .; + } > RAM_INTERN + + PROVIDE(__stack = __StackTop); + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + /* Relocate vector table in SRAM */ + .isr_vector.reloc (NOLOAD) : + { + . = ALIGN(1 << LOG2CEIL(__vector_size)); + PROVIDE(__start_vector_table__ = .); + . += __vector_size; + PROVIDE(__end_vector_table__ = .); + } > RAM_INTERN + + .data : + { + PROVIDE( __etext = LOADADDR(.data) ); + + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* All data end */ + . = ALIGN(32); + __data_end__ = .; + + } >RAM_INTERN AT>FLASH + + .bss (NOLOAD): + { + __bss_start__ = .; + *(.bss*) + *(COMMON) + __bss_end__ = .; + } > RAM_INTERN + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + end = __end__; + *(.heap*); + . += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .); + __HeapLimit = .; + } > RAM_INTERN + Image$$ARM_LIB_HEAP$$ZI$$Base = ADDR(.heap); + Image$$ARM_LIB_HEAP$$ZI$$Limit = ADDR(.heap) + SIZEOF(.heap); + + PROVIDE(__heap_size = SIZEOF(.heap)); + PROVIDE(__mbed_sbrk_start = ADDR(.heap)); + PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap)); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/TOOLCHAIN_IAR/M2354.icf b/targets/TARGET_NUVOTON/TARGET_M2354/device/TOOLCHAIN_IAR/M2354.icf new file mode 100644 index 0000000000..8a88004487 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/TOOLCHAIN_IAR/M2354.icf @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ + +include "../partition_M2354_mem.icf.h"; + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x400; +} + +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = MBED_APP_START; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1; +define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START; +define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; +define symbol __ICFEDIT_size_intvec__ = 4 * (16 + 116); +define symbol __ICFEDIT_size_heap__ = 0x400; + +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; +/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */ +define block IRAMVEC with alignment = 1024, size = __ICFEDIT_size_intvec__ { }; + + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem: __ICFEDIT_intvec_start__ { readonly section .intvec }; +place in ROM_region { readonly }; + +place at start of IRAM_region { block CSTACK }; +place in IRAM_region { block IRAMVEC }; +place in IRAM_region { readwrite }; +place in IRAM_region { block HEAP }; diff --git a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramacchannelplan/unittest.cmake b/targets/TARGET_NUVOTON/TARGET_M2354/device/cmsis.h similarity index 52% rename from connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramacchannelplan/unittest.cmake rename to targets/TARGET_NUVOTON/TARGET_M2354/device/cmsis.h index 702e41ea73..1763039219 100644 --- a/connectivity/lorawan/tests/UNITTESTS/features/lorawan/loramacchannelplan/unittest.cmake +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/cmsis.h @@ -1,5 +1,6 @@ -#[[ - * Copyright (c) 2018, Arm Limited and affiliates +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -13,28 +14,25 @@ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. -]] + */ -# Unit test suite name -set(TEST_SUITE_NAME "lorawan_LoRaMacChannelPlan") +#ifndef MBED_CMSIS_H +#define MBED_CMSIS_H -# Source files -set(unittest-sources - ../connectivity/lorawan/lorastack/mac/LoRaMacChannelPlan.cpp -) +#include "M2354.h" +#include "cmsis_nvic.h" +#if TARGET_TFM +#include "partition_M2354.h" +#include "platform_extra_secure.h" +#endif -# Add test specific include paths -set(unittest-includes ${unittest-includes} - target_h - ../connectivity/lorawan/lorastack/mac -) +// Support linker-generated symbol as start of relocated vector table. +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +extern uint32_t Image$$ER_IRAMVEC$$ZI$$Base; +#elif defined(__ICCARM__) -# Test & stub files -set(unittest-test-sources - ${CMAKE_CURRENT_LIST_DIR}/Test_LoRaMacChannelPlan.cpp - stubs/LoRaPHY_stub.cpp -) +#elif defined(__GNUC__) +extern uint32_t __start_vector_table__; +#endif -set(unittest-test-flags - -DMBED_CONF_LORA_TX_MAX_SIZE=255 -) +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/cmsis_nvic.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/cmsis_nvic.h new file mode 100644 index 0000000000..15c50816c9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/cmsis_nvic.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#define NVIC_NUM_VECTORS (16 + 116) + +#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base) +#elif defined(__ICCARM__) +# pragma section = "IRAMVEC" +# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) __section_begin("IRAMVEC")) +#elif defined(__GNUC__) +# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__) +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354.h new file mode 100644 index 0000000000..f778f10e78 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354.h @@ -0,0 +1,29 @@ +/**************************************************************************//** + * @file partition_M2354.h + * @version V3.00 + * @brief TrustZone partition file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ + +#ifndef PARTITION_M2354 +#define PARTITION_M2354 + +#include "partition_M2354_mem.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Since 6.0, Mbed OS doesn't support secure build and target platform code is basically TrustZone-unaware. + * So make this file trivial. */ + +#ifdef __cplusplus +} +#endif + +#endif /* PARTITION_M2354 */ + diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354_mem.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354_mem.h new file mode 100644 index 0000000000..b858b26ec3 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354_mem.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __PARTITION_M2354_MEM_H__ +#define __PARTITION_M2354_MEM_H__ + +/* About partition_M2354_mem.h/partition_M2354_mem.icf.h + * + * 1. partition_M2354_mem.h is created for centralizing memory partition configuration. It will be + * included by C/C++ files and linker files (except IAR linker file). + * 2. IAR linker doesn't support preprocessor, so partition_M2354_mem.icf.h, duplicate of partition_M2354_mem.h + * is created for IAR linker file. + * 3. To continue above, we name partition_M2354_mem.icf.h instead of partition_M2354_mem.icf because: + * (1) Mbed OS build tool may mis-regard partition_M2354_mem.icf as the main linker configuration file. + * (2) *.icf files may not be present in search directories for "include" directive. Per observation, + * the search directories are inconsistent among normal example build and test code build. To address + * it, we name partition_M2354_mem.icf.h instead because *.h files are always present in these builds + * (already there or via copy). + */ + +/* Update NU_TFM_S_BL2 and friends on redoing TF-M import + * + * We expect NU_TFM_S_BL2 and friends are passed along from build tool, esp. Mbed CLI2, + * If not, NU_TFM_S_BL2 and friends must update manually. */ + +#ifndef NU_TFM_S_BL2 +#define NU_TFM_S_BL2 1 +#endif + +#ifndef NU_TFM_S_MCUBOOT_IMAGE_NUMBER +#define NU_TFM_S_MCUBOOT_IMAGE_NUMBER 1 +#endif + +#ifndef NU_TFM_S_REGION_DEFS_H_PATH +#define NU_TFM_S_REGION_DEFS_H_PATH "../TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/partition/region_defs.h" +#endif + +/* TF-M exported region_defs.h depends on BL2 and MCUBOOT_IMAGE_NUMBER, so the + * following order is significant. */ +#if NU_TFM_S_BL2 +#define BL2 +#endif +#define MCUBOOT_IMAGE_NUMBER NU_TFM_S_MCUBOOT_IMAGE_NUMBER +#include NU_TFM_S_REGION_DEFS_H_PATH + +/* Avoid polluting name space, esp. BL2 */ +#undef BL2 +#undef MCUBOOT_IMAGE_NUMBER + +/* Resolve MBED_ROM_START and friends + * + * TF-M exported region_defs.h essentially resolves MBED_ROM_START and friends. + * target.mbed_rom_start and friends get unnecessary. + */ +/* Resolve non-secure ROM start */ +#undef MBED_ROM_START +#define MBED_ROM_START NS_CODE_START + +/* Resolve non-secure ROM size */ +#undef MBED_ROM_SIZE +#define MBED_ROM_SIZE NS_CODE_SIZE + +/* Resolve non-secure RAM start */ +#undef MBED_RAM_START +#define MBED_RAM_START NS_DATA_START + +/* Resolve non-secure RAM size */ +#undef MBED_RAM_SIZE +#define MBED_RAM_SIZE NS_DATA_SIZE + +/* Mbed build tool passes just APPLICATION_xxx macros to C/C++ files and just + * MBED_APP_xxx macros to linker files even though they mean the same thing. + * Because this file is to include by both C/C++ files and linker files, we add + * these macros according to the others for consistency when they are missing + * in compile or link stage. */ + +#ifndef APPLICATION_ADDR +#ifdef MBED_APP_START +#define APPLICATION_ADDR MBED_APP_START +#else +#define APPLICATION_ADDR MBED_ROM_START +#endif +#endif + +#ifndef APPLICATION_SIZE +#ifdef MBED_APP_SIZE +#define APPLICATION_SIZE MBED_APP_SIZE +#else +#define APPLICATION_SIZE MBED_ROM_SIZE +#endif +#endif + +#ifndef APPLICATION_RAM_ADDR +#ifdef MBED_RAM_APP_START +#define APPLICATION_RAM_ADDR MBED_RAM_APP_START +#else +#define APPLICATION_RAM_ADDR MBED_RAM_START +#endif +#endif + +#ifndef APPLICATION_RAM_SIZE +#ifdef MBED_RAM_APP_SIZE +#define APPLICATION_RAM_SIZE MBED_RAM_APP_SIZE +#else +#define APPLICATION_RAM_SIZE MBED_RAM_SIZE +#endif +#endif + +#ifndef MBED_APP_START +#define MBED_APP_START APPLICATION_ADDR +#endif + +#ifndef MBED_APP_SIZE +#define MBED_APP_SIZE APPLICATION_SIZE +#endif + +#ifndef MBED_RAM_APP_START +#define MBED_RAM_APP_START APPLICATION_RAM_ADDR +#endif + +#ifndef MBED_RAM_APP_SIZE +#define MBED_RAM_APP_SIZE APPLICATION_RAM_SIZE +#endif + +#if (APPLICATION_ADDR != MBED_APP_START) +#error("APPLICATION_ADDR and MBED_APP_START are not the same!!!") +#endif + +#if (APPLICATION_SIZE != MBED_APP_SIZE) +#error("APPLICATION_SIZE and MBED_APP_SIZE are not the same!!!") +#endif + +#if (APPLICATION_RAM_ADDR != MBED_RAM_APP_START) +#error("APPLICATION_RAM_ADDR and MBED_RAM_APP_START are not the same!!!") +#endif + +#if (APPLICATION_RAM_SIZE != MBED_RAM_APP_SIZE) +#error("APPLICATION_RAM_SIZE and MBED_RAM_APP_SIZE are not the same!!!") +#endif + +#endif /* __PARTITION_M2354_MEM_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354_mem.icf.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354_mem.icf.h new file mode 100644 index 0000000000..77b66303c6 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/partition_M2354_mem.icf.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* See partition_M2354_mem.h for documentation */ + +/* Update MBED_ROM_START and friends on redoing TF-M import (for IAR) + * + * IAR doesn't support CPP, so we cannot resolve MBED_ROM_START and friends by + * TF-M exported region_defs.h. + * + * Without target.mbed_rom_start and friends (replaced with TF-M exported region_defs.h), + * MBED_ROM_START and friends passed along are incorrect. Because IAR doesn't allow symbol + * redefinition, we change to MBED_ROM_START_ORIDE and friends instead for a temporary + * solution. + */ + +/* Resolve non-secure ROM start */ +define symbol MBED_ROM_START_ORIDE = 0x10070400; + +/* Resolve non-secure ROM size */ +define symbol MBED_ROM_SIZE_ORIDE = 0x8F400; + +/* Resolve non-secure RAM start */ +define symbol MBED_RAM_START_ORIDE = 0x30014000; + +/* Resolve non-secure RAM size */ +define symbol MBED_RAM_SIZE_ORIDE = 0x2C000; + +/* Mbed build tool passes just APPLICATION_xxx macros to C/C++ files and just + * MBED_APP_xxx macros to linker files even though they mean the same thing. + * Because this file is to include by both C/C++ files and linker files, we add + * these macros according to the others for consistency when they are missing + * in compile or link stage. */ + +if (!isdefinedsymbol(APPLICATION_ADDR)) { + if (isdefinedsymbol(MBED_APP_START)) { + define symbol APPLICATION_ADDR = MBED_APP_START; + } else { + define symbol APPLICATION_ADDR = MBED_ROM_START_ORIDE; + } +} + +if (!isdefinedsymbol(APPLICATION_SIZE)) { + if (isdefinedsymbol(MBED_APP_SIZE)) { + define symbol APPLICATION_SIZE = MBED_APP_SIZE; + } else { + define symbol APPLICATION_SIZE = MBED_ROM_SIZE_ORIDE; + } +} + +if (!isdefinedsymbol(APPLICATION_RAM_ADDR)) { + if (isdefinedsymbol(MBED_RAM_APP_START)) { + define symbol APPLICATION_RAM_ADDR = MBED_RAM_APP_START; + } else { + define symbol APPLICATION_RAM_ADDR = MBED_RAM_START_ORIDE; + } +} + +if (!isdefinedsymbol(APPLICATION_RAM_SIZE)) { + if (isdefinedsymbol(MBED_RAM_APP_SIZE)) { + define symbol APPLICATION_RAM_SIZE = MBED_RAM_APP_SIZE; + } else { + define symbol APPLICATION_RAM_SIZE = MBED_RAM_SIZE_ORIDE; + } +} + +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = APPLICATION_ADDR; +} + +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = APPLICATION_SIZE; +} + +if (!isdefinedsymbol(MBED_RAM_APP_START)) { + define symbol MBED_RAM_APP_START = APPLICATION_RAM_ADDR; +} + +if (!isdefinedsymbol(MBED_RAM_APP_SIZE)) { + define symbol MBED_RAM_APP_SIZE = APPLICATION_RAM_SIZE; +} + +if (APPLICATION_ADDR != MBED_APP_START) { + error "APPLICATION_ADDR and MBED_APP_START are not the same!!!"; +} + +if (APPLICATION_SIZE != MBED_APP_SIZE) { + error "APPLICATION_SIZE and MBED_APP_SIZE are not the same!!!"; +} + +if (APPLICATION_RAM_ADDR != MBED_RAM_APP_START) { + error "APPLICATION_RAM_ADDR and MBED_RAM_APP_START are not the same!!!"; +} + +if (APPLICATION_RAM_SIZE != MBED_RAM_APP_SIZE) { + error "APPLICATION_RAM_SIZE and MBED_RAM_APP_SIZE are not the same!!!"; +} diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/startup_M2354.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/startup_M2354.c new file mode 100644 index 0000000000..137cad3c67 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/startup_M2354.c @@ -0,0 +1,475 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined(__GNUC__) + +/* Get around error: conflicting type qualifiers for '__copy_table_start__' + * + * cmsis_gcc.h also imports the following symbols but with different type qualifier: + * + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * + * Define `__PROGRAM_START` to exclude __cmsis_start() in cmsis_gcc.h. + */ +#define __PROGRAM_START + +#endif + +#include "M2354.h" + +/* Suppress warning messages */ +#if defined(__ARMCC_VERSION) +#elif defined(__ICCARM__) +// Suppress warning message Pe1665 +#pragma diag_suppress=Pe1665 +#elif defined(__GNUC__) +#endif + +/* Macro Definitions */ +#if defined(__ARMCC_VERSION) +#define WEAK __attribute__ ((weak)) +#define ALIAS(f) __attribute__ ((weak, alias(#f))) + +#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \ +void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS))); + +#elif defined(__ICCARM__) +//#define STRINGIFY(x) #x +//#define _STRINGIFY(x) STRINGIFY(x) +#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \ +void FUN(void); \ +_Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUN, FUN_ALIAS))) +#define _WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) weak __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) +#define __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) FUN##=##FUN_ALIAS + +#elif defined(__GNUC__) +#define WEAK __attribute__ ((weak)) +#define ALIAS(f) __attribute__ ((weak, alias(#f))) + +#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \ +void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS))); + +#endif + +/* Initialize segments */ +#if defined(__ARMCC_VERSION) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit; +extern void __main(void); +#elif defined(__ICCARM__) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit; +extern uint32_t CSTACK$$Limit; +void __iar_program_start(void); +#elif defined(__GNUC__) +extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit; +extern uint32_t __StackTop; +extern uint32_t __copy_table_start__; +extern uint32_t __copy_table_end__; +extern uint32_t __zero_table_start__; +extern uint32_t __zero_table_end__; + +#if defined(TOOLCHAIN_GCC_ARM) +extern void _start(void); +#else +#error("For GCC toolchain, only support GNU ARM Embedded") +#endif +#endif + +/* Default empty handler */ +void Default_Handler(void); + +/* Reset handler */ +void Reset_Handler(void); + +/* Cortex-M0+ core handlers */ +WEAK_ALIAS_FUNC(NMI_Handler, Default_Handler) +WEAK_ALIAS_FUNC(HardFault_Handler, Default_Handler) +WEAK_ALIAS_FUNC(SVC_Handler, Default_Handler) + +WEAK_ALIAS_FUNC(PendSV_Handler, Default_Handler) +WEAK_ALIAS_FUNC(SysTick_Handler, Default_Handler) + +/* Peripherals handlers */ +WEAK_ALIAS_FUNC(BOD_IRQHandler, Default_Handler) // 0: Brown Out detection +WEAK_ALIAS_FUNC(IRC_IRQHandler, Default_Handler) // 1: Internal RC +WEAK_ALIAS_FUNC(PWRWU_IRQHandler, Default_Handler) // 2: Power down wake up +WEAK_ALIAS_FUNC(SRAM_IRQHandler, Default_Handler) // 3: SRAM +WEAK_ALIAS_FUNC(CLKFAIL_IRQHandler, Default_Handler) // 4: Clock detection fail + // 5: Reserved +WEAK_ALIAS_FUNC(RTC_IRQHandler, Default_Handler) // 6: Real Time Clock +WEAK_ALIAS_FUNC(RTC_TAMPER_IRQHandler, Default_Handler) // 7: RTC Tamper detection +WEAK_ALIAS_FUNC(WDT_IRQHandler, Default_Handler) // 8: Watchdog timer +WEAK_ALIAS_FUNC(WWDT_IRQHandler, Default_Handler) // 9: Window watchdog timer +WEAK_ALIAS_FUNC(EINT0_IRQHandler, Default_Handler) // 10: External Input 0 +WEAK_ALIAS_FUNC(EINT1_IRQHandler, Default_Handler) // 11: External Input 1 +WEAK_ALIAS_FUNC(EINT2_IRQHandler, Default_Handler) // 12: External Input 2 +WEAK_ALIAS_FUNC(EINT3_IRQHandler, Default_Handler) // 13: External Input 3 +WEAK_ALIAS_FUNC(EINT4_IRQHandler, Default_Handler) // 14: External Input 4 +WEAK_ALIAS_FUNC(EINT5_IRQHandler, Default_Handler) // 15: External Input 5 +WEAK_ALIAS_FUNC(GPA_IRQHandler, Default_Handler) // 16: GPIO Port A +WEAK_ALIAS_FUNC(GPB_IRQHandler, Default_Handler) // 17: GPIO Port B +WEAK_ALIAS_FUNC(GPC_IRQHandler, Default_Handler) // 18: GPIO Port C +WEAK_ALIAS_FUNC(GPD_IRQHandler, Default_Handler) // 19: GPIO Port D +WEAK_ALIAS_FUNC(GPE_IRQHandler, Default_Handler) // 20: GPIO Port E +WEAK_ALIAS_FUNC(GPF_IRQHandler, Default_Handler) // 21: GPIO Port F +WEAK_ALIAS_FUNC(QSPI0_IRQHandler, Default_Handler) // 22: QSPI0 +WEAK_ALIAS_FUNC(SPI0_IRQHandler, Default_Handler) // 23: SPI0 +WEAK_ALIAS_FUNC(BRAKE0_IRQHandler, Default_Handler) // 24: BRAKE0 +WEAK_ALIAS_FUNC(EPWM0_P0_IRQHandler, Default_Handler) // 25: EPWM0P0 +WEAK_ALIAS_FUNC(EPWM0_P1_IRQHandler, Default_Handler) // 26: EPWM0P1 +WEAK_ALIAS_FUNC(EPWM0_P2_IRQHandler, Default_Handler) // 27: EPWM0P2 +WEAK_ALIAS_FUNC(BRAKE1_IRQHandler, Default_Handler) // 28: BRAKE1 +WEAK_ALIAS_FUNC(EPWM1_P0_IRQHandler, Default_Handler) // 29: EPWM1P0 +WEAK_ALIAS_FUNC(EPWM1_P1_IRQHandler, Default_Handler) // 30: EPWM1P1 +WEAK_ALIAS_FUNC(EPWM1_P2_IRQHandler, Default_Handler) // 31: EPWM1P2 +WEAK_ALIAS_FUNC(TMR0_IRQHandler, Default_Handler) // 32: Timer 0 +WEAK_ALIAS_FUNC(TMR1_IRQHandler, Default_Handler) // 33: Timer 1 +WEAK_ALIAS_FUNC(TMR2_IRQHandler, Default_Handler) // 34: Timer 2 +WEAK_ALIAS_FUNC(TMR3_IRQHandler, Default_Handler) // 35: Timer 3 +WEAK_ALIAS_FUNC(UART0_IRQHandler, Default_Handler) // 36: UART0 +WEAK_ALIAS_FUNC(UART1_IRQHandler, Default_Handler) // 37: UART1 +WEAK_ALIAS_FUNC(I2C0_IRQHandler, Default_Handler) // 38: I2C0 +WEAK_ALIAS_FUNC(I2C1_IRQHandler, Default_Handler) // 39: I2C1 +WEAK_ALIAS_FUNC(PDMA0_IRQHandler, Default_Handler) // 40: Peripheral DMA 0 +WEAK_ALIAS_FUNC(DAC_IRQHandler, Default_Handler) // 41: DAC +WEAK_ALIAS_FUNC(EADC0_IRQHandler, Default_Handler) // 42: EADC Source 0 +WEAK_ALIAS_FUNC(EADC1_IRQHandler, Default_Handler) // 43: EADC Source 1 +WEAK_ALIAS_FUNC(ACMP01_IRQHandler, Default_Handler) // 44: ACMP0 and ACMP1 + // 45: Reserved +WEAK_ALIAS_FUNC(EADC2_IRQHandler, Default_Handler) // 46: EADC Source 2 +WEAK_ALIAS_FUNC(EADC3_IRQHandler, Default_Handler) // 47: EADC Source 3 +WEAK_ALIAS_FUNC(UART2_IRQHandler, Default_Handler) // 48: UART2 +WEAK_ALIAS_FUNC(UART3_IRQHandler, Default_Handler) // 49: UART3 + // 50: Reserved +WEAK_ALIAS_FUNC(SPI1_IRQHandler, Default_Handler) // 51: SPI1 +WEAK_ALIAS_FUNC(SPI2_IRQHandler, Default_Handler) // 52: SPI2 +WEAK_ALIAS_FUNC(USBD_IRQHandler, Default_Handler) // 53: USB device +WEAK_ALIAS_FUNC(USBH_IRQHandler, Default_Handler) // 54: USB host +WEAK_ALIAS_FUNC(USBOTG_IRQHandler, Default_Handler) // 55: USB OTG +WEAK_ALIAS_FUNC(CAN0_IRQHandler, Default_Handler) // 56: CAN0 + // 57: Reserved +WEAK_ALIAS_FUNC(SC0_IRQHandler, Default_Handler) // 58: +WEAK_ALIAS_FUNC(SC1_IRQHandler, Default_Handler) // 59: +WEAK_ALIAS_FUNC(SC2_IRQHandler, Default_Handler) // 60: + // 61: +WEAK_ALIAS_FUNC(SPI3_IRQHandler, Default_Handler) // 62: + // 63: Reserved +WEAK_ALIAS_FUNC(SDH0_IRQHandler, Default_Handler) // 64: + // 65 ~67: Reserved +WEAK_ALIAS_FUNC(I2S0_IRQHandler, Default_Handler) // 68: + // 69: Reserved +WEAK_ALIAS_FUNC(OPA0_IRQHandler, Default_Handler) // 70: +WEAK_ALIAS_FUNC(CRPT_IRQHandler, Default_Handler) // 71: +WEAK_ALIAS_FUNC(GPG_IRQHandler, Default_Handler) // 72: +WEAK_ALIAS_FUNC(EINT6_IRQHandler, Default_Handler) // 73: +WEAK_ALIAS_FUNC(UART4_IRQHandler, Default_Handler) // 74: +WEAK_ALIAS_FUNC(UART5_IRQHandler, Default_Handler) // 75: +WEAK_ALIAS_FUNC(USCI0_IRQHandler, Default_Handler) // 76: +WEAK_ALIAS_FUNC(USCI1_IRQHandler, Default_Handler) // 77: +WEAK_ALIAS_FUNC(BPWM0_IRQHandler, Default_Handler) // 78: +WEAK_ALIAS_FUNC(BPWM1_IRQHandler, Default_Handler) // 79: + // 80~81: Reserved +WEAK_ALIAS_FUNC(I2C2_IRQHandler, Default_Handler) // 82: + // 83: Reserved +WEAK_ALIAS_FUNC(QEI0_IRQHandler, Default_Handler) // 84: +WEAK_ALIAS_FUNC(QEI1_IRQHandler, Default_Handler) // 85: +WEAK_ALIAS_FUNC(ECAP0_IRQHandler, Default_Handler) // 86: +WEAK_ALIAS_FUNC(ECAP1_IRQHandler, Default_Handler) // 87: +WEAK_ALIAS_FUNC(GPH_IRQHandler, Default_Handler) // 88: +WEAK_ALIAS_FUNC(EINT7_IRQHandler, Default_Handler) // 89: + // 90~97: Reserved +WEAK_ALIAS_FUNC(PDMA1_IRQHandler, Default_Handler) // 98: Peripheral DMA 1 +WEAK_ALIAS_FUNC(SCU_IRQHandler, Default_Handler) // 99: SCU +WEAK_ALIAS_FUNC(LCD_IRQHandler, Default_Handler) // 100: LCD +WEAK_ALIAS_FUNC(TRNG_IRQHandler, Default_Handler) // 101: TRNG + // 102~108: Reserved +WEAK_ALIAS_FUNC(KS_IRQHandler, Default_Handler) // 109 +WEAK_ALIAS_FUNC(TAMPER_IRQHandler, Default_Handler) // 110 +WEAK_ALIAS_FUNC(EWDT_IRQHandler, Default_Handler) // 111 +WEAK_ALIAS_FUNC(EWWDT_IRQHandler, Default_Handler) // 112 +WEAK_ALIAS_FUNC(NS_ISP_IRQHandler, Default_Handler) // 113 +WEAK_ALIAS_FUNC(TMR4_IRQHandler, Default_Handler) // 114 +WEAK_ALIAS_FUNC(TMR5_IRQHandler, Default_Handler) // 115 + +/* Vector table */ +#if defined(__ARMCC_VERSION) +__attribute__ ((section("RESET"), used)) +const uint32_t __vector_handlers[] = { +#elif defined(__ICCARM__) +const uint32_t __vector_table[] @ ".intvec" = { +#elif defined(__GNUC__) +__attribute__ ((section(".vector_table"))) +const uint32_t __vector_handlers[] = { +#endif + + /* Configure Initial Stack Pointer, using linker-generated symbols */ +#if defined(__ARMCC_VERSION) + (uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit, +#elif defined(__ICCARM__) + (uint32_t) &CSTACK$$Limit, +#elif defined(__GNUC__) + (uint32_t) &__StackTop, +#endif + + (uint32_t) Reset_Handler, // Reset Handler + (uint32_t) NMI_Handler, // NMI Handler + (uint32_t) HardFault_Handler, // Hard Fault Handler + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + 0, // Reserved + (uint32_t) SVC_Handler, // SVCall Handler + 0, // Reserved + 0, // Reserved + (uint32_t) PendSV_Handler, // PendSV Handler + (uint32_t) SysTick_Handler, // SysTick Handler + + /* External Interrupts */ + (uint32_t) BOD_IRQHandler, // 0: Brown Out detection + (uint32_t) IRC_IRQHandler, // 1: Internal RC + (uint32_t) PWRWU_IRQHandler, // 2: Power down wake up + (uint32_t) SRAM_IRQHandler, // 3: + (uint32_t) CLKFAIL_IRQHandler, // 4: Clock detection fail + (uint32_t) Default_Handler, // 5: Reserved + (uint32_t) RTC_IRQHandler, // 6: Real Time Clock + (uint32_t) RTC_TAMPER_IRQHandler, // 7: RTC Tamper detection + (uint32_t) WDT_IRQHandler, // 8: Watchdog timer + (uint32_t) WWDT_IRQHandler, // 9: Window watchdog timer + (uint32_t) EINT0_IRQHandler, // 10: External Input 0 + (uint32_t) EINT1_IRQHandler, // 11: External Input 1 + (uint32_t) EINT2_IRQHandler, // 12: External Input 2 + (uint32_t) EINT3_IRQHandler, // 13: External Input 3 + (uint32_t) EINT4_IRQHandler, // 14: External Input 4 + (uint32_t) EINT5_IRQHandler, // 15: External Input 5 + (uint32_t) GPA_IRQHandler, // 16: GPIO Port A + (uint32_t) GPB_IRQHandler, // 17: GPIO Port B + (uint32_t) GPC_IRQHandler, // 18: GPIO Port C + (uint32_t) GPD_IRQHandler, // 19: GPIO Port D + (uint32_t) GPE_IRQHandler, // 20: GPIO Port E + (uint32_t) GPF_IRQHandler, // 21: GPIO Port F + (uint32_t) QSPI0_IRQHandler, // 22: QSPI0 + (uint32_t) SPI0_IRQHandler, // 23: SPI0 + (uint32_t) BRAKE0_IRQHandler, // 24: + (uint32_t) EPWM0_P0_IRQHandler, // 25: + (uint32_t) EPWM0_P1_IRQHandler, // 26: + (uint32_t) EPWM0_P2_IRQHandler, // 27: + (uint32_t) BRAKE1_IRQHandler, // 28: + (uint32_t) EPWM1_P0_IRQHandler, // 29: + (uint32_t) EPWM1_P1_IRQHandler, // 30: + (uint32_t) EPWM1_P2_IRQHandler, // 31: + (uint32_t) TMR0_IRQHandler, // 32: Timer 0 + (uint32_t) TMR1_IRQHandler, // 33: Timer 1 + (uint32_t) TMR2_IRQHandler, // 34: Timer 2 + (uint32_t) TMR3_IRQHandler, // 35: Timer 3 + (uint32_t) UART0_IRQHandler, // 36: UART0 + (uint32_t) UART1_IRQHandler, // 37: UART1 + (uint32_t) I2C0_IRQHandler, // 38: I2C0 + (uint32_t) I2C1_IRQHandler, // 39: I2C1 + (uint32_t) PDMA0_IRQHandler, // 40: Peripheral DMA 0 + (uint32_t) DAC_IRQHandler, // 41: DAC + (uint32_t) EADC0_IRQHandler, // 42: EADC source 0 + (uint32_t) EADC1_IRQHandler, // 43: EADC source 1 + (uint32_t) ACMP01_IRQHandler, // 44: ACMP0 and ACMP1 + (uint32_t) Default_Handler, // 45: Reserved + (uint32_t) EADC2_IRQHandler, // 46: EADC source 2 + (uint32_t) EADC3_IRQHandler, // 47: EADC source 3 + (uint32_t) UART2_IRQHandler, // 48: UART2 + (uint32_t) UART3_IRQHandler, // 49: UART3 + (uint32_t) Default_Handler, // 50: Reserved + (uint32_t) SPI1_IRQHandler, // 51: SPI1 + (uint32_t) SPI2_IRQHandler, // 52: SPI2 + (uint32_t) USBD_IRQHandler, // 53: USB device + (uint32_t) USBH_IRQHandler, // 54: USB host + (uint32_t) USBOTG_IRQHandler, // 55: USB OTG + (uint32_t) CAN0_IRQHandler, // 56: CAN0 + (uint32_t) Default_Handler, // 57: Reserved + (uint32_t) SC0_IRQHandler, // 58: + (uint32_t) SC1_IRQHandler, // 59: + (uint32_t) SC2_IRQHandler, // 60: + (uint32_t) Default_Handler, // 61: Reserved. + (uint32_t) SPI3_IRQHandler, // 62: + (uint32_t) Default_Handler, // 63: + (uint32_t) SDH0_IRQHandler, // 64: + (uint32_t) Default_Handler, // 65: + (uint32_t) Default_Handler, // 66: + (uint32_t) Default_Handler, // 67: + (uint32_t) I2S0_IRQHandler, // 68: + (uint32_t) Default_Handler, // 69: + (uint32_t) OPA0_IRQHandler, // 70: + (uint32_t) CRPT_IRQHandler, // 71: + (uint32_t) GPG_IRQHandler, // 72: + (uint32_t) EINT6_IRQHandler, // 73: + (uint32_t) UART4_IRQHandler, // 74: + (uint32_t) UART5_IRQHandler, // 75: + (uint32_t) USCI0_IRQHandler, // 76: + (uint32_t) USCI1_IRQHandler, // 77: + (uint32_t) BPWM0_IRQHandler, // 78: + (uint32_t) BPWM1_IRQHandler, // 79: + (uint32_t) Default_Handler, // 80: + (uint32_t) Default_Handler, // 81: + (uint32_t) I2C2_IRQHandler, // 82: + (uint32_t) Default_Handler, // 83: + (uint32_t) QEI0_IRQHandler, // 84: + (uint32_t) QEI1_IRQHandler, // 85: + (uint32_t) ECAP0_IRQHandler, // 86: + (uint32_t) ECAP1_IRQHandler, // 87: + (uint32_t) GPH_IRQHandler, // 88: + (uint32_t) EINT7_IRQHandler, // 89: + (uint32_t) Default_Handler, // 90: + (uint32_t) Default_Handler, // 91: + (uint32_t) Default_Handler, // 92: + (uint32_t) Default_Handler, // 93: + (uint32_t) Default_Handler, // 94: + (uint32_t) Default_Handler, // 95: + (uint32_t) Default_Handler, // 96: + (uint32_t) Default_Handler, // 97: + (uint32_t) PDMA1_IRQHandler, // 98: Peripheral DMA 1 + (uint32_t) SCU_IRQHandler, // 99: + (uint32_t) LCD_IRQHandler, // 100: + (uint32_t) TRNG_IRQHandler, // 101: + (uint32_t) Default_Handler, // 102: + (uint32_t) Default_Handler, // 103: + (uint32_t) Default_Handler, // 104: + (uint32_t) Default_Handler, // 105: + (uint32_t) Default_Handler, // 106: + (uint32_t) Default_Handler, // 107: + (uint32_t) Default_Handler, // 108: + (uint32_t) KS_IRQHandler, // 109: + (uint32_t) TAMPER_IRQHandler, // 110: + (uint32_t) EWDT_IRQHandler, // 111: + (uint32_t) EWWDT_IRQHandler, // 112: + (uint32_t) NS_ISP_IRQHandler, // 113: + (uint32_t) TMR4_IRQHandler, // 114: + (uint32_t) TMR5_IRQHandler, // 115: +}; + +/* Some reset handler code cannot implement in pure C. Implement it in inline/embedded assembly. + * + * Reset_Handler: + * For non-secure PSA/non-secure non-PSA/secure non-PSA, jump directly to Reset_Handler_1 + * For secure PSA, switch from MSP to PSP, then jump to Reset_Handler_1 + * + * Reset_Handler_1: + * Platform initialization + * C/C++ runtime initialization + */ + +void Reset_Handler_1(void); + +/* Add '__attribute__((naked))' here to make sure compiler does not generate prologue and + * epilogue sequences for Reset_Handler. We don't want MSP is updated by compiler-generated + * code during stack switch. + * + * Don't allow extended assembly in naked functions: + * The compiler only supports basic __asm statements in __attribute__((naked)) + * functions. Using extended assembly, parameter references or mixing C code with + * __asm statements might not work reliably. + */ +__attribute__((naked)) void Reset_Handler(void) +{ +#if defined(__GNUC__) + __asm(".syntax unified \n"); +#endif + + /* Jump to Reset_Handler_1 */ +#if !defined(__ICCARM__) + __asm("movw r0, #:lower16:Reset_Handler_1 \n"); + __asm("movt r0, #:upper16:Reset_Handler_1 \n"); +#else + __asm("mov32 r0, Reset_Handler_1 \n"); +#endif + __asm("bx r0 \n"); +} + +void Reset_Handler_1(void) +{ + /* SystemInit() must be called at the very start. */ + SystemInit(); + +#if defined(__ARMCC_VERSION) + __main(); + +#elif defined(__ICCARM__) + __iar_program_start(); + +#elif defined(__GNUC__) + /* Move (multiple) .data section(s) from ROM to RAM */ + { + /* Struct of copy table entry which must match linker script */ + typedef struct copy_table_entry_ { + uint32_t src; // Address to copy from + uint32_t dst; // Address to copy to + uint32_t size; // Copy size in bytes + } copy_table_entry; + + copy_table_entry *copy_table_ind = (copy_table_entry *) &__copy_table_start__; + copy_table_entry *copy_table_end = (copy_table_entry *) &__copy_table_end__; + + for (; copy_table_ind != copy_table_end; copy_table_ind ++) { + uint32_t *src_ind = (uint32_t *) copy_table_ind->src; + uint32_t *src_end = (uint32_t *) (copy_table_ind->src + copy_table_ind->size); + uint32_t *dst_ind = (uint32_t *) copy_table_ind->dst; + if (src_ind != dst_ind) { + for (; src_ind < src_end;) { + *dst_ind ++ = *src_ind ++; + } + } + } + } + + /* Initialize (multiple) .bss sections to zero */ + { + /* Struct of zero table entry which must match linker script */ + typedef struct zero_table_entry_ { + uint32_t start; // Address to start zero'ing + uint32_t size; // Zero size in bytes + } zero_table_entry; + + zero_table_entry *zero_table_ind = (zero_table_entry *) &__zero_table_start__; + zero_table_entry *zero_table_end = (zero_table_entry *) &__zero_table_end__; + + for (; zero_table_ind != zero_table_end; zero_table_ind ++) { + uint32_t *dst_ind = (uint32_t *) zero_table_ind->start; + uint32_t *dst_end = (uint32_t *) (zero_table_ind->start + zero_table_ind->size); + + for (; dst_ind < dst_end; ) { + *dst_ind ++ = 0; + } + } + } + + _start(); + +#endif + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/system_M2354.c b/targets/TARGET_NUVOTON/TARGET_M2354/device/system_M2354.c new file mode 100644 index 0000000000..848e84f7eb --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/system_M2354.c @@ -0,0 +1,101 @@ +/**************************************************************************//** + * @file system_M2354.c + * @version V2.00 + * @brief System Setting Source File + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler 6 */ +#include +#endif + +#include +#include +#include "NuMicro.h" + +#if defined(__ICCARM__) +extern void *__vector_table; /* see startup file */ +#else +extern void *__vector_handlers; /* see startup file */ +#endif + + +/*---------------------------------------------------------------------------- + Clock Variable definitions + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */ +uint32_t CyclesPerUs = (__HSI / 1000000UL);/*!< Cycles per micro second */ +uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */ + + +/** + * @brief Update the Variable SystemCoreClock + * + * @details This function is used to update the variable SystemCoreClock + * and must be called whenever the core clock is changed. + */ +void SystemCoreClockUpdate(void) +{ + /* Update PLL Clock */ + PllClock = CLK_GetPLLClockFreq(); + + /* Update System Core Clock */ + SystemCoreClock = CLK_GetCPUFreq(); + + /* Update Cycles per micro second */ + CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL; +} + + + +/** + * @brief System Initialization + * + * @details The necessary initialization of system. Global variables are forbidden here. + */ +void SystemInit(void) +{ + + if((__PC() & NS_OFFSET) == 0) + { + do + { + SYS->REGLCTL = 0x59; + SYS->REGLCTL = 0x16; + SYS->REGLCTL = 0x88; + } while(!SYS->REGLCTL); + + // power gating + M32(0x400001f4) = 0xfffffffful; + M32(0x400000dC) = 0ul; + // GPIO clk + CLK->AHBCLK |= (0xffful << 20) | (1ul << 14); + } + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +#if defined(__ICCARM__) + SCB->VTOR = (uint32_t) &__vector_table; +#else + SCB->VTOR = (uint32_t) &__vector_handlers; +#endif +#endif + +#ifdef INIT_SYSCLK_AT_BOOTING + +#endif + +} + +/* Return program counter for checking in secure/non-secure domain */ +__attribute__((naked)) uint32_t __PC(void) +{ +#if defined(__GNUC__) + __asm(".syntax unified \n"); +#endif + + __asm("mov r0, lr \n"); + __asm("blx lr \n"); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/device/system_M2354.h b/targets/TARGET_NUVOTON/TARGET_M2354/device/system_M2354.h new file mode 100644 index 0000000000..91121753d9 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/device/system_M2354.h @@ -0,0 +1,140 @@ +/**************************************************************************//** + * @file system_M2354.h + * @version V3.00 + * @brief System Setting Header File + * + * @note + * @copyright SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __SYSTEM_M2354_H__ +#define __SYSTEM_M2354_H__ + +#ifdef __cplusplus +extern "C" { +#endif +/*---------------------------------------------------------------------------------------------------------*/ +/* Macro Definition */ +/*---------------------------------------------------------------------------------------------------------*/ +#ifndef DEBUG_PORT +# define DEBUG_PORT UART0 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */ +#endif + + +/* Init ETM Interface Multi-function Pins */ +#define ETM_INIT() { \ + SYS->GPC_MFPL &= ~(SYS_GPC_MFPL_PC0MFP_ETM_TRACE_Msk | SYS_GPC_MFPL_PC1MFP_ETM_TRACE_Msk | \ + SYS_GPC_MFPL_PC2MFP_ETM_TRACE_Msk | SYS_GPC_MFPL_PC3MFP_ETM_TRACE_Msk | \ + SYS_GPC_MFPL_PC4MFP_ETM_TRACE_Msk); \ + SYS->GPC_MFPL |= SYS_GPC_MFPL_PC0MFP_ETM_TRACE_CLK | SYS_GPC_MFPL_PC1MFP_ETM_TRACE_DATA0 | \ + SYS_GPC_MFPL_PC2MFP_ETM_TRACE_DATA1 | SYS_GPC_MFPL_PC3MFP_ETM_TRACE_DATA2 | \ + SYS_GPC_MFPL_PC4MFP_ETM_TRACE_DATA3;} + + + + + +/** + * + * @details This is used to enable PLL to speed up booting at startup. Remove it will cause system using + * default clock source (External crystal or internal 22.1184MHz IRC). + * Enable this option will cause system booting in 72MHz(By XTAL) or 71.8848MHz(By IRC22M) according to + * user configuration setting in CONFIG0 + * + */ + +/* +#define INIT_SYSCLK_AT_BOOTING +*/ + +/*---------------------------------------------------------------------------- + Define SYSCLK + *----------------------------------------------------------------------------*/ +#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */ +#define __LIRC (32000UL) /*!< Internal 32K RC Oscillator Frequency */ +#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */ +#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */ +#define __HSI (48000000UL) /*!< PLL Output Clock Frequency */ +#define __HIRC48 (48000000UL) /*!< Internal 48M RC Oscillator Frequency */ +#define __LIRC32 (32000UL) /*!< Internal 32K RC Oscillator Frequency */ +#define __MIRC (4000000UL) /*!< Internal 4M RC Oscillator Frequency */ + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L) +# if defined (__ICCARM__) +# define __NONSECURE_ENTRY __cmse_nonsecure_entry +# define __NONSECURE_ENTRY_WEAK __cmse_nonsecure_entry //__weak +# define __NONSECURE_CALL __cmse_nonsecure_call +# else +# define __NONSECURE_ENTRY __attribute__((cmse_nonsecure_entry)) +# define __NONSECURE_ENTRY_WEAK __attribute__((cmse_nonsecure_entry,weak)) +# define __NONSECURE_CALL __attribute__((cmse_nonsecure_call)) +# endif +#else +# define __NONSECURE_ENTRY +# define __NONSECURE_ENTRY_WEAK +# define __NONSECURE_CALL +#endif + + + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +extern uint32_t CyclesPerUs; /*!< Cycles per micro second */ +extern uint32_t PllClock; /*!< PLL Output Clock Frequency */ +extern uint32_t __PC(void); /*!< Return the current program counter value */ + +#if USE_ASSERT +/** + * @brief Assert Function + * + * @param[in] expr Expression to be evaluated + * + * @details If the expression is false, an error message will be printed out + * from debug port (UART0 or UART1). + */ +#define ASSERT_PARAM(expr) { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } } + +void AssertError(uint8_t* file, uint32_t line); +#else +#define ASSERT_PARAM(expr) +#endif + +#define assert_param(expr) ASSERT_PARAM(expr) + + +/** + * @brief System Initialization + * + * @details The necessary initialization of system. + */ +extern void SystemInit(void); + + +/** + * @brief Update the Variable SystemCoreClock + * + * @details This function is used to update the variable SystemCoreClock + * and must be called whenever the core clock is changed. + */ +extern void SystemCoreClockUpdate(void); + + + + +#if (defined(__ICCARM__) && (__VER__ >= 7080000) && (__VER__ < 8020000)) +uint32_t __TZ_get_PSP_NS(void); +void __TZ_set_PSP_NS(uint32_t topOfProcStack); +int32_t __TZ_get_MSP_NS(void); +void __TZ_set_MSP_NS(uint32_t topOfMainStack); +uint32_t __TZ_get_PRIMASK_NS(void); +void __TZ_set_PRIMASK_NS(uint32_t priMask); +#endif + + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_M2354_H__ */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/dma.h b/targets/TARGET_NUVOTON/TARGET_M2354/dma.h new file mode 100644 index 0000000000..1935753fed --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/dma.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_DMA_H +#define MBED_DMA_H + +#include "cmsis.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define DMA_CAP_NONE (0 << 0) + +#define DMA_EVENT_ABORT (1 << 0) +#define DMA_EVENT_TRANSFER_DONE (1 << 1) +#define DMA_EVENT_TIMEOUT (1 << 2) +#define DMA_EVENT_ALL (DMA_EVENT_ABORT | DMA_EVENT_TRANSFER_DONE | DMA_EVENT_TIMEOUT) +#define DMA_EVENT_MASK DMA_EVENT_ALL + +void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event); +PDMA_T *dma_modbase(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/dma_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/dma_api.c new file mode 100644 index 0000000000..83b989a72b --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/dma_api.c @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "dma_api.h" +#include "string.h" +#include "cmsis.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "PeripheralNames.h" +#include "nu_modutil.h" +#include "nu_bitutil.h" +#include "dma.h" + +#define NU_PDMA_CH_MAX PDMA_CH_MAX /* Specify maximum channels of PDMA */ +#define NU_PDMA_CH_Pos 0 /* Specify first channel number of PDMA */ +#define NU_PDMA_CH_Msk (((1 << NU_PDMA_CH_MAX) - 1) << NU_PDMA_CH_Pos) + +struct nu_dma_chn_s { + void (*handler)(uint32_t, uint32_t); + uint32_t id; + uint32_t event; +}; + +/* Partition policy of PDMAs + * + * To support DMA for secure/non-secure peripherals simultaneously, we have the following + * partition policy: + * + * 1. PDMA0 is hard-wired to secure and PDMA1 is configured to non-secure. + * 2. In secure domain, only PDMA0 is accessible and shall be used for secure peripheral. + * 3. In non-secure domain, only PDMA1 is accessible and shall be used for non-secure peripheral. + */ + +static int dma_inited = 0; +static uint32_t dma_chn_mask = 0; +static struct nu_dma_chn_s dma_chn_arr[NU_PDMA_CH_MAX]; + +static void pdma_vec(void); +static const struct nu_modinit_s dma_modinit = {DMA_1, PDMA1_MODULE, 0, 0, PDMA1_RST, PDMA1_IRQn, (void *) pdma_vec}; + +void dma_init(void) +{ + if (dma_inited) { + return; + } + + dma_inited = 1; + dma_chn_mask = ~NU_PDMA_CH_Msk; + memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr)); + + /* Enable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_EnableModuleClock_S(dma_modinit.clkidx); + + /* Reset module + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule_S(dma_modinit.rsetidx); + + /* Check security state of PDMA0/1 match the partition policy above. */ + PDMA_T *pdma_base = dma_modbase(); + if (((uint32_t) pdma_base) != (PDMA1_BASE + NS_OFFSET)) { + error("In non-secure domain, only PDMA1 is accessible and shall be used for non-secure peripheral"); + } + + PDMA_Open(pdma_base, 0); + + NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var); + NVIC_EnableIRQ(dma_modinit.irq_n); +} + +int dma_channel_allocate(uint32_t capabilities) +{ + if (! dma_inited) { + dma_init(); + } + + int i = nu_cto(dma_chn_mask); + if (i != 32) { + dma_chn_mask |= 1 << i; + memset(dma_chn_arr + i - NU_PDMA_CH_Pos, 0x00, sizeof (struct nu_dma_chn_s)); + return i; + } + + // No channel available + return DMA_ERROR_OUT_OF_CHANNELS; +} + +int dma_channel_free(int channelid) +{ + if (channelid != DMA_ERROR_OUT_OF_CHANNELS) { + dma_chn_mask &= ~(1 << channelid); + } + + return 0; +} + +void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event) +{ + MBED_ASSERT(dma_chn_mask & (1 << channelid)); + + dma_chn_arr[channelid - NU_PDMA_CH_Pos].handler = (void (*)(uint32_t, uint32_t)) handler; + dma_chn_arr[channelid - NU_PDMA_CH_Pos].id = id; + dma_chn_arr[channelid - NU_PDMA_CH_Pos].event = event; + + // Set interrupt vector if someone has removed it. + NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var); + NVIC_EnableIRQ(dma_modinit.irq_n); +} + +PDMA_T *dma_modbase(void) +{ + return (PDMA_T *) NU_MODBASE(dma_modinit.modname); +} + +static void pdma_vec(void) +{ + PDMA_T *pdma_base = (PDMA_T *) NU_MODBASE(dma_modinit.modname); + + uint32_t intsts = PDMA_GET_INT_STATUS(pdma_base); + + // Abort + if (intsts & PDMA_INTSTS_ABTIF_Msk) { + uint32_t abtsts = PDMA_GET_ABORT_STS(pdma_base); + // Clear all Abort flags + PDMA_CLR_ABORT_FLAG(pdma_base, abtsts); + + while (abtsts) { + int chn_id = nu_ctz(abtsts) - PDMA_ABTSTS_ABTIF0_Pos + NU_PDMA_CH_Pos; + if (dma_chn_mask & (1 << chn_id)) { + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; + if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) { + dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT); + } + } + abtsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_ABTSTS_ABTIF0_Pos)); + } + } + + // Transfer done + if (intsts & PDMA_INTSTS_TDIF_Msk) { + uint32_t tdsts = PDMA_GET_TD_STS(pdma_base); + // Clear all transfer done flags + PDMA_CLR_TD_FLAG(pdma_base, tdsts); + + while (tdsts) { + int chn_id = nu_ctz(tdsts) - PDMA_TDSTS_TDIF0_Pos + NU_PDMA_CH_Pos; + if (dma_chn_mask & (1 << chn_id)) { + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; + if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) { + dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE); + } + } + tdsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_TDSTS_TDIF0_Pos)); + } + } + + // Timeout + uint32_t reqto = intsts & (PDMA_INTSTS_REQTOF0_Msk | PDMA_INTSTS_REQTOF1_Msk); + if (reqto) { + // Clear all Timeout flags + pdma_base->INTSTS = reqto; + + while (reqto) { + int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOF0_Pos + NU_PDMA_CH_Pos; + if (dma_chn_mask & (1 << chn_id)) { + struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos; + if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) { + dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT); + } + } + reqto &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_INTSTS_REQTOF0_Pos)); + } + } +} diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/gpio_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/gpio_api.c new file mode 100644 index 0000000000..cbbb1dc167 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/gpio_api.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "gpio_api.h" +#include "mbed_assert.h" +#include "pinmap.h" +#include "mbed_error.h" +#include "PeripheralPins.h" + +uint32_t gpio_set(PinName pin) +{ + if (pin == (PinName) NC) { + return 0; + } + + uint32_t pin_index = NU_PINNAME_TO_PIN(pin); + +#if 1 + pin_function(pin, 0 << NU_MFP_POS(pin_index)); +#else + pinmap_pinout(pin, PinMap_GPIO); +#endif + + return (uint32_t)(1 << pin_index); // Return the pin mask +} + +int gpio_is_connected(const gpio_t *obj) +{ + return (obj->pin != (PinName) NC); +} + +void gpio_init(gpio_t *obj, PinName pin) +{ + obj->pin = pin; + + if (obj->pin == (PinName) NC) { + return; + } + + obj->mask = gpio_set(pin); + /* Default mode/direction */ + obj->mode = PullUp; + obj->direction = PIN_INPUT; +} + +void gpio_mode(gpio_t *obj, PinMode mode) +{ + if (obj->pin == (PinName) NC) { + return; + } + + uint32_t pin_index = NU_PININDEX(obj->pin); + uint32_t port_index = NU_PINPORT(obj->pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + + switch (mode) { + case PullNone: + if (mode == PullNone) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_DISABLE); + } + case PullDown: + if (mode == PullDown) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_DOWN); + } + case PullUp: + if (mode == PullUp) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_UP); + } + /* H/W doesn't support separate configuration for input pull mode/direction. + * We translate to input-only/push-pull output I/O mode dependent on direction. */ + obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput; + break; + + case QuasiBidirectional: + /* With quasi-bidirectional I/O mode, before digital input function is performed, + * the corresponding bit in GPIOx_DOUT must be set to 1. */ + obj->mode = QuasiBidirectional; + if (obj->direction == PIN_INPUT) { + gpio_write(obj, 1); + } + break; + + case InputOnly: + case PushPullOutput: + /* We may meet contradictory I/O mode/direction configuration. Favor I/O mode + * in the gpio_mode call here. */ + if (mode == InputOnly) { + obj->direction = PIN_INPUT; + obj->mode = InputOnly; + } else { + obj->direction = PIN_OUTPUT; + obj->mode = PushPullOutput; + } + break; + + default: + /* Allow for configuring other I/O modes directly */ + obj->mode = mode; + break; + } + + pin_mode(obj->pin, obj->mode); +} + +void gpio_dir(gpio_t *obj, PinDirection direction) +{ + if (obj->pin == (PinName) NC) { + return; + } + + obj->direction = direction; + + uint32_t pin_index = NU_PININDEX(obj->pin); + uint32_t port_index = NU_PINPORT(obj->pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + + switch (obj->mode) { + case PullNone: + if (obj->mode == PullNone) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_DISABLE); + } + case PullDown: + if (obj->mode == PullDown) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_DOWN); + } + case PullUp: + if (obj->mode == PullUp) { + GPIO_SetPullCtl(gpio_base, 1 << pin_index, GPIO_PUSEL_PULL_UP); + } + /* H/W doesn't support separate configuration for input pull mode/direction. + * We translate to input-only/push-pull output I/O mode dependent on direction. */ + obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput; + break; + + case QuasiBidirectional: + /* With quasi-bidirectional I/O mode, before digital input function is performed, + * the corresponding bit in GPIOx_DOUT must be set to 1. */ + if (obj->direction == PIN_INPUT) { + gpio_write(obj, 1); + } + break; + + case InputOnly: + case PushPullOutput: + /* We may meet contradictory I/O mode/direction configuration. Favor direction + * in the gpio_dir call here. */ + obj->mode = (obj->direction == PIN_INPUT) ? InputOnly : PushPullOutput; + break; + + default: + break; + } + + pin_mode(obj->pin, obj->mode); +} diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/gpio_irq_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/gpio_irq_api.c new file mode 100644 index 0000000000..e0a6796688 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/gpio_irq_api.c @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "gpio_irq_api.h" + +#if DEVICE_INTERRUPTIN + +#include "gpio_api.h" +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "nu_bitutil.h" +#include "mbed_assert.h" + +#define NU_MAX_PIN_PER_PORT 16 + +struct nu_gpio_irq_var { + gpio_irq_t * obj_arr[NU_MAX_PIN_PER_PORT]; + IRQn_Type irq_n; + void (*vec)(void); + uint32_t port_index; +}; + +static void gpio_irq_0_vec(void); +static void gpio_irq_1_vec(void); +static void gpio_irq_2_vec(void); +static void gpio_irq_3_vec(void); +static void gpio_irq_4_vec(void); +static void gpio_irq_5_vec(void); +static void gpio_irq_6_vec(void); +static void gpio_irq_7_vec(void); +static void gpio_irq(struct nu_gpio_irq_var *var); + +//EINT0_IRQn +static struct nu_gpio_irq_var gpio_irq_var_arr[] = { + {{NULL}, GPA_IRQn, gpio_irq_0_vec, 0}, + {{NULL}, GPB_IRQn, gpio_irq_1_vec, 1}, + {{NULL}, GPC_IRQn, gpio_irq_2_vec, 2}, + {{NULL}, GPD_IRQn, gpio_irq_3_vec, 3}, + {{NULL}, GPE_IRQn, gpio_irq_4_vec, 4}, + {{NULL}, GPF_IRQn, gpio_irq_5_vec, 5}, + {{NULL}, GPG_IRQn, gpio_irq_6_vec, 6}, + {{NULL}, GPG_IRQn, gpio_irq_7_vec, 7}, +}; + +#define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0])) + +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE 0 +#endif + +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC +#endif +static PinName gpio_irq_debounce_arr[] = { + MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST +}; + +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC +#endif + +#ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE +#define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16 +#endif + +int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) +{ + if (pin == NC) { + return -1; + } + + uint32_t pin_index = NU_PINNAME_TO_PIN(pin); + uint32_t port_index = NU_PINNAME_TO_PORT(pin); + if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) { + return -1; + } + + obj->pin = pin; + obj->irq_types = 0; + obj->irq_handler = (uint32_t) handler; + obj->irq_id = id; + + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting. + // There is no need to call gpio_set() redundantly. + + { +#if MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE + // Suppress compiler warning + (void) gpio_irq_debounce_arr; + + // Configure de-bounce clock source and sampling cycle time + GPIO_SET_DEBOUNCE_TIME(gpio_base, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE); + GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index); +#else + // Enable de-bounce if the pin is in the de-bounce enable list + + // De-bounce defaults to disabled. + GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index); + + PinName *debounce_pos = gpio_irq_debounce_arr; + PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]); + for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) { + uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos); + uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos); + + if (pin_index == pin_index_debunce && + port_index == port_index_debounce) { + // Configure de-bounce clock source and sampling cycle time + GPIO_SET_DEBOUNCE_TIME(gpio_base, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE); + GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index); + break; + } + } +#endif + } + + struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; + + var->obj_arr[pin_index] = obj; + + // NOTE: InterruptIn requires IRQ enabled by default. + gpio_irq_enable(obj); + + return 0; +} + +void gpio_irq_free(gpio_irq_t *obj) +{ + uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin); + uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); + struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; + + NVIC_DisableIRQ(var->irq_n); + NU_PORT_BASE(port_index)->INTEN = 0; + + MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT); + var->obj_arr[pin_index] = NULL; +} + +void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) +{ + uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin); + uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + + /* We assume BSP has such coding so that we can easily add/remove either irq type. */ + MBED_STATIC_ASSERT(GPIO_INT_BOTH_EDGE == (GPIO_INT_RISING | GPIO_INT_FALLING), + "GPIO_INT_BOTH_EDGE must be bitwise OR of GPIO_INT_RISING and GPIO_INT_FALLING"); + uint32_t irq_type; + switch (event) { + case IRQ_RISE: + irq_type = GPIO_INT_RISING; + break; + + case IRQ_FALL: + irq_type = GPIO_INT_FALLING; + break; + + default: + irq_type = 0; + } + + /* We can handle invalid/null irq type. */ + if (enable) { + obj->irq_types |= irq_type; + } else { + obj->irq_types &= ~irq_type; + } + + /* Update irq types: + * + * Implementations of GPIO_EnableInt(...) are inconsistent: disable or not irq type not enabled. + * For consistency, disable GPIO_INT_BOTH_EDGE and then enable OR'ed irq types, GPIO_INT_RISING, + * GPIO_INT_FALLING, or both. + */ + GPIO_DisableInt(gpio_base, pin_index); + GPIO_EnableInt(gpio_base, pin_index, obj->irq_types); +} + +void gpio_irq_enable(gpio_irq_t *obj) +{ + uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); + struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; + + NVIC_SetVector(var->irq_n, (uint32_t) var->vec); + NVIC_EnableIRQ(var->irq_n); +} + +void gpio_irq_disable(gpio_irq_t *obj) +{ + uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); + struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index; + + NVIC_DisableIRQ(var->irq_n); +} + +static void gpio_irq_0_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 0); +} +static void gpio_irq_1_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 1); +} +static void gpio_irq_2_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 2); +} +static void gpio_irq_3_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 3); +} +static void gpio_irq_4_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 4); +} +static void gpio_irq_5_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 5); +} +static void gpio_irq_6_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 6); +} +static void gpio_irq_7_vec(void) +{ + gpio_irq(gpio_irq_var_arr + 7); +} + +static void gpio_irq(struct nu_gpio_irq_var *var) +{ + // NOTE: GPA_IRQn, GPB_IRQn, ... are not arranged sequentially, so we cannot calculate out port_index through offset from GPA_IRQn. + // Instead, we add port_index into gpio_irq_var_arr table. + uint32_t port_index = var->port_index; + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + + uint32_t intsrc = gpio_base->INTSRC; + uint32_t inten = gpio_base->INTEN; + while (intsrc) { + int pin_index = nu_ctz(intsrc); + gpio_irq_t *obj = var->obj_arr[pin_index]; + if (inten & (GPIO_INT_RISING << pin_index)) { + if (NU_GET_GPIO_PIN_DATA(port_index, pin_index)) { + if (obj->irq_handler) { + ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE); + } + } + } + + if (inten & (GPIO_INT_FALLING << pin_index)) { + if (! NU_GET_GPIO_PIN_DATA(port_index, pin_index)) { + if (obj->irq_handler) { + ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL); + } + } + } + + intsrc &= ~(1 << pin_index); + } + // Clear all interrupt flags + gpio_base->INTSRC = gpio_base->INTSRC; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/gpio_object.h b/targets/TARGET_NUVOTON/TARGET_M2354/gpio_object.h new file mode 100644 index 0000000000..7e73d8dd27 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/gpio_object.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_GPIO_OBJECT_H +#define MBED_GPIO_OBJECT_H + +#include "mbed_assert.h" +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + PinName pin; + uint32_t mask; + PinDirection direction; + PinMode mode; +} gpio_t; + +static inline void gpio_write(gpio_t *obj, int value) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin); + uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); + + NU_SET_GPIO_PIN_DATA(port_index, pin_index, value ? 1 : 0); +} + +static inline int gpio_read(gpio_t *obj) +{ + MBED_ASSERT(obj->pin != (PinName)NC); + uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin); + uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin); + + return (NU_GET_GPIO_PIN_DATA(port_index, pin_index) ? 1 : 0); +} + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/i2c_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/i2c_api.c new file mode 100644 index 0000000000..65a9553adb --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/i2c_api.c @@ -0,0 +1,1005 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "i2c_api.h" + +#if DEVICE_I2C + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" +#include "nu_bitutil.h" +#include "mbed_critical.h" +#include "us_ticker_api.h" + +struct nu_i2c_var { + i2c_t * obj; + void (*vec)(void); +}; + +static void i2c0_vec(void); +static void i2c1_vec(void); +static void i2c2_vec(void); +static void i2c_irq(i2c_t *obj); +static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl); +static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked); + +static struct nu_i2c_var i2c0_var = { + .obj = NULL, + .vec = i2c0_vec, +}; +static struct nu_i2c_var i2c1_var = { + .obj = NULL, + .vec = i2c1_vec, +}; +static struct nu_i2c_var i2c2_var = { + .obj = NULL, + .vec = i2c2_vec, +}; + +static uint32_t i2c_modinit_mask = 0; + +static const struct nu_modinit_s i2c_modinit_tab[] = { + {I2C_0, I2C0_MODULE, 0, 0, I2C0_RST, I2C0_IRQn, &i2c0_var}, + {I2C_1, I2C1_MODULE, 0, 0, I2C1_RST, I2C1_IRQn, &i2c1_var}, + {I2C_2, I2C2_MODULE, 0, 0, I2C2_RST, I2C2_IRQn, &i2c2_var}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + +static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata); +static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync); +#define NU_I2C_TIMEOUT_STAT_INT 500000 +#define NU_I2C_TIMEOUT_STOP 500000 +static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout); +static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout); +static int i2c_is_trsn_done(i2c_t *obj); +static int i2c_is_tran_started(i2c_t *obj); +static int i2c_addr2data(int address, int read); +#if DEVICE_I2CSLAVE +// Convert mbed address to BSP address. +static int i2c_addr2bspaddr(int address); +#endif // #if DEVICE_I2CSLAVE +static void i2c_enable_int(i2c_t *obj); +static void i2c_disable_int(i2c_t *obj); +static int i2c_set_int(i2c_t *obj, int inten); + + +#if DEVICE_I2C_ASYNCH +static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length); +static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable); +static void i2c_rollback_vector_interrupt(i2c_t *obj); +#endif + +#define TRANCTRL_STARTED (1) // Guard I2C ISR from data transfer prematurely +#define TRANCTRL_NAKLASTDATA (1 << 1) // Request NACK on last data +#define TRANCTRL_LASTDATANAKED (1 << 2) // Last data NACKed +#define TRANCTRL_RECVDATA (1 << 3) // Receive data available + +uint32_t us_ticker_read(void); + +void i2c_init(i2c_t *obj, PinName sda, PinName scl) +{ + uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA); + uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL); + obj->i2c.i2c = (I2CName) pinmap_merge(i2c_sda, i2c_scl); + MBED_ASSERT((int)obj->i2c.i2c != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + obj->i2c.pin_sda = sda; + obj->i2c.pin_scl = scl; + + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + + /* Select IP clock source + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_EnableModuleClock_S(modinit->clkidx); + + /* Reset module + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule_S(modinit->rsetidx); + +#if DEVICE_I2C_ASYNCH + obj->i2c.dma_usage = DMA_USAGE_NEVER; + obj->i2c.event = 0; + obj->i2c.stop = 0; + obj->i2c.address = 0; +#endif + + // NOTE: Setting I2C bus clock to 100 KHz is required. See I2C::I2C in common/I2C.cpp. + I2C_Open((I2C_T *) NU_MODBASE(obj->i2c.i2c), 100000); + // NOTE: INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL0. We cannot control interrupt through + // INTEN bit without impacting FSM control bits. Use NVIC_EnableIRQ/NVIC_DisableIRQ instead for interrupt control. + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + i2c_base->CTL0 |= (I2C_CTL0_INTEN_Msk | I2C_CTL0_I2CEN_Msk); + + // Enable sync-mode vector interrupt. + struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var; + var->obj = obj; + obj->i2c.tran_ctrl = 0; + obj->i2c.stop = 0; + i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1); + + // Mark this module to be inited. + int i = modinit - i2c_modinit_tab; + i2c_modinit_mask |= 1 << i; +} + +void i2c_free(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + /* Disable I2C interrupt */ + NVIC_DisableIRQ(modinit->irq_n); + + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + /* Disable I2C module */ + I2C_Close(i2c_base); + + /* Disable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_DisableModuleClock_S(modinit->clkidx); + + // Mark this module to be deinited. + int i = modinit - i2c_modinit_tab; + i2c_modinit_mask &= ~(1 << i); + + /* Free up pins */ + gpio_set(obj->i2c.pin_sda); + gpio_set(obj->i2c.pin_scl); + obj->i2c.pin_sda = NC; + obj->i2c.pin_scl = NC; +} + +int i2c_start(i2c_t *obj) +{ + return i2c_do_trsn(obj, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk, 1); +} + +int i2c_stop(i2c_t *obj) +{ + return i2c_do_trsn(obj, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk, 1); +} + +void i2c_frequency(i2c_t *obj, int hz) +{ + I2C_SetBusClockFreq((I2C_T *) NU_MODBASE(obj->i2c.i2c), hz); +} + +int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) +{ + if (i2c_start(obj)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + if (i2c_byte_write(obj, i2c_addr2data(address, 1)) != 1) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + // Read in bytes + length = i2c_do_tran(obj, data, length, 1, 1); + + // If not repeated start, send stop. + if (stop) { + i2c_stop(obj); + } + + return length; +} + +int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) +{ + if (i2c_start(obj)) { + i2c_stop(obj); + return I2C_ERROR_BUS_BUSY; + } + + if (i2c_byte_write(obj, i2c_addr2data(address, 0)) != 1) { + i2c_stop(obj); + return I2C_ERROR_NO_SLAVE; + } + + // Write out bytes + length = i2c_do_tran(obj, (char *) data, length, 0, 1); + + if (stop) { + i2c_stop(obj); + } + + return length; +} + +void i2c_reset(i2c_t *obj) +{ + i2c_stop(obj); +} + +int i2c_byte_read(i2c_t *obj, int last) +{ + char data = 0; + i2c_do_tran(obj, &data, 1, 1, last); + return data; +} + +int i2c_byte_write(i2c_t *obj, int data) +{ + char data_[1]; + data_[0] = data & 0xFF; + + if (i2c_do_tran(obj, data_, 1, 0, 0) == 1 && + ! (obj->i2c.tran_ctrl & TRANCTRL_LASTDATANAKED)) { + return 1; + } else { + return 0; + } +} + +const PinMap *i2c_master_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_master_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +const PinMap *i2c_slave_sda_pinmap() +{ + return PinMap_I2C_SDA; +} + +const PinMap *i2c_slave_scl_pinmap() +{ + return PinMap_I2C_SCL; +} + +#if DEVICE_I2CSLAVE + +// See I2CSlave.h +#define NoData 0 // the slave has not been addressed +#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter) +#define WriteGeneral 2 // the master is writing to all slave +#define WriteAddressed 3 // the master is writing to this slave (slave = receiver) + +void i2c_slave_mode(i2c_t *obj, int enable_slave) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + i2c_disable_int(obj); + + obj->i2c.slaveaddr_state = NoData; + + // Switch to not addressed mode + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + + i2c_enable_int(obj); +} + +int i2c_slave_receive(i2c_t *obj) +{ + int slaveaddr_state; + + i2c_disable_int(obj); + slaveaddr_state = obj->i2c.slaveaddr_state; + i2c_enable_int(obj); + + return slaveaddr_state; +} + +int i2c_slave_read(i2c_t *obj, char *data, int length) +{ + return i2c_do_tran(obj, data, length, 1, 1); +} + +int i2c_slave_write(i2c_t *obj, const char *data, int length) +{ + return i2c_do_tran(obj, (char *) data, length, 0, 1); +} + +void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + i2c_disable_int(obj); + + // NOTE: On NUC472/M451, non-zero slave address can still work as GC mode is enabled. + // On M480, non-zero slave address won't work as GC mode is enabled. + I2C_SetSlaveAddr(i2c_base, 0, i2c_addr2bspaddr(address), I2C_GCMODE_DISABLE); + + i2c_enable_int(obj); +} + +static int i2c_addr2bspaddr(int address) +{ + return (address >> 1); +} + +#endif // #if DEVICE_I2CSLAVE + +static void i2c_enable_int(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + + core_util_critical_section_enter(); + + // Enable I2C interrupt + NVIC_EnableIRQ(modinit->irq_n); + obj->i2c.inten = 1; + + core_util_critical_section_exit(); +} + +static void i2c_disable_int(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + + core_util_critical_section_enter(); + + // Disable I2C interrupt + NVIC_DisableIRQ(modinit->irq_n); + obj->i2c.inten = 0; + + core_util_critical_section_exit(); +} + +static int i2c_set_int(i2c_t *obj, int inten) +{ + int inten_back; + + core_util_critical_section_enter(); + + inten_back = obj->i2c.inten; + + core_util_critical_section_exit(); + + if (inten) { + i2c_enable_int(obj); + } else { + i2c_disable_int(obj); + } + + return inten_back; +} + +static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata) +{ + if (! buf || ! length) { + return 0; + } + + int tran_len = 0; + + i2c_disable_int(obj); + obj->i2c.tran_ctrl = naklastdata ? (TRANCTRL_STARTED | TRANCTRL_NAKLASTDATA) : TRANCTRL_STARTED; + obj->i2c.tran_beg = buf; + obj->i2c.tran_pos = buf; + obj->i2c.tran_end = buf + length; + i2c_enable_int(obj); + + if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) { + // N/A + } else { + i2c_disable_int(obj); + tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg; + obj->i2c.tran_beg = NULL; + obj->i2c.tran_pos = NULL; + obj->i2c.tran_end = NULL; + i2c_enable_int(obj); + } + + return tran_len; +} + +static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + int err = 0; + + i2c_disable_int(obj); + + if (i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) { + err = I2C_ERROR_BUS_BUSY; + } else { + // NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error. + uint32_t status = I2C_GET_STATUS(i2c_base); + + switch (status) { + case 0x08: // Start + case 0x10: // Master Repeat Start + if (i2c_ctl & I2C_CTL0_STA_Msk) { + return 0; + } else { + break; + } + case 0xF8: // Bus Released + if ((i2c_ctl & (I2C_CTL0_STA_Msk | I2C_CTL0_STO_Msk)) == I2C_CTL0_STO_Msk) { + return 0; + } else { + break; + } + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + if (sync && i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) { + err = I2C_ERROR_BUS_BUSY; + } + } + + i2c_enable_int(obj); + + return err; +} + +static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout) +{ + uint32_t t1, t2, elapsed = 0; + int status_assert = 0; + const uint32_t bits = us_ticker_get_info()->bits; + const uint32_t mask = (1 << bits) - 1; + + t1 = us_ticker_read(); + while (1) { + status_assert = is_status(obj); + if (status_assert) { + break; + } + + t2 = us_ticker_read(); + elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + mask - t1 + 1); + if (elapsed >= timeout) { + break; + } + } + + return (elapsed >= timeout); +} + +static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout) +{ + uint32_t t1, t2, elapsed = 0; + int tran_started; + char *tran_pos = NULL; + char *tran_pos2 = NULL; + const uint32_t bits = us_ticker_get_info()->bits; + const uint32_t mask = (1 << bits) - 1; + + i2c_disable_int(obj); + tran_pos = obj->i2c.tran_pos; + i2c_enable_int(obj); + t1 = us_ticker_read(); + while (1) { + i2c_disable_int(obj); + tran_started = i2c_is_tran_started(obj); + i2c_enable_int(obj); + if (! tran_started) { // Transfer completed or stopped + break; + } + + i2c_disable_int(obj); + tran_pos2 = obj->i2c.tran_pos; + i2c_enable_int(obj); + t2 = us_ticker_read(); + if (tran_pos2 != tran_pos) { // Transfer on-going + t1 = t2; + tran_pos = tran_pos2; + continue; + } + + elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + mask - t1 + 1); + if (elapsed >= timeout) { // Transfer idle + break; + } + } + + return (elapsed >= timeout); +} + +#if 0 +static int i2c_is_stat_int(i2c_t *obj) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + return !! (i2c_base->CTL0 & I2C_CTL0_SI_Msk); +} + +static int i2c_is_stop_det(i2c_t *obj) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + return ! (i2c_base->CTL0 & I2C_CTL0_STO_Msk); +} +#endif + +static int i2c_is_trsn_done(i2c_t *obj) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + int i2c_int; + uint32_t status; + int inten_back; + + inten_back = i2c_set_int(obj, 0); + i2c_int = !! (i2c_base->CTL0 & I2C_CTL0_SI_Msk); + status = I2C_GET_STATUS(i2c_base); + i2c_set_int(obj, inten_back); + + return (i2c_int || status == 0xF8); +} + +static int i2c_is_tran_started(i2c_t *obj) +{ + int started; + int inten_back; + + inten_back = i2c_set_int(obj, 0); + started = !! (obj->i2c.tran_ctrl & TRANCTRL_STARTED); + i2c_set_int(obj, inten_back); + + return started; +} + +static int i2c_addr2data(int address, int read) +{ + return read ? (address | 1) : (address & 0xFE); +} + +static void i2c0_vec(void) +{ + i2c_irq(i2c0_var.obj); +} +static void i2c1_vec(void) +{ + i2c_irq(i2c1_var.obj); +} +static void i2c2_vec(void) +{ + i2c_irq(i2c2_var.obj); +} + +static void i2c_irq(i2c_t *obj) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + uint32_t status; + + if (I2C_GET_TIMEOUT_FLAG(i2c_base)) { + I2C_ClearTimeoutFlag(i2c_base); + return; + } + + status = I2C_GET_STATUS(i2c_base); + + switch (status) { + // Master Transmit + case 0x28: // Master Transmit Data ACK + case 0x18: // Master Transmit Address ACK + case 0x08: // Start + case 0x10: // Master Repeat Start + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++); + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } else { + i2c_fsm_tranfini(obj, 0); + } + } else { + i2c_disable_int(obj); + } + break; + + case 0x30: // Master Transmit Data NACK + i2c_fsm_tranfini(obj, 1); + break; + + case 0x20: // Master Transmit Address NACK + i2c_fsm_tranfini(obj, 1); + break; + + case 0x38: // Master Arbitration Lost + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + break; + + case 0x48: // Master Receive Address NACK + i2c_fsm_tranfini(obj, 1); + break; + + case 0x40: // Master Receive Address ACK + case 0x50: // Master Receive Data ACK + case 0x58: // Master Receive Data NACK + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + if (status == 0x50 || status == 0x58) { + if (obj->i2c.tran_ctrl & TRANCTRL_RECVDATA) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + obj->i2c.tran_ctrl &= ~TRANCTRL_RECVDATA; + } + } + + if (status == 0x58) { + i2c_fsm_tranfini(obj, 1); + } else if (obj->i2c.tran_pos == obj->i2c.tran_end) { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + } else { + uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; + if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && + obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) { + // Last data + i2c_ctl &= ~I2C_CTL0_AA_Msk; + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.tran_ctrl |= TRANCTRL_RECVDATA; + } + } else { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + break; + } + } else { + i2c_disable_int(obj); + } + break; + + //case 0x00: // Bus error + + // Slave Transmit + case 0xB8: // Slave Transmit Data ACK + case 0xA8: // Slave Transmit Address ACK + case 0xB0: // Slave Transmit Arbitration Lost + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; + + I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++); + if (obj->i2c.tran_pos == obj->i2c.tran_end && + obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) { + // Last data + i2c_ctl &= ~I2C_CTL0_AA_Msk; + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + } else { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + break; + } + } else { + i2c_disable_int(obj); + } + obj->i2c.slaveaddr_state = ReadAddressed; + break; + //case 0xA0: // Slave Transmit Repeat Start or Stop + case 0xC0: // Slave Transmit Data NACK + case 0xC8: // Slave Transmit Last Data ACK + obj->i2c.slaveaddr_state = NoData; + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + break; + + // Slave Receive + case 0x80: // Slave Receive Data ACK + case 0x88: // Slave Receive Data NACK + case 0x60: // Slave Receive Address ACK + case 0x68: // Slave Receive Arbitration Lost + obj->i2c.slaveaddr_state = WriteAddressed; + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + if (status == 0x80 || status == 0x88) { + if (obj->i2c.tran_ctrl & TRANCTRL_RECVDATA) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + obj->i2c.tran_ctrl &= ~TRANCTRL_RECVDATA; + } + } + + if (status == 0x88) { + obj->i2c.slaveaddr_state = NoData; + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } else if (obj->i2c.tran_pos == obj->i2c.tran_end) { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + } else { + uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; + if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && + obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) { + // Last data + i2c_ctl &= ~I2C_CTL0_AA_Msk; + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.tran_ctrl |= TRANCTRL_RECVDATA; + } + } else { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + break; + } + } else { + i2c_disable_int(obj); + } + break; + //case 0xA0: // Slave Receive Repeat Start or Stop + + // GC mode + //case 0xA0: // GC mode Repeat Start or Stop + case 0x90: // GC mode Data ACK + case 0x98: // GC mode Data NACK + case 0x70: // GC mode Address ACK + case 0x78: // GC mode Arbitration Lost + obj->i2c.slaveaddr_state = WriteAddressed; + if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) { + if (obj->i2c.tran_pos < obj->i2c.tran_end) { + if (status == 0x90 || status == 0x98) { + if (obj->i2c.tran_ctrl & TRANCTRL_RECVDATA) { + *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base); + obj->i2c.tran_ctrl &= ~TRANCTRL_RECVDATA; + } + } + + if (status == 0x98) { + obj->i2c.slaveaddr_state = NoData; + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } else if (obj->i2c.tran_pos == obj->i2c.tran_end) { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + } else { + uint32_t i2c_ctl = I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk; + if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 && + obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) { + // Last data + i2c_ctl &= ~I2C_CTL0_AA_Msk; + } + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.tran_ctrl |= TRANCTRL_RECVDATA; + } + } else { + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); + break; + } + } else { + i2c_disable_int(obj); + } + break; + + case 0xF8: // Bus Released + break; + + default: + i2c_fsm_reset(obj, I2C_CTL0_SI_Msk | I2C_CTL0_AA_Msk); + } +} + +static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl) +{ + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + + obj->i2c.stop = 0; + + obj->i2c.tran_ctrl = 0; + + I2C_SET_CONTROL_REG(i2c_base, i2c_ctl); + obj->i2c.slaveaddr_state = NoData; +} + +static void i2c_fsm_tranfini(i2c_t *obj, int lastdatanaked) +{ + if (lastdatanaked) { + obj->i2c.tran_ctrl |= TRANCTRL_LASTDATANAKED; + } + + obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED; + i2c_disable_int(obj); +} + +#if DEVICE_I2C_ASYNCH + +void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint) +{ + // NOTE: The mbed I2C address passed in is shifted left by 1 bit (7-bit addr << 1). + + // NOTE: First transmit and then receive. + + (void) hint; + obj->i2c.dma_usage = DMA_USAGE_NEVER; + obj->i2c.stop = stop; + obj->i2c.address = address; + obj->i2c.event = event; + i2c_buffer_set(obj, tx, tx_length, rx, rx_length); + + i2c_enable_vector_interrupt(obj, handler, 1); + i2c_start(obj); +} + +uint32_t i2c_irq_handler_asynch(i2c_t *obj) +{ + int event = 0; + + I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c); + uint32_t status = I2C_GET_STATUS(i2c_base); + switch (status) { + case 0x08: // Start + case 0x10: {// Master Repeat Start + if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) { + I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0))); + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk); + } else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1))); + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk); + } else { + event = I2C_EVENT_TRANSFER_COMPLETE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + } + break; + } + + case 0x18: // Master Transmit Address ACK + case 0x28: // Master Transmit Data ACK + if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) { + uint8_t *tx = (uint8_t *)obj->tx_buff.buffer; + I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]); + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk); + } else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk); + } else { + event = I2C_EVENT_TRANSFER_COMPLETE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + } + break; + + case 0x20: // Master Transmit Address NACK + event = I2C_EVENT_ERROR_NO_SLAVE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + break; + + case 0x30: // Master Transmit Data NACK + if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) { + event = I2C_EVENT_TRANSFER_EARLY_NACK; + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk); + } else { + event = I2C_EVENT_TRANSFER_COMPLETE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + } + break; + + case 0x38: // Master Arbitration Lost + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk); // Enter not addressed SLV mode + event = I2C_EVENT_ERROR; + break; + + case 0x50: // Master Receive Data ACK + if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + uint8_t *rx = (uint8_t *) obj->rx_buff.buffer; + rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c))); + } + case 0x40: // Master Receive Address ACK + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_SI_Msk | ((obj->rx_buff.pos != obj->rx_buff.length - 1) ? I2C_CTL0_AA_Msk : 0)); + break; + + case 0x48: // Master Receive Address NACK + event = I2C_EVENT_ERROR_NO_SLAVE; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + break; + + case 0x58: // Master Receive Data NACK + if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) { + uint8_t *rx = (uint8_t *) obj->rx_buff.buffer; + rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c))); + } + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STA_Msk | I2C_CTL0_SI_Msk); + break; + + case 0x00: // Bus error + event = I2C_EVENT_ERROR; + i2c_reset(obj); + break; + + default: + event = I2C_EVENT_ERROR; + if (obj->i2c.stop) { + I2C_SET_CONTROL_REG(i2c_base, I2C_CTL0_STO_Msk | I2C_CTL0_SI_Msk); + } + } + + if (event) { + i2c_rollback_vector_interrupt(obj); + } + + return (event & obj->i2c.event); +} + +uint8_t i2c_active(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + // Vector will be changed for async transfer. Use it to judge if async transfer is on-going. + uint32_t vec = NVIC_GetVector(modinit->irq_n); + struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var; + return (vec && vec != (uint32_t) var->vec); +} + +void i2c_abort_asynch(i2c_t *obj) +{ + i2c_rollback_vector_interrupt(obj); + i2c_stop(obj); +} + +static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length) +{ + obj->tx_buff.buffer = (void *) tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; + obj->rx_buff.buffer = rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; +} + +static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + if (enable) { + NVIC_SetVector(modinit->irq_n, handler); + i2c_enable_int(obj); + } else { + i2c_disable_int(obj); + } + +} + +static void i2c_rollback_vector_interrupt(i2c_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c); + + struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var; + i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1); +} + +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M2354/lp_ticker.c new file mode 100644 index 0000000000..d1742f62e0 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/lp_ticker.c @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "lp_ticker_api.h" + +#if DEVICE_LPTICKER + +#include "sleep_api.h" +#include "mbed_assert.h" +#include "nu_modutil.h" +#include "nu_timer.h" +#include "nu_miscutil.h" + +/* We have the following policy for configuring security state of TIMER for us_ticer/lp_ticker: + * + * TIMER0: Hard-wired to secure for TF-M SPE use + * TIMER1: Hard-wired to secure for TF-M SPE use + * TIMER2: Configured to non-secure for NSPE use, including TF-M NSPE test + * TIMER3: Configured to non-secure for NSPE use + * TIMER4: Configured to non-secure for Mbed NSPE us_ticer exclusively + * TIMER5: Configured to non-secure for Mbed NSPE lp_ticer exclusively + */ + +/* Micro seconds per second */ +#define NU_US_PER_SEC 1000000 +/* Timer clock per lp_ticker tick */ +#define NU_TMRCLK_PER_TICK 1 +/* Timer clock per second */ +#define NU_TMRCLK_PER_SEC (__LXT) +/* Timer max counter bit size */ +#define NU_TMR_MAXCNT_BITSIZE 24 +/* Timer max counter */ +#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) + +static void tmr5_vec(void); + +/* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ +static const struct nu_modinit_s timer5_modinit = {TIMER_5, TMR5_MODULE, CLK_CLKSEL3_TMR5SEL_LXT, 0, TMR5_RST, TMR5_IRQn, (void *) tmr5_vec}; + +#define TIMER_MODINIT timer5_modinit + +/* Timer interrupt enable/disable + * + * Because Timer interrupt enable/disable (TIMER_EnableInt/TIMER_DisableInt) needs wait for lp_ticker, + * we call NVIC_DisableIRQ/NVIC_EnableIRQ instead. + */ + +/* Track ticker status */ +static volatile uint16_t ticker_inited = 0; + +#define TMR_CMP_MIN 2 +#define TMR_CMP_MAX 0xFFFFFFu + +/* Synchronization issue with LXT/LIRC-clocked Timer + * + * PCLK : typical HCLK/2 + * ECLK (engine clock) : LXT/LIRC for Timer used to implement lp_ticker + * + * When system clock is higher than Timer clock (LXT/LIRC), we need to add delay for ECLK + * domain to take effect: + * 1. Write : typical 1PCLK + 2ECLK + * Read-check doesn't work because it just checks PCLK domain and doesn't check into + * ECLK domain. + * 2. Clear interrupt flag : typical 2PCLK + * It is very rare that we would meet dummy interrupt and get stuck in ISR until + * 'clear interrupt flag' takes effect. The issue is ignorable because the pending + * time is very short (at most 1 dummy interrupt). We won't take special handling for it. + */ + +void lp_ticker_init(void) +{ + if (ticker_inited) { + /* By HAL spec, ticker_init allows the ticker to keep counting and disables the + * ticker interrupt. */ + lp_ticker_disable_interrupt(); + return; + } + ticker_inited = 1; + + /* Select IP clock source + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_SetModuleClock_S(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + + /* Enable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_EnableModuleClock_S(TIMER_MODINIT.clkidx); + + /* Reset module + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule_S(TIMER_MODINIT.rsetidx); + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + // Configure clock + uint32_t clk_timer = TIMER_GetModuleClock(timer_base); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); + // Continuous mode + // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480/M2351/M2354. In M451/M480/M2351/M2354, TIMER_CNT is updated continuously by default. + timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + timer_base->CMP = cmp_timer; + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + // Set vector + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); + + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); + + TIMER_EnableInt(timer_base); + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + TIMER_EnableWakeup(timer_base); + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + TIMER_Start(timer_base); + nu_busy_wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3); + + /* Wait for timer to start counting and raise active flag */ + while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk)); +} + +void lp_ticker_free(void) +{ + /* Disable interrupt */ + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); + + /* Disable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_DisableModuleClock_S(TIMER_MODINIT.clkidx); + + ticker_inited = 0; +} + +timestamp_t lp_ticker_read() +{ + if (! ticker_inited) { + lp_ticker_init(); + } + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); +} + +void lp_ticker_set_interrupt(timestamp_t timestamp) +{ + /* Clear any previously pending interrupts */ + lp_ticker_clear_interrupt(); + NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n); + + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + + /* NOTE: Rely on LPTICKER_DELAY_TICKS to be non-blocking. */ + timer_base->CMP = cmp_timer; + + /* We can call ticker_irq_handler now. */ + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); +} + +void lp_ticker_disable_interrupt(void) +{ + /* We cannot call ticker_irq_handler now. */ + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); +} + +void lp_ticker_clear_interrupt(void) +{ + /* To avoid sync issue, we clear TIF/TWKF simultaneously rather than call separate + * driver API: + * + * TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + * TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); + */ + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + timer_base->INTSTS = TIMER_INTSTS_TIF_Msk | TIMER_INTSTS_TWKF_Msk; +} + +void lp_ticker_fire_interrupt(void) +{ + // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. + // This prevents a recursive loop under heavy load which can lead to a stack overflow. + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); + + /* We can call ticker_irq_handler now. */ + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); +} + +const ticker_info_t* lp_ticker_get_info() +{ + static const ticker_info_t info = { + NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK, + NU_TMR_MAXCNT_BITSIZE + }; + return &info; +} + +static void tmr5_vec(void) +{ + lp_ticker_clear_interrupt(); + + // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler(); + lp_ticker_irq_handler(); +} + +#endif diff --git a/UNITTESTS/empty_baseline/empty_baseline.cpp b/targets/TARGET_NUVOTON/TARGET_M2354/mbed_overrides.c similarity index 61% rename from UNITTESTS/empty_baseline/empty_baseline.cpp rename to targets/TARGET_NUVOTON/TARGET_M2354/mbed_overrides.c index a44075c7da..f75228b914 100644 --- a/UNITTESTS/empty_baseline/empty_baseline.cpp +++ b/targets/TARGET_NUVOTON/TARGET_M2354/mbed_overrides.c @@ -1,4 +1,6 @@ -/* Copyright (c) 2019 ARM Limited +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -14,26 +16,17 @@ * limitations under the License. */ -#include "gtest/gtest.h" +#include "cmsis.h" +#include "mbed_error.h" -/* - * Purpose of this test is just to be empty baseline - * that does nothing, but includes all source files - * in the build. - * Do not add any tests here - */ - -class EmptyBaseline : public testing::Test { - virtual void SetUp() - { - } - - virtual void TearDown() - { - } -}; - -TEST_F(EmptyBaseline, constructor) +void mbed_sdk_init(void) { - EXPECT_TRUE(true); + // NOTE: Support singleton semantics to be called from other init functions + static int inited = 0; + if (inited) { + return; + } + inited = 1; + + SystemCoreClockUpdate(); } diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/objects.h b/targets/TARGET_NUVOTON/TARGET_M2354/objects.h new file mode 100644 index 0000000000..e95a865835 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/objects.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MBED_OBJECTS_H +#define MBED_OBJECTS_H + +#include "cmsis.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "PinNames.h" +#include "dma_api.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct gpio_irq_s { + PinName pin; + uint32_t irq_types; + uint32_t irq_handler; + uint32_t irq_id; + struct gpio_irq_s *next; +}; + +struct port_s { + PortName port; + uint32_t mask; + PinDirection direction; +}; + +struct analogin_s { + ADCName adc; + PinName pin; +}; + +struct dac_s { + DACName dac; + PinName pin; +}; + +struct serial_s { + UARTName uart; + PinName pin_tx; + PinName pin_rx; + PinName pin_rts; + PinName pin_cts; + + uint32_t baudrate; + uint32_t databits; + uint32_t parity; + uint32_t stopbits; + + void (*vec)(void); + uint32_t irq_handler; + uint32_t irq_id; + uint32_t irq_en; + uint32_t inten_msk; + + // Async transfer related fields + DMAUsage dma_usage_tx; + DMAUsage dma_usage_rx; + int dma_chn_id_tx; + int dma_chn_id_rx; + uint32_t event; + void (*irq_handler_tx_async)(void); + void (*irq_handler_rx_async)(void); +}; + +struct spi_s { + SPIName spi; + PinName pin_miso; + PinName pin_mosi; + PinName pin_sclk; + PinName pin_ssel; + + // Async transfer related fields + DMAUsage dma_usage; + int dma_chn_id_tx; + int dma_chn_id_rx; + uint32_t event; + uint32_t txrx_rmn; // Track tx/rx frames remaining in interrupt way + uint32_t hdlr_async; +}; + +struct i2c_s { + I2CName i2c; + PinName pin_sda; + PinName pin_scl; + int slaveaddr_state; + + uint32_t tran_ctrl; + char * tran_beg; + char * tran_pos; + char * tran_end; + int inten; + + // Async transfer related fields + DMAUsage dma_usage; + uint32_t event; + int stop; + uint32_t address; + uint32_t hdlr_async; +}; + +struct pwmout_s { + PWMName pwm; + PinName pin; + uint32_t period_us; + uint32_t pulsewidth_us; +}; + +struct sleep_s { + int powerdown; +}; + +struct trng_s { + uint8_t dummy; +}; + +#ifdef __cplusplus +} +#endif + +#include "gpio_object.h" + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/pinmap.c b/targets/TARGET_NUVOTON/TARGET_M2354/pinmap.c new file mode 100644 index 0000000000..88bd4fc13f --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/pinmap.c @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include "mbed_assert.h" +#include "pinmap.h" +#include "PortNames.h" +#include "PeripheralNames.h" +#include "mbed_error.h" + +/** + * Configure pin multi-function + */ +void pin_function(PinName pin, int data) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t pin_index = NU_PINNAME_TO_PIN(pin); + uint32_t port_index = NU_PINNAME_TO_PORT(pin); + + nu_pin_function_s(port_index, pin_index, (uint32_t) data); +} + +/** + * Configure pin pull-up/pull-down + */ +void pin_mode(PinName pin, PinMode mode) +{ + MBED_ASSERT(pin != (PinName)NC); + uint32_t pin_index = NU_PINNAME_TO_PIN(pin); + uint32_t port_index = NU_PINNAME_TO_PORT(pin); + GPIO_T *gpio_base = NU_PORT_BASE(port_index); + + uint32_t mode_intern = GPIO_MODE_INPUT; + + switch (mode) { + case InputOnly: + mode_intern = GPIO_MODE_INPUT; + break; + + case PushPullOutput: + mode_intern = GPIO_MODE_OUTPUT; + break; + + case OpenDrain: + mode_intern = GPIO_MODE_OPEN_DRAIN; + break; + + case QuasiBidirectional: + mode_intern = GPIO_MODE_QUASI; + break; + + default: + /* H/W doesn't support separate configuration for input pull mode/direction. + * We expect upper layer would have translated input pull mode/direction + * to I/O mode */ + return; + } + + GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern); + + /* Invalid combinations of PinMode/PinDirection + * + * We assume developer would avoid the following combinations of PinMode/PinDirection + * which are invalid: + * 1. InputOnly/PIN_OUTPUT + * 2. PushPullOutput/PIN_INPUT + */ +} + +/* List of peripherals excluded from testing */ +const PeripheralList *pinmap_restricted_peripherals() +{ + static const int perifs[] = { + USB_UART, // Dedicated to USB VCOM + }; + + static const PeripheralList peripheral_list = { + sizeof(perifs) / sizeof(perifs[0]), + perifs + }; + + return &peripheral_list; +} diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/port_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/port_api.c new file mode 100644 index 0000000000..36167e362c --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/port_api.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "port_api.h" +#include "gpio_api.h" +#include "pinmap.h" +#include "mbed_error.h" + +#if DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT + +PinName port_pin(PortName port, int pin_n) +{ + return (PinName) NU_PORT_N_PIN_TO_PINNAME(port, pin_n); +} + +void port_init(port_t *obj, PortName port, int mask, PinDirection dir) +{ + obj->port = port; + obj->mask = mask; + obj->direction = dir; + + uint32_t i; + obj->direction = dir; + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + gpio_set(port_pin(port, i)); + } + } + + port_dir(obj, dir); +} + +void port_dir(port_t *obj, PinDirection dir) +{ + uint32_t i; + obj->direction = dir; + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + if (dir == PIN_OUTPUT) { + GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_OUTPUT); + } else { // PIN_INPUT + GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_INPUT); + } + } + } +} + +void port_mode(port_t *obj, PinMode mode) +{ + uint32_t i; + + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + pin_mode(port_pin(obj->port, i), mode); + } + } +} + +void port_write(port_t *obj, int value) +{ + uint32_t i; + uint32_t port_index = obj->port; + + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + NU_SET_GPIO_PIN_DATA(port_index, i, (value & obj->mask) ? 1 : 0); + } + } +} + +int port_read(port_t *obj) +{ + uint32_t i; + uint32_t port_index = obj->port; + int value = 0; + + for (i = 0; i < GPIO_PIN_MAX; i++) { + if (obj->mask & (1 << i)) { + value = value | (NU_GET_GPIO_PIN_DATA(port_index, i) << i); + } + } + + return value; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/pwmout_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/pwmout_api.c new file mode 100644 index 0000000000..304f8c09fe --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/pwmout_api.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "pwmout_api.h" + +#if DEVICE_PWMOUT + +#include "cmsis.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" +#include "nu_bitutil.h" + +struct nu_pwm_var { + uint32_t en_msk; +}; + +static struct nu_pwm_var pwm0_var = { + .en_msk = 0 +}; + +static struct nu_pwm_var pwm1_var = { + .en_msk = 0 +}; + +static uint32_t pwm_modinit_mask = 0; + +static const struct nu_modinit_s pwm_modinit_tab[] = { + {PWM_0_0, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0_P0_IRQn, &pwm0_var}, + {PWM_0_1, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0_P0_IRQn, &pwm0_var}, + {PWM_0_2, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0_P1_IRQn, &pwm0_var}, + {PWM_0_3, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0_P1_IRQn, &pwm0_var}, + {PWM_0_4, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0_P2_IRQn, &pwm0_var}, + {PWM_0_5, EPWM0_MODULE, CLK_CLKSEL2_EPWM0SEL_PCLK0, 0, EPWM0_RST, EPWM0_P2_IRQn, &pwm0_var}, + + {PWM_1_0, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1_P0_IRQn, &pwm1_var}, + {PWM_1_1, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1_P0_IRQn, &pwm1_var}, + {PWM_1_2, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1_P1_IRQn, &pwm1_var}, + {PWM_1_3, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1_P1_IRQn, &pwm1_var}, + {PWM_1_4, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1_P2_IRQn, &pwm1_var}, + {PWM_1_5, EPWM1_MODULE, CLK_CLKSEL2_EPWM1SEL_PCLK1, 0, EPWM1_RST, EPWM1_P2_IRQn, &pwm1_var}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + +static void pwmout_config(pwmout_t* obj, int start); + +void pwmout_init(pwmout_t* obj, PinName pin) +{ + obj->pwm = (PWMName) pinmap_peripheral(pin, PinMap_PWM); + MBED_ASSERT((int) obj->pwm != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->pwm); + + obj->pin = pin; + + // Wire pinout + pinmap_pinout(pin, PinMap_PWM); + + // NOTE: Channels 0/1/2/3/4/5 share a clock source. + if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) { + /* Select IP clock source + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + /* Enable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_EnableModuleClock_S(modinit->clkidx); + } + + // NOTE: All channels (identified by PWMName) share a PWM module. This reset will also affect other channels of the same PWM module. + if (! ((struct nu_pwm_var *) modinit->var)->en_msk) { + /* Reset module + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule_S(modinit->rsetidx); + } + + uint32_t chn = NU_MODSUBINDEX(obj->pwm); + + // Default: period = 10 ms, pulse width = 0 ms + obj->period_us = 1000 * 10; + obj->pulsewidth_us = 0; + pwmout_config(obj, 0); + + ((struct nu_pwm_var *) modinit->var)->en_msk |= 1 << chn; + + // Mark this module to be inited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask |= 1 << i; +} + +void pwmout_free(pwmout_t* obj) +{ + EPWM_T *pwm_base = (EPWM_T *) NU_MODBASE(obj->pwm); + uint32_t chn = NU_MODSUBINDEX(obj->pwm); + EPWM_ForceStop(pwm_base, 1 << chn); + + const struct nu_modinit_s *modinit = get_modinit(obj->pwm, pwm_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->pwm); + ((struct nu_pwm_var *) modinit->var)->en_msk &= ~(1 << chn); + + + if ((((struct nu_pwm_var *) modinit->var)->en_msk & 0x3F) == 0) { + /* Disable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_DisableModuleClock_S(modinit->clkidx); + } + + // Mark this module to be deinited. + int i = modinit - pwm_modinit_tab; + pwm_modinit_mask &= ~(1 << i); + + // Free up pins + gpio_set(obj->pin); + obj->pin = NC; +} + +void pwmout_write(pwmout_t* obj, float value) +{ + obj->pulsewidth_us = NU_CLAMP((uint32_t) (value * obj->period_us), 0, obj->period_us); + pwmout_config(obj, 1); +} + +float pwmout_read(pwmout_t* obj) +{ + return NU_CLAMP((((float) obj->pulsewidth_us) / obj->period_us), 0.0f, 1.0f); +} + +void pwmout_period(pwmout_t* obj, float seconds) +{ + pwmout_period_us(obj, seconds * 1000000.0f); +} + +void pwmout_period_ms(pwmout_t* obj, int ms) +{ + pwmout_period_us(obj, ms * 1000); +} + +// Set the PWM period, keeping the duty cycle the same. +void pwmout_period_us(pwmout_t* obj, int us) +{ + uint32_t period_us_old = obj->period_us; + uint32_t pulsewidth_us_old = obj->pulsewidth_us; + obj->period_us = us; + obj->pulsewidth_us = NU_CLAMP(obj->period_us * pulsewidth_us_old / period_us_old, 0, obj->period_us); + pwmout_config(obj, 1); +} + +int pwmout_read_period_us(pwmout_t *obj) +{ + return obj->period_us; +} + +void pwmout_pulsewidth(pwmout_t* obj, float seconds) +{ + pwmout_pulsewidth_us(obj, seconds * 1000000.0f); +} + +void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) +{ + pwmout_pulsewidth_us(obj, ms * 1000); +} + +void pwmout_pulsewidth_us(pwmout_t* obj, int us) +{ + obj->pulsewidth_us = NU_CLAMP(us, 0, obj->period_us); + pwmout_config(obj, 1); +} + +int pwmout_read_pulsewidth_us(pwmout_t *obj) +{ + return obj->pulsewidth_us; +} + +static void pwmout_config(pwmout_t* obj, int start) +{ + EPWM_T *pwm_base = (EPWM_T *) NU_MODBASE(obj->pwm); + uint32_t chn = NU_MODSUBINDEX(obj->pwm); + + // To avoid abnormal pulse on (re-)configuration, follow the sequence: stop/configure(/re-start). + // NOTE: The issue is met in ARM mbed CI test tests-api-pwm on M487. + EPWM_ForceStop(pwm_base, 1 << chn); + + // NOTE: Support period < 1s + // NOTE: ARM mbed CI test fails due to first PWM pulse error. Workaround by: + // 1. Inverse duty cycle (10000 - duty) + // 2. Inverse PWM output polarity + // This trick is here to pass ARM mbed CI test. First PWM pulse error still remains. + EPWM_ConfigOutputChannel2(pwm_base, chn, 1000 * 1000, 10000 - obj->pulsewidth_us * 10000 / obj->period_us, obj->period_us); + pwm_base->POLCTL |= 1 << (EPWM_POLCTL_PINV0_Pos + chn); + + if (start) { + // Enable output of the specified PWM channel + EPWM_EnableOutput(pwm_base, 1 << chn); + EPWM_Start(pwm_base, 1 << chn); + } +} + +const PinMap *pwmout_pinmap() +{ + return PinMap_PWM; +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/rtc_api.c new file mode 100644 index 0000000000..9716d57981 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/rtc_api.c @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "rtc_api.h" + +#if DEVICE_RTC + +#include "mbed_wait_api.h" +#include "mbed_error.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" +#include "mbed_mktime.h" + +/* Secure attribution of RTC + * + * We need RTC to be secure for security concern. + * + * On M2351, configured to secure + * On M2354, hard-wired to secure + */ + +/* Micro seconds per second */ +#define NU_US_PER_SEC 1000000 +/* Timer clock per second + * + * NOTE: This dependents on real hardware. + */ +#define NU_RTCCLK_PER_SEC (__LXT) + +/* Strategy for implementation of RTC HAL + * + * H/W RTC just supports year range 2000~2099, which cannot fully cover POSIX time (starting since 2970) + * and date time of struct TM (starting since 1900). + * + * To conquer the difficulty, we don't use H/W RTC to keep real date time. Instead, we use it to keep + * elapsed time in seconds since one reference time point. The strategy would be: + * + * 1. Choose DATETIME_HWRTC_ORIGIN (00:00:00 UTC, Saturday, 1 January 2000) as reference time point of H/W RTC. + * 2. t_hwrtc_origin = DATETIME_HWRTC_ORIGIN in POSIX time + * 3. t_hwrtc_elapsed = t_hwrtc_origin + elapsed time since t_hwrtc_origin + * 4. t_write = POSIX time set by rtc_write(). + * 5. t_present = rtc_read() = t_write + (t_hwrtc_elapsed - t_hwrtc_origin) + * + * 1900 + * |---------------------------------------------------------------------------------| + * 1970 t_write t_present + * |---------|-------|-----------------|---------------------------------------------| + * + * 2000 + * |-----------------|---------------------------------------------------------------| + * t_hwrtc_origin t_hwrtc_elapsed + * + */ +/* Start year of struct TM*/ +#define NU_TM_YEAR0 1900 +/* Start year of POSIX time (set_time()/time()) */ +#define NU_POSIX_YEAR0 1970 +/* Start year of H/W RTC */ +#define NU_HWRTC_YEAR0 2000 + +/* RTC H/W origin time: 00:00:00 UTC, Saturday, 1 January 2000 */ +static const S_RTC_TIME_DATA_T DATETIME_HWRTC_ORIGIN = { + 2000, /* Year value, range between 2000 ~ 2099 */ + 1, /* Month value, range between 1 ~ 12 */ + 1, /* Day value, range between 1 ~ 31 */ + RTC_SATURDAY, /* Day of the week */ + 0, /* Hour value, range between 0 ~ 23 */ + 0, /* Minute value, range between 0 ~ 59 */ + 0, /* Second value, range between 0 ~ 59 */ + RTC_CLOCK_24, /* 12-Hour (RTC_CLOCK_12) / 24-Hour (RTC_CLOCK_24) */ + 0 /* RTC_AM / RTC_PM (used only for 12-Hour) */ +}; +/* t_hwrtc_origin initialized or not? */ +static bool t_hwrtc_origin_inited = 0; +/* POSIX time of DATETIME_HWRTC_ORIGIN (since 00:00:00 UTC, Thursday, 1 January 1970) */ +static time_t t_hwrtc_origin = 0; +/* POSIX time set by rtc_write() */ +static time_t t_write = 0; +/* Convert date time from H/W RTC to struct TM */ +static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc); + +void rtc_init(void) +{ + if (rtc_isenabled()) { + return; + } + + RTC_Open_S(NULL); + + /* POSIX time origin (00:00:00 UTC, Thursday, 1 January 1970) */ + rtc_write(0); +} + +void rtc_free(void) +{ + RTC_Close_S(); +} + +int rtc_isenabled(void) +{ + return nu_rtc_isenabled_s(); +} + +time_t rtc_read(void) +{ + /* NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency. + * RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect. + * NUC472/M453: Known issue + * M487: Fixed + */ + if (! rtc_isenabled()) { + rtc_init(); + } + + /* Used for intermediary between date time of H/W RTC and POSIX time */ + struct tm datetime_tm; + + if (! t_hwrtc_origin_inited) { + t_hwrtc_origin_inited = 1; + + /* Convert date time from H/W RTC to struct TM */ + rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &DATETIME_HWRTC_ORIGIN); + /* Convert date time of struct TM to POSIX time */ + if (! _rtc_maketime(&datetime_tm, &t_hwrtc_origin, RTC_FULL_LEAP_YEAR_SUPPORT)) { + return 0; + } + + /* Load t_write from RTC spare register to cross reset cycle */ + t_write = nu_rtc_read_spare_register_s(0); + } + + S_RTC_TIME_DATA_T hwrtc_datetime_2K_present; + RTC_WaitAccessEnable_S(); + RTC_GetDateAndTime_S(&hwrtc_datetime_2K_present); + /* Convert date time from H/W RTC to struct TM */ + rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &hwrtc_datetime_2K_present); + /* Convert date time of struct TM to POSIX time */ + time_t t_hwrtc_elapsed; + if (! _rtc_maketime(&datetime_tm, &t_hwrtc_elapsed, RTC_FULL_LEAP_YEAR_SUPPORT)) { + return 0; + } + + /* Present time in POSIX time */ + time_t t_present = t_write + (t_hwrtc_elapsed - t_hwrtc_origin); + return t_present; +} + +void rtc_write(time_t t) +{ + if (! rtc_isenabled()) { + rtc_init(); + } + + t_write = t; + + /* Store t_write to RTC spare register to cross reset cycle */ + nu_rtc_write_spare_register_s(0, t_write); + + RTC_WaitAccessEnable_S(); + RTC_SetDateAndTime_S((S_RTC_TIME_DATA_T *) &DATETIME_HWRTC_ORIGIN); + /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */ + wait_us((NU_US_PER_SEC / NU_RTCCLK_PER_SEC) * 3); +} + +/* + struct tm + tm_sec seconds after the minute 0-61 + tm_min minutes after the hour 0-59 + tm_hour hours since midnight 0-23 + tm_mday day of the month 1-31 + tm_mon months since January 0-11 + tm_year years since 1900 + tm_wday days since Sunday 0-6 + tm_yday days since January 1 0-365 + tm_isdst Daylight Saving Time flag +*/ +static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc) +{ + datetime_tm->tm_year = datetime_hwrtc->u32Year - NU_TM_YEAR0; + datetime_tm->tm_mon = datetime_hwrtc->u32Month - 1; + datetime_tm->tm_mday = datetime_hwrtc->u32Day; + datetime_tm->tm_wday = datetime_hwrtc->u32DayOfWeek; + datetime_tm->tm_hour = datetime_hwrtc->u32Hour; + if (datetime_hwrtc->u32TimeScale == RTC_CLOCK_12 && datetime_hwrtc->u32AmPm == RTC_PM) { + datetime_tm->tm_hour += 12; + } + datetime_tm->tm_min = datetime_hwrtc->u32Minute; + datetime_tm->tm_sec = datetime_hwrtc->u32Second; +} + +#endif /* #if DEVICE_RTC */ diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/serial_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/serial_api.c new file mode 100644 index 0000000000..42ad209ad2 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/serial_api.c @@ -0,0 +1,1274 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "serial_api.h" + +#if DEVICE_SERIAL + +#include "cmsis.h" +#include "mbed_error.h" +#include "mbed_assert.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "nu_modutil.h" +#include "nu_bitutil.h" +#include +#include + +#if DEVICE_SERIAL_ASYNCH +#include "dma_api.h" +#include "dma.h" +#endif + +struct nu_uart_var { + uint32_t ref_cnt; // Reference count of the H/W module + serial_t * obj; + uint32_t fifo_size_tx; + uint32_t fifo_size_rx; + void (*vec)(void); +#if DEVICE_SERIAL_ASYNCH + void (*vec_async)(void); + uint8_t pdma_perp_tx; + uint8_t pdma_perp_rx; +#endif +}; + +static void uart0_vec(void); +static void uart1_vec(void); +static void uart2_vec(void); +static void uart3_vec(void); +static void uart4_vec(void); +static void uart5_vec(void); +static void uart_irq(serial_t *obj); + +#if DEVICE_SERIAL_ASYNCH +static void uart0_vec_async(void); +static void uart1_vec_async(void); +static void uart2_vec_async(void); +static void uart3_vec_async(void); +static void uart4_vec_async(void); +static void uart5_vec_async(void); +static void uart_irq_async(serial_t *obj); + +static void uart_dma_handler_tx(uint32_t id, uint32_t event); +static void uart_dma_handler_rx(uint32_t id, uint32_t event); + +static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable); +static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable); +static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable); +static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq); +static int serial_write_async(serial_t *obj); +static int serial_read_async(serial_t *obj); + +static uint32_t serial_rx_event_check(serial_t *obj); +static uint32_t serial_tx_event_check(serial_t *obj); + +static int serial_is_tx_complete(serial_t *obj); +static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable); + +static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width); +static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width); +static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match); +static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable); +static int serial_is_rx_complete(serial_t *obj); + +static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch); +#endif + +static int serial_is_irq_en(serial_t *obj, SerialIrq irq); + +bool serial_can_deep_sleep(void); + +static struct nu_uart_var uart0_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart0_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart0_vec_async, + .pdma_perp_tx = PDMA_UART0_TX, + .pdma_perp_rx = PDMA_UART0_RX +#endif +}; +static struct nu_uart_var uart1_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart1_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart1_vec_async, + .pdma_perp_tx = PDMA_UART1_TX, + .pdma_perp_rx = PDMA_UART1_RX +#endif +}; +static struct nu_uart_var uart2_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart2_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart2_vec_async, + .pdma_perp_tx = PDMA_UART2_TX, + .pdma_perp_rx = PDMA_UART2_RX +#endif +}; +static struct nu_uart_var uart3_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart3_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart3_vec_async, + .pdma_perp_tx = PDMA_UART3_TX, + .pdma_perp_rx = PDMA_UART3_RX +#endif +}; +static struct nu_uart_var uart4_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart4_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart4_vec_async, + .pdma_perp_tx = PDMA_UART4_TX, + .pdma_perp_rx = PDMA_UART4_RX +#endif +}; +static struct nu_uart_var uart5_var = { + .ref_cnt = 0, + .obj = NULL, + .fifo_size_tx = 16, + .fifo_size_rx = 16, + .vec = uart5_vec, +#if DEVICE_SERIAL_ASYNCH + .vec_async = uart5_vec_async, + .pdma_perp_tx = PDMA_UART5_TX, + .pdma_perp_rx = PDMA_UART5_RX +#endif +}; + + +int stdio_uart_inited = 0; +serial_t stdio_uart; +static uint32_t uart_modinit_mask = 0; + +static const struct nu_modinit_s uart_modinit_tab[] = { + {UART_0, UART0_MODULE, CLK_CLKSEL2_UART0SEL_HIRC, CLK_CLKDIV0_UART0(1), UART0_RST, UART0_IRQn, &uart0_var}, + {UART_1, UART1_MODULE, CLK_CLKSEL2_UART1SEL_HIRC, CLK_CLKDIV0_UART1(1), UART1_RST, UART1_IRQn, &uart1_var}, + {UART_2, UART2_MODULE, CLK_CLKSEL2_UART2SEL_HIRC, CLK_CLKDIV4_UART2(1), UART2_RST, UART2_IRQn, &uart2_var}, + {UART_3, UART3_MODULE, CLK_CLKSEL2_UART3SEL_HIRC, CLK_CLKDIV4_UART3(1), UART3_RST, UART3_IRQn, &uart3_var}, + {UART_4, UART4_MODULE, CLK_CLKSEL3_UART4SEL_HIRC, CLK_CLKDIV4_UART4(1), UART4_RST, UART4_IRQn, &uart4_var}, + {UART_5, UART5_MODULE, CLK_CLKSEL3_UART5SEL_HIRC, CLK_CLKDIV4_UART5(1), UART5_RST, UART5_IRQn, &uart5_var}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + +extern void mbed_sdk_init(void); + +void serial_init(serial_t *obj, PinName tx, PinName rx) +{ + // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init(). + mbed_sdk_init(); + + // Determine which UART_x the pins are used for + uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX); + uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX); + // Get the peripheral name (UART_x) from the pins and assign it to the object + obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx); + MBED_ASSERT((int)obj->serial.uart != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + + obj->serial.pin_tx = tx; + obj->serial.pin_rx = rx; + obj->serial.pin_rts = NC; + obj->serial.pin_cts = NC; + + pinmap_pinout(tx, PinMap_UART_TX); + pinmap_pinout(rx, PinMap_UART_RX); + + if (! var->ref_cnt) { + /* Select IP clock source + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + /* Enable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_EnableModuleClock_S(modinit->clkidx); + + /* Reset module + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule_S(modinit->rsetidx); + + // Configure baudrate + int baudrate = 9600; + if (obj->serial.uart == STDIO_UART) { +#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE; +#endif + } else { +#if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE + baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE; +#endif + } + serial_baud(obj, baudrate); + + // Configure data bits, parity, and stop bits + serial_format(obj, 8, ParityNone, 1); + } + var->ref_cnt ++; + + obj->serial.vec = var->vec; + obj->serial.irq_en = 0; + +#if DEVICE_SERIAL_ASYNCH + obj->serial.dma_usage_tx = DMA_USAGE_NEVER; + obj->serial.dma_usage_rx = DMA_USAGE_NEVER; + obj->serial.event = 0; + obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; +#endif + + /* With support for checking H/W UART initialized or not, we allow serial_init(&stdio_uart) + * calls in even though H/W UART 'STDIO_UART' has initialized. When serial_init(&stdio_uart) + * calls in, we only need to set the 'stdio_uart_inited' flag. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); + stdio_uart_inited = 1; + } + + if (var->ref_cnt) { + // Mark this module to be inited. + int i = modinit - uart_modinit_tab; + uart_modinit_mask |= 1 << i; + } +} + +void serial_free(serial_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + + var->ref_cnt --; + if (! var->ref_cnt) { +#if DEVICE_SERIAL_ASYNCH + if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->serial.dma_chn_id_tx); + obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + } + if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->serial.dma_chn_id_rx); + obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + } +#endif + + do { + UART_Close((UART_T *) NU_MODBASE(obj->serial.uart)); + + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + NVIC_DisableIRQ(modinit->irq_n); + + /* Disable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_DisableModuleClock_S(modinit->clkidx); + } while (0); + } + + if (var->obj == obj) { + var->obj = NULL; + } + + /* Clear the 'stdio_uart_inited' flag when serial_free(&stdio_uart) calls in. */ + if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) { + MBED_ASSERT(obj->serial.uart == STDIO_UART); + stdio_uart_inited = 0; + } + + if (! var->ref_cnt) { + // Mark this module to be deinited. + int i = modinit - uart_modinit_tab; + uart_modinit_mask &= ~(1 << i); + } + + // Free up pins + gpio_set(obj->serial.pin_tx); + gpio_set(obj->serial.pin_rx); + gpio_set(obj->serial.pin_rts); + gpio_set(obj->serial.pin_cts); + obj->serial.pin_tx = NC; + obj->serial.pin_rx = NC; + obj->serial.pin_rts = NC; + obj->serial.pin_cts = NC; +} + +void serial_baud(serial_t *obj, int baudrate) +{ + // Flush Tx FIFO. Otherwise, output data may get lost on this change. + while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); + + obj->serial.baudrate = baudrate; + UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate); +} + +void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) +{ + // Flush Tx FIFO. Otherwise, output data may get lost on this change. + while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); + + // Sanity check arguments + MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8)); + MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || (parity == ParityForced1) || (parity == ParityForced0)); + MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); + + obj->serial.databits = data_bits; + obj->serial.parity = parity; + obj->serial.stopbits = stop_bits; + + uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 : + (data_bits == 6) ? UART_WORD_LEN_6 : + (data_bits == 7) ? UART_WORD_LEN_7 : + UART_WORD_LEN_8; + uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD : + (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN : + UART_PARITY_NONE; + uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1; + UART_SetLineConfig((UART_T *) NU_MODBASE(obj->serial.uart), + 0, // Don't change baudrate + databits_intern, + parity_intern, + stopbits_intern); +} + +#if DEVICE_SERIAL_FC + +void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) +{ + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + // Free up old rts/cts pins when they are different from new ones + if (obj->serial.pin_rts != rxflow) { + gpio_set(obj->serial.pin_rts); + obj->serial.pin_rts = rxflow; + } + if (obj->serial.pin_cts != txflow) { + gpio_set(obj->serial.pin_cts); + obj->serial.pin_cts = txflow; + } + + if (rxflow != NC) { + // Check if RTS pin matches. + uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS); + MBED_ASSERT(uart_rts == obj->serial.uart); + // Enable the pin for RTS function + pinmap_pinout(rxflow, PinMap_UART_RTS); + + // NOTE: Added in M480/M2351. Before configuring RTSACTLV, disable TX/RX. + uart_base->FUNCSEL |= UART_FUNCSEL_TXRXDIS_Msk; + while (uart_base->FIFOSTS & UART_FIFOSTS_TXRXACT_Msk); + // nRTS pin output is low level active + uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk; + // NOTE: Added in M480/M2351. After configuring RTSACTLV, re-enable TX/RX. + uart_base->FUNCSEL &= ~UART_FUNCSEL_TXRXDIS_Msk; + // Configure RTS trigger level to 8 bytes + uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES; + + if (type == FlowControlRTS || type == FlowControlRTSCTS) { + // Enable RTS + uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk; + } else { + // Disable RTS + uart_base->INTEN &= ~UART_INTEN_ATORTSEN_Msk; + /* Drive nRTS pin output to low-active. Allow the peer to be able to send data + * even though its CTS is still enabled. */ + uart_base->MODEM &= ~UART_MODEM_RTS_Msk; + } + } + + /* If CTS is disabled, we don't need to configure CTS. But to be consistent with + * RTS code above, we still configure CTS. */ + if (txflow != NC) { + // Check if CTS pin matches. + uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS); + MBED_ASSERT(uart_cts == obj->serial.uart); + // Enable the pin for CTS function + pinmap_pinout(txflow, PinMap_UART_CTS); + + // NOTE: Added in M480/M2351. Before configuring CTSACTLV, disable TX/RX. + uart_base->FUNCSEL |= UART_FUNCSEL_TXRXDIS_Msk; + while (uart_base->FIFOSTS & UART_FIFOSTS_TXRXACT_Msk); + // nCTS pin input is low level active + uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk; + // NOTE: Added in M480/M2351. After configuring CTSACTLV, re-enable TX/RX. + uart_base->FUNCSEL &= ~UART_FUNCSEL_TXRXDIS_Msk; + + if (type == FlowControlCTS || type == FlowControlRTSCTS) { + // Enable CTS + uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk; + } else { + // Disable CTS + uart_base->INTEN &= ~UART_INTEN_ATOCTSEN_Msk; + } + } +} + +#endif //DEVICE_SERIAL_FC + +void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) +{ + // Flush Tx FIFO. Otherwise, output data may get lost on this change. + while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); + + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + obj->serial.irq_handler = (uint32_t) handler; + obj->serial.irq_id = id; + + // Restore sync-mode vector + obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec; +} + +void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + obj->serial.irq_en = enable; + serial_enable_interrupt(obj, irq, enable); +} + +int serial_getc(serial_t *obj) +{ + // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation. + while (! serial_readable(obj)); + int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + + // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq. + // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively. + if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + } + + return c; +} + +void serial_putc(serial_t *obj, int c) +{ + // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation. + while (! serial_writable(obj)); + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c); + + // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq. + // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively. + if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + } +} + +int serial_readable(serial_t *obj) +{ + return ! UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))); +} + +int serial_writable(serial_t *obj) +{ + return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart))); +} + +int serial_tx_empty(serial_t *obj) +{ + return UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))); +} + +void serial_pinout_tx(PinName tx) +{ + pinmap_pinout(tx, PinMap_UART_TX); +} + +void serial_break_set(serial_t *obj) +{ + ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk; +} + +void serial_break_clear(serial_t *obj) +{ + ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk; +} + +static void uart0_vec(void) +{ + uart_irq(uart0_var.obj); +} + +static void uart1_vec(void) +{ + uart_irq(uart1_var.obj); +} + +static void uart2_vec(void) +{ + uart_irq(uart2_var.obj); +} + +static void uart3_vec(void) +{ + uart_irq(uart3_var.obj); +} + +static void uart4_vec(void) +{ + uart_irq(uart4_var.obj); +} + +static void uart5_vec(void) +{ + uart_irq(uart5_var.obj); +} + +static void uart_irq(serial_t *obj) +{ + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) { + // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read. + UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + if (obj->serial.irq_handler && serial_is_irq_en(obj, RxIrq)) { + // Call irq_handler() only when RxIrq is enabled + ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq); + } + } + + if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) { + // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write. + UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk); + if (obj->serial.irq_handler && serial_is_irq_en(obj, TxIrq)) { + // Call irq_handler() only when TxIrq is enabled + ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq); + } + } + + // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt. + uart_base->INTSTS = uart_base->INTSTS; + uart_base->FIFOSTS = uart_base->FIFOSTS; +} + + +#if DEVICE_SERIAL_ASYNCH +int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32); + + obj->serial.dma_usage_tx = hint; + serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx); + + // UART IRQ is necessary for both interrupt way and DMA way + serial_tx_enable_event(obj, event, 1); + serial_tx_buffer_set(obj, tx, tx_length, tx_width); + + int n_word = 0; + if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) { + // Interrupt way + n_word = serial_write_async(obj); + serial_tx_enable_interrupt(obj, handler, 1); + } else { + // DMA way + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + PDMA_T *pdma_base = dma_modbase(); + + pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel + PDMA_SetTransferMode(pdma_base, + obj->serial.dma_chn_id_tx, + ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA + 0, // Scatter-gather disabled + 0); // Scatter-gather descriptor address + PDMA_SetTransferCnt(pdma_base, + obj->serial.dma_chn_id_tx, + (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, + tx_length); + PDMA_SetTransferAddr(pdma_base, + obj->serial.dma_chn_id_tx, + (uint32_t) tx, // NOTE: + // NUC472: End of source address + // M451: Start of source address + // M480: Start of source address + // M2351: Start of source address + PDMA_SAR_INC, // Source address incremental + (uint32_t) NU_MODBASE(obj->serial.uart), // Destination address + PDMA_DAR_FIX); // Destination address fixed + PDMA_SetBurstType(pdma_base, + obj->serial.dma_chn_id_tx, + PDMA_REQ_SINGLE, // Single mode + 0); // Burst size + PDMA_EnableInt(pdma_base, + obj->serial.dma_chn_id_tx, + PDMA_INT_TRANS_DONE); // Interrupt type + // Register DMA event handler + dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); + serial_tx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + + ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer + } + + return n_word; +} + +void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) +{ + MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32); + + obj->serial.dma_usage_rx = hint; + serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx); + // DMA doesn't support char match, so fall back to IRQ if it is requested. + if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER && + (event & SERIAL_EVENT_RX_CHARACTER_MATCH) && + char_match != SERIAL_RESERVED_CHAR_MATCH) { + obj->serial.dma_usage_rx = DMA_USAGE_NEVER; + dma_channel_free(obj->serial.dma_chn_id_rx); + obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + } + + // UART IRQ is necessary for both interrupt way and DMA way + serial_rx_enable_event(obj, event, 1); + serial_rx_buffer_set(obj, rx, rx_length, rx_width); + serial_rx_set_char_match(obj, char_match); + + if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) { + // Interrupt way + serial_rx_enable_interrupt(obj, handler, 1); + } else { + // DMA way + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + PDMA_T *pdma_base = dma_modbase(); + + pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel + PDMA_SetTransferMode(pdma_base, + obj->serial.dma_chn_id_rx, + ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA + 0, // Scatter-gather disabled + 0); // Scatter-gather descriptor address + PDMA_SetTransferCnt(pdma_base, + obj->serial.dma_chn_id_rx, + (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, + rx_length); + PDMA_SetTransferAddr(pdma_base, + obj->serial.dma_chn_id_rx, + (uint32_t) NU_MODBASE(obj->serial.uart), // Source address + PDMA_SAR_FIX, // Source address fixed + (uint32_t) rx, // NOTE: + // NUC472: End of destination address + // M451: Start of destination address + // M480: Start of destination address + // M2351: Start of destination address + PDMA_DAR_INC); // Destination address incremental + PDMA_SetBurstType(pdma_base, + obj->serial.dma_chn_id_rx, + PDMA_REQ_SINGLE, // Single mode + 0); // Burst size + PDMA_EnableInt(pdma_base, + obj->serial.dma_chn_id_rx, + PDMA_INT_TRANS_DONE); // Interrupt type + // Register DMA event handler + dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL); + serial_rx_enable_interrupt(obj, handler, 1); + /* We needn't actually enable UART INT to go UART ISR -> handler. + * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler + * with serial_tx/rx_enable_interrupt having set up this call path. */ + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer + } +} + +void serial_tx_abort_asynch(serial_t *obj) +{ + // Flush Tx FIFO. Otherwise, output data may get lost on this change. + while (! UART_IS_TX_EMPTY((UART_T *) NU_MODBASE(obj->serial.uart))); + + if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) { + PDMA_T *pdma_base = dma_modbase(); + + if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { + PDMA_DisableInt(pdma_base, obj->serial.dma_chn_id_tx, PDMA_INT_TRANS_DONE); + // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. + pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx); + } + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk); + } + + // Necessary for both interrupt way and DMA way + serial_enable_interrupt(obj, TxIrq, 0); + serial_rollback_interrupt(obj, TxIrq); +} + +void serial_rx_abort_asynch(serial_t *obj) +{ + if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) { + PDMA_T *pdma_base = dma_modbase(); + + if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { + PDMA_DisableInt(pdma_base, obj->serial.dma_chn_id_rx, PDMA_INT_TRANS_DONE); + // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. + pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx); + } + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk); + } + + // Necessary for both interrupt way and DMA way + serial_enable_interrupt(obj, RxIrq, 0); + serial_rollback_interrupt(obj, RxIrq); +} + +uint8_t serial_tx_active(serial_t *obj) +{ + // NOTE: Judge by serial_is_irq_en(obj, TxIrq) doesn't work with sync/async modes interleaved. Change with TX FIFO empty flag. + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + return (obj->serial.vec == var->vec_async); +} + +uint8_t serial_rx_active(serial_t *obj) +{ + // NOTE: Judge by serial_is_irq_en(obj, RxIrq) doesn't work with sync/async modes interleaved. Change with RX FIFO empty flag. + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + return (obj->serial.vec == var->vec_async); +} + +int serial_irq_handler_asynch(serial_t *obj) +{ + int event_rx = 0; + int event_tx = 0; + + // Necessary for both interrupt way and DMA way + if (serial_is_irq_en(obj, RxIrq)) { + event_rx = serial_rx_event_check(obj); + if (event_rx) { + serial_rx_abort_asynch(obj); + } + } + + if (serial_is_irq_en(obj, TxIrq)) { + event_tx = serial_tx_event_check(obj); + if (event_tx) { + serial_tx_abort_asynch(obj); + } + } + + return (obj->serial.event & (event_rx | event_tx)); +} + +static void uart0_vec_async(void) +{ + uart_irq_async(uart0_var.obj); +} + +static void uart1_vec_async(void) +{ + uart_irq_async(uart1_var.obj); +} + +static void uart2_vec_async(void) +{ + uart_irq_async(uart2_var.obj); +} + +static void uart3_vec_async(void) +{ + uart_irq_async(uart3_var.obj); +} + +static void uart4_vec_async(void) +{ + uart_irq_async(uart4_var.obj); +} + +static void uart5_vec_async(void) +{ + uart_irq_async(uart5_var.obj); +} + +static void uart_irq_async(serial_t *obj) +{ + if (serial_is_irq_en(obj, RxIrq)) { + (*obj->serial.irq_handler_rx_async)(); + } + if (serial_is_irq_en(obj, TxIrq)) { + (*obj->serial.irq_handler_tx_async)(); + } +} + +static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match) +{ + obj->char_match = char_match; + obj->char_found = 0; +} + +static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable) +{ + obj->serial.event &= ~SERIAL_EVENT_TX_MASK; + obj->serial.event |= (event & SERIAL_EVENT_TX_MASK); + + if (event & SERIAL_EVENT_TX_COMPLETE) { + // N/A + } +} + +static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable) +{ + obj->serial.event &= ~SERIAL_EVENT_RX_MASK; + obj->serial.event |= (event & SERIAL_EVENT_RX_MASK); + + if (event & SERIAL_EVENT_RX_COMPLETE) { + // N/A + } + if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) { + // N/A + } + if (event & SERIAL_EVENT_RX_FRAMING_ERROR) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk); + } + if (event & SERIAL_EVENT_RX_PARITY_ERROR) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk); + } + if (event & SERIAL_EVENT_RX_OVERFLOW) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk); + } + if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) { + // N/A + } +} + +static int serial_is_tx_complete(serial_t *obj) +{ + // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way + return (obj->tx_buff.pos == obj->tx_buff.length); +} + +static int serial_is_rx_complete(serial_t *obj) +{ + return (obj->rx_buff.pos == obj->rx_buff.length); +} + +static uint32_t serial_tx_event_check(serial_t *obj) +{ + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) { + // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write. + UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk); + } + + uint32_t event = 0; + + if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) { + serial_write_async(obj); + } + + if (serial_is_tx_complete(obj)) { + event |= SERIAL_EVENT_TX_COMPLETE; + } + + return event; +} + +static uint32_t serial_rx_event_check(serial_t *obj) +{ + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) { + // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read. + UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + } + + uint32_t event = 0; + + if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) { + uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk; + } + if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) { + uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk; + event |= SERIAL_EVENT_RX_FRAMING_ERROR; + } + if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) { + uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk; + event |= SERIAL_EVENT_RX_PARITY_ERROR; + } + + if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) { + uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk; + event |= SERIAL_EVENT_RX_OVERFLOW; + } + + if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) { + serial_read_async(obj); + } + + if (serial_is_rx_complete(obj)) { + event |= SERIAL_EVENT_RX_COMPLETE; + } + if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) { + event |= SERIAL_EVENT_RX_CHARACTER_MATCH; + } + + return event; +} + +static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma) +{ + serial_t *obj = (serial_t *) id; + + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_ABORT) { + } + // Expect UART IRQ will catch this transfer done event + if (event_dma & DMA_EVENT_TRANSFER_DONE) { + obj->tx_buff.pos = obj->tx_buff.length; + } + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_TIMEOUT) { + } + + uart_irq_async(obj); +} + +static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma) +{ + serial_t *obj = (serial_t *) id; + + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_ABORT) { + } + // Expect UART IRQ will catch this transfer done event + if (event_dma & DMA_EVENT_TRANSFER_DONE) { + obj->rx_buff.pos = obj->rx_buff.length; + } + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_TIMEOUT) { + } + + uart_irq_async(obj); +} + +static int serial_write_async(serial_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart); + + uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx; + uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos; + if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) { + tx_fifo_busy = tx_fifo_max; + } + uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy; + if (tx_fifo_free == 0) { + // Simulate clear of the interrupt flag + if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + } + return 0; + } + + uint32_t bytes_per_word = obj->tx_buff.width / 8; + + uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos; + int n_words = 0; + while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) { + switch (bytes_per_word) { + case 4: + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); + case 2: + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); + case 1: + UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++); + } + + n_words ++; + tx_fifo_free -= bytes_per_word; + obj->tx_buff.pos ++; + } + + if (n_words) { + // Simulate clear of the interrupt flag + if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + } + } + + return n_words; +} + +static int serial_read_async(serial_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos; + + uint32_t bytes_per_word = obj->rx_buff.width / 8; + + uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos; + int n_words = 0; + while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) { + switch (bytes_per_word) { + case 4: + *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + case 2: + *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + case 1: + *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart))); + } + + n_words ++; + rx_fifo_busy -= bytes_per_word; + obj->rx_buff.pos ++; + + if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) && + obj->char_match != SERIAL_RESERVED_CHAR_MATCH) { + uint8_t *rx_cmp = rx; + switch (bytes_per_word) { + case 4: + rx_cmp -= 2; + case 2: + rx_cmp --; + case 1: + rx_cmp --; + } + if (*rx_cmp == obj->char_match) { + obj->char_found = 1; + break; + } + } + } + + if (n_words) { + // Simulate clear of the interrupt flag + if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) { + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + } + } + + return n_words; +} + +static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width) +{ + obj->tx_buff.buffer = (void *) tx; + obj->tx_buff.length = length; + obj->tx_buff.pos = 0; + obj->tx_buff.width = width; +} + +static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width) +{ + obj->rx_buff.buffer = rx; + obj->rx_buff.length = length; + obj->rx_buff.pos = 0; + obj->rx_buff.width = width; +} + +static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + // Necessary for both interrupt way and DMA way + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + // With our own async vector, tx/rx handlers can be different. + obj->serial.vec = var->vec_async; + obj->serial.irq_handler_tx_async = (void (*)(void)) handler; + serial_enable_interrupt(obj, TxIrq, enable); +} + +static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + // Necessary for both interrupt way and DMA way + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + // With our own async vector, tx/rx handlers can be different. + obj->serial.vec = var->vec_async; + obj->serial.irq_handler_rx_async = (void (*) (void)) handler; + serial_enable_interrupt(obj, RxIrq, enable); +} + +static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable) +{ + if (enable) { + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec); + NVIC_EnableIRQ(modinit->irq_n); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + // Multiple serial S/W objects for single UART H/W module possibly. + // Bind serial S/W object to UART H/W module as interrupt is enabled. + var->obj = obj; + + switch (irq) { + // NOTE: Setting inten_msk first to avoid race condition + case RxIrq: + obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + break; + case TxIrq: + obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk; + UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + break; + } + } else { // disable + switch (irq) { + case RxIrq: + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)); + obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); + break; + case TxIrq: + UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk); + obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk; + break; + } + } +} + +static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->serial.uart); + + struct nu_uart_var *var = (struct nu_uart_var *) modinit->var; + + obj->serial.vec = var->vec; + serial_enable_interrupt(obj, irq, obj->serial.irq_en); +} + +static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch) +{ + if (*dma_usage != DMA_USAGE_NEVER) { + if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_ch = dma_channel_allocate(DMA_CAP_NONE); + } + if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_usage = DMA_USAGE_NEVER; + } + } else { + dma_channel_free(*dma_ch); + *dma_ch = DMA_ERROR_OUT_OF_CHANNELS; + } +} + +#endif // #if DEVICE_SERIAL_ASYNCH + +static int serial_is_irq_en(serial_t *obj, SerialIrq irq) +{ + int inten_msk = 0; + + switch (irq) { + case RxIrq: + inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk); + break; + case TxIrq: + inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk; + break; + } + + return !! inten_msk; +} + +bool serial_can_deep_sleep(void) +{ + bool sleep_allowed = 1; + const struct nu_modinit_s *modinit = uart_modinit_tab; + while (modinit->var != NULL) { + struct nu_uart_var *uart_var = (struct nu_uart_var *) modinit->var; + UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname); + if (uart_var->ref_cnt > 0) { + if (!UART_IS_TX_EMPTY(uart_base)) { + sleep_allowed = 0; + break; + } + } + modinit++; + } + return sleep_allowed; +} + +const PinMap *serial_tx_pinmap() +{ + return PinMap_UART_TX; +} + +const PinMap *serial_rx_pinmap() +{ + return PinMap_UART_RX; +} + +const PinMap *serial_cts_pinmap() +{ + return PinMap_UART_CTS; +} + +const PinMap *serial_rts_pinmap() +{ + return PinMap_UART_RTS; +} + +#endif // #if DEVICE_SERIAL diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/sleep.c b/targets/TARGET_NUVOTON/TARGET_M2354/sleep.c new file mode 100644 index 0000000000..e135ef2127 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/sleep.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "sleep_api.h" + +#if DEVICE_SLEEP + +#include "cmsis.h" +#include "device.h" +#include "objects.h" +#include "PeripheralPins.h" +#include "platform/mbed_toolchain.h" +#include + +/* Merge SYS_UnlockReg_S()/CLK_Idle_S() or CLK_PowerDown_S()/SYS_LockReg_S() + * into nu_idle_s() or nu_powerdown_s() + * + * These APIs are secure calls. For performance, merge them into one when + * nu_idle_s() and nu_powerdown_s() are available. + * + * NOTE: MBED_WEAK gets unnecessary because nu_idle_s/nu_powerdown_s are always available + * since Mbed OS 6. + * NOTE: With ARMCLANG, MBED_WEAK doesn't cause nu_idle_s/nu_powerdown_s to link in even though + * they are strong symbols. Add MBED_USED to ensure they are linked in. + */ +void nu_idle_s(void); +void nu_powerdown_s(void); + +#if DEVICE_SERIAL +bool serial_can_deep_sleep(void); +#endif + +/** + * Enter idle mode, in which just CPU is halted. + */ +void hal_sleep(void) +{ + nu_idle_s(); +} + +/** + * Enter power-down mode, in which HXT/HIRC are halted. + */ +void hal_deepsleep(void) +{ +#if DEVICE_SERIAL + if (!serial_can_deep_sleep()) { + return; + } +#endif + + nu_powerdown_s(); +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/spi_api.c b/targets/TARGET_NUVOTON/TARGET_M2354/spi_api.c new file mode 100644 index 0000000000..3e6342935a --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/spi_api.c @@ -0,0 +1,956 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "spi_api.h" + +#if DEVICE_SPI + +#include "cmsis.h" +#include "mbed_error.h" +#include "pinmap.h" +#include "PeripheralPins.h" +#include "gpio_api.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" +#include "nu_bitutil.h" + +#if DEVICE_SPI_ASYNCH +#include "dma_api.h" +#include "dma.h" +#endif + +#define NU_SPI_FRAME_MIN 8 +#define NU_SPI_FRAME_MAX 32 + +struct nu_spi_var { +#if DEVICE_SPI_ASYNCH + uint8_t pdma_perp_tx; + uint8_t pdma_perp_rx; +#endif +}; + +static struct nu_spi_var spi0_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI0_TX, + .pdma_perp_rx = PDMA_SPI0_RX +#endif +}; +static struct nu_spi_var spi1_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI1_TX, + .pdma_perp_rx = PDMA_SPI1_RX +#endif +}; +static struct nu_spi_var spi2_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI2_TX, + .pdma_perp_rx = PDMA_SPI2_RX +#endif +}; +static struct nu_spi_var spi3_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_SPI3_TX, + .pdma_perp_rx = PDMA_SPI3_RX +#endif +}; +/* Degrade QSPI0 to SPI_4 for standard SPI usage */ +static struct nu_spi_var spi4_var = { +#if DEVICE_SPI_ASYNCH + .pdma_perp_tx = PDMA_QSPI0_TX, + .pdma_perp_rx = PDMA_QSPI0_RX +#endif +}; + +/* Change to QSPI version functions + * + * In most cases, we can control degraded QSPI H/W to standard through BSP SPI driver + * directly as if it is just SPI H/W. However, BSP SPI driver distinguishes among + * SPI H/W instances in below functions: + * + * SPI_Open + * SPI_Close + * SPI_SetBusClock + * SPI_GetBusClock + * + * In these cases, we must change to QSPI version instead for QSPI H/W. + */ +static int spi_is_qspi(spi_t *obj); + +/* Synchronous version of SPI_ENABLE()/SPI_DISABLE() macros + * + * The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI + * control logic is enabled/disabled, this bit indicates the real status of SPI controller. + * + * NOTE: All configurations shall be ready before calling SPI_ENABLE_SYNC(). + * NOTE: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, + * user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0 + * (by SPI_DISABLE_SYNC here). + */ +__STATIC_INLINE void SPI_ENABLE_SYNC(SPI_T *spi_base) +{ + if (! (spi_base->CTL & SPI_CTL_SPIEN_Msk)) { + SPI_ENABLE(spi_base); + } + while (! (spi_base->STATUS & SPI_STATUS_SPIENSTS_Msk)); +} +__STATIC_INLINE void SPI_DISABLE_SYNC(SPI_T *spi_base) +{ + if (spi_base->CTL & SPI_CTL_SPIEN_Msk) { + // NOTE: SPI H/W may get out of state without the busy check. + while (SPI_IS_BUSY(spi_base)); + + SPI_DISABLE(spi_base); + } + while (spi_base->STATUS & SPI_STATUS_SPIENSTS_Msk); +} + +#if DEVICE_SPI_ASYNCH +static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable); +static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable); +static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit); +static uint32_t spi_master_read_asynch(spi_t *obj); +static uint32_t spi_event_check(spi_t *obj); +static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable); +static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length); +static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx); +static uint8_t spi_get_data_width(spi_t *obj); +static int spi_is_tx_complete(spi_t *obj); +static int spi_is_rx_complete(spi_t *obj); +static int spi_writeable(spi_t * obj); +static int spi_readable(spi_t * obj); +static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma); +static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma); +static uint32_t spi_fifo_depth(spi_t *obj); +#endif + +static uint32_t spi_modinit_mask = 0; + +static const struct nu_modinit_s spi_modinit_tab[] = { + {SPI_0, SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK1, MODULE_NoMsk, SPI0_RST, SPI0_IRQn, &spi0_var}, + {SPI_1, SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PCLK0, MODULE_NoMsk, SPI1_RST, SPI1_IRQn, &spi1_var}, + {SPI_2, SPI2_MODULE, CLK_CLKSEL2_SPI2SEL_PCLK1, MODULE_NoMsk, SPI2_RST, SPI2_IRQn, &spi2_var}, + {SPI_3, SPI3_MODULE, CLK_CLKSEL2_SPI3SEL_PCLK0, MODULE_NoMsk, SPI3_RST, SPI3_IRQn, &spi3_var}, + /* Degrade QSPI0 to SPI_4 for standard SPI usage */ + {SPI_4, QSPI0_MODULE, CLK_CLKSEL2_QSPI0SEL_PCLK0, MODULE_NoMsk, QSPI0_RST, QSPI0_IRQn, &spi4_var}, + + {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL} +}; + +void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) +{ + // Determine which SPI_x the pins are used for + uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI); + uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO); + uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK); + uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL); + uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso); + uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel); + obj->spi.spi = (SPIName) pinmap_merge(spi_data, spi_cntl); + MBED_ASSERT((int)obj->spi.spi != NC); + + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + obj->spi.pin_mosi = mosi; + obj->spi.pin_miso = miso; + obj->spi.pin_sclk = sclk; + obj->spi.pin_ssel = ssel; + + pinmap_pinout(mosi, PinMap_SPI_MOSI); + pinmap_pinout(miso, PinMap_SPI_MISO); + pinmap_pinout(sclk, PinMap_SPI_SCLK); + pinmap_pinout(ssel, PinMap_SPI_SSEL); + + /* Select IP clock source + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv); + + /* Enable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_EnableModuleClock_S(modinit->clkidx); + + /* Reset module + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule_S(modinit->rsetidx); + +#if DEVICE_SPI_ASYNCH + obj->spi.dma_usage = DMA_USAGE_NEVER; + obj->spi.event = 0; + obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + + /* NOTE: We use vector to judge if asynchronous transfer is on-going (spi_active). + * At initial time, asynchronous transfer is not on-going and so vector must + * be cleared to zero for correct judgement. */ + NVIC_SetVector(modinit->irq_n, 0); +#endif + + // Mark this module to be inited. + int i = modinit - spi_modinit_tab; + spi_modinit_mask |= 1 << i; +} + +void spi_free(spi_t *obj) +{ +#if DEVICE_SPI_ASYNCH + if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->spi.dma_chn_id_tx); + obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + } + if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { + dma_channel_free(obj->spi.dma_chn_id_rx); + obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + } +#endif + + if (spi_is_qspi(obj)) { + QSPI_Close((QSPI_T *) NU_MODBASE(obj->spi.spi)); + } else { + SPI_Close((SPI_T *) NU_MODBASE(obj->spi.spi)); + } + + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + SPI_DisableInt(((SPI_T *) NU_MODBASE(obj->spi.spi)), (SPI_FIFO_RXOV_INT_MASK | SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK)); + NVIC_DisableIRQ(modinit->irq_n); + + /* Disable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_DisableModuleClock_S(modinit->clkidx); + + // Mark this module to be deinited. + int i = modinit - spi_modinit_tab; + spi_modinit_mask &= ~(1 << i); + + // Free up pins + gpio_set(obj->spi.pin_mosi); + gpio_set(obj->spi.pin_miso); + gpio_set(obj->spi.pin_sclk); + gpio_set(obj->spi.pin_ssel); + obj->spi.pin_mosi = NC; + obj->spi.pin_miso = NC; + obj->spi.pin_sclk = NC; + obj->spi.pin_ssel = NC; +} + +void spi_format(spi_t *obj, int bits, int mode, int slave) +{ + MBED_ASSERT(bits >= NU_SPI_FRAME_MIN && bits <= NU_SPI_FRAME_MAX); + + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_DISABLE_SYNC(spi_base); + + if (spi_is_qspi(obj)) { + QSPI_Open((QSPI_T *) spi_base, + slave ? QSPI_SLAVE : QSPI_MASTER, + (mode == 0) ? QSPI_MODE_0 : (mode == 1) ? QSPI_MODE_1 : (mode == 2) ? QSPI_MODE_2 : QSPI_MODE_3, + bits, + QSPI_GetBusClock((QSPI_T *)spi_base)); + } else { + SPI_Open(spi_base, + slave ? SPI_SLAVE : SPI_MASTER, + (mode == 0) ? SPI_MODE_0 : (mode == 1) ? SPI_MODE_1 : (mode == 2) ? SPI_MODE_2 : SPI_MODE_3, + bits, + SPI_GetBusClock(spi_base)); + } + // NOTE: Hardcode to be MSB first. + SPI_SET_MSB_FIRST(spi_base); + + if (! slave) { + // Master + if (obj->spi.pin_ssel != NC) { + // Configure SS as low active. + SPI_EnableAutoSS(spi_base, SPI_SS, SPI_SS_ACTIVE_LOW); + } else { + SPI_DisableAutoSS(spi_base); + } + } else { + // Slave + // Configure SS as low active. + spi_base->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk; + } + + /* NOTE: M451's/M480's/M2351's SPI_Open() will enable SPI transfer (SPI_CTL_SPIEN_Msk). + * We cannot use SPI_CTL_SPIEN_Msk for judgement of spi_active(). + * Judge with vector instead. */ +} + +void spi_frequency(spi_t *obj, int hz) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_DISABLE_SYNC(spi_base); + + if (spi_is_qspi(obj)) { + QSPI_SetBusClock((QSPI_T *) NU_MODBASE(obj->spi.spi), hz); + } else { + SPI_SetBusClock((SPI_T *) NU_MODBASE(obj->spi.spi), hz); + } +} + + +int spi_master_write(spi_t *obj, int value) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + PinName spi_miso = obj->spi.pin_miso; + + SPI_ENABLE_SYNC(spi_base); + + /* Wait for TX FIFO not full */ + while(! spi_writeable(obj)); + SPI_WRITE_TX(spi_base, value); + + /* Make inter-frame (SPI data frame) delay match configured suspend interval + * in no MISO case + * + * This API requires data write/read simultaneously. However, it can enlarge + * the inter-frame delay. The data flow for one call of this API would be: + * 1. Write data to TX FIFO when it is not full + * 2. Write delay consisting of TX FIFO to TX Shift Register... + * 3. Actual data transfer on SPI bus + * 4. Read delay consisting of RX FIFO from RX Shift Register... + * 5. Read data from RX FIFO when it is not empty + * Among above, S2&S4 contribute to the inter-frame delay. + * + * To favor no MISO case, we skip S4&S5. Thus, S2 can overlap with S3 and doesn't + * contribute to the inter-frame delay when data is written successively. The solution + * can cause RX FIFO overrun. Ignore it. + */ + int value2 = -1; + if (spi_miso != NC) { + /* Wait for RX FIFO not empty */ + while (! spi_readable(obj)); + value2 = SPI_READ_RX(spi_base); + } + + /* We don't call SPI_DISABLE_SYNC here for performance. */ + + return value2; +} + +int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, + char *rx_buffer, int rx_length, char write_fill) { + int total = (tx_length > rx_length) ? tx_length : rx_length; + + for (int i = 0; i < total; i++) { + char out = (i < tx_length) ? tx_buffer[i] : write_fill; + char in = spi_master_write(obj, out); + if (i < rx_length) { + rx_buffer[i] = in; + } + } + + return total; +} + +const PinMap *spi_master_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_master_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_master_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_master_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +const PinMap *spi_slave_mosi_pinmap() +{ + return PinMap_SPI_MOSI; +} + +const PinMap *spi_slave_miso_pinmap() +{ + return PinMap_SPI_MISO; +} + +const PinMap *spi_slave_clk_pinmap() +{ + return PinMap_SPI_SCLK; +} + +const PinMap *spi_slave_cs_pinmap() +{ + return PinMap_SPI_SSEL; +} + +#if DEVICE_SPISLAVE +int spi_slave_receive(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_ENABLE_SYNC(spi_base); + + return spi_readable(obj); +}; + +int spi_slave_read(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_ENABLE_SYNC(spi_base); + + // Wait for rx buffer full + while (! spi_readable(obj)); + int value = SPI_READ_RX(spi_base); + return value; +} + +void spi_slave_write(spi_t *obj, int value) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + SPI_ENABLE_SYNC(spi_base); + + // Wait for tx buffer empty + while(! spi_writeable(obj)); + SPI_WRITE_TX(spi_base, value); +} +#endif + +#if DEVICE_SPI_ASYNCH +void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + SPI_SET_DATA_WIDTH(spi_base, bit_width); + + obj->spi.dma_usage = hint; + spi_check_dma_usage(&obj->spi.dma_usage, &obj->spi.dma_chn_id_tx, &obj->spi.dma_chn_id_rx); + uint32_t data_width = spi_get_data_width(obj); + // Conditions to go DMA way: + // (1) No DMA support for non-8 multiple data width. + // (2) tx length >= rx length. Otherwise, as tx DMA is done, no bus activity for remaining rx. + if ((data_width % 8) || + (tx_length < rx_length)) { + obj->spi.dma_usage = DMA_USAGE_NEVER; + dma_channel_free(obj->spi.dma_chn_id_tx); + obj->spi.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS; + dma_channel_free(obj->spi.dma_chn_id_rx); + obj->spi.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS; + } + + // SPI IRQ is necessary for both interrupt way and DMA way + spi_enable_event(obj, event, 1); + spi_buffer_set(obj, tx, tx_length, rx, rx_length); + + SPI_ENABLE_SYNC(spi_base); + + // Initialize total SPI transfer frames + obj->spi.txrx_rmn = NU_MAX(tx_length, rx_length); + + if (obj->spi.dma_usage == DMA_USAGE_NEVER) { + // Interrupt way + spi_master_write_asynch(obj, spi_fifo_depth(obj) / 2); + spi_enable_vector_interrupt(obj, handler, 1); + spi_master_enable_interrupt(obj, 1); + } else { + // DMA way + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + PDMA_T *pdma_base = dma_modbase(); + + // Configure tx DMA + pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_tx; // Enable this DMA channel + PDMA_SetTransferMode(pdma_base, + obj->spi.dma_chn_id_tx, + ((struct nu_spi_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA + 0, // Scatter-gather disabled + 0); // Scatter-gather descriptor address + PDMA_SetTransferCnt(pdma_base, + obj->spi.dma_chn_id_tx, + (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, + tx_length); + PDMA_SetTransferAddr(pdma_base, + obj->spi.dma_chn_id_tx, + (uint32_t) tx, // NOTE: + // NUC472: End of source address + // M451/M480/M2351: Start of source address + PDMA_SAR_INC, // Source address incremental + (uint32_t) &spi_base->TX, // Destination address + PDMA_DAR_FIX); // Destination address fixed + PDMA_SetBurstType(pdma_base, + obj->spi.dma_chn_id_tx, + PDMA_REQ_SINGLE, // Single mode + 0); // Burst size + PDMA_EnableInt(pdma_base, + obj->spi.dma_chn_id_tx, + PDMA_INT_TRANS_DONE); // Interrupt type + // Register DMA event handler + dma_set_handler(obj->spi.dma_chn_id_tx, (uint32_t) spi_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL); + + // Configure rx DMA + pdma_base->CHCTL |= 1 << obj->spi.dma_chn_id_rx; // Enable this DMA channel + PDMA_SetTransferMode(pdma_base, + obj->spi.dma_chn_id_rx, + ((struct nu_spi_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA + 0, // Scatter-gather disabled + 0); // Scatter-gather descriptor address + PDMA_SetTransferCnt(pdma_base, + obj->spi.dma_chn_id_rx, + (data_width == 8) ? PDMA_WIDTH_8 : (data_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32, + rx_length); + PDMA_SetTransferAddr(pdma_base, + obj->spi.dma_chn_id_rx, + (uint32_t) &spi_base->RX, // Source address + PDMA_SAR_FIX, // Source address fixed + (uint32_t) rx, // NOTE: + // NUC472: End of destination address + // M451/M480/M2351: Start of destination address + PDMA_DAR_INC); // Destination address incremental + PDMA_SetBurstType(pdma_base, + obj->spi.dma_chn_id_rx, + PDMA_REQ_SINGLE, // Single mode + 0); // Burst size + PDMA_EnableInt(pdma_base, + obj->spi.dma_chn_id_rx, + PDMA_INT_TRANS_DONE); // Interrupt type + // Register DMA event handler + dma_set_handler(obj->spi.dma_chn_id_rx, (uint32_t) spi_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL); + + /* Start tx/rx DMA transfer + * + * If we have both PDMA and SPI interrupts enabled and PDMA priority is lower than SPI priority, + * we would trap in SPI interrupt handler endlessly with the sequence: + * + * 1. PDMA TX transfer done interrupt occurs and is well handled. + * 2. SPI RX FIFO threshold interrupt occurs. Trap here because PDMA RX transfer done interrupt doesn't get handled. + * 3. PDMA RX transfer done interrupt occurs but it cannot be handled due to above. + * + * To fix it, we don't enable SPI TX/RX threshold interrupts but keep SPI vector handler set to be called + * in PDMA TX/RX transfer done interrupt handlers (spi_dma_handler_tx/spi_dma_handler_rx). + */ + NVIC_SetVector(modinit->irq_n, handler); + + /* Order to enable PDMA TX/RX functions + * + * H/W spec: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are + * enabled, RX PDMA function cannot be enabled prior to TX PDMA function. User can enable + * TX PDMA function firstly or enable both functions simultaneously. + * Per real test, it is safer to start RX PDMA first and then TX PDMA. Otherwise, receive FIFO is + * subject to overflow by TX DMA. + * + * With the above conflicts, we enable PDMA TX/RX functions simultaneously. + */ + spi_base->PDMACTL |= (SPI_PDMACTL_TXPDMAEN_Msk | SPI_PDMACTL_RXPDMAEN_Msk); + + /* Don't enable SPI TX/RX threshold interrupts as commented above */ + } +} + +/** + * Abort an SPI transfer + * This is a helper function for event handling. When any of the events listed occurs, the HAL will abort any ongoing + * transfers + * @param[in] obj The SPI peripheral to stop + */ +void spi_abort_asynch(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + PDMA_T *pdma_base = dma_modbase(); + + if (obj->spi.dma_usage != DMA_USAGE_NEVER) { + // Receive FIFO Overrun in case of tx length > rx length on DMA way + if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) { + spi_base->STATUS = SPI_STATUS_RXOVIF_Msk; + } + + if (obj->spi.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) { + PDMA_DisableInt(pdma_base, obj->spi.dma_chn_id_tx, PDMA_INT_TRANS_DONE); + // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. + pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_tx); + } + SPI_DISABLE_TX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi))); + + if (obj->spi.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) { + PDMA_DisableInt(pdma_base, obj->spi.dma_chn_id_rx, PDMA_INT_TRANS_DONE); + // NOTE: On NUC472, next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown. + pdma_base->CHCTL &= ~(1 << obj->spi.dma_chn_id_rx); + } + SPI_DISABLE_RX_PDMA(((SPI_T *) NU_MODBASE(obj->spi.spi))); + } + + // Necessary for both interrupt way and DMA way + spi_enable_vector_interrupt(obj, 0, 0); + spi_master_enable_interrupt(obj, 0); + + /* Necessary for accessing FIFOCTL below */ + SPI_DISABLE_SYNC(spi_base); + + SPI_ClearRxFIFO(spi_base); + SPI_ClearTxFIFO(spi_base); +} + +/** + * Handle the SPI interrupt + * Read frames until the RX FIFO is empty. Write at most as many frames as were read. This way, + * it is unlikely that the RX FIFO will overflow. + * @param[in] obj The SPI peripheral that generated the interrupt + * @return + */ +uint32_t spi_irq_handler_asynch(spi_t *obj) +{ + // Check for SPI events + uint32_t event = spi_event_check(obj); + if (event) { + spi_abort_asynch(obj); + } + + return (obj->spi.event & event) | ((event & SPI_EVENT_COMPLETE) ? SPI_EVENT_INTERNAL_TRANSFER_COMPLETE : 0); +} + +uint8_t spi_active(spi_t *obj) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + /* Vector will be cleared when asynchronous transfer is finished or aborted. + Use it to judge if asynchronous transfer is on-going. */ + uint32_t vec = NVIC_GetVector(modinit->irq_n); + return vec ? 1 : 0; +} + +static int spi_is_qspi(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + return (spi_base == ((SPI_T *) QSPI0)); +} + +static int spi_writeable(spi_t * obj) +{ + // Receive FIFO must not be full to avoid receive FIFO overflow on next transmit/receive + return (! SPI_GET_TX_FIFO_FULL_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi)))); +} + +static int spi_readable(spi_t * obj) +{ + return ! SPI_GET_RX_FIFO_EMPTY_FLAG(((SPI_T *) NU_MODBASE(obj->spi.spi))); +} + +static void spi_enable_event(spi_t *obj, uint32_t event, uint8_t enable) +{ + obj->spi.event &= ~SPI_EVENT_ALL; + obj->spi.event |= (event & SPI_EVENT_ALL); + if (event & SPI_EVENT_RX_OVERFLOW) { + SPI_EnableInt((SPI_T *) NU_MODBASE(obj->spi.spi), SPI_FIFO_RXOV_INT_MASK); + } +} + +static void spi_enable_vector_interrupt(spi_t *obj, uint32_t handler, uint8_t enable) +{ + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + if (enable) { + NVIC_SetVector(modinit->irq_n, handler); + NVIC_EnableIRQ(modinit->irq_n); + } else { + NVIC_DisableIRQ(modinit->irq_n); + NVIC_SetVector(modinit->irq_n, 0); + } +} + +static void spi_master_enable_interrupt(spi_t *obj, uint8_t enable) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + if (enable) { + uint32_t fifo_depth = spi_fifo_depth(obj); + SPI_SetFIFO(spi_base, fifo_depth / 2, fifo_depth / 2); + // Enable tx/rx FIFO threshold interrupt + SPI_EnableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK); + } else { + SPI_DisableInt(spi_base, SPI_FIFO_RXTH_INT_MASK | SPI_FIFO_TXTH_INT_MASK); + } +} + +static uint32_t spi_event_check(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + uint32_t event = 0; + + if (obj->spi.dma_usage == DMA_USAGE_NEVER) { + uint32_t n_rec = spi_master_read_asynch(obj); + spi_master_write_asynch(obj, n_rec); + } + + if (spi_is_tx_complete(obj) && spi_is_rx_complete(obj)) { + event |= SPI_EVENT_COMPLETE; + } + + // Receive FIFO Overrun + if (spi_base->STATUS & SPI_STATUS_RXOVIF_Msk) { + spi_base->STATUS = SPI_STATUS_RXOVIF_Msk; + // In case of tx length > rx length on DMA way + if (obj->spi.dma_usage == DMA_USAGE_NEVER) { + event |= SPI_EVENT_RX_OVERFLOW; + } + } + + // Receive Time-Out + if (spi_base->STATUS & SPI_STATUS_RXTOIF_Msk) { + spi_base->STATUS = SPI_STATUS_RXTOIF_Msk; + // Not using this IF. Just clear it. + } + // Transmit FIFO Under-Run + if (spi_base->STATUS & SPI_STATUS_TXUFIF_Msk) { + spi_base->STATUS = SPI_STATUS_TXUFIF_Msk; + event |= SPI_EVENT_ERROR; + } + + return event; +} + +/** + * Send words from the SPI TX buffer until the send limit is reached or the TX FIFO is full + * tx_limit is provided to ensure that the number of SPI frames (words) in flight can be managed. + * @param[in] obj The SPI object on which to operate + * @param[in] tx_limit The maximum number of words to send + * @return The number of SPI words that have been transfered + */ +static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit) +{ + uint32_t n_words = 0; + uint8_t data_width = spi_get_data_width(obj); + uint8_t bytes_per_word = (data_width + 7) / 8; + uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos; + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + while (obj->spi.txrx_rmn && spi_writeable(obj)) { + if (spi_is_tx_complete(obj)) { + // Transmit dummy as transmit buffer is empty + SPI_WRITE_TX(spi_base, 0); + } else { + switch (bytes_per_word) { + case 4: + SPI_WRITE_TX(spi_base, nu_get32_le(tx)); + tx += 4; + break; + case 2: + SPI_WRITE_TX(spi_base, nu_get16_le(tx)); + tx += 2; + break; + case 1: + SPI_WRITE_TX(spi_base, *((uint8_t *) tx)); + tx += 1; + break; + } + + obj->tx_buff.pos ++; + } + n_words ++; + obj->spi.txrx_rmn --; + } + + //Return the number of words that have been sent + return n_words; +} + +/** + * Read SPI words out of the RX FIFO + * Continues reading words out of the RX FIFO until the following condition is met: + * o There are no more words in the FIFO + * OR BOTH OF: + * o At least as many words as the TX buffer have been received + * o At least as many words as the RX buffer have been received + * This way, RX overflows are not generated when the TX buffer size exceeds the RX buffer size + * @param[in] obj The SPI object on which to operate + * @return Returns the number of words extracted from the RX FIFO + */ +static uint32_t spi_master_read_asynch(spi_t *obj) +{ + uint32_t n_words = 0; + uint8_t data_width = spi_get_data_width(obj); + uint8_t bytes_per_word = (data_width + 7) / 8; + uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos; + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + while (spi_readable(obj)) { + if (spi_is_rx_complete(obj)) { + // Disregard as receive buffer is full + SPI_READ_RX(spi_base); + } else { + switch (bytes_per_word) { + case 4: { + uint32_t val = SPI_READ_RX(spi_base); + nu_set32_le(rx, val); + rx += 4; + break; + } + case 2: { + uint16_t val = SPI_READ_RX(spi_base); + nu_set16_le(rx, val); + rx += 2; + break; + } + case 1: + *rx ++ = SPI_READ_RX(spi_base); + break; + } + + obj->rx_buff.pos ++; + } + n_words ++; + } + + // Return the number of words received + return n_words; +} + +static void spi_buffer_set(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length) +{ + obj->tx_buff.buffer = (void *) tx; + obj->tx_buff.length = tx_length; + obj->tx_buff.pos = 0; + obj->tx_buff.width = spi_get_data_width(obj); + obj->rx_buff.buffer = rx; + obj->rx_buff.length = rx_length; + obj->rx_buff.pos = 0; + obj->rx_buff.width = spi_get_data_width(obj); +} + +static void spi_check_dma_usage(DMAUsage *dma_usage, int *dma_ch_tx, int *dma_ch_rx) +{ + if (*dma_usage != DMA_USAGE_NEVER) { + if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_ch_tx = dma_channel_allocate(DMA_CAP_NONE); + } + if (*dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_ch_rx = dma_channel_allocate(DMA_CAP_NONE); + } + + if (*dma_ch_tx == DMA_ERROR_OUT_OF_CHANNELS || *dma_ch_rx == DMA_ERROR_OUT_OF_CHANNELS) { + *dma_usage = DMA_USAGE_NEVER; + } + } + + if (*dma_usage == DMA_USAGE_NEVER) { + dma_channel_free(*dma_ch_tx); + *dma_ch_tx = DMA_ERROR_OUT_OF_CHANNELS; + dma_channel_free(*dma_ch_rx); + *dma_ch_rx = DMA_ERROR_OUT_OF_CHANNELS; + } +} + +static uint8_t spi_get_data_width(spi_t *obj) +{ + SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi); + + uint32_t data_width = ((spi_base->CTL & SPI_CTL_DWIDTH_Msk) >> SPI_CTL_DWIDTH_Pos); + if (data_width == 0) { + data_width = 32; + } + + return data_width; +} + +static int spi_is_tx_complete(spi_t *obj) +{ + return (obj->tx_buff.pos == obj->tx_buff.length); +} + +static int spi_is_rx_complete(spi_t *obj) +{ + return (obj->rx_buff.pos == obj->rx_buff.length); +} + +static void spi_dma_handler_tx(uint32_t id, uint32_t event_dma) +{ + spi_t *obj = (spi_t *) id; + + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_ABORT) { + } + // Expect SPI IRQ will catch this transfer done event + if (event_dma & DMA_EVENT_TRANSFER_DONE) { + obj->tx_buff.pos = obj->tx_buff.length; + } + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_TIMEOUT) { + } + + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n); + vec(); +} + +static void spi_dma_handler_rx(uint32_t id, uint32_t event_dma) +{ + spi_t *obj = (spi_t *) id; + + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_ABORT) { + } + // Expect SPI IRQ will catch this transfer done event + if (event_dma & DMA_EVENT_TRANSFER_DONE) { + obj->rx_buff.pos = obj->rx_buff.length; + } + // FIXME: Pass this error to caller + if (event_dma & DMA_EVENT_TIMEOUT) { + } + + const struct nu_modinit_s *modinit = get_modinit(obj->spi.spi, spi_modinit_tab); + MBED_ASSERT(modinit != NULL); + MBED_ASSERT(modinit->modname == (int) obj->spi.spi); + + void (*vec)(void) = (void (*)(void)) NVIC_GetVector(modinit->irq_n); + vec(); +} + +/** Return FIFO depth of the SPI peripheral + * + * @details + * M2351/M2354 + * SPI0/1/2/3 8 if data width <=16; 4 otherwise + */ +static uint32_t spi_fifo_depth(spi_t *obj) +{ + return (spi_get_data_width(obj) <= 16) ? 8 : 4; +} + +#endif + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M2354/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_M2354/us_ticker.c new file mode 100644 index 0000000000..3be5b88466 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M2354/us_ticker.c @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2020, Nuvoton Technology Corporation + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "us_ticker_api.h" + +#if DEVICE_USTICKER + +#include "sleep_api.h" +#include "mbed_assert.h" +#include "nu_modutil.h" +#include "nu_miscutil.h" + +/* We have the following policy for configuring security state of TIMER for us_ticer/lp_ticker: + * + * TIMER0: Hard-wired to secure for TF-M SPE use + * TIMER1: Hard-wired to secure for TF-M SPE use + * TIMER2: Configured to non-secure for NSPE use, including TF-M NSPE test + * TIMER3: Configured to non-secure for NSPE use + * TIMER4: Configured to non-secure for Mbed NSPE us_ticer exclusively + * TIMER5: Configured to non-secure for Mbed NSPE lp_ticer exclusively + */ + +/* Micro seconds per second */ +#define NU_US_PER_SEC 1000000 +/* Timer clock per us_ticker tick */ +#define NU_TMRCLK_PER_TICK 1 +/* Timer clock per second */ +#define NU_TMRCLK_PER_SEC (1000 * 1000) +/* Timer max counter bit size */ +#define NU_TMR_MAXCNT_BITSIZE 24 +/* Timer max counter */ +#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1) + +static void tmr4_vec(void); + +static const struct nu_modinit_s timer4_modinit = {TIMER_4, TMR4_MODULE, CLK_CLKSEL3_TMR4SEL_PCLK0, 0, TMR4_RST, TMR4_IRQn, (void *) tmr4_vec}; + +#define TIMER_MODINIT timer4_modinit + +/* Track ticker status */ +static volatile uint16_t ticker_inited = 0; + +#define TMR_CMP_MIN 2 +#define TMR_CMP_MAX 0xFFFFFFu + +void us_ticker_init(void) +{ + if (ticker_inited) { + /* By HAL spec, ticker_init allows the ticker to keep counting and disables the + * ticker interrupt. */ + us_ticker_disable_interrupt(); + return; + } + ticker_inited = 1; + + /* Select IP clock source + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_SetModuleClock_S(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv); + + /* Enable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_EnableModuleClock_S(TIMER_MODINIT.clkidx); + + /* Reset module + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + SYS_ResetModule_S(TIMER_MODINIT.rsetidx); + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + // Timer for normal counter + uint32_t clk_timer = TIMER_GetModuleClock(timer_base); + uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; + MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); + uint32_t cmp_timer = TMR_CMP_MAX; + MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); + // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480/M2351. In M451/M480/M2351, TIMER_CNT is updated continuously by default. + timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/; + timer_base->CMP = cmp_timer; + + NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var); + + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); + + TIMER_EnableInt(timer_base); + + TIMER_Start(timer_base); + /* Wait for timer to start counting and raise active flag */ + while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk)); +} + +void us_ticker_free(void) +{ + /* Disable interrupt */ + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); + + /* Disable IP clock + * + * NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure. + */ + CLK_DisableModuleClock_S(TIMER_MODINIT.clkidx); + + ticker_inited = 0; +} + +uint32_t us_ticker_read() +{ + if (! ticker_inited) { + us_ticker_init(); + } + + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK); +} + +void us_ticker_set_interrupt(timestamp_t timestamp) +{ + /* Clear any previously pending interrupts */ + us_ticker_clear_interrupt(); + NVIC_ClearPendingIRQ(TIMER_MODINIT.irq_n); + + /* In continuous mode, counter will be reset to zero with the following sequence: + * 1. Stop counting + * 2. Configure new CMP value + * 3. Restart counting + * + * This behavior is not what we want. To fix it, we could configure new CMP value + * without stopping counting first. + */ + TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname); + + /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of + * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */ + uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK; + cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX); + timer_base->CMP = cmp_timer; + + /* We can call ticker_irq_handler now. */ + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); +} + +void us_ticker_disable_interrupt(void) +{ + /* We cannot call ticker_irq_handler now. */ + NVIC_DisableIRQ(TIMER_MODINIT.irq_n); +} + +void us_ticker_clear_interrupt(void) +{ + TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname)); +} + +void us_ticker_fire_interrupt(void) +{ + // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here. + // This prevents a recursive loop under heavy load which can lead to a stack overflow. + NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n); + + /* We can call ticker_irq_handler now. */ + NVIC_EnableIRQ(TIMER_MODINIT.irq_n); +} + +const ticker_info_t* us_ticker_get_info() +{ + static const ticker_info_t info = { + NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK, + NU_TMR_MAXCNT_BITSIZE + }; + return &info; +} + +static void tmr4_vec(void) +{ + us_ticker_clear_interrupt(); + + // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler(); + us_ticker_irq_handler(); +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M251/CMakeLists.txt b/targets/TARGET_NUVOTON/TARGET_M251/CMakeLists.txt index 6b9bb26f2e..93ee521063 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/CMakeLists.txt +++ b/targets/TARGET_NUVOTON/TARGET_M251/CMakeLists.txt @@ -60,6 +60,7 @@ target_sources(mbed-m251 sleep.c spi_api.c us_ticker.c + watchdog_api.c ) target_include_directories(mbed-m251 diff --git a/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h b/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h index f15db1a9e1..a39a96dc7c 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h +++ b/targets/TARGET_NUVOTON/TARGET_M251/device/system_M251.h @@ -50,7 +50,11 @@ extern "C" { #define __HSI (48000000UL) /*!< PLL default output is 48MHz */ #define __SYS_OSC_CLK ( ___HSI) /*!< Main oscillator frequency */ +#if MBED_CONF_TARGET_HXT_PRESENT #define __SYSTEM_CLOCK (1UL*__HXT) +#else +#define __SYSTEM_CLOCK (1UL*__HIRC) +#endif extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ extern uint32_t CyclesPerUs; /*!< Cycles per micro second */ diff --git a/targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c index c05d1054ba..5845b8d2e3 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/lp_ticker.c @@ -31,7 +31,11 @@ /* Timer clock per lp_ticker tick */ #define NU_TMRCLK_PER_TICK 1 /* Timer clock per second */ +#if MBED_CONF_TARGET_LXT_PRESENT #define NU_TMRCLK_PER_SEC (__LXT) +#else +#define NU_TMRCLK_PER_SEC (__LIRC) +#endif /* Timer max counter bit size */ #define NU_TMR_MAXCNT_BITSIZE 24 /* Timer max counter */ @@ -40,7 +44,11 @@ static void tmr1_vec(void); /* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ +#if MBED_CONF_TARGET_LXT_PRESENT static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; +#else +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; +#endif #define TIMER_MODINIT timer1_modinit diff --git a/targets/TARGET_NUVOTON/TARGET_M251/mbed_overrides.c b/targets/TARGET_NUVOTON/TARGET_M251/mbed_overrides.c index b7a0af1002..db926f3436 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/mbed_overrides.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/mbed_overrides.c @@ -33,47 +33,61 @@ void mbed_sdk_init(void) /* Unlock protected registers */ SYS_UnlockReg(); -#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL) +#if MBED_CONF_TARGET_HXT_PRESENT /* HXT Enable: Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */ PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk); #endif +#if MBED_CONF_TARGET_LXT_PRESENT /* LXT Enable: Set X32_OUT(PF.4) and X32_IN(PF.5) to input mode */ PF->MODE &= ~(GPIO_MODE_MODE4_Msk | GPIO_MODE_MODE5_Msk); +#endif /* Enable HIRC clock (Internal RC 48MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); -#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL) +#if MBED_CONF_TARGET_HXT_PRESENT /* Enable HXT clock (external XTAL 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); +#else + /* Disable HXT clock (external XTAL 12MHz) */ + CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk); #endif - /* Enable LIRC for lp_ticker */ + /* Enable LIRC */ CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk); - /* Enable LXT for RTC */ +#if MBED_CONF_TARGET_LXT_PRESENT + /* Enable LXT */ CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk); +#else + /* Disable LXT */ + CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk); +#endif /* Wait for HIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); -#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL) +#if MBED_CONF_TARGET_HXT_PRESENT /* Wait for HXT clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); #endif /* Wait for LIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); +#if MBED_CONF_TARGET_LXT_PRESENT /* Wait for LXT clock ready */ CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk); +#endif -#if defined(NU_HXT_ENABLE) && (NU_HXT_ENABLE == 1UL) +#if MBED_CONF_TARGET_HXT_PRESENT /* HXT Enable: Disable digital input path of analog pin XT1_OUT to prevent leakage */ GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 2)); /* HXT Enable: Disable digital input path of analog pin XT1_IN to prevent leakage */ GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 3)); #endif +#if MBED_CONF_TARGET_LXT_PRESENT /* LXT Enable: Disable digital input path of analog pin X32_OUT to prevent leakage */ GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 4)); /* LXT Enable: Disable digital input path of analog pin XT32_IN to prevent leakage */ GPIO_DISABLE_DIGITAL_PATH(PF, (1ul << 5)); +#endif /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); diff --git a/targets/TARGET_NUVOTON/TARGET_M251/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M251/rtc_api.c index 3a06977b3f..5039db5b77 100644 --- a/targets/TARGET_NUVOTON/TARGET_M251/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M251/rtc_api.c @@ -26,6 +26,14 @@ #include "nu_miscutil.h" #include "mbed_mktime.h" +/* Not support LIRC-clocked RTC + * + * H/W doesn't support this path. + */ +#if !MBED_CONF_TARGET_LXT_PRESENT +#error "RTC can only clock by LXT but LXT is not present. Try disabling RTC by \"device_has_remove\" in mbed_app.json" +#endif + /* Micro seconds per second */ #define NU_US_PER_SEC 1000000 /* Timer clock per second diff --git a/targets/TARGET_NUVOTON/TARGET_M251/watchdog_api.c b/targets/TARGET_NUVOTON/TARGET_M251/watchdog_api.c new file mode 100644 index 0000000000..65f86685d2 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M251/watchdog_api.c @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2019-2020 Nuvoton Technology Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "watchdog_api.h" + +#if DEVICE_WATCHDOG + +#include "cmsis.h" + +/* Watchdog clock per second */ +#if MBED_CONF_TARGET_LXT_PRESENT +#define NU_WDTCLK_PER_SEC (__LXT) +#define NU_WDTCLK_PER_SEC_MAX (__LXT) +#define NU_WDTCLK_PER_SEC_MIN (__LXT) +#else +#define NU_WDTCLK_PER_SEC (__LIRC) +#define NU_WDTCLK_PER_SEC_MAX ((uint32_t) ((__LIRC) * 1.15f)) +#define NU_WDTCLK_PER_SEC_MIN ((uint32_t) ((__LIRC) * 0.85f)) +#endif + +/* Convert watchdog clock to nearest ms */ +#define NU_WDTCLK2MS(WDTCLK) (((WDTCLK) * 1000 + ((NU_WDTCLK_PER_SEC) / 2)) / (NU_WDTCLK_PER_SEC)) + +/* Convert ms to nearest watchdog clock */ +#define NU_MS2WDTCLK(MS) (((MS) * (NU_WDTCLK_PER_SEC) + 500) / 1000) + +/* List of hardware-supported watchdog timeout in clocks */ +#define NU_WDT_16CLK 16 +#define NU_WDT_64CLK 64 +#define NU_WDT_256CLK 256 +#define NU_WDT_1024CLK 1024 +#define NU_WDT_4096CLK 4096 +#define NU_WDT_16384CLK 16384 +#define NU_WDT_65536CLK 65536 +#define NU_WDT_262144CLK 262144 + +/* Watchdog reset delay + * + * 1. Cannot be too small. This is to avoid premature WDT reset in pieces of timeout cascading. + * 2. Cannot be too large. This is to pass Greentea reset_reason/watchdog_reset tests, which have e.g. 50~100 reset delay tolerance. + */ +#define NU_WDT_RESET_DELAY_RSTDSEL WDT_RESET_DELAY_130CLK + +/* Support watchdog timeout values beyond H/W + * + * Watchdog Timer H/W just supports timeout values of 2^4, 2^6, ..., 2^18 clocks. + * To extend the support range to 1 and UINT32_MAX, we cascade multiple small timeouts to + * reach one large timeout specified in hal_watchdog_init. + */ + +/* Track if WDT H/W has been initialized */ +static bool wdt_hw_inited = 0; +/* Hold initially-configured timeout in hal_watchdog_init */ +static uint32_t wdt_timeout_reload_ms = 0; +/* Track remaining timeout for cascading */ +static uint32_t wdt_timeout_rmn_clk = 0; + +static void watchdog_setup_cascade_timeout(void); +static void WDT_IRQHandler(void); + +watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) +{ + /* Check validity of arguments */ + if (! config || ! config->timeout_ms) { + return WATCHDOG_STATUS_INVALID_ARGUMENT; + } + + wdt_timeout_reload_ms = config->timeout_ms; + wdt_timeout_rmn_clk = NU_MS2WDTCLK(wdt_timeout_reload_ms); + + if (! wdt_hw_inited) { + wdt_hw_inited = 1; + + SYS_UnlockReg(); + + /* Enable IP module clock */ + CLK_EnableModuleClock(WDT_MODULE); + + /* Select IP clock source */ +#if MBED_CONF_TARGET_LXT_PRESENT + CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LXT, 0); +#else + CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0); +#endif + + SYS_LockReg(); + + /* Set up IP interrupt */ + NVIC_SetVector(WDT_IRQn, (uint32_t) WDT_IRQHandler); + NVIC_EnableIRQ(WDT_IRQn); + } + + watchdog_setup_cascade_timeout(); + + return WATCHDOG_STATUS_OK; +} + +void hal_watchdog_kick(void) +{ + /* If a watchdog is not running, this function does nothing */ + if (!(WDT->CTL & WDT_CTL_WDTEN_Msk)) { + return; + } + + wdt_timeout_rmn_clk = NU_MS2WDTCLK(wdt_timeout_reload_ms); + watchdog_setup_cascade_timeout(); +} + +watchdog_status_t hal_watchdog_stop(void) +{ + SYS_UnlockReg(); + + /* Clear all flags & Disable interrupt & Disable WDT */ + WDT->CTL = (WDT->CTL & ~(WDT_CTL_WDTEN_Msk | WDT_CTL_INTEN_Msk)) | (WDT_CTL_WKF_Msk | WDT_CTL_IF_Msk | WDT_CTL_RSTF_Msk); + + SYS_LockReg(); + + return WATCHDOG_STATUS_OK; +} + +uint32_t hal_watchdog_get_reload_value(void) +{ + return wdt_timeout_reload_ms; +} + +watchdog_features_t hal_watchdog_get_platform_features(void) +{ + watchdog_features_t wdt_feat; + + /* We can support timeout values between 1 and UINT32_MAX by cascading. */ + wdt_feat.max_timeout = UINT32_MAX; + /* Support re-configuring watchdog timer */ + wdt_feat.update_config = 1; + /* Support stopping watchdog timer */ + wdt_feat.disable_watchdog = 1; + /* Typical frequency of not calibrated watchdog clock in Hz */ + wdt_feat.clock_typical_frequency = NU_WDTCLK_PER_SEC; + /* Maximum frequency of not calibrated watchdog clock in Hz */ + wdt_feat.clock_max_frequency = NU_WDTCLK_PER_SEC_MAX; + + return wdt_feat; +} + +static void watchdog_setup_cascade_timeout(void) +{ + uint32_t wdt_timeout_clk_toutsel; + + if (wdt_timeout_rmn_clk >= NU_WDT_262144CLK) { + wdt_timeout_rmn_clk -= NU_WDT_262144CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW18; + } else if (wdt_timeout_rmn_clk >= NU_WDT_65536CLK) { + wdt_timeout_rmn_clk -= NU_WDT_65536CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW16; + } else if (wdt_timeout_rmn_clk >= NU_WDT_16384CLK) { + wdt_timeout_rmn_clk -= NU_WDT_16384CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW14; + } else if (wdt_timeout_rmn_clk >= NU_WDT_4096CLK) { + wdt_timeout_rmn_clk -= NU_WDT_4096CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW12; + } else if (wdt_timeout_rmn_clk >= NU_WDT_1024CLK) { + wdt_timeout_rmn_clk -= NU_WDT_1024CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW10; + } else if (wdt_timeout_rmn_clk >= NU_WDT_256CLK) { + wdt_timeout_rmn_clk -= NU_WDT_256CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW8; + } else if (wdt_timeout_rmn_clk >= NU_WDT_64CLK) { + wdt_timeout_rmn_clk -= NU_WDT_64CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW6; + } else if (wdt_timeout_rmn_clk >= NU_WDT_16CLK) { + wdt_timeout_rmn_clk -= NU_WDT_16CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW4; + } else if (wdt_timeout_rmn_clk) { + wdt_timeout_rmn_clk = 0; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW4; + } else { + /* WDT has timed-out and will restart system soon. We just disable interrupt to escape + * getting stuck in WDT ISR. */ + SYS_UnlockReg(); + + /* Clear all flags & Disable interrupt */ + WDT->CTL = (WDT->CTL & ~WDT_CTL_INTEN_Msk) | (WDT_CTL_WKF_Msk | WDT_CTL_IF_Msk | WDT_CTL_RSTF_Msk); + + SYS_LockReg(); + return; + } + + SYS_UnlockReg(); + + /* Configure reset delay on timeout */ + WDT->ALTCTL = NU_WDT_RESET_DELAY_RSTDSEL; + + /* Reset watchdog timer */ + WDT_RESET_COUNTER(); + + /* Configure another piece of cascaded WDT timeout */ + WDT->CTL = wdt_timeout_clk_toutsel | // Timeout interval + WDT_CTL_WDTEN_Msk | // Enable watchdog timer + WDT_CTL_INTEN_Msk | // Enable interrupt + WDT_CTL_WKF_Msk | // Clear wake-up flag + WDT_CTL_WKEN_Msk | // Enable wake-up on timeout + WDT_CTL_IF_Msk | // Clear interrupt flag + WDT_CTL_RSTF_Msk | // Clear reset flag + WDT_CTL_RSTEN_Msk; // Enable reset always to address cascaded timeout failure in interrupt disabled scenario e.g. Hard Fault + + SYS_LockReg(); +} + +void WDT_IRQHandler(void) +{ + /* Check WDT interrupt flag */ + if (WDT_GET_TIMEOUT_INT_FLAG()) { + /* Continue another piece of cascaded WDT timeout */ + watchdog_setup_cascade_timeout(); + } else { + /* Clear all flags */ + WDT->CTL |= (WDT_CTL_WKF_Msk | WDT_CTL_IF_Msk | WDT_CTL_RSTF_Msk); + } +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M261/CMakeLists.txt b/targets/TARGET_NUVOTON/TARGET_M261/CMakeLists.txt index 04b5be25e0..897c85f5c1 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/CMakeLists.txt +++ b/targets/TARGET_NUVOTON/TARGET_M261/CMakeLists.txt @@ -68,6 +68,7 @@ target_sources(mbed-m261 spi_api.c trng_api.cpp us_ticker.c + watchdog_api.c crypto/crypto-misc.cpp ) diff --git a/targets/TARGET_NUVOTON/TARGET_M261/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M261/lp_ticker.c index 379b3ef7da..f51df377f2 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/lp_ticker.c @@ -30,7 +30,11 @@ /* Timer clock per lp_ticker tick */ #define NU_TMRCLK_PER_TICK 1 /* Timer clock per second */ +#if MBED_CONF_TARGET_LXT_PRESENT #define NU_TMRCLK_PER_SEC (__LXT) +#else +#define NU_TMRCLK_PER_SEC (__LIRC) +#endif /* Timer max counter bit size */ #define NU_TMR_MAXCNT_BITSIZE 24 /* Timer max counter */ @@ -40,7 +44,11 @@ static void tmr1_vec(void); /* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ +#if MBED_CONF_TARGET_LXT_PRESENT static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; +#else +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; +#endif #define TIMER_MODINIT timer1_modinit diff --git a/targets/TARGET_NUVOTON/TARGET_M261/mbed_overrides.c b/targets/TARGET_NUVOTON/TARGET_M261/mbed_overrides.c index e29c3397e5..fb53f6c15c 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/mbed_overrides.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/mbed_overrides.c @@ -36,23 +36,37 @@ void mbed_sdk_init(void) /* Enable HIRC clock (Internal RC 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); +#if MBED_CONF_TARGET_HXT_PRESENT /* Enable HXT clock (external XTAL 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); - /* Enable LIRC for lp_ticker */ +#else + /* Disable HXT clock (external XTAL 12MHz) */ + CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk); +#endif + /* Enable LIRC */ CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk); - /* Enable LXT for RTC */ +#if MBED_CONF_TARGET_LXT_PRESENT + /* Enable LXT */ CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk); +#else + /* Disable LXT */ + CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk); +#endif /* Enable HIRC48 clock (Internal RC 48MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRC48EN_Msk); /* Wait for HIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); +#if MBED_CONF_TARGET_HXT_PRESENT /* Wait for HXT clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); +#endif /* Wait for LIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); +#if MBED_CONF_TARGET_LXT_PRESENT /* Wait for LXT clock ready */ CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk); +#endif /* Wait for HIRC48 clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRC48STB_Msk); diff --git a/targets/TARGET_NUVOTON/TARGET_M261/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M261/rtc_api.c index a0fc30a322..594a8be853 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M261/rtc_api.c @@ -25,13 +25,27 @@ #include "nu_miscutil.h" #include "mbed_mktime.h" +/* Not support LIRC-clocked RTC + * + * Though H/W supports this path, it is still not supported because: + * 1. RTC is trimmed only for 32.768 KHz LXT, not for other clock rates. + * 2. RTC's clock source will reset to default LXT on reset. This results in rtc_reset test failing. + */ +#if !MBED_CONF_TARGET_LXT_PRESENT +#error "RTC can only clock by LXT but LXT is not present. Try disabling RTC by \"device_has_remove\" in mbed_app.json" +#endif + /* Micro seconds per second */ #define NU_US_PER_SEC 1000000 /* Timer clock per second * * NOTE: This dependents on real hardware. */ +#if MBED_CONF_TARGET_LXT_PRESENT #define NU_RTCCLK_PER_SEC __LXT +#else +#define NU_RTCCLK_PER_SEC __LIRC +#endif /* Strategy for implementation of RTC HAL * @@ -85,7 +99,11 @@ static time_t t_write = 0; /* Convert date time from H/W RTC to struct TM */ static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc); +#if MBED_CONF_TARGET_LXT_PRESENT static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LXT, 0, 0, RTC_IRQn, NULL}; +#else +static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LIRC, 0, 0, RTC_IRQn, NULL}; +#endif void rtc_init(void) { diff --git a/targets/TARGET_NUVOTON/TARGET_M261/trng_api.cpp b/targets/TARGET_NUVOTON/TARGET_M261/trng_api.cpp index 18e928851a..cc5852646e 100644 --- a/targets/TARGET_NUVOTON/TARGET_M261/trng_api.cpp +++ b/targets/TARGET_NUVOTON/TARGET_M261/trng_api.cpp @@ -48,6 +48,25 @@ void trng_init(MBED_UNUSED trng_t *obj) /* Reset IP */ SYS_ResetModule(trng_modinit.rsetidx); +#if MBED_CONF_TARGET_LXT_PRESENT + /* 32K clock from (external) LXT */ +#else + /* 32K clock from LIRC32 */ + + /* Unlock protected registers */ + SYS_UnlockReg(); + + /* To access RTC registers, clock must be enabled first. */ + CLK_EnableModuleClock(RTC_MODULE); + + /* Enable 32K clock from LIRC32 */ + RTC->LXTCTL |= (RTC_LXTCTL_C32KS_Msk | RTC_LXTCTL_LIRC32KEN_Msk); + CLK_WaitClockReady(CLK_STATUS_LIRC32STB_Msk | CLK_STATUS_LXTSTB_Msk); + + /* Lock protected registers */ + SYS_LockReg(); +#endif + TRNG_T *trng_base = (TRNG_T *) NU_MODBASE(trng_modinit.modname); trng_base->ACT |= TRNG_ACT_ACT_Msk; diff --git a/targets/TARGET_NUVOTON/TARGET_M261/watchdog_api.c b/targets/TARGET_NUVOTON/TARGET_M261/watchdog_api.c new file mode 100644 index 0000000000..afe94e9453 --- /dev/null +++ b/targets/TARGET_NUVOTON/TARGET_M261/watchdog_api.c @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2019-2020 Nuvoton Technology Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "watchdog_api.h" + +#if DEVICE_WATCHDOG + +#include "cmsis.h" + +/* Watchdog clock per second */ +#if MBED_CONF_TARGET_LXT_PRESENT +#define NU_WDTCLK_PER_SEC (__LXT) +#define NU_WDTCLK_PER_SEC_MAX (__LXT) +#define NU_WDTCLK_PER_SEC_MIN (__LXT) +#else +#define NU_WDTCLK_PER_SEC (__LIRC) +#define NU_WDTCLK_PER_SEC_MAX ((uint32_t) ((__LIRC) * 1.5f)) +#define NU_WDTCLK_PER_SEC_MIN ((uint32_t) ((__LIRC) * 0.6f)) +#endif + +/* Convert watchdog clock to nearest ms */ +#define NU_WDTCLK2MS(WDTCLK) (((WDTCLK) * 1000 + ((NU_WDTCLK_PER_SEC) / 2)) / (NU_WDTCLK_PER_SEC)) + +/* Convert ms to nearest watchdog clock */ +#define NU_MS2WDTCLK(MS) (((MS) * (NU_WDTCLK_PER_SEC) + 500) / 1000) + +/* List of hardware-supported watchdog timeout in clocks */ +#define NU_WDT_16CLK 16 +#define NU_WDT_64CLK 64 +#define NU_WDT_256CLK 256 +#define NU_WDT_1024CLK 1024 +#define NU_WDT_4096CLK 4096 +#define NU_WDT_16384CLK 16384 +#define NU_WDT_65536CLK 65536 +#define NU_WDT_262144CLK 262144 + +/* Watchdog reset delay + * + * 1. Cannot be too small. This is to avoid premature WDT reset in pieces of timeout cascading. + * 2. Cannot be too large. This is to pass Greentea reset_reason/watchdog_reset tests, which have e.g. 50~100 reset delay tolerance. + */ +#define NU_WDT_RESET_DELAY_RSTDSEL WDT_RESET_DELAY_130CLK + +/* Support watchdog timeout values beyond H/W + * + * Watchdog Timer H/W just supports timeout values of 2^4, 2^6, ..., 2^18 clocks. + * To extend the support range to 1 and UINT32_MAX, we cascade multiple small timeouts to + * reach one large timeout specified in hal_watchdog_init. + */ + +/* Track if WDT H/W has been initialized */ +static bool wdt_hw_inited = 0; +/* Hold initially-configured timeout in hal_watchdog_init */ +static uint32_t wdt_timeout_reload_ms = 0; +/* Track remaining timeout for cascading */ +static uint32_t wdt_timeout_rmn_clk = 0; + +static void watchdog_setup_cascade_timeout(void); +static void WDT_IRQHandler(void); + +watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) +{ + /* Check validity of arguments */ + if (! config || ! config->timeout_ms) { + return WATCHDOG_STATUS_INVALID_ARGUMENT; + } + + wdt_timeout_reload_ms = config->timeout_ms; + wdt_timeout_rmn_clk = NU_MS2WDTCLK(wdt_timeout_reload_ms); + + if (! wdt_hw_inited) { + wdt_hw_inited = 1; + + SYS_UnlockReg(); + + /* Enable IP module clock */ + CLK_EnableModuleClock(WDT_MODULE); + + /* Select IP clock source */ +#if MBED_CONF_TARGET_LXT_PRESENT + CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LXT, 0); +#else + CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0); +#endif + + SYS_LockReg(); + + /* Set up IP interrupt */ + NVIC_SetVector(WDT_IRQn, (uint32_t) WDT_IRQHandler); + NVIC_EnableIRQ(WDT_IRQn); + } + + watchdog_setup_cascade_timeout(); + + return WATCHDOG_STATUS_OK; +} + +void hal_watchdog_kick(void) +{ + /* If a watchdog is not running, this function does nothing */ + if (!(WDT->CTL & WDT_CTL_WDTEN_Msk)) { + return; + } + + wdt_timeout_rmn_clk = NU_MS2WDTCLK(wdt_timeout_reload_ms); + watchdog_setup_cascade_timeout(); +} + +watchdog_status_t hal_watchdog_stop(void) +{ + SYS_UnlockReg(); + + /* Clear all flags & Disable interrupt & Disable WDT */ + WDT->CTL = (WDT->CTL & ~(WDT_CTL_WDTEN_Msk | WDT_CTL_INTEN_Msk)) | (WDT_CTL_WKF_Msk | WDT_CTL_IF_Msk | WDT_CTL_RSTF_Msk); + + SYS_LockReg(); + + return WATCHDOG_STATUS_OK; +} + +uint32_t hal_watchdog_get_reload_value(void) +{ + return wdt_timeout_reload_ms; +} + +watchdog_features_t hal_watchdog_get_platform_features(void) +{ + watchdog_features_t wdt_feat; + + /* We can support timeout values between 1 and UINT32_MAX by cascading. */ + wdt_feat.max_timeout = UINT32_MAX; + /* Support re-configuring watchdog timer */ + wdt_feat.update_config = 1; + /* Support stopping watchdog timer */ + wdt_feat.disable_watchdog = 1; + /* Typical frequency of not calibrated watchdog clock in Hz */ + wdt_feat.clock_typical_frequency = NU_WDTCLK_PER_SEC; + /* Maximum frequency of not calibrated watchdog clock in Hz */ + wdt_feat.clock_max_frequency = NU_WDTCLK_PER_SEC_MAX; + + return wdt_feat; +} + +static void watchdog_setup_cascade_timeout(void) +{ + uint32_t wdt_timeout_clk_toutsel; + + if (wdt_timeout_rmn_clk >= NU_WDT_262144CLK) { + wdt_timeout_rmn_clk -= NU_WDT_262144CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW18; + } else if (wdt_timeout_rmn_clk >= NU_WDT_65536CLK) { + wdt_timeout_rmn_clk -= NU_WDT_65536CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW16; + } else if (wdt_timeout_rmn_clk >= NU_WDT_16384CLK) { + wdt_timeout_rmn_clk -= NU_WDT_16384CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW14; + } else if (wdt_timeout_rmn_clk >= NU_WDT_4096CLK) { + wdt_timeout_rmn_clk -= NU_WDT_4096CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW12; + } else if (wdt_timeout_rmn_clk >= NU_WDT_1024CLK) { + wdt_timeout_rmn_clk -= NU_WDT_1024CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW10; + } else if (wdt_timeout_rmn_clk >= NU_WDT_256CLK) { + wdt_timeout_rmn_clk -= NU_WDT_256CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW8; + } else if (wdt_timeout_rmn_clk >= NU_WDT_64CLK) { + wdt_timeout_rmn_clk -= NU_WDT_64CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW6; + } else if (wdt_timeout_rmn_clk >= NU_WDT_16CLK) { + wdt_timeout_rmn_clk -= NU_WDT_16CLK; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW4; + } else if (wdt_timeout_rmn_clk) { + wdt_timeout_rmn_clk = 0; + wdt_timeout_clk_toutsel = WDT_TIMEOUT_2POW4; + } else { + /* WDT has timed-out and will restart system soon. We just disable interrupt to escape + * getting stuck in WDT ISR. */ + SYS_UnlockReg(); + + /* Clear all flags & Disable interrupt */ + WDT->CTL = (WDT->CTL & ~WDT_CTL_INTEN_Msk) | (WDT_CTL_WKF_Msk | WDT_CTL_IF_Msk | WDT_CTL_RSTF_Msk); + + SYS_LockReg(); + return; + } + + SYS_UnlockReg(); + + /* Configure reset delay on timeout */ + WDT->ALTCTL = NU_WDT_RESET_DELAY_RSTDSEL; + + /* Reset watchdog timer */ + WDT_RESET_COUNTER(); + + /* Configure another piece of cascaded WDT timeout */ + WDT->CTL = wdt_timeout_clk_toutsel | // Timeout interval + WDT_CTL_WDTEN_Msk | // Enable watchdog timer + WDT_CTL_INTEN_Msk | // Enable interrupt + WDT_CTL_WKF_Msk | // Clear wake-up flag + WDT_CTL_WKEN_Msk | // Enable wake-up on timeout + WDT_CTL_IF_Msk | // Clear interrupt flag + WDT_CTL_RSTF_Msk | // Clear reset flag + WDT_CTL_RSTEN_Msk; // Enable reset always to address cascaded timeout failure in interrupt disabled scenario e.g. Hard Fault + + SYS_LockReg(); +} + +void WDT_IRQHandler(void) +{ + /* Check WDT interrupt flag */ + if (WDT_GET_TIMEOUT_INT_FLAG()) { + /* Continue another piece of cascaded WDT timeout */ + watchdog_setup_cascade_timeout(); + } else { + /* Clear all flags */ + WDT->CTL |= (WDT_CTL_WKF_Msk | WDT_CTL_IF_Msk | WDT_CTL_RSTF_Msk); + } +} + +#endif diff --git a/targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c b/targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c index 67b0bd98c2..3f54444075 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/device/startup_M451Series.c @@ -265,10 +265,12 @@ void Reset_Handler(void) /* Disable Power-on Reset function */ SYS_DISABLE_POR(); - + +#if MBED_CONF_TARGET_HXT_PRESENT /* HXT Crystal Type Select: INV */ CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk; - +#endif + /** * NOTE 1: Unlock is required for perhaps some register access in SystemInit(). * NOTE 2: Because EBI (external SRAM) init is done in SystemInit(), SystemInit() must be called at the very start. diff --git a/targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.c b/targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.c index df23aec568..8130c774a9 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.c @@ -84,8 +84,10 @@ void SystemInit(void) { M32(GCR_BASE+0x14) |= BIT7; } +#if MBED_CONF_TARGET_HXT_PRESENT /* Force to use INV type with HXT */ CLK->PWRCTL &= ~CLK_PWRCTL_HXTSELTYP_Msk; +#endif SYS_LockReg(); diff --git a/targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.h b/targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.h index edb80e509a..4c944ed08a 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.h +++ b/targets/TARGET_NUVOTON/TARGET_M451/device/system_M451Series.h @@ -38,7 +38,11 @@ extern "C" { #define __SYS_OSC_CLK ( ___HSI) /* Main oscillator frequency */ +#if MBED_CONF_TARGET_HXT_PRESENT #define __SYSTEM_CLOCK (1*__HXT) +#else +#define __SYSTEM_CLOCK (1*__HIRC) +#endif extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ extern uint32_t CyclesPerUs; /*!< Cycles per micro second */ diff --git a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c index 1f5079668d..10b1ee2469 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c @@ -29,7 +29,11 @@ /* Timer clock per lp_ticker tick */ #define NU_TMRCLK_PER_TICK 1 /* Timer clock per second */ +#if MBED_CONF_TARGET_LXT_PRESENT #define NU_TMRCLK_PER_SEC (__LXT) +#else +#define NU_TMRCLK_PER_SEC (__LIRC) +#endif /* Timer max counter bit size */ #define NU_TMR_MAXCNT_BITSIZE 24 /* Timer max counter */ @@ -38,7 +42,11 @@ static void tmr1_vec(void); /* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ +#if MBED_CONF_TARGET_LXT_PRESENT static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; +#else +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; +#endif #define TIMER_MODINIT timer1_modinit diff --git a/targets/TARGET_NUVOTON/TARGET_M451/mbed_overrides.c b/targets/TARGET_NUVOTON/TARGET_M451/mbed_overrides.c index d98873577d..5571cd2998 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/mbed_overrides.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/mbed_overrides.c @@ -33,21 +33,35 @@ void mbed_sdk_init(void) /* Enable HIRC clock (Internal RC 22.1184MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); +#if MBED_CONF_TARGET_HXT_PRESENT /* Enable HXT clock (external XTAL 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); - /* Enable LIRC for lp_ticker */ +#else + /* Disable HXT clock (external XTAL 12MHz) */ + CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk); +#endif + /* Enable LIRC */ CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk); - /* Enable LXT for RTC */ +#if MBED_CONF_TARGET_LXT_PRESENT + /* Enable LXT */ CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk); +#else + /* Disable LXT */ + CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk); +#endif /* Wait for HIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); +#if MBED_CONF_TARGET_HXT_PRESENT /* Wait for HXT clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); +#endif /* Wait for LIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); +#if MBED_CONF_TARGET_LXT_PRESENT /* Wait for LXT clock ready */ CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk); +#endif /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); diff --git a/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c index 5c034c179d..b026d52334 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c @@ -24,13 +24,27 @@ #include "nu_miscutil.h" #include "mbed_mktime.h" +/* Not support LIRC-clocked RTC + * + * Though H/W supports this path, it is still not supported because: + * 1. RTC is trimmed only for 32.768 KHz LXT, not for other clock rates. + * 2. RTC's clock source will reset to default LXT on reset. This results in rtc_reset test failing. + */ +#if !MBED_CONF_TARGET_LXT_PRESENT +#error "RTC can only clock by LXT but LXT is not present. Try disabling RTC by \"device_has_remove\" in mbed_app.json" +#endif + /* Micro seconds per second */ #define NU_US_PER_SEC 1000000 /* Timer clock per second * * NOTE: This dependents on real hardware. */ +#if MBED_CONF_TARGET_LXT_PRESENT #define NU_RTCCLK_PER_SEC __LXT +#else +#define NU_RTCCLK_PER_SEC __LIRC +#endif /* Strategy for implementation of RTC HAL * @@ -84,7 +98,11 @@ static time_t t_write = 0; /* Convert date time from H/W RTC to struct TM */ static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc); +#if MBED_CONF_TARGET_LXT_PRESENT static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LXT, 0, 0, RTC_IRQn, NULL}; +#else +static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LIRC, 0, 0, RTC_IRQn, NULL}; +#endif void rtc_init(void) { diff --git a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c index 3b4f228b78..bf7cd866ce 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c @@ -71,7 +71,13 @@ void us_ticker_init(void) uint32_t clk_timer = TIMER_GetModuleClock(timer_base); uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + /* HIRC-clocked PLL fails to output 1MHz-aligned frequency + * + * PLL, clocked by HIRC instead of HXT, doesn't output 1MHz-aligned frequency. + */ +#if MBED_CONF_TARGET_HXT_PRESENT MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); +#endif uint32_t cmp_timer = TMR_CMP_MAX; MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default. diff --git a/targets/TARGET_NUVOTON/TARGET_M451/watchdog_api.c b/targets/TARGET_NUVOTON/TARGET_M451/watchdog_api.c index 5b8d459d87..aaa60b15d2 100644 --- a/targets/TARGET_NUVOTON/TARGET_M451/watchdog_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M451/watchdog_api.c @@ -21,26 +21,12 @@ #include "cmsis.h" -/* Define WDT clock source in target configuration option */ -#ifndef MBED_CONF_TARGET_WDT_CLKSRC_SEL -#define MBED_CONF_TARGET_WDT_CLKSRC_SEL LXT -#endif - -/* WDT clock source definition */ -#define NU_INTERN_WDT_CLKSRC_LXT 1 -#define NU_INTERN_WDT_CLKSRC_LIRC 2 - -/* WDT clock source selection */ -#define NU_INTERN_WDT_CLKSRC_SEL__(SEL) NU_INTERN_WDT_CLKSRC_##SEL -#define NU_INTERN_WDT_CLKSRC_SEL_(SEL) NU_INTERN_WDT_CLKSRC_SEL__(SEL) -#define NU_INTERN_WDT_CLKSRC_SEL NU_INTERN_WDT_CLKSRC_SEL_(MBED_CONF_TARGET_WDT_CLKSRC_SEL) - /* Watchdog clock per second */ -#if NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LXT +#if MBED_CONF_TARGET_LXT_PRESENT #define NU_WDTCLK_PER_SEC (__LXT) #define NU_WDTCLK_PER_SEC_MAX (__LXT) #define NU_WDTCLK_PER_SEC_MIN (__LXT) -#elif NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LIRC +#else #define NU_WDTCLK_PER_SEC (__LIRC) #define NU_WDTCLK_PER_SEC_MAX ((uint32_t) ((__LIRC) * 1.5f)) #define NU_WDTCLK_PER_SEC_MIN ((uint32_t) ((__LIRC) * 0.5f)) @@ -105,9 +91,9 @@ watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) CLK_EnableModuleClock(WDT_MODULE); /* Select IP clock source */ -#if NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LXT +#if MBED_CONF_TARGET_LXT_PRESENT CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LXT, 0); -#elif NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LIRC +#else CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0); #endif diff --git a/targets/TARGET_NUVOTON/TARGET_M480/device/system_M480.c b/targets/TARGET_NUVOTON/TARGET_M480/device/system_M480.c index 8bff1dc705..0ff7c7addb 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/device/system_M480.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/device/system_M480.c @@ -60,6 +60,7 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL; } +#if MBED_CONF_TARGET_HXT_PRESENT /** * @brief Set PF.2 and PF.3 to input mode * @param None @@ -73,6 +74,7 @@ static __INLINE void HXTInit(void) PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk); } +#endif /** * @brief Initialize the System @@ -106,7 +108,9 @@ void SystemInit (void) RTC->GPIOCTL1 &= ~(RTC_GPIOCTL1_CTLSEL4_Msk | RTC_GPIOCTL1_CTLSEL5_Msk | RTC_GPIOCTL1_CTLSEL6_Msk | RTC_GPIOCTL1_CTLSEL7_Msk); CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; +#if MBED_CONF_TARGET_HXT_PRESENT HXTInit(); +#endif #if MBED_CONF_TARGET_SPIM_CCM_ENABLE // Divert SRAM bank2 (32 KB) to CCM from SPIM cache diff --git a/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c index 56aa796de2..e6bc5e2ba2 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c @@ -31,7 +31,11 @@ /* Timer clock per lp_ticker tick */ #define NU_TMRCLK_PER_TICK 1 /* Timer clock per second */ +#if MBED_CONF_TARGET_LXT_PRESENT #define NU_TMRCLK_PER_SEC (__LXT) +#else +#define NU_TMRCLK_PER_SEC (__LIRC) +#endif /* Timer max counter bit size */ #define NU_TMR_MAXCNT_BITSIZE 24 /* Timer max counter */ @@ -40,7 +44,11 @@ static void tmr1_vec(void); /* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ +#if MBED_CONF_TARGET_LXT_PRESENT static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; +#else +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; +#endif #define TIMER_MODINIT timer1_modinit diff --git a/targets/TARGET_NUVOTON/TARGET_M480/mbed_overrides.c b/targets/TARGET_NUVOTON/TARGET_M480/mbed_overrides.c index a6db2db539..986a3f8d05 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/mbed_overrides.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/mbed_overrides.c @@ -35,21 +35,35 @@ void mbed_sdk_init(void) /* Enable HIRC clock (Internal RC 22.1184MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); +#if MBED_CONF_TARGET_HXT_PRESENT /* Enable HXT clock (external XTAL 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); - /* Enable LIRC for lp_ticker */ +#else + /* Disable HXT clock (external XTAL 12MHz) */ + CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk); +#endif + /* Enable LIRC */ CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk); - /* Enable LXT for RTC */ +#if MBED_CONF_TARGET_LXT_PRESENT + /* Enable LXT */ CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk); +#else + /* Disable LXT */ + CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk); +#endif /* Wait for HIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); +#if MBED_CONF_TARGET_HXT_PRESENT /* Wait for HXT clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); +#endif /* Wait for LIRC clock ready */ CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); +#if MBED_CONF_TARGET_LXT_PRESENT /* Wait for LXT clock ready */ CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk); +#endif /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); diff --git a/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c index 92f49376db..6488c8f1d1 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c @@ -26,13 +26,27 @@ #include "nu_miscutil.h" #include "mbed_mktime.h" +/* Not support LIRC-clocked RTC + * + * Though H/W supports this path, it is still not supported because: + * 1. RTC is trimmed only for 32.768 KHz LXT, not for other clock rates. + * 2. RTC's clock source will reset to default LXT on reset. This results in rtc_reset test failing. + */ +#if !MBED_CONF_TARGET_LXT_PRESENT +#error "RTC can only clock by LXT but LXT is not present. Try disabling RTC by \"device_has_remove\" in mbed_app.json" +#endif + /* Micro seconds per second */ #define NU_US_PER_SEC 1000000 /* Timer clock per second * * NOTE: This dependents on real hardware. */ +#if MBED_CONF_TARGET_LXT_PRESENT #define NU_RTCCLK_PER_SEC __LXT +#else +#define NU_RTCCLK_PER_SEC __LIRC +#endif /* Strategy for implementation of RTC HAL * @@ -86,7 +100,11 @@ static time_t t_write = 0; /* Convert date time from H/W RTC to struct TM */ static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc); +#if MBED_CONF_TARGET_LXT_PRESENT static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LXT, 0, 0, RTC_IRQn, NULL}; +#else +static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, CLK_CLKSEL3_RTCSEL_LIRC, 0, 0, RTC_IRQn, NULL}; +#endif void rtc_init(void) { diff --git a/targets/TARGET_NUVOTON/TARGET_M480/watchdog_api.c b/targets/TARGET_NUVOTON/TARGET_M480/watchdog_api.c index 18e160da3e..4157e30940 100644 --- a/targets/TARGET_NUVOTON/TARGET_M480/watchdog_api.c +++ b/targets/TARGET_NUVOTON/TARGET_M480/watchdog_api.c @@ -22,26 +22,12 @@ #include "cmsis.h" -/* Define WDT clock source in target configuration option */ -#ifndef MBED_CONF_TARGET_WDT_CLKSRC_SEL -#define MBED_CONF_TARGET_WDT_CLKSRC_SEL LXT -#endif - -/* WDT clock source definition */ -#define NU_INTERN_WDT_CLKSRC_LXT 1 -#define NU_INTERN_WDT_CLKSRC_LIRC 2 - -/* WDT clock source selection */ -#define NU_INTERN_WDT_CLKSRC_SEL__(SEL) NU_INTERN_WDT_CLKSRC_##SEL -#define NU_INTERN_WDT_CLKSRC_SEL_(SEL) NU_INTERN_WDT_CLKSRC_SEL__(SEL) -#define NU_INTERN_WDT_CLKSRC_SEL NU_INTERN_WDT_CLKSRC_SEL_(MBED_CONF_TARGET_WDT_CLKSRC_SEL) - /* Watchdog clock per second */ -#if NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LXT +#if MBED_CONF_TARGET_LXT_PRESENT #define NU_WDTCLK_PER_SEC (__LXT) #define NU_WDTCLK_PER_SEC_MAX (__LXT) #define NU_WDTCLK_PER_SEC_MIN (__LXT) -#elif NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LIRC +#else #define NU_WDTCLK_PER_SEC (__LIRC) #define NU_WDTCLK_PER_SEC_MAX ((uint32_t) ((__LIRC) * 2.0f)) #define NU_WDTCLK_PER_SEC_MIN ((uint32_t) ((__LIRC) * 0.5f)) @@ -106,9 +92,9 @@ watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) CLK_EnableModuleClock(WDT_MODULE); /* Select IP clock source */ -#if NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LXT +#if MBED_CONF_TARGET_LXT_PRESENT CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LXT, 0); -#elif NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LIRC +#else CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0); #endif diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c index 9162337f5d..190e4358bb 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c @@ -29,7 +29,11 @@ /* Timer clock per lp_ticker tick */ #define NU_TMRCLK_PER_TICK 1 /* Timer clock per second */ +#if MBED_CONF_TARGET_LXT_PRESENT #define NU_TMRCLK_PER_SEC (__LXT) +#else +#define NU_TMRCLK_PER_SEC (__LIRC) +#endif /* Timer max counter bit size */ #define NU_TMR_MAXCNT_BITSIZE 24 /* Timer max counter */ @@ -40,7 +44,11 @@ void TMR1_IRQHandler(void); /* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ +#if MBED_CONF_TARGET_LXT_PRESENT static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1_S_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) TMR1_IRQHandler}; +#else +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1_S_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) TMR1_IRQHandler}; +#endif #define TIMER_MODINIT timer1_modinit diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/mbed_overrides.c b/targets/TARGET_NUVOTON/TARGET_NANO100/mbed_overrides.c index 9e2e10082e..a88d2b52e8 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/mbed_overrides.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/mbed_overrides.c @@ -33,24 +33,42 @@ void mbed_sdk_init(void) /* Enable HIRC clock (internal OSC 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HIRC_EN_Msk); +#if MBED_CONF_TARGET_HXT_PRESENT /* Enable HXT clock (external XTAL 12MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk); - /* Enable LIRC clock (OSC 10KHz) for lp_ticker */ +#else + /* Disable HXT clock (external XTAL 12MHz) */ + CLK_DisableXtalRC(CLK_PWRCTL_HXT_EN_Msk); +#endif + /* Enable LIRC clock (OSC 10KHz) */ CLK_EnableXtalRC(CLK_PWRCTL_LIRC_EN_Msk); - /* Enable LXT clock (XTAL 32KHz) for RTC */ +#if MBED_CONF_TARGET_LXT_PRESENT + /* Enable LXT clock (XTAL 32KHz) */ CLK_EnableXtalRC(CLK_PWRCTL_LXT_EN_Msk); +#else + /* Disable LXT clock (XTAL 32KHz) */ + CLK_DisableXtalRC(CLK_PWRCTL_LXT_EN_Msk); +#endif /* Wait for HIRC clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_HIRC_STB_Msk); +#if MBED_CONF_TARGET_HXT_PRESENT /* Wait for HXT clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk); +#endif /* Wait for LIRC clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_LIRC_STB_Msk); +#if MBED_CONF_TARGET_LXT_PRESENT /* Wait for LXT clock ready */ CLK_WaitClockReady(CLK_CLKSTATUS_LXT_STB_Msk); +#endif - /* Set HCLK source form HXT and HCLK source divide 1 */ + /* Set HCLK source form HXT/HIRC and HCLK source divide 1 */ +#if MBED_CONF_TARGET_HXT_PRESENT CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT, CLK_HCLK_CLK_DIVIDER(1)); +#else + CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_HCLK_CLK_DIVIDER(1)); +#endif /* Select HXT/HIRC to clock PLL * @@ -75,6 +93,10 @@ void mbed_sdk_init(void) #define NU_CLOCK_PLL NU_HIRC_PLL #endif +#if (NU_CLOCK_PLL == NU_HXT_PLL) && (MBED_CONF_TARGET_HXT_PRESENT == 0) +#error "HXT is not present to clock PLL" +#endif + #if (NU_CLOCK_PLL == NU_HXT_PLL) CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, FREQ_48MHZ*2); CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2)); diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c index 64d1cbacc2..2a117468f1 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c @@ -24,6 +24,14 @@ #include "nu_miscutil.h" #include "mbed_mktime.h" +/* Not support LIRC-clocked RTC + * + * H/W doesn't support this path. + */ +#if !MBED_CONF_TARGET_LXT_PRESENT +#error "RTC can only clock by LXT but LXT is not present. Try disabling RTC by \"device_has_remove\" in mbed_app.json" +#endif + /* Micro seconds per second */ #define NU_US_PER_SEC 1000000 /* Timer clock per second diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c index 9298fd8d92..4a3f0e56c2 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c @@ -38,7 +38,11 @@ Vector table relocation is not actually supported for low-resource target. */ void TMR0_IRQHandler(void); +#if MBED_CONF_TARGET_HXT_PRESENT static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, 0, TMR0_RST, TMR0_IRQn, (void *) TMR0_IRQHandler}; +#else +static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HIRC, 0, TMR0_RST, TMR0_IRQn, (void *) TMR0_IRQHandler}; +#endif #define TIMER_MODINIT timer0_modinit diff --git a/targets/TARGET_NUVOTON/TARGET_NANO100/watchdog_api.c b/targets/TARGET_NUVOTON/TARGET_NANO100/watchdog_api.c index 502f59bf3c..f5432386bd 100644 --- a/targets/TARGET_NUVOTON/TARGET_NANO100/watchdog_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NANO100/watchdog_api.c @@ -20,31 +20,12 @@ #include "cmsis.h" -/* Define WDT clock source in target configuration option */ -#ifndef MBED_CONF_TARGET_WDT_CLKSRC_SEL -#define MBED_CONF_TARGET_WDT_CLKSRC_SEL LIRC -#endif - -/* WDT clock source definition */ -#define NU_INTERN_WDT_CLKSRC_LXT 1 -/* Not support LIRC clocked WDT */ -//#define NU_INTERN_WDT_CLKSRC_LIRC 2 - -/* WDT clock source selection */ -#define NU_INTERN_WDT_CLKSRC_SEL__(SEL) NU_INTERN_WDT_CLKSRC_##SEL -#define NU_INTERN_WDT_CLKSRC_SEL_(SEL) NU_INTERN_WDT_CLKSRC_SEL__(SEL) -#define NU_INTERN_WDT_CLKSRC_SEL NU_INTERN_WDT_CLKSRC_SEL_(MBED_CONF_TARGET_WDT_CLKSRC_SEL) +/* WDT can only clock by LIRC */ /* Watchdog clock per second */ -#if NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LXT -#define NU_WDTCLK_PER_SEC (__LXT) -#define NU_WDTCLK_PER_SEC_MAX (__LXT) -#define NU_WDTCLK_PER_SEC_MIN (__LXT) -#elif NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LIRC #define NU_WDTCLK_PER_SEC (__LIRC) #define NU_WDTCLK_PER_SEC_MAX ((uint32_t) ((__LIRC) * 1.5f)) #define NU_WDTCLK_PER_SEC_MIN ((uint32_t) ((__LIRC) * 0.5f)) -#endif /* Convert watchdog clock to nearest ms */ #define NU_WDTCLK2MS(WDTCLK) (((WDTCLK) * 1000 + ((NU_WDTCLK_PER_SEC) / 2)) / (NU_WDTCLK_PER_SEC)) diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c index 04aacbb4a6..44e367d2c1 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c @@ -29,7 +29,11 @@ /* Timer clock per lp_ticker tick */ #define NU_TMRCLK_PER_TICK 1 /* Timer clock per second */ +#if MBED_CONF_TARGET_LXT_PRESENT #define NU_TMRCLK_PER_SEC (__LXT) +#else +#define NU_TMRCLK_PER_SEC (__LIRC) +#endif /* Timer max counter bit size */ #define NU_TMR_MAXCNT_BITSIZE 24 /* Timer max counter */ @@ -38,7 +42,11 @@ static void tmr1_vec(void); /* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */ +#if MBED_CONF_TARGET_LXT_PRESENT static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; +#else +static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LIRC, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec}; +#endif #define TIMER_MODINIT timer1_modinit diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/mbed_overrides.c b/targets/TARGET_NUVOTON/TARGET_NUC472/mbed_overrides.c index 143d0e8a74..2e2375bc1e 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/mbed_overrides.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/mbed_overrides.c @@ -32,28 +32,51 @@ void mbed_sdk_init(void) /* Unlock protected registers */ SYS_UnlockReg(); +#if MBED_CONF_TARGET_HXT_PRESENT /* Enable External XTAL (4~24 MHz) */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); - /* Enable LIRC for lp_ticker */ +#else + /* Disable External XTAL (4~24 MHz) */ + CLK_DisableXtalRC(CLK_PWRCTL_HXTEN_Msk); +#endif + /* Enable LIRC */ CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk); - /* Enable LXT for RTC */ +#if MBED_CONF_TARGET_LXT_PRESENT + /* Enable LXT */ CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk); +#else + /* Disable LXT */ + CLK_DisableXtalRC(CLK_PWRCTL_LXTEN_Msk); +#endif +#if MBED_CONF_TARGET_HXT_PRESENT /* Waiting for External XTAL (4~24 MHz) ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); +#endif /* Waiting for LIRC ready */ CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk); +#if MBED_CONF_TARGET_LXT_PRESENT /* Waiting for LXT ready */ CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk); +#endif +#if MBED_CONF_TARGET_HXT_PRESENT /* Switch HCLK clock source to HXT */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1)); +#else + /* Switch HCLK clock source to HIRC */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC,CLK_CLKDIV0_HCLK(1)); +#endif /* Set PLL to power down mode and PLLSTB bit in CLKSTATUS register will be cleared by hardware.*/ CLK->PLLCTL|= CLK_PLLCTL_PD_Msk; /* Set PLL frequency */ +#if MBED_CONF_TARGET_HXT_PRESENT CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT; +#else + CLK->PLLCTL = CLK_PLLCTL_50MHz_HIRC; +#endif /* Waiting for clock ready */ CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); @@ -61,12 +84,6 @@ void mbed_sdk_init(void) /* Switch HCLK clock source to PLL */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV0_HCLK(1)); - /* Enable IP clock */ - //CLK_EnableModuleClock(UART0_MODULE); - - /* Select IP clock source */ - //CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UARTSEL_HXT,CLK_CLKDIV0_UART(1)); - #if DEVICE_ANALOGIN /* Vref connect to AVDD */ SYS->VREFCTL = (SYS->VREFCTL & ~SYS_VREFCTL_VREFCTL_Msk) | SYS_VREFCTL_VREF_AVDD; diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c index 85da1d37c9..6bcf87fba0 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c @@ -24,6 +24,14 @@ #include "nu_miscutil.h" #include "mbed_mktime.h" +/* Not support LIRC-clocked RTC + * + * H/W doesn't support this path. + */ +#if !MBED_CONF_TARGET_LXT_PRESENT +#error "RTC can only clock by LXT but LXT is not present. Try disabling RTC by \"device_has_remove\" in mbed_app.json" +#endif + /* Micro seconds per second */ #define NU_US_PER_SEC 1000000 /* Timer clock per second diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c b/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c index 45a6993d76..0b14763937 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c @@ -78,7 +78,13 @@ void us_ticker_init(void) uint32_t clk_timer = TIMER_GetModuleClock(timer_base); uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1; MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127); + /* HIRC-clocked PLL fails to output 1MHz-aligned frequency + * + * PLL, clocked by HIRC instead of HXT, doesn't output 1MHz-aligned frequency. + */ +#if MBED_CONF_TARGET_HXT_PRESENT MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0); +#endif uint32_t cmp_timer = TMR_CMP_MAX; MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX); timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk; diff --git a/targets/TARGET_NUVOTON/TARGET_NUC472/watchdog_api.c b/targets/TARGET_NUVOTON/TARGET_NUC472/watchdog_api.c index d760721363..21d67aa6c3 100644 --- a/targets/TARGET_NUVOTON/TARGET_NUC472/watchdog_api.c +++ b/targets/TARGET_NUVOTON/TARGET_NUC472/watchdog_api.c @@ -20,26 +20,12 @@ #include "cmsis.h" -/* Define WDT clock source in target configuration option */ -#ifndef MBED_CONF_TARGET_WDT_CLKSRC_SEL -#define MBED_CONF_TARGET_WDT_CLKSRC_SEL LXT -#endif - -/* WDT clock source definition */ -#define NU_INTERN_WDT_CLKSRC_LXT 1 -#define NU_INTERN_WDT_CLKSRC_LIRC 2 - -/* WDT clock source selection */ -#define NU_INTERN_WDT_CLKSRC_SEL__(SEL) NU_INTERN_WDT_CLKSRC_##SEL -#define NU_INTERN_WDT_CLKSRC_SEL_(SEL) NU_INTERN_WDT_CLKSRC_SEL__(SEL) -#define NU_INTERN_WDT_CLKSRC_SEL NU_INTERN_WDT_CLKSRC_SEL_(MBED_CONF_TARGET_WDT_CLKSRC_SEL) - /* Watchdog clock per second */ -#if NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LXT +#if MBED_CONF_TARGET_LXT_PRESENT #define NU_WDTCLK_PER_SEC (__LXT) #define NU_WDTCLK_PER_SEC_MAX (__LXT) #define NU_WDTCLK_PER_SEC_MIN (__LXT) -#elif NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LIRC +#else #define NU_WDTCLK_PER_SEC (__LIRC) #define NU_WDTCLK_PER_SEC_MAX ((uint32_t) ((__LIRC) * 1.4f)) #define NU_WDTCLK_PER_SEC_MIN ((uint32_t) ((__LIRC) * 0.6f)) @@ -104,9 +90,9 @@ watchdog_status_t hal_watchdog_init(const watchdog_config_t *config) CLK_EnableModuleClock(WDT_MODULE); /* Select IP clock source */ -#if NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LXT +#if MBED_CONF_TARGET_LXT_PRESENT CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LXT, 0); -#elif NU_INTERN_WDT_CLKSRC_SEL == NU_INTERN_WDT_CLKSRC_LIRC +#else CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0); #endif diff --git a/targets/TARGET_NUVOTON/scripts/NUVOTON.py b/targets/TARGET_NUVOTON/scripts/NUVOTON.py new file mode 100644 index 0000000000..0b094a1d2f --- /dev/null +++ b/targets/TARGET_NUVOTON/scripts/NUVOTON.py @@ -0,0 +1,240 @@ +#!/usr/bin/python +# Copyright (c) 2017-2021 Arm Limited +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import os +from os.path import abspath, basename, dirname, splitext, isdir +from os.path import join as path_join +import re +import subprocess +import shutil +import argparse +from intelhex import IntelHex + +SCRIPT_DIR = dirname(abspath(__file__)) +MBED_OS_ROOT = abspath(path_join(SCRIPT_DIR, os.pardir, os.pardir, os.pardir)) + +def tfm_sign_image_tgt(tfm_import_path, signing_key, non_secure_bin): + + SECURE_ROOT = abspath(tfm_import_path) + + secure_bin = path_join(SECURE_ROOT, 'tfm_s.bin') + assert os.path.isfile(secure_bin) + + non_secure_bin = abspath(non_secure_bin) + assert os.path.isfile(non_secure_bin) + + build_dir = dirname(non_secure_bin) + tempdir = path_join(build_dir, 'temp') + if not isdir(tempdir): + os.makedirs(tempdir) + + flash_layout = path_join(SECURE_ROOT, 'partition', 'flash_layout.h') + + bl2_bin = path_join(SECURE_ROOT, 'bl2.bin') + image_macros_s_ns = path_join(SECURE_ROOT, 'partition', 'signing_layout_preprocessed.h') + ns_bin_basename = splitext(basename(non_secure_bin))[0] + concatenated_bin = abspath(path_join(tempdir, 'tfm_' + ns_bin_basename + ".bin")) + signed_bin = abspath(path_join(tempdir, 'tfm_' + ns_bin_basename + '_signed' + ".bin")) + signed_nopad_bin = abspath(path_join(tempdir, 'tfm_' + ns_bin_basename + '_signed_nopad' + ".bin")) + + assert os.path.isfile(image_macros_s_ns) + + signing_key = path_join(SECURE_ROOT, 'signing_key', signing_key) + assert os.path.isfile(signing_key) + + # Find Python 3 command name across platforms + python3_cmd = "python3" if shutil.which("python3") is not None else "python" + + #1. Concatenate secure TFM and non-secure mbed binaries + cmd = [ + python3_cmd, + path_join(MBED_OS_ROOT, "tools", "psa", "tfm", "bin_utils", "assemble.py"), + "--layout", + image_macros_s_ns, + "-s", + secure_bin, + "-n", + non_secure_bin, + "-o", + concatenated_bin, + ] + + retcode = run_cmd(cmd, MBED_OS_ROOT) + if retcode: + raise Exception("Unable to concatenate " + "TF-M Secure/Mbed Non-secure" + + " binaries, Error code: " + str(retcode)) + return + + #2.1 Run wrapper to sign the concatenated binary with padding ("--pad"), so upgradeable by mcuboot + cmd = [ + python3_cmd, + path_join(MBED_OS_ROOT, "tools", "psa","tfm", "bin_utils", "wrapper.py"), + "-v", + '1.2.0', + "-k", + signing_key, + "--layout", + image_macros_s_ns, + "--public-key-format", + 'full', + "--align", + '1', + "--pad", + "--pad-header", + "-H", + '0x400', + "--overwrite-only", + "-s", + 'auto', + "-d", + '(0,0.0.0+0)', + concatenated_bin, + signed_bin, + ] + + retcode = run_cmd(cmd, MBED_OS_ROOT) + if retcode: + raise Exception("Unable to sign " + "concatenated" + + " binary, Error code: " + str(retcode)) + return + + #2.2. Re-run above but without padding ("--pad"), so non-upgradeable by mcuboot + cmd.remove("--pad") + cmd.pop() + cmd.append(signed_nopad_bin) + + retcode = run_cmd(cmd, MBED_OS_ROOT) + if retcode: + raise Exception("Unable to sign " + "concatenated" + + " binary, Error code: " + str(retcode)) + return + + #3. Concatenate mcuboot and signed binary and overwrite mbed built bin/hex file + flash_area_0_offset = find_flash_area_0_offset(flash_layout) + out_ih = IntelHex() + out_ih.loadbin(bl2_bin) + out_ih.loadbin(signed_nopad_bin, flash_area_0_offset) + out_ih.tofile(splitext(non_secure_bin)[0] + ".hex", 'hex') + out_ih.tobinfile(non_secure_bin) + +def find_flash_area_0_offset(configFile): + # Compiled regular expressions + flash_area_bl2_offset_re = re.compile(r"^#define\s+FLASH_AREA_BL2_OFFSET\s+\({0,1}(0x[0-9a-fA-F]+)\){0,1}") + flash_area_bl2_size_re = re.compile(r"^#define\s+FLASH_AREA_BL2_SIZE\s+\({0,1}(0x[0-9a-fA-F]+)\){0,1}") + rsvd_stor_size_re = re.compile(r"^#define\s+FLASH_AREA_0_OFFSET\s+\(FLASH_AREA_BL2_OFFSET\s+\+\s+FLASH_AREA_BL2_SIZE\s+\+\s+\({0,1}(0x[0-9a-fA-F]+)\){0,1}\)") + + # Match values + flash_area_bl2_offset = None + flash_area_bl2_size = None + rsvd_stor_size = None + flash_area_0_offset = None + + with open(configFile, 'r') as configFile_: + for line in configFile_: + # Seek "#define FLASH_AREA_BL2_OFFSET..." + if flash_area_bl2_offset is None: + m = flash_area_bl2_offset_re.match(line) + if m is not None: + flash_area_bl2_offset = int(m.group(1), 0) + continue + + # Seek "#define FLASH_AREA_BL2_SIZE..." + if flash_area_bl2_size is None: + m = flash_area_bl2_size_re.match(line) + if m is not None: + flash_area_bl2_size = int(m.group(1), 0) + continue + + # Seek "#define FLASH_AREA_0_OFFSET..." + if rsvd_stor_size is None: + m = rsvd_stor_size_re.match(line) + if m is not None: + rsvd_stor_size = int(m.group(1), 0) + continue + + # FLASH_AREA_0_OFFSET = FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE + Reserved storage area size + if flash_area_bl2_offset is not None and \ + flash_area_bl2_size is not None and \ + rsvd_stor_size is not None: + flash_area_0_offset = flash_area_bl2_offset + flash_area_bl2_size + rsvd_stor_size + break + + return flash_area_0_offset + +def run_cmd(cmd, directory): + + # Redirect stdout/stderr to pipe, text mode + POPEN_INSTANCE = subprocess.Popen( + cmd, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + cwd=directory, + universal_newlines=True + ) + + # Command line + print("COMMAND: {}".format(POPEN_INSTANCE.args)) + + stdout_data, stderr_data = POPEN_INSTANCE.communicate() + + # stdout/stderr messages + if (stdout_data): + print(stdout_data) + if (stderr_data): + print(stderr_data) + + # Return code + return POPEN_INSTANCE.returncode + +def parse_args(): + """Parse the command line arguments.""" + parser = argparse.ArgumentParser( + description="Nuvoton post build command" + ) + + subparsers = parser.add_subparsers(description="The action to perform") + + parser_tfm_sign_image_tgt = subparsers.add_parser( + "tfm_sign_image_tgt", + help="Sign secure and non-secure images together" + ) + + parser_tfm_sign_image_tgt.add_argument( + "--tfm-import-path", + help="Path containing the TF-M bootloader, layouts and signing keys", + required=True + ) + + parser_tfm_sign_image_tgt.add_argument( + "--signing_key", + help="File name of key for signing secure binary or secure/non-secure binaries together", + required=True + ) + + parser_tfm_sign_image_tgt.add_argument( + "--non-secure-bin", + help="Path to the non-secure binary", + required=True + ) + + parser_tfm_sign_image_tgt.set_defaults(func=tfm_sign_image_tgt) + + return parser.parse_args() + +if __name__ == "__main__": + args = parse_args() + args.func(args.tfm_import_path, args.signing_key, args.non_secure_bin) diff --git a/targets/TARGET_NUVOTON/scripts/mbed_set_post_build_nuvoton.cmake b/targets/TARGET_NUVOTON/scripts/mbed_set_post_build_nuvoton.cmake new file mode 100644 index 0000000000..3169ad5c35 --- /dev/null +++ b/targets/TARGET_NUVOTON/scripts/mbed_set_post_build_nuvoton.cmake @@ -0,0 +1,27 @@ +# Copyright (c) 2021 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +include(${MBED_PATH}/tools/cmake/mbed_set_post_build.cmake) + +# +# Sign TF-M secure and non-secure images and combine them with the bootloader +# +function(mbed_post_build_nuvoton_tfm_sign_image_tgt + mbed_target + tfm_import_path + signing_key +) + find_package(Python3) + + set(mbed_target_name ${mbed_target}) + set(post_build_command + COMMAND ${Python3_EXECUTABLE} + ${MBED_PATH}/targets/TARGET_NUVOTON/scripts/NUVOTON.py + tfm_sign_image_tgt + --tfm-import-path ${tfm_import_path} + --signing_key ${signing_key} + --non-secure-bin ${CMAKE_BINARY_DIR}/$.bin + ) + + mbed_set_post_build_operation() +endfunction() diff --git a/targets/TARGET_STM/PinNamesTypes.h b/targets/TARGET_STM/PinNamesTypes.h index 2143dadc9e..0dc935ed87 100644 --- a/targets/TARGET_STM/PinNamesTypes.h +++ b/targets/TARGET_STM/PinNamesTypes.h @@ -45,9 +45,10 @@ extern "C" { * [9:6] speed config (as in OSPEEDR) * [13:10] Alternate Num (as in AFRL/AFRG reg) * [17:14] Channel (Analog/Timer specific) - * [18] Inverted (Analog/Timer specific) - * [19] Analog ADC control - Only valid for specific families - * [32:21] Reserved + * [19] Inverted (Analog/Timer specific) + * [20] Analog ADC control - Only valid for specific families + * [21] Analog ADC Channel Bank B - Only valid for specific families + * [32:22] Reserved */ #define STM_PIN_FUNCTION_MASK 0x07 @@ -82,6 +83,10 @@ extern "C" { #define STM_PIN_AN_CTRL_SHIFT 20 #define STM_PIN_ANALOG_CONTROL_BIT (STM_PIN_AN_CTRL_MASK << STM_PIN_AN_CTRL_SHIFT) +#define STM_PIN_AN_CHAN_BANK_B_MASK 0x01 +#define STM_PIN_AN_CHAN_BANK_B_SHIFT 21 +#define STM_PIN_ANALOG_CHAN_BANK_B_BIT (STM_PIN_AN_CHAN_BANK_B_MASK << STM_PIN_AN_CHAN_BANK_B_SHIFT) + #define STM_PIN_FUNCTION(X) (((X) >> STM_PIN_FUNCTION_SHIFT) & STM_PIN_FUNCTION_MASK) #define STM_PIN_OD(X) (((X) >> STM_PIN_OD_SHIFT) & STM_PIN_OD_MASK) #define STM_PIN_PUPD(X) (((X) >> STM_PIN_PUPD_SHIFT) & STM_PIN_PUPD_MASK) @@ -90,6 +95,7 @@ extern "C" { #define STM_PIN_CHANNEL(X) (((X) >> STM_PIN_CHAN_SHIFT) & STM_PIN_CHAN_MASK) #define STM_PIN_INVERTED(X) (((X) >> STM_PIN_INV_SHIFT) & STM_PIN_INV_MASK) #define STM_PIN_ANALOG_CONTROL(X) (((X) >> STM_PIN_AN_CTRL_SHIFT) & STM_PIN_AN_CTRL_MASK) +#define STM_PIN_ANALOG_CHANNEL_BANK_B(X) (((X) >> STM_PIN_AN_CHAN_BANK_B_SHIFT) & STM_PIN_AN_CHAN_BANK_B_MASK) #define STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM) ((int)(FUNC_OD) |\ ((STM_PIN_SPEED_MASK & STM_PIN_SPEED_MASK) << STM_PIN_SPEED_SHIFT) |\ @@ -141,6 +147,7 @@ typedef enum { #define STM_MODE_AF_OD (STM_PIN_ALTERNATE | STM_PIN_OD_BITS) #define STM_MODE_ANALOG (STM_PIN_ANALOG) #define STM_MODE_ANALOG_ADC_CONTROL (STM_PIN_ANALOG | STM_PIN_ANALOG_CONTROL_BIT) +#define STM_MODE_ANALOG_ADC_CHANNEL_BANK_B (STM_PIN_ANALOG | STM_PIN_ANALOG_CHAN_BANK_B_BIT) // High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H) // Low nibble = pin number diff --git a/targets/TARGET_STM/README.md b/targets/TARGET_STM/README.md index d86835f2de..245a93f666 100644 --- a/targets/TARGET_STM/README.md +++ b/targets/TARGET_STM/README.md @@ -1,5 +1,37 @@ # README for Mbed OS STM32 targets +Table of Contents +================= + +* [README for Mbed OS STM32 targets](#readme-for-mbed-os-stm32-targets) + * [ST TOOLS](#st-tools) + * [USB drivers](#usb-drivers) + * [ST-Link FW](#st-link-fw) + * [STM32 Cube](#stm32-cube) + * [STM32CubeMX](#stm32cubemx) + * [STM32CubeProgrammer](#stm32cubeprogrammer) + * [STM32 families](#stm32-families) + * [STM32WB](#stm32wb) + * [STM32WL](#stm32wl) + * [STM32H7](#stm32h7) + * [Custom boards](#custom-boards) + * [STM32 organisation](#stm32-organisation) + * [Add a custom board](#add-a-custom-board) + * [Board specific files (pinmap)](#board-specific-files-pinmap) + * [Use of custom_targets.json](#use-of-custom_targetsjson) + * [ST specific implementation](#st-specific-implementation) + * [Pin configuration](#pin-configuration) + * [Alternate feature](#alternate-feature) + * [Conflict pins](#conflict-pins) + * [Clock selection](#clock-selection) + * [System clock](#system-clock) + * [Low power clock](#low-power-clock) + * [Sleep feature](#sleep-feature) + * [WiFi configuration](#wifi-configuration) + * [Ethernet configuration](#ethernet-configuration) + * [Mbed OS Wiki pages](#mbed-os-wiki-pages) + + ## ST TOOLS ### USB drivers @@ -66,14 +98,14 @@ This table summarizes the STM32Cube versions currently used in Mbed OS master br | F2 | 1.6.0 | https://github.com/STMicroelectronics/STM32CubeF2 | | F3 | 1.11.2 | https://github.com/STMicroelectronics/STM32CubeF3 | | F4 | 1.26.1 | https://github.com/STMicroelectronics/STM32CubeF4 | -| F7 | 1.16.0 | https://github.com/STMicroelectronics/STM32CubeF7 | +| F7 | 1.16.1 | https://github.com/STMicroelectronics/STM32CubeF7 | | G0 | 1.4.1 | https://github.com/STMicroelectronics/STM32CubeG0 | -| G4 | 1.1.0 | https://github.com/STMicroelectronics/STM32CubeG4 | -| H7 | 1.8.0 | https://github.com/STMicroelectronics/STM32CubeH7 | +| G4 | 1.4.0 | https://github.com/STMicroelectronics/STM32CubeG4 | +| H7 | 1.9.0 | https://github.com/STMicroelectronics/STM32CubeH7 | | L0 | 1.12.0 | https://github.com/STMicroelectronics/STM32CubeL0 | | L1 | 1.10.2 | https://github.com/STMicroelectronics/STM32CubeL1 | | L4 | 1.17.0 | https://github.com/STMicroelectronics/STM32CubeL4 | -| L5 | 1.3.0 | https://github.com/STMicroelectronics/STM32CubeL5 | +| L5 | 1.4.0 | https://github.com/STMicroelectronics/STM32CubeL5 | | WB | 1.11.1 | https://github.com/STMicroelectronics/STM32CubeWB | | WL | 1.0.0 | https://github.com/STMicroelectronics/STM32CubeWL | @@ -377,6 +409,27 @@ You can change this in you local mbed_app.json: ``` +### Sleep feature + +ST MCUs feature several low-power modes, please check Reference Manual of each one for more details. + +- MBED sleep mode is usually mapped to ST SLEEP mode: + - CPU clock is off + - all peripherals can run and wake up the CPU when an interrupt or an event +occurs + +- MBED deepsleep mode is mapped to ST STOP2 mode: + - all clocks in the VCORE domain are stopped + - the PLL, the MSI, the HSI and the HSE are disabled + - the LSI and the LSE can be kept running + - RTC can remain active + +Detailed sleep Mbed OS description : https://os.mbed.com/docs/mbed-os/latest/apis/power-management-sleep.html +- debug profile is disabling deepsleep +- deepsleep can also be disabled by application or drivers using sleep_manager_lock_deep_sleep() +- deep-sleep-latency value is configured to 4 by default for STM32 + + ### WiFi configuration https://github.com/ARMmbed/wifi-ism43362 @@ -406,6 +459,17 @@ Option is also to define your own `HAL_ETH_MspInit` function, you then have to add **USE_USER_DEFINED_HAL_ETH_MSPINIT** macro. +### Asynchronous SPI limitation + +The current Asynchronous SPI implementation will not be able to support high speeds (MHz Range). +The maximum speed supported depends on +- core operating frequency +- depth of SPI FIFOs (if available). + +For application that require optimized maximum performance, the recommendation is to implement the DMA-based SPI transfer. +The SPI DMA transfer support shall be implemented on a case-by-case based on below example +https://github.com/ABOSTM/mbed-os/tree/I2C_SPI_DMA_IMPLEMENTATION_FOR_STM32L4 + ## Mbed OS Wiki pages diff --git a/targets/TARGET_STM/TARGET_STM32F0/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32F0/CMakeLists.txt index fb1ef56291..cf33302d07 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32F0/CMakeLists.txt @@ -21,6 +21,7 @@ target_sources(mbed-stm32f0 cmsis_nvic.c flash_api.c gpio_irq_device.c + i2c_device.c pwmout_device.c serial_device.c spi_api.c diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F070xB/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F070xB/system_clock.c index 1d4fe38c84..91c76da81b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F070xB/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F070xB/system_clock.c @@ -95,7 +95,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) //Select HSI as system clock source to allow modification of the PLL configuration RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; - if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { return 0; // FAIL } diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F072xB/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F072xB/system_clock.c index 8317759ebf..a5aa3bd1ea 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F072xB/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F072xB/system_clock.c @@ -95,7 +95,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) //Select HSI as system clock source to allow modification of the PLL configuration RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; - if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { return 0; // FAIL } diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F091xC/system_clock.c b/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F091xC/system_clock.c index d354280b67..b3155300d4 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F091xC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_STM32F091xC/system_clock.c @@ -95,7 +95,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) //Select HSI as system clock source to allow modification of the PLL configuration RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; - if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { return 0; // FAIL } diff --git a/targets/TARGET_STM/TARGET_STM32F0/can_device.h b/targets/TARGET_STM/TARGET_STM32F0/can_device.h index cd8bee00b9..86ab3fb643 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F0/can_device.h @@ -40,4 +40,8 @@ extern "C" { #endif // DEVICE_CAN +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F0/cmsis_nvic.c b/targets/TARGET_STM/TARGET_STM32F0/cmsis_nvic.c index 0124d0edaa..3ce3bd3c65 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/cmsis_nvic.c +++ b/targets/TARGET_STM/TARGET_STM32F0/cmsis_nvic.c @@ -18,24 +18,26 @@ #define NVIC_USER_IRQ_OFFSET 16 -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ int i; // Copy and switch to dynamic vectors if first time called if ((SYSCFG->CFGR1 & SYSCFG_CFGR1_MEM_MODE) != SYSCFG_CFGR1_MEM_MODE) { uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS; for (i = 0; i < NVIC_NUM_VECTORS; i++) { - *((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (i*4))) = old_vectors[i]; + *((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (i * 4))) = old_vectors[i]; } SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE; // Embedded SRAM mapped at 0x00000000 } // Set the vector - *((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (IRQn*4) + (NVIC_USER_IRQ_OFFSET*4))) = vector; + *((uint32_t *)(NVIC_RAM_VECTOR_ADDRESS + (IRQn * 4) + (NVIC_USER_IRQ_OFFSET * 4))) = vector; } -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; +uint32_t NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS; // Return the vector return vectors[IRQn + 16]; } diff --git a/targets/TARGET_STM/TARGET_STM32F0/i2c_device.c b/targets/TARGET_STM/TARGET_STM32F0/i2c_device.c new file mode 100755 index 0000000000..bcc29d82dc --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F0/i2c_device.c @@ -0,0 +1,102 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "i2c_device.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "stm32f0xx_ll_rcc.h" + +/* Define I2C Device */ +#if DEVICE_I2C + +/** + * @brief Get I2C clock source frequency according I2C instance used. + * @param i2c I2C instance name. + * @retval I2C clock source frequency in Hz. + */ +uint32_t i2c_get_pclk(I2CName i2c) +{ + uint32_t clocksource; + uint32_t pclk = 0; + if (i2c == I2C_1) { + clocksource = __HAL_RCC_GET_I2C1_SOURCE(); + switch (clocksource) { + case RCC_I2C1CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C1CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#if defined I2C2_BASE + else if (i2c == I2C_2) { + pclk = HAL_RCC_GetSysClockFreq(); + } +#endif + else { + // should not happend + error("I2C: unknown instance"); + } + return pclk; +} + +/** + * @brief Provide the suitable timing depending on requested frequency + * @param hz Required I2C clock in Hz. + * @retval I2C timing or 0 in case of error. + */ +uint32_t i2c_get_timing(I2CName i2c, int hz) +{ + uint32_t tim; + uint32_t pclk; + + pclk = i2c_get_pclk(i2c); + + if (pclk == I2C_PCLK_DEF) { + switch (hz) { + case 100000: + tim = TIMING_VAL_DEFAULT_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_DEFAULT_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_DEFAULT_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } + + else { + /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. + User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. + Enabling this may impact performance*/ + MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO); +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + tim = i2c_compute_timing(pclk, hz); +#endif + } + return tim; +} + +/** + * @} + */ + +#endif // DEVICE_I2C diff --git a/targets/TARGET_STM/TARGET_STM32F0/i2c_device.h b/targets/TARGET_STM/TARGET_STM32F0/i2c_device.h index bda4eb7adb..8cd4f5857b 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32F0/i2c_device.h @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2015-2020 STMicroelectronics. + * Copyright (c) 2015-2021 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -16,12 +16,13 @@ #ifndef MBED_I2C_DEVICE_H #define MBED_I2C_DEVICE_H -#include "cmsis.h" +#include "PeripheralNames.h" #ifdef __cplusplus extern "C" { #endif +/* Define I2C Device */ #if DEVICE_I2C #if defined I2C1_BASE @@ -32,41 +33,33 @@ extern "C" { #define I2C2_EV_IRQn I2C2_IRQn #define I2C2_ER_IRQn I2C2_IRQn #endif -#if defined I2C3_BASE -#define I2C3_EV_IRQn I2C3_IRQn -#define I2C3_ER_IRQn I2C3_IRQn -#endif - -#define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI) - /* Define IP version */ #define I2C_IP_VERSION_V2 +#define TIMING_VAL_DEFAULT_CLK_100KHZ 0x10805E89 // Standard mode with Rise Time = 400ns and Fall Time = 100ns +#define TIMING_VAL_DEFAULT_CLK_400KHZ 0x00901850 // Fast mode with Rise Time = 250ns and Fall Time = 100ns +#define TIMING_VAL_DEFAULT_CLK_1MHZ 0x00700818 // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns +#define I2C_PCLK_DEF 48000000 // 48 MHz + +#define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI) + /* Family specifc settings for clock source */ #define I2CAPI_I2C1_CLKSRC RCC_I2C1CLKSOURCE_SYSCLK -/* Provide the suitable timing depending on requested frequencie */ -static inline uint32_t get_i2c_timing(int hz) -{ - uint32_t tim = 0; +uint32_t i2c_get_pclk(I2CName i2c); +uint32_t i2c_get_timing(I2CName i2c, int hz); - switch (hz) { - case 100000: - tim = 0x10805E89; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - tim = 0x00901850; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - tim = 0x00700818; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - return tim; -} +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq); +void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t I2C_speed); +uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t I2C_speed); +#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO #endif // DEVICE_I2C +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F0/objects.h b/targets/TARGET_STM/TARGET_STM32F0/objects.h index f6c0820ff2..6cef3652f8 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F0/objects.h @@ -98,6 +98,9 @@ struct i2c_s { uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32F0/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32F0/us_ticker_data.h index 10d646cbb2..d79efc3d0e 100644 --- a/targets/TARGET_STM/TARGET_STM32F0/us_ticker_data.h +++ b/targets/TARGET_STM/TARGET_STM32F0/us_ticker_data.h @@ -17,7 +17,7 @@ #define __US_TICKER_DATA_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #include "stm32f0xx.h" diff --git a/targets/TARGET_STM/TARGET_STM32F1/can_device.h b/targets/TARGET_STM/TARGET_STM32F1/can_device.h index f47f7bd644..77323a22b9 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F1/can_device.h @@ -41,4 +41,8 @@ extern "C" { #endif // DEVICE_CAN +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/i2c_device.h b/targets/TARGET_STM/TARGET_STM32F1/i2c_device.h index 678d56b01a..f99afc7267 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32F1/i2c_device.h @@ -45,4 +45,8 @@ extern "C" { #endif // DEVICE_I2C +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F1/objects.h b/targets/TARGET_STM/TARGET_STM32F1/objects.h index 5c2108c8d0..63085dc945 100644 --- a/targets/TARGET_STM/TARGET_STM32F1/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F1/objects.h @@ -123,6 +123,9 @@ struct i2c_s { uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32F2/can_device.h b/targets/TARGET_STM/TARGET_STM32F2/can_device.h index 8e7730e0d8..aad22f4ba6 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F2/can_device.h @@ -52,4 +52,8 @@ extern "C" { #endif // DEVICE_CAN +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F2/i2c_device.h b/targets/TARGET_STM/TARGET_STM32F2/i2c_device.h index 9de8774188..8c3c90dd5c 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32F2/i2c_device.h @@ -44,4 +44,8 @@ extern "C" { #endif // DEVICE_I2C +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F2/objects.h b/targets/TARGET_STM/TARGET_STM32F2/objects.h index fefdfec972..8b9bb00d69 100644 --- a/targets/TARGET_STM/TARGET_STM32F2/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F2/objects.h @@ -122,12 +122,15 @@ struct i2c_s { PinName scl; IRQn_Type event_i2cIRQ; IRQn_Type error_i2cIRQ; - uint8_t XferOperation; + uint32_t XferOperation; volatile uint8_t event; #if DEVICE_I2CSLAVE uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32F3/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32F3/CMakeLists.txt index b13377e017..f1684b7fc6 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32F3/CMakeLists.txt @@ -21,6 +21,7 @@ target_sources(mbed-stm32f3 analogout_device.c flash_api.c gpio_irq_device.c + i2c_device.c pwmout_device.c serial_device.c spi_api.c diff --git a/targets/TARGET_STM/TARGET_STM32F3/can_device.h b/targets/TARGET_STM/TARGET_STM32F3/can_device.h index 846e081cf1..1abc4f88db 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F3/can_device.h @@ -41,4 +41,8 @@ extern "C" { #endif // DEVICE_CAN +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/i2c_device.c b/targets/TARGET_STM/TARGET_STM32F3/i2c_device.c new file mode 100755 index 0000000000..c0e2294f45 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F3/i2c_device.c @@ -0,0 +1,140 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "i2c_device.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "stm32f3xx_ll_rcc.h" + +/* Define I2C Device */ +#if DEVICE_I2C + +/** + * @brief Get I2C clock source frequency according I2C instance used. + * @param i2c I2C instance name. + * @retval I2C clock source frequency in Hz. + */ +uint32_t i2c_get_pclk(I2CName i2c) +{ + uint32_t clocksource; + uint32_t pclk = 0; + if (i2c == I2C_1) { + clocksource = __HAL_RCC_GET_I2C1_SOURCE(); + switch (clocksource) { + case RCC_I2C1CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C1CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#if defined I2C2_BASE + else if (i2c == I2C_2) { + clocksource = __HAL_RCC_GET_I2C2_SOURCE(); + switch (clocksource) { + case RCC_I2C2CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C2CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif +#if defined I2C3_BASE + else if (i2c == I2C_3) { + clocksource = __HAL_RCC_GET_I2C3_SOURCE(); + switch (clocksource) { + case RCC_I2C3CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C3CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif + else { + // should not happend + error("I2C: unknown instance"); + } + return pclk; +} + +/** + * @brief Provide the suitable timing depending on requested frequency + * @param hz Required I2C clock in Hz. + * @retval I2C timing or 0 in case of error. + */ +uint32_t i2c_get_timing(I2CName i2c, int hz) +{ + uint32_t tim; + uint32_t pclk; + + pclk = i2c_get_pclk(i2c); + + if (pclk == I2C_PCLK_HSI) { + switch (hz) { + case 100000: + tim = TIMING_VAL_64M_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_64M_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_64M_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } else if (pclk == I2C_PCLK_HSE) { + switch (hz) { + case 100000: + tim = TIMING_VAL_72M_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_72M_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_72M_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } + + else { + /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. + User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. + Enabling this may impact performance*/ + MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO); +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + tim = i2c_compute_timing(pclk, hz); +#endif + } + return tim; +} + +/** + * @} + */ + +#endif // DEVICE_I2C diff --git a/targets/TARGET_STM/TARGET_STM32F3/i2c_device.h b/targets/TARGET_STM/TARGET_STM32F3/i2c_device.h index 7ef29226aa..6b39b244d5 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32F3/i2c_device.h @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2015-2021, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,76 +27,53 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ + #ifndef MBED_I2C_DEVICE_H #define MBED_I2C_DEVICE_H -#include "cmsis.h" +#include "PeripheralNames.h" #ifdef __cplusplus extern "C" { #endif +/* Define I2C Device */ #if DEVICE_I2C -#define I2C_IP_VERSION_V2 +#define TIMING_VAL_64M_CLK_100KHZ 0x10B17DB4 // Standard mode with Rise time = 120ns, Fall time = 120ns +#define TIMING_VAL_64M_CLK_400KHZ 0x00E22163 // Fast Mode with Rise time = 120ns, Fall time = 120ns +#define TIMING_VAL_64M_CLK_1MHZ 0x00A00D1E // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns +#define I2C_PCLK_HSI 64000000 // 64 MHz + +#define TIMING_VAL_72M_CLK_100KHZ 0x10D28DCB // Standard mode with Rise time = 120ns, Fall time = 120ns +#define TIMING_VAL_72M_CLK_400KHZ 0x00F32571 // Fast Mode with Rise time = 120ns, Fall time = 120ns +#define TIMING_VAL_72M_CLK_1MHZ 0x00C00D24 // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns +#define I2C_PCLK_HSE 72000000 // 72 MHz + #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI) +/* Define IP version */ +#define I2C_IP_VERSION_V2 + /* Family specifc settings for clock source */ #define I2CAPI_I2C1_CLKSRC RCC_I2C1CLKSOURCE_SYSCLK #define I2CAPI_I2C2_CLKSRC RCC_I2C2CLKSOURCE_SYSCLK #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_SYSCLK -/* Provide the suitable timing depending on requested frequencie */ -static inline uint32_t get_i2c_timing(int hz) -{ - uint32_t tim = 0; - /* - Values calculated with I2C_Timing_Configuration_V1.0.1.xls file (see AN4235) - * Standard mode (up to 100 kHz) - * Fast Mode (up to 400 kHz) - * Fast Mode Plus (up to 1 MHz) - Below values obtained with: - - I2C clock source = 64 MHz (System Clock w/ HSI) or 72 (System Clock w/ HSE) - - Analog filter delay = ON - - Digital filter coefficient = 0 - */ - if (SystemCoreClock == 64000000) { - switch (hz) { - case 100000: - tim = 0x10B17DB4; // Standard mode with Rise time = 120ns, Fall time = 120ns - break; - case 400000: - tim = 0x00E22163; // Fast Mode with Rise time = 120ns, Fall time = 120ns - break; - case 1000000: - tim = 0x00A00D1E; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns - break; - default: - break; - } - } else if (SystemCoreClock == 72000000) { - switch (hz) { - case 100000: - tim = 0x10D28DCB; // Standard mode with Rise time = 120ns, Fall time = 120ns - break; - case 400000: - tim = 0x00F32571; // Fast Mode with Rise time = 120ns, Fall time = 120ns - break; - case 1000000: - tim = 0x00C00D24; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns - break; - default: - break; - } - } - return tim; -} +uint32_t i2c_get_pclk(I2CName i2c); +uint32_t i2c_get_timing(I2CName i2c, int hz); + +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq); +void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t I2C_speed); +uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t I2C_speed); +#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + +#endif // DEVICE_I2C #ifdef __cplusplus } #endif -#endif // DEVICE_I2C - #endif diff --git a/targets/TARGET_STM/TARGET_STM32F3/objects.h b/targets/TARGET_STM/TARGET_STM32F3/objects.h index a5489d0b98..b947130665 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F3/objects.h @@ -113,6 +113,9 @@ struct i2c_s { uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32F3/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32F3/us_ticker_data.h index 043950aee9..713e11a11d 100644 --- a/targets/TARGET_STM/TARGET_STM32F3/us_ticker_data.h +++ b/targets/TARGET_STM/TARGET_STM32F3/us_ticker_data.h @@ -18,13 +18,13 @@ #define __US_TICKER_DATA_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #include "stm32f3xx.h" #include "stm32f3xx_ll_tim.h" #include "cmsis_nvic.h" - + #define TIM_MST TIM2 #define TIM_MST_IRQ TIM2_IRQn #define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c index e7f27727b8..e60fee8f1d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/system_clock.c @@ -106,8 +106,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) HAL_RCC_GetOscConfig(&RCC_OscInitStruct); /* PLL could be already configured by bootlader */ - if (RCC_OscInitStruct.PLL.PLLState != RCC_PLL_ON) - { + if (RCC_OscInitStruct.PLL.PLLState != RCC_PLL_ON) { /* Enable HSE oscillator and activate PLL with HSE as source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; if (bypass == 0) { diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/TargetInit.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/TargetInit.c index 38905fb0a7..c9c89ca985 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/TargetInit.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/TargetInit.c @@ -15,7 +15,8 @@ #include "stm32f4xx.h" -void TargetBSP_Init(void) { +void TargetBSP_Init(void) +{ /* In DISCO_F413ZH board, Arduino connector and Wifi embeded module are sharing the same SPI pins */ /* We need to set the default SPI SS pin for the Wifi module to the inactive state i.e. 1 */ /* See board User Manual: WIFI_SPI_CS = PG_11*/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h index 0a023971f3..1770f451d5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/PinNames.h @@ -290,7 +290,7 @@ typedef enum { D69 = PF_1, D70 = PF_2, D71 = PA_7, - + // STDIO for console print #ifdef MBED_CONF_TARGET_STDIO_UART_TX CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, @@ -394,4 +394,3 @@ typedef enum { #endif #endif - \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h index 127813a35f..b4b02a07cb 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/PinNames.h @@ -287,7 +287,7 @@ typedef enum { D69 = PF_1, D70 = PF_2, D71 = PA_7, - + // STDIO for console print #ifdef MBED_CONF_TARGET_STDIO_UART_TX CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, @@ -387,4 +387,3 @@ typedef enum { #endif #endif - \ No newline at end of file diff --git a/targets/TARGET_STM/TARGET_STM32F4/can_device.h b/targets/TARGET_STM/TARGET_STM32F4/can_device.h index 1a12fec282..ece0a52017 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F4/can_device.h @@ -70,4 +70,8 @@ extern "C" { #endif // DEVICE_CAN +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/i2c_device.h b/targets/TARGET_STM/TARGET_STM32F4/i2c_device.h index fc229220ed..604b7bafc8 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32F4/i2c_device.h @@ -31,4 +31,8 @@ extern "C" { #endif // DEVICE_I2C +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F4/objects.h b/targets/TARGET_STM/TARGET_STM32F4/objects.h index 73eb6e690b..69460b4d1f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F4/objects.h @@ -106,12 +106,15 @@ struct i2c_s { int scl_func; IRQn_Type event_i2cIRQ; IRQn_Type error_i2cIRQ; - uint8_t XferOperation; + uint32_t XferOperation; volatile uint8_t event; #if DEVICE_I2CSLAVE uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32F7/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32F7/CMakeLists.txt index a7e0becfd3..9cada3e83c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32F7/CMakeLists.txt @@ -15,6 +15,7 @@ target_sources(mbed-stm32f7 analogout_device.c flash_api.c gpio_irq_device.c + i2c_device.c pwmout_device.c serial_device.c spi_api.c diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f745xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f745xx.h index 658fb72e1a..25039936b6 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f745xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f745xx.h @@ -475,7 +475,8 @@ typedef struct __IO uint32_t PTPTTLR; __IO uint32_t RESERVED8; __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; + __IO uint32_t PTPPPSCR; + uint32_t RESERVED9[564]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; @@ -12899,6 +12900,30 @@ typedef struct #define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */ /****************** Bit definition for SYSCFG_PMC register ******************/ +#define SYSCFG_PMC_I2C1_FMP_Pos (0U) +#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */ +#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C2_FMP_Pos (1U) +#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */ +#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C3_FMP_Pos (2U) +#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */ +#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C4_FMP_Pos (3U) +#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */ +#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U) +#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */ +#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U) +#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */ +#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U) +#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */ +#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U) +#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */ +#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */ #define SYSCFG_PMC_ADCxDC2_Pos (16U) #define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */ @@ -15221,6 +15246,11 @@ typedef struct #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */ #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */ +/* Bit definition for Ethernet PTP PPS Control Register */ +#define ETH_PTPPPSCR_PPSFREQ_Pos (0U) +#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */ +#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */ + /******************************************************************************/ /* Ethernet DMA Registers bits definition */ /******************************************************************************/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f746xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f746xx.h index 24de996f92..3da6583903 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f746xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f746xx.h @@ -477,7 +477,8 @@ typedef struct __IO uint32_t PTPTTLR; __IO uint32_t RESERVED8; __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; + __IO uint32_t PTPPPSCR; + uint32_t RESERVED9[564]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; @@ -13247,6 +13248,30 @@ typedef struct #define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */ /****************** Bit definition for SYSCFG_PMC register ******************/ +#define SYSCFG_PMC_I2C1_FMP_Pos (0U) +#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */ +#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C2_FMP_Pos (1U) +#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */ +#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C3_FMP_Pos (2U) +#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */ +#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C4_FMP_Pos (3U) +#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */ +#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U) +#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */ +#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U) +#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */ +#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U) +#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */ +#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U) +#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */ +#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */ #define SYSCFG_PMC_ADCxDC2_Pos (16U) #define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */ @@ -15569,6 +15594,11 @@ typedef struct #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */ #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */ +/* Bit definition for Ethernet PTP PPS Control Register */ +#define ETH_PTPPPSCR_PPSFREQ_Pos (0U) +#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */ +#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */ + /******************************************************************************/ /* Ethernet DMA Registers bits definition */ /******************************************************************************/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f750xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f750xx.h index 65480da755..4a0cee6020 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f750xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f750xx.h @@ -478,7 +478,8 @@ typedef struct __IO uint32_t PTPTTLR; __IO uint32_t RESERVED8; __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; + __IO uint32_t PTPPPSCR; + uint32_t RESERVED9[564]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; @@ -13540,6 +13541,30 @@ typedef struct #define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */ /****************** Bit definition for SYSCFG_PMC register ******************/ +#define SYSCFG_PMC_I2C1_FMP_Pos (0U) +#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */ +#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C2_FMP_Pos (1U) +#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */ +#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C3_FMP_Pos (2U) +#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */ +#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C4_FMP_Pos (3U) +#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */ +#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U) +#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */ +#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U) +#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */ +#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U) +#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */ +#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U) +#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */ +#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */ #define SYSCFG_PMC_ADCxDC2_Pos (16U) #define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */ @@ -15862,6 +15887,11 @@ typedef struct #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */ #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */ +/* Bit definition for Ethernet PTP PPS Control Register */ +#define ETH_PTPPPSCR_PPSFREQ_Pos (0U) +#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */ +#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */ + /******************************************************************************/ /* Ethernet DMA Registers bits definition */ /******************************************************************************/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f756xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f756xx.h index ff1052363e..0c889c7179 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f756xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f756xx.h @@ -478,7 +478,8 @@ typedef struct __IO uint32_t PTPTTLR; __IO uint32_t RESERVED8; __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; + __IO uint32_t PTPPPSCR; + uint32_t RESERVED9[564]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; @@ -13540,6 +13541,30 @@ typedef struct #define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */ /****************** Bit definition for SYSCFG_PMC register ******************/ +#define SYSCFG_PMC_I2C1_FMP_Pos (0U) +#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */ +#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C2_FMP_Pos (1U) +#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */ +#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C3_FMP_Pos (2U) +#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */ +#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C4_FMP_Pos (3U) +#define SYSCFG_PMC_I2C4_FMP_Msk (0x1UL << SYSCFG_PMC_I2C4_FMP_Pos) /*!< 0x00000008 */ +#define SYSCFG_PMC_I2C4_FMP SYSCFG_PMC_I2C4_FMP_Msk /*!< I2C4_FMP I2C4 Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U) +#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */ +#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U) +#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */ +#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U) +#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */ +#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */ +#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U) +#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */ +#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */ #define SYSCFG_PMC_ADCxDC2_Pos (16U) #define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */ @@ -15862,6 +15887,11 @@ typedef struct #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */ #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */ +/* Bit definition for Ethernet PTP PPS Control Register */ +#define ETH_PTPPPSCR_PPSFREQ_Pos (0U) +#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */ +#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */ + /******************************************************************************/ /* Ethernet DMA Registers bits definition */ /******************************************************************************/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f765xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f765xx.h index 97845ad3a3..0dd0b24746 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f765xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f765xx.h @@ -519,7 +519,8 @@ typedef struct __IO uint32_t PTPTTLR; __IO uint32_t RESERVED8; __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; + __IO uint32_t PTPPPSCR; + uint32_t RESERVED9[564]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; @@ -15879,6 +15880,11 @@ typedef struct #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */ #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */ +/* Bit definition for Ethernet PTP PPS Control Register */ +#define ETH_PTPPPSCR_PPSFREQ_Pos (0U) +#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */ +#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */ + /******************************************************************************/ /* Ethernet DMA Registers bits definition */ /******************************************************************************/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f767xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f767xx.h index 2f9a672997..e89cc7d19f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f767xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f767xx.h @@ -522,7 +522,8 @@ typedef struct __IO uint32_t PTPTTLR; __IO uint32_t RESERVED8; __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; + __IO uint32_t PTPPPSCR; + uint32_t RESERVED9[564]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; @@ -16273,6 +16274,11 @@ typedef struct #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */ #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */ +/* Bit definition for Ethernet PTP PPS Control Register */ +#define ETH_PTPPPSCR_PPSFREQ_Pos (0U) +#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */ +#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */ + /******************************************************************************/ /* Ethernet DMA Registers bits definition */ /******************************************************************************/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f769xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f769xx.h index 88afec7cf7..e11eb75b16 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f769xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f769xx.h @@ -523,7 +523,8 @@ typedef struct __IO uint32_t PTPTTLR; __IO uint32_t RESERVED8; __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; + __IO uint32_t PTPPPSCR; + uint32_t RESERVED9[564]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; @@ -16368,6 +16369,11 @@ typedef struct #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */ #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */ +/* Bit definition for Ethernet PTP PPS Control Register */ +#define ETH_PTPPPSCR_PPSFREQ_Pos (0U) +#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */ +#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */ + /******************************************************************************/ /* Ethernet DMA Registers bits definition */ /******************************************************************************/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f777xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f777xx.h index c5bcd8a63d..4e4b2db115 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f777xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f777xx.h @@ -523,7 +523,8 @@ typedef struct __IO uint32_t PTPTTLR; __IO uint32_t RESERVED8; __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; + __IO uint32_t PTPPPSCR; + uint32_t RESERVED9[564]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; @@ -16566,6 +16567,11 @@ typedef struct #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */ #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */ +/* Bit definition for Ethernet PTP PPS Control Register */ +#define ETH_PTPPPSCR_PPSFREQ_Pos (0U) +#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */ +#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */ + /******************************************************************************/ /* Ethernet DMA Registers bits definition */ /******************************************************************************/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f779xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f779xx.h index 5565a0b34e..2af746576a 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f779xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f779xx.h @@ -524,7 +524,8 @@ typedef struct __IO uint32_t PTPTTLR; __IO uint32_t RESERVED8; __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; + __IO uint32_t PTPPPSCR; + uint32_t RESERVED9[564]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; @@ -16661,6 +16662,11 @@ typedef struct #define ETH_PTPTSSR_TSSO_Msk (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */ #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */ +/* Bit definition for Ethernet PTP PPS Control Register */ +#define ETH_PTPPPSCR_PPSFREQ_Pos (0U) +#define ETH_PTPPPSCR_PPSFREQ_Msk (0x0FUL << ETH_PTPPPSCR_PPSFREQ_Pos) /*!< 0x0000000F */ +#define ETH_PTPPPSCR_PPSFREQ ETH_PTPPPSCR_PPSFREQ_Msk /* PPS frequency selection */ + /******************************************************************************/ /* Ethernet DMA Registers bits definition */ /******************************************************************************/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f7xx.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f7xx.h index 84f9de4503..5bc217f80c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f7xx.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMSIS/stm32f7xx.h @@ -97,11 +97,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.2.5 + * @brief CMSIS Device version number V1.2.6 */ #define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F7_CMSIS_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */ +#define __STM32F7_CMSIS_VERSION_SUB2 (0x06) /*!< [15:8] sub2 version */ #define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\ |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMakeLists.txt index 1f9c78b97d..95653610e2 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/CMakeLists.txt @@ -6,7 +6,6 @@ add_library(mbed-stm32f7cube-fw INTERFACE) target_sources(mbed-stm32f7cube-fw INTERFACE system_stm32f7xx.c - STM32F7xx_HAL_Driver/Legacy/stm32f7xx_hal_can_legacy.c STM32F7xx_HAL_Driver/stm32f7xx_hal.c STM32F7xx_HAL_Driver/stm32f7xx_hal_adc.c @@ -95,8 +94,6 @@ target_sources(mbed-stm32f7cube-fw STM32F7xx_HAL_Driver/stm32f7xx_ll_usart.c STM32F7xx_HAL_Driver/stm32f7xx_ll_usb.c STM32F7xx_HAL_Driver/stm32f7xx_ll_utils.c - system_stm32f7xx.c - ) target_include_directories(mbed-stm32f7cube-fw diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/Legacy/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/Legacy/stm32_hal_legacy.h index 90767ed33b..299ed70498 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/Legacy/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/Legacy/stm32_hal_legacy.h @@ -23,7 +23,7 @@ #define STM32_HAL_LEGACY #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -38,7 +38,6 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - /** * @} */ @@ -241,7 +240,7 @@ #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -313,8 +312,13 @@ #endif /* STM32L4 */ #if defined(STM32G0) -#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 -#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 +#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM #endif #if defined(STM32H7) @@ -591,24 +595,24 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/ #if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 @@ -643,6 +647,10 @@ #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable #define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable #define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset +#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A +#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B +#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL +#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL #endif /* STM32G4 */ #if defined(STM32H7) @@ -765,49 +773,6 @@ #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) -/** @brief Constants defining the events that can be selected to configure the - * set/reset crossbar of a timer output - */ -#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) -#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) -#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) -#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) -#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) -#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) -#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) -#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) -#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) - -#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) -#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) -#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) -#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) -#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) -#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) -#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) -#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) -#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) - -/** @brief Constants defining the event filtering applied to external events - * by a timer - */ -#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) - /** @brief Constants defining the DLL calibration periods (in micro seconds) */ #define HRTIM_CALIBRATIONRATE_7300 0x00000000U @@ -955,11 +920,16 @@ #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) +#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) #define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif /** * @} @@ -971,15 +941,15 @@ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #if defined(STM32H7) - #define I2S_IT_TXE I2S_IT_TXP - #define I2S_IT_RXNE I2S_IT_RXP +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP - #define I2S_FLAG_TXE I2S_FLAG_TXP - #define I2S_FLAG_RXNE I2S_FLAG_RXP +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP #endif #if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** * @} @@ -1114,16 +1084,16 @@ #if defined(STM32H7) - #define SPI_FLAG_TXE SPI_FLAG_TXP - #define SPI_FLAG_RXNE SPI_FLAG_RXP +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP - #define SPI_IT_TXE SPI_IT_TXP - #define SPI_IT_RXNE SPI_IT_RXP +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP - #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET - #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET - #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET - #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET #endif /* STM32H7 */ @@ -1450,7 +1420,7 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY -#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End @@ -1472,7 +1442,7 @@ #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT -#endif /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */ +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1486,7 +1456,8 @@ #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1494,7 +1465,8 @@ #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode @@ -1517,9 +1489,9 @@ #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - /** +/** * @} - */ + */ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ @@ -1529,20 +1501,21 @@ #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ + )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */ +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ #if defined(STM32F4) #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT @@ -1554,19 +1527,19 @@ #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA #endif /* STM32F4 */ - /** +/** * @} - */ + */ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ */ #if defined(STM32G0) -#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD -#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD -#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD -#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler +#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD +#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD +#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD +#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler #endif #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg @@ -1611,9 +1584,9 @@ #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - /** +/** * @} - */ + */ /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ @@ -1862,15 +1835,15 @@ #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC #if defined(STM32H7) - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 #else - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG #endif /* STM32H7 */ #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT @@ -2081,8 +2054,8 @@ */ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) /** * @} @@ -2138,7 +2111,7 @@ #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT #if defined(STM32H7) - #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG #endif /** @@ -2275,7 +2248,8 @@ #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -3243,9 +3217,8 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #endif @@ -3373,7 +3346,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3393,19 +3366,19 @@ #else #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ #define IS_ALARM IS_RTC_ALARM @@ -3481,9 +3454,9 @@ #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND +#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS +#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT +#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND /* alias CMSIS for compatibilities */ #define SDIO_IRQn SDMMC1_IRQn #define SDIO_IRQHandler SDMMC1_IRQHandler @@ -3589,6 +3562,13 @@ #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ /** * @} */ @@ -3751,7 +3731,7 @@ /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) +#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE #endif /* STM32L4 || STM32F4 || STM32F7 */ /** diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/Legacy/stm32f7xx_hal_can_legacy.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/Legacy/stm32f7xx_hal_can_legacy.c index f47543a2d3..83a8c46122 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/Legacy/stm32f7xx_hal_can_legacy.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/Legacy/stm32f7xx_hal_can_legacy.c @@ -130,7 +130,7 @@ #error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32f7xx_hal_conf.h file' #endif /* HAL_CAN_MODULE_ENABLED */ -// #warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver' +//#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver' /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal.c index ce308e44a1..e65e36fdfc 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal.c @@ -50,11 +50,11 @@ * @{ */ /** - * @brief STM32F7xx HAL Driver version number V1.2.8 + * @brief STM32F7xx HAL Driver version number V1.2.9 */ #define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __STM32F7xx_HAL_VERSION_SUB2 (0x08) /*!< [15:8] sub2 version */ +#define __STM32F7xx_HAL_VERSION_SUB2 (0x09) /*!< [15:8] sub2 version */ #define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_adc.c index f6b64e7e44..c244fc203b 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_adc.c @@ -3,7 +3,7 @@ * @file stm32f7xx_hal_adc.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) peripheral: + * functionalities of the Analog to Digital Converter (ADC) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + State and errors functions @@ -825,6 +825,14 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) } } } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } /* Return function status */ return HAL_OK; @@ -916,13 +924,17 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti { if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } } } } @@ -987,13 +999,17 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy { if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if(!(__HAL_ADC_GET_FLAG(hadc,EventType))) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } } } } @@ -1131,6 +1147,14 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) } } } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } /* Return function status */ return HAL_OK; @@ -1463,6 +1487,14 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui } } } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } /* Return function status */ return HAL_OK; @@ -1496,7 +1528,17 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* DMA transfer is on going) */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) + { + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status != HAL_OK) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } + } /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); @@ -1574,7 +1616,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) /** * @brief Error ADC callback. * @note In case of error due to overrun when using ADC with DMA transfer - * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_adc.h index 2d882c0250..38a681882a 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_adc.h @@ -52,7 +52,7 @@ * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly). + * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_adc_ex.c index 40f0587620..ec26b35bd6 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_adc_ex.c @@ -221,6 +221,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) } } } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } /* Return function status */ return HAL_OK; @@ -313,6 +321,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) } } } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } /* Return function status */ return HAL_OK; @@ -399,10 +415,14 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u { if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { - hadc->State= HAL_ADC_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + { + hadc->State= HAL_ADC_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hadc); + return HAL_TIMEOUT; + } } } } @@ -666,6 +686,14 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } /* Return function status */ return HAL_OK; diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_can.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_can.c index 954f5ce3c7..96c6d80eb7 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_can.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_can.c @@ -120,7 +120,7 @@ submitted (the sleep mode is not yet entered), and become HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. - (#) The wake-up from sleep mode can be trigged by two ways: + (#) The wake-up from sleep mode can be triggered by two ways: (++) Using HAL_CAN_WakeUp(). When returning from this function, the sleep mode is exited (if return status is HAL_OK). (++) When a start of Rx CAN frame is detected by the CAN peripheral, @@ -1901,7 +1901,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) /* Check if message is still pending */ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) { - /* Receive FIFO 0 mesage pending Callback */ + /* Receive FIFO 0 message pending Callback */ #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo0MsgPendingCallback(hcan); @@ -1950,7 +1950,7 @@ void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) /* Check if message is still pending */ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) { - /* Receive FIFO 1 mesage pending Callback */ + /* Receive FIFO 1 message pending Callback */ #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Call registered callback*/ hcan->RxFifo1MsgPendingCallback(hcan); diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_can.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_can.h index c076e077fd..54038285f1 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_can.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_can.h @@ -255,7 +255,7 @@ typedef enum HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */ HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */ HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */ - HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up fropm Rx msg callback ID */ + HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */ HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */ HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */ @@ -295,11 +295,11 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to #define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ #define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ #define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ -#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ -#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */ #define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ #define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ #define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cec.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cec.c index 3f3802ed07..5e2877bd2b 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cec.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cec.c @@ -822,19 +822,15 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* CEC TX byte request interrupt ------------------------------------------------*/ if ((reg & CEC_FLAG_TXBR) != 0U) { + --hcec->TxXferCount; if (hcec->TxXferCount == 0U) { /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ __HAL_CEC_LAST_BYTE_TX_SET(hcec); - hcec->Instance->TXDR = *hcec->pTxBuffPtr; - hcec->pTxBuffPtr++; - } - else - { - hcec->Instance->TXDR = *hcec->pTxBuffPtr; - hcec->pTxBuffPtr++; - hcec->TxXferCount--; } + /* In all cases transmit the byte */ + hcec->Instance->TXDR = *hcec->pTxBuffPtr; + hcec->pTxBuffPtr++; /* clear Tx-Byte request flag */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); } diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cec.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cec.h index ed7ee8c557..721edc1c2a 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cec.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cec.h @@ -121,7 +121,7 @@ typedef struct * b6 Error information * 0 : No Error * 1 : Error - * b5 IP initilisation status + * b5 IP initialization status * 0 : Reset (IP not initialized) * 1 : Init done (IP initialized. HAL CEC Init function already called) * b4-b3 (not used) @@ -138,7 +138,7 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initilisation status + * b5 IP initialization status * 0 : Reset (IP not initialized) * 1 : Init done (IP initialized) * b4-b2 (not used) diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_crc.h index ece8790235..08a5025d01 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_crc.h @@ -267,7 +267,6 @@ typedef struct #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) - #define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_crc_ex.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_crc_ex.c index 004cb3ae67..d542da1197 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_crc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_crc_ex.c @@ -11,7 +11,7 @@ ##### How to use this driver ##### ================================================================================ [..] - (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set() + (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set() (+) Configure Input or Output data inversion @endverbatim diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp.c index adc35bd9d8..6b9424412c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp.c @@ -586,6 +586,8 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD hcryp->Init.HeaderSize = pConf->HeaderSize; hcryp->Init.B0 = pConf->B0; hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; + hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; + hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; /* Set the key size(This bit field is don’t care in the DES or TDES modes) data type, AlgoMode and operating mode*/ #if defined (CRYP) @@ -660,7 +662,9 @@ HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD pConf->Header = hcryp->Init.Header ; pConf->HeaderSize = hcryp->Init.HeaderSize; pConf->B0 = hcryp->Init.B0; - pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip; + pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit; /* Process Unlocked */ __HAL_UNLOCK(hcryp); @@ -692,8 +696,8 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspInit could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRYP_MspInit can be implemented in the user file */ } @@ -708,8 +712,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspDeInit could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRYP_MspDeInit can be implemented in the user file */ } @@ -2157,8 +2161,8 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_InCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRYP_InCpltCallback can be implemented in the user file */ } @@ -2173,8 +2177,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_OutCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_CRYP_OutCpltCallback can be implemented in the user file */ } @@ -5534,17 +5538,17 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) - { - /* Call Input transfer complete callback */ + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) + { + /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } + } } else /* Last block of payload < 128bit*/ { @@ -5593,10 +5597,24 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint32_t loopcounter; + uint32_t size_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ - if ((hcryp->Init.HeaderSize != 0U)) + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + size_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + size_in_bytes = hcryp->Init.HeaderSize; + } + + if (size_in_bytes != 0U) { #if defined(CRYP) @@ -5607,10 +5625,10 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - if ((hcryp->Init.HeaderSize % 4U) == 0U) + if ((size_in_bytes % 16U) == 0U) { /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) + for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U) { hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; @@ -5640,7 +5658,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u else { /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) + for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U) { hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; @@ -5667,16 +5685,34 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } } /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++) { hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while (loopcounter < 4U) + /* If the header size is a multiple of words */ + if ((size_in_bytes % 4U) == 0U) { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DIN = 0x0U; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DIN = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeroes */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; + hcryp->Instance->DIN = tmp; loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DIN = 0x0U; + loopcounter++; + } } /* Wait for CCF IFEM to be raised */ if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) @@ -5722,10 +5758,11 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u __HAL_CRYP_ENABLE(hcryp); } - if ((hcryp->Init.HeaderSize % 4U) == 0U) + /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */ + if ((size_in_bytes % 16U) == 0U) { - /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) + /* No padding */ + for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U) { /* Write the input block in the data input register */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -5757,7 +5794,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u else { /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) + for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U) { /* Write the input block in the data input register */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -5785,17 +5822,35 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + /* Write last complete words */ + for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while (loopcounter < 4U) + /* If the header size is a multiple of words */ + if ((size_in_bytes % 4U) == 0U) { - /*Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeroes */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) @@ -5846,9 +5901,23 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry { __IO uint32_t count = 0U; uint32_t loopcounter; + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ - if ((hcryp->Init.HeaderSize != 0U)) + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + if (headersize_in_bytes != 0U) { #if defined(CRYP) @@ -5859,10 +5928,10 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - if ((hcryp->Init.HeaderSize % 4U) == 0U) + if ((headersize_in_bytes % 16U) == 0U) { /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U) { hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; @@ -5897,7 +5966,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry else { /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U) { hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; @@ -5929,16 +5998,34 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) { hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while (loopcounter < 4U) + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) { /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DIN = 0x0U; + while (loopcounter < 4U) + { + hcryp->Instance->DIN = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeroes */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DIN = tmp; loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DIN = 0x0U; + loopcounter++; + } } /* Wait for IFEM to be raised */ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; @@ -5993,10 +6080,10 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); } - if ((hcryp->Init.HeaderSize % 4U) == 0U) + if ((headersize_in_bytes % 16U) == 0U) { /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U) { /* Write the input block in the data input register */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -6035,7 +6122,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry else { /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U) { /* Write the Input block in the Data Input register */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -6071,18 +6158,35 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes /4U) % 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while (loopcounter < 4U) + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) { /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeroes */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } } - /*Wait on CCF flag*/ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; do @@ -6141,10 +6245,25 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) uint32_t lastwordsize; uint32_t npblb; #endif + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + /***************************** Header phase *********************************/ #if defined(CRYP) - if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) + if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U)) { /* Disable interrupts */ __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); @@ -6164,7 +6283,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); } - else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U) + else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U) { /* HeaderSize %4, no padding */ @@ -6180,21 +6299,41 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) else { /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) + for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++) { hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while (loopcounter < 4U) + if ((headersize_in_bytes % 4U) == 0U) { /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DIN = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DIN = tmp; + loopcounter++; + hcryp->CrypHeaderCount++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { hcryp->Instance->DIN = 0x0U; loopcounter++; + hcryp->CrypHeaderCount++; + } } } #else /* AES */ - if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) + if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U)) { /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -6278,7 +6417,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) } } } - else if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U) + else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U) { /* Write the input block in the IN FIFO */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -6293,16 +6432,37 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/ { /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) + for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + hcryp->CrypHeaderCount++; + /* Pad the data with zeros to have a complete block */ while (loopcounter < 4U) { - /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; loopcounter++; + hcryp->CrypHeaderCount++; + } } } #endif /* End AES or CRYP */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp.h index 076d2cd280..83bffaf10e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp.h @@ -65,6 +65,7 @@ typedef struct uint32_t HeaderSize; /*!< The size of header buffer in word */ uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ + uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/ uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization Vector only once and to skip configuration for consecutive processings. This parameter can be a value of @ref CRYP_Configuration_Skip */ @@ -214,6 +215,17 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @} */ +/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit + * @{ + */ + +#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */ +#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */ + +/** + * @} + */ + /** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp_ex.c index 1a7a6b9ede..5bcce35223 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_cryp_ex.c @@ -128,10 +128,17 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) { uint32_t tickstart; + /* Assume first Init.HeaderSize is in words */ uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */ - uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */ + uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */ uint32_t tagaddr = (uint32_t)AuthTag; + /* Correct headerlength if Init.HeaderSize is actually in bytes */ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE) + { + headerlength /= 4U; + } + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Process locked */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac.c index 42b6d0834c..98b57c2992 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac.c @@ -3,124 +3,134 @@ * @file stm32f7xx_hal_dac.c * @author MCD Application Team * @brief DAC HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions - * + Peripheral State and Errors functions - * + * + Peripheral State and Errors functions * - @verbatim + * + @verbatim ============================================================================== ##### DAC Peripheral features ##### ============================================================================== - [..] + [..] *** DAC Channels *** - ==================== - [..] - The device integrates two 12-bit Digital Analog Converters that can + ==================== + [..] + STM32F7 devices integrates two 12-bit Digital Analog Converters that can be used independently or simultaneously (dual mode): (#) DAC channel1 with DAC_OUT1 (PA4) as output (#) DAC channel2 with DAC_OUT2 (PA5) as output - + *** DAC Triggers *** ==================== [..] Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE - and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. - [..] + and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. + [..] Digital to Analog conversion can be triggered by: (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9. The used pin (GPIOx_Pin9) must be configured in input mode. - - (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 + + (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...) - + (#) Software using DAC_TRIGGER_SOFTWARE - + *** DAC Buffer mode feature *** - =============================== - [..] - Each DAC channel integrates an output buffer that can be used to + =============================== + [..] + Each DAC channel integrates an output buffer that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. - To enable, the output buffer use + To enable, the output buffer use sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; - [..] - (@) Refer to the device datasheet for more details about output + [..] + (@) Refer to the device datasheet for more details about output impedance value with and without output buffer. - + *** DAC wave generation feature *** - =================================== - [..] + =================================== + [..] Both DAC channels can be used to generate - (#) Noise wave using HAL_DACEx_NoiseWaveGenerate() - (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate() - + (#) Noise wave + (#) Triangle wave + *** DAC data format *** ======================= - [..] + [..] The DAC data format can be: (#) 8-bit right alignment using DAC_ALIGN_8B_R (#) 12-bit left alignment using DAC_ALIGN_12B_L (#) 12-bit right alignment using DAC_ALIGN_12B_R - - *** DAC data value to voltage correspondence *** - ================================================ - [..] - The analog output voltage on each DAC channel pin is determined - by the following equation: - DAC_OUTx = VREF+ * DOR / 4095 - with DOR is the Data Output Register - VEF+ is the input voltage reference (refer to the device datasheet) - e.g. To set DAC_OUT1 to 0.7V, use - Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V - - *** DMA requests *** - ===================== - [..] - A DMA1 request can be generated when an external trigger (but not - a software trigger) occurs if DMA1 requests are enabled using - HAL_DAC_Start_DMA() + + *** DAC data value to voltage correspondence *** + ================================================ [..] + The analog output voltage on each DAC channel pin is determined + by the following equation: + [..] + DAC_OUTx = VREF+ * DOR / 4095 + (+) with DOR is the Data Output Register + [..] + VREF+ is the input voltage reference (refer to the device datasheet) + [..] + e.g. To set DAC_OUT1 to 0.7V, use + (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V + + *** DMA requests *** + ===================== + [..] + A DMA request can be generated when an external trigger (but not a software trigger) + occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA(). DMA1 requests are mapped as following: - (#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be - already configured - (#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be - already configured - - -@- For Dual mode and specific signal (Triangle and noise) generation please - refer to Extension Features Driver description - - + (#) DAC channel1 mapped on DMA1 Stream5 channel7 which must be + already configured + (#) DAC channel2 mapped on DMA1 Stream6 channel7 which must be + already configured + + [..] + (@) For Dual mode and specific signal (Triangle and noise) generation please + refer to Extended Features Driver description + ##### How to use this driver ##### ============================================================================== - [..] + [..] (+) DAC APB clock must be enabled to get write access to DAC registers using HAL_DAC_Init() (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. - (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions + (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions. + *** Polling mode IO operation *** ================================= - [..] - (+) Start the DAC peripheral using HAL_DAC_Start() + [..] + (+) Start the DAC peripheral using HAL_DAC_Start() (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function. (+) Stop the DAC peripheral using HAL_DAC_Stop() - - *** DMA mode IO operation *** + *** DMA mode IO operation *** ============================== - [..] - (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length - of data to be transferred at each end of conversion - (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2() - function is executed and user can add his own code by customization of function pointer - HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2 - (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can + [..] + (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion + First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue(). + (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() + (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 + (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. + HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and + add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1() (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() *** Callback registration *** @@ -178,21 +188,21 @@ When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. - + *** DAC HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in DAC HAL driver. - + (+) __HAL_DAC_ENABLE : Enable the DAC peripheral (+) __HAL_DAC_DISABLE : Disable the DAC peripheral (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status - + [..] - (@) You can refer to the DAC HAL driver header file for more useful macros - - @endverbatim + (@) You can refer to the DAC HAL driver header file for more useful macros + +@endverbatim ****************************************************************************** * @attention * @@ -205,8 +215,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ - + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" @@ -215,67 +224,60 @@ * @{ */ +#ifdef HAL_DAC_MODULE_ENABLED +#if defined(DAC) + /** @defgroup DAC DAC * @brief DAC driver modules * @{ - */ - -#ifdef HAL_DAC_MODULE_ENABLED + */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/** @addtogroup DAC_Private_Functions - * @{ - */ /* Private function prototypes -----------------------------------------------*/ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); -/** - * @} - */ +/* Exported functions -------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ /** @defgroup DAC_Exported_Functions DAC Exported Functions * @{ */ -/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim +/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim ============================================================================== ##### Initialization and de-initialization functions ##### ============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the DAC. - (+) De-initialize the DAC. - + (+) Initialize and configure the DAC. + (+) De-initialize the DAC. + @endverbatim * @{ */ /** - * @brief Initializes the DAC peripheral according to the specified parameters - * in the DAC_InitStruct. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Initialize the DAC peripheral according to the specified parameters + * in the DAC_InitStruct and initialize the associated handle. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) -{ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) +{ /* Check DAC handle */ - if(hdac == NULL) + if (hdac == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); - - if(hdac->State == HAL_DAC_STATE_RESET) - { + + if (hdac->State == HAL_DAC_STATE_RESET) + { #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the DAC Callback settings */ hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; @@ -288,13 +290,15 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; - if(hdac->MspInitCallback == NULL) + if (hdac->MspInitCallback == NULL) { - hdac->MspInitCallback = HAL_DAC_MspInit; + hdac->MspInitCallback = HAL_DAC_MspInit; } #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /* Allocate lock resource and initialize it */ - hdac->Lock = HAL_UNLOCKED; + hdac->Lock = HAL_UNLOCKED; + #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /* Init the low level hardware */ hdac->MspInitCallback(hdac); @@ -303,32 +307,32 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) HAL_DAC_MspInit(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } - + /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_BUSY; - + /* Set DAC error code to none */ hdac->ErrorCode = HAL_DAC_ERROR_NONE; - + /* Initialize the DAC state*/ hdac->State = HAL_DAC_STATE_READY; - + /* Return function status */ return HAL_OK; } /** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Deinitialize the DAC peripheral registers to their default reset values. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac) { /* Check DAC handle */ - if(hdac == NULL) + if (hdac == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ @@ -338,7 +342,7 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) hdac->State = HAL_DAC_STATE_BUSY; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - if(hdac->MspDeInitCallback == NULL) + if (hdac->MspDeInitCallback == NULL) { hdac->MspDeInitCallback = HAL_DAC_MspDeInit; } @@ -363,35 +367,35 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) } /** - * @brief Initializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Initialize the DAC MSP. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ -__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) +__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_MspInit could be implemented in the user file - */ + */ } /** - * @brief DeInitializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. + * @brief DeInitialize the DAC MSP. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. * @retval None */ -__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) +__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_MspDeInit could be implemented in the user file - */ + */ } /** @@ -399,139 +403,137 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) */ /** @defgroup DAC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim + * @brief IO operation functions + * +@verbatim ============================================================================== ##### IO operation functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Start conversion. (+) Stop conversion. (+) Start conversion and enable DMA transfer. (+) Stop conversion and disable DMA transfer. (+) Get result of conversion. - + @endverbatim * @{ */ /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) { - uint32_t tmp1 = 0, tmp2 = 0; - /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - + /* Enable the Peripheral */ __HAL_DAC_ENABLE(hdac, Channel); - - if(Channel == DAC_CHANNEL_1) + + if (Channel == DAC_CHANNEL_1) { - tmp1 = hdac->Instance->CR & DAC_CR_TEN1; - tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; /* Check if software trigger enabled */ - if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) + if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) { /* Enable the selected DAC software conversion */ - hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1; + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); } } + else { - tmp1 = hdac->Instance->CR & DAC_CR_TEN2; - tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; /* Check if software trigger enabled */ - if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2)) + if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) { /* Enable the selected DAC software conversion*/ - hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2; + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); } } - + + /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdac); - + /* Return function status */ return HAL_OK; } /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - + /* Disable the Peripheral */ __HAL_DAC_DISABLE(hdac, Channel); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; - + /* Return function status */ return HAL_OK; } /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The Source memory Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, + uint32_t Alignment) { - uint32_t tmpreg = 0; - + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t tmpreg = 0U; + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_ALIGN(Alignment)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - if(Channel == DAC_CHANNEL_1) + if (Channel == DAC_CHANNEL_1) { /* Set the DMA transfer complete callback for channel1 */ hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; @@ -543,10 +545,10 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; /* Enable the selected DAC channel1 DMA request */ - hdac->Instance->CR |= DAC_CR_DMAEN1; - + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + /* Case of use of channel 1 */ - switch(Alignment) + switch (Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R1 address */ @@ -564,6 +566,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u break; } } + else { /* Set the DMA transfer complete callback for channel2 */ @@ -576,10 +579,10 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; /* Enable the selected DAC channel2 DMA request */ - hdac->Instance->CR |= DAC_CR_DMAEN2; + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); /* Case of use of channel 2 */ - switch(Alignment) + switch (Alignment) { case DAC_ALIGN_12B_R: /* Get DHR12R2 address */ @@ -597,79 +600,39 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u break; } } - + + /* Enable the DMA Stream */ - if(Channel == DAC_CHANNEL_1) + if (Channel == DAC_CHANNEL_1) { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); - + /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); - } + status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + } + else { /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); - + /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); + status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } - - /* Enable the Peripheral */ - __HAL_DAC_ENABLE(hdac, Channel); - + + /* Process Unlocked */ __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} -/** - * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Disable the selected DAC channel DMA request */ - hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); - - /* Disable the Peripheral */ - __HAL_DAC_DISABLE(hdac, Channel); - - /* Disable the DMA Channel */ - /* Channel1 is used */ - if(Channel == DAC_CHANNEL_1) - { - status = HAL_DMA_Abort(hdac->DMA_Handle1); - } - else /* Channel2 is used for */ - { - status = HAL_DMA_Abort(hdac->DMA_Handle2); - } - - /* Check if DMA Channel effectively disabled */ - if(status != HAL_OK) + if (status == HAL_OK) { - /* Update DAC state machine to error */ - hdac->State = HAL_DAC_STATE_ERROR; + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, Channel); } else { - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; } /* Return function status */ @@ -677,120 +640,199 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) } /** - * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Disables DAC and stop conversion of channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. + * @retval HAL status */ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); - - /* Returns the DAC channel data output register value */ - if(Channel == DAC_CHANNEL_1) + + /* Disable the selected DAC channel DMA request */ + hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL)); + + /* Disable the Peripheral */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Disable the DMA Stream */ + + /* Channel1 is used */ + if (Channel == DAC_CHANNEL_1) { - return hdac->Instance->DOR1; + /* Disable the DMA Stream */ + (void)HAL_DMA_Abort(hdac->DMA_Handle1); + + /* Disable the DAC DMA underrun interrupt */ + __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); } - else + + else /* Channel2 is used for */ { - return hdac->Instance->DOR2; + /* Disable the DMA Stream */ + (void)HAL_DMA_Abort(hdac->DMA_Handle2); + + /* Disable the DAC DMA underrun interrupt */ + __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); } + + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; } /** - * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Handles DAC interrupt request + * This function uses the interruption of DMA + * underrun. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ -void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) +void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) { - /* Check underrun channel 1 flag */ - if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) { - /* Change DAC state to error state */ - hdac->State = HAL_DAC_STATE_ERROR; - - /* Set DAC error code to channel1 DMA underrun error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; - - /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); - - /* Disable the selected DAC channel1 DMA request */ - hdac->Instance->CR &= ~DAC_CR_DMAEN1; - - /* Error callback */ + /* Check underrun flag of DAC channel 1 */ + if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to channel1 DMA underrun error */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); + + /* Disable the selected DAC channel1 DMA request */ + CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + + /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh1(hdac); #else - HAL_DAC_DMAUnderrunCallbackCh1(hdac); + HAL_DAC_DMAUnderrunCallbackCh1(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } } - /* Check underrun channel 2 flag */ - if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + + + if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) { - /* Change DAC state to error state */ - hdac->State = HAL_DAC_STATE_ERROR; - - /* Set DAC error code to channel2 DMA underrun error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2; - - /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); - - /* Disable the selected DAC channel1 DMA request */ - hdac->Instance->CR &= ~DAC_CR_DMAEN2; - - /* Error callback */ + /* Check underrun flag of DAC channel 2 */ + if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to channel2 DMA underrun error */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); + + /* Disable the selected DAC channel2 DMA request */ + CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); + + /* Error callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->DMAUnderrunCallbackCh2(hdac); #else - HAL_DACEx_DMAUnderrunCallbackCh2(hdac); + HAL_DACEx_DMAUnderrunCallbackCh2(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + } } + } /** - * @brief Conversion complete callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Set the specified data holding register value for DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Alignment Specifies the data alignment. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data Data to be loaded in the selected data holding register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) +{ + __IO uint32_t tmp = 0UL; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)hdac->Instance; + if (Channel == DAC_CHANNEL_1) + { + tmp += DAC_DHR12R1_ALIGNMENT(Alignment); + } + + else + { + tmp += DAC_DHR12R2_ALIGNMENT(Alignment); + } + + + /* Set the DAC channel selected data holding register */ + *(__IO uint32_t *) tmp = Data; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Conversion complete callback in non-blocking mode for Channel1 + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ -__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) +__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ConvCpltCallback could be implemented in the user file + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file */ } /** - * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ -__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) +__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file */ } /** * @brief Error DAC callback for Channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -798,15 +840,15 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file */ } /** * @brief DMA underrun DAC callback for channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -814,8 +856,8 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file */ } @@ -823,111 +865,101 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) /** * @} */ - + /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim + * @brief Peripheral Control functions + * +@verbatim ============================================================================== ##### Peripheral Control functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: - (+) Configure channels. + (+) Configure channels. (+) Set the specified data holding register value for DAC channel. - + @endverbatim * @{ */ /** - * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) +{ + uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + if (Channel == DAC_CHANNEL_1) + { + tmp = hdac->Instance->DOR1; + } + + else + { + tmp = hdac->Instance->DOR2; + } + + /* Returns the DAC channel data output register value */ + return tmp; +} + +/** + * @brief Configures the selected DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { - uint32_t tmpreg1 = 0, tmpreg2 = 0; + uint32_t tmpreg1; + uint32_t tmpreg2; /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); assert_param(IS_DAC_CHANNEL(Channel)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - + /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: buffer output, trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << Channel; + tmpreg1 |= tmpreg2 << (Channel & 0x10UL); /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; /* Disable wave generation */ - hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel); - + CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); + /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} -/** - * @brief Set the specified data holding register value for DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Alignment: Specifies the data alignment. - * This parameter can be one of the following values: - * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected - * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected - * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - assert_param(IS_DAC_ALIGN(Alignment)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)hdac->Instance; - if(Channel == DAC_CHANNEL_1) - { - tmp += DAC_DHR12R1_ALIGNMENT(Alignment); - } - else - { - tmp += DAC_DHR12R2_ALIGNMENT(Alignment); - } - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; - /* Return function status */ return HAL_OK; } @@ -937,37 +969,37 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui */ /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim + * @brief Peripheral State and Errors functions + * +@verbatim ============================================================================== ##### Peripheral State and Errors functions ##### - ============================================================================== + ============================================================================== [..] This subsection provides functions allowing to (+) Check the DAC state. (+) Check the DAC Errors. - + @endverbatim * @{ */ /** - * @brief return the DAC state - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief return the DAC handle state + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL state */ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac) { - /* Return DAC state */ + /* Return DAC handle state */ return hdac->State; } /** * @brief Return the DAC error code - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval DAC Error Code */ @@ -995,9 +1027,9 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) /** * @brief Register a User DAC Callback * To be used instead of the weak (surcharged) predefined callback - * @param hdac DAC handle + * @param hdac DAC handle * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: + * This parameter can be one of the following values: * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID @@ -1007,17 +1039,18 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID - * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID - * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID + * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID * - * @param pCallback pointer to the Callback function + * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, + pDAC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; @@ -1027,64 +1060,66 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_Cal /* Process locked */ __HAL_LOCK(hdac); - if(hdac->State == HAL_DAC_STATE_READY) + if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) { - case HAL_DAC_CH1_COMPLETE_CB_ID : - hdac->ConvCpltCallbackCh1 = pCallback; - break; - case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : - hdac->ConvHalfCpltCallbackCh1 = pCallback; - break; - case HAL_DAC_CH1_ERROR_ID : - hdac->ErrorCallbackCh1 = pCallback; - break; - case HAL_DAC_CH1_UNDERRUN_CB_ID : - hdac->DMAUnderrunCallbackCh1 = pCallback; - break; - case HAL_DAC_CH2_COMPLETE_CB_ID : - hdac->ConvCpltCallbackCh2 = pCallback; - break; - case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : - hdac->ConvHalfCpltCallbackCh2 = pCallback; - break; - case HAL_DAC_CH2_ERROR_ID : - hdac->ErrorCallbackCh2 = pCallback; - break; - case HAL_DAC_CH2_UNDERRUN_CB_ID : - hdac->DMAUnderrunCallbackCh2 = pCallback; - break; - case HAL_DAC_MSP_INIT_CB_ID : - hdac->MspInitCallback = pCallback; - break; - case HAL_DAC_MSP_DEINIT_CB_ID : - hdac->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_DAC_CH1_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_ERROR_ID : + hdac->ErrorCallbackCh1 = pCallback; + break; + case HAL_DAC_CH1_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh1 = pCallback; + break; + + case HAL_DAC_CH2_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_ERROR_ID : + hdac->ErrorCallbackCh2 = pCallback; + break; + case HAL_DAC_CH2_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh2 = pCallback; + break; + + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = pCallback; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else if (hdac->State == HAL_DAC_STATE_RESET) { switch (CallbackID) { - case HAL_DAC_MSP_INIT_CB_ID : - hdac->MspInitCallback = pCallback; - break; - case HAL_DAC_MSP_DEINIT_CB_ID : - hdac->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = pCallback; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1103,10 +1138,10 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_Cal /** * @brief Unregister a User DAC Callback * DAC Callback is redirected to the weak (surcharged) predefined callback - * @param hdac DAC handle + * @param hdac DAC handle * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID + * This parameter can be one of the following values: + * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID @@ -1114,88 +1149,92 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_Cal * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID - * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID - * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID + * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID + * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks * @retval status */ -HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdac); - if(hdac->State == HAL_DAC_STATE_READY) + if (hdac->State == HAL_DAC_STATE_READY) { switch (CallbackID) { - case HAL_DAC_CH1_COMPLETE_CB_ID : - hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; - break; - case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : - hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; - break; - case HAL_DAC_CH1_ERROR_ID : - hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; - break; - case HAL_DAC_CH1_UNDERRUN_CB_ID : - hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; - break; - case HAL_DAC_CH2_COMPLETE_CB_ID : - hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; - break; - case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : - hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; - break; - case HAL_DAC_CH2_ERROR_ID : - hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; - break; - case HAL_DAC_CH2_UNDERRUN_CB_ID : - hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; - break; - case HAL_DAC_MSP_INIT_CB_ID : - hdac->MspInitCallback = HAL_DAC_MspInit; - break; - case HAL_DAC_MSP_DEINIT_CB_ID : - hdac->MspDeInitCallback = HAL_DAC_MspDeInit; - break; - case HAL_DAC_ALL_CB_ID : - hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; - hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; - hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; - hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; - hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; - hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; - hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; - hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; - hdac->MspInitCallback = HAL_DAC_MspInit; - hdac->MspDeInitCallback = HAL_DAC_MspDeInit; - break; - default : - /* Update the error code */ - hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_DAC_CH1_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + break; + case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + break; + case HAL_DAC_CH1_ERROR_ID : + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + break; + case HAL_DAC_CH1_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + break; + + case HAL_DAC_CH2_COMPLETE_CB_ID : + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + break; + case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + break; + case HAL_DAC_CH2_ERROR_ID : + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + break; + case HAL_DAC_CH2_UNDERRUN_CB_ID : + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + break; + + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = HAL_DAC_MspInit; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + case HAL_DAC_ALL_CB_ID : + hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; + hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; + hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; + hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; + hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; + hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; + hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + + hdac->MspInitCallback = HAL_DAC_MspInit; + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else if (hdac->State == HAL_DAC_STATE_RESET) { switch (CallbackID) { - case HAL_DAC_MSP_INIT_CB_ID : - hdac->MspInitCallback = HAL_DAC_MspInit; - break; - case HAL_DAC_MSP_DEINIT_CB_ID : - hdac->MspDeInitCallback = HAL_DAC_MspDeInit; - break; - default : - /* Update the error code */ - hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_DAC_MSPINIT_CB_ID : + hdac->MspInitCallback = HAL_DAC_MspInit; + break; + case HAL_DAC_MSPDEINIT_CB_ID : + hdac->MspDeInitCallback = HAL_DAC_MspDeInit; + break; + default : + /* Update the error code */ + hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1225,73 +1264,75 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_C */ /** - * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA conversion complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) +void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ConvCpltCallbackCh1(hdac); #else - HAL_DAC_ConvCpltCallbackCh1(hdac); + HAL_DAC_ConvCpltCallbackCh1(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - - hdac->State= HAL_DAC_STATE_READY; + + hdac->State = HAL_DAC_STATE_READY; } /** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) +void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Conversion complete callback */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ConvHalfCpltCallbackCh1(hdac); #else - HAL_DAC_ConvHalfCpltCallbackCh1(hdac); + HAL_DAC_ConvHalfCpltCallbackCh1(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } /** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @brief DMA error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) +void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) { - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Set DAC error code to DMA error */ hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - + #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) hdac->ErrorCallbackCh1(hdac); #else - HAL_DAC_ErrorCallbackCh1(hdac); + HAL_DAC_ErrorCallbackCh1(hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - - hdac->State= HAL_DAC_STATE_READY; + + hdac->State = HAL_DAC_STATE_READY; } /** * @} */ +/** + * @} + */ + +#endif /* DAC */ + #endif /* HAL_DAC_MODULE_ENABLED */ -/** - * @} - */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac.h index b86205d5a6..3e01e29ce2 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac.h @@ -18,31 +18,34 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_DAC_H -#define __STM32F7xx_HAL_DAC_H +#ifndef STM32F7xx_HAL_DAC_H +#define STM32F7xx_HAL_DAC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - /** @addtogroup STM32F7xx_HAL_Driver * @{ */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +#if defined(DAC) + /** @addtogroup DAC * @{ */ /* Exported types ------------------------------------------------------------*/ + /** @defgroup DAC_Exported_Types DAC Exported Types * @{ */ -/** - * @brief HAL State structures definition +/** + * @brief HAL State structures definition */ typedef enum { @@ -51,16 +54,17 @@ typedef enum HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ -}HAL_DAC_StateTypeDef; - -/** - * @brief DAC handle Structure definition + +} HAL_DAC_StateTypeDef; + +/** + * @brief DAC handle Structure definition */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) typedef struct __DAC_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ { DAC_TypeDef *Instance; /*!< Register base address */ @@ -73,33 +77,37 @@ typedef struct DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ __IO uint32_t ErrorCode; /*!< DAC Error code */ -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac); - void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac); - void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef* hdac); - void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef* hdac); - void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); - void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac); +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + + void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + + + void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ -}DAC_HandleTypeDef; +} DAC_HandleTypeDef; -/** - * @brief DAC Configuration regular Channel structure definition +/** + * @brief DAC Configuration regular Channel structure definition */ typedef struct { - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_ChannelConfTypeDef; + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ + +} DAC_ChannelConfTypeDef; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) /** @@ -111,25 +119,29 @@ typedef enum HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ + HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ - HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ - HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ + + HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ + HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ -}HAL_DAC_CallbackIDTypeDef; +} HAL_DAC_CallbackIDTypeDef; /** * @brief HAL DAC Callback pointer definition */ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup DAC_Exported_Constants DAC Exported Constants * @{ */ @@ -138,77 +150,87 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @{ */ #define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */ #define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ +#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) #define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /** * @} */ -/** @defgroup DAC_trigger_selection DAC Trigger Selection +/** @defgroup DAC_trigger_selection DAC trigger selection * @{ */ +#define DAC_TRIGGER_NONE 0x00000000UL /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE (DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ - -#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ /** * @} */ -/** @defgroup DAC_output_buffer DAC Output Buffer +/** @defgroup DAC_output_buffer DAC output buffer * @{ */ -#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U) -#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1) +#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U +#define DAC_OUTPUTBUFFER_DISABLE (DAC_CR_BOFF1) + /** * @} */ -/** @defgroup DAC_Channel_selection DAC Channel Selection +/** @defgroup DAC_Channel_selection DAC Channel selection * @{ */ -#define DAC_CHANNEL_1 ((uint32_t)0x00000000U) -#define DAC_CHANNEL_2 ((uint32_t)0x00000010U) +#define DAC_CHANNEL_1 0x00000000U + +#define DAC_CHANNEL_2 0x00000010U + /** * @} */ -/** @defgroup DAC_data_alignment DAC Data Alignment +/** @defgroup DAC_data_alignment DAC data alignment * @{ */ -#define DAC_ALIGN_12B_R ((uint32_t)0x00000000U) -#define DAC_ALIGN_12B_L ((uint32_t)0x00000004U) -#define DAC_ALIGN_8B_R ((uint32_t)0x00000008U) +#define DAC_ALIGN_12B_R 0x00000000U +#define DAC_ALIGN_12B_L 0x00000004U +#define DAC_ALIGN_8B_R 0x00000008U + /** * @} */ -/** @defgroup DAC_flags_definition DAC Flags Definition +/** @defgroup DAC_flags_definition DAC flags definition * @{ - */ -#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) -#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) + */ +#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) + +#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) + + /** * @} */ -/** @defgroup DAC_IT_definition DAC IT Definition +/** @defgroup DAC_IT_definition DAC IT definition * @{ - */ -#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) -#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) + */ +#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) + +#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) + + /** * @} */ @@ -218,92 +240,142 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); */ /* Exported macro ------------------------------------------------------------*/ + /** @defgroup DAC_Exported_Macros DAC Exported Macros * @{ */ -/** @brief Reset DAC handle state - * @param __HANDLE__: specifies the DAC handle. +/** @brief Reset DAC handle state. + * @param __HANDLE__ specifies the DAC handle. * @retval None */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) -#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ -/** @brief Enable the DAC channel - * @param __HANDLE__: specifies the DAC handle. - * @param __DAC_CHANNEL__: specifies the DAC channel +/** @brief Enable the DAC channel. + * @param __HANDLE__ specifies the DAC handle. + * @param __DAC_Channel__ specifies the DAC channel * @retval None */ -#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \ -((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_CHANNEL__))) +#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ + ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) -/** @brief Disable the DAC channel - * @param __HANDLE__: specifies the DAC handle - * @param __DAC_CHANNEL__: specifies the DAC channel. +/** @brief Disable the DAC channel. + * @param __HANDLE__ specifies the DAC handle + * @param __DAC_Channel__ specifies the DAC channel. * @retval None */ -#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \ -((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_CHANNEL__))) +#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ + ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) + +/** @brief Set DHR12R1 alignment. + * @param __ALIGNMENT__ specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__)) -/** @brief Enable the DAC interrupt - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. +/** @brief Set DHR12R2 alignment. + * @param __ALIGNMENT__ specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__)) + + +/** @brief Set DHR12RD alignment. + * @param __ALIGNMENT__ specifies the DAC alignment + * @retval None + */ +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__)) + +/** @brief Enable the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt * @retval None */ #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) -/** @brief Disable the DAC interrupt - * @param __HANDLE__: specifies the DAC handle - * @param __INTERRUPT__: specifies the DAC interrupt. +/** @brief Disable the DAC interrupt. + * @param __HANDLE__ specifies the DAC handle + * @param __INTERRUPT__ specifies the DAC interrupt. + * This parameter can be any combination of the following values: + * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt * @retval None */ #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) -/** @brief Checks if the specified DAC interrupt source is enabled or disabled. - * @param __HANDLE__: DAC handle - * @param __INTERRUPT__: DAC interrupt source to check +/** @brief Check whether the specified DAC interrupt source is enabled or not. + * @param __HANDLE__ DAC handle + * @param __INTERRUPT__ DAC interrupt source to check * This parameter can be any combination of the following values: - * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt - * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt + * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt * @retval State of interruption (SET or RESET) */ -#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected DAC's flag status. - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag - * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to get. + * This parameter can be any combination of the following values: + * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag + * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag * @retval None */ #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the DAC's flag. - * @param __HANDLE__: specifies the DAC handle. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag - * @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag + * @param __HANDLE__ specifies the DAC handle. + * @param __FLAG__ specifies the DAC flag to clear. + * This parameter can be any combination of the following values: + * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag + * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag * @retval None */ #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) + /** * @} */ -/* Include DAC HAL Extension module */ +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup DAC_Private_Macros DAC Private Macros + * @{ + */ +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ + ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) + +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ + ((CHANNEL) == DAC_CHANNEL_2)) + +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ + ((ALIGN) == DAC_ALIGN_12B_L) || \ + ((ALIGN) == DAC_ALIGN_8B_R)) + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL) + +/** + * @} + */ + +/* Include DAC HAL Extended module */ #include "stm32f7xx_hal_dac_ex.h" /* Exported functions --------------------------------------------------------*/ + /** @addtogroup DAC_Exported_Functions * @{ */ @@ -311,11 +383,12 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @addtogroup DAC_Exported_Functions_Group1 * @{ */ -/* Initialization/de-initialization functions *********************************/ -HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac); -HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); -void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac); -void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); +HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac); +void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); +void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); + /** * @} */ @@ -323,12 +396,27 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); /** @addtogroup DAC_Exported_Functions_Group2 * @{ */ -/* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment); -HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, + uint32_t Alignment); +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); +void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); + +void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); +void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac); +void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); +void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) +/* DAC callback registering/unregistering */ +HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, + pDAC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + /** * @} */ @@ -337,8 +425,8 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); /** * @} */ @@ -346,20 +434,10 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui /** @addtogroup DAC_Exported_Functions_Group4 * @{ */ -/* Peripheral State functions *************************************************/ -HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); -void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); +/* Peripheral State and Error functions ***************************************/ +HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); -void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac); -void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac); -void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); -void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) -/* DAC callback registering/unregistering */ -HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ /** * @} */ @@ -367,66 +445,13 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_D /** * @} */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup DAC_Private_Constants DAC Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DAC_Private_Macros DAC Private Macros - * @{ - */ -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ - ((ALIGN) == DAC_ALIGN_12B_L) || \ - ((ALIGN) == DAC_ALIGN_8B_R)) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ - ((CHANNEL) == DAC_CHANNEL_2)) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ - ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ - ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ - ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) - -/** @brief Set DHR12R1 alignment - * @param __ALIGNMENT__: specifies the DAC alignment - * @retval None - */ -#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__)) - -/** @brief Set DHR12R2 alignment - * @param __ALIGNMENT__: specifies the DAC alignment - * @retval None - */ -#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__)) - -/** @brief Set DHR12RD alignment - * @param __ALIGNMENT__: specifies the DAC alignment - * @retval None - */ -#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ /** @defgroup DAC_Private_Functions DAC Private Functions * @{ */ +void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); +void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); +void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); /** * @} */ @@ -435,14 +460,17 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_D * @} */ +#endif /* DAC */ + /** * @} */ - + #ifdef __cplusplus } #endif -#endif /*__STM32F7xx_HAL_DAC_H */ + +#endif /* STM32F7xx_HAL_DAC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac_ex.c index d61d9eb7eb..2871e78a68 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac_ex.c @@ -3,23 +3,31 @@ * @file stm32f7xx_hal_dac_ex.c * @author MCD Application Team * @brief Extended DAC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of DAC extension peripheral: - * + Extended features functions - * + * This file provides firmware functions to manage the extended + * functionalities of the DAC peripheral. * - @verbatim + * + @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] - (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) : + [..] + + *** Dual mode IO operation *** + ============================== + [..] + (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) : Use HAL_DACEx_DualGetValue() to get digital data to be converted and use - HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. + HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in + Channel 1 and Channel 2. + + *** Signal generation operation *** + =================================== + [..] (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. - - @endverbatim + + @endverbatim ****************************************************************************** * @attention * @@ -32,7 +40,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ @@ -42,31 +50,33 @@ * @{ */ -/** @defgroup DACEx DACEx - * @brief DAC driver modules - * @{ - */ - #ifdef HAL_DAC_MODULE_ENABLED +#if defined(DAC) + +/** @defgroup DACEx DACEx + * @brief DAC Extended HAL module driver + * @{ + */ + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup DACEx_Exported_Functions DAC Exported Functions + +/** @defgroup DACEx_Exported_Functions DACEx Exported Functions * @{ */ -/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * -@verbatim +/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions + * @brief Extended IO operation functions + * +@verbatim ============================================================================== ##### Extended features functions ##### - ============================================================================== + ============================================================================== [..] This section provides functions allowing to: (+) Start conversion. (+) Stop conversion. @@ -74,38 +84,86 @@ (+) Stop conversion and disable DMA transfer. (+) Get result of conversion. (+) Get result of dual mode conversion. - + @endverbatim * @{ */ + /** - * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Enables DAC and starts conversion of both channels. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @retval The selected DAC channel data output value. + * @retval HAL status */ -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) +HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) { - uint32_t tmp = 0; - - tmp |= hdac->Instance->DOR1; - - tmp |= hdac->Instance->DOR2 << 16; - - /* Returns the DAC channel data output register value */ - return tmp; + uint32_t tmp_swtrig = 0UL; + + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the Peripheral */ + __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1); + __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2); + + /* Check if software trigger enabled */ + if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) + { + tmp_swtrig |= DAC_SWTRIGR_SWTRIG1; + } + if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL))) + { + tmp_swtrig |= DAC_SWTRIGR_SWTRIG2; + } + /* Enable the selected DAC software conversion*/ + SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; } /** - * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Disables DAC and stop conversion of both channels. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) +{ + + /* Disable the Peripheral */ + __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); + __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + + + +/** + * @brief Enable or disable the selected DAC channel wave generation. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Amplitude: Select max triangle amplitude. + * @param Amplitude Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 @@ -118,166 +176,166 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 - * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 + * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) -{ +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) +{ /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - - /* Enable the selected wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel); + + /* Enable the triangle wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), + (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdac); - + /* Return function status */ return HAL_OK; } /** - * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @brief Enable or disable the selected DAC channel wave generation. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. - * This parameter can be one of the following values: + * @param Amplitude Unmask DAC channel LFSR for noise wave generation. + * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation - * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) -{ +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) +{ /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); - + /* Process locked */ __HAL_LOCK(hdac); - + /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - - /* Enable the selected wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel); - + + /* Enable the noise wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), + (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); + /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hdac); - + /* Return function status */ return HAL_OK; } + /** * @brief Set the specified data holding register value for dual DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Alignment: Specifies the data alignment for dual channel DAC. + * @param Alignment Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * DAC_ALIGN_8B_R: 8bit right data alignment selected * DAC_ALIGN_12B_L: 12bit left data alignment selected * DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) -{ - uint32_t data = 0, tmp = 0; - +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) +{ + uint32_t data; + uint32_t tmp; + /* Check the parameters */ assert_param(IS_DAC_ALIGN(Alignment)); assert_param(IS_DAC_DATA(Data1)); assert_param(IS_DAC_DATA(Data2)); - + /* Calculate and set dual DAC data holding register value */ if (Alignment == DAC_ALIGN_8B_R) { - data = ((uint32_t)Data2 << 8) | Data1; + data = ((uint32_t)Data2 << 8U) | Data1; } else { - data = ((uint32_t)Data2 << 16) | Data1; + data = ((uint32_t)Data2 << 16U) | Data1; } - + tmp = (uint32_t)hdac->Instance; tmp += DAC_DHR12RD_ALIGNMENT(Alignment); /* Set the dual DAC selected data holding register */ *(__IO uint32_t *)tmp = data; - + /* Return function status */ return HAL_OK; } /** - * @} - */ - -/** - * @brief Conversion complete callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Conversion complete callback in non-blocking mode for Channel2. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ -__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) +__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file */ } /** - * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ -__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) +__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file */ } /** * @brief Error DAC callback for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -285,15 +343,15 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file */ } /** - * @brief DMA underrun DAC callback for channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @brief DMA underrun DAC callback for Channel2. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -301,80 +359,137 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdac); - - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file */ } -/** - * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - hdac->ConvCpltCallbackCh2(hdac); -#else - HAL_DACEx_ConvCpltCallbackCh2(hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - - hdac->State= HAL_DAC_STATE_READY; -} -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - hdac->ConvHalfCpltCallbackCh2(hdac); -#else - HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Set DAC error code to DMA error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - hdac->ErrorCallbackCh2(hdac); -#else - HAL_DACEx_ErrorCallbackCh2(hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - - hdac->State= HAL_DAC_STATE_READY; -} /** * @} */ +/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Set the specified data holding register value for DAC channel. + +@endverbatim + * @{ + */ + + +/** + * @brief Return the last data output value of the selected DAC channel. + * @param hdac pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) +{ + uint32_t tmp = 0UL; + + tmp |= hdac->Instance->DOR1; + + tmp |= hdac->Instance->DOR2 << 16UL; + + /* Returns the DAC channel data output register value */ + return tmp; +} + + +/** + * @} + */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DACEx_Private_Functions DACEx private functions + * @brief Extended private functions + * @{ + */ + + +/** + * @brief DMA conversion complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvCpltCallbackCh2(hdac); +#else + HAL_DACEx_ConvCpltCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Conversion complete callback */ +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ConvHalfCpltCallbackCh2(hdac); +#else + HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + +#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) + hdac->ErrorCallbackCh2(hdac); +#else + HAL_DACEx_ErrorCallbackCh2(hdac); +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ + + hdac->State = HAL_DAC_STATE_READY; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DAC */ + #endif /* HAL_DAC_MODULE_ENABLED */ -/** - * @} - */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac_ex.h index 2e3650d064..1646c8ebd3 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dac_ex.h @@ -1,8 +1,8 @@ /** ****************************************************************************** - * @file stm32f7xx_hal_dac.h + * @file stm32f7xx_hal_dac_ex.h * @author MCD Application Team - * @brief Header file of DAC HAL Extension module. + * @brief Header file of DAC HAL Extended module. ****************************************************************************** * @attention * @@ -18,57 +18,66 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_DAC_EX_H -#define __STM32F7xx_HAL_DAC_EX_H +#ifndef STM32F7xx_HAL_DAC_EX_H +#define STM32F7xx_HAL_DAC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - /** @addtogroup STM32F7xx_HAL_Driver * @{ */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +#if defined(DAC) + /** @addtogroup DACEx * @{ */ /* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL State structures definition + */ + /* Exported constants --------------------------------------------------------*/ -/** @defgroup DACEx_Exported_Constants DAC Exported Constants + +/** @defgroup DACEx_Exported_Constants DACEx Exported Constants * @{ */ - -/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude + +/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude * @{ */ -#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */ -#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ -#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */ -#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ -#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */ -#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ -#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */ -#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ -#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */ -#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ +#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ + /** * @} */ @@ -76,47 +85,25 @@ /** * @} */ + /* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DACEx_Exported_Functions + + +/* Private macro -------------------------------------------------------------*/ + +/** @defgroup DACEx_Private_Macros DACEx Private Macros * @{ */ +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) -/** @addtogroup DACEx_Exported_Functions_Group1 - * @{ - */ -/* Extension features functions ***********************************************/ -uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); -HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); -HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); -HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); - -void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac); -void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac); -void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac); -void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup DACEx_Private_Constants DAC Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DACEx_Private_Macros DAC Private Macros - * @{ - */ #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ @@ -145,16 +132,53 @@ void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); * @} */ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DACEx_Private_Functions DAC Private Functions +/* Exported functions --------------------------------------------------------*/ +/* Extended features functions ***********************************************/ + +/** @addtogroup DACEx_Exported_Functions * @{ */ + +/** @addtogroup DACEx_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ + +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); + +HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac); +HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac); +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac); + +void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac); +void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac); +void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac); +void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac); + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DACEx_Private_Functions + * @{ + */ + +/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */ +/* are called by HAL_DAC_Start_DMA */ void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); -void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); -/** - * @} - */ +void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); /** * @} @@ -163,11 +187,17 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); /** * @} */ - + +#endif /* DAC */ + +/** + * @} + */ + #ifdef __cplusplus } #endif -#endif /*__STM32F7xx_HAL_DAC_EX_H */ +#endif /* STM32F7xx_HAL_DAC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_def.h index 334b42c7d8..3d94fb2c31 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_def.h @@ -107,7 +107,14 @@ typedef enum }while (0U) #endif /* USE_RTOS */ -#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif + #ifndef __packed + #define __packed __attribute__((packed)) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -118,7 +125,14 @@ typedef enum /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ @@ -130,7 +144,7 @@ typedef enum #define __ALIGN_END #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN - #if defined (__CC_ARM) /* ARM Compiler */ + #if defined (__CC_ARM) /* ARM Compiler V5*/ #define __ALIGN_BEGIN __align(4) #elif defined (__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN @@ -150,9 +164,9 @@ typedef enum /** * @brief __RAM_FUNC definition */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' @@ -182,9 +196,9 @@ typedef enum /** * @brief __NOINLINE definition */ -#if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- */ #define __NOINLINE __attribute__ ( (noinline) ) diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dfsdm.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dfsdm.c index dd253e59e5..caf3398055 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dfsdm.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dfsdm.c @@ -3334,7 +3334,7 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) */ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) { - uint32_t channel = 0xFF; + uint32_t channel; /* Get channel from instance */ if(Instance == DFSDM1_Channel0) @@ -3365,7 +3365,7 @@ static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) { channel = 6; } - else if(Instance == DFSDM1_Channel7) + else /* DFSDM1_Channel7 */ { channel = 7; } diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dfsdm.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dfsdm.h index 53cd794c16..677dbad9e1 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dfsdm.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dfsdm.h @@ -301,8 +301,8 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection * @{ */ -#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */ -#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ +#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for output clock is system clock */ +#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for output clock is audio clock */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma.c index 84d080cd0d..9b3abe3e9d 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma.c @@ -604,7 +604,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param CompleteLevel Specifies the DMA level complete. - * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. + * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. * This model could be used for debug purpose. * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). * @param Timeout Timeout duration. @@ -961,7 +961,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) * @brief Register callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifer + * @param CallbackID User Callback identifier * a DMA_HandleTypeDef structure as parameter. * @param pCallback pointer to private callbacsk function which has pointer to * a DMA_HandleTypeDef structure as parameter. @@ -1023,7 +1023,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call * @brief UnRegister callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifer + * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma2d.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma2d.c index c08a4b9a62..e52b29f53c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma2d.c @@ -201,7 +201,8 @@ /** @addtogroup DMA2D_Private_Functions DMA2D Private Functions * @{ */ -static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); +static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height); /** * @} */ @@ -213,8 +214,8 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ */ /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### @@ -237,9 +238,9 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) { /* Check the DMA2D peripheral state */ - if(hdma2d == NULL) + if (hdma2d == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ @@ -258,7 +259,7 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */ hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; - if(hdma2d->MspInitCallback == NULL) + if (hdma2d->MspInitCallback == NULL) { hdma2d->MspInitCallback = HAL_DMA2D_MspInit; } @@ -267,7 +268,7 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) hdma2d->MspInitCallback(hdma2d); } #else - if(hdma2d->State == HAL_DMA2D_STATE_RESET) + if (hdma2d->State == HAL_DMA2D_STATE_RESET) { /* Allocate lock resource and initialize it */ hdma2d->Lock = HAL_UNLOCKED; @@ -289,7 +290,9 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/ - MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos))); + MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS), + ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | \ + (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos))); #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ @@ -314,9 +317,9 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) { /* Check the DMA2D peripheral state */ - if(hdma2d == NULL) + if (hdma2d == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Before aborting any DMA2D transfer or CLUT loading, check @@ -369,13 +372,13 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) - if(hdma2d->MspDeInitCallback == NULL) - { - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; - } + if (hdma2d->MspDeInitCallback == NULL) + { + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; + } - /* DeInit the low level hardware */ - hdma2d->MspDeInitCallback(hdma2d); + /* DeInit the low level hardware */ + hdma2d->MspDeInitCallback(hdma2d); #else /* Carry on with de-initialization of low level hardware */ @@ -400,7 +403,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) * the configuration information for the DMA2D. * @retval None */ -__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) +__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma2d); @@ -416,7 +419,7 @@ __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) * the configuration information for the DMA2D. * @retval None */ -__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) +__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma2d); @@ -443,11 +446,12 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID * @retval status */ -HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, + pDMA2D_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; @@ -456,68 +460,68 @@ HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DM /* Process locked */ __HAL_LOCK(hdma2d); - if(HAL_DMA2D_STATE_READY == hdma2d->State) + if (HAL_DMA2D_STATE_READY == hdma2d->State) { switch (CallbackID) { - case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : - hdma2d->XferCpltCallback = pCallback; - break; + case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : + hdma2d->XferCpltCallback = pCallback; + break; - case HAL_DMA2D_TRANSFERERROR_CB_ID : - hdma2d->XferErrorCallback = pCallback; - break; + case HAL_DMA2D_TRANSFERERROR_CB_ID : + hdma2d->XferErrorCallback = pCallback; + break; - case HAL_DMA2D_LINEEVENT_CB_ID : - hdma2d->LineEventCallback = pCallback; - break; + case HAL_DMA2D_LINEEVENT_CB_ID : + hdma2d->LineEventCallback = pCallback; + break; - case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : - hdma2d->CLUTLoadingCpltCallback = pCallback; - break; + case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : + hdma2d->CLUTLoadingCpltCallback = pCallback; + break; - case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = pCallback; - break; + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = pCallback; + break; - case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = pCallback; - break; + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = pCallback; + break; - default : - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } - else if(HAL_DMA2D_STATE_RESET == hdma2d->State) + else if (HAL_DMA2D_STATE_RESET == hdma2d->State) { switch (CallbackID) { - case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = pCallback; - break; + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = pCallback; + break; - case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = pCallback; - break; + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = pCallback; + break; - default : - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else { /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; } /* Release Lock */ @@ -542,73 +546,73 @@ HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DM */ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID) { -HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma2d); - if(HAL_DMA2D_STATE_READY == hdma2d->State) + if (HAL_DMA2D_STATE_READY == hdma2d->State) { switch (CallbackID) { - case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : - hdma2d->XferCpltCallback = NULL; - break; + case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : + hdma2d->XferCpltCallback = NULL; + break; - case HAL_DMA2D_TRANSFERERROR_CB_ID : - hdma2d->XferErrorCallback = NULL; - break; + case HAL_DMA2D_TRANSFERERROR_CB_ID : + hdma2d->XferErrorCallback = NULL; + break; - case HAL_DMA2D_LINEEVENT_CB_ID : - hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; - break; + case HAL_DMA2D_LINEEVENT_CB_ID : + hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; + break; - case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : - hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; - break; + case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : + hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; + break; - case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ - break; + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; - case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ - break; + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; - default : - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } - else if(HAL_DMA2D_STATE_RESET == hdma2d->State) + else if (HAL_DMA2D_STATE_RESET == hdma2d->State) { switch (CallbackID) { - case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ - break; + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; - case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ - break; + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; - default : - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else { - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; } /* Release Lock */ @@ -623,8 +627,8 @@ HAL_StatusTypeDef status = HAL_OK; /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * + * @brief IO operation functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -666,11 +670,13 @@ HAL_StatusTypeDef status = HAL_OK; * conversion mode is selected, or configure * the color value if Register-to-Memory mode is selected. * @param DstAddress The destination memory Buffer address. - * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Width The width of data to be transferred from source + * to destination (expressed in number of pixels per line). * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height) { /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); @@ -700,11 +706,13 @@ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, u * conversion mode is selected, or configure * the color value if Register-to-Memory mode is selected. * @param DstAddress The destination memory Buffer address. - * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Width The width of data to be transferred from source + * to destination (expressed in number of pixels per line). * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height) { /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); @@ -720,7 +728,7 @@ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); /* Enable the transfer complete, transfer error and configuration error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE); /* Enable the Peripheral */ __HAL_DMA2D_ENABLE(hdma2d); @@ -735,11 +743,13 @@ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata * @param SrcAddress1 The source memory Buffer address for the foreground layer. * @param SrcAddress2 The source memory Buffer address for the background layer. * @param DstAddress The destination memory Buffer address. - * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Width The width of data to be transferred from source + * to destination (expressed in number of pixels per line). * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) +HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, + uint32_t DstAddress, uint32_t Width, uint32_t Height) { /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); @@ -770,11 +780,13 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t * @param SrcAddress1 The source memory Buffer address for the foreground layer. * @param SrcAddress2 The source memory Buffer address for the background layer. * @param DstAddress The destination memory Buffer address. - * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Width The width of data to be transferred from source + * to destination (expressed in number of pixels per line). * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) +HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, + uint32_t DstAddress, uint32_t Width, uint32_t Height) { /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); @@ -793,7 +805,7 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); /* Enable the transfer complete, transfer error and configuration error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE); /* Enable the Peripheral */ __HAL_DMA2D_ENABLE(hdma2d); @@ -815,15 +827,15 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) /* START bit is reset to make sure not to set it again, in the event the HW clears it between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue) */ - MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT); + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT); /* Get tick */ tickstart = HAL_GetTick(); /* Check if the DMA2D is effectively disabled */ - while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) { - if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) + if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; @@ -839,7 +851,7 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) } /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE); /* Change the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; @@ -864,7 +876,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) /* START bit is reset to make sure not to set it again, in the event the HW clears it between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ - MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP); + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP); /* Get tick */ tickstart = HAL_GetTick(); @@ -872,7 +884,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) /* Check if the DMA2D is effectively suspended */ while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START) { - if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) + if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; @@ -884,7 +896,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) } } - /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) { hdma2d->State = HAL_DMA2D_STATE_SUSPEND; @@ -892,7 +904,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) else { /* Make sure SUSP bit is cleared since it is meaningless - when no tranfer is on-going */ + when no transfer is on-going */ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); } @@ -908,7 +920,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) { /* Check the SUSP and START bits */ - if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START)) + if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START)) { /* Ongoing transfer is suspended: change the DMA2D state before resuming */ hdma2d->State = HAL_DMA2D_STATE_BUSY; @@ -918,7 +930,7 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) /* START bit is reset to make sure not to set it again, in the event the HW clears it between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ - CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); + CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START)); return HAL_OK; } @@ -944,7 +956,7 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Enable the background CLUT loading */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -958,7 +970,6 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay return HAL_OK; } - /** * @brief Start DMA2D CLUT Loading. * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains @@ -968,15 +979,14 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) - * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT(). * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); - assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); - assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size)); /* Process locked */ __HAL_LOCK(hdma2d); @@ -985,14 +995,14 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT hdma2d->State = HAL_DMA2D_STATE_BUSY; /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ - WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT); /* Write background CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); /* Enable the CLUT loading for the background */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -1001,13 +1011,13 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT else { /* Write foreground CLUT memory address */ - WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT); /* Write foreground CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); - /* Enable the CLUT loading for the foreground */ + /* Enable the CLUT loading for the foreground */ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); } @@ -1025,6 +1035,127 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if (LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); + + /* Enable the CLUT loading for the background */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + + /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); + + /* Enable the CLUT loading for the foreground */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + +/** + * @brief Start DMA2D CLUT Loading. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @note API obsolete and maintained for compatibility with legacy. User is + * invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from + * code compactness, code size and improved heap usage. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) +{ + /* Check the parameters */ + assert_param(IS_DMA2D_LAYER(LayerIdx)); + assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); + assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); + + /* Process locked */ + __HAL_LOCK(hdma2d); + + /* Change DMA2D peripheral state */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + + /* Configure the CLUT of the background DMA2D layer */ + if (LayerIdx == DMA2D_BACKGROUND_LAYER) + { + /* Write background CLUT memory address */ + WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write background CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + + /* Enable the CLUT loading for the background */ + SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ + WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); + + /* Write foreground CLUT size and CLUT color mode */ + MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + + /* Enable the CLUT loading for the foreground */ + SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); + } + + return HAL_OK; +} + +/** + * @brief Start DMA2D CLUT Loading with interrupt enabled. + * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains + * the configuration information for the DMA2D. + * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains + * the configuration information for the color look up table. + * @param LayerIdx DMA2D Layer index. + * This parameter can be one of the following values: + * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @note API obsolete and maintained for compatibility with legacy. User is + * invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit + * from code compactness, code size and improved heap usage. + * @retval HAL status + */ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) { /* Check the parameters */ @@ -1039,17 +1170,17 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC hdma2d->State = HAL_DMA2D_STATE_BUSY; /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); /* Write background CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); /* Enable the CLUT loading for the background */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -1062,10 +1193,10 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC /* Write foreground CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); /* Enable the CLUT loading for the foreground */ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); @@ -1086,13 +1217,13 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { uint32_t tickstart; - const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ + const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ /* Abort the CLUT loading */ SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT); /* If foreground CLUT loading is considered, update local variables */ - if(LayerIdx == DMA2D_FOREGROUND_LAYER) + if (LayerIdx == DMA2D_FOREGROUND_LAYER) { reg = &(hdma2d->Instance->FGPFCCR); } @@ -1102,9 +1233,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint3 tickstart = HAL_GetTick(); /* Check if the CLUT loading is aborted */ - while((*reg & DMA2D_BGPFCCR_START) != 0U) + while ((*reg & DMA2D_BGPFCCR_START) != 0U) { - if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) + if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; @@ -1120,7 +1251,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint3 } /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); /* Change the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; @@ -1144,13 +1275,13 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin { uint32_t tickstart; uint32_t loadsuspended; - const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ + const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ /* Suspend the CLUT loading */ SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); /* If foreground CLUT loading is considered, update local variables */ - if(LayerIdx == DMA2D_FOREGROUND_LAYER) + if (LayerIdx == DMA2D_FOREGROUND_LAYER) { reg = &(hdma2d->Instance->FGPFCCR); } @@ -1159,11 +1290,13 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin tickstart = HAL_GetTick(); /* Check if the CLUT loading is suspended */ - loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/ - loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */ + /* 1st condition: Suspend Check */ + loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL; + /* 2nd condition: Not Start Check */ + loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL; while (loadsuspended == 0UL) { - if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) + if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; @@ -1173,11 +1306,13 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin return HAL_TIMEOUT; } - loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/ - loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */ + /* 1st condition: Suspend Check */ + loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL; + /* 2nd condition: Not Start Check */ + loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL; } - /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ if ((*reg & DMA2D_BGPFCCR_START) != 0U) { hdma2d->State = HAL_DMA2D_STATE_SUSPEND; @@ -1185,7 +1320,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin else { /* Make sure SUSP bit is cleared since it is meaningless - when no tranfer is on-going */ + when no transfer is on-going */ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); } @@ -1204,18 +1339,18 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { /* Check the SUSP and START bits for background or foreground CLUT loading */ - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Background CLUT loading suspension check */ if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) { - if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) + if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) { - /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; + /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } } } - } else { /* Foreground CLUT loading suspension check */ @@ -1223,11 +1358,11 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint { if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) { - /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; + /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } } } - } /* Resume the CLUT loading */ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); @@ -1251,15 +1386,15 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ __IO uint32_t isrflags = 0x0U; /* Polling for DMA2D transfer */ - if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) { - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); - while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U) + while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U) { isrflags = READ_REG(hdma2d->Instance->ISR); - if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U) + if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U) { if ((isrflags & DMA2D_FLAG_CE) != 0U) { @@ -1281,9 +1416,9 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ return HAL_ERROR; } /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; @@ -1307,10 +1442,10 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ /* Get tick */ tickstart = HAL_GetTick(); - while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U) + while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U) { isrflags = READ_REG(hdma2d->Instance->ISR); - if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U) + if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U) { if ((isrflags & DMA2D_FLAG_CAE) != 0U) { @@ -1328,7 +1463,7 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE); /* Change DMA2D state */ - hdma2d->State= HAL_DMA2D_STATE_ERROR; + hdma2d->State = HAL_DMA2D_STATE_ERROR; /* Process unlocked */ __HAL_UNLOCK(hdma2d); @@ -1336,15 +1471,15 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ return HAL_ERROR; } /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; /* Change the DMA2D state */ - hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; /* Process unlocked */ __HAL_UNLOCK(hdma2d); @@ -1356,7 +1491,7 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ } /* Clear the transfer complete and CLUT loading flags */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC); + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC); /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_READY; @@ -1397,7 +1532,7 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) /* Process Unlocked */ __HAL_UNLOCK(hdma2d); - if(hdma2d->XferErrorCallback != NULL) + if (hdma2d->XferErrorCallback != NULL) { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); @@ -1424,7 +1559,7 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) /* Process Unlocked */ __HAL_UNLOCK(hdma2d); - if(hdma2d->XferErrorCallback != NULL) + if (hdma2d->XferErrorCallback != NULL) { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); @@ -1451,7 +1586,7 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) /* Process Unlocked */ __HAL_UNLOCK(hdma2d); - if(hdma2d->XferErrorCallback != NULL) + if (hdma2d->XferErrorCallback != NULL) { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); @@ -1498,7 +1633,7 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) /* Process Unlocked */ __HAL_UNLOCK(hdma2d); - if(hdma2d->XferCpltCallback != NULL) + if (hdma2d->XferCpltCallback != NULL) { /* Transfer complete Callback */ hdma2d->XferCpltCallback(hdma2d); @@ -1573,8 +1708,8 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) */ /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * + * @brief Peripheral Control functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -1604,15 +1739,16 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { DMA2D_LayerCfgTypeDef *pLayerCfg; - uint32_t regMask, regValue; + uint32_t regMask; + uint32_t regValue; /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset)); - if(hdma2d->Init.Mode != DMA2D_R2M) + if (hdma2d->Init.Mode != DMA2D_R2M) { assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode)); - if(hdma2d->Init.Mode != DMA2D_M2M) + if (hdma2d->Init.Mode != DMA2D_M2M) { assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode)); } @@ -1632,7 +1768,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */ #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\ + regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) | \ (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos); regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS); #else @@ -1647,11 +1783,11 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La } else { - regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos); + regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos); } /* Configure the background DMA2D layer */ - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write DMA2D BGPFCCR register */ MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); @@ -1662,7 +1798,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La /* DMA2D BGCOLR register configuration -------------------------------------*/ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) { - WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED)); + WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \ + DMA2D_BGCOLR_RED)); } } /* Configure the foreground DMA2D layer */ @@ -1670,7 +1807,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La { - /* Write DMA2D FGPFCCR register */ + /* Write DMA2D FGPFCCR register */ MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); /* DMA2D FGOR register configuration -------------------------------------*/ @@ -1679,7 +1816,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La /* DMA2D FGCOLR register configuration -------------------------------------*/ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) { - WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED)); + WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \ + DMA2D_FGCOLR_RED)); } } /* Initialize the DMA2D state*/ @@ -1700,6 +1838,9 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) + * @note API obsolete and maintained for compatibility with legacy. User is invited + * to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness, + * code size and improved heap usage. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) @@ -1716,24 +1857,24 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCf hdma2d->State = HAL_DMA2D_STATE_BUSY; /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); /* Write background CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); - } - /* Configure the CLUT of the foreground DMA2D layer */ - else - { - /* Write foreground CLUT memory address */ + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); /* Write foreground CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); } /* Set the DMA2D state to Ready*/ @@ -1759,8 +1900,6 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCf HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line) { /* Check the parameters */ - assert_param(IS_DMA2D_LINEWATERMARK(Line)); - if (Line > DMA2D_LWR_LW) { return HAL_ERROR; @@ -1867,8 +2006,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### @@ -1927,7 +2066,8 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) * @param Height The height of data to be transferred from source to destination. * @retval HAL status */ -static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height) { uint32_t tmp; uint32_t tmp1; @@ -1936,7 +2076,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ uint32_t tmp4; /* Configure DMA2D data size */ - MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos))); + MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos))); /* Configure DMA2D destination address */ WRITE_REG(hdma2d->Instance->OMAR, DstAddress); @@ -1952,7 +2092,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ /* Prepare the value to be written to the OCOLR register according to the color mode */ if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888) { - tmp = (tmp3 | tmp2 | tmp1| tmp4); + tmp = (tmp3 | tmp2 | tmp1 | tmp4); } else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888) { @@ -1962,7 +2102,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ { tmp2 = (tmp2 >> 19U); tmp3 = (tmp3 >> 10U); - tmp4 = (tmp4 >> 3U ); + tmp4 = (tmp4 >> 3U); tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4); } else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555) @@ -1970,7 +2110,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ tmp1 = (tmp1 >> 31U); tmp2 = (tmp2 >> 19U); tmp3 = (tmp3 >> 11U); - tmp4 = (tmp4 >> 3U ); + tmp4 = (tmp4 >> 3U); tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4); } else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */ @@ -1978,7 +2118,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ tmp1 = (tmp1 >> 28U); tmp2 = (tmp2 >> 20U); tmp3 = (tmp3 >> 12U); - tmp4 = (tmp4 >> 4U ); + tmp4 = (tmp4 >> 4U); tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4); } /* Write to DMA2D OCOLR register */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma2d.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma2d.h index 31d5b1a165..7af0c6c5cc 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dma2d.h @@ -22,11 +22,9 @@ #define STM32F7xx_HAL_DMA2D_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined (DMA2D) - /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -34,6 +32,8 @@ * @{ */ +#if defined (DMA2D) + /** @addtogroup DMA2D DMA2D * @brief DMA2D HAL module driver * @{ @@ -71,9 +71,11 @@ typedef struct This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ uint32_t OutputOffset; /*!< Specifies the Offset value. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x3FFF. */ #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. + uint32_t AlphaInverted; /*!< Select regular or inverted alpha value + for the output pixel format converter. This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) @@ -94,7 +96,8 @@ typedef struct typedef struct { uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x3FFF. */ uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ @@ -102,9 +105,12 @@ typedef struct uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. This parameter can be one value of @ref DMA2D_Alpha_Mode. */ - uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. - @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between + uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value + in case of A8 or A4 color mode. + This parameter must be a number between Min_Data = 0x00 + and Max_Data = 0xFF except for the color modes detailed below. + @note In case of A8 or A4 color mode (ARGB), + this parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where - InputAlpha[24:31] is the alpha value ALPHA[0:7] - InputAlpha[16:23] is the red value RED[0:7] @@ -132,46 +138,46 @@ typedef enum HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ -}HAL_DMA2D_StateTypeDef; +} HAL_DMA2D_StateTypeDef; /** * @brief DMA2D handle Structure definition */ typedef struct __DMA2D_HandleTypeDef { - DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ + DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ - DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ + DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ - void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ + void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ - void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ + void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) - void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */ + void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ - void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */ + void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ - void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */ + void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ - void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */ + void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ - DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ + DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ - HAL_LockTypeDef Lock; /*!< DMA2D lock. */ + HAL_LockTypeDef Lock; /*!< DMA2D lock. */ - __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ + __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ - __IO uint32_t ErrorCode; /*!< DMA2D error code. */ + __IO uint32_t ErrorCode; /*!< DMA2D error code. */ } DMA2D_HandleTypeDef; #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) /** * @brief HAL DMA2D Callback pointer definition */ -typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */ +typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ /** * @} @@ -242,10 +248,10 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode * @{ */ -#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ +#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value - with original alpha channel value */ + with original alpha channel value */ /** * @} */ @@ -312,7 +318,8 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin /** @defgroup DMA2D_Aliases DMA2D API Aliases * @{ */ -#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ /** * @} */ @@ -329,7 +336,7 @@ typedef enum HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ -}HAL_DMA2D_CallbackIDTypeDef; +} HAL_DMA2D_CallbackIDTypeDef; #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ @@ -346,10 +353,10 @@ typedef enum * @retval None */ #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) -#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ +#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ }while(0) #else #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) @@ -455,12 +462,13 @@ typedef enum /* Initialization and de-initialization functions *******************************/ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); -HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); -void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); -void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); +HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, + pDMA2D_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ @@ -474,14 +482,22 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_ */ /* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); -HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); -HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); -HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, + uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, + uint32_t DstAddress, uint32_t Width, uint32_t Height); HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); @@ -601,13 +617,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); /** @defgroup DMA2D_Private_Macros DMA2D Private Macros * @{ */ -#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER)) +#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ + || ((LAYER) == DMA2D_FOREGROUND_LAYER)) #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) -#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ - ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ +#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) @@ -615,11 +634,16 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) -#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ - ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ - ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ - ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ - ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ +#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ + ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ + ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ + ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ + ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ + ((INPUT_CM) == DMA2D_INPUT_L8) || \ + ((INPUT_CM) == DMA2D_INPUT_AL44) || \ + ((INPUT_CM) == DMA2D_INPUT_AL88) || \ + ((INPUT_CM) == DMA2D_INPUT_L4) || \ + ((INPUT_CM) == DMA2D_INPUT_A8) || \ ((INPUT_CM) == DMA2D_INPUT_A4)) #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ @@ -641,15 +665,11 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ - ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ - ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) + ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ + ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ - ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ - ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) -/** - * @} - */ - + ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ + ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) /** * @} */ @@ -660,6 +680,10 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #endif /* defined (DMA2D) */ +/** + * @} + */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dsi.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dsi.c index a01a6defd3..341b48d3f2 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dsi.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dsi.c @@ -13,36 +13,57 @@ ============================================================================== ##### How to use this driver ##### ============================================================================== + [..] + The DSI HAL driver can be used as follows: + + (#) Declare a DSI_HandleTypeDef handle structure, for example: DSI_HandleTypeDef hdsi; + + (#) Initialize the DSI low level resources by implementing the HAL_DSI_MspInit() API: + (##) Enable the DSI interface clock + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the DSI interrupt priority + (+++) Enable the NVIC DSI IRQ Channel + + (#) Initialize the DSI Host peripheral, the required PLL parameters, number of lances and + TX Escape clock divider by calling the HAL_DSI_Init() API which calls HAL_DSI_MspInit(). + + *** Configuration *** + ========================= [..] - (#) Use @ref HAL_DSI_Init() function to initialize the DSI Host IP and program the required - PLL parameters, number of lanes and TX Escape clock divider. - (#) Use @ref HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted + (#) Use HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted command mode. - (#) When operating in video mode , use @ref HAL_DSI_ConfigVideoMode() to configure the DSI host. - (#) Function @ref HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode. - (#) To configure the DSI PHY timings parameters, use function @ref HAL_DSI_ConfigPhyTimer(). - (#) The DSI Host can be started/stopped using respectively functions @ref HAL_DSI_Start() and @ref HAL_DSI_Stop(). - Functions @ref HAL_DSI_ShortWrite(), @ref HAL_DSI_LongWrite() and @ref HAL_DSI_Read() allows respectively + + (#) When operating in video mode , use HAL_DSI_ConfigVideoMode() to configure the DSI host. + + (#) Function HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode. + + (#) To configure the DSI PHY timings parameters, use function HAL_DSI_ConfigPhyTimer(). + + (#) The DSI Host can be started/stopped using respectively functions HAL_DSI_Start() and HAL_DSI_Stop(). + Functions HAL_DSI_ShortWrite(), HAL_DSI_LongWrite() and HAL_DSI_Read() allows respectively to write DSI short packets, long packets and to read DSI packets. (#) The DSI Host Offers two Low power modes : - (+) Low Power Mode on data lanes only: Only DSI data lanes are shut down. - It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPMData() - and @ref HAL_DSI_ExitULPMData() + (++) Low Power Mode on data lanes only: Only DSI data lanes are shut down. + It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPMData() + and HAL_DSI_ExitULPMData() - (+) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes. - It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPM() - and @ref HAL_DSI_ExitULPM() - - (#) User can select the DSI errors to be reported/monitored using function @ref HAL_DSI_ConfigErrorMonitor() - When an error occurs, the callback @ref HAL_DSI_ErrorCallback() is asserted and then user can retrieve - the error code by calling function @ref HAL_DSI_GetError() + (++) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes. + It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPM() + and HAL_DSI_ExitULPM() (#) To control DSI state you can use the following function: HAL_DSI_GetState() - *** DSI HAL driver macros list *** - ============================================= - [..] + *** Error management *** + ======================== + [..] + (#) User can select the DSI errors to be reported/monitored using function HAL_DSI_ConfigErrorMonitor() + When an error occurs, the callback HAL_DSI_ErrorCallback() is asserted and then user can retrieve + the error code by calling function HAL_DSI_GetError() + + *** DSI HAL driver macros list *** + ============================================= + [..] Below the list of most used macros in DSI HAL driver. (+) __HAL_DSI_ENABLE: Enable the DSI Host. @@ -59,58 +80,63 @@ (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts. (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not. + [..] + (@) You can refer to the DSI HAL driver header file for more useful macros + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_DSI_RegisterCallback() to register a callback. - *** Callback registration *** - ============================================= + [..] + Function HAL_DSI_RegisterCallback() allows to register following callbacks: + (+) TearingEffectCallback : DSI Tearing Effect Callback. + (+) EndOfRefreshCallback : DSI End Of Refresh Callback. + (+) ErrorCallback : DSI Error Callback + (+) MspInitCallback : DSI MspInit. + (+) MspDeInitCallback : DSI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. - The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_DSI_RegisterCallback() to register a callback. + [..] + Use function HAL_DSI_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) TearingEffectCallback : DSI Tearing Effect Callback. + (+) EndOfRefreshCallback : DSI End Of Refresh Callback. + (+) ErrorCallback : DSI Error Callback + (+) MspInitCallback : DSI MspInit. + (+) MspDeInitCallback : DSI MspDeInit. - Function @ref HAL_DSI_RegisterCallback() allows to register following callbacks: - (+) TearingEffectCallback : DSI Tearing Effect Callback. - (+) EndOfRefreshCallback : DSI End Of Refresh Callback. - (+) ErrorCallback : DSI Error Callback - (+) MspInitCallback : DSI MspInit. - (+) MspDeInitCallback : DSI MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. + [..] + By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the HAL_DSI_Init() + and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - Use function @ref HAL_DSI_UnRegisterCallback() to reset a callback to the default - weak function. - @ref HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TearingEffectCallback : DSI Tearing Effect Callback. - (+) EndOfRefreshCallback : DSI End Of Refresh Callback. - (+) ErrorCallback : DSI Error Callback - (+) MspInitCallback : DSI MspInit. - (+) MspDeInitCallback : DSI MspDeInit. + [..] + Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_DSI_RegisterCallback() before calling HAL_DSI_DeInit() + or HAL_DSI_Init() function. - By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples @ref HAL_DSI_TearingEffectCallback(), @ref HAL_DSI_EndOfRefreshCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_DSI_Init/ @ref HAL_DSI_DeInit only when - these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_DSI_Init/ @ref HAL_DSI_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_DSI_RegisterCallback() before calling @ref HAL_DSI_DeInit - or HAL_DSI_Init function. - - When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - [..] - (@) You can refer to the DSI HAL driver header file for more useful macros + [..] + When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. @endverbatim ****************************************************************************** @@ -186,10 +212,10 @@ static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, * @param ChannelID Virtual channel ID of the header packet * @param DataType Packet data type of the header packet * This parameter can be any value of : - * @ref DSI_SHORT_WRITE_PKT_Data_Type - * or @ref DSI_LONG_WRITE_PKT_Data_Type - * or @ref DSI_SHORT_READ_PKT_Data_Type - * or DSI_MAX_RETURN_PKT_SIZE + * @arg DSI_SHORT_WRITE_PKT_Data_Type + * @arg DSI_LONG_WRITE_PKT_Data_Type + * @arg DSI_SHORT_READ_PKT_Data_Type + * @arg DSI_MAX_RETURN_PKT_SIZE * @param Data0 Word count LSB * @param Data1 Word count MSB * @retval None @@ -210,9 +236,9 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, * the configuration information for the DSI. * @param ChannelID Virtual channel ID. * @param Mode DSI short packet data type. - * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. + * This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type. * @param Param1 DSC command or first generic parameter. - * This parameter can be any value of @ref DSI_DCS_Command or a + * This parameter can be any value of @arg DSI_DCS_Command or a * generic command code. * @param Param2 DSC parameter or second generic parameter. * @retval HAL status @@ -464,7 +490,7 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @param ActiveErrors indicates which error interrupts will be enabled. - * This parameter can be any combination of @ref DSI_Error_Data_Type. + * This parameter can be any combination of @arg DSI_Error_Data_Type. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors) @@ -581,11 +607,11 @@ __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi) * @param hdsi dsi handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID - * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID - * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID + * @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID + * @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID + * @arg HAL_DSI_ERROR_CB_ID Error Callback ID + * @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval status */ @@ -676,11 +702,11 @@ HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Call * @param hdsi dsi handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID - * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID - * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID + * @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID + * @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID + * @arg HAL_DSI_ERROR_CB_ID Error Callback ID + * @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID + * @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID * @retval status */ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID) @@ -1295,7 +1321,7 @@ HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDe * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @param FlowControl flow control feature(s) to be enabled. - * This parameter can be any combination of @ref DSI_FlowControl. + * This parameter can be any combination of @arg DSI_FlowControl. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl) @@ -1488,7 +1514,7 @@ HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @param ColorMode Color mode (full or 8-colors). - * This parameter can be any value of @ref DSI_Color_Mode + * This parameter can be any value of @arg DSI_Color_Mode * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) @@ -1514,7 +1540,7 @@ HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @param Shutdown Shut-down (Display-ON or Display-OFF). - * This parameter can be any value of @ref DSI_ShutDown + * This parameter can be any value of @arg DSI_ShutDown * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) @@ -1541,9 +1567,9 @@ HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) * the configuration information for the DSI. * @param ChannelID Virtual channel ID. * @param Mode DSI short packet data type. - * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. + * This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type. * @param Param1 DSC command or first generic parameter. - * This parameter can be any value of @ref DSI_DCS_Command or a + * This parameter can be any value of @arg DSI_DCS_Command or a * generic command code. * @param Param2 DSC parameter or second generic parameter. * @retval HAL status @@ -1575,10 +1601,10 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, * the configuration information for the DSI. * @param ChannelID Virtual channel ID. * @param Mode DSI long packet data type. - * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. + * This parameter can be any value of @arg DSI_LONG_WRITE_PKT_Data_Type. * @param NbParams Number of parameters. * @param Param1 DSC command or first generic parameter. - * This parameter can be any value of @ref DSI_DCS_Command or a + * This parameter can be any value of @arg DSI_DCS_Command or a * generic command code * @param ParametersTable Pointer to parameter values table. * @retval HAL status @@ -1665,7 +1691,7 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, * @param Array pointer to a buffer to store the payload of a read back operation. * @param Size Data size to be read (in byte). * @param Mode DSI read packet data type. - * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. + * This parameter can be any value of @arg DSI_SHORT_READ_PKT_Data_Type. * @param DCSCmd DCS get/read command. * @param ParametersTable Pointer to parameter values table. * @retval HAL status @@ -2120,9 +2146,9 @@ HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @param CommDelay Communication delay to be adjusted. - * This parameter can be any value of @ref DSI_Communication_Delay + * This parameter can be any value of @arg DSI_Communication_Delay * @param Lane select between clock or data lanes. - * This parameter can be any value of @ref DSI_Lane_Group + * This parameter can be any value of @arg DSI_Lane_Group * @param Value Custom value of the slew-rate or delay * @retval HAL status */ @@ -2263,10 +2289,10 @@ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) * @brief Custom lane pins configuration * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CustomLane Function to be applyed on selected lane. - * This parameter can be any value of @ref DSI_CustomLane + * @param CustomLane Function to be applied on selected lane. + * This parameter can be any value of @arg DSI_CustomLane * @param Lane select between clock or data lane 0 or data lane 1. - * This parameter can be any value of @ref DSI_Lane_Select + * This parameter can be any value of @arg DSI_Lane_Select * @param State ENABLE or DISABLE * @retval HAL status */ @@ -2352,7 +2378,7 @@ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @param Timing PHY timing to be adjusted. - * This parameter can be any value of @ref DSI_PHY_Timing + * This parameter can be any value of @arg DSI_PHY_Timing * @param State ENABLE or DISABLE * @param Value Custom value of the timing * @retval HAL status @@ -2500,7 +2526,7 @@ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @param Lane select between clock or data lanes. - * This parameter can be any value of @ref DSI_Lane_Group + * This parameter can be any value of @arg DSI_Lane_Group * @param State ENABLE or DISABLE * @retval HAL status */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dsi.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dsi.h index 38cb0e5718..7091e826af 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dsi.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_dsi.h @@ -25,10 +25,11 @@ extern "C" { #endif -#if defined(DSI) /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" +#if defined(DSI) + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ @@ -347,6 +348,9 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ /* Exported constants --------------------------------------------------------*/ +/** @defgroup DSI_Exported_Constants DSI Exported Constants + * @{ + */ /** @defgroup DSI_DCS_Command DSI DCS Command * @{ */ @@ -908,10 +912,18 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @} */ +/** + * @} + */ + /* Exported macros -----------------------------------------------------------*/ +/** @defgroup DSI_Exported_Macros DSI Exported Macros + * @{ + */ + /** * @brief Reset DSI handle state. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None */ #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) @@ -1101,6 +1113,10 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to */ #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @defgroup DSI_Exported_Functions DSI Exported Functions * @{ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_eth.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_eth.c index 407883ec7f..7047ae9f37 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_eth.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_eth.c @@ -543,7 +543,7 @@ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc /* Fill each DMATxDesc descriptor with the right values */ for(i=0; i < TxBuffCount; i++) { - /* Get the pointer on the ith member of the Tx Desc list */ + /* Get the pointer on the member (i) of the Tx Desc list */ dmatxdesc = DMATxDescTab + i; /* Set Second Address Chained bit */ @@ -610,7 +610,7 @@ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADesc /* Fill each DMARxDesc descriptor with the right values */ for(i=0; i < RxBuffCount; i++) { - /* Get the pointer on the ith member of the Rx Desc list */ + /* Get the pointer on the member (i) of the Rx Desc list */ DMARxDesc = DMARxDescTab+i; /* Set Own bit of the Rx descriptor Status */ @@ -934,7 +934,7 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL // MBED: added // Ensure rest of descriptor is written to RAM before the OWN bit __DMB(); - + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ heth->TxDesc->Status |= ETH_DMATXDESC_OWN; /* Point to next descriptor */ @@ -963,11 +963,11 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE; heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); } - - // MBED: added + + // MBED: added // Ensure rest of descriptor is written to RAM before the OWN bit __DMB(); - + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ heth->TxDesc->Status |= ETH_DMATXDESC_OWN; /* point to next descriptor */ @@ -978,7 +978,7 @@ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameL // MBED: added // Ensure all descriptors are written to RAM before checking transmitter status __DMB(); - + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) { @@ -1129,7 +1129,7 @@ HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) /* Set HAL State to Ready */ heth->State = HAL_ETH_STATE_READY; - + /* Return function status */ return HAL_OK; } diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_eth.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_eth.h index fbc7b3547a..303983231b 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_eth.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_eth.h @@ -591,7 +591,7 @@ typedef struct /** - * @brief Received Frame Informations structure definition + * @brief Received Frame Information structure definition */ typedef struct { diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_exti.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_exti.h index e64414ffcf..6411f81797 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_exti.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_exti.h @@ -218,21 +218,21 @@ typedef struct /** @defgroup EXTI_Private_Macros EXTI Private Macros * @{ */ -#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ - ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ - (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ - (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) -#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ - (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) -#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) -#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_FALLING) || \ - ((__LINE__) == EXTI_TRIGGER_RISING) || \ - ((__LINE__) == EXTI_TRIGGER_RISING_FALLING)) +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_FALLING) || \ + ((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \ + ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)) -#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) #if defined (GPIOK) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_flash.c index 9cb569e55d..cc8932e074 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_flash.c @@ -660,8 +660,13 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; FLASH->CR |= FLASH_CR_PG; - /* Program the double-word */ + /* Program first word */ *(__IO uint32_t*)Address = (uint32_t)Data; + /* Barrier to ensure programming is performed in 2 steps, in right order + (independently of compiler optimization behavior) */ + __ISB(); + + /* Program second word */ *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); /* Data synchronous Barrier (DSB) Just after the write operation @@ -673,7 +678,7 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) /** * @brief Program word (32-bit) at a specified address. * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V. + * 2.7V to 3.3V. * * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. @@ -702,7 +707,7 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data) /** * @brief Program a half-word (16-bit) at a specified address. * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V. + * 2.1V to 3.6V. * * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. @@ -732,7 +737,7 @@ static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) /** * @brief Program byte (8-bit) at a specified address. * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V. + * 1.7V to 3.6V. * * @note If an erase and a program operations are requested simultaneously, * the erase operation is performed before the program one. diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_flash_ex.h index 572d7e5006..8b2cf99da2 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_flash_ex.h @@ -502,10 +502,10 @@ typedef struct * @{ */ /** - * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1) + * @brief Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1) * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. * @param __ADDRESS__ FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) - * @retval The FLASH Boot Base Adress + * @retval The FLASH Boot Base Address */ #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14) /** diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_gpio.c index 75e4b5b1b1..c9d4c122e3 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_gpio.c @@ -428,17 +428,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { + uint32_t odr; + /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - if ((GPIOx->ODR & GPIO_Pin) != 0X00u) - { - GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; - } - else - { - GPIOx->BSRR = (uint32_t)GPIO_Pin; - } + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash.c index c752efac8e..521e395b7a 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash.c @@ -34,7 +34,7 @@ (+++) Associate the initialized DMA handle to the HASH DMA handle using __HAL_LINKDMA() (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the DMA Stream: use + interrupt on the DMA stream: use HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() @@ -71,10 +71,11 @@ well the computed digest. (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. - (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro. - From that point, each buffer can be fed to the Peripheral thru HAL_HASH_xxx_Start_DMA() API. + (+++) HASH processing: once initialization is done, MDMAT bit must be set + through __HAL_HASH_SET_MDMAT() macro. + From that point, each buffer can be fed to the Peripheral through HAL_HASH_xxx_Start_DMA() API. Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() - macro then wrap-up the HASH processing in feeding the last input buffer thru the + macro then wrap-up the HASH processing in feeding the last input buffer through the same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to API HAL_HASH_xxx_Finish(). (+++) HMAC processing (requires to resort to extended functions): @@ -119,25 +120,27 @@ and not extra bits. (##) If user needs to perform a hash computation of a large input buffer that is spread around various places - in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it - becomes necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral. + in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it becomes + necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral. It is advised to the user to (+++) achieve the first formatting operation by software then enter the data - (+++) while the Peripheral is processing the first input set, carry out the second formatting operation by software, to be ready when DINIS occurs. + (+++) while the Peripheral is processing the first input set, carry out the second formatting + operation by software, to be ready when DINIS occurs. (+++) repeat step 2 until the whole message is processed. [..] (#) HAL in DMA mode (##) Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis. - The same field described above in HASH_STR is used to specify which bits to discard at the end of the DMA transfer - to process only the message bits and not extra bits. Due to hardware implementation, this is possible only at the - end of the complete message. When several DMA transfers are needed to enter the message, this is not applicable at - the end of the intermediary transfers. + The same field described above in HASH_STR is used to specify which bits to discard at the end of the + DMA transfer to process only the message bits and not extra bits. Due to hardware implementation, + this is possible only at the end of the complete message. When several DMA transfers are needed to + enter the message, this is not applicable at the end of the intermediary transfers. - (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive chunks of data - by software while the DMA transfer and processing is on-going for the first parts of the message. Due to the 32-bit alignment - required for the DMA transfer, it is underlined that the software formatting operation is more complex than in the IT mode. + (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive + chunks of data by software while the DMA transfer and processing is on-going for the first parts of + the message. Due to the 32-bit alignment required for the DMA transfer, it is underlined that the + software formatting operation is more complex than in the IT mode. *** Callback registration *** =================================== @@ -270,7 +273,8 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); static void HASH_DMAError(DMA_HandleTypeDef *hdma); static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); -static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, + uint32_t Timeout); static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash); static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash); @@ -284,8 +288,8 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim */ /** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization, configuration and call-back functions. - * + * @brief Initialization, configuration and call-back functions. + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -324,11 +328,11 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) { /* Check the hash handle allocation */ - if(hhash == NULL) + if (hhash == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_HASH_DATATYPE(hhash->Init.DataType)); @@ -340,9 +344,10 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) /* Reset Callback pointers in HAL_HASH_STATE_RESET only */ hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */ - hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */ + hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation + completion callback */ hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */ - if(hhash->MspInitCallback == NULL) + if (hhash->MspInitCallback == NULL) { hhash->MspInitCallback = HAL_HASH_MspInit; } @@ -351,7 +356,7 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) hhash->MspInitCallback(hhash); } #else - if(hhash->State == HAL_HASH_STATE_RESET) + if (hhash->State == HAL_HASH_STATE_RESET) { /* Allocate lock resource and initialize it */ hhash->Lock = HAL_UNLOCKED; @@ -361,7 +366,7 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) } #endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ - /* Change the HASH state */ + /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; /* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */ @@ -379,7 +384,7 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) /* Set the data type bit */ MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType); /* Reset MDMAT bit */ -__HAL_HASH_RESET_MDMAT(); + __HAL_HASH_RESET_MDMAT(); /* Reset HASH handle status */ hhash->Status = HAL_OK; @@ -401,7 +406,7 @@ __HAL_HASH_RESET_MDMAT(); HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) { /* Check the HASH handle allocation */ - if(hhash == NULL) + if (hhash == NULL) { return HAL_ERROR; } @@ -420,13 +425,13 @@ HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) hhash->DigestCalculationDisable = RESET; #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - if(hhash->MspDeInitCallback == NULL) - { - hhash->MspDeInitCallback = HAL_HASH_MspDeInit; - } + if (hhash->MspDeInitCallback == NULL) + { + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; + } - /* DeInit the low level hardware */ - hhash->MspDeInitCallback(hhash); + /* DeInit the low level hardware */ + hhash->MspDeInitCallback(hhash); #else /* DeInit the low level hardware: CLOCK, NVIC */ HAL_HASH_MspDeInit(hhash); @@ -483,7 +488,7 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) * @brief Input data transfer complete call back. * @note HAL_HASH_InCpltCallback() is called when the complete input message * has been fed to the Peripheral. This API is invoked only when input data are - * entered under interruption or thru DMA. + * entered under interruption or through DMA. * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set), * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding * to the Peripheral. @@ -549,11 +554,12 @@ __weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, + pHASH_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; @@ -562,64 +568,64 @@ HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_ /* Process locked */ __HAL_LOCK(hhash); - if(HAL_HASH_STATE_READY == hhash->State) + if (HAL_HASH_STATE_READY == hhash->State) { switch (CallbackID) { - case HAL_HASH_INPUTCPLT_CB_ID : - hhash->InCpltCallback = pCallback; - break; + case HAL_HASH_INPUTCPLT_CB_ID : + hhash->InCpltCallback = pCallback; + break; - case HAL_HASH_DGSTCPLT_CB_ID : - hhash->DgstCpltCallback = pCallback; - break; + case HAL_HASH_DGSTCPLT_CB_ID : + hhash->DgstCpltCallback = pCallback; + break; - case HAL_HASH_ERROR_CB_ID : - hhash->ErrorCallback = pCallback; - break; + case HAL_HASH_ERROR_CB_ID : + hhash->ErrorCallback = pCallback; + break; - case HAL_HASH_MSPINIT_CB_ID : - hhash->MspInitCallback = pCallback; - break; + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = pCallback; + break; - case HAL_HASH_MSPDEINIT_CB_ID : - hhash->MspDeInitCallback = pCallback; - break; + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = pCallback; + break; - default : - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } - else if(HAL_HASH_STATE_RESET == hhash->State) + else if (HAL_HASH_STATE_RESET == hhash->State) { switch (CallbackID) { - case HAL_HASH_MSPINIT_CB_ID : - hhash->MspInitCallback = pCallback; - break; + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = pCallback; + break; - case HAL_HASH_MSPDEINIT_CB_ID : - hhash->MspDeInitCallback = pCallback; - break; + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = pCallback; + break; - default : - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else { /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; } /* Release Lock */ @@ -642,69 +648,70 @@ HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_ */ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID) { -HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hhash); - if(HAL_HASH_STATE_READY == hhash->State) + if (HAL_HASH_STATE_READY == hhash->State) { switch (CallbackID) { - case HAL_HASH_INPUTCPLT_CB_ID : - hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */ - break; + case HAL_HASH_INPUTCPLT_CB_ID : + hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */ + break; - case HAL_HASH_DGSTCPLT_CB_ID : - hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation completion callback */ - break; + case HAL_HASH_DGSTCPLT_CB_ID : + hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation + completion callback */ + break; - case HAL_HASH_ERROR_CB_ID : - hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */ - break; + case HAL_HASH_ERROR_CB_ID : + hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */ + break; - case HAL_HASH_MSPINIT_CB_ID : - hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ - break; + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; - case HAL_HASH_MSPDEINIT_CB_ID : - hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ - break; + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; - default : - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } - else if(HAL_HASH_STATE_RESET == hhash->State) + else if (HAL_HASH_STATE_RESET == hhash->State) { switch (CallbackID) { - case HAL_HASH_MSPINIT_CB_ID : - hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ - break; + case HAL_HASH_MSPINIT_CB_ID : + hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; - case HAL_HASH_MSPDEINIT_CB_ID : - hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ - break; + case HAL_HASH_MSPDEINIT_CB_ID : + hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; - default : - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else { - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; + /* Update the error code */ + hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; } /* Release Lock */ @@ -718,8 +725,8 @@ HAL_StatusTypeDef status = HAL_OK; */ /** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode - * @brief HASH processing functions using polling mode. - * + * @brief HASH processing functions using polling mode. + * @verbatim =============================================================================== ##### Polling mode HASH processing functions ##### @@ -757,7 +764,8 @@ HAL_StatusTypeDef status = HAL_OK; * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); } @@ -784,7 +792,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff */ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5); + return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } /** @@ -797,7 +805,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); } @@ -813,7 +822,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); } @@ -840,7 +850,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf */ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1); + return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } /** @@ -853,7 +863,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBu * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); } @@ -863,8 +874,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p */ /** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode - * @brief HASH processing functions using interrupt mode. - * + * @brief HASH processing functions using interrupt mode. + * @verbatim =============================================================================== ##### Interruption mode HASH processing functions ##### @@ -900,9 +911,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); } /** @@ -925,7 +937,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB */ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_MD5); + return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } /** @@ -937,9 +949,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_MD5); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); } /** @@ -952,9 +965,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); } @@ -978,7 +992,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA1); + return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } /** @@ -990,9 +1004,10 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA1); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); } /** @@ -1025,8 +1040,8 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) */ /** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode - * @brief HASH processing functions using DMA mode. - * + * @brief HASH processing functions using DMA mode. + * @verbatim =============================================================================== ##### DMA mode HASH processing functions ##### @@ -1077,9 +1092,9 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) { - return HASH_Finish(hhash, pOutBuffer, Timeout); + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** @@ -1108,9 +1123,9 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) { - return HASH_Finish(hhash, pOutBuffer, Timeout); + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** @@ -1118,8 +1133,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB */ /** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode - * @brief HMAC processing functions using polling mode. - * + * @brief HMAC processing functions using polling mode. + * @verbatim =============================================================================== ##### Polling mode HMAC processing functions ##### @@ -1149,7 +1164,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutB * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); } @@ -1167,7 +1183,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); } @@ -1178,8 +1195,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf /** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode - * @brief HMAC processing functions using interrupt mode. - * + * @brief HMAC processing functions using interrupt mode. + * @verbatim =============================================================================== ##### Interrupt mode HMAC processing functions ##### @@ -1208,7 +1225,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); } @@ -1225,7 +1243,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); } @@ -1237,8 +1256,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn /** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode - * @brief HMAC processing functions using DMA modes. - * + * @brief HMAC processing functions using DMA modes. + * @verbatim =============================================================================== ##### DMA mode HMAC processing functions ##### @@ -1313,8 +1332,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI */ /** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim =============================================================================== ##### Peripheral State methods ##### @@ -1381,7 +1400,7 @@ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long. * @retval None */ -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) +void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; @@ -1391,20 +1410,21 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) UNUSED(hhash); /* Save IMR register content */ - *(uint32_t*)(mem_ptr) = READ_BIT(HASH->IMR,HASH_IT_DINI|HASH_IT_DCI); - mem_ptr+=4U; + *(uint32_t *)(mem_ptr) = READ_BIT(HASH->IMR, HASH_IT_DINI | HASH_IT_DCI); + mem_ptr += 4U; /* Save STR register content */ - *(uint32_t*)(mem_ptr) = READ_BIT(HASH->STR,HASH_STR_NBLW); - mem_ptr+=4U; + *(uint32_t *)(mem_ptr) = READ_BIT(HASH->STR, HASH_STR_NBLW); + mem_ptr += 4U; /* Save CR register content */ - *(uint32_t*)(mem_ptr) = READ_BIT(HASH->CR,HASH_CR_DMAE|HASH_CR_DATATYPE|HASH_CR_MODE|HASH_CR_ALGO|HASH_CR_LKEY|HASH_CR_MDMAT); - mem_ptr+=4U; + *(uint32_t *)(mem_ptr) = READ_BIT(HASH->CR, HASH_CR_DMAE | HASH_CR_DATATYPE | HASH_CR_MODE | HASH_CR_ALGO | + HASH_CR_LKEY | HASH_CR_MDMAT); + mem_ptr += 4U; /* By default, save all CSRs registers */ - for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--) + for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--) { - *(uint32_t*)(mem_ptr) = *(uint32_t*)(csr_ptr); - mem_ptr+=4U; - csr_ptr+=4U; + *(uint32_t *)(mem_ptr) = *(uint32_t *)(csr_ptr); + mem_ptr += 4U; + csr_ptr += 4U; } } @@ -1421,7 +1441,7 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) * beforehand). * @retval None */ -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) +void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; @@ -1431,25 +1451,25 @@ void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer) UNUSED(hhash); /* Restore IMR register content */ - WRITE_REG(HASH->IMR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4U; + WRITE_REG(HASH->IMR, (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; /* Restore STR register content */ - WRITE_REG(HASH->STR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4U; + WRITE_REG(HASH->STR, (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; /* Restore CR register content */ - WRITE_REG(HASH->CR, (*(uint32_t*)(mem_ptr))); - mem_ptr+=4U; + WRITE_REG(HASH->CR, (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; /* Reset the HASH processor before restoring the Context Swap Registers (CSR) */ __HAL_HASH_INIT(); /* By default, restore all CSR registers */ - for (i = HASH_NUMBER_OF_CSR_REGISTERS; i >0U; i--) + for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--) { - WRITE_REG((*(uint32_t*)(csr_ptr)), (*(uint32_t*)(mem_ptr))); - mem_ptr+=4U; - csr_ptr+=4U; + WRITE_REG((*(uint32_t *)(csr_ptr)), (*(uint32_t *)(mem_ptr))); + mem_ptr += 4U; + csr_ptr += 4U; } } @@ -1492,7 +1512,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) else { - /* Make sure there is enough time to suspend the processing */ + /* Make sure there is enough time to suspend the processing */ tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR; if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT) @@ -1505,7 +1525,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) /* Wait for BUSY flag to be reset */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_TIMEOUT; } if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET) @@ -1516,7 +1536,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) /* Wait for BUSY flag to be set */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK) { - return HAL_TIMEOUT; + return HAL_TIMEOUT; } /* Disable DMA channel */ /* Note that the Abort function will @@ -1524,13 +1544,13 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) - Unlock - Set the State */ - if (HAL_DMA_Abort(hhash->hdmain) !=HAL_OK) + if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK) { return HAL_ERROR; } /* Clear DMAE bit */ - CLEAR_BIT(HASH->CR,HASH_CR_DMAE); + CLEAR_BIT(HASH->CR, HASH_CR_DMAE); /* Wait for BUSY flag to be reset */ if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) @@ -1564,19 +1584,22 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) { /* Compute how many words were supposed to be transferred by DMA */ - tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount%4U)!=0U) ? ((hhash->HashInCount+3U)/4U): (hhash->HashInCount/4U)); + tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount % 4U) != 0U) ? \ + ((hhash->HashInCount + 3U) / 4U) : (hhash->HashInCount / 4U)); - /* If discrepancy between the number of words reported by DMA Peripheral and the numbers of words entered as reported - by HASH Peripheral, correct it */ + /* If discrepancy between the number of words reported by DMA Peripheral and + the numbers of words entered as reported by HASH Peripheral, correct it */ /* tmp_words_already_pushed reflects the number of words that were already pushed before the start of DMA transfer (multi-buffer processing case) */ tmp_words_already_pushed = hhash->NbWordsAlreadyPushed; - if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) %16U) != HASH_NBW_PUSHED()) + if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - \ + tmp_remaining_DMATransferSize_inWords) % 16U) != HASH_NBW_PUSHED()) { tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */ } - /* Accordingly, update the input pointer that points at the next word to be transferred to the Peripheral by DMA */ + /* Accordingly, update the input pointer that points at the next word to be + transferred to the Peripheral by DMA */ hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ; /* And store in HashInCount the remaining size to transfer (in bytes) */ @@ -1596,7 +1619,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) * @brief Return the HASH handle error code. * @param hhash pointer to a HASH_HandleTypeDef structure. * @retval HASH Error Code -*/ + */ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) { /* Return HASH Error Code */ @@ -1624,10 +1647,10 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) { - HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; uint32_t inputaddr; uint32_t buffersize; - HAL_StatusTypeDef status ; + HAL_StatusTypeDef status = HAL_OK; if (hhash->State != HAL_HASH_STATE_SUSPENDED) { @@ -1726,19 +1749,23 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) } } - /* Configure the Number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(buffersize); + /* Configure the Number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(buffersize); - /* Set the HASH DMA transfert completion call back */ + /* Set the HASH DMA transfer completion call back */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; - /* Enable the DMA In DMA Stream */ - status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U))); + /* Enable the DMA In DMA stream */ + status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \ + (((buffersize % 4U) != 0U) ? ((buffersize + (4U - (buffersize % 4U))) / 4U) : \ + (buffersize / 4U))); - /* Enable DMA requests */ - SET_BIT(HASH->CR, HASH_CR_DMAE); - /* Return function status */ + + /* Enable DMA requests */ + SET_BIT(HASH->CR, HASH_CR_DMAE); + + /* Return function status */ if (status != HAL_OK) { /* Update HASH state machine to error */ @@ -1747,9 +1774,9 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) else { /* Change HASH state */ - hhash->State = HAL_HASH_STATE_READY; + hhash->State = HAL_HASH_STATE_BUSY; } - } + } } return; @@ -1764,14 +1791,14 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) */ static void HASH_DMAError(DMA_HandleTypeDef *hdma) { - HASH_HandleTypeDef* hhash = ( HASH_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hhash->State != HAL_HASH_STATE_SUSPENDED) { hhash->ErrorCode |= HAL_HASH_ERROR_DMA; /* Set HASH state to ready to prevent any blocking issue in user code present in HAL_HASH_ErrorCallback() */ - hhash->State= HAL_HASH_STATE_READY; + hhash->State = HAL_HASH_STATE_READY; /* Set HASH handle status to error */ hhash->Status = HAL_ERROR; #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) @@ -1801,15 +1828,15 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; - for(buffercounter = 0U; buffercounter < Size; buffercounter+=4U) + for (buffercounter = 0U; buffercounter < Size; buffercounter += 4U) { /* Write input data 4 bytes at a time */ - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4U; + HASH->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4U) < Size)) + if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter + 4U) < Size)) { /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free in the input buffer */ @@ -1823,14 +1850,14 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)) { /* Save current reading and writing locations of Input and Output buffers */ - hhash->pHashInBuffPtr = (uint8_t *)inputaddr; + hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ hhash->HashInCount = Size - (buffercounter + 4U); } else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) { /* Save current reading and writing locations of Input and Output buffers */ - hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr; + hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr; /* Save the number of bytes that remain to be processed at this point */ hhash->HashKeyCount = Size - (buffercounter + 4U); } @@ -1864,63 +1891,63 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) { uint32_t msgdigest = (uint32_t)pMsgDigest; - switch(Size) + switch (Size) { /* Read the message digest */ case 16: /* MD5 */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - break; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]); + break; case 20: /* SHA1 */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - break; - case 28: /* SHA224 */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]); - break; - case 32: /* SHA256 */ - *(uint32_t*)(msgdigest) = __REV(HASH->HR[0]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[1]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[2]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[3]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH->HR[4]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[6]); - msgdigest+=4U; - *(uint32_t*)(msgdigest) = __REV(HASH_DIGEST->HR[7]); - break; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]); + break; + case 28: /* SHA224 */ + *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]); + break; + case 32: /* SHA256 */ + *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]); + msgdigest += 4U; + *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]); + break; default: - break; + break; } } @@ -1934,19 +1961,20 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) * @param Timeout Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, + uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); /* Wait until flag is set */ - if(Status == RESET) + if (Status == RESET) { - while(__HAL_HASH_GET_FLAG(Flag) == RESET) + while (__HAL_HASH_GET_FLAG(Flag) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Set State to Ready to be able to restart later on */ hhash->State = HAL_HASH_STATE_READY; @@ -1963,12 +1991,12 @@ static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, } else { - while(__HAL_HASH_GET_FLAG(Flag) != RESET) + while (__HAL_HASH_GET_FLAG(Flag) != RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Set State to Ready to be able to restart later on */ hhash->State = HAL_HASH_STATE_READY; @@ -2001,10 +2029,10 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) if (hhash->State == HAL_HASH_STATE_BUSY) { /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */ - if(hhash->HashITCounter == 0U) + if (hhash->HashITCounter == 0U) { /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); /* HASH state set back to Ready to prevent any issue in user code present in HAL_HASH_ErrorCallback() */ hhash->State = HAL_HASH_STATE_READY; @@ -2012,9 +2040,9 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) } else if (hhash->HashITCounter == 1U) { - /* This is the first call to HASH_IT, the first input data are about to be - entered in the Peripheral. A specific processing is carried out at this point to - start-up the processing. */ + /* This is the first call to HASH_IT, the first input data are about to be + entered in the Peripheral. A specific processing is carried out at this point to + start-up the processing. */ hhash->HashITCounter = 2U; } else @@ -2031,7 +2059,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH()); /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; /* Reset HASH state machine */ @@ -2052,10 +2080,10 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) /* If the suspension flag has been raised and if the processing is not about to end, suspend processing */ - if ( (hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND)) + if ((hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND)) { /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); /* Reset SuspendRequest */ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; @@ -2066,7 +2094,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) return HAL_OK; } - /* Enter input data in the Peripheral thru HASH_Write_Block_Data() call and + /* Enter input data in the Peripheral through HASH_Write_Block_Data() call and check whether the digest calculation has been triggered */ if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) { @@ -2084,7 +2112,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); return HAL_TIMEOUT; } /* Initialization start for HMAC STEP 2 */ @@ -2092,7 +2120,8 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); /* Set NBLW for the input message */ hhash->HashInCount = hhash->HashBuffSize; /* Set the input data size (in bytes) */ hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr; /* Set the input data address */ - hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */ + hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start + of a new phase */ __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */ } else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) @@ -2101,7 +2130,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) { /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); return HAL_TIMEOUT; } /* Initialization start for HMAC STEP 3 */ @@ -2109,7 +2138,8 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */ hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */ hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */ - hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start of a new phase */ + hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start + of a new phase */ __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */ } else @@ -2143,28 +2173,28 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED; /* If there are more than 64 bytes remaining to be entered */ - if(hhash->HashInCount > 64U) + if (hhash->HashInCount > 64U) { inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* Write the Input block in the Data IN register (16 32-bit words, or 64 bytes are entered) */ - for(buffercounter = 0U; buffercounter < 64U; buffercounter+=4U) + for (buffercounter = 0U; buffercounter < 64U; buffercounter += 4U) { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4U; + HASH->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; } /* If this is the start of input data entering, an additional word must be entered to start up the HASH processing */ - if(hhash->HashITCounter == 2U) + if (hhash->HashITCounter == 2U) { - HASH->DIN = *(uint32_t*)inputaddr; - if(hhash->HashInCount >= 68U) + HASH->DIN = *(uint32_t *)inputaddr; + if (hhash->HashInCount >= 68U) { /* There are still data waiting to be entered in the Peripheral. Decrement buffer counter and set pointer to the proper memory location for the next data entering round. */ hhash->HashInCount -= 68U; - hhash->pHashInBuffPtr+= 68U; + hhash->pHashInBuffPtr += 68U; } else { @@ -2178,7 +2208,7 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) Decrement buffer counter and set pointer to the proper memory location for the next data entering round.*/ hhash->HashInCount -= 64U; - hhash->pHashInBuffPtr+= 64U; + hhash->pHashInBuffPtr += 64U; } } else @@ -2194,10 +2224,10 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) __HAL_HASH_DISABLE_IT(HASH_IT_DINI); /* Write the Input block in the Data IN register */ - for(buffercounter = 0U; buffercounter < ((inputcounter+3U)/4U); buffercounter++) + for (buffercounter = 0U; buffercounter < ((inputcounter + 3U) / 4U); buffercounter++) { - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4U; + HASH->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; } if (hhash->Accumulation == 1U) @@ -2211,9 +2241,9 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) hhash->State = HAL_HASH_STATE_READY; /* Call Input data transfer complete call back */ #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - hhash->InCpltCallback(hhash); + hhash->InCpltCallback(hhash); #else - HAL_HASH_InCpltCallback(hhash); + HAL_HASH_InCpltCallback(hhash); #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ } else @@ -2243,7 +2273,8 @@ static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout) { /* Ensure first that Phase is correct */ - if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3)) + if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) + && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3)) { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_READY; @@ -2340,11 +2371,11 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim } - /* HMAC Step 3 processing. - After phase check, HMAC_Processing() may - - directly start up from this point in resumption case - if the same Step 3 processing was suspended previously - - or fall through from the Step 2 processing carried out hereabove */ + /* HMAC Step 3 processing. + After phase check, HMAC_Processing() may + - directly start up from this point in resumption case + if the same Step 3 processing was suspended previously + - or fall through from the Step 2 processing carried out hereabove */ if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3) { /************************** STEP 3 ******************************************/ @@ -2372,7 +2403,7 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim __HAL_HASH_START_DIGEST(); /* Wait for DCIS flag to be set */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) + if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -2384,14 +2415,14 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim hhash->Phase = HAL_HASH_PHASE_READY; } - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_READY; - /* Process Unlock */ - __HAL_UNLOCK(hhash); + /* Process Unlock */ + __HAL_UNLOCK(hhash); - /* Return function status */ - return HAL_OK; + /* Return function status */ + return HAL_OK; } @@ -2407,7 +2438,8 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout, uint32_t Algorithm) { uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ @@ -2415,7 +2447,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* Initiate HASH processing in case of start or resumption */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ if ((pInBuffer == NULL) || (pOutBuffer == NULL)) @@ -2428,13 +2460,13 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED __HAL_LOCK(hhash); /* Check if initialization phase has not been already performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) + if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); /* Configure the number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(Size); @@ -2556,7 +2588,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, } /* Initiate HASH processing in case of start or resumption */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ if ((pInBuffer == NULL) || (Size == 0U)) @@ -2565,7 +2597,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED return HAL_ERROR; } - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hhash); /* If resuming the HASH processing */ @@ -2592,10 +2624,10 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Check if initialization phase has already be performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) + if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); } /* Set the phase */ @@ -2659,7 +2691,7 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff } /* Initiate HASH processing in case of start or resumption */ - if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ if ((pInBuffer == NULL) || (Size == 0U)) @@ -2668,7 +2700,7 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff return HAL_ERROR; } - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hhash); /* If resuming the HASH processing */ @@ -2683,15 +2715,15 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff hhash->State = HAL_HASH_STATE_BUSY; /* Check if initialization phase has already be performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) + if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); hhash->HashITCounter = 1; } else { - hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */ + hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */ } /* Set the phase */ @@ -2701,13 +2733,13 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set. Therefore, first words are manually entered until DINIS raises, or until there is not more data to enter. */ - while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U)) + while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U)) { /* Write input data 4 bytes at a time */ - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4U; - SizeVar-=4U; + HASH->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + SizeVar -= 4U; } /* If DINIS is still not set or if all the data have been fed, stop here */ @@ -2728,10 +2760,10 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff to be fed to the Peripheral */ hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at the next interruption */ - /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain - the information describing where the HASH process is stopped. - These variables are used later on to resume the HASH processing at the - correct location. */ + /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain + the information describing where the HASH process is stopped. + These variables are used later on to resume the HASH processing at the + correct location. */ } @@ -2768,16 +2800,17 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Algorithm) { - HAL_HASH_StateTypeDef State_tmp = hhash->State; + HAL_HASH_StateTypeDef State_tmp = hhash->State; __IO uint32_t inputaddr = (uint32_t) pInBuffer; uint32_t polling_step = 0U; uint32_t initialization_skipped = 0U; uint32_t SizeVar = Size; /* If State is ready or suspended, start or resume IT-based HASH processing */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL)) @@ -2796,23 +2829,23 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED hhash->HashITCounter = 1; /* Check if initialization phase has already be performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) + if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(SizeVar); + __HAL_HASH_SET_NBVALIDBITS(SizeVar); hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data to be fed to the Peripheral */ hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the Peripheral at the next interruption */ - /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain - the information describing where the HASH process is stopped. - These variables are used later on to resume the HASH processing at the - correct location. */ + /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain + the information describing where the HASH process is stopped. + These variables are used later on to resume the HASH processing at the + correct location. */ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ } @@ -2824,17 +2857,17 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /* Set the phase */ hhash->Phase = HAL_HASH_PHASE_PROCESS; - /* If DINIS is equal to 0 (for example if an incomplete block has been previously - fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set. - Therefore, first words are manually entered until DINIS raises. */ - while((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U)) + /* If DINIS is equal to 0 (for example if an incomplete block has been previously + fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set. + Therefore, first words are manually entered until DINIS raises. */ + while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U)) { polling_step = 1U; /* note that some words are entered before enabling the interrupt */ /* Write input data 4 bytes at a time */ - HASH->DIN = *(uint32_t*)inputaddr; - inputaddr+=4U; - SizeVar-=4U; + HASH->DIN = *(uint32_t *)inputaddr; + inputaddr += 4U; + SizeVar -= 4U; } if (polling_step == 1U) @@ -2846,7 +2879,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ /* Start the Digest calculation */ - __HAL_HASH_START_DIGEST(); + __HAL_HASH_START_DIGEST(); /* Process Unlock */ __HAL_UNLOCK(hhash); @@ -2863,7 +2896,8 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED Update HashInCount and pHashInBuffPtr accordingly. */ hhash->HashInCount = SizeVar; hhash->pHashInBuffPtr = (uint8_t *)inputaddr; - __HAL_HASH_SET_NBVALIDBITS(SizeVar); /* Update the configuration of the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS( + SizeVar); /* Update the configuration of the number of valid bits in last word of the message */ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ if (initialization_skipped == 1U) { @@ -2875,11 +2909,11 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /* DINIS is not set but it remains a few data to enter (not enough for a full word). Manually enter the last bytes before enabling DCIE. */ __HAL_HASH_SET_NBVALIDBITS(SizeVar); - HASH->DIN = *(uint32_t*)inputaddr; + HASH->DIN = *(uint32_t *)inputaddr; - /* Start the Digest calculation */ + /* Start the Digest calculation */ hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ - __HAL_HASH_START_DIGEST(); + __HAL_HASH_START_DIGEST(); /* Process Unlock */ __HAL_UNLOCK(hhash); @@ -2896,7 +2930,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED __HAL_UNLOCK(hhash); /* Enable Interrupts */ - __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI); /* Return function status */ return HAL_OK; @@ -2931,20 +2965,20 @@ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, HAL_StatusTypeDef status ; HAL_HASH_StateTypeDef State_tmp = hhash->State; - + /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set (case of multi-buffer HASH processing) */ assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size)); - - /* If State is ready or suspended, start or resume polling-based HASH processing */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + + /* If State is ready or suspended, start or resume polling-based HASH processing */ + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ( (pInBuffer == NULL ) || (Size == 0U) || - /* Check phase coherency. Phase must be - either READY (fresh start) - or PROCESS (multi-buffer HASH management) */ - ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash))))) + if ((pInBuffer == NULL) || (Size == 0U) || + /* Check phase coherency. Phase must be + either READY (fresh start) + or PROCESS (multi-buffer HASH management) */ + ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash))))) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -2964,10 +2998,10 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the API is processing a new input data message in case of multi-buffer HASH computation. */ - if(hhash->Phase == HAL_HASH_PHASE_READY) + if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); /* Set the phase */ hhash->Phase = HAL_HASH_PHASE_PROCESS; @@ -2998,7 +3032,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED } - /* Set the HASH DMA transfert complete callback */ + /* Set the HASH DMA transfer complete callback */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; /* Set the DMA error callback */ hhash->hdmain->XferErrorCallback = HASH_DMAError; @@ -3006,8 +3040,10 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /* Store number of words already pushed to manage proper DMA processing suspension */ hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); - /* Enable the DMA In DMA Stream */ - status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U))); + /* Enable the DMA In DMA stream */ + status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \ + (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) : \ + (inputSize / 4U))); /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); @@ -3038,10 +3074,10 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) { - if(hhash->State == HAL_HASH_STATE_READY) + if (hhash->State == HAL_HASH_STATE_READY) { /* Check parameter */ if (pOutBuffer == NULL) @@ -3099,15 +3135,17 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, ui * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm) +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout, uint32_t Algorithm) { - HAL_HASH_StateTypeDef State_tmp = hhash->State; + HAL_HASH_StateTypeDef State_tmp = hhash->State; - /* If State is ready or suspended, start or resume polling-based HASH processing */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + /* If State is ready or suspended, start or resume polling-based HASH processing */ + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL)) + if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) + || (pOutBuffer == NULL)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -3120,28 +3158,34 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED hhash->State = HAL_HASH_STATE_BUSY; /* Check if initialization phase has already be performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) + if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ - if(hhash->Init.KeySize > 64U) + if (hhash->Init.KeySize > 64U) { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, + Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); } else { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, + Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); } /* Set the phase to Step 1 */ hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; /* Resort to hhash internal fields to feed the Peripheral. Parameters will be updated in case of suspension to contain the proper information at resumption time. */ - hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */ - hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input parameter for Step 2 */ - hhash->HashInCount = Size; /* Input data size, HMAC_Processing input parameter for Step 2 */ - hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process */ - hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step 1 and Step 3 */ - hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 and Step 3 */ + hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */ + hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input + parameter for Step 2 */ + hhash->HashInCount = Size; /* Input data size, HMAC_Processing input + parameter for Step 2 */ + hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process*/ + hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step + 1 and Step 3 */ + hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 + and Step 3 */ } /* Carry out HMAC processing */ @@ -3169,15 +3213,17 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm) +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Algorithm) { - HAL_HASH_StateTypeDef State_tmp = hhash->State; + HAL_HASH_StateTypeDef State_tmp = hhash->State; /* If State is ready or suspended, start or resume IT-based HASH processing */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || (pOutBuffer == NULL)) + if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) + || (pOutBuffer == NULL)) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -3196,13 +3242,15 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED if (hhash->Phase == HAL_HASH_PHASE_READY) { /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ - if(hhash->Init.KeySize > 64U) + if (hhash->Init.KeySize > 64U) { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, + Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); } else { - MODIFY_REG(HASH->CR, HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); + MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, + Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); } /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount @@ -3247,7 +3295,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED __HAL_UNLOCK(hhash); /* Enable Interrupts */ - __HAL_HASH_ENABLE_IT(HASH_IT_DINI|HASH_IT_DCI); + __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI); /* Return function status */ return HAL_OK; @@ -3282,18 +3330,18 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t inputSize; HAL_StatusTypeDef status ; HAL_HASH_StateTypeDef State_tmp = hhash->State; - /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation - is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */ - assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size)); + /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation + is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */ + assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size)); /* If State is ready or suspended, start or resume DMA-based HASH processing */ -if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) + if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { /* Check input parameters */ - if ((pInBuffer == NULL ) || (Size == 0U) || (hhash->Init.pKey == NULL ) || (hhash->Init.KeySize == 0U) || - /* Check phase coherency. Phase must be - either READY (fresh start) - or one of HMAC PROCESS steps (multi-buffer HASH management) */ - ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash))))) + if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || + /* Check phase coherency. Phase must be + either READY (fresh start) + or one of HMAC PROCESS steps (multi-buffer HASH management) */ + ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash))))) { hhash->State = HAL_HASH_STATE_READY; return HAL_ERROR; @@ -3306,63 +3354,65 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /* If not a case of resumption after suspension */ if (hhash->State == HAL_HASH_STATE_READY) { - /* Check whether or not initialization phase has already be performed */ - if(hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits. - At the same time, ensure MDMAT bit is cleared. */ - if(hhash->Init.KeySize > 64U) + /* Check whether or not initialization phase has already be performed */ + if (hhash->Phase == HAL_HASH_PHASE_READY) { - MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; + /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits. + At the same time, ensure MDMAT bit is cleared. */ + if (hhash->Init.KeySize > 64U) + { + MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, + Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); + } + else + { + MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, + Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); + } + /* Store input aparameters in handle fields to manage steps transition + or possible HMAC suspension/resumption */ + hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */ + hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */ + hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */ + hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */ + hhash->HashBuffSize = Size; /* input data size (in bytes) */ + + /* Set DMA input parameters */ + inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */ + inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */ + + /* Configure the number of valid bits in last word of the key */ + __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); + + /* Set the phase to Step 1 */ + hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; + } - else - { - MODIFY_REG(HASH->CR, HASH_CR_MDMAT|HASH_CR_LKEY|HASH_CR_ALGO|HASH_CR_MODE|HASH_CR_INIT, Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); - } - /* Store input aparameters in handle fields to manage steps transition - or possible HMAC suspension/resumption */ - hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */ - hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */ - hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */ - hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */ - hhash->HashBuffSize = Size; /* input data size (in bytes) */ - - /* Set DMA input parameters */ - inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */ - inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */ - - /* Configure the number of valid bits in last word of the key */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Set the phase to Step 1 */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; - - } else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) - { - /* Process a new input data message in case of multi-buffer HMAC processing - (this is not a resumption case) */ + { + /* Process a new input data message in case of multi-buffer HMAC processing + (this is not a resumption case) */ - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; + /* Change the HASH state */ + hhash->State = HAL_HASH_STATE_BUSY; - /* Save input parameters to be able to manage possible suspension/resumption */ + /* Save input parameters to be able to manage possible suspension/resumption */ hhash->HashInCount = Size; /* Input message address */ hhash->pHashInBuffPtr = pInBuffer; /* Input message size in bytes */ - /* Set DMA input parameters */ + /* Set DMA input parameters */ inputaddr = (uint32_t)pInBuffer; /* Input message address */ inputSize = Size; /* Input message size in bytes */ - if (hhash->DigestCalculationDisable == RESET) - { - /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */ - __HAL_HASH_RESET_MDMAT(); - __HAL_HASH_SET_NBVALIDBITS(inputSize); + if (hhash->DigestCalculationDisable == RESET) + { + /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */ + __HAL_HASH_RESET_MDMAT(); + __HAL_HASH_SET_NBVALIDBITS(inputSize); + } } - } else { /* Phase not aligned with handle READY state */ @@ -3373,7 +3423,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED } else { - /* Resumption case (phase may be Step 1, 2 or 3) */ + /* Resumption case (phase may be Step 1, 2 or 3) */ /* Change the HASH state */ hhash->State = HAL_HASH_STATE_BUSY; @@ -3387,7 +3437,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED } - /* Set the HASH DMA transfert complete callback */ + /* Set the HASH DMA transfer complete callback */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; /* Set the DMA error callback */ hhash->hdmain->XferErrorCallback = HASH_DMAError; @@ -3395,8 +3445,10 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /* Store number of words already pushed to manage proper DMA processing suspension */ hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); - /* Enable the DMA In DMA Stream */ - status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U))); + /* Enable the DMA In DMA stream */ + status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \ + (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \ + : (inputSize / 4U))); /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash.h index 93177b716e..a9ccf3f736 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash.h @@ -22,7 +22,7 @@ #define STM32F7xx_HAL_HASH_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -51,7 +51,7 @@ typedef struct uint32_t KeySize; /*!< The key size is used only in HMAC operation. */ - uint8_t* pKey; /*!< The key is used only in HMAC operation. */ + uint8_t *pKey; /*!< The key is used only in HMAC operation. */ } HASH_InitTypeDef; @@ -66,7 +66,7 @@ typedef enum HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */ HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */ HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */ -}HAL_HASH_StateTypeDef; +} HAL_HASH_StateTypeDef; /** * @brief HAL phase structures definition @@ -81,7 +81,7 @@ typedef enum (step 2 consists in entering the message text) */ HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase (step 3 consists in entering the outer hash function key) */ -}HAL_HASH_PhaseTypeDef; +} HAL_HASH_PhaseTypeDef; /** * @brief HAL HASH mode suspend definitions @@ -90,7 +90,7 @@ typedef enum { HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */ HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */ -}HAL_HASH_SuspendTypeDef; +} HAL_HASH_SuspendTypeDef; #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) /** @@ -103,7 +103,7 @@ typedef enum HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */ HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */ HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */ -}HAL_HASH_CallbackIDTypeDef; +} HAL_HASH_CallbackIDTypeDef; #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ @@ -155,15 +155,15 @@ typedef struct __IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */ #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - void (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH input completion callback */ + void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */ - void (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH digest computation completion callback */ + void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation completion callback */ - void (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH error callback */ + void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */ - void (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp Init callback */ + void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */ - void (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */ + void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */ #endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ } HASH_HandleTypeDef; @@ -172,7 +172,7 @@ typedef struct /** * @brief HAL HASH Callback pointer definition */ -typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */ +typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */ #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ /** @@ -250,7 +250,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer /** @defgroup HASH_alias HASH API alias * @{ */ -#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ /** * @} */ @@ -288,8 +288,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \ - ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\ - ((HASH->SR & (__FLAG__)) == (__FLAG__)) ) + ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\ + ((HASH->SR & (__FLAG__)) == (__FLAG__)) ) /** @brief Clear the specified HASH flag. @@ -366,7 +366,7 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @brief Set the number of valid bits in the last word written in data register DIN. * @param __SIZE__ size in bytes of last data written in Data register. * @retval None -*/ + */ #define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U)) /** @@ -389,8 +389,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @retval Digest length */ #define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \ - ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \ - ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) ) + ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \ + ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) ) /** * @brief Return number of words already pushed in the FIFO. * @retval Number of words already pushed in the FIFO @@ -424,7 +424,8 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer * @param __SIZE__ input data buffer size. * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) */ -#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U)) +#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET)\ + || (((__SIZE__) % 4U) == 0U)) /** * @brief Ensure that handle phase is set to HASH processing. * @param __HANDLE__ HASH handle. @@ -467,7 +468,8 @@ void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash); void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, + pHASH_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ @@ -482,12 +484,16 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS /* HASH processing using polling *********************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout); HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -499,12 +505,16 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p */ /* HASH processing using IT **************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** * @} @@ -516,9 +526,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /* HASH processing using DMA *************************************************/ HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -529,8 +539,10 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBu */ /* HASH-MAC processing using polling *****************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout); +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout); /** * @} @@ -540,8 +552,10 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @{ */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); /** * @} @@ -567,8 +581,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /* Peripheral State methods **************************************************/ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash); -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer); -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer); +void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); +void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); @@ -588,14 +602,18 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); */ /* Private functions */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout, uint32_t Algorithm); HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Algorithm); HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Timeout, uint32_t Algorithm); +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, + uint32_t Algorithm); HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); /** diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash_ex.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash_ex.c index fd61814c72..78f1f4e554 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash_ex.c @@ -5,7 +5,7 @@ * @brief Extended HASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the HASH peripheral for SHA-224 and SHA-256 - * alogrithms: + * algorithms: * + HASH or HMAC processing in polling mode * + HASH or HMAC processing in interrupt mode * + HASH or HMAC processing in DMA mode @@ -39,17 +39,18 @@ User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as well the computed digest. - (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer, + (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer, except for the last one. User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as well the computed digest. (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. - (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro. - From that point, each buffer can be fed to the Peripheral thru HAL_HASHEx_xxx_Start_DMA() API. + (+++) HASH processing: once initialization is done, MDMAT bit must be set through + __HAL_HASH_SET_MDMAT() macro. + From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API. Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() - macro then wrap-up the HASH processing in feeding the last input buffer thru the + macro then wrap-up the HASH processing in feeding the last input buffer through the same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to API HAL_HASHEx_xxx_Finish(). @@ -107,8 +108,8 @@ */ /** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode - * @brief HASH extended processing functions using polling mode. - * + * @brief HASH extended processing functions using polling mode. + * @verbatim =============================================================================== ##### Polling mode HASH extended processing functions ##### @@ -147,7 +148,8 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); } @@ -174,7 +176,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224); + return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } /** @@ -187,7 +189,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); } @@ -203,7 +206,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); } @@ -230,7 +234,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256); + return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } /** @@ -243,7 +247,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); } @@ -253,8 +258,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ */ /** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode - * @brief HASH extended processing functions using interrupt mode. - * + * @brief HASH extended processing functions using interrupt mode. + * @verbatim =============================================================================== ##### Interruption mode HASH extended processing functions ##### @@ -285,9 +290,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); } /** @@ -310,7 +316,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA224); + return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } /** @@ -322,9 +328,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA224); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); } /** @@ -337,9 +344,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); } /** @@ -362,7 +370,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t */ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) { - return HASH_Accumulate_IT(hhash, pInBuffer, Size,HASH_ALGOSELECTION_SHA256); + return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } /** @@ -374,9 +382,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer,HASH_ALGOSELECTION_SHA256); + return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); } /** @@ -384,11 +393,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin */ /** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode - * @brief HASH extended processing functions using DMA mode. - * + * @brief HASH extended processing functions using DMA mode. + * @verbatim =============================================================================== - ##### DMA mode HASH extended processing functionss ##### + ##### DMA mode HASH extended processing functions ##### =============================================================================== [..] This section provides functions allowing to calculate in DMA mode the hash value using one of the following algorithms: @@ -440,9 +449,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) { - return HASH_Finish(hhash, pOutBuffer, Timeout); + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** @@ -470,9 +479,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) { - return HASH_Finish(hhash, pOutBuffer, Timeout); + return HASH_Finish(hhash, pOutBuffer, Timeout); } /** @@ -480,8 +489,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p */ /** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode - * @brief HMAC extended processing functions using polling mode. - * + * @brief HMAC extended processing functions using polling mode. + * @verbatim =============================================================================== ##### Polling mode HMAC extended processing functions ##### @@ -512,7 +521,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); } @@ -530,7 +540,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); } @@ -541,8 +552,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI /** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode - * @brief HMAC extended processing functions using interruption mode. - * + * @brief HMAC extended processing functions using interruption mode. + * @verbatim =============================================================================== ##### Interrupt mode HMAC extended processing functions ##### @@ -572,7 +583,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); } @@ -589,7 +601,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); } @@ -603,8 +616,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t /** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode - * @brief HMAC extended processing functions using DMA mode. - * + * @brief HMAC extended processing functions using DMA mode. + * @verbatim =============================================================================== ##### DMA mode HMAC extended processing functions ##### @@ -681,8 +694,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t */ /** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode - * @brief HMAC extended processing functions in multi-buffer DMA mode. - * + * @brief HMAC extended processing functions in multi-buffer DMA mode. + * @verbatim =============================================================================== ##### Multi-buffer DMA mode HMAC extended processing functions ##### diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash_ex.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash_ex.h index 60717df1bb..6ac0715dd5 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hash_ex.h @@ -22,7 +22,7 @@ #define STM32F7xx_HAL_HASH_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -51,12 +51,16 @@ * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -66,12 +70,16 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); /** * @} @@ -81,9 +89,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @{ */ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -92,8 +100,10 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* p /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); /** * @} */ @@ -102,8 +112,10 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, + uint8_t *pOutBuffer); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hcd.c index 735d7d188b..7dd58166bc 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hcd.c @@ -91,8 +91,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); */ /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -185,9 +185,9 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) * This parameter can be a value from 0 to 255 * @param speed Current device speed. * This parameter can be one of these values: - * HCD_SPEED_HIGH: High speed mode, - * HCD_SPEED_FULL: Full speed mode, - * HCD_SPEED_LOW: Low speed mode + * HCD_DEVICE_SPEED_HIGH: High speed mode, + * HCD_DEVICE_SPEED_FULL: Full speed mode, + * HCD_DEVICE_SPEED_LOW: Low speed mode * @param ep_type Endpoint Type. * This parameter can be one of these values: * EP_TYPE_CTRL: Control type, @@ -566,6 +566,16 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); } + /* Handle Rx Queue Level Interrupts */ + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) + { + USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + HCD_RXQLVL_IRQHandler(hhcd); + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + /* Handle Host channel Interrupt */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) { @@ -586,19 +596,21 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) } __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); } - - /* Handle Rx Queue Level Interrupts */ - if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) - { - USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - HCD_RXQLVL_IRQHandler(hhcd); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } } } + +/** + * @brief Handles HCD Wakeup interrupt request. + * @param hhcd HCD handle + * @retval HAL status + */ +void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd) +{ + UNUSED(hhcd); +} + + /** * @brief SOF callback. * @param hhcd HCD handle @@ -718,7 +730,9 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -806,7 +820,7 @@ HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_Call /** * @brief Unregister an USB HCD Callback - * USB HCD callabck is redirected to the weak predefined callback + * USB HCD callback is redirected to the weak predefined callback * @param hhcd USB HCD handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -910,7 +924,8 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_Ca * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -945,7 +960,7 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * } /** - * @brief UnRegister the USB HCD Host Channel Notify URB Change Callback + * @brief Unregister the USB HCD Host Channel Notify URB Change Callback * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback * @param hhcd HCD handle * @retval HAL status @@ -982,8 +997,8 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef */ /** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions - * @brief Management functions - * + * @brief Management functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -1041,8 +1056,8 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) */ /** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -1192,10 +1207,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); hhcd->hc[ch_num].state = HC_DATATGLERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); } else { @@ -1212,7 +1234,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { if (hhcd->Init.dma_enable != 0U) { - hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \ + hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \ (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); } @@ -1253,8 +1275,18 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { /* ... */ } - hhcd->hc[ch_num].toggle_in ^= 1U; + if (hhcd->Init.dma_enable == 1U) + { + if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U) + { + hhcd->hc[ch_num].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[ch_num].toggle_in ^= 1U; + } } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { @@ -1262,17 +1294,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->hc[ch_num].state == HC_XFRC) { - hhcd->hc[ch_num].urb_state = URB_DONE; + hhcd->hc[ch_num].urb_state = URB_DONE; } else if (hhcd->hc[ch_num].state == HC_STALL) { - hhcd->hc[ch_num].urb_state = URB_STALL; + hhcd->hc[ch_num].urb_state = URB_STALL; } else if ((hhcd->hc[ch_num].state == HC_XACTERR) || (hhcd->hc[ch_num].state == HC_DATATGLERR)) { hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 3U) + if (hhcd->hc[ch_num].ErrCnt > 2U) { hhcd->hc[ch_num].ErrCnt = 0U; hhcd->hc[ch_num].urb_state = URB_ERROR; @@ -1280,18 +1312,19 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else { hhcd->hc[ch_num].urb_state = URB_NOTREADY; - } - /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + /* re-activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } } else if (hhcd->hc[ch_num].state == HC_NAK) { hhcd->hc[ch_num].urb_state = URB_NOTREADY; - /* re-activate the channel */ + + /* re-activate the channel */ tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; @@ -1309,14 +1342,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - hhcd->hc[ch_num].ErrCnt++; - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); - } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) { if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) @@ -1362,6 +1387,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) uint32_t USBx_BASE = (uint32_t)USBx; uint32_t ch_num = (uint32_t)chnum; uint32_t tmpreg; + uint32_t num_packets; if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { @@ -1380,15 +1406,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) - { - hhcd->hc[ch_num].state = HC_NYET; - hhcd->hc[ch_num].do_ping = 1U; - hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); - } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); @@ -1398,11 +1415,27 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) { hhcd->hc[ch_num].ErrCnt = 0U; + + /* transaction completed with NYET state, update do ping state */ + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + { + hhcd->hc[ch_num].do_ping = 1U; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + } __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); hhcd->hc[ch_num].state = HC_XFRC; } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + { + hhcd->hc[ch_num].state = HC_NYET; + hhcd->hc[ch_num].do_ping = 1U; + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); @@ -1417,7 +1450,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->hc[ch_num].do_ping == 0U) { - if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH) + if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH) { hhcd->hc[ch_num].do_ping = 1U; } @@ -1429,9 +1462,26 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - hhcd->hc[ch_num].state = HC_XACTERR; + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[ch_num].state = HC_XACTERR; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else + { + hhcd->hc[ch_num].ErrCnt++; + if (hhcd->hc[ch_num].ErrCnt > 2U) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + } + else + { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + } __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) @@ -1452,7 +1502,22 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)) { - hhcd->hc[ch_num].toggle_out ^= 1U; + if (hhcd->Init.dma_enable == 1U) + { + if (hhcd->hc[ch_num].xfer_len > 0U) + { + num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet; + + if ((num_packets & 1U) != 0U) + { + hhcd->hc[ch_num].toggle_out ^= 1U; + } + } + } + else + { + hhcd->hc[ch_num].toggle_out ^= 1U; + } } } else if (hhcd->hc[ch_num].state == HC_NAK) @@ -1471,7 +1536,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) (hhcd->hc[ch_num].state == HC_DATATGLERR)) { hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 3U) + if (hhcd->hc[ch_num].ErrCnt > 2U) { hhcd->hc[ch_num].ErrCnt = 0U; hhcd->hc[ch_num].urb_state = URB_ERROR; @@ -1479,13 +1544,13 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else { hhcd->hc[ch_num].urb_state = URB_NOTREADY; - } - /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + /* re-activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } } else { @@ -1512,14 +1577,15 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) uint32_t USBx_BASE = (uint32_t)USBx; uint32_t pktsts; uint32_t pktcnt; - uint32_t temp; + uint32_t GrxstspReg; + uint32_t xferSizePktCnt; uint32_t tmpreg; uint32_t ch_num; - temp = hhcd->Instance->GRXSTSP; - ch_num = temp & USB_OTG_GRXSTSP_EPNUM; - pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; - pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + GrxstspReg = hhcd->Instance->GRXSTSP; + ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; + pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17; + pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4; switch (pktsts) { @@ -1527,20 +1593,31 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) /* Read the data into the host buffer. */ if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0)) { - (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); - - /*manage multiple Xfer */ - hhcd->hc[ch_num].xfer_buff += pktcnt; - hhcd->hc[ch_num].xfer_count += pktcnt; - - if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U) + if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len) { - /* re-activate the channel when more packets are expected */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; - hhcd->hc[ch_num].toggle_in ^= 1U; + (void)USB_ReadPacket(hhcd->Instance, + hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); + + /* manage multiple Xfer */ + hhcd->hc[ch_num].xfer_buff += pktcnt; + hhcd->hc[ch_num].xfer_count += pktcnt; + + /* get transfer size packet count */ + xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; + + if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U)) + { + /* re-activate the channel when more packets are expected */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + hhcd->hc[ch_num].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[ch_num].urb_state = URB_ERROR; } } break; diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hcd.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hcd.h index 28c578efc8..68d915adbe 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hcd.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_hcd.h @@ -33,7 +33,7 @@ extern "C" { * @{ */ -/** @addtogroup HCD +/** @addtogroup HCD HCD * @{ */ @@ -112,6 +112,10 @@ typedef struct #define HCD_SPEED_FULL USBH_FSLS_SPEED #define HCD_SPEED_LOW USBH_FSLS_SPEED +#define HCD_DEVICE_SPEED_HIGH 0U +#define HCD_DEVICE_SPEED_FULL 1U +#define HCD_DEVICE_SPEED_LOW 2U + /** * @} */ @@ -143,9 +147,9 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ /** @defgroup HCD_Exported_Macros HCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ #define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) @@ -214,10 +218,16 @@ typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, * @} */ -HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ /** @@ -235,6 +245,7 @@ HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_n /* Non-Blocking mode: Interrupt */ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); +void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd); void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); @@ -267,6 +278,7 @@ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chn uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); + /** * @} */ @@ -277,36 +289,17 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /* Private macros ------------------------------------------------------------*/ /** @defgroup HCD_Private_Macros HCD Private Macros - * @{ - */ - + * @{ + */ /** * @} */ - /* Private functions prototypes ----------------------------------------------*/ -/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes - * @{ - */ -/** + /** * @} */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup HCD_Private_Functions HCD Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** + /** * @} */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c.c index 4b3cee4d7e..64e9ba97a6 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c.c @@ -93,7 +93,7 @@ [..] (+) A specific option field manage the different steps of a sequential transfer (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address @@ -112,7 +112,7 @@ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). - Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit without stopping the communication and so generate a restart condition. (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential interface. @@ -122,7 +122,7 @@ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. - (+) Differents sequential I2C interfaces are listed below: + (+) Different sequential I2C interfaces are listed below: (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() or using @ref HAL_I2C_Master_Seq_Transmit_DMA() (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can @@ -351,13 +351,13 @@ /* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (0x00000001U) -#define I2C_XFER_RX_IT (0x00000002U) -#define I2C_XFER_LISTEN_IT (0x00000004U) +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref I2C_XFER_TX_IT and @ref I2C_XFER_RX_IT */ -#define I2C_XFER_ERROR_IT (0x00000011U) -#define I2C_XFER_CPLT_IT (0x00000012U) -#define I2C_XFER_RELOAD_IT (0x00000012U) +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define I2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -390,8 +390,10 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); /* Private functions for I2C transfer IRQ handler */ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); @@ -400,7 +402,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); @@ -410,11 +413,15 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + /* Private function to flush TXDR register */ static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); /* Private function to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); /* Private function to Convert Specific options */ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); @@ -429,8 +436,8 @@ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); */ /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -669,7 +676,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -974,8 +982,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -1057,7 +1065,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1171,7 +1180,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1547,7 +1557,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; @@ -1783,7 +1794,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; @@ -1926,7 +1938,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; @@ -2277,7 +2290,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2369,8 +2383,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - } - while (hi2c->XferCount > 0U); + } while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ @@ -2412,7 +2425,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2504,8 +2518,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - } - while (hi2c->XferCount > 0U); + } while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ @@ -2545,7 +2558,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2636,7 +2650,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2726,7 +2741,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2870,7 +2886,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param Size Amount of data to be read * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -3121,8 +3138,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Increment Trials */ I2C_Trials++; - } - while (I2C_Trials < Trials); + } while (I2C_Trials < Trials); /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; @@ -3153,7 +3169,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; @@ -3200,7 +3217,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3237,7 +3254,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; @@ -3285,7 +3303,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3399,7 +3417,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; @@ -3446,7 +3465,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3483,7 +3502,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; @@ -3531,7 +3551,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 I2C_ConvertOtherXferOptions(hi2c); /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount < MAX_NBYTE_SIZE) + if (hi2c->XferCount <= MAX_NBYTE_SIZE) { xfermode = hi2c->XferOptions; } @@ -3643,7 +3663,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3738,7 +3759,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { HAL_StatusTypeDef dmaxferstatus; @@ -3917,7 +3939,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -4012,7 +4035,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { HAL_StatusTypeDef dmaxferstatus; @@ -4251,9 +4275,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA /* Process Locked */ __HAL_LOCK(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Set State at HAL_I2C_STATE_ABORT */ hi2c->State = HAL_I2C_STATE_ABORT; @@ -4285,8 +4321,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA */ /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /** * @brief This function handles I2C event interrupt request. @@ -4524,8 +4560,8 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @brief Peripheral State, Mode and Error functions - * + * @brief Peripheral State, Mode and Error functions + * @verbatim =============================================================================== ##### Peripheral State, Mode and Error functions ##### @@ -4562,11 +4598,11 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) } /** -* @brief Return the I2C error code. + * @brief Return the I2C error code. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. -* @retval I2C Error Code -*/ + * @retval I2C Error Code + */ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) { return hi2c->ErrorCode; @@ -4752,7 +4788,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); @@ -4812,7 +4849,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint I2C_ITSlaveSeqCplt(hi2c); } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, tmpITFlags); } @@ -4820,7 +4858,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Datas have already been sent */ + /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) { @@ -5001,6 +5039,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin { uint32_t tmpoptions = hi2c->XferOptions; uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; /* Process locked */ __HAL_LOCK(hi2c); @@ -5047,7 +5086,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin if (treatdmanack == 1U) { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); @@ -5079,8 +5119,24 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ I2C_ITError(hi2c, hi2c->ErrorCode); } @@ -5119,7 +5175,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); @@ -5172,7 +5229,8 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); @@ -5369,9 +5427,27 @@ static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) */ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) { + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + /* Reset I2C handle mode */ hi2c->Mode = HAL_I2C_MODE_NONE; + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) { /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ @@ -5426,19 +5502,36 @@ static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + /* Clear Configuration Register 2 */ I2C_RESET_CR2(hi2c); /* Reset handle parameters */ - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; hi2c->XferOptions = I2C_NO_OPTION_FRAME; - if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) { /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); @@ -5447,12 +5540,17 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + /* Flush TX register */ I2C_Flush_TXDR(hi2c); - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); - /* Store current volatile hi2c->ErrorCode, misra rule */ tmperror = hi2c->ErrorCode; @@ -5466,6 +5564,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5500,6 +5599,7 @@ static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; if (hi2c->Mode == HAL_I2C_MODE_MEM) { @@ -5546,12 +5646,26 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) { uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); uint32_t tmpITFlags = ITFlags; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; /* Clear STOP Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } /* Disable Address Acknowledge */ hi2c->Instance->CR2 |= I2C_CR2_NACK; @@ -5565,6 +5679,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* If a DMA is ongoing, Update handle size context */ if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if (hi2c->hdmatx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmatx); @@ -5572,6 +5689,9 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if (hi2c->hdmarx != NULL) { hi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hi2c->hdmarx); @@ -5608,7 +5728,6 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->XferISR = NULL; @@ -5626,11 +5745,12 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { - /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */ + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ I2C_ITSlaveSeqCplt(hi2c); hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5646,6 +5766,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5660,6 +5781,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) else { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5733,6 +5855,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { HAL_I2C_StateTypeDef tmpstate = hi2c->State; + uint32_t tmppreviousstate; /* Reset handle parameters */ hi2c->Mode = HAL_I2C_MODE_NONE; @@ -5752,7 +5875,6 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* keep HAL_I2C_STATE_LISTEN if set */ hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = I2C_Slave_ISR_IT; } else @@ -5760,23 +5882,27 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - /* If state is an abort treatment on goind, don't change state */ + /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) { /* Set HAL_I2C_STATE_READY */ hi2c->State = HAL_I2C_STATE_READY; } - hi2c->PreviousState = I2C_STATE_NONE; hi2c->XferISR = NULL; } /* Abort DMA TX transfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + tmppreviousstate = hi2c->PreviousState; + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } - if (hi2c->hdmatx != NULL) + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5792,13 +5918,21 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } /* Abort DMA RX transfer if any */ - else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } - if (hi2c->hdmarx != NULL) + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) { /* Set the I2C DMA Abort callback : will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ @@ -5814,10 +5948,28 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); } } + else + { + I2C_TreatErrorCallback(hi2c); + } } - else if (hi2c->State == HAL_I2C_STATE_ABORT) + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -5831,6 +5983,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } else { + hi2c->PreviousState = I2C_STATE_NONE; + /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -6062,30 +6216,16 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ /* Reset AbortCpltCallback */ - hi2c->hdmatx->XferAbortCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Check if come from abort from user */ - if (hi2c->State == HAL_I2C_STATE_ABORT) + if (hi2c->hdmatx != NULL) { - hi2c->State = HAL_I2C_STATE_READY; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AbortCpltCallback(hi2c); -#else - HAL_I2C_AbortCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmatx->XferAbortCallback = NULL; } - else + if (hi2c->hdmarx != NULL) { - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ErrorCallback(hi2c); -#else - HAL_I2C_ErrorCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + hi2c->hdmarx->XferAbortCallback = NULL; } + + I2C_TreatErrorCallback(hi2c); } /** @@ -6098,7 +6238,8 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { @@ -6330,7 +6471,8 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) { /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); @@ -6338,8 +6480,11 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin assert_param(IS_TRANSFER_REQUEST(Request)); /* update CR2 register */ - MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + MODIFY_REG(hi2c->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** @@ -6362,19 +6507,19 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -6400,7 +6545,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; @@ -6454,19 +6599,19 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; } - if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) + if (InterruptRequest == I2C_XFER_ERROR_IT) { /* Enable ERR and NACK interrupts */ tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; } - if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) + if (InterruptRequest == I2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ tmpisr |= I2C_IT_STOPI; } - if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) + if (InterruptRequest == I2C_XFER_RELOAD_IT) { /* Enable TC interrupts */ tmpisr |= I2C_IT_TCI; @@ -6479,7 +6624,7 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) } /** - * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. * @param hi2c I2C handle. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c.h index 1722843408..c2aa9f6e16 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c.h @@ -495,7 +495,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified I2C flag is set or not. * @param __HANDLE__ specifies the I2C Handle. @@ -521,7 +522,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @retval The new state of __FLAG__ (SET or RESET). */ #define I2C_FLAG_MASK (0x0001FFFFU) -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the I2C Handle. @@ -541,7 +543,7 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @retval None */ #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) + : ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. @@ -583,7 +585,8 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); @@ -598,49 +601,70 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); */ /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); /******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); /** * @} */ /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); @@ -732,7 +756,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) #define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) #define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) @@ -743,13 +768,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) #define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) -#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c_ex.c index 1a14aa6603..05c5775371 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c_ex.c @@ -69,7 +69,7 @@ /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions * @brief Extended features functions - * + * @verbatim =============================================================================== ##### Extended features functions ##### diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c_ex.h index f45be67b70..580e67f936 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2c_ex.h @@ -38,7 +38,6 @@ extern "C" { /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ - /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants * @{ */ @@ -99,24 +98,51 @@ extern "C" { */ /* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions * @{ */ -/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions +/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions * @{ */ - /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions + * @{ + */ +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions + * @{ + */ #if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP) void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #endif +/** + * @} + */ + + +/** + * @} + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants @@ -132,7 +158,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @{ */ #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) @@ -167,9 +193,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1)) #endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */ - - - /** * @} */ @@ -191,14 +214,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @} */ -/** - * @} - */ - -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2s.c index aa955fc4b2..a116d92d8c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2s.c @@ -88,6 +88,10 @@ (+) Pause the DMA Transfer using HAL_I2S_DMAPause() (+) Resume the DMA Transfer using HAL_I2S_DMAResume() (+) Stop the DMA Transfer using HAL_I2S_DMAStop() + In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error + HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data. + In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data + inside DR register and avoid using DeInit/Init process for the next transfer. *** I2S HAL driver macros list *** =================================== @@ -99,6 +103,7 @@ (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not + (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data [..] (@) You can refer to the I2S HAL driver header file for more useful macros @@ -113,13 +118,13 @@ Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback. Function HAL_I2S_RegisterCallback() allows to register following callbacks: - (+) TxCpltCallback : I2S Tx Completed callback - (+) RxCpltCallback : I2S Rx Completed callback - (+) TxHalfCpltCallback : I2S Tx Half Completed callback - (+) RxHalfCpltCallback : I2S Rx Half Completed callback - (+) ErrorCallback : I2S Error callback - (+) MspInitCallback : I2S Msp Init callback - (+) MspDeInitCallback : I2S Msp DeInit callback + (++) TxCpltCallback : I2S Tx Completed callback + (++) RxCpltCallback : I2S Rx Completed callback + (++) TxHalfCpltCallback : I2S Tx Half Completed callback + (++) RxHalfCpltCallback : I2S Rx Half Completed callback + (++) ErrorCallback : I2S Error callback + (++) MspInitCallback : I2S Msp Init callback + (++) MspDeInitCallback : I2S Msp DeInit callback This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. @@ -129,14 +134,15 @@ HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: - (+) TxCpltCallback : I2S Tx Completed callback - (+) RxCpltCallback : I2S Rx Completed callback - (+) TxHalfCpltCallback : I2S Tx Half Completed callback - (+) RxHalfCpltCallback : I2S Rx Half Completed callback - (+) ErrorCallback : I2S Error callback - (+) MspInitCallback : I2S Msp Init callback - (+) MspDeInitCallback : I2S Msp DeInit callback + (++) TxCpltCallback : I2S Tx Completed callback + (++) RxCpltCallback : I2S Rx Completed callback + (++) TxHalfCpltCallback : I2S Tx Half Completed callback + (++) RxHalfCpltCallback : I2S Rx Half Completed callback + (++) ErrorCallback : I2S Error callback + (++) MspInitCallback : I2S Msp Init callback + (++) MspDeInitCallback : I2S Msp DeInit callback + [..] By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET all callbacks are set to the corresponding weak functions: examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback(). @@ -146,6 +152,7 @@ If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state, @@ -154,7 +161,8 @@ using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit() or HAL_I2S_Init() function. - When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or + [..] + When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. @@ -189,6 +197,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -328,7 +337,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) /* I2S standard */ if (hi2s->Init.Standard <= I2S_STANDARD_LSB) { - /* In I2S standard packet lenght is multiplied by 2 */ + /* In I2S standard packet length is multiplied by 2 */ packetlength = packetlength * 2U; } @@ -412,7 +421,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) /* Write to SPIx I2SCFGR */ SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN); } -#endif +#endif /* SPI_I2SCFGR_ASTRTEN */ hi2s->ErrorCode = HAL_I2S_ERROR_NONE; hi2s->State = HAL_I2S_STATE_READY; @@ -506,7 +515,8 @@ __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, + pI2S_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -742,7 +752,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). @@ -831,7 +841,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin } /* Check if Slave mode is selected */ - if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) + if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) + || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) { /* Wait until Busy flag is reset */ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK) @@ -858,7 +869,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). @@ -959,7 +970,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -1023,7 +1034,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization @@ -1089,7 +1100,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -1140,7 +1151,10 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, hi2s->hdmatx->XferErrorCallback = I2S_DMAError; /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize)) + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, + (uint32_t)hi2s->pTxBuffPtr, + (uint32_t)&hi2s->Instance->DR, + hi2s->TxXferSize)) { /* Update SPI error code */ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); @@ -1177,7 +1191,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -1236,7 +1250,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, } /* Enable the Rx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize)) + if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, + hi2s->RxXferSize)) { /* Update SPI error code */ SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); @@ -1350,35 +1365,86 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() */ - /* Disable the I2S Tx/Rx DMA requests */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Abort the I2S DMA tx Stream/Channel */ - if (hi2s->hdmatx != NULL) + if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) { - /* Disable the I2S DMA tx Stream/Channel */ - if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + /* Abort the I2S DMA tx Stream/Channel */ + if (hi2s->hdmatx != NULL) { - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - errorcode = HAL_ERROR; + /* Disable the I2S DMA tx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } } + + /* Wait until TXE flag is set */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + + /* Wait until BSY flag is Reset */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); + hi2s->State = HAL_I2S_STATE_READY; + errorcode = HAL_ERROR; + } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + /* Clear UDR flag */ + __HAL_I2S_CLEAR_UDRFLAG(hi2s); + + /* Disable the I2S Tx DMA requests */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + } - /* Abort the I2S DMA rx Stream/Channel */ - if (hi2s->hdmarx != NULL) + else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)) { - /* Disable the I2S DMA rx Stream/Channel */ - if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + /* Abort the I2S DMA rx Stream/Channel */ + if (hi2s->hdmarx != NULL) { - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + /* Disable the I2S DMA rx Stream/Channel */ + if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) + { + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable I2S peripheral */ + __HAL_I2S_DISABLE(hi2s); + + /* Clear OVR flag */ + __HAL_I2S_CLEAR_OVRFLAG(hi2s); + + /* Disable the I2S Rx DMA request */ + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); + + if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX) + { + /* Set the error code */ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX); + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; errorcode = HAL_ERROR; } + else + { + /* Read DR to Flush RX Data */ + READ_REG((hi2s->Instance)->DR); + } } - /* Disable I2S peripheral */ - __HAL_I2S_DISABLE(hi2s); - hi2s->State = HAL_I2S_STATE_READY; return errorcode; @@ -1814,7 +1880,8 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) * @param Timeout Duration of the timeout * @retval HAL status */ -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, uint32_t Timeout) +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, + uint32_t Timeout) { uint32_t tickstart; diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2s.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2s.h index dca9ca03b1..116306dbf6 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2s.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_i2s.h @@ -89,7 +89,7 @@ typedef enum typedef struct __I2S_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ { SPI_TypeDef *Instance; /*!< I2S registers base address */ @@ -176,6 +176,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) #define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ +#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */ /** * @} */ @@ -272,7 +273,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE #define I2S_FLAG_BSY SPI_SR_BSY -#define I2S_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY) +#define I2S_FLAG_MASK (SPI_SR_RXNE\ + | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY) /** * @} */ @@ -306,7 +308,7 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to } while(0) #else #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) -#endif +#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ /** @brief Enable the specified SPI peripheral (in I2S mode). * @param __HANDLE__ specifies the I2S Handle. @@ -352,7 +354,8 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to * @arg I2S_IT_ERR: Error interrupt enable * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified I2S flag is set or not. * @param __HANDLE__ specifies the I2S Handle. @@ -374,19 +377,28 @@ typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to * @retval None */ #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \ - __IO uint32_t tmpreg_ovr = 0x00U; \ - tmpreg_ovr = (__HANDLE__)->Instance->DR; \ - tmpreg_ovr = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg_ovr); \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ }while(0U) /** @brief Clears the I2S UDR pending flag. * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\ - __IO uint32_t tmpreg_udr = 0x00U;\ - tmpreg_udr = ((__HANDLE__)->Instance->SR);\ - UNUSED(tmpreg_udr); \ + __IO uint32_t tmpreg_udr = 0x00U;\ + tmpreg_udr = ((__HANDLE__)->Instance->SR);\ + UNUSED(tmpreg_udr); \ + }while(0U) +/** @brief Flush the I2S DR Register. + * @param __HANDLE__ specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\ + __IO uint32_t tmpreg_dr = 0x00U;\ + tmpreg_dr = ((__HANDLE__)->Instance->DR);\ + UNUSED(tmpreg_dr); \ }while(0U) /** * @} @@ -408,7 +420,8 @@ void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, + pI2S_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ /** @@ -463,21 +476,13 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @defgroup I2S_Private_Constants I2S Private Constants - * @{ - */ - -/** - * @} - */ - /* Private macros ------------------------------------------------------------*/ /** @defgroup I2S_Private_Macros I2S Private Macros * @{ */ /** @brief Check whether the specified SPI flag is set or not. - * @param __SR__ copy of I2S SR regsiter. + * @param __SR__ copy of I2S SR register. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg I2S_FLAG_RXNE: Receive buffer not empty flag @@ -488,10 +493,11 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); * @arg I2S_FLAG_BSY: Busy flag * @retval SET or RESET. */ -#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) +#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\ + & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. - * @param __CR2__ copy of I2S CR2 regsiter. + * @param __CR2__ copy of I2S CR2 register. * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable @@ -499,7 +505,8 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); * @arg I2S_IT_ERR: Error interrupt enable * @retval SET or RESET. */ -#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if I2S Mode parameter is in allowed range. * @param __MODE__ specifies the I2S Mode. @@ -527,7 +534,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); #define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ - ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) + ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) /** @brief Checks if I2S Serial clock steady state parameter is in allowed range. * @param __CPOL__ specifies the I2S serial clock steady state. @@ -535,7 +542,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); * @retval None */ #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ - ((__CPOL__) == I2S_CPOL_HIGH)) + ((__CPOL__) == I2S_CPOL_HIGH)) #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \ ((CLOCK) == I2S_CLOCK_PLL)) diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_irda.c index 03675cbd76..8fcc80a86e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_irda.c @@ -40,7 +40,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter), the normal or low power mode and the clock prescaler in the hirda handle Init structure. @@ -610,43 +611,45 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD switch (CallbackID) { case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : - hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_IRDA_TX_COMPLETE_CB_ID : - hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : - hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_IRDA_RX_COMPLETE_CB_ID : - hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_IRDA_ERROR_CB_ID : - hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_IRDA_ABORT_COMPLETE_CB_ID : - hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : - hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ break; case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : - hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_IRDA_MSPINIT_CB_ID : - hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ + hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_IRDA_MSPDEINIT_CB_ID : - hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -769,13 +772,16 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + Transfer is kept ongoing on IRDA side. If user wants to abort it, Abort services should be called by user. (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + Error code is set to allow user to identify error type, and + HAL_IRDA_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -813,7 +819,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u hirda->ErrorCode = HAL_IRDA_ERROR_NONE; hirda->gState = HAL_IRDA_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); hirda->TxXferSize = Size; @@ -903,7 +909,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui hirda->ErrorCode = HAL_IRDA_ERROR_NONE; hirda->RxState = HAL_IRDA_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); hirda->RxXferSize = Size; @@ -1278,7 +1284,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_IRDA_CLEAR_OREFLAG(hirda); - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -2314,7 +2320,7 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) /* Initialize the IRDA ErrorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ @@ -2359,7 +2365,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_irda.h index 09baf21516..3712b697f0 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_irda.h @@ -75,7 +75,8 @@ typedef struct /** * @brief HAL IRDA State definition - * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition). + * @note HAL IRDA State value is a combination of 2 different substates: + * gState and RxState (see @ref IRDA_State_Definition). * - gState contains IRDA state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -86,7 +87,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called) + * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -103,7 +104,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -245,7 +246,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer Value is allowed for RxState only */ #define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ + Value is result of combination (Or) between + gState and RxState values */ #define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state Value is allowed for gState only */ #define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error @@ -257,15 +259,15 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer /** @defgroup IRDA_Error_Definition IRDA Error Code Definition * @{ */ -#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */ +#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */ #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ /** * @} @@ -547,9 +549,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((__HANDLE__)->Instance->CR3 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. * @param __HANDLE__ specifies the IRDA Handle. @@ -563,10 +570,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) - +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Check whether the specified IRDA interrupt has occurred or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -582,8 +593,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -597,9 +608,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \ + & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \ + & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the IRDA Handle. diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_iwdg.c index 7041a2d937..49c4e518ab 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_iwdg.c @@ -16,52 +16,62 @@ (+) The IWDG can be started by either software or hardware (configurable through option byte). - (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even - if the main clock fails. + (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays + active even if the main clock fails. - (+) Once the IWDG is started, the LSI is forced ON and both can not be + (+) Once the IWDG is started, the LSI is forced ON and both cannot be disabled. The counter starts counting down from the reset value (0xFFF). When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, - the IWDG_RLR value is reloaded in the counter and the watchdog reset is - prevented. + the IWDG_RLR value is reloaded into the counter and the watchdog reset + is prevented. (+) The IWDG is implemented in the VDD voltage domain that is still functional - in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY). IWDGRST flag in RCC_CSR register can be used to inform when an IWDG reset occurs. - (+) Debug mode : When the microcontroller enters debug mode (core halted), + (+) Debug mode: When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module, accessible through __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros. [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s - The IWDG timeout may vary due to LSI frequency dispersion. STM32F7xx - devices provide the capability to measure the LSI frequency (LSI clock - connected internally to TIM16 CH1 input capture). The measured value - can be used to have an IWDG timeout with an acceptable accuracy. + The IWDG timeout may vary due to LSI clock frequency dispersion. + STM32F7xx devices provide the capability to measure the LSI clock + frequency (LSI clock is internally connected to TIM16 CH1 input capture). + The measured value can be used to have an IWDG timeout with an + acceptable accuracy. + + [..] Default timeout value (necessary for IWDG_SR status register update): + Constant LSI_VALUE is defined based on the nominal LSI clock frequency. + This frequency being subject to variations as mentioned above, the + default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT + below) may become too short or too long. + In such cases, this default timeout value can be tuned by redefining + the constant LSI_VALUE at user-application level (based, for instance, + on the measured LSI clock frequency as explained above). ##### How to use this driver ##### ============================================================================== [..] (#) Use IWDG using HAL_IWDG_Init() function to : - (+) Enable instance by writing Start keyword in IWDG_KEY register. LSI + (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI clock is forced ON and IWDG counter starts counting down. - (+) Enable write access to configuration registers: + (++) Enable write access to configuration registers: IWDG_PR, IWDG_RLR and IWDG_WINR. - (+) Configure the IWDG prescaler and counter reload value. This reload + (++) Configure the IWDG prescaler and counter reload value. This reload value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. - (+) Wait for status flags to be reset. - (+) Depending on window parameter: - (++) If Window Init parameter is same as Window register value, + (++) Depending on window parameter: + (+++) If Window Init parameter is same as Window register value, nothing more is done but reload counter value in order to exit function with exact time base. - (++) Else modify Window register. This will automatically reload + (+++) Else modify Window register. This will automatically reload watchdog counter. + (++) Wait for status flags to be reset. (#) Then the application program must refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using @@ -108,8 +118,15 @@ /** @defgroup IWDG_Private_Defines IWDG Private Defines * @{ */ -/* MBED */ -#define HAL_IWDG_DEFAULT_TIMEOUT 96u +/* Status register needs up to 5 LSI clock periods divided by the clock + prescaler to be updated. The number of LSI clock periods is upper-rounded to + 6 for the timeout value calculation. + The timeout value is also calculated using the highest prescaler (256) and + the LSI_VALUE constant. The value of this constant can be changed by the user + to take into account possible LSI clock period variations. + The timeout value is multiplied by 1000 to be converted in milliseconds. */ +#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) +#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} */ @@ -124,8 +141,8 @@ */ /** @addtogroup IWDG_Exported_Functions_Group1 - * @brief Initialization and Start functions. - * + * @brief Initialization and Start functions. + * @verbatim =============================================================================== ##### Initialization and Start functions ##### @@ -180,11 +197,14 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) tickstart = HAL_GetTick(); /* Wait for register to be updated */ - while (hiwdg->Instance->SR != 0x00u) + while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) { - return HAL_TIMEOUT; + if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) + { + return HAL_TIMEOUT; + } } } @@ -207,14 +227,15 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) return HAL_OK; } + /** * @} */ /** @addtogroup IWDG_Exported_Functions_Group2 - * @brief IO operation functions - * + * @brief IO operation functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -226,7 +247,6 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) * @{ */ - /** * @brief Refresh the IWDG. * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains @@ -242,6 +262,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) return HAL_OK; } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_iwdg.h index 7ceb39568c..f4608502f0 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_iwdg.h @@ -87,7 +87,6 @@ typedef struct #define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ #define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ #define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ - /** * @} */ @@ -100,7 +99,6 @@ typedef struct * @} */ - /** * @} */ @@ -138,7 +136,7 @@ typedef struct * @{ */ /* Initialization/Start functions ********************************************/ -HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); /** * @} */ @@ -147,7 +145,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); * @{ */ /* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_jpeg.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_jpeg.c index 282d8f70dc..ab3b542424 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_jpeg.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_jpeg.c @@ -223,15 +223,15 @@ * @{ */ +#ifdef HAL_JPEG_MODULE_ENABLED + +#if defined (JPEG) + /** @defgroup JPEG JPEG * @brief JPEG HAL module driver. * @{ */ -#ifdef HAL_JPEG_MODULE_ENABLED - -#if defined (JPEG) - /* Private define ------------------------------------------------------------*/ /** @addtogroup JPEG_Private_Constants * @{ @@ -1116,7 +1116,11 @@ HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf) { uint32_t error; - uint32_t numberMCU, hfactor, vfactor, hMCU, vMCU; + uint32_t numberMCU; + uint32_t hfactor; + uint32_t vfactor; + uint32_t hMCU; + uint32_t vMCU; /* Check the JPEG handle allocation */ if ((hjpeg == NULL) || (pConf == NULL)) @@ -1296,12 +1300,14 @@ HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTy * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains - * The JPEG decoded header informations + * The JPEG decoded header information * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo) { - uint32_t yblockNb, cBblockNb, cRblockNb; + uint32_t yblockNb; + uint32_t cBblockNb; + uint32_t cRblockNb; /* Check the JPEG handle allocation */ if ((hjpeg == NULL) || (pInfo == NULL)) @@ -2185,7 +2191,8 @@ void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputB */ HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg) { - uint32_t tickstart, tmpContext; + uint32_t tickstart; + uint32_t tmpContext; tmpContext = hjpeg->Context; /*Reset the Context operation and method*/ @@ -2301,7 +2308,7 @@ HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg) * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains - * The JPEG decoded header informations + * The JPEG decoded header information * @retval None */ __weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo) @@ -2512,12 +2519,16 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg) * @param Bits pointer to bits table * @param Huffsize pointer to sizes table * @param Huffcode pointer to codes table - * @param LastK pointer to last Coeff (table dimmension) + * @param LastK pointer to last Coeff (table dimension) * @retval HAL status */ static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK) { - uint32_t i, p, l, code, si; + uint32_t i; + uint32_t p; + uint32_t l; + uint32_t code; + uint32_t si; /* Figure C.1: Generation of table of Huffman code sizes */ p = 0; @@ -2683,7 +2694,9 @@ static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCH { HAL_StatusTypeDef error; JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable; - uint32_t i, lsb, msb; + uint32_t i; + uint32_t lsb; + uint32_t msb; __IO uint32_t *address, *addressDef; if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC0)) @@ -3048,7 +3061,11 @@ static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg) static uint32_t JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, __IO uint32_t *QTableAddress) { - uint32_t i, j, quantRow, quantVal, ScaleFactor; + uint32_t i; + uint32_t j; + uint32_t quantRow; + uint32_t quantVal; + uint32_t ScaleFactor; __IO uint32_t *tableAddress; tableAddress = QTableAddress; @@ -3308,12 +3325,12 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) { uint32_t tmpContext; - /*End of header processing flag rised*/ + /*End of header processing flag */ if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) { if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL) { - /*Call Header parsing complet callback */ + /*Call Header parsing complete callback */ (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); /* Reset the ImageQuality */ hjpeg->Conf.ImageQuality = 0; @@ -3339,13 +3356,13 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) { if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != 0UL) { - /*Input FIFO threshold flag rised*/ + /*Input FIFO threshold flag */ /*JPEG_FIFO_TH_SIZE words can be written in */ JPEG_ReadInputData(hjpeg, JPEG_FIFO_TH_SIZE); } else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != 0UL) { - /*Input FIFO Not Full flag rised*/ + /*Input FIFO Not Full flag */ /*32-bit value can be written in */ JPEG_ReadInputData(hjpeg, 1); } @@ -3361,13 +3378,13 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) { if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != 0UL) { - /*Output FIFO threshold flag rised*/ + /*Output FIFO threshold flag */ /*JPEG_FIFO_TH_SIZE words can be read out */ JPEG_StoreOutputData(hjpeg, JPEG_FIFO_TH_SIZE); } else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL) { - /*Output FIFO Not Empty flag rised*/ + /*Output FIFO Not Empty flag */ /*32-bit value can be read out */ JPEG_StoreOutputData(hjpeg, 1); } @@ -3452,7 +3469,10 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) */ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords) { - uint32_t index, nBwords, nbBytes, dataword; + uint32_t index; + uint32_t nb_words; + uint32_t nb_bytes; + uint32_t dataword; if (hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords * 4UL))) { @@ -3479,8 +3499,8 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor } else if (hjpeg->OutDataLength > hjpeg->JpegOutCount) { - nBwords = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL; - for (index = 0; index < nBwords; index++) + nb_words = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL; + for (index = 0; index < nb_words; index++) { /*Transfer 32 bits from the JPEG output FIFO*/ dataword = hjpeg->Instance->DOR; @@ -3502,9 +3522,9 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor } else { - nbBytes = hjpeg->OutDataLength - hjpeg->JpegOutCount; + nb_bytes = hjpeg->OutDataLength - hjpeg->JpegOutCount; dataword = hjpeg->Instance->DOR; - for (index = 0; index < nbBytes; index++) + for (index = 0; index < nb_bytes; index++) { hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * (index & 0x3UL))) & 0xFFUL); hjpeg->JpegOutCount++; @@ -3518,8 +3538,8 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor hjpeg->JpegOutCount = 0; - nbBytes = 4UL - nbBytes; - for (index = nbBytes; index < 4UL; index++) + nb_bytes = 4UL - nb_bytes; + for (index = nb_bytes; index < 4UL; index++) { hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * index)) & 0xFFUL); hjpeg->JpegOutCount++; @@ -3543,7 +3563,11 @@ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWor */ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords) { - uint32_t nbBytes = 0, nBwords, index, Dataword, inputCount; + uint32_t nb_bytes = 0; + uint32_t nb_words; + uint32_t index; + uint32_t dataword; + uint32_t input_count; if ((hjpeg->InDataLength == 0UL) || (nbRequestWords == 0UL)) { @@ -3552,7 +3576,7 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord } else if (hjpeg->InDataLength > hjpeg->JpegInCount) { - nbBytes = hjpeg->InDataLength - hjpeg->JpegInCount; + nb_bytes = hjpeg->InDataLength - hjpeg->JpegInCount; } else if (hjpeg->InDataLength == hjpeg->JpegInCount) { @@ -3568,39 +3592,39 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL); } hjpeg->JpegInCount = 0; - nbBytes = hjpeg->InDataLength; + nb_bytes = hjpeg->InDataLength; } else { /* Nothing to do */ } - if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nbBytes > 0UL)) + if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nb_bytes > 0UL)) { - nBwords = nbBytes / 4UL; - if (nBwords >= nbRequestWords) + nb_words = nb_bytes / 4UL; + if (nb_words >= nbRequestWords) { for (index = 0; index < nbRequestWords; index++) { - inputCount = hjpeg->JpegInCount; - hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24)); + input_count = hjpeg->JpegInCount; + hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24)); hjpeg->JpegInCount += 4UL; } } - else /*nBwords < nbRequestWords*/ + else /*nb_words < nbRequestWords*/ { - if (nBwords > 0UL) + if (nb_words > 0UL) { - for (index = 0; index < nBwords; index++) + for (index = 0; index < nb_words; index++) { - inputCount = hjpeg->JpegInCount; - hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount])) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 1UL])) << 8) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 2UL])) << 16) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[inputCount + 3UL])) << 24)); + input_count = hjpeg->JpegInCount; + hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \ + (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24)); hjpeg->JpegInCount += 4UL; } @@ -3608,13 +3632,13 @@ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWord else { /* end of file*/ - Dataword = 0; - for (index = 0; index < nbBytes; index++) + dataword = 0; + for (index = 0; index < nb_bytes; index++) { - Dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL)); + dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL)); hjpeg->JpegInCount++; } - hjpeg->Instance->DIR = Dataword; + hjpeg->Instance->DIR = dataword; } } } @@ -3650,10 +3674,10 @@ static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg) /* Set the DMA Out Abort callback */ hjpeg->hdmaout->XferAbortCallback = JPEG_DMAOutAbortCallback; - /*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/ + /*DMA transfer size must be a multiple of 4 bytes i.e multiple of 32bits words*/ hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL); - /*DMA transfer size must be a multiple of 4 bytes i.e mutliple of 32bits words*/ + /*DMA transfer size must be a multiple of 4 bytes i.e multiple of 32bits words*/ hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % 4UL); /* Start DMA FIFO In transfer */ @@ -3791,7 +3815,7 @@ static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg) hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; tmpContext = hjpeg->Context; - /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ + /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); /* Process Unlocked */ @@ -3837,7 +3861,9 @@ static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg) */ static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg) { - uint32_t tmpContext, count, dataOut; + uint32_t tmpContext; + uint32_t count; + uint32_t dataOut; for (count = JPEG_FIFO_SIZE; count > 0UL; count--) { @@ -3888,7 +3914,7 @@ static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg) } tmpContext = hjpeg->Context; - /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ + /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); /* Process Unlocked */ @@ -4127,11 +4153,12 @@ static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg) * @} */ -#endif /* JPEG */ -#endif /* HAL_JPEG_MODULE_ENABLED */ /** * @} */ +#endif /* JPEG */ +#endif /* HAL_JPEG_MODULE_ENABLED */ + /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_jpeg.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_jpeg.h index 52022146db..9acbabd146 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_jpeg.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_jpeg.h @@ -24,10 +24,12 @@ #ifdef __cplusplus extern "C" { #endif -#if defined (JPEG) + /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" +#if defined (JPEG) + /** @addtogroup STM32F7xx_HAL_Driver * @{ */ @@ -397,7 +399,7 @@ typedef void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8 * @arg JPEG_IT_EOC : End of Conversion Interrupt * @arg JPEG_IT_HPD : Header Parsing Done Interrupt * - * @retval No retrun + * @retval No return */ #define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) ) @@ -415,7 +417,7 @@ typedef void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8 * * @note To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits * located in the same IT enable register (CR register). - * @retval No retrun + * @retval No return */ #define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL) @@ -643,6 +645,7 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg); */ #endif /* JPEG */ + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_lptim.c index 09fed9a68f..a29e1ec4b3 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_lptim.c @@ -194,8 +194,8 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t */ /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -232,19 +232,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); - } - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) - { assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); - assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); @@ -278,21 +276,18 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); } if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL)); - } - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) - { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); } - /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | + /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE)); /* Set initialization parameters */ @@ -311,19 +306,21 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) hlptim->Init.UltraLowPowerClock.SampleTime); } - /* Configure the active edge or edges used by the counter only if LPTIM is - * clocked by an external clock source - */ - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + /* Configure LPTIM external clock polarity and digital filter */ + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity); + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + hlptim->Init.UltraLowPowerClock.SampleTime); } + /* Configure LPTIM external trigger */ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ - tmpcfgr |= (hlptim->Init.Trigger.Source | - hlptim->Init.Trigger.ActiveEdge); + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge | + hlptim->Init.Trigger.SampleTime); } /* Write to LPTIMx CFGR */ @@ -418,8 +415,8 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions - * @brief Start-Stop operation functions. - * + * @brief Start-Stop operation functions. + * @verbatim ============================================================================== ##### LPTIM Start Stop operation functions ##### @@ -1548,7 +1545,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t hlptim->State = HAL_LPTIM_STATE_BUSY; /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1631,7 +1629,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1724,8 +1723,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions - * @brief Read operation functions. - * + * @brief Read operation functions. + * @verbatim ============================================================================== ##### LPTIM Read operation functions ##### @@ -1782,8 +1781,8 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks - * @brief LPTIM IRQ handler. - * + * @brief LPTIM IRQ handler. + * @verbatim ============================================================================== ##### LPTIM IRQ handler and callbacks ##### @@ -2251,8 +2250,8 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti */ /** @defgroup LPTIM_Group5 Peripheral State functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim ============================================================================== ##### Peripheral State functions ##### @@ -2327,8 +2326,7 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t { result = HAL_TIMEOUT; } - } - while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); return result; } diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_lptim.h index 9241b88fea..2594f1cfdc 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_lptim.h @@ -345,10 +345,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -484,55 +484,64 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @retval Interrupt status. */ -#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line. * @retval None */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR\ + |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) /** * @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line. * @retval None */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR\ + &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) /** * @brief Enable event on the LPTIM Wake-up Timer associated Exti line. * @retval None. */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR\ + |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) /** * @brief Disable event on the LPTIM Wake-up Timer associated Exti line. * @retval None. */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR\ + &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) /** * @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. * @retval None. */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR\ + |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) /** * @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. * @retval None. */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR\ + &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) /** * @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line. * @retval None. */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR\ + |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) /** * @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line. * @retval None. */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR\ + &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) /** * @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line. @@ -547,26 +556,29 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @retval None. */ #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\ - __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\ + __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\ }while(0) /** * @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not. * @retval Line Status. */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR\ + & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) /** * @brief Clear the LPTIM Wake-up Timer associated Exti line flag. * @retval None. */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR\ + = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) /** * @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line. * @retval None. */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER\ + |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) /** * @} @@ -578,9 +590,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ /** @addtogroup LPTIM_Exported_Functions_Group1 - * @brief Initialization and Configuration functions. - * @{ - */ + * @brief Initialization and Configuration functions. + * @{ + */ /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); @@ -593,9 +605,9 @@ void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group2 - * @brief Start-Stop operation functions. - * @{ - */ + * @brief Start-Stop operation functions. + * @{ + */ /* Start/Stop operation functions *********************************************/ /* ################################# PWM Mode ################################*/ /* Blocking mode: Polling */ @@ -649,9 +661,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group3 - * @brief Read operation functions. - * @{ - */ + * @brief Read operation functions. + * @{ + */ /* Reading operation functions ************************************************/ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); @@ -661,9 +673,9 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group4 - * @brief LPTIM IRQ handler and callback functions. - * @{ - */ + * @brief LPTIM IRQ handler and callback functions. + * @{ + */ /* LPTIM IRQ functions *******************************************************/ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); @@ -678,7 +690,8 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, + pLPTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** @@ -686,9 +699,9 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_ */ /** @addtogroup LPTIM_Group5 - * @brief Peripheral State functions. - * @{ - */ + * @brief Peripheral State functions. + * @{ + */ /* Peripheral State functions ************************************************/ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_mdios.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_mdios.c index 7b5e5a6130..b2caab0582 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_mdios.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_mdios.c @@ -54,8 +54,8 @@ -@@- HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt and execute the previous callbacks - (#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API. - (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources + (#) Reset the MDIOS peripheral and all related resources by calling the HAL_MDIOS_DeInit() API. + (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level resources (GPIO, Clocks, NVIC configuration ...) *** Callback registration *** diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_mmc.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_mmc.c index 155001980c..57058f1357 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_mmc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_mmc.c @@ -287,6 +287,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc); static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc); static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus); +static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout); static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc); static void MMC_Write_IT(MMC_HandleTypeDef *hmmc); static void MMC_Read_IT(MMC_HandleTypeDef *hmmc); @@ -444,6 +445,17 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) return HAL_ERROR; } + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + return HAL_OK; } @@ -584,17 +596,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; @@ -796,17 +797,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) { @@ -984,17 +974,6 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - /* Configure the MMC DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; @@ -1088,17 +1067,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) { @@ -1196,16 +1164,9 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode = errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } + /* Force DMA Direction */ + hmmc->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY; + MODIFY_REG(hmmc->hdmarx->Instance->CR, DMA_SxCR_DIR, hmmc->hdmarx->Init.Direction); /* Enable the DMA Channel */ if(HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK) @@ -1321,16 +1282,6 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) @@ -1360,6 +1311,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat /* Enable SDMMC DMA transfer */ __HAL_MMC_DMA_ENABLE(hmmc); + /* Force DMA Direction */ + hmmc->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH; + MODIFY_REG(hmmc->hdmatx->Instance->CR, DMA_SxCR_DIR, hmmc->hdmatx->Init.Direction); + /* Enable the DMA Channel */ if(HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK) { @@ -1997,6 +1952,8 @@ HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTyp */ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD) { + uint32_t block_nbr = 0; + pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U); pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U); @@ -2035,13 +1992,35 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U); - hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ; - hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); - hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */ + { + return HAL_ERROR; + } + + if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD) + { + hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); + hmmc->MmcCard.LogBlockSize = 512U; + } + else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD) + { + hmmc->MmcCard.BlockNbr = block_nbr; + hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr; + hmmc->MmcCard.BlockSize = 512U; + hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize; + } + else + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } - hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); - hmmc->MmcCard.LogBlockSize = 512U; - pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U); pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U); @@ -2122,7 +2101,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 /* Check the parameters */ assert_param(IS_SDMMC_BUS_WIDE(WideMode)); - /* Chnage Satte */ + /* Change State */ hmmc->State = HAL_MMC_STATE_BUSY; /* Update Clock for Bus mode update */ @@ -2762,6 +2741,93 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) return HAL_MMC_ERROR_NONE; } +/** + * @brief Reads extended CSD register to get the sectors number of the device + * @param hmmc: Pointer to MMC handle + * @param pFieldData: Pointer to the read buffer + * @param FieldIndex: Index of the field to be read + * @param Timeout: Specify timeout value + * @retval HAL status + */ +static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t i = 0; + uint32_t tmp_data; + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 512; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + tmp_data = SDMMC_ReadFIFO(hmmc->Instance); + /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ + /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */ + if ((i + count) == ((uint32_t)FieldIndex/4U)) + { + *pFieldData = tmp_data; + } + } + i += 8U; + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; +} + + /** * @brief Wrap up reading in non-blocking mode. * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_mmc.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_mmc.h index 2d3878f5c5..0635fffa67 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_mmc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_mmc.h @@ -54,7 +54,7 @@ typedef enum HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */ HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */ HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */ - HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfert State */ + HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfer State */ HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */ }HAL_MMC_StateTypeDef; /** diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_nand.c index 7ee025de39..87070dc89b 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_nand.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_nand.c @@ -753,7 +753,18 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); __DSB(); } - + + /* Calculate PageSize */ + if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) + { + size = size / 2U; + } + else + { + /* Do nothing */ + /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ + } + /* Get Data into Buffer */ for(; index < size; index++) { @@ -1013,7 +1024,18 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres __DSB(); } } - + + /* Calculate PageSize */ + if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) + { + size = size / 2U; + } + else + { + /* Do nothing */ + /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ + } + /* Write data to memory */ for(; index < size; index++) { @@ -1238,7 +1260,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad nandAddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2); + columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand)); /* Spare area(s) read loop */ while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) @@ -1534,7 +1556,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A nandAddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2); + columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand)); /* Spare area(s) write loop */ while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_nand.h index c44dd350f1..1d225cfffc 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_nand.h @@ -88,10 +88,10 @@ typedef struct typedef struct { uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes - for 8 bits adressing or words for 16 bits addressing */ + for 8 bits addressing or words for 16 bits addressing */ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes - for 8 bits adressing or words for 16 bits addressing */ + for 8 bits addressing or words for 16 bits addressing */ uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pcd.c index 6ce4edda19..c71fd4c3fd 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pcd.c @@ -102,8 +102,8 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint */ /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -228,7 +228,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { (void)HAL_PCDEx_ActivateLPM(hpcd); } - + (void)USB_DevDisconnect(hpcd->Instance); return HAL_OK; @@ -250,7 +250,10 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; /* Stop Device */ - (void)HAL_PCD_Stop(hpcd); + if (USB_StopDevice(hpcd->Instance) != HAL_OK) + { + return HAL_ERROR; + } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) if (hpcd->MspDeInitCallback == NULL) @@ -319,7 +322,9 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -529,7 +534,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca * @param pCallback pointer to the USB PCD Data OUT Stage Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -564,7 +570,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, } /** - * @brief UnRegister the USB PCD Data OUT Stage Callback + * @brief Unregister the USB PCD Data OUT Stage Callback * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -602,7 +608,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd * @param pCallback pointer to the USB PCD Data IN Stage Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -637,7 +644,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, p } /** - * @brief UnRegister the USB PCD Data IN Stage Callback + * @brief Unregister the USB PCD Data IN Stage Callback * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -675,7 +682,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -710,7 +718,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, } /** - * @brief UnRegister the USB PCD Iso OUT incomplete Callback + * @brief Unregister the USB PCD Iso OUT incomplete Callback * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -748,7 +756,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -783,7 +792,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, p } /** - * @brief UnRegister the USB PCD Iso IN incomplete Callback + * @brief Unregister the USB PCD Iso IN incomplete Callback * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -856,7 +865,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmC } /** - * @brief UnRegister the USB PCD LPM Callback + * @brief Unregister the USB PCD LPM Callback * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -893,8 +902,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -915,9 +924,10 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); - (void)USB_DevConnect(hpcd->Instance); __HAL_PCD_ENABLE(hpcd); + (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -930,18 +940,15 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) { __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); - - if (USB_StopDevice(hpcd->Instance) != HAL_OK) - { - __HAL_UNLOCK(hpcd); - return HAL_ERROR; - } - (void)USB_DevDisconnect(hpcd->Instance); + + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + __HAL_UNLOCK(hpcd); return HAL_OK; } + #if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * @brief Handles PCD interrupt request. @@ -971,7 +978,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); } - /* Handle RxQLevel Interrupt */ + /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); @@ -1156,7 +1163,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); } - + /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) { @@ -1182,7 +1189,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } - + /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { @@ -1326,6 +1333,30 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } } } + + +/** + * @brief Handles PCD Wakeup interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx; + + USBx = hpcd->Instance; + + if ((USBx->CID & (0x1U << 8)) == 0U) + { + /* Clear EXTI pending Bit */ + __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG(); + } + else + { + /* Clear EXTI pending Bit */ + __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG(); + } +} #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -1506,8 +1537,8 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * + * @brief management functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -1530,6 +1561,7 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1543,6 +1575,7 @@ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) __HAL_LOCK(hpcd); (void)USB_DevDisconnect(hpcd->Instance); __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1558,6 +1591,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) hpcd->USB_Address = address; (void)USB_SetDevAddress(hpcd->Instance, address); __HAL_UNLOCK(hpcd); + return HAL_OK; } /** @@ -1568,7 +1602,8 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) * @param ep_type endpoint type * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type) { HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; @@ -1753,10 +1788,12 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) __HAL_LOCK(hpcd); (void)USB_EPSetStall(hpcd->Instance, ep); + if ((ep_addr & EP_ADDR_MSK) == 0U) { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); } + __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1847,8 +1884,8 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State functions ##### diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pcd.h index 650dfd5137..87d02fdb93 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pcd.h @@ -183,9 +183,9 @@ typedef struct /* Exported macros -----------------------------------------------------------*/ /** @defgroup PCD_Exported_Macros PCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ #if defined (USB_OTG_FS) || defined (USB_OTG_HS) #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) @@ -195,12 +195,11 @@ typedef struct #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) -#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ - ~(USB_OTG_PCGCCTL_STOPCLK) +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) -#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) @@ -208,20 +207,20 @@ typedef struct #define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ - do { \ - EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \ - EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ - } while(0U) + do { \ + EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ + } while(0U) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE #define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE #define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ - do { \ - EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ - EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ - } while(0U) + do { \ + EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ + } while(0U) #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -282,22 +281,36 @@ typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgType * @} */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, + pPCD_LpmCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /** @@ -312,6 +325,7 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); +void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd); void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); @@ -336,16 +350,24 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type); + HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint8_t *pBuf, uint32_t len); + +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint8_t *pBuf, uint32_t len); + + HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); + +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); /** * @} */ @@ -411,8 +433,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros - * @{ - */ + * @{ + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pcd_ex.c index 168d963959..f5ed461ccb 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pcd_ex.c @@ -49,7 +49,7 @@ /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @brief PCDEx control functions - * + * @verbatim =============================================================================== ##### Extended features functions ##### diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pwr_ex.h index 698bde6eab..0c33bdf2d4 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_pwr_ex.h @@ -145,7 +145,7 @@ /** @brief Clear the Under-Drive Ready flag. */ -#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY) +#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= (PWR_FLAG_UDRDY | PWR_CSR1_EIWUP)) /** @brief Check Wake Up flag is set or not. * @param __WUFLAG__ specifies the Wake Up flag to check. diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rcc.c index d7132c0454..ab8bb29069 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rcc.c @@ -17,8 +17,8 @@ (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache and I-Cache are disabled, and all peripherals are off except internal SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; - all peripherals mapped on these busses are running at HSI speed. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in input floating state, except the JTAG pins which are assigned to be used for debug purpose. @@ -28,7 +28,7 @@ (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers + (+) Configure the AHB and APB buses prescalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals which clocks are not derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) @@ -154,14 +154,14 @@ (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S clock (through a configurable prescaler) on PC9 pin. - [..] System, AHB and APB busses clocks configuration + [..] System, AHB and APB buses clocks configuration (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, HSE and PLL. The AHB clock (HCLK) is derived from System clock through configurable prescaler and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use + the peripherals mapped on these buses. You can use "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: @@ -696,7 +696,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } /** - * @brief Initializes the CPU, AHB and APB busses clocks according to the specified + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified * parameters in the RCC_ClkInitStruct. * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that * contains the configuration information for the RCC peripheral. diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rcc.h index 1681d79b27..4db8222ee0 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rcc.h @@ -74,7 +74,7 @@ typedef struct }RCC_OscInitTypeDef; /** - * @brief RCC System, AHB and APB busses clock configuration structure definition + * @brief RCC System, AHB and APB buses clock configuration structure definition */ typedef struct { diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rcc_ex.c index ee0900391e..87ae701729 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rcc_ex.c @@ -454,7 +454,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ - if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); @@ -1105,7 +1105,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */ - if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) + if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rtc.c index dad8655fda..f4ce9e09a3 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rtc.c @@ -323,7 +323,19 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Exit Initialization mode */ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + hrtc->State = HAL_RTC_STATE_ERROR; + + return HAL_ERROR; + } + } hrtc->Instance->OR &= (uint32_t)~RTC_OR_ALARMTYPE; hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType); @@ -799,10 +811,10 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Set the RTC_TR register */ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - /* Clear the bits to be configured */ + /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP; - /* Configure the RTC_CR register */ + /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); /* Exit Initialization mode */ @@ -1765,6 +1777,72 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) return hrtc->State; } +/** + * @brief Daylight Saving Time, Add one hour to the calendar in one single operation + * without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(RTC->CR, RTC_CR_ADD1H); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Subtract one hour from the calendar in one + * single operation without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(RTC->CR, RTC_CR_SUB1H); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Set the store operation bit. + * @note It can be used by the software in order to memorize the DST status. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(RTC->CR, RTC_CR_BKP); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Clear the store operation bit. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + CLEAR_BIT(RTC->CR, RTC_CR_BKP); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Read the store operation bit. + * @param hrtc RTC handle + * @retval operation see RTC_StoreOperation_Definitions + */ +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + return READ_BIT(RTC->CR, RTC_CR_BKP); +} + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rtc.h index 87feafad84..9652bef3e3 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_rtc.h @@ -106,12 +106,11 @@ typedef struct uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ - uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. - This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ + uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time, + please use HAL_RTC_DST_xxx functions */ - uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BKP bit - in CR register to store the operation. - This parameter can be a value of @ref RTC_StoreOperation_Definitions */ + uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time, + please use HAL_RTC_DST_xxx functions */ }RTC_TimeTypeDef; /** @@ -693,6 +692,11 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai.c index e8022f4b92..a0ec9a5aae 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai.c @@ -222,10 +222,11 @@ /** @defgroup SAI_Private_Typedefs SAI Private Typedefs * @{ */ -typedef enum { +typedef enum +{ SAI_MODE_DMA, SAI_MODE_IT -}SAI_ModeTypedef; +} SAI_ModeTypedef; /** * @} */ @@ -235,7 +236,8 @@ typedef enum { /** @defgroup SAI_Private_Constants SAI Private Constants * @{ */ -#define SAI_DEFAULT_TIMEOUT 4 /* 4ms */ +#define SAI_DEFAULT_TIMEOUT 4U /* 4ms */ +#define SAI_LONG_TIMEOUT 1000U /** * @} */ @@ -327,23 +329,23 @@ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protoco assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol)); assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize)); - switch(protocol) + switch (protocol) { - case SAI_I2S_STANDARD : - case SAI_I2S_MSBJUSTIFIED : - case SAI_I2S_LSBJUSTIFIED : - status = SAI_InitI2S(hsai, protocol, datasize, nbslot); - break; - case SAI_PCM_LONG : - case SAI_PCM_SHORT : - status = SAI_InitPCM(hsai, protocol, datasize, nbslot); - break; - default : - status = HAL_ERROR; - break; + case SAI_I2S_STANDARD : + case SAI_I2S_MSBJUSTIFIED : + case SAI_I2S_LSBJUSTIFIED : + status = SAI_InitI2S(hsai, protocol, datasize, nbslot); + break; + case SAI_PCM_LONG : + case SAI_PCM_SHORT : + status = SAI_InitPCM(hsai, protocol, datasize, nbslot); + break; + default : + status = HAL_ERROR; + break; } - if(status == HAL_OK) + if (status == HAL_OK) { status = HAL_SAI_Init(hsai); } @@ -365,7 +367,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) uint32_t syncen_bits = 0; /* Check the SAI handle allocation */ - if(hsai == NULL) + if (hsai == NULL) { return HAL_ERROR; } @@ -402,7 +404,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber)); assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive)); - if(hsai->State == HAL_SAI_STATE_RESET) + if (hsai->State == HAL_SAI_STATE_RESET) { /* Allocate lock resource and initialize it */ hsai->Lock = HAL_UNLOCKED; @@ -434,7 +436,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) /* SAI Block Synchro Configuration -----------------------------------------*/ /* This setting must be done with both audio block (A & B) disabled */ - switch(hsai->Init.SynchroExt) + switch (hsai->Init.SynchroExt) { case SAI_SYNCEXT_DISABLE : tmpregisterGCR = 0; @@ -445,38 +447,38 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) case SAI_SYNCEXT_OUTBLOCKB_ENABLE : tmpregisterGCR = SAI_GCR_SYNCOUT_1; break; - default: - break; + default: + break; } - switch(hsai->Init.Synchro) + switch (hsai->Init.Synchro) { case SAI_ASYNCHRONOUS : - { - syncen_bits = 0; - } - break; - case SAI_SYNCHRONOUS : - { - syncen_bits = SAI_xCR1_SYNCEN_0; - } - break; - case SAI_SYNCHRONOUS_EXT_SAI1 : - { - syncen_bits = SAI_xCR1_SYNCEN_1; - } - break; - case SAI_SYNCHRONOUS_EXT_SAI2 : - { - syncen_bits = SAI_xCR1_SYNCEN_1; - tmpregisterGCR |= SAI_GCR_SYNCIN_0; - } - break; - default: + { + syncen_bits = 0; + } break; + case SAI_SYNCHRONOUS : + { + syncen_bits = SAI_xCR1_SYNCEN_0; + } + break; + case SAI_SYNCHRONOUS_EXT_SAI1 : + { + syncen_bits = SAI_xCR1_SYNCEN_1; + } + break; + case SAI_SYNCHRONOUS_EXT_SAI2 : + { + syncen_bits = SAI_xCR1_SYNCEN_1; + tmpregisterGCR |= SAI_GCR_SYNCIN_0; + } + break; + default: + break; } - if((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) + if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) { SAI1->GCR = tmpregisterGCR; } @@ -485,16 +487,16 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) SAI2->GCR = tmpregisterGCR; } - if(hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) + if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) { uint32_t freq = 0; uint32_t tmpval; - if((hsai->Instance == SAI1_Block_A ) || (hsai->Instance == SAI1_Block_B )) + if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); } - if((hsai->Instance == SAI2_Block_A ) || (hsai->Instance == SAI2_Block_B )) + if ((hsai->Instance == SAI2_Block_A) || (hsai->Instance == SAI2_Block_B)) { freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2); } @@ -508,63 +510,71 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) hsai->Init.Mckdiv = tmpval / 10; /* Round result to the nearest integer */ - if((tmpval % 10) > 8) + if ((tmpval % 10) > 8) { - hsai->Init.Mckdiv+= 1; + hsai->Init.Mckdiv += 1; + } + + /* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */ + if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL) + { + hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1; } } /* Check the SAI Block master clock divider parameter */ assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv)); /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */ - if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { /* Transmit */ + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0 : SAI_xCR1_CKSTR; } else - { /* Receive */ + { + /* Receive */ ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0; } /* SAI Block Configuration -------------------------------------------------*/ /* SAI CR1 Configuration */ - hsai->Instance->CR1&=~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ - SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN |\ - SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ - SAI_xCR1_NODIV | SAI_xCR1_MCKDIV); + hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ + SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \ + SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ + SAI_xCR1_NODIV | SAI_xCR1_MCKDIV); - hsai->Instance->CR1|=(hsai->Init.AudioMode | hsai->Init.Protocol | \ - hsai->Init.DataSize | hsai->Init.FirstBit | \ - ckstr_bits | syncen_bits | \ - hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ - hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20)); + hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \ + hsai->Init.DataSize | hsai->Init.FirstBit | \ + ckstr_bits | syncen_bits | \ + hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ + hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20)); /* SAI CR2 Configuration */ - hsai->Instance->CR2&= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL); - hsai->Instance->CR2|= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState); + hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL); + hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState); /* SAI Frame Configuration -----------------------------------------*/ - hsai->Instance->FRCR&=(~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \ - SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF)); - hsai->Instance->FRCR|=((hsai->FrameInit.FrameLength - 1) | - hsai->FrameInit.FSOffset | - hsai->FrameInit.FSDefinition | - hsai->FrameInit.FSPolarity | - ((hsai->FrameInit.ActiveFrameLength - 1) << 8)); + hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \ + SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF)); + hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1) | + hsai->FrameInit.FSOffset | + hsai->FrameInit.FSDefinition | + hsai->FrameInit.FSPolarity | + ((hsai->FrameInit.ActiveFrameLength - 1) << 8)); /* SAI Block_x SLOT Configuration ------------------------------------------*/ /* This register has no meaning in AC 97 and SPDIF audio protocol */ - hsai->Instance->SLOTR&= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \ - SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN )); + hsai->Instance->SLOTR &= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \ + SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN)); - hsai->Instance->SLOTR|= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize - | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) << 8); + hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize + | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) << 8); /* Initialize the error code */ hsai->ErrorCode = HAL_SAI_ERROR_NONE; /* Initialize the SAI state */ - hsai->State= HAL_SAI_STATE_READY; + hsai->State = HAL_SAI_STATE_READY; /* Release Lock */ __HAL_UNLOCK(hsai); @@ -581,7 +591,7 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) { /* Check the SAI handle allocation */ - if(hsai == NULL) + if (hsai == NULL) { return HAL_ERROR; } @@ -884,16 +894,16 @@ HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); - if((pData == NULL ) || (Size == 0)) + if ((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(hsai->State == HAL_SAI_STATE_READY) + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); @@ -905,7 +915,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint hsai->ErrorCode = HAL_SAI_ERROR_NONE; /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) { /* fill the fifo with data before to enabled the SAI */ SAI_FillFifo(hsai); @@ -913,31 +923,31 @@ HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint __HAL_SAI_ENABLE(hsai); } - while(hsai->XferCount > 0) + while (hsai->XferCount > 0) { /* Write data if the FIFO is not full */ - if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) + if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) { - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { hsai->Instance->DR = (*hsai->pBuffPtr++); } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 2; + hsai->pBuffPtr += 2; } else { hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 4; + hsai->pBuffPtr += 4; } hsai->XferCount--; } else { /* Check for the Timeout */ - if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart) > Timeout))) + if ((Timeout != HAL_MAX_DELAY) && ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; @@ -988,12 +998,12 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 { uint32_t tickstart = HAL_GetTick(); - if((pData == NULL ) || (Size == 0)) + if ((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(hsai->State == HAL_SAI_STATE_READY) + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); @@ -1005,37 +1015,37 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 hsai->ErrorCode = HAL_SAI_ERROR_NONE; /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); } /* Receive data */ - while(hsai->XferCount > 0) + while (hsai->XferCount > 0) { - if((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY) + if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY) { - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { (*hsai->pBuffPtr++) = hsai->Instance->DR; } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { - *((uint16_t*)hsai->pBuffPtr) = hsai->Instance->DR; - hsai->pBuffPtr+= 2; + *((uint16_t *)hsai->pBuffPtr) = hsai->Instance->DR; + hsai->pBuffPtr += 2; } else { - *((uint32_t*)hsai->pBuffPtr) = hsai->Instance->DR; - hsai->pBuffPtr+= 4; + *((uint32_t *)hsai->pBuffPtr) = hsai->Instance->DR; + hsai->pBuffPtr += 4; } hsai->XferCount--; } else { /* Check for the Timeout */ - if((Timeout != HAL_MAX_DELAY) && ((Timeout == 0)||((HAL_GetTick() - tickstart) > Timeout))) + if ((Timeout != HAL_MAX_DELAY) && ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))) { /* Update error code */ hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; @@ -1083,12 +1093,12 @@ HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint1 */ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(hsai->State == HAL_SAI_STATE_READY) + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); @@ -1099,11 +1109,11 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_TX; - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit; } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit; } @@ -1119,7 +1129,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); @@ -1145,12 +1155,12 @@ HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, u */ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(hsai->State == HAL_SAI_STATE_READY) + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); @@ -1161,11 +1171,11 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui hsai->ErrorCode = HAL_SAI_ERROR_NONE; hsai->State = HAL_SAI_STATE_BUSY_RX; - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit; } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit; } @@ -1178,7 +1188,7 @@ HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, ui __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) { /* Enable SAI peripheral */ __HAL_SAI_ENABLE(hsai); @@ -1259,12 +1269,12 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; /* Abort the SAI Tx DMA Stream */ - if((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX)) + if ((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX)) { - if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) + if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) { /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ - if(hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) { status = HAL_ERROR; hsai->ErrorCode |= HAL_SAI_ERROR_DMA; @@ -1273,12 +1283,12 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) } /* Abort the SAI Rx DMA Stream */ - if((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX)) + if ((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX)) { - if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) + if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) { /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ - if(hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) { status = HAL_ERROR; hsai->ErrorCode |= HAL_SAI_ERROR_DMA; @@ -1315,18 +1325,18 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) __HAL_LOCK(hsai); /* Check SAI DMA is enabled or not */ - if((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; /* Abort the SAI Tx DMA Stream */ - if((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX)) + if ((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX)) { - if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) + if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) { /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ - if(hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) { status = HAL_ERROR; hsai->ErrorCode |= HAL_SAI_ERROR_DMA; @@ -1335,12 +1345,12 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) } /* Abort the SAI Rx DMA Stream */ - if((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX)) + if ((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX)) { - if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) + if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) { /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ - if(hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) + if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) { status = HAL_ERROR; hsai->ErrorCode |= HAL_SAI_ERROR_DMA; @@ -1377,12 +1387,14 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) */ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + uint32_t tickstart = HAL_GetTick(); + + if ((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(hsai->State == HAL_SAI_STATE_READY) + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); @@ -1406,25 +1418,41 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, hsai->hdmatx->XferAbortCallback = NULL; /* Enable the Tx DMA Stream */ - if(HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK) { __HAL_UNLOCK(hsai); return HAL_ERROR; } - /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - /* Enable the interrupts for error handling */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); /* Enable SAI Tx DMA Request */ hsai->Instance->CR1 |= SAI_xCR1_DMAEN; + /* Wait until FIFO is not empty */ + while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT) + { + /* Update error code */ + hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hsai); + + return HAL_TIMEOUT; + } + } + + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + /* Process Unlocked */ __HAL_UNLOCK(hsai); @@ -1447,12 +1475,12 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) { - if((pData == NULL) || (Size == 0)) + if ((pData == NULL) || (Size == 0)) { return HAL_ERROR; } - if(hsai->State == HAL_SAI_STATE_READY) + if (hsai->State == HAL_SAI_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsai); @@ -1476,25 +1504,25 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u hsai->hdmarx->XferAbortCallback = NULL; /* Enable the Rx DMA Stream */ - if(HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK) { __HAL_UNLOCK(hsai); return HAL_ERROR; } - /* Check if the SAI is already enabled */ - if((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - /* Enable the interrupts for error handling */ __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); /* Enable SAI Rx DMA Request */ hsai->Instance->CR1 |= SAI_xCR1_DMAEN; + /* Check if the SAI is already enabled */ + if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) + { + /* Enable SAI peripheral */ + __HAL_SAI_ENABLE(hsai); + } + /* Process Unlocked */ __HAL_UNLOCK(hsai); @@ -1517,7 +1545,7 @@ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val { assert_param(IS_SAI_BLOCK_MUTE_VALUE(val)); - if(hsai->State != HAL_SAI_STATE_RESET) + if (hsai->State != HAL_SAI_STATE_RESET) { CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val); @@ -1534,7 +1562,7 @@ HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val */ HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) { - if(hsai->State != HAL_SAI_STATE_RESET) + if (hsai->State != HAL_SAI_STATE_RESET) { CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); return HAL_OK; @@ -1554,7 +1582,7 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback { assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter)); - if(hsai->State != HAL_SAI_STATE_RESET) + if (hsai->State != HAL_SAI_STATE_RESET) { /* set the mute counter */ CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT); @@ -1575,7 +1603,7 @@ HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback */ HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) { - if(hsai->State != HAL_SAI_STATE_RESET) + if (hsai->State != HAL_SAI_STATE_RESET) { /* set the mutecallback to NULL */ hsai->mutecallback = (SAIcallback)NULL; @@ -1594,7 +1622,7 @@ HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) */ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) { - if(hsai->State != HAL_SAI_STATE_RESET) + if (hsai->State != HAL_SAI_STATE_RESET) { uint32_t itflags = hsai->Instance->SR; uint32_t itsources = hsai->Instance->IMR; @@ -1602,12 +1630,12 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) uint32_t tmperror; /* SAI Fifo request interrupt occurred ------------------------------------*/ - if(((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) + if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) { hsai->InterruptServiceRoutine(hsai); } /* SAI Overrun error interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR)) + else if (((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR)) { /* Clear the SAI Overrun flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); @@ -1623,27 +1651,30 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) #endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ } /* SAI mutedet interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET)) + else if (((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET)) { /* Clear the SAI mutedet flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET); /* call the call back function */ - if(hsai->mutecallback != (SAIcallback)NULL) + if (hsai->mutecallback != (SAIcallback)NULL) { /* inform the user that an RX mute event has been detected */ hsai->mutecallback(); } } /* SAI AFSDET interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) + else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) { + /* Clear the SAI AFSDET flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET); + /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET; /* Check SAI DMA is enabled or not */ - if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) + if (hsai->hdmatx != NULL) { /* Set the DMA Tx abort callback */ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; @@ -1651,7 +1682,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) /* Abort DMA in IT mode */ HAL_DMA_Abort_IT(hsai->hdmatx); } - else if(hsai->hdmarx != NULL) + else if (hsai->hdmarx != NULL) { /* Set the DMA Rx abort callback */ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; @@ -1673,23 +1704,26 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) } } /* SAI LFSDET interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) + else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) { + /* Clear the SAI LFSDET flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET); + /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET; /* Check SAI DMA is enabled or not */ - if((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) + if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) + if (hsai->hdmatx != NULL) { /* Set the DMA Tx abort callback */ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; /* Abort DMA in IT mode */ HAL_DMA_Abort_IT(hsai->hdmatx); } - else if(hsai->hdmarx != NULL) + else if (hsai->hdmarx != NULL) { /* Set the DMA Rx abort callback */ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; @@ -1711,20 +1745,23 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) } } /* SAI WCKCFG interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) + else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) { + /* Clear the SAI WCKCFG flag */ + __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG); + /* Change the SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG; /* Abort the SAI DMA Streams */ - if(hsai->hdmatx != NULL) + if (hsai->hdmatx != NULL) { /* Set the DMA Tx abort callback */ hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; /* Abort DMA in IT mode */ HAL_DMA_Abort_IT(hsai->hdmatx); } - else if(hsai->hdmarx != NULL) + else if (hsai->hdmarx != NULL) { /* Set the DMA Rx abort callback */ hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; @@ -1752,7 +1789,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) } } /* SAI CNRDY interrupt occurred ----------------------------------*/ - else if(((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY)) + else if (((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY)) { /* Clear the SAI CNRDY flag */ __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY); @@ -1794,7 +1831,7 @@ __weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) * the configuration information for SAI module. * @retval None */ - __weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) +__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsai); @@ -1923,12 +1960,14 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, hsai->Init.Protocol = SAI_FREE_PROTOCOL; hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; /* Compute ClockStrobing according AudioMode */ - if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { /* Transmit */ + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; } else - { /* Receive */ + { + /* Receive */ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; } hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; @@ -1937,57 +1976,54 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, hsai->SlotInit.SlotNumber = nbslot; /* in IS2 the number of slot must be even */ - if((nbslot & 0x1) != 0 ) + if ((nbslot & 0x1) != 0) { return HAL_ERROR; } - switch(protocol) + if (protocol == SAI_I2S_STANDARD) { - case SAI_I2S_STANDARD : hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; - break; - case SAI_I2S_MSBJUSTIFIED : - case SAI_I2S_LSBJUSTIFIED : + } + else + { + /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */ hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; - break; - default : - return HAL_ERROR; } /* Frame definition */ - switch(datasize) + switch (datasize) { - case SAI_PROTOCOL_DATASIZE_16BIT: - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 32*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 16*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; - break; - case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 64*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_24BIT: - hsai->Init.DataSize = SAI_DATASIZE_24; - hsai->FrameInit.FrameLength = 64*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_32BIT: - hsai->Init.DataSize = SAI_DATASIZE_32; - hsai->FrameInit.FrameLength = 64*(nbslot/2); - hsai->FrameInit.ActiveFrameLength = 32*(nbslot/2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - default : - return HAL_ERROR; + case SAI_PROTOCOL_DATASIZE_16BIT: + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 32 * (nbslot / 2); + hsai->FrameInit.ActiveFrameLength = 16 * (nbslot / 2); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; + break; + case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 64 * (nbslot / 2); + hsai->FrameInit.ActiveFrameLength = 32 * (nbslot / 2); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_24BIT: + hsai->Init.DataSize = SAI_DATASIZE_24; + hsai->FrameInit.FrameLength = 64 * (nbslot / 2); + hsai->FrameInit.ActiveFrameLength = 32 * (nbslot / 2); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_32BIT: + hsai->Init.DataSize = SAI_DATASIZE_32; + hsai->FrameInit.FrameLength = 64 * (nbslot / 2); + hsai->FrameInit.ActiveFrameLength = 32 * (nbslot / 2); + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + default : + return HAL_ERROR; } - if(protocol == SAI_I2S_LSBJUSTIFIED) + if (protocol == SAI_I2S_LSBJUSTIFIED) { if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) { @@ -2016,12 +2052,14 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, hsai->Init.Protocol = SAI_FREE_PROTOCOL; hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; /* Compute ClockStrobing according AudioMode */ - if((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { /* Transmit */ + if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + { + /* Transmit */ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; } else - { /* Receive */ + { + /* Receive */ hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; } hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME; @@ -2031,42 +2069,40 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, hsai->SlotInit.SlotNumber = nbslot; hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; - switch(protocol) + if (protocol == SAI_PCM_SHORT) { - case SAI_PCM_SHORT : hsai->FrameInit.ActiveFrameLength = 1; - break; - case SAI_PCM_LONG : + } + else + { + /* SAI_PCM_LONG */ hsai->FrameInit.ActiveFrameLength = 13; - break; - default : - return HAL_ERROR; } - switch(datasize) + switch (datasize) { - case SAI_PROTOCOL_DATASIZE_16BIT: - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 16 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; - break; - case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_24BIT : - hsai->Init.DataSize = SAI_DATASIZE_24; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_32BIT: - hsai->Init.DataSize = SAI_DATASIZE_32; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - default : - return HAL_ERROR; + case SAI_PROTOCOL_DATASIZE_16BIT: + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 16 * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; + break; + case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : + hsai->Init.DataSize = SAI_DATASIZE_16; + hsai->FrameInit.FrameLength = 32 * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_24BIT : + hsai->Init.DataSize = SAI_DATASIZE_24; + hsai->FrameInit.FrameLength = 32 * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + case SAI_PROTOCOL_DATASIZE_32BIT: + hsai->Init.DataSize = SAI_DATASIZE_32; + hsai->FrameInit.FrameLength = 32 * nbslot; + hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; + break; + default : + return HAL_ERROR; } return HAL_OK; @@ -2081,21 +2117,21 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, static void SAI_FillFifo(SAI_HandleTypeDef *hsai) { /* fill the fifo with data before to enabled the SAI */ - while(((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0)) + while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0)) { - if((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) + if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) { hsai->Instance->DR = (*hsai->pBuffPtr++); } - else if(hsai->Init.DataSize <= SAI_DATASIZE_16) + else if (hsai->Init.DataSize <= SAI_DATASIZE_16) { hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 2; + hsai->pBuffPtr += 2; } else { hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr+= 4; + hsai->pBuffPtr += 4; } hsai->XferCount--; } @@ -2112,25 +2148,25 @@ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) { uint32_t tmpIT = SAI_IT_OVRUDR; - if(mode == SAI_MODE_IT) + if (mode == SAI_MODE_IT) { - tmpIT|= SAI_IT_FREQ; + tmpIT |= SAI_IT_FREQ; } - if((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && - ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX))) + if ((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && + ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX))) { - tmpIT|= SAI_IT_CNRDY; + tmpIT |= SAI_IT_CNRDY; } - if((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) + if ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) { - tmpIT|= SAI_IT_AFSDET | SAI_IT_LFSDET; + tmpIT |= SAI_IT_AFSDET | SAI_IT_LFSDET; } else { /* hsai has been configured in master mode */ - tmpIT|= SAI_IT_WCKCFG; + tmpIT |= SAI_IT_WCKCFG; } return tmpIT; } @@ -2143,7 +2179,7 @@ static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) */ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) { - register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock /7/1000); + uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7 / 1000); HAL_StatusTypeDef status = HAL_OK; /* Disable the SAI instance */ @@ -2159,7 +2195,8 @@ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) status = HAL_TIMEOUT; break; } - } while((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET); + } + while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET); return status; } @@ -2172,7 +2209,7 @@ static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) */ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) { - if(hsai->XferCount == 0) + if (hsai->XferCount == 0) { /* Handle the end of the transmission */ /* Disable FREQ and OVRUDR interrupts */ @@ -2200,7 +2237,7 @@ static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) */ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) { - if(hsai->XferCount == 0) + if (hsai->XferCount == 0) { /* Handle the end of the transmission */ /* Disable FREQ and OVRUDR interrupts */ @@ -2216,7 +2253,7 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) { /* Write data on DR register */ hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr; - hsai->pBuffPtr+=2; + hsai->pBuffPtr += 2; hsai->XferCount--; } } @@ -2229,7 +2266,7 @@ static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) */ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) { - if(hsai->XferCount == 0) + if (hsai->XferCount == 0) { /* Handle the end of the transmission */ /* Disable FREQ and OVRUDR interrupts */ @@ -2245,7 +2282,7 @@ static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) { /* Write data on DR register */ hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr; - hsai->pBuffPtr+=4; + hsai->pBuffPtr += 4; hsai->XferCount--; } } @@ -2263,7 +2300,7 @@ static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) hsai->XferCount--; /* Check end of the transfer */ - if(hsai->XferCount == 0) + if (hsai->XferCount == 0) { /* Disable TXE and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); @@ -2289,12 +2326,12 @@ static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) { /* Receive data */ - *(uint16_t*)hsai->pBuffPtr = hsai->Instance->DR; - hsai->pBuffPtr+=2; + *(uint16_t *)hsai->pBuffPtr = hsai->Instance->DR; + hsai->pBuffPtr += 2; hsai->XferCount--; /* Check end of the transfer */ - if(hsai->XferCount == 0) + if (hsai->XferCount == 0) { /* Disable TXE and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); @@ -2320,12 +2357,12 @@ static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) { /* Receive data */ - *(uint32_t*)hsai->pBuffPtr = hsai->Instance->DR; - hsai->pBuffPtr+=4; + *(uint32_t *)hsai->pBuffPtr = hsai->Instance->DR; + hsai->pBuffPtr += 4; hsai->XferCount--; /* Check end of the transfer */ - if(hsai->XferCount == 0) + if (hsai->XferCount == 0) { /* Disable TXE and OVRUDR interrupts */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); @@ -2350,7 +2387,7 @@ static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) */ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef* )hdma)->Parent; + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma->Init.Mode != DMA_CIRCULAR) { @@ -2362,7 +2399,7 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) /* Stop the interrupts error handling */ __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - hsai->State= HAL_SAI_STATE_READY; + hsai->State = HAL_SAI_STATE_READY; } #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) hsai->TxCpltCallback(hsai); @@ -2379,7 +2416,7 @@ static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) */ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) hsai->TxHalfCpltCallback(hsai); @@ -2396,7 +2433,7 @@ static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) */ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma->Init.Mode != DMA_CIRCULAR) { @@ -2424,7 +2461,7 @@ static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) */ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = (SAI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) hsai->RxHalfCpltCallback(hsai); @@ -2441,12 +2478,12 @@ static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) */ static void SAI_DMAError(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Set SAI error code */ hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - if((hsai->hdmatx->ErrorCode == HAL_DMA_ERROR_TE) || (hsai->hdmarx->ErrorCode == HAL_DMA_ERROR_TE)) + if ((hsai->hdmatx->ErrorCode == HAL_DMA_ERROR_TE) || (hsai->hdmarx->ErrorCode == HAL_DMA_ERROR_TE)) { /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; @@ -2476,7 +2513,7 @@ static void SAI_DMAError(DMA_HandleTypeDef *hdma) */ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) { - SAI_HandleTypeDef* hsai = ( SAI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; @@ -2485,7 +2522,7 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) hsai->Instance->IMR = 0U; hsai->Instance->CLRFR = 0xFFFFFFFFU; - if(hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG) + if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG) { /* Disable SAI peripheral */ SAI_Disable(hsai); diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai.h index 3a32096dc4..d782269a38 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai.h @@ -22,7 +22,7 @@ #define __STM32F7xx_HAL_SAI_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif @@ -52,7 +52,7 @@ typedef enum HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */ HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */ HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */ -}HAL_SAI_StateTypeDef; +} HAL_SAI_StateTypeDef; /** * @brief SAI Callback prototype @@ -125,13 +125,14 @@ typedef struct uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. This parameter can be a value of @ref SAI_Block_Clock_Strobing */ -}SAI_InitTypeDef; +} SAI_InitTypeDef; /** * @} */ /** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition * @brief SAI Frame Init structure definition + * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware). * @{ */ typedef struct @@ -157,13 +158,15 @@ typedef struct uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset. This parameter can be a value of @ref SAI_Block_FS_Offset */ -}SAI_FrameInitTypeDef; +} SAI_FrameInitTypeDef; /** * @} */ /** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition * @brief SAI Block Slot Init Structure definition + * @note For SPDIF protocol, these parameters are not used (set by hardware). + * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware). * @{ */ typedef struct @@ -179,7 +182,7 @@ typedef struct uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated. This parameter can be a value of @ref SAI_Block_Slot_Active */ -}SAI_SlotInitTypeDef; +} SAI_SlotInitTypeDef; /** * @} */ @@ -227,7 +230,7 @@ typedef struct __SAI_HandleTypeDef void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */ void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */ #endif -}SAI_HandleTypeDef; +} SAI_HandleTypeDef; /** * @} */ @@ -657,9 +660,9 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) - /** - * @} - */ +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup SAI_Exported_Functions @@ -672,7 +675,7 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); */ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai); -HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai); +HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai); void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai); void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai); diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai_ex.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai_ex.c index 4785555aac..f9eb86234e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai_ex.c @@ -19,7 +19,7 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai_ex.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai_ex.h index 51832019d1..1a521cb593 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sai_ex.h @@ -24,7 +24,7 @@ /* Includes ------------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Extended features functions ************************************************/ /* Private types -------------------------------------------------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sd.c index 33a086184a..4a3744fcb1 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sd.c @@ -448,6 +448,17 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) return HAL_ERROR; } + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + return HAL_OK; } @@ -588,17 +599,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = NumberOfBlocks * BLOCKSIZE; @@ -810,17 +810,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = NumberOfBlocks * BLOCKSIZE; @@ -1007,17 +996,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; @@ -1111,17 +1089,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) { @@ -1215,6 +1182,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Set the DMA Abort callback */ hsd->hdmarx->XferAbortCallback = NULL; + /* Force DMA Direction */ + hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY; + MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction); + /* Enable the DMA Channel */ if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) { @@ -1234,17 +1205,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - /* Configure the SD DPSM (Data Path State Machine) */ config.DataTimeOut = SDMMC_DATATIMEOUT; config.DataLength = BLOCKSIZE * NumberOfBlocks; @@ -1345,17 +1305,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, add *= 512U; } - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - /* Write Blocks in Polling mode */ if(NumberOfBlocks > 1U) { @@ -1384,6 +1333,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, /* Enable SDMMC DMA transfer */ __HAL_SD_DMA_ENABLE(hsd); + /* Force DMA Direction */ + hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH; + MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction); + /* Enable the DMA Channel */ if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) { @@ -2144,6 +2097,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT { uint32_t sd_status[16]; uint32_t errorstate; + HAL_StatusTypeDef status = HAL_OK; errorstate = SD_SendSDStatus(hsd, sd_status); if(errorstate != HAL_SD_ERROR_NONE) @@ -2152,7 +2106,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= errorstate; hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; + status = HAL_ERROR; } else { @@ -2178,7 +2132,18 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U); } - return HAL_OK; + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode = errorstate; + hsd->State = HAL_SD_STATE_READY; + status = HAL_ERROR; + } + + return status; } /** @@ -2217,6 +2182,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t { SDMMC_InitTypeDef Init; uint32_t errorstate; + HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_SDMMC_BUS_WIDE(WideMode)); @@ -2259,7 +2225,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; + status = HAL_ERROR; } else { @@ -2273,10 +2239,20 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t (void)SDMMC_Init(hsd->Instance, Init); } + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + status = HAL_ERROR; + } + /* Change State */ hsd->State = HAL_SD_STATE_READY; - return HAL_OK; + return status; } /** @@ -3097,13 +3073,17 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) return errorstate; } - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT)) { if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) { *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance); index++; } + else if(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXACT)) + { + break; + } if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sd.h index 305f83aa88..176dc1236f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sd.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_sd.h @@ -55,7 +55,7 @@ typedef enum HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */ HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */ HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */ - HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfert State */ + HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfer State */ HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */ }HAL_SD_StateTypeDef; /** diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smartcard.c index c964ad0ab4..704c236f45 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smartcard.c @@ -35,7 +35,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission @@ -107,8 +108,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback. - Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: + Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback. + Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. (+) ErrorCallback : Error Callback. @@ -121,9 +122,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default + Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Complete Callback. @@ -136,13 +137,13 @@ (+) MspDeInitCallback : SMARTCARD MspDeInit. [..] - By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET + By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback(). + examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init() - and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init() + and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -151,8 +152,8 @@ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit() - or @ref HAL_SMARTCARD_Init() function. + using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit() + or HAL_SMARTCARD_Init() function. [..] When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or @@ -194,21 +195,23 @@ /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants * @{ */ -#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ +#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \ - USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ +#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ + USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ -#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \ + USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | \ + USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ -#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ +#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ /** * @} */ @@ -473,7 +476,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -599,36 +603,38 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma switch (CallbackID) { case HAL_SMARTCARD_TX_COMPLETE_CB_ID : - hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_SMARTCARD_RX_COMPLETE_CB_ID : - hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_SMARTCARD_ERROR_CB_ID : - hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : - hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : - hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback*/ break; case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : - hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_SMARTCARD_MSPINIT_CB_ID : - hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_SMARTCARD_MSPDEINIT_CB_ID : - hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -699,62 +705,67 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. [..] - (+) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. + (#) There are two modes of transfer: + (##) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. - (++) Non-Blocking mode: The communication is performed using Interrupts + (##) Non-Blocking mode: The communication is performed using Interrupts or DMA, the relevant API's return the HAL status. The end of the data processing will be indicated through the dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks + (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks will be executed respectively at the end of the Transmit or Receive process The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication error is detected. - (+) Blocking mode APIs are : - (++) HAL_SMARTCARD_Transmit() - (++) HAL_SMARTCARD_Receive() + (#) Blocking mode APIs are : + (##) HAL_SMARTCARD_Transmit() + (##) HAL_SMARTCARD_Receive() - (+) Non Blocking mode APIs with Interrupt are : - (++) HAL_SMARTCARD_Transmit_IT() - (++) HAL_SMARTCARD_Receive_IT() - (++) HAL_SMARTCARD_IRQHandler() + (#) Non Blocking mode APIs with Interrupt are : + (##) HAL_SMARTCARD_Transmit_IT() + (##) HAL_SMARTCARD_Receive_IT() + (##) HAL_SMARTCARD_IRQHandler() - (+) Non Blocking mode functions with DMA are : - (++) HAL_SMARTCARD_Transmit_DMA() - (++) HAL_SMARTCARD_Receive_DMA() + (#) Non Blocking mode functions with DMA are : + (##) HAL_SMARTCARD_Transmit_DMA() + (##) HAL_SMARTCARD_Receive_DMA() - (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_SMARTCARD_TxCpltCallback() - (++) HAL_SMARTCARD_RxCpltCallback() - (++) HAL_SMARTCARD_ErrorCallback() + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (##) HAL_SMARTCARD_TxCpltCallback() + (##) HAL_SMARTCARD_RxCpltCallback() + (##) HAL_SMARTCARD_ErrorCallback() [..] (#) Non-Blocking mode transfers could be aborted using Abort API's : - (++) HAL_SMARTCARD_Abort() - (++) HAL_SMARTCARD_AbortTransmit() - (++) HAL_SMARTCARD_AbortReceive() - (++) HAL_SMARTCARD_Abort_IT() - (++) HAL_SMARTCARD_AbortTransmit_IT() - (++) HAL_SMARTCARD_AbortReceive_IT() + (##) HAL_SMARTCARD_Abort() + (##) HAL_SMARTCARD_AbortTransmit() + (##) HAL_SMARTCARD_AbortReceive() + (##) HAL_SMARTCARD_Abort_IT() + (##) HAL_SMARTCARD_AbortTransmit_IT() + (##) HAL_SMARTCARD_AbortReceive_IT() - (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (++) HAL_SMARTCARD_AbortCpltCallback() - (++) HAL_SMARTCARD_AbortTransmitCpltCallback() - (++) HAL_SMARTCARD_AbortReceiveCpltCallback() + (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), + a set of Abort Complete Callbacks are provided: + (##) HAL_SMARTCARD_AbortCpltCallback() + (##) HAL_SMARTCARD_AbortTransmitCpltCallback() + (##) HAL_SMARTCARD_AbortReceiveCpltCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. - If user wants to abort it, Abort services should be called by user. - (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. + (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, + Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. + If user wants to abort it, Abort services should be called by user. + (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt + mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -794,14 +805,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - /* Disable Rx, enable Tx */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST); + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; hsmartcard->TxXferSize = Size; hsmartcard->TxXferCount = Size; @@ -816,20 +836,28 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); ptmpdata++; } - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, - Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, + tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */ - if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + + /* Disable the Peripheral first to update mode */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { - /* Disable the Peripheral first to update modes */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - /* Enable the Peripheral */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* In case of TX only mode, if NACK is enabled, receiver block has been enabled + for Transmit phase. Disable this receiver block. */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + } + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); /* At end of Tx process, restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -939,14 +967,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - /* Disable Rx, enable Tx */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST); + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + /* Configure Tx interrupt processing */ /* Set the Tx ISR function pointer */ hsmartcard->TxISR = SMARTCARD_TxISR; @@ -1048,14 +1085,23 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard /* Disable the Peripheral first to update mode for TX master */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - /* Disable Rx, enable Tx */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST); + /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor + the bidirectional line to detect a NACK signal in case of parity error. + Therefore, the receiver block must be enabled as well (RE bit must be set). */ + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); + } + /* Enable Tx */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); /* Enable the Peripheral */ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* Perform a TX/RX FIFO Flush */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + /* Set the SMARTCARD DMA transfer complete callback */ hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; @@ -1198,7 +1244,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, - (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); /* Disable the SMARTCARD DMA Tx request if enabled */ @@ -1257,8 +1304,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1388,8 +1435,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1418,11 +1465,13 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, - (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ + /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, + DMA Abort complete callbacks should be initialised before any call + to DMA Abort functions */ /* DMA Tx Handle is valid */ if (hsmartcard->hdmatx != NULL) { @@ -1516,8 +1565,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1687,8 +1736,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1713,8 +1762,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -2156,12 +2205,14 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard) { /* Init the SMARTCARD Callback settings */ - hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ - hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ - hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ - hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ } #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -2200,7 +2251,8 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * Configure the Parity and Mode: * set PS bit according to hsmartcard->Init.Parity value * set TE and RE bits according to hsmartcard->Init.Mode value */ - tmpreg = (uint32_t)(hsmartcard->Init.Parity | hsmartcard->Init.Mode | hsmartcard->Init.WordLength); + tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) | + ((uint32_t)hsmartcard->Init.WordLength)); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ @@ -2405,7 +2457,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -2599,8 +2652,8 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2648,8 +2701,8 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2710,8 +2763,8 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -2773,15 +2826,22 @@ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); } - /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */ - if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + /* Disable the Peripheral first to update mode */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { - /* Disable the Peripheral first to update modes */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - /* Enable the Peripheral */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); + /* In case of TX only mode, if NACK is enabled, receiver block has been enabled + for Transmit phase. Disable this receiver block. */ + CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } + if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + { + /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ + __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); + } + SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); /* Tx process is ended, restore hsmartcard->gState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smartcard.h index c14c584b89..b5e19b5734 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smartcard.h @@ -52,7 +52,8 @@ typedef struct where usart_ker_ckpres is the USART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */ + This parameter @ref SMARTCARD_Word_Length can only be + set to 9 (8 data + 1 parity bits). */ uint32_t StopBits; /*!< Specifies the number of stop bits. This parameter can be a value of @ref SMARTCARD_Stop_Bits. */ @@ -76,13 +77,14 @@ typedef struct data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref SMARTCARD_Last_Bit */ - uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ + uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote + is selected. Selecting the single sample method increases + the receiver tolerance to clock deviations. This parameter can be a value + of @ref SMARTCARD_OneBit_Sampling. */ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. - This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied - by 2 to give the division factor of the source clock frequency */ + This parameter can be any value from 0x01 to 0x1F. Prescaler value is + multiplied by 2 to give the division factor of the source clock frequency */ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ @@ -108,7 +110,7 @@ typedef struct } SMARTCARD_InitTypeDef; /** - * @brief SMARTCARD advanced features initalization structure definition + * @brief SMARTCARD advanced features initialization structure definition */ typedef struct { @@ -138,14 +140,16 @@ typedef struct uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. This parameter can be a value of @ref SMARTCARD_MSB_First */ - uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when - relevant flag is available) or once guard time period has elapsed. - This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */ + uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when + relevant flag is available) or once guard time period has elapsed. + This parameter can be a value + of @ref SMARTCARDEx_Transmission_Completion_Indication. */ } SMARTCARD_AdvFeatureInitTypeDef; /** * @brief HAL SMARTCARD State definition - * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition). + * @note HAL SMARTCARD State value is a combination of 2 different substates: + * gState and RxState (see @ref SMARTCARD_State_Definition). * - gState contains SMARTCARD state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -156,7 +160,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called) + * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -173,7 +177,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -218,12 +222,14 @@ typedef struct __SMARTCARD_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global + Handle management and also related to Tx operations. + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO uint32_t ErrorCode; /*!< SmartCard Error code */ @@ -297,23 +303,26 @@ typedef enum /** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition * @{ */ -#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ -#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value + is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for + use. Value is allowed for gState + and RxState */ #define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing Value is allowed for RxState only */ -#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ +#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception + process is ongoing Not to be used for + neither gState nor RxState. + Value is result of combination (Or) + between gState and RxState values */ #define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error - Value is allowed for gState only */ + Value is allowed for gState only */ /** * @} */ @@ -321,15 +330,15 @@ typedef enum /** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition * @{ */ -#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */ +#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */ #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) -#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** * @} @@ -622,16 +631,24 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before + * guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -641,16 +658,24 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard + * time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -660,15 +685,18 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\ + (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\ + & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\ + ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -678,16 +706,24 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x01U)?\ + (__HANDLE__)->Instance->CR1 : \ + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x02U)?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) &\ + (0x01UL << (((uint16_t)(__INTERRUPT__))\ + & SMARTCARD_IT_MASK))) != 0U)\ + ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -1038,7 +1074,8 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smbus.c index a01d9f8c61..0da63dc730 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smbus.c @@ -203,18 +203,20 @@ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, + uint32_t Timeout); -static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); -static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); -static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); /** * @} */ @@ -226,8 +228,8 @@ static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t */ /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -579,7 +581,8 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, + pSMBUS_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -858,8 +861,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) */ /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -911,7 +914,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -950,7 +954,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } else { @@ -1010,7 +1015,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -1050,7 +1056,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); } else { @@ -1165,7 +1172,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -1213,7 +1221,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); } else { @@ -1259,7 +1268,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -1417,7 +1427,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) { uint32_t tickstart; @@ -1526,8 +1537,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Increment Trials */ SMBUS_Trials++; - } - while (SMBUS_Trials < Trials); + } while (SMBUS_Trials < Trials); hsmbus->State = HAL_SMBUS_STATE_READY; @@ -1549,8 +1559,8 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t */ /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /** * @brief Handle SMBUS event interrupt request. @@ -1566,7 +1576,12 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1); /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) @@ -1585,7 +1600,12 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Receiver ----------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) @@ -1604,7 +1624,12 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Listener Only --------------------------------------------------*/ - if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { @@ -1744,8 +1769,8 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) */ /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * + * @brief Peripheral State and Errors functions + * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### @@ -1771,11 +1796,11 @@ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) } /** -* @brief Return the SMBUS error code. + * @brief Return the SMBUS error code. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. -* @retval SMBUS Error Code -*/ + * @retval SMBUS Error Code + */ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) { return hsmbus->ErrorCode; @@ -1790,7 +1815,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) */ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions - * @brief Data transfers Private functions + * @brief Data transfers Private functions * @{ */ @@ -1801,7 +1826,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { uint16_t DevAddress; @@ -1854,7 +1879,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* REenable the selected SMBUS peripheral */ + /* Re-enable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); /* Call the corresponding callback to inform upper layer of End of Transfer */ @@ -1941,7 +1966,8 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, if (hsmbus->XferCount > MAX_NBYTE_SIZE) { - SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else @@ -2085,7 +2111,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(struct __SMBUS_HandleTypeDef *hsmbus, * @param StatusFlags Value of Interrupt Flags. * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) +static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) { uint8_t TransferDirection; uint16_t SlaveAddrCode; @@ -2155,7 +2181,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, u HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } - else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) + else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || + (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) { if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { @@ -2210,7 +2237,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, u { if (hsmbus->XferCount > MAX_NBYTE_SIZE) { - SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else @@ -2341,7 +2369,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(struct __SMBUS_HandleTypeDef *hsmbus, u * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) { uint32_t tmpisr = 0UL; @@ -2381,7 +2409,7 @@ static void SMBUS_Enable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Inte * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. * @retval HAL status */ -static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) +static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) { uint32_t tmpisr = 0UL; uint32_t tmpstate = hsmbus->State; @@ -2453,7 +2481,7 @@ static void SMBUS_Disable_IRQ(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Int * @param hsmbus SMBUS handle. * @retval None */ -static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus) +static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) { uint32_t itflags = READ_REG(hsmbus->Instance->ISR); uint32_t itsources = READ_REG(hsmbus->Instance->CR1); @@ -2554,7 +2582,8 @@ static void SMBUS_ITErrorHandler(struct __SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, + uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2603,7 +2632,8 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(struct __SMBUS_HandleTypeD * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) { /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -2611,16 +2641,20 @@ static void SMBUS_TransferConfig(struct __SMBUS_HandleTypeDef *hsmbus, uint16_t assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); /* update CR2 register */ - MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + MODIFY_REG(hsmbus->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** - * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions. + * @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions. * @param hsmbus SMBUS handle. * @retval None */ -static void SMBUS_ConvertOtherXferOptions(struct __SMBUS_HandleTypeDef *hsmbus) +static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) { /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ /* it request implicitly to generate a restart condition */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smbus.h index e0b67da98e..704735ee0f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_smbus.h @@ -65,7 +65,7 @@ typedef struct uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected This parameter can be a value of @ref SMBUS_own_address2_masks. */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. @@ -132,7 +132,11 @@ typedef struct * @brief SMBUS handle Structure definition * @{ */ +#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) typedef struct __SMBUS_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ { I2C_TypeDef *Instance; /*!< SMBUS registers base address */ @@ -326,6 +330,7 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE +#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) @@ -353,7 +358,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE #define SMBUS_IT_RXI I2C_CR1_RXIE #define SMBUS_IT_TXI I2C_CR1_TXIE -#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) +#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | \ + SMBUS_IT_TXI) #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) @@ -403,10 +409,10 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) #endif @@ -457,7 +463,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SMBUS flag is set or not. * @param __HANDLE__ specifies the SMBUS Handle. @@ -483,7 +490,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @retval The new state of __FLAG__ (SET or RESET). */ #define SMBUS_FLAG_MASK (0x0001FFFFU) -#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) +#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ + (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the SMBUS Handle. @@ -534,15 +542,15 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t */ #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ - ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) + ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ - ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) + ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) + ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ ((MASK) == SMBUS_OA2_MASK01) || \ @@ -560,46 +568,49 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ - ((PEC) == SMBUS_PEC_ENABLE)) + ((PEC) == SMBUS_PEC_ENABLE)) -#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) +#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) -#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ - ((MODE) == SMBUS_AUTOEND_MODE) || \ - ((MODE) == SMBUS_SOFTEND_MODE) || \ - ((MODE) == SMBUS_SENDPEC_MODE) || \ - ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) +#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ + ((MODE) == SMBUS_AUTOEND_MODE) || \ + ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == SMBUS_SENDPEC_MODE) || \ + ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ - ((REQUEST) == SMBUS_GENERATE_START_READ) || \ - ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ - ((REQUEST) == SMBUS_NO_STARTSTOP)) + ((REQUEST) == SMBUS_GENERATE_START_READ) || \ + ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == SMBUS_NO_STARTSTOP)) #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ - ((REQUEST) == SMBUS_FIRST_FRAME) || \ - ((REQUEST) == SMBUS_NEXT_FRAME) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) + ((REQUEST) == SMBUS_FIRST_FRAME) || \ + ((REQUEST) == SMBUS_NEXT_FRAME) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) -#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) -#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ + (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) +#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) @@ -607,7 +618,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) -#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) +#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ + ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) @@ -623,8 +635,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t */ /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ + * @{ + */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); @@ -636,7 +648,8 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, + pSMBUS_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); @@ -647,28 +660,33 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ + * @{ + */ /* IO operation functions *****************************************************/ /** @addtogroup Blocking_mode_Polling Blocking mode Polling - * @{ - */ + * @{ + */ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); /** * @} */ /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt - * @{ - */ + * @{ + */ /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); -HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); @@ -679,8 +697,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); @@ -697,8 +715,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @{ - */ + * @{ + */ /* Peripheral State and Errors functions **************************************************/ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_spdifrx.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_spdifrx.c index 15c03ac3f9..036a9d9875 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_spdifrx.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_spdifrx.c @@ -93,7 +93,7 @@ The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use HAL_SPDIFRX_RegisterCallback() funtion to register an interrupt callback. + Use HAL_SPDIFRX_RegisterCallback() function to register an interrupt callback. The HAL_SPDIFRX_RegisterCallback() function allows to register the following callbacks: (+) RxHalfCpltCallback : SPDIFRX Data flow half completed callback. @@ -841,7 +841,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) { - register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); + uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; @@ -926,7 +926,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) { - register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); + uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; @@ -1011,7 +1011,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) { - register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); + uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; @@ -1112,7 +1112,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) { - register uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); + uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_spi.c index 2e14cea07e..684621c3ee 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_spi.c @@ -65,16 +65,16 @@ Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. Function HAL_SPI_RegisterCallback() allows to register following callbacks: - (+) TxCpltCallback : SPI Tx Completed callback - (+) RxCpltCallback : SPI Rx Completed callback - (+) TxRxCpltCallback : SPI TxRx Completed callback - (+) TxHalfCpltCallback : SPI Tx Half Completed callback - (+) RxHalfCpltCallback : SPI Rx Half Completed callback - (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback - (+) ErrorCallback : SPI Error callback - (+) AbortCpltCallback : SPI Abort callback - (+) MspInitCallback : SPI Msp Init callback - (+) MspDeInitCallback : SPI Msp DeInit callback + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. @@ -84,17 +84,18 @@ HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: - (+) TxCpltCallback : SPI Tx Completed callback - (+) RxCpltCallback : SPI Rx Completed callback - (+) TxRxCpltCallback : SPI TxRx Completed callback - (+) TxHalfCpltCallback : SPI Tx Half Completed callback - (+) RxHalfCpltCallback : SPI Rx Half Completed callback - (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback - (+) ErrorCallback : SPI Error callback - (+) AbortCpltCallback : SPI Abort callback - (+) MspInitCallback : SPI Msp Init callback - (+) MspDeInitCallback : SPI Msp DeInit callback + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + [..] By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET all callbacks are set to the corresponding weak functions: examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). @@ -104,6 +105,7 @@ If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, @@ -112,7 +114,8 @@ using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() or HAL_SPI_Init() function. - When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + [..] + When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available and weak (surcharged) callbacks are used. @@ -128,7 +131,7 @@ DataSize = SPI_DATASIZE_8BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Tranfert mode |---------------------|----------------------|----------------------| + | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | @@ -153,7 +156,7 @@ DataSize = SPI_DATASIZE_16BIT: +----------------------------------------------------------------------------------------------+ | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Tranfert mode |---------------------|----------------------|----------------------| + | Process | Transfer mode |---------------------|----------------------|----------------------| | | | Master | Slave | Master | Slave | Master | Slave | |==============================================================================================| | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | @@ -269,8 +272,8 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ */ /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -334,6 +337,24 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + } + } + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; } #if (USE_SPI_CRC != 0U) assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); @@ -397,44 +418,56 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; } - /* Align the CRC Length on the data size */ - if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) - { - /* CRC Length aligned on the data size : value set by default */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; - } - else - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; - } - } - /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ - WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | - hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | - hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation)); + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | + (hspi->Init.CLKPolarity & SPI_CR1_CPOL) | + (hspi->Init.CLKPhase & SPI_CR1_CPHA) | + (hspi->Init.NSS & SPI_CR1_SSM) | + (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); #if (USE_SPI_CRC != 0U) - /* Configure : CRC Length */ - if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + /*---------------------------- SPIx CRCL Configuration -------------------*/ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCL; + /* Align the CRC Length on the data size */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + /* CRC Length aligned on the data size : value set by default */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; + } + else + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; + } + } + + /* Configure : CRC Length */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL); + } } #endif /* USE_SPI_CRC */ /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ - WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode | - hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth); + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | + (hspi->Init.TIMode & SPI_CR2_FRF) | + (hspi->Init.NSSPMode & SPI_CR2_NSSP) | + (hspi->Init.DataSize & SPI_CR2_DS_Msk) | + (frxth & SPI_CR2_FRXTH))); #if (USE_SPI_CRC != 0U) /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ /* Configure : CRC Polynomial */ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk)); } #endif /* USE_SPI_CRC */ @@ -535,7 +568,8 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -745,8 +779,8 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca */ /** @defgroup SPI_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -831,6 +865,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -971,6 +1007,9 @@ error: */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; @@ -1038,6 +1077,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Configure communication direction: 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -1135,12 +1176,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) { @@ -1152,7 +1197,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 goto error; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } } @@ -1197,6 +1244,9 @@ error : HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; uint32_t tmp_mode; @@ -1438,12 +1488,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -1455,7 +1509,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD goto error; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } } @@ -1540,6 +1596,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -1631,6 +1689,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -1831,6 +1891,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_TX(hspi); } @@ -1872,7 +1934,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, } /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount)) + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); @@ -1960,6 +2023,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Configure communication direction : 1Line */ if (hspi->Init.Direction == SPI_DIRECTION_1LINE) { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); SPI_1LINE_RX(hspi); } @@ -2014,7 +2079,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u hspi->hdmarx->XferAbortCallback = NULL; /* Enable the Rx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); @@ -2181,7 +2247,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->hdmarx->XferAbortCallback = NULL; /* Enable the Rx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); @@ -2202,7 +2269,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->hdmatx->XferAbortCallback = NULL; /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount)) + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); @@ -2242,11 +2310,12 @@ error : * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode; - __IO uint32_t count, resetcount; + __IO uint32_t count; + __IO uint32_t resetcount; /* Initialized local variable */ errorcode = HAL_OK; @@ -2269,8 +2338,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) break; } count--; - } - while (hspi->State != HAL_SPI_STATE_ABORT); + } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ count = resetcount; } @@ -2287,8 +2355,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) break; } count--; - } - while (hspi->State != HAL_SPI_STATE_ABORT); + } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ count = resetcount; } @@ -2403,12 +2470,13 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode; uint32_t abortcplt ; - __IO uint32_t count, resetcount; + __IO uint32_t count; + __IO uint32_t resetcount; /* Initialized local variable */ errorcode = HAL_OK; @@ -2432,8 +2500,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) break; } count--; - } - while (hspi->State != HAL_SPI_STATE_ABORT); + } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ count = resetcount; } @@ -2450,8 +2517,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) break; } count--; - } - while (hspi->State != HAL_SPI_STATE_ABORT); + } while (hspi->State != HAL_SPI_STATE_ABORT); /* Reset Timeout Counter */ count = resetcount; } @@ -2667,7 +2733,8 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) } /* SPI in Error Treatment --------------------------------------------------*/ - if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) + if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) { /* SPI Overrun error interrupt occurred ----------------------------------*/ if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) @@ -2999,6 +3066,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3023,12 +3093,16 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -3038,14 +3112,25 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } } #endif /* USE_SPI_CRC */ - /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + /* Check if we are in Master RX 2 line mode */ + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + } + else + { + /* Normal case */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + } /* Check the end of the transaction */ if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) @@ -3094,6 +3179,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3117,7 +3205,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { @@ -3127,7 +3217,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } #endif /* USE_SPI_CRC */ @@ -3462,8 +3554,12 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - /* Read 8bit CRC to flush Data Regsiter */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + __IO uint32_t tmpreg = 0U; + + /* Read 8bit CRC to flush Data Register */ + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); hspi->CRCSize--; @@ -3570,8 +3666,12 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { - /* Read 16bit CRC to flush Data Regsiter */ - READ_REG(hspi->Instance->DR); + __IO uint32_t tmpreg = 0U; + + /* Read 16bit CRC to flush Data Register */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); @@ -3626,8 +3726,12 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 8bit CRC to flush Data Register */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); hspi->CRCSize--; @@ -3680,8 +3784,12 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 16bit CRC to flush Data Register */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); @@ -3787,69 +3895,22 @@ static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, uint32_t Timeout, uint32_t Tickstart) { + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) { if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) - { - /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ - - /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) - || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - hspi->State = HAL_SPI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - -/** - * @brief Handle SPI FIFO Communication Timeout. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Fifo Fifo to check - * @param State Fifo state to check - * @param Timeout Timeout duration - * @param Tickstart tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, - uint32_t Timeout, uint32_t Tickstart) -{ - while ((hspi->Instance->SR & Fifo) != State) - { - if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) - { - /* Read 8bit CRC to flush Data Register */ - READ_REG(*((__IO uint8_t *)&hspi->Instance->DR)); - } - - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -3878,6 +3939,90 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, return HAL_TIMEOUT; } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if(count == 0U) + { + tmp_timeout = 0U; + } + count--; + } + } + + return HAL_OK; +} + +/** + * @brief Handle SPI FIFO Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Fifo Fifo to check + * @param State Fifo state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart) +{ + __IO uint32_t tmpreg; + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); + + while ((hspi->Instance->SR & Fifo) != State) + { + if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) + { + /* Flush Data Register by a blank read */ + tmpreg = READ_REG(*((__IO uint8_t *)&hspi->Instance->DR)); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if(count == 0U) + { + tmp_timeout = 0U; + } + count--; } } @@ -3964,7 +4109,7 @@ static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) { uint32_t tickstart; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Disable ERR interrupt */ @@ -4164,8 +4309,7 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) break; } count--; - } - while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) @@ -4206,8 +4350,7 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) break; } count--; - } - while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) { @@ -4238,8 +4381,7 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) break; } count--; - } - while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); /* Control the BSY flag */ if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_spi.h index 4d5be75d88..296481abcd 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_spi.h @@ -383,7 +383,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ -#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) +#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ + | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) /** * @} */ @@ -433,7 +434,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) -#endif +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** @brief Enable the specified SPI interrupts. * @param __HANDLE__ specifies the SPI Handle. @@ -469,7 +470,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_IT_ERR: Error interrupt enable * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. * @param __HANDLE__ specifies the SPI Handle. @@ -529,9 +531,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ do{ \ - __IO uint32_t tmpreg_fre = 0x00U; \ - tmpreg_fre = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg_fre); \ + __IO uint32_t tmpreg_fre = 0x00U; \ + tmpreg_fre = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_fre); \ }while(0U) /** @brief Enable the SPI peripheral. @@ -580,7 +582,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) /** @brief Check whether the specified SPI flag is set or not. - * @param __SR__ copy of SPI SR regsiter. + * @param __SR__ copy of SPI SR register. * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag @@ -594,10 +596,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_FLAG_FRLVL: SPI fifo reception level * @retval SET or RESET. */ -#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. - * @param __CR2__ copy of SPI CR2 regsiter. + * @param __CR2__ copy of SPI CR2 register. * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable @@ -605,15 +608,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @arg SPI_IT_ERR: Error interrupt enable * @retval SET or RESET. */ -#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. * This parameter can be a value of @ref SPI_Mode * @retval None */ -#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ - ((__MODE__) == SPI_MODE_MASTER)) +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) /** @brief Checks if SPI Direction Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Direction Mode. @@ -661,33 +665,33 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_Clock_Polarity * @retval None */ -#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ - ((__CPOL__) == SPI_POLARITY_HIGH)) +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) /** @brief Checks if SPI Clock Phase parameter is in allowed range. * @param __CPHA__ specifies the SPI Clock Phase. * This parameter can be a value of @ref SPI_Clock_Phase * @retval None */ -#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ - ((__CPHA__) == SPI_PHASE_2EDGE)) +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) /** @brief Checks if SPI Slave Select parameter is in allowed range. * @param __NSS__ specifies the SPI Slave Select management parameter. * This parameter can be a value of @ref SPI_Slave_Select_management * @retval None */ -#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ - ((__NSS__) == SPI_NSS_HARD_INPUT) || \ - ((__NSS__) == SPI_NSS_HARD_OUTPUT)) +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) /** @brief Checks if SPI NSS Pulse parameter is in allowed range. * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. * This parameter can be a value of @ref SPI_NSSP_Mode * @retval None */ -#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ - ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) +#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ + ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. * @param __PRESCALER__ specifies the SPI Baudrate prescaler. @@ -708,16 +712,16 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_MSB_LSB_transmission * @retval None */ -#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ - ((__BIT__) == SPI_FIRSTBIT_LSB)) +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) /** @brief Checks if SPI TI mode parameter is in allowed range. * @param __MODE__ specifies the SPI TI mode. * This parameter can be a value of @ref SPI_TI_mode * @retval None */ -#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ - ((__MODE__) == SPI_TIMODE_ENABLE)) +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) /** @brief Checks if SPI CRC calculation enabled state is in allowed range. * @param __CALCULATION__ specifies the SPI CRC calculation enable state. @@ -732,8 +736,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be a value of @ref SPI_CRC_length * @retval None */ -#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\ - ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ +#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. @@ -741,7 +745,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 * @retval None */ -#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ + ((__POLYNOMIAL__) <= 0xFFFFU) && \ + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim.c index b3365d6fb3..2496dd6563 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim.c @@ -199,7 +199,7 @@ all interrupt callbacks are set to the corresponding weak functions: /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @addtogroup TIM_Private_Functions @@ -221,6 +221,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, @@ -306,6 +307,13 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -339,6 +347,13 @@ HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Base_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -391,19 +406,29 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } - /* Change the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -418,13 +443,10 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the TIM state*/ + /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -443,12 +465,28 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -466,12 +504,16 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + /* Return function status */ return HAL_OK; } @@ -490,6 +532,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + /* Set the TIM state */ if (htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; @@ -507,7 +550,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat } else { - /* nothing to do */ + return HAL_ERROR; } /* Set the DMA Period elapsed callbacks */ @@ -520,6 +563,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -527,8 +571,15 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -555,7 +606,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ + /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -638,6 +689,13 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the Output Compare */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -671,6 +729,13 @@ HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -730,6 +795,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -740,8 +814,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -780,6 +861,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -802,6 +886,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -846,8 +939,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -918,6 +1018,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -942,11 +1045,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -954,12 +1058,12 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -976,6 +1080,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -996,6 +1101,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1016,6 +1122,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1035,6 +1142,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1056,8 +1164,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1132,8 +1247,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1215,6 +1330,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -1248,6 +1370,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_PWM_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1307,6 +1436,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -1317,8 +1455,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1357,8 +1502,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1381,6 +1526,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1425,8 +1579,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1497,6 +1658,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1521,11 +1685,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { if ((pData == NULL) && (Length > 0U)) { @@ -1533,12 +1698,12 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -1555,6 +1720,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1575,6 +1741,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1594,6 +1761,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Capture/Compare 3 request */ @@ -1613,6 +1781,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1634,8 +1803,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1710,8 +1886,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1793,6 +1969,13 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) /* Init the base time for the input capture */ TIM_Base_SetConfig(htim->Instance, &htim->Init); + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -1826,6 +2009,13 @@ HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_IC_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -1879,16 +2069,36 @@ __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1919,6 +2129,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1937,10 +2151,23 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1978,8 +2205,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -2044,6 +2278,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2064,16 +2302,21 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { @@ -2081,12 +2324,30 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); } switch (Channel) @@ -2103,6 +2364,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -2122,6 +2384,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -2141,6 +2404,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -2160,6 +2424,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -2171,16 +2436,6 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - /* Return function status */ return HAL_OK; } @@ -2202,6 +2457,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + switch (Channel) { case TIM_CHANNEL_1: @@ -2240,14 +2498,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) break; } - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -2284,6 +2540,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) * requires a timer reset to avoid unexpected direction * due to DIR bit readonly in center aligned mode. * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. * @param htim TIM One Pulse handle * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: @@ -2339,6 +2598,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul /* Configure the OPM Mode */ htim->Instance->CR1 |= OnePulseMode; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -2372,6 +2640,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_OnePulse_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2413,23 +2690,44 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2449,11 +2747,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2465,7 +2764,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2479,29 +2778,56 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Prevent unused argument(s) compilation warning */ UNUSED(OutputChannel); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2527,11 +2853,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2549,7 +2876,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2562,6 +2889,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -2600,6 +2933,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status @@ -2697,6 +3033,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -2731,6 +3076,15 @@ HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) HAL_TIM_Encoder_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -2782,9 +3136,59 @@ __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + /* Enable the encoder interface channels */ switch (Channel) { @@ -2856,6 +3260,20 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + /* Return function status */ return HAL_OK; } @@ -2872,9 +3290,59 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + /* Enable the encoder interface channels */ /* Enable the capture compare Interrupts 1 and/or 2 */ switch (Channel) @@ -2954,8 +3422,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ return HAL_OK; @@ -2977,27 +3456,95 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) { + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) { - return HAL_BUSY; - } - else if (htim->State == HAL_TIM_STATE_READY) - { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { - return HAL_ERROR; + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } } else { - htim->State = HAL_TIM_STATE_BUSY; + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; } } else { - /* nothing to do */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } } switch (Channel) @@ -3014,6 +3561,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3038,6 +3586,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3063,6 +3612,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -3076,6 +3626,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the Peripheral */ @@ -3095,6 +3646,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch default: break; } + /* Return function status */ return HAL_OK; } @@ -3147,8 +3699,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ return HAL_OK; @@ -3417,8 +3980,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - switch (Channel) { case TIM_CHANNEL_1: @@ -3485,8 +4046,6 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, break; } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3517,8 +4076,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - if (Channel == TIM_CHANNEL_1) { /* TI1 Configuration */ @@ -3582,8 +4139,6 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3617,8 +4172,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, /* Process Locked */ __HAL_LOCK(htim); - htim->State = HAL_TIM_STATE_BUSY; - switch (Channel) { case TIM_CHANNEL_1: @@ -3727,8 +4280,6 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, break; } - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); return HAL_OK; @@ -3899,20 +4450,75 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @note This function should be used only when BurstLength is equal to DMA data transfer length. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, - uint32_t *BurstBuffer, uint32_t BurstLength) +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 (*) + * @arg TIM_DMABASE_AF2 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - if (htim->State == HAL_TIM_STATE_BUSY) + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -3920,7 +4526,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t } else { - htim->State = HAL_TIM_STATE_BUSY; + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else @@ -3939,8 +4545,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3956,8 +4564,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3973,8 +4582,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -3990,8 +4600,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4007,8 +4618,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4024,8 +4636,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4041,8 +4654,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4050,14 +4664,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t default: break; } - /* configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -4070,7 +4682,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { - HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4079,51 +4690,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B { case TIM_DMA_UPDATE: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -4173,18 +4784,73 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 (*) + * @arg TIM_DMABASE_AF2 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - if (htim->State == HAL_TIM_STATE_BUSY) + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) { if ((BurstBuffer == NULL) && (BurstLength > 0U)) { @@ -4192,7 +4858,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B } else { - htim->State = HAL_TIM_STATE_BUSY; + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; } } else @@ -4211,8 +4877,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4227,15 +4895,17 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; } case TIM_DMA_CC2: { - /* Set the DMA capture/compare callbacks */ + /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; @@ -4243,8 +4913,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4259,8 +4931,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4275,8 +4949,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4291,8 +4967,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4307,8 +4985,10 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4317,14 +4997,12 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B break; } - /* configure the DMA Burst Mode */ + /* Configure the DMA Burst Mode */ htim->Instance->DCR = (BurstBaseAddress | BurstLength); /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - htim->State = HAL_TIM_STATE_READY; - /* Return function status */ return HAL_OK; } @@ -4337,7 +5015,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { - HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4346,51 +5023,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu { case TIM_DMA_UPDATE: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -4727,13 +5404,13 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_ITR1: case TIM_CLOCKSOURCE_ITR2: case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } default: break; @@ -5673,6 +6350,54 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) return htim->State; } +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + /** * @} */ @@ -5694,13 +6419,38 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** @@ -5708,27 +6458,45 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) * @param hdma pointer to DMA handle. * @retval None */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } } else { @@ -5753,8 +6521,6 @@ void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -5794,23 +6560,45 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } } else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } } else { @@ -5835,8 +6623,6 @@ void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; @@ -5876,7 +6662,10 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); @@ -5894,8 +6683,6 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedHalfCpltCallback(htim); #else @@ -5912,7 +6699,10 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); @@ -5930,8 +6720,6 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - htim->State = HAL_TIM_STATE_READY; - #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerHalfCpltCallback(htim); #else @@ -5990,7 +6778,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Timer Output Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6065,7 +6853,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6141,7 +6929,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6215,7 +7003,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6275,7 +7063,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 5 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, @@ -6328,7 +7116,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, /** * @brief Timer Output Compare 6 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, @@ -6432,7 +7220,7 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) { return HAL_ERROR; } @@ -6484,11 +7272,11 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, case TIM_TS_ITR1: case TIM_TS_ITR2: case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - break; - } + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } default: break; diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim.h index c77e99c3d1..4934e62a2c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim.h @@ -304,6 +304,26 @@ typedef enum HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ } HAL_TIM_StateTypeDef; +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + /** * @brief HAL Active channel structures definition */ @@ -327,13 +347,16 @@ typedef struct __TIM_HandleTypeDef typedef struct #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ { - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ @@ -373,35 +396,35 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ - ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ - ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ - ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ - ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ - ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ - ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ - ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ - ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ - ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ } HAL_TIM_CallbackIDTypeDef; /** @@ -879,7 +902,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ /** * @} @@ -1028,24 +1051,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ @@ -1101,25 +1124,49 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @retval None */ #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->Base_MspInitCallback = NULL; \ - (__HANDLE__)->Base_MspDeInitCallback = NULL; \ - (__HANDLE__)->IC_MspInitCallback = NULL; \ - (__HANDLE__)->IC_MspDeInitCallback = NULL; \ - (__HANDLE__)->OC_MspInitCallback = NULL; \ - (__HANDLE__)->OC_MspDeInitCallback = NULL; \ - (__HANDLE__)->PWM_MspInitCallback = NULL; \ - (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ } while(0) #else -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ /** @@ -1946,15 +1993,15 @@ mode. #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ @@ -1965,6 +2012,8 @@ mode. ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) @@ -2001,6 +2050,50 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) + /** * @} */ @@ -2172,9 +2265,15 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, + uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); @@ -2220,6 +2319,11 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** * @} */ @@ -2239,7 +2343,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); void TIM_DMAError(DMA_HandleTypeDef *hdma); void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim_ex.c index 7dd91df446..a5ae918780 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim_ex.c @@ -55,7 +55,7 @@ the commutation event). (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT() + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). @@ -91,9 +91,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); /* Exported functions --------------------------------------------------------*/ @@ -124,6 +126,9 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha */ /** * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. * @param htim TIM Hall Sensor Interface handle * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status @@ -209,6 +214,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSen htim->Instance->CR2 &= ~TIM_CR2_MMS; htim->Instance->CR2 |= TIM_TRGO_OC2REF; + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; @@ -242,6 +256,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) HAL_TIMEx_HallSensor_MspDeInit(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; @@ -289,17 +312,43 @@ __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -325,6 +374,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -337,10 +392,29 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the capture compare Interrupts 1 event */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -349,8 +423,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -379,6 +460,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -393,29 +480,36 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); /* Check the parameters */ assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } + /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -429,14 +523,22 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Enable the DMA stream for Capture 1*/ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the capture compare 1 Interrupt */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -464,9 +566,14 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -513,6 +620,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the Capture compare channel N */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -520,8 +636,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -555,6 +678,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -577,6 +703,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -615,8 +750,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -685,6 +827,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -709,24 +854,25 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } switch (Channel) @@ -734,15 +880,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -753,15 +900,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -772,15 +920,16 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -799,8 +948,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -864,8 +1020,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -922,6 +1078,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the complementary PWM output */ TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); @@ -929,8 +1094,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -963,6 +1135,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -985,6 +1160,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + switch (Channel) { case TIM_CHANNEL_1: @@ -1022,8 +1206,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1093,6 +1284,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1117,39 +1311,42 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - if (htim->State == HAL_TIM_STATE_BUSY) + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) { return HAL_BUSY; } - else if (htim->State == HAL_TIM_STATE_READY) + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) { - if (((uint32_t)pData == 0U) && (Length > 0U)) + if ((pData == NULL) && (Length > 0U)) { return HAL_ERROR; } else { - htim->State = HAL_TIM_STATE_BUSY; + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); } } else { - /* nothing to do */ + return HAL_ERROR; } + switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -1160,15 +1357,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_2: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1179,15 +1377,16 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha case TIM_CHANNEL_3: { /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1206,8 +1405,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1271,8 +1477,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1303,8 +1509,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1312,11 +1520,33 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - /* Enable the complementary One Pulse output */ + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1328,8 +1558,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1337,12 +1569,14 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - /* Disable the complementary One Pulse output */ + /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1350,6 +1584,12 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1357,8 +1597,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1366,17 +1608,39 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - /* Enable the complementary One Pulse output */ + /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); /* Enable the Main Output */ __HAL_TIM_MOE_ENABLE(htim); @@ -1388,8 +1652,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1397,6 +1663,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t */ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); @@ -1406,8 +1674,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - /* Disable the complementary One Pulse output */ + /* Disable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); /* Disable the Main Output */ __HAL_TIM_MOE_DISABLE(htim); @@ -1415,6 +1684,12 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + /* Return function status */ return HAL_OK; } @@ -1839,10 +2114,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, #if defined(DFSDM1_Channel0) if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) #endif /* DFSDM1_Channel0 */ - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } /* Set TIMx_AF1 */ htim->Instance->AF1 = tmporx; @@ -1861,10 +2136,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, #if defined(DFSDM1_Channel0) if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) #endif /* DFSDM1_Channel0 */ - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } /* Set TIMx_AF2 */ htim->Instance->AF2 = tmporx; @@ -2062,6 +2337,27 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) return htim->State; } +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} /** * @} */ @@ -2114,6 +2410,103 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) } +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim_ex.h index 2897aca4d7..f0944ab79f 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_tim_ex.h @@ -119,8 +119,8 @@ TIMEx_BreakInputConfigTypeDef; /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source * @{ */ -#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */ -#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_BKIN (0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_DFSDM1 (0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ /** * @} */ @@ -323,6 +323,7 @@ void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); */ /* Extended Peripheral State functions ***************************************/ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart.c index 0e557de5e6..5498ce7e5d 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart.c @@ -39,7 +39,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. @@ -86,8 +87,6 @@ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. (+) WakeupCallback : Wakeup Callback. - (+) RxFifoFullCallback : Rx Fifo Full Callback. - (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. (+) MspInitCallback : UART MspInit. (+) MspDeInitCallback : UART MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID @@ -108,11 +107,13 @@ (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. (+) WakeupCallback : Wakeup Callback. - (+) RxFifoFullCallback : Rx Fifo Full Callback. - (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. (+) MspInitCallback : UART MspInit. (+) MspDeInitCallback : UART MspDeInit. + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback(). + [..] By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: @@ -172,15 +173,15 @@ /** @defgroup UART_Private_Constants UART Private Constants * @{ */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE |\ + USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ #define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ #define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ - /** * @} */ @@ -212,6 +213,7 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); * @} */ + /* Exported functions --------------------------------------------------------*/ /** @defgroup UART_Exported_Functions UART Exported Functions @@ -635,6 +637,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; __HAL_UNLOCK(huart); @@ -687,8 +690,6 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID - * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID - * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID * @param pCallback pointer to the Callback function @@ -744,10 +745,14 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ huart->AbortReceiveCpltCallback = pCallback; break; +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) case HAL_UART_WAKEUP_CB_ID : huart->WakeupCallback = pCallback; break; +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ case HAL_UART_MSPINIT_CB_ID : huart->MspInitCallback = pCallback; @@ -810,8 +815,6 @@ HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_ * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID - * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID - * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID * @retval HAL status @@ -827,49 +830,53 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR switch (CallbackID) { case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ break; case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) case HAL_UART_WAKEUP_CB_ID : - huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ break; +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -909,6 +916,74 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR return status; } + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + return status; +} + #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** @@ -973,6 +1048,10 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR (+) HAL_UART_AbortCpltCallback() (+) HAL_UART_AbortTransmitCpltCallback() (+) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: + (+) HAL_UARTEx_RxEventCallback() #if defined(USART_CR1_UESM) (#) Wakeup from Stop mode Callback: @@ -982,13 +1061,16 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. If user wants to abort it, Abort services should be called by user. (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -1027,7 +1109,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); huart->TxXferSize = Size; @@ -1112,8 +1194,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); huart->RxXferSize = Size; @@ -1243,36 +1326,17 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, __HAL_LOCK(huart); - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = Size; - huart->RxISR = NULL; + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) { - huart->RxISR = UART_RxISR_16BIT; - } - else - { - huart->RxISR = UART_RxISR_8BIT; + /* Enable the UART Receiver Timeout Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); - - return HAL_OK; + return (UART_Start_Receive_IT(huart, pData, Size)); } else { @@ -1378,53 +1442,17 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData __HAL_LOCK(huart); - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - if (huart->hdmarx != NULL) + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) { - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - __HAL_UNLOCK(huart); - - /* Restore huart->gState to ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_ERROR; - } + /* Enable the UART Receiver Timeout Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; + return (UART_Start_Receive_DMA(huart, pData, Size)); } else { @@ -1485,7 +1513,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) /* Clear the Overrun flag before resuming the Rx transfer */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); SET_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -1584,6 +1612,12 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { @@ -1648,6 +1682,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1724,6 +1759,12 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { @@ -1760,6 +1801,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; return HAL_OK; } @@ -1786,6 +1828,12 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ @@ -1889,6 +1937,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* As no DMA to be aborted, call directly user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -2007,6 +2056,12 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { @@ -2042,6 +2097,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* As no DMA to be aborted, call directly user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -2066,6 +2122,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* As no DMA to be aborted, call directly user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -2113,7 +2170,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* If some errors occur */ if ((errorflags != 0U) && (((cr3its & USART_CR3_EIE) != 0U) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))) { /* UART parity error interrupt occurred -------------------------------------*/ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) @@ -2245,7 +2302,95 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) return; } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + } + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + } + } #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) @@ -2264,6 +2409,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ return; } +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ /* UART in mode Transmitter ------------------------------------------------*/ @@ -2406,6 +2552,24 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) */ } +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + #if defined(USART_CR1_UESM) /** * @brief UART wakeup from Stop mode callback. @@ -2726,8 +2890,11 @@ void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ } #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -2742,7 +2909,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; - uint32_t usartdiv = 0x00000000U; + uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; uint32_t pclk; @@ -2793,37 +2960,39 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); + pclk = (uint32_t) HSI_VALUE; break; case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); + pclk = (uint32_t) LSE_VALUE; break; default: + pclk = 0U; ret = HAL_ERROR; break; } /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + if (pclk != 0U) { - brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - huart->Instance->BRR = brrtemp; - } - else - { - ret = HAL_ERROR; + usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } } } else @@ -2832,35 +3001,37 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_HSI: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); + pclk = (uint32_t) HSI_VALUE; break; case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); + pclk = (uint32_t) LSE_VALUE; break; default: + pclk = 0U; ret = HAL_ERROR; break; } - /* USARTDIV must be greater than or equal to 0d16 */ - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + if (pclk != 0U) { - huart->Instance->BRR = usartdiv; - } - else - { - ret = HAL_ERROR; + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } } } @@ -2958,7 +3129,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ @@ -2988,6 +3159,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; __HAL_UNLOCK(huart); @@ -3014,7 +3186,8 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3032,18 +3205,19 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; huart->ErrorCode = HAL_UART_ERROR_RTO; - + /* Process Unlocked */ __HAL_UNLOCK(huart); - + return HAL_TIMEOUT; } } @@ -3052,6 +3226,112 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ return HAL_OK; } +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + return HAL_OK; +} + +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + /** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). @@ -3079,8 +3359,15 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Reset RxIsr function pointer */ huart->RxISR = NULL; @@ -3163,15 +3450,37 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } } + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } /** @@ -3183,13 +3492,29 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Half complete callback*/ - huart->RxHalfCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else - /*Call legacy weak Rx Half complete callback*/ - HAL_UART_RxHalfCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } /** @@ -3289,6 +3614,7 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Call user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -3340,6 +3666,7 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Call user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -3402,6 +3729,7 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Call user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -3414,7 +3742,7 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) } /** - * @brief TX interrrupt handler for 7 or 8 bits data word length . + * @brief TX interrupt handler for 7 or 8 bits data word length . * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3443,7 +3771,7 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) } /** - * @brief TX interrrupt handler for 9 bits data word length. + * @brief TX interrupt handler for 9 bits data word length. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3502,7 +3830,7 @@ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 7 or 8 bits data word length . + * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ @@ -3533,13 +3861,33 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } else @@ -3550,7 +3898,7 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 9 bits data word length . + * @brief RX interrupt handler for 9 bits data word length . * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. @@ -3585,13 +3933,33 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } else diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart.h index eb186d6f5e..6341d32dd6 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart.h @@ -46,42 +46,45 @@ extern "C" { */ typedef struct { - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate register is computed using the following formula: - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[3:0]) >> 1 - where uart_ker_ck is the UART input clock */ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ck) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ck) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck is the UART input clock */ - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length. */ + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits. */ + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode. */ + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. */ + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ - uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ } UART_InitTypeDef; @@ -93,7 +96,8 @@ typedef struct { uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . - This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. This parameter can be a value of @ref UART_Tx_Inv. */ @@ -127,7 +131,8 @@ typedef struct /** * @brief HAL UART State definition - * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition). + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). * - gState contains UART state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -138,7 +143,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -155,7 +160,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -179,6 +184,17 @@ typedef enum UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ } UART_ClockSourceTypeDef; +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * It is expected to admit following values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + /** * @brief UART handle Structure definition */ @@ -204,6 +220,8 @@ typedef struct __UART_HandleTypeDef uint16_t Mask; /*!< UART Rx RDR register mask */ + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ @@ -215,11 +233,11 @@ typedef struct __UART_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ __IO uint32_t ErrorCode; /*!< UART Error code */ @@ -232,7 +250,12 @@ typedef struct __UART_HandleTypeDef void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ @@ -264,7 +287,9 @@ typedef enum /** * @brief HAL UART Callback pointer definition */ -typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -291,8 +316,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing Value is allowed for RxState only */ #define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ #define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state Value is allowed for gState only */ #define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error @@ -304,16 +329,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_Error_Definition UART Error Definition * @{ */ -#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ -#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -391,10 +416,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ /** * @} */ @@ -556,8 +585,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ -#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ /** * @} */ @@ -585,7 +616,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register * @{ */ -#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ /** * @} */ @@ -594,9 +625,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection * @{ */ -#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ -#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ -#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */ +#if defined(USART_CR3_WUS) +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ +#else +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY 0x00000001U /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ +#endif /* USART_CR3_WUS */ /** * @} */ @@ -614,7 +652,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ /** * @} */ @@ -622,7 +661,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ /** * @} */ @@ -653,7 +693,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #endif /* USART_ISR_REACK */ #define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) #define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ #define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ #define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ @@ -695,24 +737,26 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ -#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ -#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ -#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ -#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ -#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ -#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ -#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ -#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ #if defined(USART_CR1_UESM) -#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#if defined(USART_CR3_WUFIE) +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ -#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ -#define UART_IT_ERR 0x0060U /*!< UART error interruption */ +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ -#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ -#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ -#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ /** * @} */ @@ -730,13 +774,25 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ #define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ /** * @} */ +/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ /** * @} @@ -790,7 +846,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag * @arg @ref UART_CLEAR_CMF Character Match Clear Flag #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag +#endif #endif * @retval None */ @@ -835,9 +893,11 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag #endif * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag - #if defined(USART_CR1_UESM) +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) * @arg @ref UART_FLAG_WUF Wake up from stop mode flag - #endif +#endif +#endif * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) * @arg @ref UART_FLAG_SBKF Send Break flag * @arg @ref UART_FLAG_CMF Character match flag @@ -864,7 +924,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __INTERRUPT__ specifies the UART interrupt source to enable. * This parameter can be one of the following values: #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif #endif * @arg @ref UART_IT_CM Character match interrupt * @arg @ref UART_IT_CTS CTS change interrupt @@ -878,17 +940,24 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) - +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Disable the specified UART interrupt. * @param __HANDLE__ specifies the UART Handle. * @param __INTERRUPT__ specifies the UART interrupt source to disable. * This parameter can be one of the following values: #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif #endif * @arg @ref UART_IT_CM Character match interrupt * @arg @ref UART_IT_CTS CTS change interrupt @@ -902,16 +971,24 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Check whether the specified UART interrupt has occurred or not. * @param __HANDLE__ specifies the UART Handle. * @param __INTERRUPT__ specifies the UART interrupt to check. * This parameter can be one of the following values: #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif #endif * @arg @ref UART_IT_CM Character match interrupt * @arg @ref UART_IT_CTS CTS change interrupt @@ -933,7 +1010,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __INTERRUPT__ specifies the UART interrupt source to check. * This parameter can be one of the following values: #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif #endif * @arg @ref UART_IT_CM Character match interrupt * @arg @ref UART_IT_CTS CTS change interrupt @@ -947,9 +1026,13 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the UART Handle. @@ -966,8 +1049,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag * @arg @ref UART_CLEAR_CMF Character Match Clear Flag - #if defined(USART_CR1_UESM) +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag +#endif #endif * @retval None */ @@ -1017,8 +1102,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1035,8 +1121,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1053,8 +1140,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1071,8 +1159,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1332,8 +1421,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __AUTOBAUDRATE__ UART auto Baud rate state. * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ - ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. @@ -1375,9 +1465,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __WAKE__ UART wake-up selection. * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) */ +#if defined(USART_CR3_WUFIE) #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) +#else +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ /** @@ -1396,7 +1491,6 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /* Include UART HAL Extended module */ #include "stm32f7xx_hal_uart_ex.h" - /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ @@ -1420,6 +1514,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** @@ -1458,6 +1555,8 @@ void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + /** * @} */ @@ -1503,13 +1602,15 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); * @{ */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart_ex.c index cdc535c511..75654e64cc 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart_ex.c @@ -248,6 +248,41 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, (+) HAL_UARTEx_DisableStopMode() API disables the above functionality #endif + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (+) Detection of inactivity period (RX line has not been active for a given period). + (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (+) Detection that a specific character has been received. + + (#) There are two mode of transfer: + (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (+) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (+) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (+) HAL_UARTEx_ReceiveToIdle_DMA() + @endverbatim * @{ */ @@ -366,8 +401,10 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); +#if defined(USART_CR3_WUS) /* Set the wake-up selection scheme */ MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); +#endif /* USART_CR3_WUS */ if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) { @@ -377,7 +414,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Wait until REACK flag is set */ @@ -437,6 +474,255 @@ HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) } #endif /* USART_CR1_UESM */ +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + status = UART_Start_Receive_IT(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart_ex.h index e99d8d6846..6e6b0906e2 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_uart_ex.h @@ -117,7 +117,6 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); #endif /* USART_CR1_UESM */ - /** * @} */ @@ -141,6 +140,12 @@ HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_usart.c index 92f27abb68..1fc591eb38 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_usart.c @@ -39,7 +39,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode (Receiver/Transmitter) in the husart handle Init structure. @@ -510,9 +511,9 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US } /** - * @brief Unregister an UART Callback - * UART callaback is redirected to the weak predefined callback - * @param husart uart handle + * @brief Unregister an USART Callback + * USART callaback is redirected to the weak predefined callback + * @param husart usart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID @@ -538,40 +539,40 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ switch (CallbackID) { case HAL_USART_TX_HALFCOMPLETE_CB_ID : - husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_USART_TX_COMPLETE_CB_ID : - husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_USART_RX_HALFCOMPLETE_CB_ID : - husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_USART_RX_COMPLETE_CB_ID : - husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_USART_TX_RX_COMPLETE_CB_ID : - husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ break; case HAL_USART_ERROR_CB_ID : - husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_USART_ABORT_COMPLETE_CB_ID : - husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_USART_MSPINIT_CB_ID : - husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ + husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_USART_MSPDEINIT_CB_ID : - husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ + husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -690,13 +691,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side. + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify + error type, and HAL_USART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on USART side. If user wants to abort it, Abort services should be called by user. (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed. + Error code is set to allow user to identify error type, + and HAL_USART_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -704,7 +708,7 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ /** * @brief Simplex send an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart USART handle. @@ -732,7 +736,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); husart->TxXferSize = Size; @@ -801,7 +805,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Receive an amount of data in blocking mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart USART handle. @@ -830,7 +834,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); husart->RxXferSize = Size; @@ -905,7 +909,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /** * @brief Full-Duplex Send and Receive an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart USART handle. @@ -939,7 +943,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); husart->RxXferSize = Size; @@ -1054,7 +1058,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t /** * @brief Send an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart USART handle. @@ -1117,7 +1121,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /** * @brief Receive an amount of data in interrupt mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart USART handle. @@ -1187,7 +1191,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /** * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart USART handle. @@ -1258,7 +1262,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /** * @brief Send an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart USART handle. @@ -1343,7 +1347,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p * @note When the USART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart USART handle. @@ -1457,7 +1461,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /** * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart USART handle. @@ -1648,7 +1652,7 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -2763,7 +2767,7 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) /* Initialize the USART ErrorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_usart.h index 4707dfd80b..9e90feec73 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_usart.h @@ -48,11 +48,14 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. The baud rate is computed using the following formula: - Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[15:4] = ((2 * fclk_pres) / + ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 + Baud Rate Register[2:0] = (((2 * fclk_pres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 where fclk_pres is the USART input clock frequency - @note Oversampling by 8 is systematically applied to achieve high baud rates. */ + @note Oversampling by 8 is systematically applied to + achieve high baud rates. */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USARTEx_Word_Length. */ @@ -200,16 +203,16 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin /** @defgroup USART_Error_Definition USART Error Definition * @{ */ -#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ -#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ +#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ -#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */ +#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */ /** * @} */ @@ -245,15 +248,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @} */ -/** @defgroup USART_Over_Sampling USART Over Sampling - * @{ - */ -#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - /** @defgroup USART_Clock USART Clock * @{ */ @@ -474,9 +468,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -490,10 +487,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) - +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. @@ -510,7 +509,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) + & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ + USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__ specifies the USART Handle. @@ -526,10 +526,13 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) - +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + USART_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the USART Handle. @@ -728,14 +731,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) -/** - * @brief Ensure that USART oversampling is valid. - * @param __SAMPLING__ USART oversampling. - * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ -#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == USART_OVERSAMPLING_8)) - /** * @brief Ensure that USART clock state is valid. * @param __CLOCK__ USART clock state. diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_usart_ex.h index 47abbf4dd4..d1eeb8584b 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_usart_ex.h @@ -45,9 +45,9 @@ extern "C" { /** @defgroup USARTEx_Word_Length USARTEx Word Length * @{ */ -#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ #define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ +#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_wwdg.c index 82af5e2ed7..4f3a9855d5 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_wwdg.c @@ -21,6 +21,13 @@ before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window. (+) Once enabled the WWDG cannot be disabled except by a system reset. + (+) If required by application, an Early Wakeup Interrupt can be triggered + in order to be warned before WWDG expiration. The Early Wakeup Interrupt + (EWI) can be used if specific safety operations or data logging must + be performed before the actual reset is generated. When the downcounter + reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt + line to be enabled in NVIC. Once enabled, EWI interrupt cannot be + disabled except by a system reset. (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG reset occurs. (+) The WWDG counter input clock is derived from the APB clock divided @@ -32,12 +39,12 @@ (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock (+) Typical values: - (++) Counter min (T[5;0] = 0x00) @54MHz (PCLK1) with zero prescaler: + (++) Counter min (T[5;0] = 0x00) at 54MHz (PCLK1) with zero prescaler: max timeout before reset: approximately 75.85µs - (++) Counter max (T[5;0] = 0x3F) @54MHz (PCLK1) with prescaler dividing by 8: + (++) Counter max (T[5;0] = 0x3F) at 54MHz (PCLK1) with prescaler + dividing by 8: max timeout before reset: approximately 38.83ms - ============================================================================== ##### How to use this driver ##### ============================================================================== @@ -46,16 +53,16 @@ [..] (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). - (+) Set the WWDG prescaler, refresh window and counter value - using HAL_WWDG_Init() function. - (+) Start the WWDG using HAL_WWDG_Start() function. - When the WWDG is enabled the counter value should be configured to - a value greater than 0x40 to prevent generating an immediate reset. - (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is - generated when the counter reaches 0x40, and then start the WWDG using - HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can - add his own code by customization of callback HAL_WWDG_WakeupCallback. - Once enabled, EWI interrupt cannot be disabled except by a system reset. + (+) Configure the WWDG prescaler, refresh window value, counter value and early + interrupt status using HAL_WWDG_Init() function. This will automatically + enable WWDG and start its downcounter. Time reference can be taken from + function exit. Care must be taken to provide a counter value + greater than 0x40 to prevent generation of immediate reset. + (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is + generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is + triggered by the interrupt service routine, flag will be automatically + cleared and HAL_WWDG_WakeupCallback user callback will be executed. User + can add his own code by customization of callback HAL_WWDG_WakeupCallback. (+) Then the application program must refresh the WWDG counter at regular intervals during normal operation to prevent an MCU reset, using HAL_WWDG_Refresh() function. This operation must occur only when @@ -65,28 +72,28 @@ ============================= [..] - The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows + The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions - @ref HAL_WWDG_RegisterCallback() to register a user callback. + HAL_WWDG_RegisterCallback() to register a user callback. - (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following + (+) Function HAL_WWDG_RegisterCallback() allows to register following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. (++) MspInitCallback : WWDG MspInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to - the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback() + (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to + the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. This function allows to reset following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. (++) MspInitCallback : WWDG MspInit. [..] - When calling @ref HAL_WWDG_Init function, callbacks are reset to the + When calling HAL_WWDG_Init function, callbacks are reset to the corresponding legacy weak (surcharged) functions: - @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have + HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have not been registered before. [..] @@ -97,7 +104,7 @@ *** WWDG HAL driver macros list *** =================================== [..] - Below the list of most used macros in WWDG HAL driver. + Below the list of available macros in WWDG HAL driver. (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags @@ -198,7 +205,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) #else /* Init the low level hardware */ HAL_WWDG_MspInit(hwwdg); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /* Set WWDG Counter */ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); @@ -243,7 +250,8 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -304,7 +312,7 @@ HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWD return status; } -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} @@ -372,7 +380,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) #else /* Early Wakeup callback */ HAL_WWDG_EarlyWakeupCallback(hwwdg); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ } } } diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_wwdg.h index c0ce8e4cc4..d393ea607c 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_wwdg.h @@ -56,7 +56,7 @@ typedef struct uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ - uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not. + uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not. This parameter can be a value of @ref WWDG_EWI_Mode */ } WWDG_InitTypeDef; @@ -68,17 +68,17 @@ typedef struct typedef struct __WWDG_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ { WWDG_TypeDef *Instance; /*!< Register base address */ WWDG_InitTypeDef Init; /*!< WWDG required parameters */ #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) - void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ + void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ - void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ -#endif + void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ } WWDG_HandleTypeDef; #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) @@ -87,8 +87,8 @@ typedef struct */ typedef enum { - HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */ - HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */ + HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */ + HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */ } HAL_WWDG_CallbackIDTypeDef; /** @@ -96,7 +96,7 @@ typedef enum */ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */ -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} */ @@ -260,9 +260,10 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_adc.c index bec94293ac..2bcc2c9936 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_adc.c @@ -328,7 +328,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* Note: Hardware constraint (refer to description of functions */ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ - /* On this STM32 serie, setting of these features is conditioned to */ + /* On this STM32 series, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) @@ -673,7 +673,12 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I } assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); - + + /* ADC group regular continuous mode and discontinuous mode */ + /* can not be enabled simultenaeously */ + assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ if(LL_ADC_IsEnabled(ADCx) == 0U) @@ -686,7 +691,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* - Set ADC group regular continuous mode */ /* - Set ADC group regular conversion data transfer: no transfer or */ /* transfer by DMA, and DMA requests mode */ - /* Note: On this STM32 serie, ADC trigger edge is set when starting */ + /* Note: On this STM32 series, ADC trigger edge is set when starting */ /* ADC conversion. */ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) @@ -749,7 +754,7 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) { /* Set ADC_REG_InitStruct fields to default values */ /* Set fields of ADC group regular */ - /* Note: On this STM32 serie, ADC trigger edge is set when starting */ + /* Note: On this STM32 series, ADC trigger edge is set when starting */ /* ADC conversion. */ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; @@ -816,7 +821,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* - Set ADC group injected sequencer discontinuous mode */ /* - Set ADC group injected conversion trigger: independent or */ /* from ADC group regular */ - /* Note: On this STM32 serie, ADC trigger edge is set when starting */ + /* Note: On this STM32 series, ADC trigger edge is set when starting */ /* ADC conversion. */ /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_adc.h index 77f0ea2060..2dab9abbde 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_adc.h @@ -402,7 +402,7 @@ typedef struct { uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE - @note On this STM32 serie, setting of external trigger edge is performed + @note On this STM32 series, setting of external trigger edge is performed using function @ref LL_ADC_REG_StartConversionExtTrig(). This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ @@ -456,7 +456,7 @@ typedef struct { uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE - @note On this STM32 serie, setting of external trigger edge is performed + @note On this STM32 series, setting of external trigger edge is performed using function @ref LL_ADC_INJ_StartConversionExtTrig(). This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ @@ -500,7 +500,7 @@ typedef struct #define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ #define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */ #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ -#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ #define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ #define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ @@ -508,9 +508,9 @@ typedef struct #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */ #define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */ #define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */ -#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ -#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ -#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ #define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */ #define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */ @@ -524,7 +524,7 @@ typedef struct */ #define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ #define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */ -#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ /** * @} @@ -561,7 +561,7 @@ typedef struct /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */ +#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement paths all disabled */ #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */ @@ -584,7 +584,7 @@ typedef struct * @{ */ #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} */ @@ -1031,7 +1031,7 @@ typedef struct /* configuration (system clock versus ADC clock), */ /* and therefore must be defined in user application. */ /* Indications for estimation of ADC timeout delays, for this */ -/* STM32 serie: */ +/* STM32 series: */ /* - ADC enable time: maximum delay is 2us */ /* (refer to device datasheet, parameter "tSTAB") */ /* - ADC conversion time: duration depending on ADC clock and ADC */ @@ -1635,7 +1635,7 @@ typedef struct * connected to pin Vref+. * On devices with small package, the pin Vref+ is not present * and internally bonded to pin Vdda. - * @note On this STM32 serie, calibration data of internal voltage reference + * @note On this STM32 series, calibration data of internal voltage reference * VrefInt corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * internal voltage reference VrefInt. @@ -1685,7 +1685,7 @@ typedef struct * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note On this STM32 serie, calibration data of temperature sensor + * @note On this STM32 series, calibration data of temperature sensor * corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * temperature sensor. @@ -1832,7 +1832,7 @@ typedef struct */ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { - register uint32_t data_reg_addr = 0U; + uint32_t data_reg_addr = 0U; if (Register == LL_ADC_DMA_REG_REGULAR_DATA) { @@ -2080,7 +2080,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) * @brief Set ADC group regular conversion trigger source: * internal (SW start) or from external IP (timer event, * external interrupt line). - * @note On this STM32 serie, setting of external trigger edge is performed + * @note On this STM32 series, setting of external trigger edge is performed * using function @ref LL_ADC_REG_StartConversionExtTrig(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. @@ -2108,7 +2108,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { -/* Note: On this STM32 serie, ADC group regular external trigger edge */ +/* Note: On this STM32 series, ADC group regular external trigger edge */ /* is used to perform a ADC conversion start. */ /* This function does not set external trigger edge. */ /* This feature is set using function */ @@ -2151,11 +2151,11 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { - register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN); + uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); + uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */ /* to match with triggers literals definition. */ @@ -2184,7 +2184,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) /** * @brief Get ADC group regular conversion trigger polarity. * @note Applicable only for trigger source set to external trigger. - * @note On this STM32 serie, setting of external trigger edge is performed + * @note On this STM32 series, setting of external trigger edge is performed * using function @ref LL_ADC_REG_StartConversionExtTrig(). * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge * @param ADCx ADC instance @@ -2226,7 +2226,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) * highest channel number). * Sequencer ranks are selected using * function "LL_ADC_REG_SetSequencerChannels()". - * @note On this STM32 serie, group regular sequencer configuration + * @note On this STM32 series, group regular sequencer configuration * is conditioned to ADC instance sequencer mode. * If ADC instance sequencer mode is disabled, sequencers of * all groups (group regular, group injected) can be configured @@ -2287,7 +2287,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * highest channel number). * Sequencer ranks are selected using * function "LL_ADC_REG_SetSequencerChannels()". - * @note On this STM32 serie, group regular sequencer configuration + * @note On this STM32 series, group regular sequencer configuration * is conditioned to ADC instance sequencer mode. * If ADC instance sequencer mode is disabled, sequencers of * all groups (group regular, group injected) can be configured @@ -2377,13 +2377,13 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * @note This function performs configuration of: * - Channels ordering into each rank of scan sequence: * whatever channel can be placed into whatever rank. - * @note On this STM32 serie, ADC group regular sequencer is + * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). @@ -2455,7 +2455,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register and register position depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), @@ -2465,7 +2465,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /** * @brief Get ADC group regular sequence: channel on the selected * scan sequence rank. - * @note On this STM32 serie, ADC group regular sequencer is + * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). @@ -2548,7 +2548,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); return (uint32_t) (READ_BIT(*preg, ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) @@ -2713,7 +2713,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) * @brief Set ADC group injected conversion trigger source: * internal (SW start) or from external IP (timer event, * external interrupt line). - * @note On this STM32 serie, setting of external trigger edge is performed + * @note On this STM32 series, setting of external trigger edge is performed * using function @ref LL_ADC_INJ_StartConversionExtTrig(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. @@ -2740,7 +2740,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { -/* Note: On this STM32 serie, ADC group injected external trigger edge */ +/* Note: On this STM32 series, ADC group injected external trigger edge */ /* is used to perform a ADC conversion start. */ /* This function does not set external trigger edge. */ /* This feature is set using function */ @@ -2782,11 +2782,11 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) { - register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN); + uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN); /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); + uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */ /* to match with triggers literals definition. */ @@ -2833,7 +2833,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) * - Sequence length: Number of ranks in the scan sequence. * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from rank 1 to rank n). - * @note On this STM32 serie, group injected sequencer configuration + * @note On this STM32 series, group injected sequencer configuration * is conditioned to ADC instance sequencer mode. * If ADC instance sequencer mode is disabled, sequencers of * all groups (group regular, group injected) can be configured @@ -2861,7 +2861,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * - Sequence length: Number of ranks in the scan sequence. * - Sequence direction: Unless specified in parameters, sequencer * scan direction is forward (from rank 1 to rank n). - * @note On this STM32 serie, group injected sequencer configuration + * @note On this STM32 series, group injected sequencer configuration * is conditioned to ADC instance sequencer mode. * If ADC instance sequencer mode is disabled, sequencers of * all groups (group regular, group injected) can be configured @@ -2920,7 +2920,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * sequence rank. * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). @@ -2968,7 +2968,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* in register depending on parameter "Rank". */ /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ - register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; + uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; MODIFY_REG(ADCx->JSQR, ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))), @@ -3033,7 +3033,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { - register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; + uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))) @@ -3113,7 +3113,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_JOFR1_JOFFSET1, @@ -3140,7 +3140,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint */ __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_JOFR1_JOFFSET1) @@ -3169,7 +3169,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) * TS_temp, ...). * @note Conversion time is the addition of sampling time and processing time. * Refer to reference manual for ADC processing time of - * this STM32 serie. + * this STM32 series. * @note In case of ADC conversion of internal channel (VrefInt, * temperature sensor, ...), a sampling time minimum value * is required. @@ -3237,7 +3237,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* in register and register position depending on parameter "Channel". */ /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); MODIFY_REG(*preg, ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), @@ -3251,7 +3251,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * of channel mapped on ADC group regular or injected. * @note Conversion time is the addition of sampling time and processing time. * Refer to reference manual for ADC processing time of - * this STM32 serie. + * this STM32 series. * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n @@ -3310,7 +3310,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C */ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) @@ -3335,7 +3335,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * @note In case of need to define a single channel to monitor * with analog watchdog from sequencer channel definition, * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). - * @note On this STM32 serie, there is only 1 kind of analog watchdog + * @note On this STM32 series, there is only 1 kind of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -3444,7 +3444,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Applicable only when the analog watchdog is set to monitor * one channel. - * @note On this STM32 serie, there is only 1 kind of analog watchdog + * @note On this STM32 series, there is only 1 kind of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -3529,7 +3529,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this STM32 serie, there is only 1 kind of analog watchdog + * @note On this STM32 series, there is only 1 kind of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -3547,7 +3547,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); MODIFY_REG(*preg, ADC_HTR_HT, @@ -3570,7 +3570,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); } @@ -3812,7 +3812,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADC /** * @brief Enable the selected ADC instance. - * @note On this STM32 serie, after ADC enable, a delay for + * @note On this STM32 series, after ADC enable, a delay for * ADC internal analog stabilization is required before performing a * ADC conversion start. * Refer to device datasheet, parameter tSTAB. @@ -3857,7 +3857,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) /** * @brief Start ADC group regular conversion. - * @note On this STM32 serie, this function is relevant only for + * @note On this STM32 series, this function is relevant only for * internal trigger (SW start), not for external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. @@ -3880,7 +3880,7 @@ __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) * @brief Start ADC group regular conversion from external trigger. * @note ADC conversion will start at next trigger event (on the selected * trigger edge) following the ADC start conversion command. - * @note On this STM32 serie, this function is relevant for + * @note On this STM32 series, this function is relevant for * ADC conversion start from external trigger. * If internal trigger (SW start) is needed, perform ADC conversion * start using function @ref LL_ADC_REG_StartConversionSWStart(). @@ -3902,7 +3902,7 @@ __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32 * @note No more ADC conversion will start at next trigger event * following the ADC stop conversion command. * If a conversion is on-going, it will be completed. - * @note On this STM32 serie, there is no specific command + * @note On this STM32 series, there is no specific command * to stop a conversion on-going or to stop ADC converting * in continuous mode. These actions can be performed * using function @ref LL_ADC_Disable(). @@ -4028,7 +4028,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef /** * @brief Start ADC group injected conversion. - * @note On this STM32 serie, this function is relevant only for + * @note On this STM32 series, this function is relevant only for * internal trigger (SW start), not for external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. @@ -4051,7 +4051,7 @@ __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) * @brief Start ADC group injected conversion from external trigger. * @note ADC conversion will start at next trigger event (on the selected * trigger edge) following the ADC start conversion command. - * @note On this STM32 serie, this function is relevant for + * @note On this STM32 series, this function is relevant for * ADC conversion start from external trigger. * If internal trigger (SW start) is needed, perform ADC conversion * start using function @ref LL_ADC_INJ_StartConversionSWStart(). @@ -4073,7 +4073,7 @@ __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32 * @note No more ADC conversion will start at next trigger event * following the ADC stop conversion command. * If a conversion is on-going, it will be completed. - * @note On this STM32 serie, there is no specific command + * @note On this STM32 series, there is no specific command * to stop a conversion on-going or to stop ADC converting * in continuous mode. These actions can be performed * using function @ref LL_ADC_Disable(). @@ -4105,7 +4105,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -4132,7 +4132,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -4159,7 +4159,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -4186,7 +4186,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -4213,7 +4213,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 */ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) { - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) @@ -4263,7 +4263,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) { - /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* Note: on this STM32 series, there is no flag ADC group injected */ /* end of unitary conversion. */ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ /* in other STM32 families). */ @@ -4316,7 +4316,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) { - /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* Note: on this STM32 series, there is no flag ADC group injected */ /* end of unitary conversion. */ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ /* in other STM32 families). */ @@ -4427,7 +4427,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) { - /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* Note: on this STM32 series, there is no flag ADC group injected */ /* end of unitary conversion. */ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ /* in other STM32 families). */ @@ -4443,7 +4443,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_ */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) { - /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* Note: on this STM32 series, there is no flag ADC group injected */ /* end of unitary conversion. */ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ /* in other STM32 families). */ @@ -4459,7 +4459,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) { - /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* Note: on this STM32 series, there is no flag ADC group injected */ /* end of unitary conversion. */ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ /* in other STM32 families). */ @@ -4546,7 +4546,7 @@ __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) { - /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* Note: on this STM32 series, there is no flag ADC group injected */ /* end of unitary conversion. */ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ /* in other STM32 families). */ @@ -4599,7 +4599,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) { - /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* Note: on this STM32 series, there is no flag ADC group injected */ /* end of unitary conversion. */ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ /* in other STM32 families). */ @@ -4655,7 +4655,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) { - /* Note: on this STM32 serie, there is no flag ADC group injected */ + /* Note: on this STM32 series, there is no flag ADC group injected */ /* end of unitary conversion. */ /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ /* in other STM32 families). */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dac.c index 57b1f8dbed..f3c8f5b719 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dac.c @@ -23,10 +23,10 @@ #include "stm32f7xx_ll_bus.h" #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" +#include "stm32_assert.h" #else - #define assert_param(expr) ((void)0U) -#endif +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F7xx_LL_Driver * @{ @@ -46,7 +46,6 @@ /** @addtogroup DAC_LL_Private_Macros * @{ */ - #define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ ( \ ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ @@ -64,42 +63,46 @@ || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ ) -#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ - ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ +#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ + ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ ) -#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \ - ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \ +#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \ + ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ + ) \ + ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ + && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ + ) \ ) #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ - || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ + || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ ) /** @@ -130,20 +133,32 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) { /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); - - /* Force reset of DAC1 clock */ + + /* Force reset of DAC clock */ LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1); - - /* Release reset of DAC1 clock */ + + /* Release reset of DAC clock */ LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1); + return SUCCESS; } /** - * @brief Initialize some features of DAC instance. + * @brief Initialize some features of DAC channel. + * @note @ref LL_DAC_Init() aims to ease basic configuration of a DAC channel. + * Leaving it ready to be enabled and output: + * a level by calling one of + * @ref LL_DAC_ConvertData12RightAligned + * @ref LL_DAC_ConvertData12LeftAligned + * @ref LL_DAC_ConvertData8RightAligned + * or one of the supported autogenerated wave. + * @note This function allows configuration of: + * - Output mode + * - Trigger + * - Wave generation * @note The setting of these parameters by function @ref LL_DAC_Init() * is conditioned to DAC state: - * DAC instance must be disabled. + * DAC channel must be disabled. * @param DACx DAC instance * @param DAC_Channel This parameter can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 @@ -156,7 +171,7 @@ ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx) ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_DAC_ALL_INSTANCE(DACx)); assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel)); @@ -165,27 +180,29 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration)); if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) { - assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig)); + assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGeneration, + DAC_InitStruct->WaveAutoGenerationConfig)); } - + /* Note: Hardware constraint (refer to description of this function) */ /* DAC instance must be disabled. */ - if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U) + if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0UL) { /* Configuration of DAC channel: */ /* - TriggerSource */ /* - WaveAutoGeneration */ /* - OutputBuffer */ + /* - OutputMode */ if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) { MODIFY_REG(DACx->CR, - ( DAC_CR_TSEL1 + (DAC_CR_TSEL1 | DAC_CR_WAVE1 | DAC_CR_MAMP1 | DAC_CR_BOFF1 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) - , - ( DAC_InitStruct->TriggerSource + , + (DAC_InitStruct->TriggerSource | DAC_InitStruct->WaveAutoGeneration | DAC_InitStruct->WaveAutoGenerationConfig | DAC_InitStruct->OutputBuffer @@ -195,12 +212,12 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType else { MODIFY_REG(DACx->CR, - ( DAC_CR_TSEL1 + (DAC_CR_TSEL1 | DAC_CR_WAVE1 | DAC_CR_BOFF1 ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) - , - ( DAC_InitStruct->TriggerSource + , + (DAC_InitStruct->TriggerSource | LL_DAC_WAVE_AUTO_GENERATION_NONE | DAC_InitStruct->OutputBuffer ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dac.h index 1ed5031ce5..9886317f54 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dac.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dac.h @@ -18,8 +18,8 @@ */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_DAC_H -#define __STM32F7xx_LL_DAC_H +#ifndef STM32F7xx_LL_DAC_H +#define STM32F7xx_LL_DAC_H #ifdef __cplusplus extern "C" { @@ -48,40 +48,76 @@ extern "C" { /* Internal masks for DAC channels definition */ /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ -/* - channel bits position into register CR */ +/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ /* - channel bits position into register SWTRIG */ /* - channel register offset of data holding register DHRx */ /* - channel register offset of data output register DORx */ -#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ -#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ +#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers + CR, MCR, CCR, SHHR, SHRR of channel 1 */ +#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers + CR, MCR, CCR, SHHR, SHRR of channel 2 */ #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) -#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ -#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ +#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ +#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) -#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ -#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ -#define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ -#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ -#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U -#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U -#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U -#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) +#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ +#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus + DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus + DHR12Rx channel 1 (shifted left of 24 bits) */ -#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ -#define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ +#define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus + DHR12Rx channel 1 (shifted left of 16 bits) */ +#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus + DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus + DHR12Rx channel 1 (shifted left of 24 bits) */ + +#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL +#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL +#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL +#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ + | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) + +#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ + +#define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus + DORx channel 2 (shifted left of 28 bits) */ #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) + + +#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, + DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ +#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted + to position 0 */ +#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted + to position 0 */ + +#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 16 bits) */ +#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 20 bits) */ +#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 24 bits) */ +#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx + channel 1 or 2 versus DORx channel 1 + (shifted left of 28 bits) */ + /* DAC registers bits positions */ -#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ -#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ -#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ +#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos +#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos +#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos /* Miscellaneous data */ -#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ +#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 + bits (voltage range determined by analog voltage + references Vref+ and Vref-, refer to reference manual) */ /** * @} @@ -93,17 +129,6 @@ extern "C" { * @{ */ -/** - * @brief Driver macro reserved for internal use: isolate bits with the - * selected mask and shift them to the register LSB - * (shift mask on register position bit 0). - * @param __BITS__ Bits in register 32 bits - * @param __MASK__ Mask in register 32 bits - * @retval Bits in register 32 bits -*/ -#define __DAC_MASK_SHIFT(__BITS__, __MASK__) \ - (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) - /** * @brief Driver macro reserved for internal use: set a pointer to * a register from a register basis from which an offset @@ -111,9 +136,9 @@ extern "C" { * @param __REG__ Register basis from which the offset is applied. * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). * @retval Pointer to register address -*/ + */ #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) /** * @} @@ -131,28 +156,38 @@ extern "C" { */ typedef struct { - uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). + uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: + internal (SW start) or from external peripheral + (timer event, external interrupt line). This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE - - This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ + + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetTriggerSource(). */ uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE - - This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ + + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetWaveAutoGeneration(). */ uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. - If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS - If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE - @note If waveform automatic generation mode is disabled, this parameter is discarded. - - This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */ + If waveform automatic generation mode is set to noise, this parameter + can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS + If waveform automatic generation mode is set to triangle, + this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE + @note If waveform automatic generation mode is disabled, + this parameter is discarded. + + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetWaveNoiseLFSR(), + @ref LL_DAC_SetWaveTriangleAmplitude() + depending on the wave automatic generation selected. */ uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER - - This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetOutputBuffer(). */ } LL_DAC_InitTypeDef; /** @@ -174,6 +209,7 @@ typedef struct /* DAC channel 2 flags */ #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ + /** * @} */ @@ -183,7 +219,9 @@ typedef struct * @{ */ #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ + #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ + /** * @} */ @@ -192,7 +230,9 @@ typedef struct * @{ */ #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ + #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ + /** * @} */ @@ -201,13 +241,13 @@ typedef struct * @{ */ #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ -#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ -#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ +#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ +#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */ +#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ /** * @} */ @@ -215,9 +255,9 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode * @{ */ -#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ -#define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ -#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ +#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ /** * @} */ @@ -225,7 +265,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits * @{ */ -#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ @@ -244,7 +284,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude * @{ */ -#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ @@ -263,18 +303,17 @@ typedef struct /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer * @{ */ -#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ +#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ /** * @} */ - /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution * @{ */ -#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ -#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ +#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */ +#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */ /** * @} */ @@ -285,15 +324,15 @@ typedef struct /* List of DAC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ -#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */ -#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */ -#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */ +#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ +#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ +#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ /** * @} */ /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays - * @note Only DAC IP HW delays are defined in DAC LL driver driver, + * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, * not timeout values. * For details on delays values, refer to descriptions in source code * above each literal definition. @@ -312,7 +351,7 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tWAKEUP"). */ /* Unit: us */ -#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ +#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ /* Delay for DAC channel voltage settling time. */ /* Note: DAC channel startup time depends on board application environment: */ @@ -325,7 +364,8 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSETTLING"). */ /* Unit: us */ -#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */ +#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */ + /** * @} */ @@ -397,22 +437,8 @@ typedef struct * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 */ -#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) == 1U) \ - ? ( \ - LL_DAC_CHANNEL_1 \ - ) \ - : \ - (((__DECIMAL_NB__) == 2U) \ - ? ( \ - LL_DAC_CHANNEL_2 \ - ) \ - : \ - ( \ - 0 \ - ) \ - ) \ - ) +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\ + (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL))) /** * @brief Helper macro to define the DAC conversion data full-scale digital @@ -426,7 +452,7 @@ typedef struct * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) + ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL)) /** * @brief Helper macro to calculate the DAC conversion data (unit: digital @@ -437,7 +463,7 @@ typedef struct * @ref LL_DAC_ConvertData12RightAligned(). * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel * (unit: mVolt). @@ -449,9 +475,9 @@ typedef struct #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ __DAC_VOLTAGE__,\ __DAC_RESOLUTION__) \ - ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - / (__VREFANALOG_VOLTAGE__) \ - ) +((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ +) /** * @} @@ -466,10 +492,6 @@ typedef struct /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions * @{ */ -/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels - * @{ - */ - /** * @brief Set the conversion trigger source for the selected DAC channel. * @note For conversion trigger source to be effective, DAC trigger @@ -611,7 +633,7 @@ __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Cha } /** - * @brief Set the noise waveform generation for the selected DAC channel: + * @brief Get the noise waveform generation for the selected DAC channel: * Noise mode and parameters LFSR (linear feedback shift register). * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n * CR MAMP2 LL_DAC_GetWaveNoiseLFSR @@ -669,7 +691,8 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 * @retval None */ -__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude) +__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, + uint32_t TriangleAmplitude) { MODIFY_REG(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), @@ -677,7 +700,7 @@ __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t } /** - * @brief Set the triangle waveform generation for the selected DAC channel: + * @brief Get the triangle waveform generation for the selected DAC channel: * triangle mode and amplitude. * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude @@ -802,9 +825,9 @@ __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channe */ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (READ_BIT(DACx->CR, - DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); + return ((READ_BIT(DACx->CR, + DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); } /** @@ -820,7 +843,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_ * LL_DMA_ConfigAddresses(DMA1, * LL_DMA_CHANNEL_1, * (uint32_t)&< array or variable >, - * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), + * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, + * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n @@ -842,7 +866,8 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C { /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ /* DAC channel selected. */ - return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register)))); + return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); } /** * @} @@ -900,9 +925,9 @@ __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) */ __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (READ_BIT(DACx->CR, - DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); + return ((READ_BIT(DACx->CR, + DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); } /** @@ -958,15 +983,17 @@ __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Chann */ __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - return (READ_BIT(DACx->CR, - DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); + return ((READ_BIT(DACx->CR, + DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) + == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); } /** * @brief Trig DAC conversion by software for the selected DAC channel. * @note Preliminarily, DAC trigger must be set to software trigger - * using function @ref LL_DAC_SetTriggerSource() + * using function + * @ref LL_DAC_Init() + * @ref LL_DAC_SetTriggerSource() * with parameter "LL_DAC_TRIGGER_SOFTWARE". * and DAC trigger must be enabled using * function @ref LL_DAC_EnableTrigger(). @@ -1003,11 +1030,10 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha */ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK)); - - MODIFY_REG(*preg, - DAC_DHR12R1_DACC1DHR, - Data); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + + MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); } /** @@ -1025,11 +1051,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_ */ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK)); - - MODIFY_REG(*preg, - DAC_DHR12L1_DACC1DHR, - Data); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + + MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); } /** @@ -1047,13 +1072,13 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK)); - - MODIFY_REG(*preg, - DAC_DHR8R1_DACC1DHR, - Data); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + + MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); } + /** * @brief Set the data to be loaded in the data holding register * in format 12 bits left alignment (LSB aligned on bit 0), @@ -1065,7 +1090,8 @@ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ -__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, + uint32_t DataChannel2) { MODIFY_REG(DACx->DHR12RD, (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), @@ -1083,7 +1109,8 @@ __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uin * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ -__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, + uint32_t DataChannel2) { /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ @@ -1104,13 +1131,15 @@ __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF * @retval None */ -__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) +__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, + uint32_t DataChannel2) { MODIFY_REG(DACx->DHR8RD, (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); } + /** * @brief Retrieve output data currently generated for the selected DAC channel. * @note Whatever alignment and resolution settings @@ -1127,8 +1156,9 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint */ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK)); - + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); + return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); } @@ -1139,6 +1169,8 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management * @{ */ + + /** * @brief Get DAC underrun flag for DAC channel 1 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 @@ -1147,9 +1179,10 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); } + /** * @brief Get DAC underrun flag for DAC channel 2 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 @@ -1158,9 +1191,10 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)); + return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); } + /** * @brief Clear DAC underrun flag for DAC channel 1 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 @@ -1172,6 +1206,7 @@ __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); } + /** * @brief Clear DAC underrun flag for DAC channel 2 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 @@ -1183,6 +1218,7 @@ __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); } + /** * @} */ @@ -1202,6 +1238,7 @@ __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); } + /** * @brief Enable DMA underrun interrupt for DAC channel 2 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 @@ -1213,6 +1250,7 @@ __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); } + /** * @brief Disable DMA underrun interrupt for DAC channel 1 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 @@ -1224,6 +1262,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); } + /** * @brief Disable DMA underrun interrupt for DAC channel 2 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 @@ -1235,6 +1274,7 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); } + /** * @brief Get DMA underrun interrupt for DAC channel 1 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 @@ -1243,9 +1283,10 @@ __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)); + return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); } + /** * @brief Get DMA underrun interrupt for DAC channel 2 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 @@ -1254,9 +1295,10 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) */ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) { - return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)); + return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); } + /** * @} */ @@ -1266,9 +1308,9 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) * @{ */ -ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx); -ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct); -void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); +ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); +ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); +void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); /** * @} @@ -1293,6 +1335,6 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); } #endif -#endif /* __STM32F7xx_LL_DAC_H */ +#endif /* STM32F7xx_LL_DAC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dma2d.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dma2d.c index 9e3ae778c6..34b711cfb0 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dma2d.c @@ -25,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F7xx_LL_Driver * @{ @@ -167,9 +167,12 @@ ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct) { ErrorStatus status = ERROR; - LL_DMA2D_ColorTypeDef DMA2D_ColorStruct; - uint32_t tmp, tmp1, tmp2; - uint32_t regMask, regValue; + LL_DMA2D_ColorTypeDef dma2d_colorstruct; + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; + uint32_t regMask; + uint32_t regValue; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -219,12 +222,12 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini LL_DMA2D_SetOutputMemAddr(DMA2Dx, DMA2D_InitStruct->OutputMemoryAddress); /* DMA2D OCOLR register configuration ------------------------------------------*/ - DMA2D_ColorStruct.ColorMode = DMA2D_InitStruct->ColorMode; - DMA2D_ColorStruct.OutputBlue = DMA2D_InitStruct->OutputBlue; - DMA2D_ColorStruct.OutputGreen = DMA2D_InitStruct->OutputGreen; - DMA2D_ColorStruct.OutputRed = DMA2D_InitStruct->OutputRed; - DMA2D_ColorStruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha; - LL_DMA2D_ConfigOutputColor(DMA2Dx, &DMA2D_ColorStruct); + dma2d_colorstruct.ColorMode = DMA2D_InitStruct->ColorMode; + dma2d_colorstruct.OutputBlue = DMA2D_InitStruct->OutputBlue; + dma2d_colorstruct.OutputGreen = DMA2D_InitStruct->OutputGreen; + dma2d_colorstruct.OutputRed = DMA2D_InitStruct->OutputRed; + dma2d_colorstruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha; + LL_DMA2D_ConfigOutputColor(DMA2Dx, &dma2d_colorstruct); status = SUCCESS; } diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dma2d.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dma2d.h index f8e1f11311..f9d1d23ee5 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_dma2d.h @@ -66,84 +66,116 @@ typedef struct uint32_t Mode; /*!< Specifies the DMA2D transfer mode. - This parameter can be one value of @ref DMA2D_LL_EC_MODE. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/ + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetMode(). */ uint32_t ColorMode; /*!< Specifies the color format of the output image. - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */ + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputColorMode(). */ uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputGreen; /*!< Specifies the Green value of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputRed; /*!< Specifies the Red value of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter is not considered if RGB888 or RGB565 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputMemoryAddress; /*!< Specifies the memory address. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */ + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */ uint32_t LineOffset; /*!< Specifies the output line offset value. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */ + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetLineOffset(). */ uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFF. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */ + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetNbrOfLines(). */ - uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered. + uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */ + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */ #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode. - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */ + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */ uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode. - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */ + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */ #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ } LL_DMA2D_InitTypeDef; @@ -154,7 +186,8 @@ typedef struct typedef struct { uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. This parameter can be modified afterwards using unitary functions - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer, @@ -224,7 +257,8 @@ typedef struct - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */ uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. This parameter can be modified afterwards using unitary functions - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer, @@ -257,45 +291,68 @@ typedef struct uint32_t ColorMode; /*!< Specifies the color format of the output image. - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */ + This parameter can be modified afterwards using + unitary function @ref LL_DMA2D_SetOutputColorMode(). */ uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputGreen; /*!< Specifies the Green value of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputRed; /*!< Specifies the Red value of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter is not considered if RGB888 or RGB565 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ } LL_DMA2D_ColorTypeDef; @@ -383,9 +440,11 @@ typedef struct * @{ */ #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */ -#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */ -#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value - with original alpha channel value */ +#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by + programmed alpha value */ +#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by + programmed alpha value with, + original alpha channel value */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_fmc.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_fmc.c index 79c3479f68..680ccf475e 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_fmc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_fmc.c @@ -969,9 +969,7 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, u * @retval HAL state */ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) -{ - __IO uint32_t tmpr = 0; - +{ /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); @@ -980,13 +978,10 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Com assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); /* Set command register */ - tmpr = (uint32_t)((Command->CommandMode) |\ - (Command->CommandTarget) |\ - (((Command->AutoRefreshNumber)-1) << 5) |\ - ((Command->ModeRegisterDefinition) << 9) - ); - - Device->SDCMR = tmpr; + MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | + FMC_SDCMR_NRFS | FMC_SDCMR_MRD), ((Command->CommandMode) | + (Command->CommandTarget) | (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) | + ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos))); return HAL_OK; } diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_gpio.h index bff720a7bc..eab42b19e4 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_gpio.h @@ -939,7 +939,8 @@ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMas */ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { - WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_i2c.h index cb56430deb..76dc4c6468 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_i2c.h @@ -67,38 +67,38 @@ extern "C" { typedef struct { uint32_t PeripheralMode; /*!< Specifies the peripheral mode. - This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and - the helper macro @ref __LL_I2C_CONVERT_TIMINGS() + the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. - This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ uint32_t DigitalFilter; /*!< Configures the digital noise filter. - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ uint32_t OwnAddress1; /*!< Specifies the device own address 1. - This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. - This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). - This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ } LL_I2C_InitTypeDef; @@ -360,11 +360,11 @@ typedef struct * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ - (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ - (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) /** * @} */ @@ -578,17 +578,17 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) */ __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) { /* return address of TXDR register */ - data_reg_addr = (uint32_t) & (I2Cx->TXDR); + data_reg_addr = (uint32_t) &(I2Cx->TXDR); } else { /* return address of RXDR register */ - data_reg_addr = (uint32_t) & (I2Cx->RXDR); + data_reg_addr = (uint32_t) &(I2Cx->RXDR); } return data_reg_addr; @@ -902,7 +902,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) /** * @brief Configure peripheral mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n * CR1 SMBDEN LL_I2C_SetMode @@ -921,7 +921,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) /** * @brief Get peripheral mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n * CR1 SMBDEN LL_I2C_GetMode @@ -939,7 +939,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus alert (Host or Device mode) - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is drived low and @@ -957,7 +957,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus alert (Host or Device mode) - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is not drived (can be used as a standard GPIO) and @@ -975,7 +975,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert * @param I2Cx I2C Instance. @@ -988,7 +988,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) /** * @brief Enable SMBus Packet Error Calculation (PEC). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC * @param I2Cx I2C Instance. @@ -1001,7 +1001,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Disable SMBus Packet Error Calculation (PEC). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC * @param I2Cx I2C Instance. @@ -1014,7 +1014,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC * @param I2Cx I2C Instance. @@ -1027,7 +1027,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) /** * @brief Configure the SMBus Clock Timeout. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n @@ -1050,7 +1050,7 @@ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Timeo /** * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note These bits can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA @@ -1065,7 +1065,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout /** * @brief Get the SMBus Clock TimeoutA setting. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA * @param I2Cx I2C Instance. @@ -1078,7 +1078,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) /** * @brief Set the SMBus Clock TimeoutA mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This bit can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode @@ -1095,7 +1095,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim /** * @brief Get the SMBus Clock TimeoutA mode. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode * @param I2Cx I2C Instance. @@ -1110,7 +1110,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) /** * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note These bits can only be programmed when TimeoutB is disabled. * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB @@ -1124,8 +1124,8 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout } /** - * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB * @param I2Cx I2C Instance. @@ -1138,7 +1138,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) /** * @brief Enable the SMBus Clock Timeout. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout @@ -1156,7 +1156,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Clock /** * @brief Disable the SMBus Clock Timeout. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout @@ -1174,7 +1174,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc /** * @brief Check if the SMBus Clock Timeout is enabled or disabled. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout @@ -1404,7 +1404,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) /** * @brief Enable Error interrupts. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1424,7 +1424,7 @@ __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) /** * @brief Disable Error interrupts. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1606,7 +1606,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus PEC error flag in reception. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When the received PEC does not match with the PEC register content. @@ -1621,7 +1621,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus Timeout detection flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When a timeout or extended clock timeout occurs. @@ -1636,7 +1636,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Indicate the status of SMBus alert flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note RESET: Clear default value. * SET: When SMBus host configuration, SMBus alert enabled and @@ -1743,7 +1743,7 @@ __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus PEC error flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR * @param I2Cx I2C Instance. @@ -1756,7 +1756,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Timeout detection flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT * @param I2Cx I2C Instance. @@ -1769,7 +1769,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) /** * @brief Clear SMBus Alert flag. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT * @param I2Cx I2C Instance. @@ -2051,7 +2051,9 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { - MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); } @@ -2084,7 +2086,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) /** * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. * This bit has no effect when RELOAD bit is set. @@ -2100,7 +2102,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare * @param I2Cx I2C Instance. @@ -2113,12 +2115,12 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) /** * @brief Get the SMBus Packet Error byte calculated. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll PECR PEC LL_I2C_GetSMBusPEC * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF -*/ + */ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_iwdg.h index 50412ac08f..686f09e4f9 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_iwdg.h @@ -304,8 +304,8 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) /** * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not * @rmtoll SR PVU LL_IWDG_IsReady\n - * SR WVU LL_IWDG_IsReady\n - * SR RVU LL_IWDG_IsReady + * SR RVU LL_IWDG_IsReady\n + * SR WVU LL_IWDG_IsReady * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ @@ -318,7 +318,6 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) * @} */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_lptim.c index 63c8a55cff..6c58544396 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_lptim.c @@ -48,22 +48,22 @@ * @{ */ #define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ - || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) + || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) #define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) #define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) + || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) #define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) + || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) /** * @} */ @@ -240,8 +240,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } - while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_CMPOK(LPTIMx); } diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_lptim.h index 03baa9158c..b9a07196d6 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_lptim.h @@ -100,9 +100,9 @@ typedef struct * @{ */ #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */ +#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */ -#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ @@ -114,13 +114,13 @@ typedef struct * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions * @{ */ -#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */ -#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */ -#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */ -#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */ -#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */ -#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */ -#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */ +#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */ +#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */ +#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */ +#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */ +#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */ +#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */ +#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */ /** * @} */ @@ -155,7 +155,7 @@ typedef struct /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type * @{ */ -#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ @@ -1520,7 +1520,7 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year) { - register uint32_t temp = 0U; + uint32_t temp = 0U; temp = (WeekDay << RTC_DR_WDU_Pos) | \ (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ @@ -1548,7 +1548,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin */ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; + uint32_t temp = 0U; temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ @@ -1848,7 +1848,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp = 0U; + uint32_t temp = 0U; temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ @@ -2214,7 +2214,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp = 0U; + uint32_t temp = 0U; temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ @@ -2992,7 +2992,7 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) { - register uint32_t tmp = 0U; + uint32_t tmp = 0U; tmp = (uint32_t)(&(RTCx->BKP0R)); tmp += (BackupRegister * 4U); @@ -3042,7 +3042,7 @@ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe */ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) { - register uint32_t tmp = 0U; + uint32_t tmp = 0U; tmp = (uint32_t)(&(RTCx->BKP0R)); tmp += (BackupRegister * 4U); diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_sdmmc.c index 3cd5b1f59d..a69b28c725 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_sdmmc.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_sdmmc.c @@ -511,7 +511,7 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM */ /** - * @brief Send the Data Block Lenght command and check the response + * @brief Send the Data Block Length command and check the response * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ @@ -1099,7 +1099,7 @@ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) } /** - * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand + * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command * @param SDMMCx: Pointer to SDMMC register base * @parame Argument: Argument used for the command * @retval HAL status @@ -1142,7 +1142,7 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) { /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { @@ -1172,7 +1172,7 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ /* 8 is the number of required instructions cycles for the below loop statement. The Timeout is expressed in ms */ - register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); + uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); do { @@ -1305,7 +1305,7 @@ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { @@ -1349,7 +1349,7 @@ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { @@ -1391,7 +1391,7 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { @@ -1462,7 +1462,7 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); do { @@ -1503,6 +1503,32 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) } +/** + * @brief Send the Send EXT_CSD command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD9 SEND_CSD */ + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT); + + return errorstate; +} + + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_sdmmc.h index aa0d0eed8b..b9781880e3 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_sdmmc.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_sdmmc.h @@ -301,7 +301,9 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U #define SDMMC_CARD_LOCKED 0x02000000U +#ifndef SDMMC_DATATIMEOUT #define SDMMC_DATATIMEOUT 0xFFFFFFFFU +#endif /* SDMMC_DATATIMEOUT */ #define SDMMC_0TO7BITS 0x000000FFU #define SDMMC_8TO15BITS 0x0000FF00U @@ -455,7 +457,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Data_Length Data Lenght +/** @defgroup SDMMC_LL_Data_Length Data Length * @{ */ #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) @@ -984,6 +986,7 @@ uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_spi.c index 60494951cc..668e2dc222 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_spi.c @@ -60,52 +60,52 @@ /** @defgroup SPI_LL_Private_Macros SPI Private Macros * @{ */ -#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ - || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ - || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ - || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) +#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ + || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ + || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ + || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ - || ((__VALUE__) == LL_SPI_MODE_SLAVE)) + || ((__VALUE__) == LL_SPI_MODE_SLAVE)) -#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) +#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ - || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) + || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ - || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) + || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) -#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ - || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ - || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) +#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ + || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ + || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) -#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) +#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ - || ((__VALUE__) == LL_SPI_MSB_FIRST)) + || ((__VALUE__) == LL_SPI_MSB_FIRST)) #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \ - || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) + || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U) @@ -269,6 +269,12 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) SPI_CR2_DS | SPI_CR2_SSOE, SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U)); + /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */ + if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT) + { + LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER); + } + /*---------------------------- SPIx CRCPR Configuration ---------------------- * Configure SPIx CRCPR with parameters: * - CRCPoly: CRCPOLY[15:0] bits @@ -343,36 +349,36 @@ void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) * @{ */ -#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) +#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ - || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) + || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) -#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ - || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ - || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ - || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ - || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) +#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ + || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ + || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ + || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ + || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) -#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ - || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ - || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ - || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) +#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ + || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ + || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ + || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ - || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) + || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) -#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ - && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ - || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) +#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ + && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ + || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ - || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) + || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) /** * @} */ @@ -412,7 +418,9 @@ ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) */ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) { - uint32_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U; + uint32_t i2sdiv = 2U; + uint32_t i2sodd = 0U; + uint32_t packetlength = 1U; uint32_t tmp; uint32_t sourceclock; ErrorStatus status = ERROR; diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_spi.h index 1a0ac48668..a9beeeb3ec 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_spi.h @@ -266,8 +266,8 @@ typedef struct /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold * @{ */ -#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ -#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */ +#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */ +#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */ /** * @} */ @@ -848,8 +848,8 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) */ __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) { - register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); - register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); return (Ssm | Ssoe); } @@ -1314,7 +1314,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) { - return (uint32_t) & (SPIx->DR); + return (uint32_t) &(SPIx->DR); } /** @@ -1361,7 +1361,7 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) *spidr = TxData; #else *((__IO uint8_t *)&SPIx->DR) = TxData; -#endif +#endif /* __GNUC__ */ } /** @@ -1378,7 +1378,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) *spidr = TxData; #else SPIx->DR = TxData; -#endif +#endif /* __GNUC__ */ } /** @@ -1500,10 +1500,10 @@ typedef struct /** @defgroup I2S_LL_EC_DATA_FORMAT Data format * @{ */ -#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ -#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ -#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ -#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */ +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */ /** * @} */ @@ -1838,7 +1838,7 @@ __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) } /** - * @brief Enable the master clock ouput (Pin MCK) + * @brief Enable the master clock output (Pin MCK) * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock * @param SPIx SPI Instance * @retval None @@ -1849,7 +1849,7 @@ __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) } /** - * @brief Disable the master clock ouput (Pin MCK) + * @brief Disable the master clock output (Pin MCK) * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock * @param SPIx SPI Instance * @retval None @@ -1860,7 +1860,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) } /** - * @brief Check if the master clock ouput (Pin MCK) is enabled + * @brief Check if the master clock output (Pin MCK) is enabled * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock * @param SPIx SPI Instance * @retval State of bit (1 or 0). diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_tim.h index 5750eeffd2..470970f583 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_tim.h @@ -570,8 +570,8 @@ typedef struct /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode * @{ */ -#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ -#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ @@ -581,8 +581,8 @@ typedef struct */ #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!CR1, TIM_CR1_DIR | TIM_CR1_CMS)); + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; } /** @@ -1868,8 +1877,8 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); @@ -1913,8 +1922,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } @@ -1952,8 +1961,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint */ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } @@ -1986,7 +1995,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); } @@ -2018,7 +2027,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -2055,7 +2064,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann */ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); } @@ -2087,7 +2096,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); } @@ -2112,8 +2121,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2138,8 +2147,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2164,9 +2173,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2190,8 +2199,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha */ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2215,8 +2224,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2240,9 +2249,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2269,8 +2278,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2296,8 +2305,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2325,9 +2334,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2596,8 +2605,8 @@ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t G */ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), @@ -2624,8 +2633,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 */ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2648,8 +2657,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2674,8 +2683,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch */ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2699,8 +2708,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2737,8 +2746,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2774,8 +2783,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui */ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2803,7 +2812,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), ICPolarity << SHIFT_TAB_CCxP[iChannel]); } @@ -2831,7 +2840,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -3457,7 +3466,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); SET_BIT(*pReg, Source); } @@ -3480,7 +3489,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B */ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); CLEAR_BIT(*pReg, Source); } @@ -3507,7 +3516,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity) { - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); } #endif /* TIM_BREAK_INPUT_SUPPORT */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usart.c index d7f367518e..ab924353d6 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usart.c @@ -53,9 +53,6 @@ /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) -/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ -#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) - #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ || ((__VALUE__) == LL_USART_DIRECTION_RX) \ || ((__VALUE__) == LL_USART_DIRECTION_TX) \ @@ -198,8 +195,9 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) /** * @brief Initialize USART registers according to the specified * parameters in USART_InitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). * @param USARTx USART Instance * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure @@ -249,7 +247,8 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /*---------------------------- USART CR3 Configuration --------------------- * Configure USARTx CR3 (Hardware Flow Control) with parameters: - * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value. + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to + * USART_InitStruct->HardwareFlowControl value. */ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); @@ -308,9 +307,6 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* Check BRR is greater than or equal to 16d */ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); - - /* Check BRR is lower than or equal to 0xFFFF */ - assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); } } /* Endif (=> USART not in Disabled state => return ERROR) */ @@ -340,13 +336,15 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) /** * @brief Initialize USART Clock related settings according to the * specified parameters in the USART_ClockInitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. * @param USARTx USART Instance * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * that contains the Clock configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content + * - SUCCESS: USART registers related to Clock settings are initialized according + * to USART_ClockInitStruct content * - ERROR: Problem occurred during USART Registers initialization */ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) @@ -361,8 +359,7 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef CRx registers */ if (LL_USART_IsEnabled(USARTx) == 0U) { - /*---------------------------- USART CR2 Configuration -----------------------*/ - /* If Clock signal has to be output */ + /* If USART Clock signal is disabled */ if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) { /* Deactivate Clock signal delivery : @@ -412,9 +409,12 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) { /* Set LL_USART_ClockInitStruct fields with default values */ USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; - USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ } /** diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usart.h index 5a89688ee7..7a3cdaf209 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usart.h @@ -66,37 +66,44 @@ typedef struct uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. - This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref USART_LL_EC_STOPBITS. - This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref USART_LL_EC_PARITY. - This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of @ref USART_LL_EC_DIRECTION. - This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref USART_LL_EC_HWCONTROL. - This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. - This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ } LL_USART_InitTypeDef; @@ -115,20 +122,23 @@ typedef struct uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. This parameter can be a value of @ref USART_LL_EC_POLARITY. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). For more details, refer to description of this function. */ uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref USART_LL_EC_PHASE. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). For more details, refer to description of this function. */ uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). For more details, refer to description of this function. */ } LL_USART_ClockInitTypeDef; @@ -147,22 +157,24 @@ typedef struct * @brief Flags defines which can be used with LL_USART_WriteReg function * @{ */ -#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ -#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected flag */ -#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ -#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ -#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ #if defined(USART_TCBGT_SUPPORT) -#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */ +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ #endif /* USART_TCBGT_SUPPORT */ -#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */ -#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ -#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */ -#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */ -#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ #if defined(USART_CR1_UESM) -#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ +#if defined(USART_CR3_WUFIE) +#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ /** * @} @@ -192,7 +204,9 @@ typedef struct #define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ #define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) #define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ #define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ #if defined(USART_ISR_REACK) @@ -221,7 +235,9 @@ typedef struct #define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ #define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) #define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ #if defined(USART_TCBGT_SUPPORT) #define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ @@ -406,6 +422,7 @@ typedef struct */ #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUS) /** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation * @{ */ @@ -416,6 +433,7 @@ typedef struct * @} */ +#endif /* USART_CR3_WUS */ #endif /* USART_CR1_UESM */ /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power * @{ @@ -568,7 +586,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) * @brief USART enabled in STOP Mode. * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that * USART clock selection is HSI or LSE in RCC. - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR1 UESM LL_USART_EnableInStopMode * @param USARTx USART Instance @@ -582,7 +600,7 @@ __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) /** * @brief USART disabled in STOP Mode. * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR1 UESM LL_USART_DisableInStopMode * @param USARTx USART Instance @@ -595,7 +613,7 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) /** * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode * @param USARTx USART Instance @@ -876,7 +894,7 @@ __STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) /** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput * @param USARTx USART Instance @@ -893,7 +911,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3 /** * @brief Retrieve Clock pulse of the last data bit output configuration * (Last bit Clock pulse output to the SCLK pin or not) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput * @param USARTx USART Instance @@ -908,7 +926,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) /** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_SetClockPhase * @param USARTx USART Instance @@ -924,7 +942,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc /** * @brief Return phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_GetClockPhase * @param USARTx USART Instance @@ -939,7 +957,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) /** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_SetClockPolarity * @param USARTx USART Instance @@ -955,7 +973,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C /** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_GetClockPolarity * @param USARTx USART Instance @@ -970,7 +988,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) /** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function @@ -998,7 +1016,7 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, /** * @brief Enable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput * @param USARTx USART Instance @@ -1011,7 +1029,7 @@ __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) /** * @brief Disable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput * @param USARTx USART Instance @@ -1024,7 +1042,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) /** * @brief Indicate if Clock output on SCLK pin is enabled - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput * @param USARTx USART Instance @@ -1243,7 +1261,7 @@ __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx) /** * @brief Enable Auto Baud-Rate Detection - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate * @param USARTx USART Instance @@ -1256,7 +1274,7 @@ __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) /** * @brief Disable Auto Baud-Rate Detection - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate * @param USARTx USART Instance @@ -1269,7 +1287,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) /** * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud * @param USARTx USART Instance @@ -1282,7 +1300,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx) /** * @brief Set Auto Baud-Rate mode bits - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode * @param USARTx USART Instance @@ -1300,7 +1318,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_ /** * @brief Return Auto Baud-Rate mode - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode * @param USARTx USART Instance @@ -1407,7 +1425,7 @@ __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx) /** * @brief Enable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl * @param USARTx USART Instance @@ -1420,7 +1438,7 @@ __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Disable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl * @param USARTx USART Instance @@ -1433,7 +1451,7 @@ __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Enable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl * @param USARTx USART Instance @@ -1446,7 +1464,7 @@ __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Disable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl * @param USARTx USART Instance @@ -1459,7 +1477,7 @@ __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Configure HW Flow Control mode (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n * CR3 CTSE LL_USART_SetHWFlowCtrl @@ -1478,7 +1496,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard /** * @brief Return HW Flow Control configuration (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n * CR3 CTSE LL_USART_GetHWFlowCtrl @@ -1561,9 +1579,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx) } #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUS) /** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUS LL_USART_SetWKUPType * @param USARTx USART Instance @@ -1580,7 +1599,7 @@ __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) /** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUS LL_USART_GetWKUPType * @param USARTx USART Instance @@ -1594,6 +1613,7 @@ __STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx) return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); } +#endif /* USART_CR3_WUS */ #endif /* USART_CR1_UESM */ /** * @brief Configure USART BRR register for achieving expected Baud Rate value. @@ -1615,7 +1635,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph uint32_t BaudRate) { uint32_t usartdiv; - register uint32_t brrtemp; + uint32_t brrtemp; if (OverSampling == LL_USART_OVERSAMPLING_8) { @@ -1645,8 +1665,8 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph */ __STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) { - register uint32_t usartdiv; - register uint32_t brrresult = 0x0U; + uint32_t usartdiv; + uint32_t brrresult = 0x0U; usartdiv = USARTx->BRR; @@ -1728,7 +1748,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx) /** * @brief Enable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_EnableIrda * @param USARTx USART Instance @@ -1741,7 +1761,7 @@ __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) /** * @brief Disable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_DisableIrda * @param USARTx USART Instance @@ -1754,7 +1774,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) /** * @brief Indicate if IrDA mode is enabled - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_IsEnabledIrda * @param USARTx USART Instance @@ -1767,7 +1787,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) /** * @brief Configure IrDA Power Mode (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode * @param USARTx USART Instance @@ -1783,7 +1803,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P /** * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode * @param USARTx USART Instance @@ -1799,7 +1819,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) /** * @brief Set Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler * @param USARTx USART Instance @@ -1814,7 +1834,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P /** * @brief Return Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler * @param USARTx USART Instance @@ -1835,7 +1855,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) /** * @brief Enable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK * @param USARTx USART Instance @@ -1848,7 +1868,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Disable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK * @param USARTx USART Instance @@ -1861,7 +1881,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Indicate if Smartcard NACK transmission is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK * @param USARTx USART Instance @@ -1874,7 +1894,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Enable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_EnableSmartcard * @param USARTx USART Instance @@ -1887,7 +1907,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) /** * @brief Disable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_DisableSmartcard * @param USARTx USART Instance @@ -1900,7 +1920,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) /** * @brief Indicate if Smartcard mode is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard * @param USARTx USART Instance @@ -1913,7 +1933,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) /** * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. * In transmission mode, it specifies the number of automatic retransmission retries, before @@ -1932,7 +1952,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, /** * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount * @param USARTx USART Instance @@ -1946,7 +1966,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USAR /** * @brief Set Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler * @param USARTx USART Instance @@ -1961,7 +1981,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3 /** * @brief Return Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler * @param USARTx USART Instance @@ -1975,7 +1995,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) /** * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime * @param USARTx USART Instance @@ -1990,7 +2010,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 /** * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime * @param USARTx USART Instance @@ -2011,7 +2031,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) /** * @brief Enable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex * @param USARTx USART Instance @@ -2024,7 +2044,7 @@ __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) /** * @brief Disable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex * @param USARTx USART Instance @@ -2037,7 +2057,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) /** * @brief Indicate if Single Wire Half-Duplex mode is enabled - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex * @param USARTx USART Instance @@ -2058,7 +2078,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) /** * @brief Set LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen * @param USARTx USART Instance @@ -2074,7 +2094,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3 /** * @brief Return LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen * @param USARTx USART Instance @@ -2089,7 +2109,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) /** * @brief Enable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_EnableLIN * @param USARTx USART Instance @@ -2102,7 +2122,7 @@ __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) /** * @brief Disable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_DisableLIN * @param USARTx USART Instance @@ -2115,7 +2135,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) /** * @brief Indicate if LIN mode is enabled - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN * @param USARTx USART Instance @@ -2136,7 +2156,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) /** * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime * @param USARTx USART Instance @@ -2150,7 +2170,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32 /** * @brief Return DEDT (Driver Enable De-Assertion Time) - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime * @param USARTx USART Instance @@ -2163,7 +2183,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx) /** * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime * @param USARTx USART Instance @@ -2177,7 +2197,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t /** * @brief Return DEAT (Driver Enable Assertion Time) - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime * @param USARTx USART Instance @@ -2190,7 +2210,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx) /** * @brief Enable Driver Enable (DE) Mode - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEM LL_USART_EnableDEMode * @param USARTx USART Instance @@ -2203,7 +2223,7 @@ __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) /** * @brief Disable Driver Enable (DE) Mode - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEM LL_USART_DisableDEMode * @param USARTx USART Instance @@ -2216,7 +2236,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) /** * @brief Indicate if Driver Enable (DE) Mode is enabled - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode * @param USARTx USART Instance @@ -2229,7 +2249,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx) /** * @brief Select Driver Enable Polarity - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity * @param USARTx USART Instance @@ -2245,7 +2265,7 @@ __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_ /** * @brief Return Driver Enable Polarity - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity * @param USARTx USART Instance @@ -2309,7 +2329,7 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the USART in Synchronous mode. - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2348,7 +2368,7 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also set the UART/USART in LIN mode. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function @@ -2389,7 +2409,7 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) * - SCEN bit in the USART_CR3 register, * - IREN bit in the USART_CR3 register, * This function also sets the UART/USART in Half Duplex mode. - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2429,7 +2449,7 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) * This function also configures Stop bits to 1.5 bits and * sets the USART in Smartcard mode (SCEN bit). * Clock Output is also enabled (CLKEN). - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2472,7 +2492,7 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) * - SCEN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the UART/USART in IRDA mode (IREN bit). - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2640,7 +2660,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) /** * @brief Check if the USART LIN Break Detection Flag is set or not - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD * @param USARTx USART Instance @@ -2653,7 +2673,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) /** * @brief Check if the USART CTS interrupt Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS * @param USARTx USART Instance @@ -2666,7 +2686,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) /** * @brief Check if the USART CTS Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS * @param USARTx USART Instance @@ -2690,7 +2710,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx) /** * @brief Check if the USART End Of Block Flag is set or not - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB * @param USARTx USART Instance @@ -2703,7 +2723,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx) /** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE * @param USARTx USART Instance @@ -2716,7 +2736,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) /** * @brief Check if the USART Auto-Baud Rate Flag is set or not - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR * @param USARTx USART Instance @@ -2772,9 +2792,10 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) } #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) /** * @brief Check if the USART Wake Up from stop mode Flag is set or not - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP * @param USARTx USART Instance @@ -2785,6 +2806,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx) return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); } +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ /** * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not @@ -2906,7 +2928,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) /** * @brief Clear LIN Break Detection Flag - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD * @param USARTx USART Instance @@ -2919,7 +2941,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) /** * @brief Clear CTS Interrupt Flag - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS * @param USARTx USART Instance @@ -2943,7 +2965,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) /** * @brief Clear End Of Block Flag - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB * @param USARTx USART Instance @@ -2966,9 +2988,10 @@ __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) } #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) /** * @brief Clear Wake Up from stop mode Flag - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP * @param USARTx USART Instance @@ -2979,6 +3002,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) WRITE_REG(USARTx->ICR, USART_ICR_WUCF); } +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ /** * @} @@ -3067,7 +3091,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) /** * @brief Enable End Of Block Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB * @param USARTx USART Instance @@ -3080,7 +3104,7 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) /** * @brief Enable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD * @param USARTx USART Instance @@ -3108,7 +3132,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) /** * @brief Enable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS * @param USARTx USART Instance @@ -3120,9 +3144,10 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) } #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) /** * @brief Enable Wake Up from Stop Mode Interrupt - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP * @param USARTx USART Instance @@ -3133,12 +3158,13 @@ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) SET_BIT(USARTx->CR3, USART_CR3_WUFIE); } +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ #if defined(USART_TCBGT_SUPPORT) /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT * @param USARTx USART Instance @@ -3229,7 +3255,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) /** * @brief Disable End Of Block Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB * @param USARTx USART Instance @@ -3242,7 +3268,7 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) /** * @brief Disable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD * @param USARTx USART Instance @@ -3270,7 +3296,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) /** * @brief Disable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS * @param USARTx USART Instance @@ -3282,9 +3308,10 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) } #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) /** * @brief Disable Wake Up from Stop Mode Interrupt - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP * @param USARTx USART Instance @@ -3295,12 +3322,13 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); } +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ #if defined(USART_TCBGT_SUPPORT) /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT * @param USARTx USART Instance @@ -3391,7 +3419,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx) /** * @brief Check if the USART End Of Block Interrupt is enabled or disabled. - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB * @param USARTx USART Instance @@ -3404,7 +3432,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx) /** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD * @param USARTx USART Instance @@ -3428,7 +3456,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) /** * @brief Check if the USART CTS Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS * @param USARTx USART Instance @@ -3440,9 +3468,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) } #if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) /** * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP * @param USARTx USART Instance @@ -3453,12 +3482,13 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx) return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); } +#endif /* USART_CR3_WUFIE */ #endif /* USART_CR1_UESM */ #if defined(USART_TCBGT_SUPPORT) /* Function available only on devices supporting Transmit Complete before Guard Time feature */ /** * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT * @param USARTx USART Instance @@ -3589,7 +3619,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx */ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction) { - register uint32_t data_reg_addr; + uint32_t data_reg_addr; if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) { @@ -3669,7 +3699,7 @@ __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Valu /** * @brief Request an Automatic Baud Rate measurement on next received data frame - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate * @param USARTx USART Instance @@ -3717,7 +3747,7 @@ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) /** * @brief Request a Transmit data flush - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush * @param USARTx USART Instance diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usb.c index cb59bad1a7..17d4ed3f82 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usb.c @@ -65,8 +65,8 @@ static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx); */ /** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization/de-initialization functions ##### @@ -119,7 +119,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Select vbus source */ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); - /* Select UTMI Interace */ + /* Select UTMI Interface */ USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN; @@ -142,7 +142,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - /* Reset after a PHY select and set Host mode */ + /* Reset after a PHY select */ ret = USB_CoreReset(USBx); /* Activate the USB Transceiver */ @@ -259,7 +259,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status -*/ + */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; @@ -267,13 +267,12 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) } /** - * @brief USB_SetCurrentMode : Set functional mode + * @brief USB_SetCurrentMode Set functional mode * @param USBx Selected device - * @param mode current core mode + * @param mode current core mode * This parameter can be one of these values: - * @arg USB_DEVICE_MODE: Peripheral mode - * @arg USB_HOST_MODE: Host mode - * @arg USB_DRD_MODE: Dual Role Device mode + * @arg USB_DEVICE_MODE Peripheral mode + * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) @@ -298,7 +297,7 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy } /** - * @brief USB_DevInit : Initializes the USB_OTG controller registers + * @brief USB_DevInit Initializes the USB_OTG controller registers * for device mode * @param USBx Selected device * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains @@ -485,8 +484,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { return HAL_TIMEOUT; } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); return HAL_OK; } @@ -508,8 +506,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { return HAL_TIMEOUT; } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); return HAL_OK; } @@ -538,8 +535,8 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) * @param USBx Selected device * @retval speed device speed * This parameter can be one of these values: - * @arg PCD_SPEED_HIGH: High speed mode - * @arg PCD_SPEED_FULL: Full speed mode + * @arg USBD_HS_SPEED: High speed mode + * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { @@ -978,7 +975,8 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe * 1 : DMA feature used * @retval HAL status */ -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t *pSrc = (uint32_t *)src; @@ -1138,7 +1136,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t addres } /** - * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down + * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ @@ -1146,14 +1144,16 @@ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; - HAL_Delay(3U); return HAL_OK; } /** - * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down + * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ @@ -1161,8 +1161,10 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; - HAL_Delay(3U); return HAL_OK; } @@ -1255,7 +1257,7 @@ uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) /** * @brief USB_ClearInterrupts: clear a USB interrupt * @param USBx Selected device - * @param interrupt interrupt flag + * @param interrupt flag * @retval None */ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) @@ -1347,8 +1349,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { return HAL_TIMEOUT; } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); /* Core Soft Reset */ count = 0U; @@ -1360,8 +1361,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { return HAL_TIMEOUT; } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); return HAL_OK; } @@ -1556,7 +1556,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) } /** -* @brief USB_OTG_ResetPort : Reset Host Port + * @brief USB_OTG_ResetPort : Reset Host Port * @param USBx Selected device * @retval HAL status * @note (1)The application must wait at least 10 ms @@ -1585,10 +1585,10 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) * @brief USB_DriveVbus : activate or de-activate vbus * @param state VBUS state * This parameter can be one of these values: - * 0 : VBUS Active - * 1 : VBUS Inactive + * 0 : Deactivate VBUS + * 1 : Activate VBUS * @retval HAL status -*/ + */ HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1632,7 +1632,7 @@ uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) * @brief Return Host Current Frame number * @param USBx Selected device * @retval current frame number -*/ + */ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1661,20 +1661,17 @@ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) * @arg EP_TYPE_BULK: Bulk type * @arg EP_TYPE_INTR: Interrupt type * @param mps Max Packet Size - * This parameter can be a value from 0 to32K + * This parameter can be a value from 0 to 32K * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps) { HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t HCcharEpDir, HCcharLowSpeed; + uint32_t HostCoreSpeed; /* Clear old interrupt conditions for this host channel. */ USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; @@ -1699,7 +1696,8 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, { if ((USBx->CID & (0x1U << 8)) != 0U) { - USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM; } } break; @@ -1753,7 +1751,10 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, HCcharEpDir = 0U; } - if (speed == HPRT0_PRTSPD_LOW_SPEED) + HostCoreSpeed = USB_GetHostSpeed(USBx); + + /* LS device plugged to HUB */ + if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) { HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; } @@ -1789,7 +1790,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t ch_num = (uint32_t)hc->ch_num; - static __IO uint32_t tmpreg = 0U; + __IO uint32_t tmpreg; uint8_t is_oddframe; uint16_t len_words; uint16_t num_packets; @@ -1797,20 +1798,20 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED)) { + /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ + if ((dma == 1U) && ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK))) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NAKM); + } + if ((dma == 0U) && (hc->do_ping == 1U)) { (void)USB_DoPing(USBx, hc->ch_num); return HAL_OK; } - else if (dma == 1U) - { - USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); - hc->do_ping = 0U; - } - else - { - /* ... */ - } + } /* Compute the expected number of packets associated to the transfer */ @@ -1821,20 +1822,29 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe if (num_packets > max_hc_pkt_count) { num_packets = max_hc_pkt_count; - hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; } } else { num_packets = 1U; } + + /* + * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of + * max_packet size. + */ if (hc->ep_is_in != 0U) { - hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; } /* Initialize the HCTSIZn register */ - USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | + USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) | (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); @@ -1864,45 +1874,47 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe tmpreg |= USB_OTG_HCCHAR_CHENA; USBx_HC(ch_num)->HCCHAR = tmpreg; - if (dma == 0U) /* Slave mode */ + if (dma != 0U) /* dma mode */ { - if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + return HAL_OK; + } + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + { + switch (hc->ep_type) { - switch (hc->ep_type) - { - /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: - len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); - /* check if there is enough space in FIFO space */ - if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) - { - /* need to process data in nptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; - } - break; + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); - /* check if there is enough space in FIFO space */ - if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; - } - break; + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; - default: - break; - } - - /* Write packet into the Tx FIFO. */ - (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); + default: + break; } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); } return HAL_OK; @@ -1933,29 +1945,38 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) uint32_t hcnum = (uint32_t)hc_num; uint32_t count = 0U; uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; + + if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && + (ChannelEna == 0U)) + { + return HAL_OK; + } /* Check for space in the request queue to issue the halt. */ if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) { - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; - do + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) { - if (++count > 1000U) + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + do { - break; - } + if (++count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } - while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - else - { - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } else @@ -1973,8 +1994,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { break; } - } - while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { @@ -2054,8 +2074,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) { break; } - } - while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } /* Clear any pending Host interrupts */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usb.h index 6d3769c88b..95042b2610 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_usb.h @@ -81,7 +81,7 @@ typedef enum } USB_OTG_HCStateTypeDef; /** - * @brief USB OTG Initialization Structure definition + * @brief USB Instance Initialization Structure definition */ typedef struct { @@ -94,14 +94,14 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed_ */ + This parameter can be any value of @ref USB_Core_Speed */ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY_ */ + This parameter can be any value of @ref USB_Core_PHY */ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ @@ -116,6 +116,7 @@ typedef struct uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + } USB_OTG_CfgTypeDef; typedef struct @@ -185,6 +186,8 @@ typedef struct uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + uint32_t XferSize; /*!< OTG Channel transfer size. */ + uint32_t xfer_len; /*!< Current transfer length. */ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ @@ -197,13 +200,13 @@ typedef struct uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ - uint32_t ErrCnt; /*!< Host channel error count.*/ + uint32_t ErrCnt; /*!< Host channel error count. */ USB_OTG_URBStateTypeDef urb_state; /*!< URB state. This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ USB_OTG_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ + This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ } USB_OTG_HCTypeDef; #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -318,10 +321,10 @@ typedef struct /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define DEP0CTL_MPS_64 0U -#define DEP0CTL_MPS_32 1U -#define DEP0CTL_MPS_16 2U -#define DEP0CTL_MPS_8 3U +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U /** * @} */ @@ -408,7 +411,7 @@ typedef struct #define USBPHYC ((USBPHYC_GlobalTypeDef *)((uint32_t )USB_PHY_HS_CONTROLLER_BASE)) #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#define EP_ADDR_MSK 0xFU +#define EP_ADDR_MSK 0xFU /** * @} */ @@ -448,7 +451,9 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma); + void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); @@ -476,7 +481,9 @@ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, + USB_OTG_HCTypeDef *hc, uint8_t dma); + uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_utils.c index 0717d8970a..4ac57c0002 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_utils.c @@ -193,7 +193,6 @@ */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); -static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency); static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_PLL_IsBusy(void); /** @@ -316,6 +315,161 @@ void LL_SetSystemCoreClock(uint32_t HCLKFrequency) SystemCoreClock = HCLKFrequency; } +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V + * @param HCLK_Frequency HCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) +{ + uint32_t timeout; + uint32_t getlatency; + uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ + ErrorStatus status = SUCCESS; + + /* Frequency cannot be equal to 0 */ + if(HCLK_Frequency == 0U) + { + status = ERROR; + } + else + { + if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + { + if(LL_PWR_IsEnabledOverDriveMode() != 0U) + { + if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ) + { + /* 210 < HCLK <= 216 => 7WS (8 CPU cycles) */ + latency = LL_FLASH_LATENCY_7; + } + else /* (HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) */ + { + /* 180 < HCLK <= 210 => 6WS (7 CPU cycles) */ + latency = LL_FLASH_LATENCY_6; + } + } + if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) && (latency == LL_FLASH_LATENCY_0)) + { + /* 150 < HCLK <= 180 => 5WS (6 CPU cycles) */ + latency = LL_FLASH_LATENCY_5; + } + else if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (latency == LL_FLASH_LATENCY_0)) + { + /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (latency == LL_FLASH_LATENCY_0)) + { + /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (latency == LL_FLASH_LATENCY_0)) + { + /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (latency == LL_FLASH_LATENCY_0)) + { + /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */ + } + } + else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) + { + if(HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ) + { + /* 150 < HCLK <= 168 OR 150 < HCLK <= 180 (when OverDrive mode is enable) => 5WS (6 CPU cycles) */ + latency = LL_FLASH_LATENCY_5; + } + else if(HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ) + { + /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) + { + /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) + { + /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) + { + /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */ + } + } + else /* Scale 3 */ + { + if(HCLK_Frequency > UTILS_SCALE3_LATENCY4_FREQ) + { + /* 120 < HCLK <= 144 => 4WS (5 CPU cycles) */ + latency = LL_FLASH_LATENCY_4; + } + else if(HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) + { + /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ + latency = LL_FLASH_LATENCY_3; + } + else if(HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) + { + /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ + latency = LL_FLASH_LATENCY_2; + } + else + { + if(HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) + { + /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + /* else HCLK_Frequency < 22MHz default LL_FLASH_LATENCY_0 0WS */ + } + } + + if (status != ERROR) + { + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + timeout = 2; + do + { + /* Wait for Flash latency to be updated */ + getlatency = LL_FLASH_GetLatency(); + timeout--; + } while ((getlatency != latency) && (timeout > 0)); + + if(getlatency != latency) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + } + return status; +} + /** * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL * @note The application need to ensure that PLL is disabled. @@ -454,145 +608,6 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa /** @addtogroup UTILS_LL_Private_Functions * @{ */ -/** - * @brief Update number of Flash wait states in line with new frequency and current - voltage range. - * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V - * @param HCLK_Frequency HCLK frequency - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified - */ -static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency) -{ - ErrorStatus status = SUCCESS; - - uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ - - /* Frequency cannot be equal to 0 */ - if(HCLK_Frequency == 0U) - { - status = ERROR; - } - else - { - if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) - { - if(LL_PWR_IsEnabledOverDriveMode() != 0U) - { - if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ) - { - /* 210 < HCLK <= 216 => 7WS (8 CPU cycles) */ - latency = LL_FLASH_LATENCY_7; - } - else /* (HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) */ - { - /* 180 < HCLK <= 210 => 6WS (7 CPU cycles) */ - latency = LL_FLASH_LATENCY_6; - } - } - if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) && (latency == LL_FLASH_LATENCY_0)) - { - /* 150 < HCLK <= 180 => 5WS (6 CPU cycles) */ - latency = LL_FLASH_LATENCY_5; - } - else if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (latency == LL_FLASH_LATENCY_0)) - { - /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */ - latency = LL_FLASH_LATENCY_4; - } - else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (latency == LL_FLASH_LATENCY_0)) - { - /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (latency == LL_FLASH_LATENCY_0)) - { - /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (latency == LL_FLASH_LATENCY_0)) - { - /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */ - } - } - else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) - { - if(HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ) - { - /* 150 < HCLK <= 168 OR 150 < HCLK <= 180 (when OverDrive mode is enable) => 5WS (6 CPU cycles) */ - latency = LL_FLASH_LATENCY_5; - } - else if(HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ) - { - /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */ - latency = LL_FLASH_LATENCY_4; - } - else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) - { - /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) - { - /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) - { - /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */ - } - } - else /* Scale 3 */ - { - if(HCLK_Frequency > UTILS_SCALE3_LATENCY4_FREQ) - { - /* 120 < HCLK <= 144 => 4WS (5 CPU cycles) */ - latency = LL_FLASH_LATENCY_4; - } - else if(HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) - { - /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if(HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) - { - /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) - { - /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency < 22MHz default LL_FLASH_LATENCY_0 0WS */ - } - } - - LL_FLASH_SetLatency(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(LL_FLASH_GetLatency() != latency) - { - status = ERROR; - } - } - return status; -} - /** * @brief Function to check that PLL can be modified * @param PLL_InputFrequency PLL input frequency (in Hz) @@ -682,7 +697,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if(SystemCoreClock < hclk_frequency) { /* Set FLASH latency to highest latency */ - status = UTILS_SetFlashLatency(hclk_frequency); + status = LL_SetFlashLatency(hclk_frequency); } /* Update system clock configuration */ @@ -712,7 +727,7 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ if(SystemCoreClock > hclk_frequency) { /* Set FLASH latency to lowest latency */ - status = UTILS_SetFlashLatency(hclk_frequency); + status = LL_SetFlashLatency(hclk_frequency); } /* Update SystemCoreClock variable */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_utils.h index e9a8b3439d..fdf925cc27 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_utils.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_ll_utils.h @@ -275,6 +275,7 @@ void LL_mDelay(uint32_t Delay); */ void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/stm32f7xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/stm32f7xx_hal_conf.h index 8ac84dbda1..e4ef4b02ef 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/stm32f7xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/stm32f7xx_hal_conf.h @@ -2,11 +2,11 @@ ****************************************************************************** * @file stm32f7xx_hal_conf.h * @author MCD Application Team - * @brief HAL configuration file. + * @brief HAL configuration template file. ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. + *

© Copyright (c) 2021 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -33,9 +33,9 @@ * @brief This is the list of modules to be used in the HAL driver */ #define HAL_MODULE_ENABLED -#define HAL_ADC_MODULE_ENABLED -// MBED: use the legacy module for now -// #define HAL_CAN_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +// MBED: use the legacy module for now +/* #define HAL_CAN_MODULE_ENABLED */ #define HAL_CAN_LEGACY_MODULE_ENABLED #define HAL_CEC_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED @@ -149,155 +149,155 @@ #define ART_ACCLERATOR_ENABLE 1U /* To enable ART Accelerator */ #if !defined (USE_HAL_ADC_REGISTER_CALLBACKS) - #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ #endif #if !defined (USE_HAL_CAN_REGISTER_CALLBACKS) - #define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ #endif #if !defined (USE_HAL_CEC_REGISTER_CALLBACKS) - #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ #endif #if !defined (USE_HAL_CRYP_REGISTER_CALLBACKS) - #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ #endif #if !defined (USE_HAL_DAC_REGISTER_CALLBACKS) - #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ #endif #if !defined (USE_HAL_DCMI_REGISTER_CALLBACKS) - #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ #endif #if !defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) - #define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ #endif #if !defined (USE_HAL_DMA2D_REGISTER_CALLBACKS) - #define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ #endif #if !defined (USE_HAL_DSI_REGISTER_CALLBACKS) - #define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ #endif #if !defined (USE_HAL_ETH_REGISTER_CALLBACKS) - #define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ #endif #if !defined (USE_HAL_HASH_REGISTER_CALLBACKS) - #define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ #endif #if !defined (USE_HAL_HCD_REGISTER_CALLBACKS) - #define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ #endif #if !defined (USE_HAL_I2C_REGISTER_CALLBACKS) - #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ #endif #if !defined (USE_HAL_I2S_REGISTER_CALLBACKS) - #define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ #endif #if !defined (USE_HAL_IRDA_REGISTER_CALLBACKS) - #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ #endif #if !defined (USE_HAL_JPEG_REGISTER_CALLBACKS) - #define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ #endif #if !defined (USE_HAL_LPTIM_REGISTER_CALLBACKS) - #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ #endif #if !defined (USE_HAL_LTDC_REGISTER_CALLBACKS) - #define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ #endif #if !defined (USE_HAL_MDIOS_REGISTER_CALLBACKS) - #define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ #endif #if !defined (USE_HAL_MMC_REGISTER_CALLBACKS) - #define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ #endif #if !defined (USE_HAL_NAND_REGISTER_CALLBACKS) - #define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ #endif #if !defined (USE_HAL_NOR_REGISTER_CALLBACKS) - #define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ #endif #if !defined (USE_HAL_PCD_REGISTER_CALLBACKS) - #define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ #endif #if !defined (USE_HAL_QSPI_REGISTER_CALLBACKS) - #define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ #endif #if !defined (USE_HAL_RNG_REGISTER_CALLBACKS) - #define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ #endif #if !defined (USE_HAL_RTC_REGISTER_CALLBACKS) - #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ #endif #if !defined (USE_HAL_SAI_REGISTER_CALLBACKS) - #define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ #endif #if !defined (USE_HAL_SD_REGISTER_CALLBACKS) - #define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ #endif #if !defined (USE_HAL_SMARTCARD_REGISTER_CALLBACKS) - #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ #endif #if !defined (USE_HAL_SDRAM_REGISTER_CALLBACKS) - #define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ #endif #if !defined (USE_HAL_SRAM_REGISTER_CALLBACKS) - #define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ #endif #if !defined (USE_HAL_SPDIFRX_REGISTER_CALLBACKS) - #define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ #endif #if !defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) - #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ #endif #if !defined (USE_HAL_SPI_REGISTER_CALLBACKS) - #define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ #endif #if !defined (USE_HAL_TIM_REGISTER_CALLBACKS) - #define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ #endif #if !defined (USE_HAL_UART_REGISTER_CALLBACKS) - #define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ #endif #if !defined (USE_HAL_USART_REGISTER_CALLBACKS) - #define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ #endif #if !defined (USE_HAL_WWDG_REGISTER_CALLBACKS) - #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ #endif /* ########################## Assert Selection ############################## */ @@ -309,7 +309,9 @@ /* ################## Ethernet peripheral configuration ##################### */ -/* Definition of the Ethernet driver buffers size and count */ +/* Section 1 : Ethernet peripheral configuration */ + +/* Definition of the Ethernet driver buffers size and count */ #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ @@ -324,14 +326,15 @@ #endif /* Section 2: PHY configuration section */ - /* PHY delay */ #ifdef MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY #define PHY_RESET_DELAY MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY #else #define PHY_RESET_DELAY 0 #endif +/* PHY Configuration delay */ #define PHY_CONFIG_DELAY 0x00000FFFU + #define PHY_READ_TO 0x0000FFFFU #define PHY_WRITE_TO 0x0000FFFFU @@ -339,7 +342,6 @@ #define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ #define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ - #define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ #define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/system_stm32f7xx.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/system_stm32f7xx.c index a5a396f8db..12ce6e1eaa 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/system_stm32f7xx.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/system_stm32f7xx.c @@ -73,11 +73,27 @@ /************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS RAMDTCM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ /** @@ -133,18 +149,18 @@ */ __weak void SystemInit(void) { +#include "nvic_addr.h" // MBED + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED + /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ #endif - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else -#include "nvic_addr.h" // MBED - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED -#endif + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ } /** diff --git a/targets/TARGET_STM/TARGET_STM32F7/can_device.h b/targets/TARGET_STM/TARGET_STM32F7/can_device.h index 006bd78074..31a4811684 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32F7/can_device.h @@ -71,4 +71,8 @@ extern "C" { #endif // DEVICE_CAN +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/i2c_device.c b/targets/TARGET_STM/TARGET_STM32F7/i2c_device.c new file mode 100755 index 0000000000..6eb967be51 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F7/i2c_device.c @@ -0,0 +1,150 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "i2c_device.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "stm32f7xx_ll_rcc.h" + +/* Define I2C Device */ +#if DEVICE_I2C + +/** + * @brief Get I2C clock source frequency according I2C instance used. + * @param i2c I2C instance name. + * @retval I2C clock source frequency in Hz. + */ +uint32_t i2c_get_pclk(I2CName i2c) +{ + uint32_t clocksource; + uint32_t pclk = 0; + if (i2c == I2C_1) { + clocksource = __HAL_RCC_GET_I2C1_SOURCE(); + switch (clocksource) { + case RCC_I2C1CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C1CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C1CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#if defined I2C2_BASE + else if (i2c == I2C_2) { + clocksource = __HAL_RCC_GET_I2C2_SOURCE(); + switch (clocksource) { + case RCC_I2C2CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C2CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C2CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif +#if defined I2C3_BASE + else if (i2c == I2C_3) { + clocksource = __HAL_RCC_GET_I2C3_SOURCE(); + switch (clocksource) { + case RCC_I2C3CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C3CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C3CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif +#if defined I2C4_BASE + else if (i2c == I2C_4) { + clocksource = __HAL_RCC_GET_I2C4_SOURCE(); + switch (clocksource) { + case RCC_I2C4CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C4CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C4CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif + else { + // should not happend + error("I2C: unknown instance"); + } + return pclk; +} + +/** + * @brief Provide the suitable timing depending on requested frequency + * @param hz Required I2C clock in Hz. + * @retval I2C timing or 0 in case of error. + */ +uint32_t i2c_get_timing(I2CName i2c, int hz) +{ + uint32_t tim; + uint32_t pclk; + pclk = i2c_get_pclk(i2c); + if (pclk == I2C_PCLK_DEF) { + switch (hz) { + case 100000: + tim = TIMING_VAL_DEFAULT_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_DEFAULT_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_DEFAULT_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } else { + /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. + User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. + Enabling this may impact performance*/ + MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO); +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + tim = i2c_compute_timing(pclk, hz); +#endif + } + return tim; +} + +/** + * @} + */ +#endif // DEVICE_I2C diff --git a/targets/TARGET_STM/TARGET_STM32F7/i2c_device.h b/targets/TARGET_STM/TARGET_STM32F7/i2c_device.h index 3bfbc23c86..8bc86a3106 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32F7/i2c_device.h @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2015-2021, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -27,17 +27,25 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ******************************************************************************* */ + #ifndef MBED_I2C_DEVICE_H #define MBED_I2C_DEVICE_H -#include "cmsis.h" +#include "PeripheralNames.h" #ifdef __cplusplus extern "C" { #endif +/* Define I2C Device */ #if DEVICE_I2C +#define TIMING_VAL_DEFAULT_CLK_100KHZ 0x10916998 // Standard mode with Rise time = 120ns, Fall time = 120ns +#define TIMING_VAL_DEFAULT_CLK_400KHZ 0x00B11B54 // Fast Mode with Rise time = 120ns, Fall time = 120ns +#define TIMING_VAL_DEFAULT_CLK_1MHZ 0x0090091B // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns +#define I2C_PCLK_DEF 54000000 // 54 MHz + +/* Define IP version */ #define I2C_IP_VERSION_V2 #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI) @@ -48,40 +56,19 @@ extern "C" { #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_PCLK1 #define I2CAPI_I2C4_CLKSRC RCC_I2C4CLKSOURCE_PCLK1 -/* Provide the suitable timing depending on requested frequencie */ -static inline uint32_t get_i2c_timing(int hz) -{ - uint32_t tim = 0; - /* - Values calculated with I2C_Timing_Configuration tool (excel file) - * Standard mode (up to 100 kHz) - * Fast Mode (up to 400 kHz) - * Fast Mode Plus (up to 1 MHz) - Below values obtained with: - - I2Cx clock source = APB1CLK = 54 MHz - - Analog filter delay = ON - - Digital filter coefficient = 0 - */ - switch (hz) { - case 100000: - tim = 0x10916998; // Standard mode with Rise time = 120ns, Fall time = 120ns - break; - case 400000: - tim = 0x00B11B54; // Fast Mode with Rise time = 120ns, Fall time = 120ns - break; - case 1000000: - tim = 0x0090091B; // Fast Mode Plus with Rise time = 120ns, Fall time = 10ns - break; - default: - break; - } - return tim; -} +uint32_t i2c_get_pclk(I2CName i2c); +uint32_t i2c_get_timing(I2CName i2c, int hz); + +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq); +void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t I2C_speed); +uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t I2C_speed); +#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + +#endif // DEVICE_I2C #ifdef __cplusplus } #endif -#endif // DEVICE_I2C - #endif diff --git a/targets/TARGET_STM/TARGET_STM32F7/objects.h b/targets/TARGET_STM/TARGET_STM32F7/objects.h index 006e4f38d8..4809402224 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/objects.h +++ b/targets/TARGET_STM/TARGET_STM32F7/objects.h @@ -129,6 +129,9 @@ struct i2c_s { uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32G0/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G0/CMakeLists.txt index 697a933c3e..6fabba85b5 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G0/CMakeLists.txt @@ -17,6 +17,7 @@ target_sources(mbed-stm32g0 analogout_device.c flash_api.c gpio_irq_device.c + i2c_device.c pwmout_device.c serial_device.c spi_api.c diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/cmsis_nvic.h index 86a986e6f9..8045b5a794 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G030xx/cmsis_nvic.h @@ -23,8 +23,8 @@ #if !defined(MBED_ROM_SIZE) #define MBED_ROM_SIZE 0x10000 - // 0x10000 STM32G030K8Tx STM32G030C8Tx - // 0x8000 STM32G030F6Px STM32G030K6Tx STM32G030C6Tx STM32G030J6Mx +// 0x10000 STM32G030K8Tx STM32G030C8Tx +// 0x8000 STM32G030F6Px STM32G030K6Tx STM32G030C6Tx STM32G030J6Mx #endif #if !defined(MBED_RAM_START) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c index e2f541a310..6d20b8a9e4 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G031xx/TARGET_NUCLEO_G031K8/system_clock.c @@ -99,6 +99,7 @@ uint8_t SetSysClock_PLL_HSI(void) /** Configure the main internal regulator output voltage */ + __HAL_RCC_PWR_CLK_ENABLE(); HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); /** Initializes the CPU, AHB and APB busses clocks */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/cmsis_nvic.h index 2c6795b12d..4c135e696f 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G041xx/cmsis_nvic.h @@ -23,8 +23,8 @@ #if !defined(MBED_ROM_SIZE) #define MBED_ROM_SIZE 0x10000 - // 0x10000 STM32G041Y8Yx STM32G041K8Ux STM32G041C8Ux STM32G041C8Tx STM32G041K8Tx STM32G041G8Ux STM32G041F8Px - // 0x8000 STM32G041G6Ux STM32G041K6Tx STM32G041C6Tx STM32G041J6Mx STM32G041K6Ux STM32G041C6Ux STM32G041F6Px +// 0x10000 STM32G041Y8Yx STM32G041K8Ux STM32G041C8Ux STM32G041C8Tx STM32G041K8Tx STM32G041G8Ux STM32G041F8Px +// 0x8000 STM32G041G6Ux STM32G041K6Tx STM32G041C6Tx STM32G041J6Mx STM32G041K6Ux STM32G041C6Ux STM32G041F6Px #endif #if !defined(MBED_RAM_START) diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c index 5b79cdf058..996533d115 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/TARGET_NUCLEO_G071RB/system_clock.c @@ -97,6 +97,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) /** Configure the main internal regulator output voltage */ + __HAL_RCC_PWR_CLK_ENABLE(); HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); /** Initializes the CPU, AHB and APB busses clocks */ @@ -139,6 +140,7 @@ uint8_t SetSysClock_PLL_HSI(void) /** Configure the main internal regulator output voltage */ + __HAL_RCC_PWR_CLK_ENABLE(); HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); /** Initializes the CPU, AHB and APB busses clocks */ diff --git a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h index 02e1da1b2e..49b2a4318a 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32G0/TARGET_STM32G071xx/cmsis_nvic.h @@ -25,9 +25,9 @@ #if defined (TARGET_NUCLEO_G071RB) #define MBED_ROM_SIZE 0x20000 #else - // 0x10000 STM32G071C8Ux STM32G071K8TxN STM32G071R8Tx STM32G071K8Ux STM32G071G8UxN STM32G071C8Tx STM32G071K8Tx STM32G071K8UxN STM32G071G8Ux - // 0x8000 STM32G071K6Tx STM32G071G6Ux STM32G071C6Tx STM32G071K6Ux STM32G071R6Tx STM32G071C6Ux - // 0x20000 STM32G071GBUxN STM32G071CBUx STM32G071KBTx STM32G071KBUxN STM32G071RBTx STM32G071EBYx STM32G071GBUx STM32G071CBTx STM32G071KBUx STM32G071RBIx STM32G071KBTxN +// 0x10000 STM32G071C8Ux STM32G071K8TxN STM32G071R8Tx STM32G071K8Ux STM32G071G8UxN STM32G071C8Tx STM32G071K8Tx STM32G071K8UxN STM32G071G8Ux +// 0x8000 STM32G071K6Tx STM32G071G6Ux STM32G071C6Tx STM32G071K6Ux STM32G071R6Tx STM32G071C6Ux +// 0x20000 STM32G071GBUxN STM32G071CBUx STM32G071KBTx STM32G071KBUxN STM32G071RBTx STM32G071EBYx STM32G071GBUx STM32G071CBTx STM32G071KBUx STM32G071RBIx STM32G071KBTxN #error "MBED_ROM_SIZE not defined" #endif #endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/i2c_device.c b/targets/TARGET_STM/TARGET_STM32G0/i2c_device.c new file mode 100755 index 0000000000..f9a60d3af3 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G0/i2c_device.c @@ -0,0 +1,96 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "i2c_device.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "stm32g0xx_ll_rcc.h" + +/* Define I2C Device */ +#if DEVICE_I2C + +/** + * @brief Get I2C clock source frequency according I2C instance used. + * @param i2c I2C instance name. + * @retval I2C clock source frequency in Hz. + */ +uint32_t i2c_get_pclk(I2CName i2c) +{ + uint32_t clocksource; + uint32_t pclk = 0; + if (i2c == I2C_1) { + clocksource = __HAL_RCC_GET_I2C1_SOURCE(); + switch (clocksource) { + case RCC_I2C1CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C1CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C1CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } else { + // should not happend + error("I2C: unknown instance"); + } + return pclk; +} + +/** + * @brief Provide the suitable timing depending on requested frequency + * @param hz Required I2C clock in Hz. + * @retval I2C timing or 0 in case of error. + */ +uint32_t i2c_get_timing(I2CName i2c, int hz) +{ + uint32_t tim; + uint32_t pclk; + pclk = i2c_get_pclk(i2c); + if (pclk == I2C_PCLK_DEF) { + switch (hz) { + case 100000: + tim = TIMING_VAL_DEFAULT_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_DEFAULT_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_DEFAULT_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } else { + /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. + User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. + Enabling this may impact performance*/ + MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO); +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + tim = i2c_compute_timing(pclk, hz); +#endif + } + return tim; +} + +/** + * @} + */ + +#endif // DEVICE_I2C diff --git a/targets/TARGET_STM/TARGET_STM32G0/i2c_device.h b/targets/TARGET_STM/TARGET_STM32G0/i2c_device.h index 21d527549c..ec808d37a7 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32G0/i2c_device.h @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2015 STMicroelectronics. + * Copyright (c) 2015-2021 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -12,19 +12,27 @@ * ****************************************************************************** */ + #ifndef MBED_I2C_DEVICE_H #define MBED_I2C_DEVICE_H -#include "cmsis.h" +#include "PeripheralNames.h" #ifdef __cplusplus extern "C" { #endif +/* Define IP version */ #if DEVICE_I2C -#define I2C_IP_VERSION_V2 +// Common settings: I2C clock = 64 MHz, Analog filter = ON, Digital filter coefficient = 0 +#define TIMING_VAL_DEFAULT_CLK_100KHZ 0xC0311319 // Standard mode with Rise Time = 400ns and Fall Time = 100ns +#define TIMING_VAL_DEFAULT_CLK_400KHZ 0x10B1102E // Fast mode with Rise Time = 250ns and Fall Time = 100ns +#define TIMING_VAL_DEFAULT_CLK_1MHZ 0x00710B1E // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns +#define I2C_PCLK_DEF 64000000 // 64 MHz +/* Define IP version */ +#define I2C_IP_VERSION_V2 #define I2C1_EV_IRQn I2C1_IRQn #define I2C1_ER_IRQn I2C1_IRQn @@ -32,39 +40,25 @@ extern "C" { #define I2C2_EV_IRQn I2C2_IRQn #define I2C2_ER_IRQn I2C2_IRQn - - #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI) /* Family specifc settings for clock source */ #define I2CAPI_I2C1_CLKSRC RCC_I2C1CLKSOURCE_SYSCLK #define I2CAPI_I2C2_CLKSRC RCC_I2C2CLKSOURCE_SYSCLK -/* Provide the suitable timing depending on requested frequencie */ -static inline uint32_t get_i2c_timing(int hz) -{ - uint32_t tim = 0; - // Common settings: I2C clock = 64 MHz, Analog filter = ON, Digital filter coefficient = 0 - switch (hz) { - case 100000: - tim = 0xC0311319; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - tim = 0x10B1102E; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - tim = 0x00710B1E; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - return tim; -} +uint32_t i2c_get_pclk(I2CName i2c); +uint32_t i2c_get_timing(I2CName i2c, int hz); + +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq); +void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t I2C_speed); +uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t I2C_speed); +#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + +#endif // DEVICE_I2C #ifdef __cplusplus } #endif -#endif // DEVICE_I2C - #endif diff --git a/targets/TARGET_STM/TARGET_STM32G0/objects.h b/targets/TARGET_STM/TARGET_STM32G0/objects.h index 3f9ecf736c..638d4e8725 100644 --- a/targets/TARGET_STM/TARGET_STM32G0/objects.h +++ b/targets/TARGET_STM/TARGET_STM32G0/objects.h @@ -112,6 +112,9 @@ struct i2c_s { uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32G4/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G4/CMakeLists.txt index 298030962a..a670385d2d 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G4/CMakeLists.txt @@ -18,6 +18,7 @@ target_sources(mbed-stm32g4 analogout_device.c flash_api.c gpio_irq_device.c + i2c_device.c pwmout_device.c serial_device.c spi_api.c diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g471xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g471xx.h index 284c344992..9a3fe226de 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g471xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g471xx.h @@ -152,6 +152,7 @@ typedef enum I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */ I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */ DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */ + QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */ DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */ DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */ DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */ @@ -586,6 +587,26 @@ typedef struct __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */ } PWR_TypeDef; +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; /** * @brief Reset and Clock Control @@ -955,7 +976,9 @@ typedef struct #define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */ #define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(32 KB) base address */ #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */ +#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */ #define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */ #define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */ #define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(32 KB) base address in the bit-band region */ @@ -1242,6 +1265,7 @@ typedef struct #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE) +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) @@ -7492,6 +7516,203 @@ typedef struct #define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */ #define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< selection for Main Regulator in Range1 */ +/******************************************************************************/ +/* */ +/* QUADSPI */ +/* */ +/******************************************************************************/ +/***************** Bit definition for QUADSPI_CR register *******************/ +#define QUADSPI_CR_EN_Pos (0U) +#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */ +#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */ +#define QUADSPI_CR_ABORT_Pos (1U) +#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */ +#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */ +#define QUADSPI_CR_DMAEN_Pos (2U) +#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */ +#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */ +#define QUADSPI_CR_TCEN_Pos (3U) +#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */ +#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */ +#define QUADSPI_CR_SSHIFT_Pos (4U) +#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */ +#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */ +#define QUADSPI_CR_DFM_Pos (6U) +#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */ +#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */ +#define QUADSPI_CR_FSEL_Pos (7U) +#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ +#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */ +#define QUADSPI_CR_FTHRES_Pos (8U) +#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */ +#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ +#define QUADSPI_CR_TEIE_Pos (16U) +#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ +#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ +#define QUADSPI_CR_TCIE_Pos (17U) +#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */ +#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */ +#define QUADSPI_CR_FTIE_Pos (18U) +#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */ +#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */ +#define QUADSPI_CR_SMIE_Pos (19U) +#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */ +#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */ +#define QUADSPI_CR_TOIE_Pos (20U) +#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */ +#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */ +#define QUADSPI_CR_APMS_Pos (22U) +#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */ +#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */ +#define QUADSPI_CR_PMM_Pos (23U) +#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */ +#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */ +#define QUADSPI_CR_PRESCALER_Pos (24U) +#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */ +#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */ + +/***************** Bit definition for QUADSPI_DCR register ******************/ +#define QUADSPI_DCR_CKMODE_Pos (0U) +#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */ +#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */ +#define QUADSPI_DCR_CSHT_Pos (8U) +#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */ +#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */ +#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */ +#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */ +#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */ +#define QUADSPI_DCR_FSIZE_Pos (16U) +#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */ +#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */ + +/****************** Bit definition for QUADSPI_SR register *******************/ +#define QUADSPI_SR_TEF_Pos (0U) +#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */ +#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */ +#define QUADSPI_SR_TCF_Pos (1U) +#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */ +#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */ +#define QUADSPI_SR_FTF_Pos (2U) +#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */ +#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */ +#define QUADSPI_SR_SMF_Pos (3U) +#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */ +#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */ +#define QUADSPI_SR_TOF_Pos (4U) +#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */ +#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */ +#define QUADSPI_SR_BUSY_Pos (5U) +#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */ +#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */ +#define QUADSPI_SR_FLEVEL_Pos (8U) +#define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */ +#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */ + +/****************** Bit definition for QUADSPI_FCR register ******************/ +#define QUADSPI_FCR_CTEF_Pos (0U) +#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */ +#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */ +#define QUADSPI_FCR_CTCF_Pos (1U) +#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */ +#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */ +#define QUADSPI_FCR_CSMF_Pos (3U) +#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */ +#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */ +#define QUADSPI_FCR_CTOF_Pos (4U) +#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */ +#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */ + +/****************** Bit definition for QUADSPI_DLR register ******************/ +#define QUADSPI_DLR_DL_Pos (0U) +#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */ +#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */ + +/****************** Bit definition for QUADSPI_CCR register ******************/ +#define QUADSPI_CCR_INSTRUCTION_Pos (0U) +#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */ +#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */ +#define QUADSPI_CCR_IMODE_Pos (8U) +#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */ +#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */ +#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */ +#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */ +#define QUADSPI_CCR_ADMODE_Pos (10U) +#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */ +#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */ +#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */ +#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */ +#define QUADSPI_CCR_ADSIZE_Pos (12U) +#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */ +#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */ +#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */ +#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */ +#define QUADSPI_CCR_ABMODE_Pos (14U) +#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */ +#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */ +#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */ +#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */ +#define QUADSPI_CCR_ABSIZE_Pos (16U) +#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */ +#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */ +#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */ +#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */ +#define QUADSPI_CCR_DCYC_Pos (18U) +#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */ +#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */ +#define QUADSPI_CCR_DMODE_Pos (24U) +#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */ +#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */ +#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */ +#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */ +#define QUADSPI_CCR_FMODE_Pos (26U) +#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */ +#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */ +#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */ +#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */ +#define QUADSPI_CCR_SIOO_Pos (28U) +#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */ +#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */ +#define QUADSPI_CCR_DHHC_Pos (30U) +#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */ +#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */ +#define QUADSPI_CCR_DDRM_Pos (31U) +#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */ +#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */ + +/****************** Bit definition for QUADSPI_AR register *******************/ +#define QUADSPI_AR_ADDRESS_Pos (0U) +#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)/*!< 0xFFFFFFFF */ +#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */ + +/****************** Bit definition for QUADSPI_ABR register ******************/ +#define QUADSPI_ABR_ALTERNATE_Pos (0U) +#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)/*!< 0xFFFFFFFF */ +#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */ + +/****************** Bit definition for QUADSPI_DR register *******************/ +#define QUADSPI_DR_DATA_Pos (0U) +#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */ +#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */ + +/****************** Bit definition for QUADSPI_PSMKR register ****************/ +#define QUADSPI_PSMKR_MASK_Pos (0U) +#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)/*!< 0xFFFFFFFF */ +#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */ + +/****************** Bit definition for QUADSPI_PSMAR register ****************/ +#define QUADSPI_PSMAR_MATCH_Pos (0U) +#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)/*!< 0xFFFFFFFF */ +#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */ + +/****************** Bit definition for QUADSPI_PIR register *****************/ +#define QUADSPI_PIR_INTERVAL_Pos (0U) +#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */ +#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */ + +/****************** Bit definition for QUADSPI_LPTR register *****************/ +#define QUADSPI_LPTR_TIMEOUT_Pos (0U) +#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */ +#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */ /******************************************************************************/ /* */ @@ -13131,6 +13352,8 @@ typedef struct /******************************** PCD Instances *******************************/ #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) +/******************************* QSPI Instances *******************************/ +#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI) /******************************* RNG Instances ********************************/ #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g474xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g474xx.h index b536688af7..46563790fa 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g474xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g474xx.h @@ -1120,7 +1120,6 @@ typedef struct typedef struct { HRTIM_Master_TypeDef sMasterRegs; HRTIM_Timerx_TypeDef sTimerxRegs[6]; -// uint32_t RESERVED0[32]; HRTIM_Common_TypeDef sCommonRegs; }HRTIM_TypeDef; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g484xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g484xx.h index f62b205955..402b8e3c43 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g484xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g484xx.h @@ -1152,7 +1152,6 @@ typedef struct typedef struct { HRTIM_Master_TypeDef sMasterRegs; HRTIM_Timerx_TypeDef sTimerxRegs[6]; -// uint32_t RESERVED0[32]; HRTIM_Common_TypeDef sCommonRegs; }HRTIM_TypeDef; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g4xx.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g4xx.h index 1ae1a7be20..65d3559e0a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g4xx.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMSIS/stm32g4xx.h @@ -85,11 +85,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.2.0 + * @brief CMSIS Device version number V1.2.1 */ #define __STM32G4_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G4_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ -#define __STM32G4_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32G4_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32G4_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G4_CMSIS_VERSION ((__STM32G4_CMSIS_VERSION_MAIN << 24)\ |(__STM32G4_CMSIS_VERSION_SUB1 << 16)\ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMakeLists.txt index bc60f7b0a9..7943337699 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/CMakeLists.txt @@ -52,6 +52,7 @@ target_sources(mbed-stm32g4cube-fw STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.c STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard_ex.c STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus.c + STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus_ex.c STM32G4xx_HAL_Driver/stm32g4xx_hal_spi.c STM32G4xx_HAL_Driver/stm32g4xx_hal_spi_ex.c STM32G4xx_HAL_Driver/stm32g4xx_hal_sram.c diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/Legacy/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/Legacy/stm32_hal_legacy.h index 1b36402b6a..299ed70498 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/Legacy/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/Legacy/stm32_hal_legacy.h @@ -23,7 +23,7 @@ #define STM32_HAL_LEGACY #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -38,7 +38,6 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - /** * @} */ @@ -315,6 +314,11 @@ #if defined(STM32G0) #define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 #define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 +#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM +#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM + +#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM +#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM #endif #if defined(STM32H7) @@ -591,24 +595,24 @@ #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/ #if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 @@ -769,49 +773,6 @@ #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) -/** @brief Constants defining the events that can be selected to configure the - * set/reset crossbar of a timer output - */ -#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) -#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) -#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) -#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) -#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) -#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) -#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) -#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) -#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) - -#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) -#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) -#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) -#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) -#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) -#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) -#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) -#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) -#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) - -/** @brief Constants defining the event filtering applied to external events - * by a timer - */ -#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) - /** @brief Constants defining the DLL calibration periods (in micro seconds) */ #define HRTIM_CALIBRATIONRATE_7300 0x00000000U @@ -964,6 +925,11 @@ #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif /** * @} @@ -975,15 +941,15 @@ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #if defined(STM32H7) - #define I2S_IT_TXE I2S_IT_TXP - #define I2S_IT_RXNE I2S_IT_RXP +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP - #define I2S_FLAG_TXE I2S_FLAG_TXP - #define I2S_FLAG_RXNE I2S_FLAG_RXP +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP #endif #if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** * @} @@ -1018,7 +984,7 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ @@ -1118,16 +1084,16 @@ #if defined(STM32H7) - #define SPI_FLAG_TXE SPI_FLAG_TXP - #define SPI_FLAG_RXNE SPI_FLAG_RXP +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP - #define SPI_IT_TXE SPI_IT_TXP - #define SPI_IT_RXNE SPI_IT_RXP +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP - #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET - #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET - #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET - #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET #endif /* STM32H7 */ @@ -1454,7 +1420,7 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY -#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End @@ -1476,7 +1442,7 @@ #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT -#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */ +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1490,7 +1456,8 @@ #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1498,7 +1465,8 @@ #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode @@ -1521,9 +1489,9 @@ #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - /** +/** * @} - */ + */ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ @@ -1533,7 +1501,8 @@ #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ + )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT @@ -1558,9 +1527,9 @@ #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA #endif /* STM32F4 */ - /** +/** * @} - */ + */ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ @@ -1615,9 +1584,9 @@ #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - /** +/** * @} - */ + */ /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ @@ -1866,15 +1835,15 @@ #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC #if defined(STM32H7) - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 #else - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG #endif /* STM32H7 */ #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT @@ -2085,8 +2054,8 @@ */ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) /** * @} @@ -2142,7 +2111,7 @@ #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT #if defined(STM32H7) - #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG #endif /** @@ -2279,7 +2248,8 @@ #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -3247,7 +3217,7 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3376,7 +3346,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3396,19 +3366,19 @@ #else #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ #define IS_ALARM IS_RTC_ALARM @@ -3592,6 +3562,13 @@ #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal.c index 304cef8955..b6b85a7bf5 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal.c @@ -49,11 +49,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32G4xx HAL Driver version number V1.2.0 + * @brief STM32G4xx HAL Driver version number V1.2.1 */ #define __STM32G4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32G4xx_HAL_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */ -#define __STM32G4xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32G4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32G4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32G4xx_HAL_VERSION ((__STM32G4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32G4xx_HAL_VERSION_SUB1 << 16U)\ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.c index 1c05daeab9..01e6636862 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.c @@ -325,8 +325,7 @@ #define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\ ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ - ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated - when no regular conversion is on-going */ + ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */ /* Timeout values for ADC operations (enable settling time, */ /* disable settling time, ...). */ @@ -501,7 +500,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -874,31 +873,28 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) */ ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc); - } - /* DeInit the low level hardware. - - For example: - __HAL_RCC_ADC_FORCE_RESET(); - __HAL_RCC_ADC_RELEASE_RESET(); - __HAL_RCC_ADC_CLK_DISABLE(); - - Keep in mind that all ADCs use the same clock: disabling - the clock will reset all ADCs. - - */ + /* ========== Hard reset ADC peripheral ========== */ + /* Performs a global reset of the entire ADC peripherals instances */ + /* sharing the same common ADC instance: ADC state is forced to */ + /* a similar state as after device power-on. */ + /* Note: A possible implementation is to add RCC bus reset of ADC */ + /* (for example, using macro */ + /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */ + /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - if (hadc->MspDeInitCallback == NULL) - { - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - } + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } - /* DeInit the low level hardware: RCC clock, NVIC */ - hadc->MspDeInitCallback(hadc); + /* DeInit the low level hardware */ + hadc->MspDeInitCallback(hadc); #else - /* DeInit the low level hardware: RCC clock, NVIC */ - HAL_ADC_MspDeInit(hadc); + /* DeInit the low level hardware */ + HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); @@ -973,7 +969,8 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, + pADC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -1499,13 +1496,17 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -1615,13 +1616,17 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -2404,7 +2409,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ /* to determine if conversion has been triggered from EOC or EOS, */ /* possibility to use: */ - /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ + /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else @@ -2459,44 +2464,46 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ - if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || - ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && - ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && - (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) + if (tmp_adc_inj_is_trigger_source_sw_start != 0UL) { - /* If End of Sequence is reached, disable interrupts */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) || + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))) { - /* Particular case if injected contexts queue is enabled: */ - /* when the last context has been fully processed, JSQR is reset */ - /* by the hardware. Even if no injected conversion is planned to come */ - /* (queue empty, triggers are ignored), it can start again */ - /* immediately after setting a new context (JADSTART is still set). */ - /* Therefore, state of HAL ADC injected group is kept to busy. */ - if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) + /* If End of Sequence is reached, disable interrupts */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { - /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ - /* JADSTART==0 (no conversion on going) */ - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + /* Particular case if injected contexts queue is enabled: */ + /* when the last context has been fully processed, JSQR is reset */ + /* by the hardware. Even if no injected conversion is planned to come */ + /* (queue empty, triggers are ignored), it can start again */ + /* immediately after setting a new context (JADSTART is still set). */ + /* Therefore, state of HAL ADC injected group is kept to busy. */ + if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) { - /* Disable ADC end of sequence conversion interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ + /* JADSTART==0 (no conversion on going) */ + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* Disable ADC end of sequence conversion interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } } } } @@ -2504,8 +2511,8 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* Injected Conversion complete callback */ /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to - if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or - if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether + if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or + if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether interruption has been triggered by end of conversion or end of sequence. */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) @@ -2760,7 +2767,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmpOffsetShifted; uint32_t tmp_config_internal_channel; - __IO uint32_t wait_loop_index = 0; + __IO uint32_t wait_loop_index = 0UL; uint32_t tmp_adc_is_conversion_on_going_regular; uint32_t tmp_adc_is_conversion_on_going_injected; @@ -2849,19 +2856,23 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } @@ -2913,7 +2924,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -3388,13 +3399,17 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } @@ -3404,8 +3419,6 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio return HAL_OK; } - - /** * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled @@ -3424,7 +3437,8 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) { /* Check if conditions to enable the ADC are fulfilled */ - if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) + if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART + | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); @@ -3458,13 +3472,17 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -3518,13 +3536,17 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.h index 30160c3ad7..7013801a7a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc.h @@ -384,7 +384,7 @@ typedef struct typedef struct __ADC_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ { ADC_TypeDef *Instance; /*!< Register base address */ ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ @@ -769,7 +769,6 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @} */ - /** @defgroup ADC_Event_type ADC Event type * @{ */ @@ -1239,7 +1238,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #else #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ ((__HANDLE__)->State = HAL_ADC_STATE_RESET) -#endif +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ /** * @brief Enable ADC interrupt. @@ -1667,7 +1666,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Helper macro to select the ADC common instance @@ -1738,10 +1737,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ - __ADC_RESOLUTION_TARGET__) \ - __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \ - (__ADC_RESOLUTION_CURRENT__), \ - (__ADC_RESOLUTION_TARGET__)) + __ADC_RESOLUTION_TARGET__) \ +__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ + (__ADC_RESOLUTION_CURRENT__),\ + (__ADC_RESOLUTION_TARGET__)) /** * @brief Helper macro to calculate the voltage (unit: mVolt) @@ -1761,10 +1760,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ - __ADC_RESOLUTION__) \ - __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \ - (__ADC_DATA__), \ - (__ADC_RESOLUTION__)) + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ + (__ADC_DATA__),\ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate analog reference voltage (Vref+) @@ -1792,9 +1791,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @retval Analog reference voltage (unit: mV) */ #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \ - (__ADC_RESOLUTION__)) + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -1843,10 +1842,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \ - (__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__)) + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -1897,13 +1896,13 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to __TEMPSENSOR_CALX_TEMP__,\ __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \ - (__TEMPSENSOR_TYP_CALX_V__), \ - (__TEMPSENSOR_CALX_TEMP__), \ - (__VREFANALOG_VOLTAGE__), \ - (__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__)) + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ + (__TEMPSENSOR_TYP_CALX_V__),\ + (__TEMPSENSOR_CALX_TEMP__),\ + (__VREFANALOG_VOLTAGE__),\ + (__TEMPSENSOR_ADC_DATA__),\ + (__ADC_RESOLUTION__)) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.c index 65d3983ef7..9fdf1aad3b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.c @@ -62,8 +62,7 @@ #define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\ ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\ - ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime - once the ADC is enabled */ + ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */ /* Fixed timeout value for ADC calibration. */ /* Values defined to be higher than worst cases: low clock frequency, */ @@ -227,7 +226,8 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t Single * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) * @retval HAL state */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor) +HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, + uint32_t CalibrationFactor) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tmp_adc_is_conversion_on_going_regular; @@ -523,13 +523,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -885,6 +889,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t /* Process locked */ __HAL_LOCK(hadc); + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -1000,6 +1008,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -1027,13 +1039,20 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_ERROR; + return HAL_ERROR; + } } tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); @@ -1484,6 +1503,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -1511,13 +1534,20 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_ERROR; + return HAL_ERROR; + } } tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); @@ -1957,19 +1987,23 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I { /* Scan each offset register to check if the selected channel is targeted. */ /* If this is the case, the corresponding offset number is disabled. */ - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); } - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); } - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); } - if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) + if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) + == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel)) { LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); } @@ -1990,7 +2024,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) { /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); + LL_ADC_SetChannelSamplingTime(hadc->Instance, + (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime); } } @@ -2021,7 +2057,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -2080,7 +2116,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; - ADC_HandleTypeDef tmphadcSlave; + ADC_HandleTypeDef tmphadcSlave; uint32_t tmphadcSlave_conversion_on_going; /* Check the parameters */ @@ -2095,6 +2131,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ /* Process locked */ __HAL_LOCK(hadc); + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + ADC_MULTI_SLAVE(hadc, &tmphadcSlave); if (tmphadcSlave.Instance == NULL) diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.h index d23015b69c..2223be4431 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_adc_ex.h @@ -393,7 +393,7 @@ typedef struct ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ ADC_SMPR1_SMP0) -#endif +#endif /* ADC_SMPR1_SMPPLUS */ /** * @} */ @@ -482,7 +482,7 @@ typedef struct ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) -#endif +#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ /** * @brief Set the selected injected Channel rank. @@ -490,7 +490,8 @@ typedef struct * @param __RANKNB__ Rank number. * @retval None */ -#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) +#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\ + & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) /** * @brief Configure ADC injected context queue @@ -658,7 +659,7 @@ typedef struct #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5)) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) -#endif +#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ /** * @brief Verify the ADC instance connected to the battery voltage VBAT. @@ -838,7 +839,7 @@ typedef struct ((__CHANNEL__) == ADC_CHANNEL_16) || \ ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \ ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))) -#endif +#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */ /** * @brief Verify the ADC channel setting in differential mode. @@ -1360,7 +1361,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected); +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, + ADC_InjectionConfTypeDef *sConfigInjected); #if defined(ADC_MULTIMODE_SUPPORT) HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); #endif /* ADC_MULTIMODE_SUPPORT */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.c index 5397c4ca45..e523b6a6f6 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.c @@ -363,7 +363,8 @@ __weak void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, void (* pCallback)(CORDIC_HandleTypeDef *_hcordic)) +HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, + void (* pCallback)(CORDIC_HandleTypeDef *_hcordic)) { HAL_StatusTypeDef status = HAL_OK; @@ -525,8 +526,8 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H */ /** @defgroup CORDIC_Exported_Functions_Group2 Peripheral Control functions - * @brief Control functions. - * + * @brief Control functions. + * @verbatim ============================================================================== ##### Peripheral Control functions ##### @@ -602,7 +603,8 @@ HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_Con * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout) +HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t Timeout) { uint32_t tickstart; uint32_t index; @@ -659,8 +661,7 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *p return HAL_ERROR; } } - } - while (HAL_IS_BIT_CLR(hcordic->Instance->CSR, CORDIC_CSR_RRDY)); + } while (HAL_IS_BIT_CLR(hcordic->Instance->CSR, CORDIC_CSR_RRDY)); /* Read output data from Read Data register, and increment output buffer pointer */ CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff); @@ -696,7 +697,8 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *p * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout) +HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t Timeout) { uint32_t tickstart; uint32_t index; @@ -788,7 +790,8 @@ HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t * @param NbCalc Number of CORDIC calculation to process. * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc) +HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc) { int32_t *tmp_pInBuff = pInBuff; @@ -879,7 +882,8 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t * DMA transfer to and from the Peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection) +HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t DMADirection) { uint32_t sizeinbuff; uint32_t sizeoutbuff; @@ -1026,8 +1030,8 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_ */ /** @defgroup CORDIC_Exported_Functions_Group3 Callback functions - * @brief Callback functions. - * + * @brief Callback functions. + * @verbatim ============================================================================== ##### Callback functions ##### @@ -1077,8 +1081,8 @@ __weak void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic) */ /** @defgroup CORDIC_Exported_Functions_Group4 IRQ handler management - * @brief IRQ handler. - * + * @brief IRQ handler. + * @verbatim ============================================================================== ##### IRQ handler management ##### @@ -1147,8 +1151,8 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic) */ /** @defgroup CORDIC_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim ============================================================================== ##### Peripheral State functions ##### diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.h index 53eacadab7..d415b756fe 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cordic.h @@ -198,15 +198,21 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2)) #define CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) #define CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) -#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) #define CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3)) #define CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0)) #define CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1)) -#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) #define CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2)) -#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) -#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) -#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) +#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ + |CORDIC_CSR_PRECISION_0)) /** * @} */ @@ -257,7 +263,8 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one 32-bit data input (Q1.31 format), or two 16-bit - data input (Q1.15 format) packed in one 32 bits Data */ + data input (Q1.15 format) packed in one 32 bits + Data */ #define CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input (Q1.31 format) */ /** @@ -269,7 +276,8 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one 32-bit data output (Q1.31 format), or two 16-bit - data output (Q1.15 format) packed in one 32 bits Data */ + data output (Q1.15 format) packed in one 32 bits + Data */ #define CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output (Q1.31 format) */ /** @@ -329,9 +337,9 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET) @@ -346,7 +354,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @retval None */ #define __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__)) + (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__)) /** * @brief Disable the CORDIC interrupt @@ -357,7 +365,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @retval None */ #define __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__)) + (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__)) /** @brief Check whether the specified CORDIC interrupt occurred or not. Dummy macro as no interrupt status flag. @@ -383,7 +391,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @retval SET (flag is set) or RESET (flag is reset) */ #define __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__) \ - ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__)) + ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear specified CORDIC status flag. Dummy macro as no flag can be cleared. @@ -403,7 +411,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @retval FlagStatus */ #define __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__)) + (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__)) /** * @} @@ -527,7 +535,8 @@ void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic); #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, pCORDIC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, + pCORDIC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID); /** * @} @@ -539,10 +548,14 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig); -HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout); -HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout); -HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc); -HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection); +HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t Timeout); +HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t Timeout); +HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc); +HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t DMADirection); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_crc.h index dd95f38c14..1db487c7bb 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_crc.h @@ -267,7 +267,6 @@ typedef struct #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) - #define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.c index b815b7086b..3db536beff 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.c @@ -6,7 +6,7 @@ * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: * + Initialization, de-initialization, set config and get config functions - * + DES/TDES, AES processing functions + * + AES processing functions * + DMA callback functions * + CRYP IRQ handler management * + Peripheral State functions @@ -32,8 +32,8 @@ (+++) Associate the initialized DMA handle to the CRYP DMA handle using __HAL_LINKDMA() (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() + interrupt on the two DMA channels. The output channel should have higher + priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). (#)Initialize the CRYP according to the specified parameters : (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit. @@ -44,9 +44,13 @@ (+++) In some specific configurations, the key is written by the application code out of the HAL scope. In that case, user can still resort to the HAL APIs as usual but must make sure that pKey pointer is set to NULL. + (##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication + algorithms) is in words or bytes. (##) The Header used only in AES GCM and CCM Algorithm for authentication. - (##) The HeaderSize The size of header buffer in word. - (##) The B0 block is the first authentication block used only in AES CCM mode. + (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field. + (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes. + (##) The B0 block is the first authentication block used only in AES CCM mode. + (##) The KeyIVConfigSkip used to process several messages in a row (please see more information below). (#)Three processing (encryption/decryption) functions are available: (##) Polling mode: encryption and decryption APIs are blocking functions @@ -194,11 +198,11 @@ [..] The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() + Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() to register an interrupt callback. [..] - Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks: + Function HAL_CRYP_RegisterCallback() allows to register following callbacks: (+) InCpltCallback : Input FIFO transfer completed callback. (+) OutCpltCallback : Output FIFO transfer completed callback. (+) ErrorCallback : callback for error detection. @@ -208,9 +212,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default + Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) InCpltCallback : Input FIFO transfer completed callback. @@ -220,13 +224,13 @@ (+) MspDeInitCallback : CRYP MspDeInit. [..] - By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET + By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET all callbacks are set to the corresponding weak functions : - examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback(). + examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when + reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit() keep and use the user MspInit/MspDeInit functions (registered beforehand) [..] @@ -235,8 +239,8 @@ in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit() - or @ref HAL_CRYP_Init() function. + using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit() + or HAL_CRYP_Init() function. [..] When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or @@ -321,6 +325,7 @@ #define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */ #define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */ #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ +#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in DMA mode */ #define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */ #define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */ @@ -345,9 +350,7 @@ * @{ */ -#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\ - (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\ - }while(0U) +#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__)) /** * @} @@ -361,6 +364,7 @@ */ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); +static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size); static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CRYP_DMAError(DMA_HandleTypeDef *hdma); @@ -370,6 +374,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); @@ -383,6 +388,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output); static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input); @@ -418,13 +424,13 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); (+) DeInitialize the CRYP MSP (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef Parameters which are configured in This section are : - (+) Key size - (+) Data Type : 32,16, 8 or 1bit - (+) AlgoMode : - - for CRYP1 peripheral : + (++) Key size + (++) Data Type : 32,16, 8 or 1bit + (++) AlgoMode : + (+++) for CRYP1 peripheral : ECB and CBC in DES/TDES Standard ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard. - - for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported. + (+++) for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported. (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef @endverbatim @@ -581,15 +587,17 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD __HAL_LOCK(hcryp); /* Set CRYP parameters */ - hcryp->Init.DataType = pConf->DataType; - hcryp->Init.pKey = pConf->pKey; - hcryp->Init.Algorithm = pConf->Algorithm; - hcryp->Init.KeySize = pConf->KeySize; - hcryp->Init.pInitVect = pConf->pInitVect; - hcryp->Init.Header = pConf->Header; - hcryp->Init.HeaderSize = pConf->HeaderSize; - hcryp->Init.B0 = pConf->B0; - hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; + hcryp->Init.DataType = pConf->DataType; + hcryp->Init.pKey = pConf->pKey; + hcryp->Init.Algorithm = pConf->Algorithm; + hcryp->Init.KeySize = pConf->KeySize; + hcryp->Init.pInitVect = pConf->pInitVect; + hcryp->Init.Header = pConf->Header; + hcryp->Init.HeaderSize = pConf->HeaderSize; + hcryp->Init.B0 = pConf->B0; + hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; + hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; + hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); @@ -655,7 +663,9 @@ HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD pConf->Header = hcryp->Init.Header ; pConf->HeaderSize = hcryp->Init.HeaderSize; pConf->B0 = hcryp->Init.B0; - pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit; + pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip; /* Process Unlocked */ __HAL_UNLOCK(hcryp); @@ -687,8 +697,8 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspInit could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspInit can be implemented in the user file */ } @@ -703,8 +713,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspDeInit could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspDeInit can be implemented in the user file */ } @@ -1185,7 +1195,7 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Input Pointer to the input buffer (plaintext) - * @param Size Length of the plaintext buffer in word. + * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field) * @param Output Pointer to the output buffer(ciphertext) * @param Timeout Specify Timeout value * @retval HAL status @@ -1285,7 +1295,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Input Pointer to the input buffer (ciphertext ) - * @param Size Length of the plaintext buffer in word. + * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field) * @param Output Pointer to the output buffer(plaintext) * @param Timeout Specify Timeout value * @retval HAL status @@ -1385,7 +1395,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Input Pointer to the input buffer (plaintext) - * @param Size Length of the plaintext buffer in word + * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field) * @param Output Pointer to the output buffer(ciphertext) * @retval HAL status */ @@ -1495,7 +1505,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Input Pointer to the input buffer (ciphertext ) - * @param Size Length of the plaintext buffer in word. + * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field) * @param Output Pointer to the output buffer(plaintext) * @retval HAL status */ @@ -1604,7 +1614,7 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Input Pointer to the input buffer (plaintext) - * @param Size Length of the plaintext buffer in word. + * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field) * @param Output Pointer to the output buffer(ciphertext) * @retval HAL status */ @@ -1731,7 +1741,7 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Input Pointer to the input buffer (ciphertext ) - * @param Size Length of the plaintext buffer in word + * @param Size Length of the plaintext buffer in bytes or words (depending upon DataWidthUnit field) * @param Output Pointer to the output buffer(plaintext) * @retval HAL status */ @@ -1869,7 +1879,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) /* Clear computation complete flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM)) { /* if header phase */ @@ -1882,18 +1892,6 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); } } - else if (hcryp->Init.Algorithm == CRYP_AES_CCM) - { - /* if header phase */ - if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount) - { - CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); - } - else /* if payload phase */ - { - CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); - } - } else /* AES Algorithm ECB,CBC or CTR*/ { CRYP_AES_IT(hcryp); @@ -1935,8 +1933,8 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_InCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_InCpltCallback can be implemented in the user file */ } @@ -1951,8 +1949,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_OutCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_OutCpltCallback can be implemented in the user file */ } @@ -1967,8 +1965,8 @@ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_ErrorCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_ErrorCallback can be implemented in the user file */ } /** @@ -2502,18 +2500,105 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) { CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + uint32_t loopcounter; + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ /* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); - /* Call input data transfer complete callback */ + if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) + { + /* DMA is disabled, CCF is meaningful. Wait for computation completion before moving forward */ + CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + if ((headersize_in_bytes % 16U) != 0U) + { + /* Write last words that couldn't be fed by DMA */ + hcryp->CrypHeaderCount = (uint16_t)((headersize_in_bytes / 16U) * 4U); + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + + /* Wait for computation completion before moving forward */ + CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); + } /* if ((headersize_in_bytes % 16U) != 0U) */ + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Initiate payload DMA IN and processed data DMA OUT transfers */ + (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp); + } + else + { + uint32_t algo; + /* ECB, CBC or CTR end of input data feeding + or + end of GCM/CCM payload data feeding through DMA */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + /* Don't call input data transfer complete callback only if + it remains some input data to write to the peripheral. + This case can only occur for GCM and CCM with a payload length + not a multiple of 16 bytes */ + if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \ + (((hcryp->Size) % 16U) != 0U))) + { + /* Call input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } /* if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) */ } /** @@ -2526,7 +2611,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) uint32_t count; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ uint32_t mode; CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -2577,46 +2662,31 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) hcryp->Instance->DINR = 0x0U; count++; } + /* Call input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); /*Read the output block from the output FIFO */ for (count = 0U; count < 4U; count++) { /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUTR; + temp[count] = hcryp->Instance->DOUTR; + } - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; + count = 0U; + while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (count<4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count]; hcryp->CrypOutCount++; + count++; } } @@ -2675,7 +2745,7 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param inputaddr address of the input buffer - * @param Size size of the input buffer, must be a multiple of 16. + * @param Size size of the input and output buffers in words, must be a multiple of 4 * @param outputaddr address of the output buffer * @retval None */ @@ -2733,6 +2803,43 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); } +/** + * @brief Set the DMA configuration and start the header DMA transfer + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param inputaddr address of the input buffer + * @param Size size of the input buffer in words, must be a multiple of 4 + * @retval None + */ +static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size) +{ + /* Set the CRYP DMA transfer complete callback */ + hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt; + + /* Set the DMA input error callback */ + hcryp->hdmain->XferErrorCallback = CRYP_DMAError; + + /* Mark that header is fed to the peripheral in DMA mode */ + hcryp->Phase = CRYP_PHASE_HEADER_DMA_FEED; + /* Enable the DMA input stream */ + if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK) + { + /* DMA error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + /* Call error callback */ + } + + /* Enable IN DMA requests */ + SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); + + return HAL_OK; +} + /** * @brief Process Data: Write Input data in polling mode and used in AES functions. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -3162,6 +3269,12 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t lastwordsize; uint32_t npblb; uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -3171,6 +3284,17 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) } #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + /* Manage header size given in bytes to handle cases where + header size is not a multiple of 4 bytes */ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { if (hcryp->KeyIVConfig == 1U) @@ -3284,7 +3408,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3335,42 +3459,58 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } - else if ((hcryp->Init.HeaderSize) < 4U) + /* Enter header data */ + /* Cher first whether header length is small enough to enter the full header in one shot */ + else if (headersize_in_bytes <= 16U) { - for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++) + /* Write header data, padded with zeros if need be */ + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + hcryp->CrypHeaderCount++ ; + /* Pad the data with zeros to have a complete block */ while (loopcounter < 4U) { - /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; loopcounter++; + hcryp->CrypHeaderCount++; + } } - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - - /* Call Input transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } else { - /* Write the input block in the IN FIFO */ + /* Write the first input header block in the Input FIFO, + the following header data will be fed after interrupt occurrence */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -3415,7 +3555,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3466,6 +3606,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -3482,12 +3630,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) */ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) { - __IO uint32_t count; - uint16_t wordsize = hcryp->Size / 4U ; - uint32_t index; - uint32_t npblb; - uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t count; uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) @@ -3566,122 +3709,16 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) return HAL_ERROR; } - /************************ Payload phase ************************************/ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - + } + else + { + /* Initialization and header phases already done, only do payload phase */ + if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } } /* if (DoKeyIVConfig == 1U) */ - if (hcryp->Size == 0U) - { - /* Process unLocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state and phase */ - hcryp->State = HAL_CRYP_STATE_READY; - } - else if (hcryp->Size >= 16U) - { - /*DMA transfer must not include the last block in case of Size is not %16 */ - wordsize = wordsize - (wordsize % 4U); - - /*DMA transfer */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr)); - } - else /* length of input data is < 16 */ - { - /* Compute the number of padding bytes in last block of payload */ - npblb = 16U - (uint32_t)hcryp->Size; - - /* Set Npblb in case of AES GCM payload encryption to get right tag*/ - if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) - { - /* Specify the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); - } - - /* Enable CRYP to start the final phase */ - __HAL_CRYP_ENABLE(hcryp); - - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } - - /* last block optionally pad the data with zeros*/ - for (index = 0U; index < lastwordsize; index ++) - { - /* Write the last Input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (index < 4U) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0U; - index++; - } - /* Wait for CCF flag to be raised */ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /*Read the output block from the output FIFO */ - for (index = 0U; index < 4U; index++) - { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp[index] = hcryp->Instance->DOUTR; - } - for (index = 0U; index < lastwordsize; index++) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; - hcryp->CrypOutCount++; - } - - /* Change the CRYP state to ready */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } - /* Return function status */ return HAL_OK; } @@ -4075,6 +4112,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */ @@ -4180,6 +4225,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -4196,12 +4249,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) */ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) { - __IO uint32_t count = 0U; - uint16_t wordsize = hcryp->Size / 4U ; - uint32_t index; - uint32_t npblb; - uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t count; uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) @@ -4282,119 +4330,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) return HAL_ERROR; } - /******************** Payload phase *****************************************/ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - - /* Select payload phase once the header phase is performed */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); - + } + else + { + /* Initialization and header phases already done, only do payload phase */ + if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } } /* if (DoKeyIVConfig == 1U) */ - if (hcryp->Size == 0U) - { - /* Process unLocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state and phase */ - hcryp->State = HAL_CRYP_STATE_READY; - } - else if (hcryp->Size >= 16U) - { - /*DMA transfer must not include the last block in case of Size is not %16 */ - wordsize = wordsize - (wordsize % 4U); - - /*DMA transfer */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr)); - } - else /* length of input data is < 16 */ - { - /* Compute the number of padding bytes in last block of payload */ - npblb = 16U - (uint32_t)hcryp->Size; - - /* Set Npblb in case of AES CCM payload decryption to get right tag*/ - if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) - { - /* Specify the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); - } - - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } - - /* last block optionally pad the data with zeros*/ - for (index = 0U; index < lastwordsize; index ++) - { - /* Write the last Input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (index < 4U) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0U; - index++; - } - /* Wait for CCF flag to be raised */ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /*Read the output block from the output FIFO */ - for (index = 0U; index < 4U; index++) - { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp[index] = hcryp->Instance->DOUTR; - } - for (index = 0U; index < lastwordsize; index++) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; - hcryp->CrypOutCount++; - } - - /* Change the CRYP state to ready */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } - /* Return function status */ return HAL_OK; } @@ -4493,9 +4438,9 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { - /* Call output transfer complete callback */ + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) /*Call registered Input complete callback*/ hcryp->InCpltCallback(hcryp); @@ -4541,10 +4486,151 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } +/** + * @brief Sets the payload phase in DMA mode + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval state + */ +static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp) +{ + uint16_t wordsize = hcryp->Size / 4U ; + uint32_t index; + uint32_t npblb; + uint32_t lastwordsize; + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t count; + uint32_t reg; + + /************************ Payload phase ************************************/ + if (hcryp->Size == 0U) + { + /* Process unLocked */ + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state and phase */ + hcryp->State = HAL_CRYP_STATE_READY; + } + else if (hcryp->Size >= 16U) + { + /*DMA transfer must not include the last block in case of Size is not %16 */ + wordsize = wordsize - (wordsize % 4U); + + /*DMA transfer */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr)); + } + else /* length of input data is < 16 */ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - (uint32_t)hcryp->Size; + + /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/ + reg = hcryp->Instance->CR & (AES_CR_CHMOD|AES_CR_MODE); + if ((reg == (CRYP_AES_GCM_GMAC|CRYP_OPERATINGMODE_ENCRYPT)) ||\ + (reg == (CRYP_AES_CCM|CRYP_OPERATINGMODE_DECRYPT))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* last block optionally pad the data with zeros*/ + for (index = 0U; index < lastwordsize; index ++) + { + /* Write the last Input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (index < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0U; + index++; + } + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /*Read the output block from the output FIFO */ + for (index = 0U; index < 4U; index++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + temp[index] = hcryp->Instance->DOUTR; + } + for (index = 0U; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + hcryp->CrypOutCount++; + } + + /* Change the CRYP state to ready */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + + /* Call Output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + /** * @brief Sets the header phase in polling mode * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -4557,7 +4643,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u uint32_t loopcounter; uint32_t size_in_bytes; uint32_t tmp; - uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU}; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -4659,9 +4747,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } else { - /* Enter last bytes, padded with zeroes */ + /* Enter last bytes, padded with zeros */ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[size_in_bytes % 4U]; + tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; hcryp->Instance->DINR = tmp; loopcounter++; /* Pad the data with zeros to have a complete block */ @@ -4691,17 +4779,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } else { - if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) - { - /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); + /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - } + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); } /* Return function status */ return HAL_OK; @@ -4715,143 +4800,112 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u */ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp) { - __IO uint32_t count = 0U; uint32_t loopcounter; + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ - if ((hcryp->Init.HeaderSize != 0U)) + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) { - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - if ((hcryp->Init.HeaderSize % 4U) == 0U) + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* If header size is at least equal to 16 bytes, feed the header through DMA. + If size_in_bytes is not a multiple of blocks (is not a multiple of four 32-bit words ), + last bytes feeding and padding will be done in CRYP_DMAInCplt() */ + if (headersize_in_bytes >= 16U) + { + /* Initiate header DMA transfer */ + if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK) { - /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) - { - /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - } - else - { - /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) - { - /* Write the Input block in the Data Input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - while (loopcounter < 4U) - { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - - /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + return HAL_ERROR; } } else { - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + if (headersize_in_bytes != 0U) + { + /* Header length is larger than 0 and strictly less than 16 bytes */ + /* Write last complete words */ + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + + if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + } /* if (headersize_in_bytes != 0U) */ + + /* Move to payload phase if header length is null or + if the header length was less than 16 and header written by software instead of DMA */ + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Initiate payload DMA IN and processed data DMA OUT transfers */ + if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + } /* if (headersize_in_bytes >= 16U) */ - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - } /* Return function status */ return HAL_OK; } @@ -4868,9 +4922,25 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) uint32_t lastwordsize; uint32_t npblb; uint32_t mode; + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } /***************************** Header phase *********************************/ - if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) + /* Test whether or not the header phase is over. + If the test below is true, move to payload phase */ + if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U)) { /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -4953,11 +5023,19 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } - else if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)) + else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)) { - + /* Can enter full 4 header words */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) /* If suspension flag has been raised, suspend processing only if not already at the end of the header */ @@ -4992,19 +5070,40 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypHeaderCount++; } } - else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/ + else /* Write last header block (4 words), padded with zeros if needed */ { - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) + + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + hcryp->CrypHeaderCount++; + /* Pad the data with zeros to have a complete block */ while (loopcounter < 4U) { - /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; loopcounter++; + hcryp->CrypHeaderCount++; + } } } } @@ -5014,6 +5113,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @param Timeout Timeout duration. + * @note This function can only be used in thread mode. * @retval HAL status */ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) @@ -5037,6 +5137,47 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T return HAL_OK; } +/** + * @brief Wait for Computation Complete Flag (CCF) to raise then clear it. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Timeout Timeout duration. + * @note This function can be used in thread or handler mode. + * @retval HAL status + */ +static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t count = Timeout; + + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + hcryp->State = HAL_CRYP_STATE_READY; + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); +} #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) /** @@ -5341,9 +5482,9 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); hcryp->CrypInCount++; - if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { - /* Call output transfer complete callback */ + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) /*Call registered Input complete callback*/ hcryp->InCpltCallback(hcryp); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.h index a9f0b2ebba..b6d27e2987 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_cryp.h @@ -109,7 +109,7 @@ typedef struct __CRYP_HandleTypeDef typedef struct #endif { - AES_TypeDef *Instance; /*!< AES Register base address */ + AES_TypeDef *Instance; /*!< AES Register base address */ CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */ @@ -120,13 +120,13 @@ typedef struct uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - __IO uint16_t CrypHeaderCount; /*!< Counter of header data */ + __IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */ - __IO uint16_t CrypInCount; /*!< Counter of input data */ + __IO uint16_t CrypInCount; /*!< Counter of input data in words */ - __IO uint16_t CrypOutCount; /*!< Counter of output data */ + __IO uint16_t CrypOutCount; /*!< Counter of output data in words */ - uint16_t Size; /*!< length of input data in words */ + uint16_t Size; /*!< Length of input data */ uint32_t Phase; /*!< CRYP peripheral phase */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.c index 1d95fd71a1..94b1d4bdf5 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.c @@ -177,7 +177,7 @@ DAC_OUTx = VREF+ * DOR / 4095 (+) with DOR is the Data Output Register [..] - VEF+ is the input voltage reference (refer to the device datasheet) + VREF+ is the input voltage reference (refer to the device datasheet) [..] e.g. To set DAC_OUT1 to 0.7V, use (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V @@ -327,7 +327,7 @@ [..] (@) You can refer to the DAC HAL driver header file for more useful macros - @endverbatim +@endverbatim ****************************************************************************** * @attention * @@ -594,6 +594,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); } } + else { /* Check if software trigger enabled */ @@ -604,6 +605,7 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) } } + /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -655,7 +657,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. - * @param pData The destination peripheral Buffer address. + * @param pData The source Buffer address. * @param Length The length of data to be transferred from memory to DAC peripheral * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: @@ -667,7 +669,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment) { - HAL_StatusTypeDef status; + HAL_StatusTypeDef status = HAL_ERROR; uint32_t tmpreg = 0U; /* Check the parameters */ @@ -713,6 +715,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u break; } } + else { /* Set the DMA transfer complete callback for channel2 */ @@ -747,6 +750,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u } } + /* Enable the DMA channel */ if (Channel == DAC_CHANNEL_1) { @@ -756,6 +760,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Enable the DMA channel */ status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); } + else { /* Enable the DAC DMA underrun interrupt */ @@ -765,6 +770,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); } + /* Process Unlocked */ __HAL_UNLOCK(hdac); @@ -799,8 +805,6 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { - HAL_StatusTypeDef status; - /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); @@ -818,34 +822,27 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) if (Channel == DAC_CHANNEL_1) { /* Disable the DMA channel */ - status = HAL_DMA_Abort(hdac->DMA_Handle1); + (void)HAL_DMA_Abort(hdac->DMA_Handle1); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); } + else /* Channel2 is used for */ { /* Disable the DMA channel */ - status = HAL_DMA_Abort(hdac->DMA_Handle2); + (void)HAL_DMA_Abort(hdac->DMA_Handle2); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); } - /* Check if DMA Channel effectively disabled */ - if (status != HAL_OK) - { - /* Update DAC state machine to error */ - hdac->State = HAL_DAC_STATE_ERROR; - } - else - { - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - } + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -866,7 +863,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) /* Change DAC state to error state */ hdac->State = HAL_DAC_STATE_ERROR; - /* Set DAC error code to chanel1 DMA underrun error */ + /* Set DAC error code to channel1 DMA underrun error */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); /* Clear the underrun flag */ @@ -884,6 +881,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) } } + if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) { /* Check underrun flag of DAC channel 2 */ @@ -909,6 +907,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } } + } /** @@ -932,7 +931,7 @@ void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { - __IO uint32_t tmp = 0; + __IO uint32_t tmp = 0UL; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); @@ -948,11 +947,13 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, ui { tmp += DAC_DHR12R1_ALIGNMENT(Alignment); } + else { tmp += DAC_DHR12R2_ALIGNMENT(Alignment); } + /* Set the DAC channel selected data holding register */ *(__IO uint32_t *) tmp = Data; @@ -1058,18 +1059,23 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) */ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) { + uint32_t tmp = 0U; + /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); - /* Returns the DAC channel data output register value */ if (Channel == DAC_CHANNEL_1) { - return hdac->Instance->DOR1; + tmp = hdac->Instance->DOR1; } + else { - return hdac->Instance->DOR2; + tmp = hdac->Instance->DOR2; } + + /* Returns the DAC channel data output register value */ + return tmp; } /** @@ -1095,7 +1101,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf { uint32_t tmpreg1; uint32_t tmpreg2; - uint32_t tickstart = 0U; + uint32_t tickstart; uint32_t hclkfreq; uint32_t connectOnChip; @@ -1127,15 +1133,14 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; + /* Sample and hold configuration */ if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) - /* Sample on old configuration */ { - /* SampleTime */ + /* Get timeout */ + tickstart = HAL_GetTick(); + if (Channel == DAC_CHANNEL_1) { - /* Get timeout */ - tickstart = HAL_GetTick(); - /* SHSR1 can be written when BWST1 is cleared */ while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) { @@ -1154,10 +1159,10 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf HAL_Delay(1); hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } + else /* Channel 2 */ { /* SHSR2 can be written when BWST2 is cleared */ - while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) { /* Check for the Timeout */ @@ -1176,10 +1181,13 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } + /* HoldTime */ - MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), + (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ - MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), + (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) @@ -1204,15 +1212,15 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Clear DAC_MCR_MODEx bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL)); /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ - if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_EXTERNAL) == DAC_CHIPCONNECT_EXTERNAL) + if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL) { connectOnChip = 0x00000000UL; } - else if ((sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_INTERNAL) == DAC_CHIPCONNECT_INTERNAL) + else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL) { connectOnChip = DAC_MCR_MODE1_0; } - else /* (sConfig->DAC_ConnectOnChipPeripheral & DAC_CHIPCONNECT_BOTH) == DAC_CHIPCONNECT_BOTH */ + else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */ { if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE) { @@ -1275,7 +1283,7 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; /* Disable wave generation */ - hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL)); + CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); /* Set STRSTTRIGSELx and STINCTRIGSELx bits according to DAC_Trigger & DAC_Trigger2 values */ tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos; @@ -1404,6 +1412,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call case HAL_DAC_CH1_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh1 = pCallback; break; + case HAL_DAC_CH2_COMPLETE_CB_ID : hdac->ConvCpltCallbackCh2 = pCallback; break; @@ -1416,6 +1425,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call case HAL_DAC_CH2_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh2 = pCallback; break; + case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = pCallback; break; @@ -1503,6 +1513,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca case HAL_DAC_CH1_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; break; + case HAL_DAC_CH2_COMPLETE_CB_ID : hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; break; @@ -1515,6 +1526,7 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca case HAL_DAC_CH2_UNDERRUN_CB_ID : hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; break; + case HAL_DAC_MSPINIT_CB_ID : hdac->MspInitCallback = HAL_DAC_MspInit; break; @@ -1526,10 +1538,12 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Ca hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; + hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; + hdac->MspInitCallback = HAL_DAC_MspInit; hdac->MspDeInitCallback = HAL_DAC_MspDeInit; break; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.h index d6fc8a1804..a9b6759bbf 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac.h @@ -64,7 +64,7 @@ typedef enum typedef struct __DAC_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ { DAC_TypeDef *Instance; /*!< Register base address */ @@ -79,17 +79,19 @@ typedef struct __IO uint32_t ErrorCode; /*!< DAC Error code */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); - void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + + + void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } DAC_HandleTypeDef; @@ -131,11 +133,13 @@ typedef struct uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection. - Note: In case of sawtooth wave generation, this trigger corresponds to the reset trigger. */ + Note: In case of sawtooth wave generation, this + trigger corresponds to the reset trigger. */ uint32_t DAC_Trigger2; /*!< Specifies the external secondary trigger for the selected DAC channel. This parameter can be a value of @ref DAC_trigger_selection. - Note: In case of sawtooth wave generation, this trigger corresponds to the step trigger.*/ + Note: In case of sawtooth wave generation, this + trigger corresponds to the step trigger.*/ uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. This parameter can be a value of @ref DAC_output_buffer */ @@ -150,9 +154,7 @@ typedef struct uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ - DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ - } DAC_ChannelConfTypeDef; #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) @@ -165,10 +167,12 @@ typedef enum HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ + HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ + HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ @@ -209,7 +213,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_trigger_selection DAC trigger selection * @{ */ -#define DAC_TRIGGER_NONE 0x00000000U /*!< DAC (all) conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ +#define DAC_TRIGGER_NONE 0x00000000UL /*!< DAC (all) conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ #define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< DAC (all) conversion started by software trigger for DAC channel */ #define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: TIM1 TRGO selected as external conversion trigger for DAC channel. */ #define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1/2/4: TIM8 TRGO selected as external conversion trigger for DAC channel. Refer to device datasheet for DACx availability. */ @@ -255,7 +259,9 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @{ */ #define DAC_CHANNEL_1 0x00000000U + #define DAC_CHANNEL_2 0x00000010U + /** * @} */ @@ -275,10 +281,14 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @{ */ #define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) + #define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) + #define DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY) + #define DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) + /** * @} */ @@ -287,8 +297,10 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @{ */ #define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) + #define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) + /** * @} */ @@ -307,9 +319,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_UserTrimming DAC User Trimming * @{ */ -#define DAC_TRIMMING_FACTORY 0x00000000U /*!< Factory trimming */ -#define DAC_TRIMMING_USER 0x00000001U /*!< User trimming */ - +#define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */ +#define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */ /** * @} */ @@ -317,7 +328,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_SampleAndHold DAC power mode * @{ */ -#define DAC_SAMPLEANDHOLD_DISABLE 0x00000000U +#define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL) #define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2) /** @@ -326,10 +337,10 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_HighFrequency DAC high frequency interface mode * @{ */ -#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000U /*!< High frequency interface mode disabled */ +#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */ #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */ #define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */ -#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002U /*!< High frequency interface mode automatic */ +#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL /*!< High frequency interface mode automatic */ /** * @} @@ -379,26 +390,28 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ -#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__)) +#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__)) + /** @brief Set DHR12R2 alignment. * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ -#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__)) +#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__)) + /** @brief Set DHR12RD alignment. * @param __ALIGNMENT__ specifies the DAC alignment * @retval None */ -#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__)) +#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__)) /** @brief Enable the DAC interrupt. * @param __HANDLE__ specifies the DAC handle * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: - * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt - * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt (1) + * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. @@ -410,8 +423,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @param __HANDLE__ specifies the DAC handle * @param __INTERRUPT__ specifies the DAC interrupt. * This parameter can be any combination of the following values: - * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt - * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt (1) + * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. @@ -423,23 +436,24 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @param __HANDLE__ DAC handle * @param __INTERRUPT__ DAC interrupt source to check * This parameter can be any combination of the following values: - * @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt - * @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt (1) + * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt + * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. * @retval State of interruption (SET or RESET) */ -#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected DAC's flag status. * @param __HANDLE__ specifies the DAC handle. * @param __FLAG__ specifies the DAC flag to get. * This parameter can be any combination of the following values: - * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag - * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag (1) - * @arg DAC_FLAG_DAC1RDY: DAC channel 1 ready status flag - * @arg DAC_FLAG_DAC2RDY: DAC channel 2 ready status flag (1) + * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag + * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1) + * @arg DAC_FLAG_DAC1RDY DAC channel 1 ready status flag + * @arg DAC_FLAG_DAC2RDY DAC channel 2 ready status flag (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. @@ -451,8 +465,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @param __HANDLE__ specifies the DAC handle. * @param __FLAG__ specifies the DAC flag to clear. * This parameter can be any combination of the following values: - * @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag - * @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag (1) + * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag + * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1) * * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. @@ -489,9 +503,9 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); ((ALIGN) == DAC_ALIGN_12B_L) || \ ((ALIGN) == DAC_ALIGN_8B_R)) -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U) +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL) -#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFU) +#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL) /** * @} @@ -528,9 +542,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment); HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); - void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); - HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); @@ -554,7 +566,6 @@ HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA */ /* Peripheral Control functions ***********************************************/ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); - HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); /** * @} @@ -600,7 +611,6 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); #endif -#endif /*STM32G4xx_HAL_DAC_H */ +#endif /* STM32G4xx_HAL_DAC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac_ex.c index 550f59c274..cf40f178eb 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac_ex.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32g4xx_hal_dac_ex.c * @author MCD Application Team - * @brief DAC HAL module driver. + * @brief Extended DAC HAL module driver. * This file provides firmware functions to manage the extended * functionalities of the DAC peripheral. * @@ -12,8 +12,10 @@ ##### How to use this driver ##### ============================================================================== [..] + *** Dual mode IO operation *** ============================== + [..] (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion for dual mode operation. If software trigger is selected, using HAL_DACEx_DualStart() will start @@ -35,6 +37,7 @@ *** Signal generation operation *** =================================== + [..] (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. @@ -110,6 +113,7 @@ * @{ */ + /** * @brief Enables DAC and starts conversion of both channels. * @param hdac pointer to a DAC_HandleTypeDef structure that contains @@ -136,11 +140,11 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) HAL_Delay(1); /* Check if software trigger enabled */ - if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1) + if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) { tmp_swtrig |= DAC_SWTRIGR_SWTRIG1; } - if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2) + if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL))) { tmp_swtrig |= DAC_SWTRIGR_SWTRIG2; } @@ -202,7 +206,7 @@ HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Chan uint32_t Alignment) { HAL_StatusTypeDef status; - uint32_t tmpreg = 0U; + uint32_t tmpreg = 0UL; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); @@ -363,6 +367,7 @@ HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Chann return status; } + /** * @brief Enable or disable the selected DAC channel wave generation. * @param hdac pointer to a DAC_HandleTypeDef structure that contains @@ -403,7 +408,8 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32 hdac->State = HAL_DAC_STATE_BUSY; /* Enable the triangle wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), + (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -455,7 +461,8 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t hdac->State = HAL_DAC_STATE_BUSY; /* Enable the noise wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), + (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -563,7 +570,7 @@ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint3 /* Process locked */ __HAL_LOCK(hdac); - if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STRSTTRIGSEL1) == 0U /* SW TRIGGER */) + if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STRSTTRIGSEL1) == 0UL /* SW TRIGGER */) { /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; @@ -619,7 +626,7 @@ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32 /* Process locked */ __HAL_LOCK(hdac); - if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STINCTRIGSEL1) == 0U /* SW TRIGGER */) + if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STINCTRIGSEL1) == 0UL /* SW TRIGGER */) { /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; @@ -650,6 +657,7 @@ HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32 return status; } + /** * @brief Set the specified data holding register value for dual DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains @@ -759,6 +767,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) */ } + /** * @brief Run the self calibration of one DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains @@ -775,7 +784,6 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) * @retval HAL status * @note Calibration runs about 7 ms. */ - HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) { HAL_StatusTypeDef status = HAL_OK; @@ -828,7 +836,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R); } - *(__IO uint32_t *) tmp = 0x0800U; + *(__IO uint32_t *) tmp = 0x0800UL; /* Enable the selected DAC channel calibration */ /* i.e. set DAC_CR_CENx bit */ @@ -836,9 +844,9 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Init trimming counter */ /* Medium value */ - trimmingvalue = 16U; - delta = 8U; - while (delta != 0U) + trimmingvalue = 16UL; + delta = 8UL; + while (delta != 0UL) { /* Set candidate trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); @@ -857,7 +865,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* DAC_SR_CAL_FLAGx is LOW try lower trimming */ trimmingvalue += delta; } - delta >>= 1U; + delta >>= 1UL; } /* Still need to check if right calibration is current value or one step below */ @@ -871,7 +879,7 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { - /* OPAMP_CSR_OUTCAL is actually one value more */ + /* Trimming is actually one value more */ trimmingvalue++; /* Set right trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); @@ -909,7 +917,6 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo * @param NewTrimmingValue DAC new trimming value * @retval HAL status */ - HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue) { @@ -955,13 +962,12 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel * @retval Trimming value : range: 0->31 * */ - uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) { /* Check the parameter */ assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel)); - /* Retrieve trimming */ + /* Retrieve trimming */ return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL)); } @@ -983,6 +989,7 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) * @{ */ + /** * @brief Return the last data output value of the selected DAC channel. * @param hdac pointer to a DAC_HandleTypeDef structure that contains @@ -991,20 +998,20 @@ uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel) */ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) { - uint32_t tmp = 0U; + uint32_t tmp = 0UL; tmp |= hdac->Instance->DOR1; - tmp |= hdac->Instance->DOR2 << 16U; + tmp |= hdac->Instance->DOR2 << 16UL; /* Returns the DAC channel data output register value */ return tmp; } + /** * @} */ - /** * @} */ @@ -1012,9 +1019,10 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac) /* Private functions ---------------------------------------------------------*/ /** @defgroup DACEx_Private_Functions DACEx private functions * @brief Extended private functions - * @{ + * @{ */ + /** * @brief DMA conversion complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains @@ -1073,6 +1081,7 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) hdac->State = HAL_DAC_STATE_READY; } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac_ex.h index 03e1ab5e9e..2383fb5818 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_dac_ex.h @@ -53,7 +53,7 @@ extern "C" { /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude * @{ */ -#define DAC_LFSRUNMASK_BIT0 0x00000000U /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ #define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ @@ -65,7 +65,7 @@ extern "C" { #define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ #define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TRIANGLEAMPLITUDE_1 0x00000000U /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */ #define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ #define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */ #define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ @@ -85,7 +85,7 @@ extern "C" { /** @defgroup DACEx_SawtoothPolarityMode DAC Sawtooth polarity mode * @{ */ -#define DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000U /*!< Sawtooth wave generation, polarity is decrement */ +#define DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL /*!< Sawtooth wave generation, polarity is decrement */ #define DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */ /** @@ -342,6 +342,6 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); } #endif -#endif /*STM32G4xx_HAL_DAC_EX_H */ +#endif /* STM32G4xx_HAL_DAC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_def.h index e30a61512f..06e1e93c8c 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_def.h @@ -107,7 +107,14 @@ typedef enum }while (0U) #endif /* USE_RTOS */ -#if defined ( __GNUC__ ) +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif +#ifndef __packed +#define __packed __attribute__((packed)) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -118,7 +125,14 @@ typedef enum /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4U))) #endif /* __ALIGN_END */ @@ -130,7 +144,7 @@ typedef enum #define __ALIGN_END #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN -#if defined (__CC_ARM) /* ARM Compiler */ +#if defined (__CC_ARM) /* ARM Compiler V5*/ #define __ALIGN_BEGIN __align(4U) #elif defined (__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN @@ -141,9 +155,9 @@ typedef enum /** * @brief __RAM_FUNC definition */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' @@ -173,9 +187,9 @@ typedef enum /** * @brief __NOINLINE definition */ -#if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- */ #define __NOINLINE __attribute__ ( (noinline) ) diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_exti.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_exti.h index 0872e28098..c095702a44 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_exti.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_exti.h @@ -228,19 +228,19 @@ typedef struct /** @defgroup EXTI_Private_Macros EXTI Private Macros * @{ */ -#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \ - ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ - (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ - (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ - (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ - (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ + (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u)))) -#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00U) && \ - (((__LINE__) & ~EXTI_MODE_MASK) == 0x00U)) +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U)) -#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) -#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00U) +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_flash.h index d4f381baad..7f6a59cf97 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_flash.h @@ -273,6 +273,9 @@ typedef struct #define OB_USER_BFB2 0x00000080U /*!< Dual-bank boot */ #define OB_USER_DBANK 0x00000100U /*!< Single bank with 128-bits data or two banks with 64-bits data */ #endif +#if defined (FLASH_OPTR_PB4_PUPEN) +#define OB_USER_PB4_PUPEN 0x00000100U /*!< USB power delivery dead-battery/TDI pull-up */ +#endif #define OB_USER_nBOOT1 0x00000200U /*!< Boot configuration */ #define OB_USER_SRAM_PE 0x00000400U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */ #define OB_USER_CCMSRAM_RST 0x00000800U /*!< CCMSRAM Erase when system reset */ @@ -380,6 +383,17 @@ typedef struct */ #endif +#if defined (FLASH_OPTR_PB4_PUPEN) +/** @defgroup FLASH_OB_USER_PB4_PUPEN FLASH Option Bytes User PB4 PUPEN bit + * @{ + */ +#define OB_PB4_PUPEN_DISABLE 0x00000000U /*!< USB power delivery dead-battery enabled/ TDI pull-up deactivated */ +#define OB_PB4_PUPEN_ENABLE FLASH_OPTR_PB4_PUPEN /*!< USB power delivery dead-battery disabled/ TDI pull-up activated */ +/** + * @} + */ +#endif + /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type * @{ */ @@ -952,6 +966,10 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS)) #endif +#if defined (FLASH_OPTR_PB4_PUPEN) +#define IS_OB_USER_PB4_PUPEN(VALUE) (((VALUE) == OB_PB4_PUPEN_DISABLE) || ((VALUE) == OB_PB4_PUPEN_ENABLE)) +#endif + #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM)) #define IS_OB_USER_SRAM_PARITY(VALUE) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE)) diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.c index 988428a693..f55d771d6c 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.c @@ -213,6 +213,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal.h" +#if defined(FMAC) #ifdef HAL_FMAC_MODULE_ENABLED /** @addtogroup STM32G4xx_HAL_Driver @@ -430,13 +431,13 @@ HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac) FMAC_ResetDataPointers(hfmac); /* Reset FMAC unit (internal pointers) */ - if (FMAC_Reset(hfmac) == HAL_TIMEOUT) + if (FMAC_Reset(hfmac) == HAL_ERROR) { /* Update FMAC error code and FMAC peripheral state */ hfmac->ErrorCode |= HAL_FMAC_ERROR_RESET; hfmac->State = HAL_FMAC_STATE_TIMEOUT; - status = HAL_TIMEOUT; + status = HAL_ERROR; } else { @@ -688,39 +689,42 @@ HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMA switch (CallbackID) { case HAL_FMAC_ERROR_CB_ID : - hfmac->ErrorCallback = HAL_FMAC_ErrorCallback; /* Legacy weak ErrorCallback */ + hfmac->ErrorCallback = HAL_FMAC_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_FMAC_HALF_GET_DATA_CB_ID : - hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback; /* Legacy weak HalfGetDataCallback */ + hfmac->HalfGetDataCallback = HAL_FMAC_HalfGetDataCallback; /* Legacy weak HalfGetDataCallback */ break; case HAL_FMAC_GET_DATA_CB_ID : - hfmac->GetDataCallback = HAL_FMAC_GetDataCallback; /* Legacy weak GetDataCallback */ + hfmac->GetDataCallback = HAL_FMAC_GetDataCallback; /* Legacy weak GetDataCallback */ break; case HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID : - hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak HalfOutputDataReadyCallback */ + hfmac->HalfOutputDataReadyCallback = HAL_FMAC_HalfOutputDataReadyCallback; /* Legacy weak + HalfOutputDataReadyCallback */ break; case HAL_FMAC_OUTPUT_DATA_READY_CB_ID : - hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback; /* Legacy weak OutputDataReadyCallback */ + hfmac->OutputDataReadyCallback = HAL_FMAC_OutputDataReadyCallback; /* Legacy weak + OutputDataReadyCallback */ break; case HAL_FMAC_FILTER_CONFIG_CB_ID : - hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback; /* Legacy weak FilterConfigCallback */ + hfmac->FilterConfigCallback = HAL_FMAC_FilterConfigCallback; /* Legacy weak + FilterConfigCallback */ break; case HAL_FMAC_FILTER_PRELOAD_CB_ID : - hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback; /* Legacy weak FilterPreloadCallback */ + hfmac->FilterPreloadCallback = HAL_FMAC_FilterPreloadCallback; /* Legacy weak FilterPreloadCallba */ break; case HAL_FMAC_MSPINIT_CB_ID : - hfmac->MspInitCallback = HAL_FMAC_MspInit; /* Legacy weak MspInitCallback */ + hfmac->MspInitCallback = HAL_FMAC_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_FMAC_MSPDEINIT_CB_ID : - hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit; /* Legacy weak MspDeInitCallback */ + hfmac->MspDeInitCallback = HAL_FMAC_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -955,7 +959,7 @@ HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutp } else { - status = HAL_BUSY; + status = HAL_ERROR; } return status; @@ -999,7 +1003,7 @@ HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t * /* Check whether the previous input vector has been handled */ if ((hfmac->pInputSize != NULL) && (hfmac->InputCurrentSize < * (hfmac->pInputSize))) { - return HAL_BUSY; + return HAL_ERROR; } /* Check that FMAC was initialized and that no writing is already ongoing */ @@ -1010,7 +1014,7 @@ HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t * } else { - status = HAL_BUSY; + status = HAL_ERROR; } return status; @@ -1055,7 +1059,7 @@ HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, i /* Check whether the previous output vector has been handled */ if ((hfmac->pOutputSize != NULL) && (hfmac->OutputCurrentSize < * (hfmac->pOutputSize))) { - return HAL_BUSY; + return HAL_ERROR; } /* Check that FMAC was initialized and that not reading is already ongoing */ @@ -1066,7 +1070,7 @@ HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, i } else { - status = HAL_BUSY; + status = HAL_ERROR; } return status; @@ -1185,7 +1189,7 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti if ((HAL_GetTick() - tickstart) >= Timeout) { hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; - status = HAL_TIMEOUT; + status = HAL_ERROR; } else { @@ -1194,7 +1198,7 @@ HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Ti } else { - status = HAL_BUSY; + status = HAL_ERROR; } return status; @@ -1233,12 +1237,12 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) } /* Reset FMAC unit (internal pointers) */ - if (FMAC_Reset(hfmac) == HAL_TIMEOUT) + if (FMAC_Reset(hfmac) == HAL_ERROR) { /* Update FMAC error code and FMAC peripheral state */ hfmac->ErrorCode = HAL_FMAC_ERROR_RESET; hfmac->State = HAL_FMAC_STATE_TIMEOUT; - status = HAL_TIMEOUT; + status = HAL_ERROR; } else { @@ -1253,7 +1257,7 @@ HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac) } else { - status = HAL_BUSY; + status = HAL_ERROR; } return status; @@ -1589,7 +1593,7 @@ static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac) if ((HAL_GetTick() - tickstart) > HAL_FMAC_RESET_TIMEOUT_VALUE) { hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; - return HAL_TIMEOUT; + return HAL_ERROR; } } @@ -1674,7 +1678,7 @@ static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_Filte /* Check handle state is ready */ if (hfmac->State != HAL_FMAC_STATE_READY) { - return HAL_BUSY; + return HAL_ERROR; } /* Change the FMAC state */ @@ -1692,7 +1696,8 @@ static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_Filte MODIFY_REG(hfmac->Instance->X1BUFCFG, \ (FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE), \ (((((uint32_t)(pConfig->InputBaseAddress)) << FMAC_X1BUFCFG_X1_BASE_Pos) & FMAC_X1BUFCFG_X1_BASE) | \ - ((((uint32_t)(pConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & FMAC_X1BUFCFG_X1_BUF_SIZE))); + ((((uint32_t)(pConfig->InputBufferSize)) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) & \ + FMAC_X1BUFCFG_X1_BUF_SIZE))); } /* FMAC_X1BUFCFG: Configure the input threshold if valid when compared to the configured X1 size */ @@ -1712,7 +1717,8 @@ static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_Filte MODIFY_REG(hfmac->Instance->X2BUFCFG, \ (FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE), \ (((((uint32_t)(pConfig->CoeffBaseAddress)) << FMAC_X2BUFCFG_X2_BASE_Pos) & FMAC_X2BUFCFG_X2_BASE) | \ - ((((uint32_t)(pConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) & FMAC_X2BUFCFG_X2_BUF_SIZE))); + ((((uint32_t)(pConfig->CoeffBufferSize)) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) &\ + FMAC_X2BUFCFG_X2_BUF_SIZE))); } /* FMAC_YBUFCFG: Configure the output buffer within the internal memory if required */ @@ -1758,7 +1764,8 @@ static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_Filte x2size = FMAC_GET_X2_SIZE(hfmac); #endif /* USE_FULL_ASSERT */ assert_param(((pConfig->Filter == FMAC_FUNC_CONVO_FIR) && (x2size >= pConfig->P)) || \ - ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && (x2size >= ((uint32_t)pConfig->P + (uint32_t)pConfig->Q)))); + ((pConfig->Filter == FMAC_FUNC_IIR_DIRECT_FORM_1) && \ + (x2size >= ((uint32_t)pConfig->P + (uint32_t)pConfig->Q)))); /* Build the PARAM value that will be used when starting the filter */ hfmac->FilterParam = (FMAC_PARAM_START | pConfig->Filter | \ @@ -1805,7 +1812,7 @@ static HAL_StatusTypeDef FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_Filte { hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; hfmac->State = HAL_FMAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + return HAL_ERROR; } /* Change the FMAC state */ @@ -1888,7 +1895,7 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t * /* Check handle state is ready */ if (hfmac->State != HAL_FMAC_STATE_READY) { - return HAL_BUSY; + return HAL_ERROR; } /* Change the FMAC state */ @@ -1914,7 +1921,7 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t * { hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; hfmac->State = HAL_FMAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + return HAL_ERROR; } } else @@ -1950,7 +1957,7 @@ static HAL_StatusTypeDef FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t * { hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; hfmac->State = HAL_FMAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + return HAL_ERROR; } } else @@ -2035,7 +2042,7 @@ static HAL_StatusTypeDef FMAC_WaitOnStartUntilTimeout(FMAC_HandleTypeDef *hfmac, { hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT; - return HAL_TIMEOUT; + return HAL_ERROR; } } return HAL_OK; @@ -2532,5 +2539,6 @@ static void FMAC_DMAError(DMA_HandleTypeDef *hdma) */ #endif /* HAL_FMAC_MODULE_ENABLED */ +#endif /* FMAC */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.h index 1f289dd8d7..221f64071e 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_fmac.h @@ -28,6 +28,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" +#if defined(FMAC) /** @addtogroup STM32G4xx_HAL_Driver * @{ */ @@ -80,14 +81,16 @@ typedef struct uint16_t InputCurrentSize; /*!< Number of the input elements already written into FMAC */ uint16_t *pInputSize; /*!< Number of input elements to write (memory allocated to pInput). - In case of early interruption of the filter operation, its value will be updated. */ + In case of early interruption of the filter operation, + its value will be updated. */ int16_t *pOutput; /*!< Pointer to FMAC output data buffer */ uint16_t OutputCurrentSize; /*!< Number of the output elements already read from FMAC */ uint16_t *pOutputSize; /*!< Number of output elements to read (memory allocated to pOutput). - In case of early interruption of the filter operation, its value will be updated. */ + In case of early interruption of the filter operation, + its value will be updated. */ DMA_HandleTypeDef *hdmaIn; /*!< FMAC peripheral input data DMA handle parameters */ @@ -163,7 +166,8 @@ typedef void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac); /*!< pointer typedef struct { uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF). - Ignored if InputBufferSize is set to 0 (previous configuration kept). + Ignored if InputBufferSize is set to 0 + (previous configuration kept). Note: the buffers can overlap or even coincide exactly. */ uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer (including the optional "headroom"). @@ -171,17 +175,20 @@ typedef struct uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces in the buffer is lower than this threshold. - This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */ + This parameter can be a value + of @ref FMAC_Data_Buffer_Threshold. */ uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF). - Ignored if CoeffBufferSize is set to 0 (previous configuration kept). + Ignored if CoeffBufferSize is set to 0 + (previous configuration kept). Note: the buffers can overlap or even coincide exactly. */ uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer. 0 if a previous configuration should be kept. */ uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF). - Ignored if OuputBufferSize is set to 0 (previous configuration kept). + Ignored if OuputBufferSize is set to 0 + (previous configuration kept). Note: the buffers can overlap or even coincide exactly. */ uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer (including the optional "headroom"). @@ -189,7 +196,8 @@ typedef struct uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values in the buffer is lower than this threshold. - This parameter can be a value of @ref FMAC_Data_Buffer_Threshold. */ + This parameter can be a value + of @ref FMAC_Data_Buffer_Threshold. */ int16_t *pCoeffA; /*!< [IIR only] Initialization of the coefficient vector A. If not needed, it should be set to NULL. */ @@ -197,7 +205,8 @@ typedef struct uint8_t CoeffASize; /*!< Size of the coefficient vector A. */ int16_t *pCoeffB; /*!< Initialization of the coefficient vector B. - If not needed (re-use of a previously loaded buffer), it should be set to NULL. */ + If not needed (re-use of a previously loaded buffer), + it should be set to NULL. */ uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */ @@ -208,12 +217,13 @@ typedef struct This parameter can be a value of @ref FMAC_Buffer_Access. */ uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping - is done when the clipping feature is disabled and saturation is done when the - clipping feature is enabled. + is done when the clipping feature is disabled + and saturation is done when the clipping feature is enabled. This parameter can be a value of @ref FMAC_Clip_State. */ uint32_t Filter; /*!< Filter type. - This parameter can be a value of @ref FMAC_Functions (filter related values). */ + This parameter can be a value + of @ref FMAC_Functions (filter related values). */ uint8_t P; /*!< Parameter P (vector length, number of filter taps, etc.). */ @@ -271,13 +281,17 @@ typedef struct * @note This parameter sets a watermark for buffer full (input) or buffer empty (output). */ #define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1. - Output: Buffer empty flag set if the number of unread values in the buffer is less than 1. */ + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 1. */ #define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2. - Output: Buffer empty flag set if the number of unread values in the buffer is less than 2. */ + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 2. */ #define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4. - Output: Buffer empty flag set if the number of unread values in the buffer is less than 4. */ + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 4. */ #define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8. - Output: Buffer empty flag set if the number of unread values in the buffer is less than 8. */ + Output: Buffer empty flag set if the number + of unread values in the buffer is less than 8. */ #define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */ /** * @} @@ -333,6 +347,13 @@ typedef struct /* External variables --------------------------------------------------------*/ +/** @defgroup FMAC_External_variables FMAC External variables + * @{ + */ +/** + * @} + */ + /* Exported macros -----------------------------------------------------------*/ /** @defgroup FMAC_Exported_Macros FMAC Exported Macros * @{ @@ -444,7 +465,8 @@ typedef struct * @} */ -/** @addtogroup FMAC_Private_Macros +/* Private Macros-----------------------------------------------------------*/ +/** @addtogroup FMAC_Private_Macros FMAC Private Macros * @{ */ @@ -559,11 +581,13 @@ typedef struct * @param __ACCESS__ Access to the buffer (polling, it, dma, none). * @retval THRESHOLD */ -#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \ - ((__WM__) == FMAC_THRESHOLD_2)? 2U: \ - ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \ - ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&&((__WM__) == FMAC_THRESHOLD_1))|| \ - ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA))) +#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) \ + (( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \ + ((__WM__) == FMAC_THRESHOLD_2)? 2U: \ + ((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \ + ((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&& \ + ((__WM__) == FMAC_THRESHOLD_1))|| \ + ((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA))) /** * @} @@ -650,18 +674,20 @@ uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac); * @} */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* FMAC */ + #ifdef __cplusplus } #endif #endif /* STM32G4xx_HAL_FMAC_H */ -/** - * @} - */ - -/** - * @} - */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.c index b9a8fdaa28..19a03051f1 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_hrtim.c @@ -10319,10 +10319,13 @@ static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, */ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) { + uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); + uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); + /* Fault 1 event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET) + if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1); @@ -10336,9 +10339,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 2 event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET) + if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2); @@ -10352,9 +10355,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 3 event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET) + if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3); @@ -10368,9 +10371,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 4 event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET) + if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4); @@ -10384,9 +10387,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 5 event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET) + if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5); @@ -10400,9 +10403,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 6 event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT6) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_FLT6) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT6) != RESET) + if((uint32_t)(ierits & HRTIM_IT_FLT6) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT6); @@ -10416,9 +10419,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* System fault event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET) + if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT); @@ -10439,10 +10442,15 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) */ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) { + uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); + uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); + uint32_t misrflags = READ_REG(hhrtim->Instance->sMasterRegs.MISR); + uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER); + /* DLL calibration ready event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_DLLRDY) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_DLLRDY) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_DLLRDY) != RESET) + if((uint32_t)(ierits & HRTIM_IT_DLLRDY) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY); @@ -10462,9 +10470,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Burst mode period event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET) + if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER); @@ -10478,9 +10486,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 1 event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1); @@ -10494,9 +10502,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 2 event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2); @@ -10510,9 +10518,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 3 event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3); @@ -10526,9 +10534,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 4 event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4); @@ -10542,9 +10550,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer repetition event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP); @@ -10558,9 +10566,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Synchronization input event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC); @@ -10574,9 +10582,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer registers update event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD); @@ -10606,10 +10614,13 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx) { + uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR); + uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER); + /* Timer compare 1 event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); @@ -10623,9 +10634,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 2 event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); @@ -10639,9 +10650,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 3 event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3); @@ -10655,9 +10666,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 4 event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4); @@ -10671,9 +10682,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer repetition event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP); @@ -10687,9 +10698,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer registers update event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD); @@ -10703,9 +10714,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 1 event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1); @@ -10719,9 +10730,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 2 event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2); @@ -10735,9 +10746,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 set event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1); @@ -10751,9 +10762,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 reset event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1); @@ -10767,9 +10778,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 set event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2); @@ -10783,9 +10794,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 reset event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2); @@ -10799,9 +10810,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer reset event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST); @@ -10815,9 +10826,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Delayed protection event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c.c index b5a79be700..199e1b9bd3 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2c.c @@ -4858,7 +4858,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - /* Check if all data have already been sent */ + /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) { diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2s.c index bacad7d2d0..769c4fb720 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_i2s.c @@ -743,7 +743,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). @@ -860,7 +860,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). @@ -961,7 +961,7 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -1025,7 +1025,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization @@ -1091,7 +1091,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -1182,7 +1182,7 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 16-bit data length. + * the Size parameter means the number of 24-bit or 32-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.c index 953cd02776..a739c4ed71 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.c @@ -2244,7 +2244,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) uint32_t tmpreg; IRDA_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; - const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; uint32_t pclk; /* Check the communication parameters */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.h index 7190535f17..d72c1af84b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_irda.h @@ -90,7 +90,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called) + * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -107,7 +107,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -262,15 +262,15 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer /** @defgroup IRDA_Error_Definition IRDA Error Code Definition * @{ */ -#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */ +#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */ #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ /** * @} @@ -574,12 +574,12 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @retval None */ #define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ - ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << \ + ((__HANDLE__)->Instance->CR1 |= (1U << \ ((__INTERRUPT__) & IRDA_IT_MASK))):\ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ - ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << \ + ((__HANDLE__)->Instance->CR2 |= (1U << \ ((__INTERRUPT__) & IRDA_IT_MASK))):\ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << \ + ((__HANDLE__)->Instance->CR3 |= (1U << \ ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. @@ -595,12 +595,12 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @retval None */ #define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ - ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << \ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << \ ((__INTERRUPT__) & IRDA_IT_MASK))): \ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ - ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << \ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << \ ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << \ ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Check whether the specified IRDA interrupt has occurred or not. @@ -635,7 +635,7 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \ & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \ - & ((uint32_t)0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) + & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the IRDA Handle. diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_iwdg.c index 38fe72d995..83cd68b27b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_iwdg.c @@ -16,33 +16,43 @@ (+) The IWDG can be started by either software or hardware (configurable through option byte). - (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even - if the main clock fails. + (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays + active even if the main clock fails. - (+) Once the IWDG is started, the LSI is forced ON and both can not be + (+) Once the IWDG is started, the LSI is forced ON and both cannot be disabled. The counter starts counting down from the reset value (0xFFF). When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, - the IWDG_RLR value is reloaded in the counter and the watchdog reset is - prevented. + the IWDG_RLR value is reloaded into the counter and the watchdog reset + is prevented. (+) The IWDG is implemented in the VDD voltage domain that is still functional - in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). + in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY). IWDGRST flag in RCC_CSR register can be used to inform when an IWDG reset occurs. - (+) Debug mode : When the microcontroller enters debug mode (core halted), + (+) Debug mode: When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module, accessible through __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros. [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s - The IWDG timeout may vary due to LSI frequency dispersion. STM32G4xx - devices provide the capability to measure the LSI frequency (LSI clock - connected internally to TIM16 CH1 input capture). The measured value - can be used to have an IWDG timeout with an acceptable accuracy. + The IWDG timeout may vary due to LSI clock frequency dispersion. + STM32G4xx devices provide the capability to measure the LSI clock + frequency (LSI clock is internally connected to TIM16 CH1 input capture). + The measured value can be used to have an IWDG timeout with an + acceptable accuracy. + + [..] Default timeout value (necessary for IWDG_SR status register update): + Constant LSI_VALUE is defined based on the nominal LSI clock frequency. + This frequency being subject to variations as mentioned above, the + default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT + below) may become too short or too long. + In such cases, this default timeout value can be tuned by redefining + the constant LSI_VALUE at user-application level (based, for instance, + on the measured LSI clock frequency as explained above). ##### How to use this driver ##### ============================================================================== @@ -55,13 +65,13 @@ (++) Configure the IWDG prescaler and counter reload value. This reload value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. - (++) Wait for status flags to be reset. (++) Depending on window parameter: (+++) If Window Init parameter is same as Window register value, nothing more is done but reload counter value in order to exit function with exact time base. (+++) Else modify Window register. This will automatically reload watchdog counter. + (++) Wait for status flags to be reset. (#) Then the application program must refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using @@ -108,10 +118,15 @@ /** @defgroup IWDG_Private_Defines IWDG Private Defines * @{ */ -/* Status register need 5 RC LSI divided by prescaler clock to be updated. With - higher prescaler (256), and according to LSI variation, we need to wait at - least 6 cycles so 48 ms. */ -#define HAL_IWDG_DEFAULT_TIMEOUT 48u +/* Status register needs up to 5 LSI clock periods divided by the clock + prescaler to be updated. The number of LSI clock periods is upper-rounded to + 6 for the timeout value calculation. + The timeout value is also calculated using the highest prescaler (256) and + the LSI_VALUE constant. The value of this constant can be changed by the user + to take into account possible LSI clock period variations. + The timeout value is multiplied by 1000 to be converted in milliseconds. */ +#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) +#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} */ @@ -182,11 +197,14 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) tickstart = HAL_GetTick(); /* Wait for register to be updated */ - while (hiwdg->Instance->SR != 0x00u) + while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) { - return HAL_TIMEOUT; + if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) + { + return HAL_TIMEOUT; + } } } @@ -209,6 +227,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) return HAL_OK; } + /** * @} */ @@ -228,7 +247,6 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) * @{ */ - /** * @brief Refresh the IWDG. * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains @@ -244,6 +262,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) return HAL_OK; } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_iwdg.h index da0c9465b4..c79de2c16a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_iwdg.h @@ -87,7 +87,6 @@ typedef struct #define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ #define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ #define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ - /** * @} */ @@ -100,7 +99,6 @@ typedef struct * @} */ - /** * @} */ @@ -138,7 +136,7 @@ typedef struct * @{ */ /* Initialization/Start functions ********************************************/ -HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); /** * @} */ @@ -147,7 +145,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); * @{ */ /* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.c index e4f887fcb8..e70e5f9142 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.c @@ -197,8 +197,8 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t */ /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -235,19 +235,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); - } - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) - { assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); - assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); @@ -281,21 +279,18 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); } if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL)); - } - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) - { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); } - /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | + /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE)); /* Set initialization parameters */ @@ -314,19 +309,21 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) hlptim->Init.UltraLowPowerClock.SampleTime); } - /* Configure the active edge or edges used by the counter only if LPTIM is - * clocked by an external clock source - */ - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + /* Configure LPTIM external clock polarity and digital filter */ + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity); + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + hlptim->Init.UltraLowPowerClock.SampleTime); } + /* Configure LPTIM external trigger */ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ - tmpcfgr |= (hlptim->Init.Trigger.Source | - hlptim->Init.Trigger.ActiveEdge); + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge | + hlptim->Init.Trigger.SampleTime); } /* Write to LPTIMx CFGR */ @@ -432,8 +429,8 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions - * @brief Start-Stop operation functions. - * + * @brief Start-Stop operation functions. + * @verbatim ============================================================================== ##### LPTIM Start Stop operation functions ##### @@ -1558,7 +1555,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t hlptim->State = HAL_LPTIM_STATE_BUSY; /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1639,7 +1637,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1730,8 +1729,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions - * @brief Read operation functions. - * + * @brief Read operation functions. + * @verbatim ============================================================================== ##### LPTIM Read operation functions ##### @@ -1788,8 +1787,8 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks - * @brief LPTIM IRQ handler. - * + * @brief LPTIM IRQ handler. + * @verbatim ============================================================================== ##### LPTIM IRQ handler and callbacks ##### @@ -2256,8 +2255,8 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti */ /** @defgroup LPTIM_Group5 Peripheral State functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim ============================================================================== ##### Peripheral State functions ##### @@ -2332,8 +2331,7 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t { result = HAL_TIMEOUT; } - } - while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); return result; } diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.h index d5bb1664b8..6972921e0a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_lptim.h @@ -391,10 +391,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -544,31 +544,36 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @retval Interrupt status. */ -#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line. * @retval None */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR2 |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR2\ + |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) /** * @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line. * @retval None */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR2 &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR2\ + &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) /** * @brief Enable event on the LPTIM Wake-up Timer associated Exti line. * @retval None. */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR2 |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR2\ + |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) /** * @brief Disable event on the LPTIM Wake-up Timer associated Exti line. * @retval None. */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR2 &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR2\ + &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) /** * @} @@ -580,9 +585,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ /** @addtogroup LPTIM_Exported_Functions_Group1 - * @brief Initialization and Configuration functions. - * @{ - */ + * @brief Initialization and Configuration functions. + * @{ + */ /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); @@ -595,9 +600,9 @@ void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group2 - * @brief Start-Stop operation functions. - * @{ - */ + * @brief Start-Stop operation functions. + * @{ + */ /* Start/Stop operation functions *********************************************/ /* ################################# PWM Mode ################################*/ /* Blocking mode: Polling */ @@ -651,9 +656,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group3 - * @brief Read operation functions. - * @{ - */ + * @brief Read operation functions. + * @{ + */ /* Reading operation functions ************************************************/ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); @@ -663,9 +668,9 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group4 - * @brief LPTIM IRQ handler and callback functions. - * @{ - */ + * @brief LPTIM IRQ handler and callback functions. + * @{ + */ /* LPTIM IRQ functions *******************************************************/ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); @@ -680,7 +685,8 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, + pLPTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** @@ -688,9 +694,9 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_ */ /** @addtogroup LPTIM_Group5 - * @brief Peripheral State functions. - * @{ - */ + * @brief Peripheral State functions. + * @{ + */ /* Peripheral State functions ************************************************/ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** @@ -814,31 +820,31 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #if defined(COMP5) && defined(COMP6) && defined(COMP7) #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ - ((((__INSTANCE__) == LPTIM1) && \ - (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP5) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP7)))) + ((((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP5) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP7)))) #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ - (((__INSTANCE__) == LPTIM1) && \ - (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) || \ - ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4) || \ - ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP6))) + (((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) || \ + ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4) || \ + ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP6))) #else #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ - ((((__INSTANCE__) == LPTIM1) && \ - (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3)))) + ((((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3)))) #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ - (((__INSTANCE__) == LPTIM1) && \ - (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) || \ - ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4))) + (((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) || \ + ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4))) #endif /* COMP5 && COMP6 && COMP7 */ /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nand.c index 6cf1e21ac0..f610be3f25 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nand.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nand.c @@ -156,7 +156,8 @@ * @param AttSpace_Timing pointer to Attribute space timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, + FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) { /* Check the NAND handle state */ if (hnand == NULL) @@ -170,7 +171,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT hnand->Lock = HAL_UNLOCKED; #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - if(hnand->MspInitCallback == NULL) + if (hnand->MspInitCallback == NULL) { hnand->MspInitCallback = HAL_NAND_MspInit; } @@ -181,7 +182,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT #else /* Initialize the low level hardware (MSP) */ HAL_NAND_MspInit(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ } /* Initialize NAND control Interface */ @@ -195,7 +196,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT /* Enable the NAND device */ __FMC_NAND_ENABLE(hnand->Instance); - + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -211,7 +212,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) { #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - if(hnand->MspDeInitCallback == NULL) + if (hnand->MspDeInitCallback == NULL) { hnand->MspDeInitCallback = HAL_NAND_MspDeInit; } @@ -221,7 +222,7 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) #else /* Initialize the low level hardware (MSP) */ HAL_NAND_MspDeInit(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Configure the NAND registers with their reset values */ (void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank); @@ -273,7 +274,7 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status -*/ + */ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) { /* Check NAND interrupt Rising edge flag */ @@ -284,7 +285,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Rising edge pending bit */ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE); @@ -298,7 +299,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Level pending bit */ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL); @@ -312,7 +313,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Falling edge pending bit */ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE); @@ -326,7 +327,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt FIFO empty pending bit */ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT); @@ -380,7 +381,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN { __IO uint32_t data = 0; __IO uint32_t data1 = 0; - uint32_t deviceAddress; + uint32_t deviceaddress; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -396,18 +397,18 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Send Read ID command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; __DSB(); /* Read the electronic signature from NAND flash */ if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) { - data = *(__IO uint32_t *)deviceAddress; + data = *(__IO uint32_t *)deviceaddress; /* Return the data read */ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); @@ -417,8 +418,8 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN } else { - data = *(__IO uint32_t *)deviceAddress; - data1 = *((__IO uint32_t *)deviceAddress + 4); + data = *(__IO uint32_t *)deviceaddress; + data1 = *((__IO uint32_t *)deviceaddress + 4); /* Return the data read */ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); @@ -449,7 +450,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN */ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) { - uint32_t deviceAddress; + uint32_t deviceaddress; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -465,10 +466,10 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Send NAND reset command */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -505,7 +506,6 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC return HAL_OK; } - /** * @brief Read Page(s) from NAND memory block (8-bits addressing) * @param hnand pointer to a NAND_HandleTypeDef structure that contains @@ -515,12 +515,16 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesRead = 0U, nandAddress, nbpages = NumPageToRead; - uint8_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numpagesread = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -536,16 +540,16 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) read loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); /* Cards with page size <= 512 bytes */ @@ -553,22 +557,22 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -576,31 +580,31 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); @@ -625,25 +629,25 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint8_t *)deviceAddress; + *buff = *(uint8_t *)deviceaddress; buff++; } /* Increment read pages number */ - numPagesRead++; + numpagesread++; /* Decrement pages to read */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -658,7 +662,6 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT } return HAL_OK; - } /** @@ -670,12 +673,16 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesRead = 0, nandAddress, nbpages = NumPageToRead; - uint16_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numpagesread = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -691,16 +698,16 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) read loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); /* Cards with page size <= 512 bytes */ @@ -708,22 +715,22 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -731,31 +738,31 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); if (hnand->Config.ExtraCommandEnable == ENABLE) @@ -779,25 +786,25 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint16_t *)deviceAddress; + *buff = *(uint16_t *)deviceaddress; buff++; } /* Increment read pages number */ - numPagesRead++; + numpagesread++; /* Decrement pages to read */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -823,12 +830,16 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite; - uint8_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numpageswritten = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -844,18 +855,18 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) write loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); /* Cards with page size <= 512 bytes */ @@ -863,22 +874,22 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -886,26 +897,26 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -913,12 +924,12 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address /* Write data to memory */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *(__IO uint8_t *)deviceAddress = *buff; + *(__IO uint8_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -940,13 +951,13 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address } /* Increment written pages number */ - numPagesWritten++; + numpageswritten++; /* Decrement pages to write */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -972,12 +983,16 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite; - uint16_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numpageswritten = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -993,18 +1008,18 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) write loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); /* Cards with page size <= 512 bytes */ @@ -1012,22 +1027,22 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1035,26 +1050,26 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1062,12 +1077,12 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres /* Write data to memory */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *(__IO uint16_t *)deviceAddress = *buff; + *(__IO uint16_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -1089,13 +1104,13 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres } /* Increment written pages number */ - numPagesWritten++; + numpageswritten++; /* Decrement pages to write */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1120,13 +1135,18 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres * @param pBuffer pointer to source buffer to write * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) + */ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumSpareAreaToRead) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead; - uint8_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numsparearearead = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1142,78 +1162,78 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = COLUMN_ADDRESS(hnand); + columnaddress = COLUMN_ADDRESS(hnand); /* Spare area(s) read loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); if (hnand->Config.ExtraCommandEnable == ENABLE) @@ -1237,25 +1257,25 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint8_t *)deviceAddress; + *buff = *(uint8_t *)deviceaddress; buff++; } /* Increment read spare areas number */ - numSpareAreaRead++; + numsparearearead++; /* Decrement spare areas to read */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1280,13 +1300,18 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) + */ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaToRead) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead; - uint16_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numsparearearead = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1302,78 +1327,78 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U); + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); /* Spare area(s) read loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); if (hnand->Config.ExtraCommandEnable == ENABLE) @@ -1397,25 +1422,25 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint16_t *)deviceAddress; + *buff = *(uint16_t *)deviceaddress; buff++; } /* Increment read spare areas number */ - numSpareAreaRead++; + numsparearearead++; /* Decrement spare areas to read */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1441,12 +1466,17 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite; - uint8_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1462,77 +1492,77 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Page address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = COLUMN_ADDRESS(hnand); + columnaddress = COLUMN_ADDRESS(hnand); /* Spare area(s) write loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1540,12 +1570,12 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad /* Write data to memory */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *(__IO uint8_t *)deviceAddress = *buff; + *(__IO uint8_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -1567,13 +1597,13 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad } /* Increment written spare areas number */ - numSpareAreaWritten++; + numspareareawritten++; /* Decrement spare areas to write */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1599,12 +1629,17 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite; - uint16_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1620,77 +1655,77 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U); + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); /* Spare area(s) write loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1698,12 +1733,12 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A /* Write data to memory */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *(__IO uint16_t *)deviceAddress = *buff; + *(__IO uint16_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -1725,13 +1760,13 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A } /* Increment written spare areas number */ - numSpareAreaWritten++; + numspareareawritten++; /* Decrement spare areas to write */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1757,7 +1792,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A */ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { - uint32_t DeviceAddress; + uint32_t deviceaddress; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1773,19 +1808,19 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - DeviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Send Erase block command sequence */ - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; __DSB(); /* Update the NAND controller state */ @@ -1852,11 +1887,12 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, + pNAND_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -1864,39 +1900,39 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND /* Process locked */ __HAL_LOCK(hnand); - if(hnand->State == HAL_NAND_STATE_READY) + if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = pCallback; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = pCallback; - break; - case HAL_NAND_IT_CB_ID : - hnand->ItCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = pCallback; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = pCallback; + break; + case HAL_NAND_IT_CB_ID : + hnand->ItCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hnand->State == HAL_NAND_STATE_RESET) + else if (hnand->State == HAL_NAND_STATE_RESET) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = pCallback; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = pCallback; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1921,46 +1957,46 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID * @retval status */ -HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hnand); - if(hnand->State == HAL_NAND_STATE_READY) + if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = HAL_NAND_MspInit; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = HAL_NAND_MspDeInit; - break; - case HAL_NAND_IT_CB_ID : - hnand->ItCallback = HAL_NAND_ITCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = HAL_NAND_MspInit; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = HAL_NAND_MspDeInit; + break; + case HAL_NAND_IT_CB_ID : + hnand->ItCallback = HAL_NAND_ITCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hnand->State == HAL_NAND_STATE_RESET) + else if (hnand->State == HAL_NAND_STATE_RESET) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = HAL_NAND_MspInit; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = HAL_NAND_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = HAL_NAND_MspInit; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = HAL_NAND_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1973,15 +2009,15 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NA __HAL_UNLOCK(hnand); return status; } -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### NAND Control functions ##### @@ -2101,8 +2137,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### NAND State functions ##### @@ -2135,17 +2171,17 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) { uint32_t data; - uint32_t DeviceAddress; + uint32_t deviceaddress; UNUSED(hnand); /* Identify the device address */ - DeviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Send Read status operation command */ - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; /* Read status register data */ - data = *(__IO uint8_t *)DeviceAddress; + data = *(__IO uint8_t *)deviceaddress; /* Return the status */ if ((data & NAND_ERROR) == NAND_ERROR) diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nand.h index 4edf511d10..a2eb70ba4e 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nand.h @@ -131,10 +131,10 @@ typedef struct NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */ - void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */ - void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */ -#endif + void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ + void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ + void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ } NAND_HandleTypeDef; #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) @@ -146,13 +146,13 @@ typedef enum HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ -}HAL_NAND_CallbackIDTypeDef; +} HAL_NAND_CallbackIDTypeDef; /** * @brief HAL NAND Callback pointer definition */ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} @@ -161,8 +161,8 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup NAND_Exported_Macros NAND Exported Macros - * @{ - */ + * @{ + */ /** @brief Reset NAND handle state * @param __HANDLE__ specifies the NAND handle. @@ -176,7 +176,7 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); } while(0) #else #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} @@ -192,7 +192,8 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, + FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); @@ -213,18 +214,25 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); */ /* IO operation functions ****************************************************/ - HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); @@ -232,9 +240,10 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressT #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /* NAND callback registering/unregistering */ -HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, + pNAND_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} @@ -266,39 +275,40 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); /** * @} */ + /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup NAND_Private_Constants NAND Private Constants * @{ */ -#define NAND_DEVICE ((uint32_t)0x80000000U) -#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U) +#define NAND_DEVICE 0x80000000UL +#define NAND_WRITE_TIMEOUT 0x01000000UL -#define CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */ -#define ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */ +#define CMD_AREA (1UL<<16U) /* A16 = CLE high */ +#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ -#define NAND_CMD_AREA_A ((uint8_t)0x00U) -#define NAND_CMD_AREA_B ((uint8_t)0x01U) -#define NAND_CMD_AREA_C ((uint8_t)0x50U) -#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) +#define NAND_CMD_AREA_A ((uint8_t)0x00) +#define NAND_CMD_AREA_B ((uint8_t)0x01) +#define NAND_CMD_AREA_C ((uint8_t)0x50) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) -#define NAND_CMD_WRITE0 ((uint8_t)0x80U) -#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) -#define NAND_CMD_ERASE0 ((uint8_t)0x60U) -#define NAND_CMD_ERASE1 ((uint8_t)0xD0U) -#define NAND_CMD_READID ((uint8_t)0x90U) -#define NAND_CMD_STATUS ((uint8_t)0x70U) -#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) -#define NAND_CMD_RESET ((uint8_t)0xFFU) +#define NAND_CMD_WRITE0 ((uint8_t)0x80) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) +#define NAND_CMD_ERASE0 ((uint8_t)0x60) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0) +#define NAND_CMD_READID ((uint8_t)0x90) +#define NAND_CMD_STATUS ((uint8_t)0x70) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) +#define NAND_CMD_RESET ((uint8_t)0xFF) /* NAND memory status */ -#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U) -#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U) -#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U) -#define NAND_BUSY ((uint32_t)0x00000000U) -#define NAND_ERROR ((uint32_t)0x00000001U) -#define NAND_READY ((uint32_t)0x00000040U) +#define NAND_VALID_ADDRESS 0x00000100UL +#define NAND_INVALID_ADDRESS 0x00000200UL +#define NAND_TIMEOUT_ERROR 0x00000400UL +#define NAND_BUSY 0x00000000UL +#define NAND_ERROR 0x00000001UL +#define NAND_READY 0x00000040UL /** * @} */ @@ -315,8 +325,14 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ - (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) + (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * \ + ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) +/** + * @brief NAND memory Column address computation. + * @param __HANDLE__ NAND handle. + * @retval NAND Raw address value + */ #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nor.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nor.c index bcf7df0193..f01efbe5cb 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nor.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nor.c @@ -151,9 +151,35 @@ #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 +#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF +#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040 +#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8 +#define NOR_CMD_CONFIRM (uint16_t)0x00D0 +#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020 +#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060 +#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070 +#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050 + /* Mask on NOR STATUS REGISTER */ +#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 +#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080 + +/* Address of the primary command set */ +#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013 + +/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */ +#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */ +#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */ +#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */ +#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */ +#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */ +#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */ +#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */ +#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */ +#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */ +#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */ /** * @} @@ -200,8 +226,11 @@ static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; * @param ExtTiming pointer to NOR extended mode timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming) { + uint32_t deviceaddress; + /* Check the NOR handle parameter */ if (hnor == NULL) { @@ -214,7 +243,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe hnor->Lock = HAL_UNLOCKED; #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - if(hnor->MspInitCallback == NULL) + if (hnor->MspInitCallback == NULL) { hnor->MspInitCallback = HAL_NOR_MspInit; } @@ -252,7 +281,29 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe /* Initialize the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - return HAL_OK; + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Get the value of the command set */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + + return HAL_NOR_ReturnToReadMode(hnor); } /** @@ -264,7 +315,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) { #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - if(hnor->MspDeInitCallback == NULL) + if (hnor->MspDeInitCallback == NULL) { hnor->MspDeInitCallback = HAL_NOR_MspDeInit; } @@ -367,6 +418,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I { uint32_t deviceaddress; HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ state = hnor->State; @@ -401,15 +453,33 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I } /* Send read ID command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Read the NOR IDs */ - pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); - pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); - pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); - pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); + if (status != HAL_ERROR) + { + /* Read the NOR IDs */ + pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); + pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE1_ADDR); + pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE2_ADDR); + pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE3_ADDR); + } /* Check the NOR controller state */ hnor->State = state; @@ -422,7 +492,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -435,6 +505,7 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { uint32_t deviceaddress; HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ state = hnor->State; @@ -468,7 +539,19 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) deviceaddress = NOR_MEMORY_ADRESS4; } - NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } /* Check the NOR controller state */ hnor->State = state; @@ -481,7 +564,7 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -496,6 +579,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint { uint32_t deviceaddress; HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ state = hnor->State; @@ -530,12 +614,27 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint } /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Read the data */ - *pData = (uint16_t)(*(__IO uint32_t *)pAddress); + if (status != HAL_ERROR) + { + /* Read the data */ + *pData = (uint16_t)(*(__IO uint32_t *)pAddress); + } /* Check the NOR controller state */ hnor->State = state; @@ -548,7 +647,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -562,6 +661,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ if (hnor->State == HAL_NOR_STATE_BUSY) @@ -595,12 +695,27 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u } /* Send program data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Write the data */ - NOR_WRITE(pAddress, *pData); + if (status != HAL_ERROR) + { + /* Write the data */ + NOR_WRITE(pAddress, *pData); + } /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -613,7 +728,7 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -625,11 +740,15 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u * @param uwBufferSize number of Half word to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize) { - uint32_t deviceaddress, size = uwBufferSize, address = uwAddress; + uint32_t deviceaddress; + uint32_t size = uwBufferSize; + uint32_t address = uwAddress; uint16_t *data = pData; HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ state = hnor->State; @@ -664,17 +783,32 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress } /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); - - /* Read buffer */ - while (size > 0U) + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - *data = *(__IO uint16_t *)address; - data++; - address += 2U; - size--; + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + if (status != HAL_ERROR) + { + /* Read buffer */ + while (size > 0U) + { + *data = *(__IO uint16_t *)address; + data++; + address += 2U; + size--; + } } /* Check the NOR controller state */ @@ -688,7 +822,7 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -700,12 +834,14 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress * @param uwBufferSize Size of the buffer to write * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize) { uint16_t *p_currentaddress; const uint16_t *p_endaddress; uint16_t *data = pData; - uint32_t lastloadedaddress, deviceaddress; + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ if (hnor->State == HAL_NOR_STATE_BUSY) @@ -739,31 +875,51 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr } /* Initialize variables */ - p_currentaddress = (uint16_t *)(uwAddress); - p_endaddress = (const uint16_t *)(uwAddress + (uwBufferSize - 1U)); - lastloadedaddress = uwAddress; + p_currentaddress = (uint16_t *)(deviceaddress + uwAddress); + p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U))); - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - - /* Write Buffer Load Command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uint16_t)(uwBufferSize - 1U)); - - /* Load Data into NOR Buffer */ - while (p_currentaddress <= p_endaddress) + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - /* Store last loaded address & data value (for polling) */ - lastloadedaddress = (uint32_t)p_currentaddress; + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(p_currentaddress, *data); - - data++; - p_currentaddress ++; + /* Write Buffer Load Command */ + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); + NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + /* Write Buffer Load Command */ + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM); + NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; } - NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); + if (status != HAL_ERROR) + { + /* Load Data into NOR Buffer */ + while (p_currentaddress <= p_endaddress) + { + NOR_WRITE(p_currentaddress, *data); + + data++; + p_currentaddress ++; + } + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); + } + else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */ + { + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM); + } + } /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -776,7 +932,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr return HAL_ERROR; } - return HAL_OK; + return status; } @@ -791,6 +947,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) { uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ if (hnor->State == HAL_NOR_STATE_BUSY) @@ -824,12 +981,30 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd } /* Send block erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK); + NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); + NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE); + NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -842,7 +1017,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd return HAL_ERROR; } - return HAL_OK; + return status; } @@ -856,6 +1031,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; UNUSED(Address); /* Check the NOR controller state */ @@ -890,12 +1066,23 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) } /* Send NOR chip erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -908,7 +1095,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -990,12 +1177,13 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, + pNOR_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -1004,20 +1192,20 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal __HAL_LOCK(hnor); state = hnor->State; - if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) + if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_NOR_MSP_INIT_CB_ID : - hnor->MspInitCallback = pCallback; - break; - case HAL_NOR_MSP_DEINIT_CB_ID : - hnor->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NOR_MSP_INIT_CB_ID : + hnor->MspInitCallback = pCallback; + break; + case HAL_NOR_MSP_DEINIT_CB_ID : + hnor->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1041,7 +1229,7 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID * @retval status */ -HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; @@ -1050,20 +1238,20 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C __HAL_LOCK(hnor); state = hnor->State; - if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) + if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_NOR_MSP_INIT_CB_ID : - hnor->MspInitCallback = HAL_NOR_MspInit; - break; - case HAL_NOR_MSP_DEINIT_CB_ID : - hnor->MspDeInitCallback = HAL_NOR_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NOR_MSP_INIT_CB_ID : + hnor->MspInitCallback = HAL_NOR_MspInit; + break; + case HAL_NOR_MSP_DEINIT_CB_ID : + hnor->MspDeInitCallback = HAL_NOR_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1083,8 +1271,8 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C */ /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### NOR Control functions ##### @@ -1106,7 +1294,7 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) { /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_PROTECTED) + if (hnor->State == HAL_NOR_STATE_PROTECTED) { /* Process Locked */ __HAL_LOCK(hnor); @@ -1140,7 +1328,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) { /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_READY) + if (hnor->State == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -1170,8 +1358,8 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) */ /** @defgroup NOR_Exported_Functions_Group4 NOR State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### NOR State functions ##### @@ -1207,7 +1395,8 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) { HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; - uint16_t tmpSR1, tmpSR2; + uint16_t tmpsr1; + uint16_t tmpsr2; uint32_t tickstart; /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ @@ -1217,45 +1406,84 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /* Get tick */ tickstart = HAL_GetTick(); - while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) { - status = HAL_NOR_STATUS_TIMEOUT; + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + status = HAL_NOR_STATUS_TIMEOUT; + } + } + + /* Read NOR status register (DQ6 and DQ5) */ + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) + { + return HAL_NOR_STATUS_SUCCESS ; + } + + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + { + status = HAL_NOR_STATUS_ONGOING; + } + + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) + { + return HAL_NOR_STATUS_SUCCESS; + } + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + { + return HAL_NOR_STATUS_ERROR; } } - - /* Read NOR status register (DQ6 and DQ5) */ - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; - - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + do { - return HAL_NOR_STATUS_SUCCESS ; - } + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + tmpsr2 = *(__IO uint16_t *)(Address); - if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) - { - status = HAL_NOR_STATUS_ONGOING; - } + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_NOR_STATUS_TIMEOUT; + } + } + } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U); - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; - - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + tmpsr1 = *(__IO uint16_t *)(Address); + if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U) { - return HAL_NOR_STATUS_SUCCESS; + /* Clear the Status Register */ + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + status = HAL_NOR_STATUS_ERROR; } - if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + else { - return HAL_NOR_STATUS_ERROR; + status = HAL_NOR_STATUS_SUCCESS; } } + else + { + /* Primary command set not supported by the driver */ + status = HAL_NOR_STATUS_ERROR; + } /* Return the operation status */ return status; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nor.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nor.h index cf6d5cf98d..ce87ef5fed 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nor.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_nor.h @@ -30,7 +30,6 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_ll_fmc.h" - /** @addtogroup STM32G4xx_HAL_Driver * @{ */ @@ -122,10 +121,12 @@ typedef struct __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ + uint32_t CommandSet; /*!< NOR algorithm command set and control */ + #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */ - void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */ -#endif + void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */ + void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */ +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ } NOR_HandleTypeDef; #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) @@ -136,13 +137,13 @@ typedef enum { HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */ HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */ -}HAL_NOR_CallbackIDTypeDef; +} HAL_NOR_CallbackIDTypeDef; /** * @brief HAL NOR Callback pointer definition */ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ @@ -164,7 +165,7 @@ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); } while(0) #else #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ @@ -179,7 +180,8 @@ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming); HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); @@ -198,8 +200,10 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); @@ -207,9 +211,10 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) /* NOR callback registering/unregistering */ -HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, + pNOR_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ @@ -247,29 +252,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @{ */ /* NOR device IDs addresses */ -#define MC_ADDRESS ((uint16_t)0x0000U) -#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) -#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) -#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) +#define MC_ADDRESS ((uint16_t)0x0000) +#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) +#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) +#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) /* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x61U) -#define CFI2_ADDRESS ((uint16_t)0x62U) -#define CFI3_ADDRESS ((uint16_t)0x63U) -#define CFI4_ADDRESS ((uint16_t)0x64U) +#define CFI1_ADDRESS ((uint16_t)0x0061) +#define CFI2_ADDRESS ((uint16_t)0x0062) +#define CFI3_ADDRESS ((uint16_t)0x0063) +#define CFI4_ADDRESS ((uint16_t)0x0064) /* NOR operation wait timeout */ -#define NOR_TMEOUT ((uint16_t)0xFFFFU) +#define NOR_TMEOUT ((uint16_t)0xFFFF) /* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x0U) -#define NOR_MEMORY_16B ((uint8_t)0x1U) +#define NOR_MEMORY_8B ((uint8_t)0x00) +#define NOR_MEMORY_16B ((uint8_t)0x01) /* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U) -#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U) -#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U) -#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U) +#define NOR_MEMORY_ADRESS1 (0x60000000U) +#define NOR_MEMORY_ADRESS2 (0x64000000U) +#define NOR_MEMORY_ADRESS3 (0x68000000U) +#define NOR_MEMORY_ADRESS4 (0x6C000000U) /** * @} */ @@ -286,7 +291,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @retval NOR shifted address value */ #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ - ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ + ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp.h index 31050a32c5..c45a19922c 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_opamp.h @@ -335,7 +335,7 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); /** @defgroup OPAMP_PowerMode OPAMP PowerMode * @{ */ -#define OPAMP_POWERMODE_NORMAL (0x00000000UL) /*!< Output in normal mode */ +#define OPAMP_POWERMODE_NORMALSPEED (0x00000000UL) /*!< Output in normal mode */ #define OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_HIGHSPEEDEN /*!< Output in highspeed mode */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.c index e36b98a3a0..8455511d47 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.c @@ -206,7 +206,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { (void)HAL_PCDEx_ActivateLPM(hpcd); } - + return HAL_OK; } @@ -298,7 +298,9 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -508,7 +510,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca * @param pCallback pointer to the USB PCD Data OUT Stage Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -581,7 +584,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd * @param pCallback pointer to the USB PCD Data IN Stage Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -654,7 +658,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -727,7 +732,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -1357,7 +1363,8 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) * @param ep_type endpoint type * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type) { HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; @@ -1534,10 +1541,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) __HAL_LOCK(hpcd); (void)USB_EPSetStall(hpcd->Instance, ep); - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); - } + __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1672,6 +1676,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) { wIstr = hpcd->Instance->ISTR; + /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); @@ -1754,8 +1759,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U) + { + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } } } } @@ -1842,9 +1850,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - /* Manage all non bulk transaction or Bulk Single Buffer Transaction */ - if ((ep->type != EP_TYPE_BULK) || - ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U))) + /* Manage Bulk Single Buffer Transaction */ + if ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U)) { /* multi-packet on the NON control IN endpoint */ TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); @@ -1876,7 +1883,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) (void)USB_EPStartXfer(hpcd->Instance, ep); } } - /* bulk in double buffer enable in case of transferLen> Ep_Mps */ + /* Double Buffer Iso/bulk IN (bulk transfer Len > Ep_Mps) */ else { (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); @@ -2000,6 +2007,9 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, /* Transfer is completed */ if (ep->xfer_len == 0U) { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2070,6 +2080,9 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, /* Transfer is completed */ if (ep->xfer_len == 0U) { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2077,7 +2090,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, HAL_PCD_DataInStageCallback(hpcd, ep->num); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - /*need to Free USB Buff*/ + /* need to Free USB Buff */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.h index df2d62b6f6..17ec7644b3 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd.h @@ -260,25 +260,41 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType * @} */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, + pPCD_BcdCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, + pPCD_LpmCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /** @@ -317,16 +333,24 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type); + HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint8_t *pBuf, uint32_t len); + +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint8_t *pBuf, uint32_t len); + + HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); + +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); /** * @} */ @@ -412,10 +436,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) /* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) /* ENDPOINT transfer */ -#define USB_EP0StartXfer USB_EPStartXfer +#define USB_EP0StartXfer USB_EPStartXfer /** * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) @@ -424,8 +448,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wType Endpoint Type. * @retval None */ -#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) +#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) /** * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) @@ -442,18 +465,19 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum, bDir * @retval None */ -#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \ - if ((bDir) == 0U) \ - { \ - /* OUT double buffered endpoint */ \ - PCD_TX_DTOG((USBx), (bEpNum)); \ - } \ - else if ((bDir) == 1U) \ - { \ - /* IN double buffered endpoint */ \ - PCD_RX_DTOG((USBx), (bEpNum)); \ - } \ -} while(0) +#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT double buffered endpoint */ \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + else if ((bDir) == 1U) \ + { \ + /* IN double buffered endpoint */ \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /** * @brief sets the status for tx transfer (bits STAT_TX[1:0]). @@ -462,21 +486,22 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wState new state * @retval None */ -#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \ - uint16_t _wRegVal; \ - \ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \ + do { \ + uint16_t _wRegVal; \ + \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \ - /* toggle first bit ? */ \ - if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ - { \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ + { \ _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ - { \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ + { \ _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ } while(0) /* PCD_SET_EP_TX_STATUS */ /** @@ -486,19 +511,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wState new state * @retval None */ -#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \ +#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \ /* toggle first bit ? */ \ if ((USB_EPRX_DTOG1 & (wState))!= 0U) \ { \ - _wRegVal ^= USB_EPRX_DTOG1; \ + _wRegVal ^= USB_EPRX_DTOG1; \ } \ /* toggle second bit ? */ \ if ((USB_EPRX_DTOG2 & (wState))!= 0U) \ { \ - _wRegVal ^= USB_EPRX_DTOG2; \ + _wRegVal ^= USB_EPRX_DTOG2; \ } \ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ } while(0) /* PCD_SET_EP_RX_STATUS */ @@ -511,7 +537,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wStatetx new state. * @retval None */ -#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \ +#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \ @@ -573,7 +600,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_SET_EP_KIND(USBx, bEpNum) do { \ +#define PCD_SET_EP_KIND(USBx, bEpNum) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ @@ -581,7 +609,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \ } while(0) /* PCD_SET_EP_KIND */ -#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \ +#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \ @@ -613,7 +642,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \ +#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \ @@ -621,7 +651,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \ } while(0) /* PCD_CLEAR_RX_EP_CTR */ -#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \ +#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \ @@ -635,7 +666,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_RX_DTOG(USBx, bEpNum) do { \ +#define PCD_RX_DTOG(USBx, bEpNum) \ + do { \ uint16_t _wEPVal; \ \ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ @@ -643,7 +675,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \ } while(0) /* PCD_RX_DTOG */ -#define PCD_TX_DTOG(USBx, bEpNum) do { \ +#define PCD_TX_DTOG(USBx, bEpNum) \ + do { \ uint16_t _wEPVal; \ \ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ @@ -656,7 +689,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \ +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ @@ -667,7 +701,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } \ } while(0) /* PCD_CLEAR_RX_DTOG */ -#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \ +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ @@ -685,7 +720,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bAddr Address. * @retval None */ -#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \ +#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \ @@ -711,23 +747,25 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wAddr address to be set (must be word aligned). * @retval None */ -#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \ - __IO uint16_t *_wRegVal; \ - uint32_t _wRegBase = (uint32_t)USBx; \ - \ - _wRegBase += (uint32_t)(USBx)->BTABLE; \ - _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ - *_wRegVal = ((wAddr) >> 1) << 1; \ -} while(0) /* PCD_SET_EP_TX_ADDRESS */ +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \ + do { \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ + } while(0) /* PCD_SET_EP_TX_ADDRESS */ -#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \ - __IO uint16_t *_wRegVal; \ - uint32_t _wRegBase = (uint32_t)USBx; \ - \ - _wRegBase += (uint32_t)(USBx)->BTABLE; \ - _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ - *_wRegVal = ((wAddr) >> 1) << 1; \ -} while(0) /* PCD_SET_EP_RX_ADDRESS */ +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \ + do { \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ + } while(0) /* PCD_SET_EP_RX_ADDRESS */ /** * @brief Gets address of the tx/rx buffer. @@ -745,7 +783,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wNBlocks no. of Blocks. * @retval None */ -#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \ +#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ + do { \ (wNBlocks) = (wCount) >> 5; \ if (((wCount) & 0x1fU) == 0U) \ { \ @@ -754,7 +793,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \ } while(0) /* PCD_CALC_BLK32 */ -#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \ +#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ + do { \ (wNBlocks) = (wCount) >> 1; \ if (((wCount) & 0x1U) != 0U) \ { \ @@ -763,7 +803,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); *(pdwReg) = (uint16_t)((wNBlocks) << 10); \ } while(0) /* PCD_CALC_BLK2 */ -#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \ +#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \ + do { \ uint32_t wNBlocks; \ if ((wCount) == 0U) \ { \ @@ -780,10 +821,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } \ } while(0) /* PCD_SET_EP_CNT_RX_REG */ -#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \ - uint32_t _wRegBase = (uint32_t)(USBx); \ - __IO uint16_t *pdwReg; \ - \ +#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *pdwReg; \ + \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \ @@ -796,23 +838,25 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wCount Counter value. * @retval None */ -#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \ +#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \ + do { \ uint32_t _wRegBase = (uint32_t)(USBx); \ __IO uint16_t *_wRegVal; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ *_wRegVal = (uint16_t)(wCount); \ -} while(0) + } while(0) -#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \ +#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \ + do { \ uint32_t _wRegBase = (uint32_t)(USBx); \ __IO uint16_t *_wRegVal; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \ -} while(0) + } while(0) /** * @brief gets counter of the tx buffer. @@ -830,10 +874,13 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wBuf0Addr buffer 0 address. * @retval Counter value */ -#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \ +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \ + do { \ PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \ } while(0) /* PCD_SET_EP_DBUF0_ADDR */ -#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \ + +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \ + do { \ PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \ } while(0) /* PCD_SET_EP_DBUF1_ADDR */ @@ -845,7 +892,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wBuf1Addr = buffer 1 address. * @retval None */ -#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \ +#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \ + do { \ PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \ PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \ } while(0) /* PCD_SET_EP_DBUF_ADDR */ @@ -868,7 +916,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wCount: Counter value * @retval None */ -#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \ +#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ if ((bDir) == 0U) \ /* OUT endpoint */ \ { \ @@ -884,7 +933,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } \ } while(0) /* SetEPDblBuf0Count*/ -#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \ +#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ uint32_t _wBase = (uint32_t)(USBx); \ __IO uint16_t *_wEPRegVal; \ \ @@ -905,7 +955,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } \ } while(0) /* SetEPDblBuf1Count */ -#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \ +#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ } while(0) /* PCD_SET_EP_DBUF_CNT */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd_ex.c index 1fe3b6bcf4..91ad5f7060 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd_ex.c @@ -78,10 +78,8 @@ * @retval HAL status */ -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress) +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, + uint16_t ep_kind, uint32_t pmaadress) { PCD_EPTypeDef *ep; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd_ex.h index e8c1b2e790..2c74eb0bb0 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_pcd_ex.h @@ -49,10 +49,8 @@ extern "C" { -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress); +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, + uint16_t ep_kind, uint32_t pmaadress); HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.c index 879efa617d..5d9afdadfc 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.c @@ -918,10 +918,10 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Set the RTC_TR register */ WRITE_REG(RTC->TR, (tmpreg & RTC_TR_RESERVED_MASK)); - /* Clear the bits to be configured */ + /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ CLEAR_BIT(RTC->CR, RTC_CR_BKP); - /* Configure the RTC_CR register */ + /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ SET_BIT(RTC->CR, (sTime->DayLightSaving | sTime->StoreOperation)); /* Exit Initialization mode */ @@ -1744,6 +1744,10 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + return HAL_TIMEOUT; } } @@ -1798,7 +1802,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) UNUSED(hrtc); /* Clear RSF flag */ - SET_BIT(RTC->ICSR, RTC_RSF_MASK); + CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF); tickstart = HAL_GetTick(); @@ -1959,6 +1963,72 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value) return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU)); } +/** + * @brief Daylight Saving Time, Add one hour to the calendar in one single operation + * without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(RTC->CR, RTC_CR_ADD1H); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Subtract one hour from the calendar in one + * single operation without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(RTC->CR, RTC_CR_SUB1H); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Set the store operation bit. + * @note It can be used by the software in order to memorize the DST status. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(RTC->CR, RTC_CR_BKP); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Clear the store operation bit. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + CLEAR_BIT(RTC->CR, RTC_CR_BKP); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Read the store operation bit. + * @param hrtc RTC handle + * @retval operation see RTC_StoreOperation_Definitions + */ +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + return READ_BIT(RTC->CR, RTC_CR_BKP); +} + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.h index 5e66443420..3fa2e84d4e 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc.h @@ -111,12 +111,11 @@ typedef struct with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function */ - uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. - This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ + uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time, + please use HAL_RTC_DST_xxx functions */ - uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BKP bit - in CR register to store the operation. - This parameter can be a value of @ref RTC_StoreOperation_Definitions */ + uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time, + please use HAL_RTC_DST_xxx functions */ } RTC_TimeTypeDef; /** @@ -562,6 +561,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** * @brief Add 1 hour (summer time change). + * @note This interface is deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions * @param __HANDLE__ specifies the RTC handle. * @param __BKP__ Backup * This parameter can be: @@ -579,6 +580,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** * @brief Subtract 1 hour (winter time change). + * @note This interface is deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions * @param __HANDLE__ specifies the RTC handle. * @param __BKP__ Backup * This parameter can be: @@ -815,6 +818,11 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); /** * @} */ @@ -870,7 +878,6 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ RTC_DR_DU) #define RTC_INIT_MASK 0xFFFFFFFFU -#define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) #define RTC_TIMEOUT_VALUE 1000U diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc_ex.c index fc3adce9c5..f43bd1fc0d 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_rtc_ex.c @@ -225,16 +225,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti hrtc->State = HAL_RTC_STATE_BUSY; - /* RTC timestamp Interrupt Configuration: EXTI configuration (always rising edge)*/ - __HAL_RTC_TIMESTAMP_EXTI_RISING_IT(); - __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT(); - - /* Get the RTC_CR register and clear the bits to be configured */ - CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE)); - /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /* Get the RTC_CR register and clear the bits to be configured */ + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE)); + /* Configure the Time Stamp TSEDGE before Enable bit to avoid unwanted TSF setting. */ SET_BIT(RTC->CR, (uint32_t)TimeStampEdge); @@ -247,6 +243,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* RTC timestamp Interrupt Configuration: EXTI configuration (always rising edge)*/ + __HAL_RTC_TIMESTAMP_EXTI_RISING_IT(); + __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT(); + hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -490,6 +490,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + return HAL_TIMEOUT; } } @@ -792,6 +796,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + return HAL_TIMEOUT; } } @@ -1282,6 +1290,10 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + return HAL_TIMEOUT; } } diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.c index 85581f3cbb..c8137fb088 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.c @@ -199,23 +199,24 @@ /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants * @{ */ -#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ +#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ - USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE | USART_CR1_OVER8| \ + USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \ - USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ +#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ + USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ -#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \ + USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \ - USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \ + USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ -#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ +#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ /** * @} */ @@ -2345,7 +2346,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard uint32_t tmpreg; SMARTCARD_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; - const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; uint32_t pclk; /* Check the parameters */ @@ -2370,8 +2371,8 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * Configure the Parity and Mode: * set PS bit according to hsmartcard->Init.Parity value * set TE and RE bits according to hsmartcard->Init.Mode value */ - tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode; - tmpreg |= (uint32_t) hsmartcard->Init.WordLength | hsmartcard->FifoMode; + tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) | + ((uint32_t)hsmartcard->Init.WordLength)); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.h index 4af3163117..7896477c91 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard.h @@ -163,7 +163,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called) + * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -180,7 +180,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -346,15 +346,15 @@ typedef enum /** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition * @{ */ -#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */ +#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */ #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) -#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** * @} @@ -690,13 +690,13 @@ typedef enum */ #define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U <<\ + ((__HANDLE__)->Instance->CR1 |= (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U <<\ + ((__HANDLE__)->Instance->CR2 |= (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U <<\ + ((__HANDLE__)->Instance->CR3 |= (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. @@ -723,13 +723,13 @@ typedef enum */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U <<\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U <<\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U <<\ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. @@ -754,9 +754,9 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__)\ - & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U)\ +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\ + (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\ + & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\ ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. @@ -788,8 +788,9 @@ typedef enum SMARTCARD_CR_POS) == 0x02U)?\ (__HANDLE__)->Instance->CR2 : \ (__HANDLE__)->Instance->CR3)) &\ - ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__))\ - & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) + (0x01UL << (((uint16_t)(__INTERRUPT__))\ + & SMARTCARD_IT_MASK))) != 0U)\ + ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the SMARTCARD Handle. diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard_ex.c index ad2626fade..327d021287 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smartcard_ex.c @@ -458,8 +458,8 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE) { diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus.h index 2bb2d88287..a81bbb2e1a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus.h @@ -27,6 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32g4xx_hal_def.h" +#include "stm32g4xx_hal_smbus_ex.h" /** @addtogroup STM32G4xx_HAL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus_ex.c new file mode 100644 index 0000000000..db6ed3ad30 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus_ex.c @@ -0,0 +1,156 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_smbus_ex.c + * @author MCD Application Team + * @brief SMBUS Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of SMBUS Extended peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### SMBUS peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the SMBUS interface for STM32G4xx + devices contains the following additional features + + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_SMBUSEx_EnableFastModePlus() + (++) HAL_SMBUSEx_DisableFastModePlus() + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @defgroup SMBUSEx SMBUSEx + * @brief SMBUS Extended HAL module driver + * @{ + */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Enable the SMBUS fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref SMBUSEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @retval None + */ +void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the SMBUS fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref SMBUSEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @retval None + */ +void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SMBUS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus_ex.h new file mode 100644 index 0000000000..5b023965b7 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_smbus_ex.h @@ -0,0 +1,146 @@ +/** + ****************************************************************************** + * @file stm32g4xx_hal_smbus_ex.h + * @author MCD Application Team + * @brief Header file of SMBUS HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32G4xx_HAL_SMBUS_EX_H +#define STM32G4xx_HAL_SMBUS_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32g4xx_hal_def.h" + +/** @addtogroup STM32G4xx_HAL_Driver + * @{ + */ + +/** @addtogroup SMBUSEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants + * @{ + */ + +/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus + * @{ + */ +#define SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#define SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#if defined(SYSCFG_CFGR1_I2C4_FMP) +#define SMBUS_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ +#else +#define SMBUS_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions + * @{ + */ +void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros + * @{ + */ +#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & SMBUS_FMP_NOT_SUPPORTED) != SMBUS_FMP_NOT_SUPPORTED) && \ + ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8)) == SMBUS_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9)) == SMBUS_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C4)) == SMBUS_FASTMODEPLUS_I2C4))) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32g4xx_hal_smbus_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32G4xx_HAL_SMBUS_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_spi.c index 5fa006098c..58b6d3964b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_spi.c @@ -1007,6 +1007,9 @@ error: */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; @@ -1173,12 +1176,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) { @@ -1190,7 +1197,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 goto error; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } } @@ -1235,6 +1244,9 @@ error : HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; uint32_t tmp_mode; @@ -1476,12 +1488,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -1493,7 +1509,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD goto error; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } } @@ -3048,6 +3066,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3072,12 +3093,16 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -3087,7 +3112,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } } @@ -3152,6 +3179,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3175,7 +3205,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { @@ -3185,7 +3217,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } #endif /* USE_SPI_CRC */ @@ -3520,8 +3554,12 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 8bit CRC to flush Data Register */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); hspi->CRCSize--; @@ -3628,8 +3666,12 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 16bit CRC to flush Data Register */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); @@ -3684,8 +3726,12 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 8bit CRC to flush Data Register */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); hspi->CRCSize--; @@ -3738,8 +3784,12 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 16bit CRC to flush Data Register */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); @@ -3914,6 +3964,7 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { + __IO uint32_t tmpreg; __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; @@ -3929,8 +3980,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, { if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) { - /* Read 8bit CRC to flush Data Register */ - READ_REG(*((__IO uint8_t *)&hspi->Instance->DR)); + /* Flush Data Register by a blank read */ + tmpreg = READ_REG(*((__IO uint8_t *)&hspi->Instance->DR)); + /* To avoid GCC warning */ + UNUSED(tmpreg); } if (Timeout != HAL_MAX_DELAY) diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sram.c index da4d951e04..a07ee118b2 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sram.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sram.c @@ -128,20 +128,14 @@ * @{ */ -/** - @cond 0 - */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void SRAM_DMACplt (DMA_HandleTypeDef *hdma); +static void SRAM_DMACplt(DMA_HandleTypeDef *hdma); static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma); -static void SRAM_DMAError (DMA_HandleTypeDef *hdma); -/** - @endcond - */ +static void SRAM_DMAError(DMA_HandleTypeDef *hdma); /* Exported functions --------------------------------------------------------*/ @@ -171,7 +165,8 @@ static void SRAM_DMAError (DMA_HandleTypeDef *hdma); * @param ExtTiming Pointer to SRAM extended mode timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming) { /* Check the SRAM handle parameter */ if (hsram == NULL) @@ -185,7 +180,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp hsram->Lock = HAL_UNLOCKED; #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - if(hsram->MspInitCallback == NULL) + if (hsram->MspInitCallback == NULL) { hsram->MspInitCallback = HAL_SRAM_MspInit; } @@ -197,7 +192,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp #else /* Initialize the low level hardware (MSP) */ HAL_SRAM_MspInit(hsram); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } /* Initialize SRAM control Interface */ @@ -207,7 +202,8 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); /* Initialize SRAM extended mode timing Interface */ - (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); + (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, + hsram->Init.ExtendedMode); /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); @@ -227,7 +223,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) { #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - if(hsram->MspDeInitCallback == NULL) + if (hsram->MspDeInitCallback == NULL) { hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; } @@ -237,7 +233,7 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) #else /* De-Initialize the low level hardware (MSP) */ HAL_SRAM_MspDeInit(hsram); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /* Configure the SRAM registers with their reset values */ (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); @@ -342,11 +338,12 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint8_t *psramaddress = (uint8_t *)pAddress; - uint8_t * pdestbuff = pDstBuffer; + uint8_t *pdestbuff = pDstBuffer; HAL_SRAM_StateTypeDef state = hsram->State; /* Check the SRAM controller state */ @@ -389,11 +386,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint8_t *psramaddress = (uint8_t *)pAddress; - uint8_t * psrcbuff = pSrcBuffer; + uint8_t *psrcbuff = pSrcBuffer; /* Check the SRAM controller state */ if (hsram->State == HAL_SRAM_STATE_READY) @@ -435,7 +433,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint32_t *psramaddress = pAddress; @@ -456,7 +455,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); /* Read data from memory */ - for (size = BufferSize; size != limit; size-=2U) + for (size = BufferSize; size != limit; size -= 2U) { *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); pdestbuff++; @@ -494,11 +493,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint32_t *psramaddress = pAddress; - uint16_t * psrcbuff = pSrcBuffer; + uint16_t *psrcbuff = pSrcBuffer; uint8_t limit; /* Check the SRAM controller state */ @@ -514,7 +514,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); /* Write data to memory */ - for (size = BufferSize; size != limit; size-=2U) + for (size = BufferSize; size != limit; size -= 2U) { *psramaddress = (uint32_t)(*psrcbuff); psrcbuff++; @@ -552,11 +552,12 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { uint32_t size; - __IO uint32_t * psramaddress = pAddress; - uint32_t * pdestbuff = pDstBuffer; + __IO uint32_t *psramaddress = pAddress; + uint32_t *pdestbuff = pDstBuffer; HAL_SRAM_StateTypeDef state = hsram->State; /* Check the SRAM controller state */ @@ -599,11 +600,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { uint32_t size; - __IO uint32_t * psramaddress = pAddress; - uint32_t * psrcbuff = pSrcBuffer; + __IO uint32_t *psramaddress = pAddress; + uint32_t *psrcbuff = pSrcBuffer; /* Check the SRAM controller state */ if (hsram->State == HAL_SRAM_STATE_READY) @@ -645,7 +647,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { HAL_StatusTypeDef status; HAL_SRAM_StateTypeDef state = hsram->State; @@ -678,7 +681,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres } else { - return HAL_ERROR; + status = HAL_ERROR; } return status; @@ -693,7 +696,8 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { HAL_StatusTypeDef status; @@ -718,7 +722,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre } else { - return HAL_ERROR; + status = HAL_ERROR; } return status; @@ -736,12 +740,13 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -750,20 +755,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = pCallback; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = pCallback; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -789,7 +794,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID * @retval status */ -HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; @@ -798,42 +803,42 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = HAL_SRAM_MspInit; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; - break; - case HAL_SRAM_DMA_XFER_CPLT_CB_ID : - hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - break; - case HAL_SRAM_DMA_XFER_ERR_CB_ID : - hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(state == HAL_SRAM_STATE_RESET) + else if (state == HAL_SRAM_STATE_RESET) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = HAL_SRAM_MspInit; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -858,12 +863,13 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -872,20 +878,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_DMA_XFER_CPLT_CB_ID : - hsram->DmaXferCpltCallback = pCallback; - break; - case HAL_SRAM_DMA_XFER_ERR_CB_ID : - hsram->DmaXferErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = pCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -898,15 +904,15 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR __HAL_UNLOCK(hsram); return status; } -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup SRAM_Exported_Functions_Group3 Control functions - * @brief Control functions - * + * @brief Control functions + * @verbatim ============================================================================== ##### SRAM Control functions ##### @@ -928,7 +934,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) { /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) + if (hsram->State == HAL_SRAM_STATE_PROTECTED) { /* Process Locked */ __HAL_LOCK(hsram); @@ -962,7 +968,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) { /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_READY) + if (hsram->State == HAL_SRAM_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsram); @@ -992,8 +998,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) */ /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### SRAM State functions ##### @@ -1025,9 +1031,6 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) * @} */ -/** - @cond 0 - */ /** * @brief DMA SRAM process complete callback. * @param hdma : DMA handle @@ -1035,7 +1038,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) */ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) { - SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent); + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ __HAL_DMA_DISABLE(hdma); @@ -1047,7 +1050,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) hsram->DmaXferCpltCallback(hdma); #else HAL_SRAM_DMA_XferCpltCallback(hdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } /** @@ -1057,7 +1060,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) { - SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent); + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ __HAL_DMA_DISABLE(hdma); @@ -1069,7 +1072,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) hsram->DmaXferCpltCallback(hdma); #else HAL_SRAM_DMA_XferCpltCallback(hdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } /** @@ -1079,7 +1082,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) { - SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent); + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ __HAL_DMA_DISABLE(hdma); @@ -1091,11 +1094,8 @@ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) hsram->DmaXferErrorCallback(hdma); #else HAL_SRAM_DMA_XferErrorCallback(hdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } -/** - @endcond - */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sram.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sram.h index 90c674db95..9ccff8cffc 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sram.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_sram.h @@ -62,7 +62,7 @@ typedef enum typedef struct __SRAM_HandleTypeDef #else typedef struct -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ { FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ @@ -77,11 +77,11 @@ typedef struct DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */ - void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */ - void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */ - void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */ -#endif + void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ + void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ + void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } SRAM_HandleTypeDef; #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) @@ -94,14 +94,14 @@ typedef enum HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ -}HAL_SRAM_CallbackIDTypeDef; +} HAL_SRAM_CallbackIDTypeDef; /** * @brief HAL SRAM Callback pointer definition */ typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} */ @@ -110,8 +110,8 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); /* Exported macro ------------------------------------------------------------*/ /** @defgroup SRAM_Exported_Macros SRAM Exported Macros - * @{ - */ + * @{ + */ /** @brief Reset SRAM handle state * @param __HANDLE__ SRAM handle @@ -125,7 +125,7 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); } while(0) #else #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} @@ -137,11 +137,12 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); */ /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ + * @{ + */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming); HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); @@ -151,36 +152,46 @@ void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); */ /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions - * @{ - */ + * @{ + */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) /* SRAM callback registering/unregistering */ -HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); -HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback); -#endif +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} */ /** @addtogroup SRAM_Exported_Functions_Group3 Control functions - * @{ - */ + * @{ + */ /* SRAM Control functions ****************************************************/ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); @@ -191,8 +202,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); */ /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions - * @{ - */ + * @{ + */ /* SRAM State functions ******************************************************/ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.c index fd78efb895..e9711093c5 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.c @@ -510,7 +510,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - + /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); @@ -569,6 +569,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1085,6 +1086,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1105,6 +1107,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1125,6 +1128,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1144,6 +1148,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1721,6 +1726,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1741,6 +1747,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1760,6 +1767,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Capture/Compare 3 request */ @@ -1779,6 +1787,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -2074,7 +2083,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2156,7 +2165,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2308,12 +2317,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Set the TIM channel state */ if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { @@ -2344,6 +2353,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -2363,6 +2373,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -2382,6 +2393,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -2401,6 +2413,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -2683,11 +2696,12 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2702,9 +2716,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2719,7 +2733,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2739,11 +2753,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2755,7 +2770,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2781,11 +2796,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2800,9 +2816,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2817,7 +2833,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2843,11 +2859,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2865,7 +2882,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -3137,7 +3154,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3150,7 +3167,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3163,9 +3180,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3255,7 +3272,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - else + else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -3291,7 +3308,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3304,7 +3321,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3317,9 +3334,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3417,7 +3434,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - else + else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -3457,12 +3474,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch if (Channel == TIM_CHANNEL_1) { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData1 == NULL) && (Length > 0U)) { @@ -3482,12 +3499,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData2 == NULL) && (Length > 0U)) { @@ -3507,16 +3524,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) { @@ -3550,6 +3567,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3574,6 +3592,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3599,6 +3618,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -3612,6 +3632,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the Peripheral */ @@ -3690,7 +3711,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - else + else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -4587,8 +4608,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4604,8 +4626,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4621,8 +4644,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4638,8 +4662,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4655,8 +4680,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4672,8 +4698,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4689,8 +4716,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4916,8 +4944,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4933,8 +4962,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4950,8 +4980,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4967,8 +4998,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4984,8 +5016,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -5001,8 +5034,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -5018,8 +5052,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -5491,7 +5526,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo #endif /* TIM20 */ #if defined (HRTIM1) case TIM_CLOCKSOURCE_ITR10: -#endif /* HRTIM1 */ +#endif /* HRTIM1 */ case TIM_CLOCKSOURCE_ITR11: { /* Check whether or not the timer instance supports internal trigger input */ @@ -6177,7 +6212,7 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID - * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transistion Error Callback ID + * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID * @retval status */ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) @@ -6509,12 +6544,12 @@ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; - + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - + return channel_state; } @@ -6527,7 +6562,7 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - + return htim->DMABurstState; } @@ -6591,14 +6626,14 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) * @param hdma pointer to DMA handle. * @retval None */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); @@ -6607,7 +6642,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -6616,7 +6651,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); @@ -6625,7 +6660,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); @@ -6696,7 +6731,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); @@ -6706,7 +6741,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -6716,7 +6751,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); @@ -6726,7 +6761,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.h index b7516e4d20..f9ac00d81f 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim.h @@ -1142,32 +1142,32 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ @@ -2299,7 +2299,7 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ (__HANDLE__)->ChannelState[5]) - + #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ @@ -2322,7 +2322,7 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ (__HANDLE__)->ChannelNState[3]) - + #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim_ex.c index 1ee2f14176..6148affbef 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_tim_ex.c @@ -340,9 +340,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -352,7 +352,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - + /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -420,9 +420,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -506,12 +506,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Set the TIM channel state */ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - ||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { @@ -541,6 +541,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Enable the DMA channel for Capture 1*/ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the capture compare 1 Interrupt */ @@ -643,7 +644,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { return HAL_ERROR; } - + /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); @@ -925,6 +926,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -944,6 +946,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -963,6 +966,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -982,6 +986,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -1426,6 +1431,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -1445,6 +1451,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1464,6 +1471,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1483,6 +1491,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1614,8 +1623,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1624,22 +1635,28 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); - HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); @@ -1655,8 +1672,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1680,8 +1699,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1690,8 +1711,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1700,22 +1723,28 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); - HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -1737,8 +1766,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1768,8 +1799,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -3401,12 +3434,12 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; - + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); - + return channel_state; } /** @@ -3473,7 +3506,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); @@ -3482,7 +3515,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -3491,7 +3524,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); @@ -3500,7 +3533,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); @@ -3525,7 +3558,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) * @param hdma pointer to DMA handle. * @retval None */ -void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -3548,13 +3581,13 @@ void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) { /* nothing to do */ } - + #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.c index 15d681ada8..fb5c3e8037 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.c @@ -114,6 +114,10 @@ (+) MspInitCallback : UART MspInit. (+) MspDeInitCallback : UART MspDeInit. + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback(). + [..] By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: @@ -173,27 +177,23 @@ /** @defgroup UART_Private_Constants UART Private Constants * @{ */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ - USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ - USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ + USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ #define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ #define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ #define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ #define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ - /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; - /* Private function prototypes -----------------------------------------------*/ /** @addtogroup UART_Private_Functions * @{ @@ -223,6 +223,15 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); * @} */ +/* Exported Constants --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Constants + * @{ + */ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @defgroup UART_Exported_Functions UART Exported Functions @@ -646,6 +655,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; __HAL_UNLOCK(huart); @@ -935,6 +945,74 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR return status; } + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + return status; +} + #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** @@ -1000,6 +1078,10 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR (+) HAL_UART_AbortTransmitCpltCallback() (+) HAL_UART_AbortReceiveCpltCallback() + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: + (+) HAL_UARTEx_RxEventCallback() + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is @@ -1144,6 +1226,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); @@ -1296,58 +1379,20 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, __HAL_LOCK(huart); - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = Size; - huart->RxISR = NULL; + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Configure Rx interrupt processing*/ - if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + if (!(IS_LPUART_INSTANCE(huart->Instance))) { - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) { - huart->RxISR = UART_RxISR_16BIT_FIFOEN; + /* Enable the UART Receiver Timeout Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } - else - { - huart->RxISR = UART_RxISR_8BIT_FIFOEN; - } - - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - } - else - { - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->RxISR = UART_RxISR_16BIT; - } - else - { - huart->RxISR = UART_RxISR_8BIT; - } - - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); } - return HAL_OK; + return (UART_Start_Receive_IT(huart, pData, Size)); } else { @@ -1453,53 +1498,20 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData __HAL_LOCK(huart); - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - if (huart->hdmarx != NULL) + if (!(IS_LPUART_INSTANCE(huart->Instance))) { - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - __HAL_UNLOCK(huart); - - /* Restore huart->gState to ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_ERROR; + /* Enable the UART Receiver Timeout Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; + return (UART_Start_Receive_DMA(huart, pData, Size)); } else { @@ -1660,6 +1672,12 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) USART_CR1_TCIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { @@ -1729,6 +1747,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1811,6 +1830,12 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { @@ -1847,6 +1872,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; return HAL_OK; } @@ -1874,6 +1900,12 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ @@ -1982,6 +2014,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* As no DMA to be aborted, call directly user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -2106,6 +2139,12 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { @@ -2141,6 +2180,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* As no DMA to be aborted, call directly user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -2165,6 +2205,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* As no DMA to be aborted, call directly user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -2347,6 +2388,93 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* End if some error occurs */ + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + } + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + } + } + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) { @@ -2531,6 +2659,24 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) */ } +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + /** * @} */ @@ -2853,6 +2999,7 @@ void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ } #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -2899,7 +3046,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - tmpreg |= (uint32_t)huart->FifoMode; MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ @@ -3189,6 +3335,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; __HAL_UNLOCK(huart); @@ -3255,6 +3402,134 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ return HAL_OK; } +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + } + + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + /** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). @@ -3283,8 +3558,15 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Reset RxIsr function pointer */ huart->RxISR = NULL; @@ -3367,15 +3649,37 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } } + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } /** @@ -3387,13 +3691,29 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Half complete callback*/ - huart->RxHalfCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else - /*Call legacy weak Rx Half complete callback*/ - HAL_UART_RxHalfCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } /** @@ -3498,6 +3818,7 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Call user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -3549,6 +3870,7 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Call user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -3616,6 +3938,7 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Call user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -3828,13 +4151,33 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } else @@ -3880,13 +4223,33 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } else @@ -3907,18 +4270,66 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { uint16_t uhMask = huart->Mask; uint16_t uhdata; - uint16_t nb_rx_data; + uint16_t nb_rx_data; uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) { - for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); huart->pRxBuffPtr++; huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } if (huart->RxXferCount == 0U) { @@ -3935,13 +4346,33 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } @@ -3981,19 +4412,67 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) uint16_t *tmp; uint16_t uhMask = huart->Mask; uint16_t uhdata; - uint16_t nb_rx_data; + uint16_t nb_rx_data; uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) { - for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); tmp = (uint16_t *) huart->pRxBuffPtr ; *tmp = (uint16_t)(uhdata & uhMask); huart->pRxBuffPtr += 2U; huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } if (huart->RxXferCount == 0U) { @@ -4010,13 +4489,33 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.h index bf38d1a578..64fb89dea2 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart.h @@ -46,54 +46,54 @@ extern "C" { */ typedef struct { - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate register is computed using the following formula: - LPUART: - ======= - Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / - ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / - ((huart->Init.BaudRate)))[3:0]) >> 1 - where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + LPUART: + ======= + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler + UART: + ===== + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length. */ + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits. */ + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode. */ + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, - to achieve higher speed (up to f_PCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. */ + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ - uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ - uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. - This parameter can be a value of @ref UART_ClockPrescaler. */ + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ } UART_InitTypeDef; @@ -151,7 +151,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -168,7 +168,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -192,6 +192,17 @@ typedef enum UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ } UART_ClockSourceTypeDef; +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * It is expected to admit following values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + /** * @brief UART handle Structure definition */ @@ -224,6 +235,8 @@ typedef struct __UART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ @@ -255,6 +268,7 @@ typedef struct __UART_HandleTypeDef void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ @@ -288,7 +302,9 @@ typedef enum /** * @brief HAL UART Callback pointer definition */ -typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -328,16 +344,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_Error_Definition UART Error Definition * @{ */ -#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ -#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -790,6 +806,20 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @} */ +/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ + +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; /** * @} @@ -1200,7 +1230,6 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) - /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. * @param __BAUD__ Baud rate set by the user. @@ -1547,12 +1576,6 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /* Include UART HAL Extended module */ #include "stm32g4xx_hal_uart_ex.h" - -/* Prescaler Table used in BRR computation macros. - Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ -extern const uint16_t UARTPrescTable[12]; - - /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ @@ -1576,6 +1599,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** @@ -1614,6 +1640,8 @@ void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + /** * @} */ @@ -1659,13 +1687,15 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); * @{ */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.c index fe2678b90c..b854fa7141 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.c @@ -332,6 +332,41 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (+) Detection of inactivity period (RX line has not been active for a given period). + (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (+) Detection that a specific character has been received. + + (#) There are two mode of transfer: + (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (+) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (+) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (+) HAL_UARTEx_ReceiveToIdle_DMA() + @endverbatim * @{ */ @@ -652,6 +687,259 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 return HAL_OK; } +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + status = UART_Start_Receive_IT(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + /** * @} */ @@ -694,8 +982,8 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) { diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.h index 2450681d71..d88d61fa29 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_uart_ex.h @@ -99,12 +99,12 @@ typedef struct * @brief UART TXFIFO threshold level * @{ */ -#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ -#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ /** * @} */ @@ -113,12 +113,12 @@ typedef struct * @brief UART RXFIFO threshold level * @{ */ -#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ -#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ /** * @} */ @@ -174,6 +174,12 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart.h index a51ac4e2e6..5d213cb5fa 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart.h @@ -220,17 +220,17 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin /** @defgroup USART_Error_Definition USART Error Definition * @{ */ -#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ -#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U) /*!< SPI slave underrun error */ +#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ -#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */ +#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */ /** * @} */ @@ -266,15 +266,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @} */ -/** @defgroup USART_Over_Sampling USART Over Sampling - * @{ - */ -#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - /** @defgroup USART_Clock USART Clock * @{ */ @@ -556,10 +547,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -581,10 +572,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. @@ -607,7 +598,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ + & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. @@ -836,14 +827,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) -/** - * @brief Ensure that USART oversampling is valid. - * @param __SAMPLING__ USART oversampling. - * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ -#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == USART_OVERSAMPLING_8)) - /** * @brief Ensure that USART clock state is valid. * @param __CLOCK__ USART clock state. diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.c index a013c54de0..45908ad84d 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.c @@ -503,8 +503,8 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (husart->FifoMode == USART_FIFOMODE_DISABLE) { diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.h index 96a67cdf8c..e03d595adb 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_usart_ex.h @@ -45,9 +45,9 @@ extern "C" { /** @defgroup USARTEx_Word_Length USARTEx Word Length * @{ */ -#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ #define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ +#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.c index 01ed73bdc2..43ae8593e1 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_hal_wwdg.c @@ -21,6 +21,13 @@ before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window. (+) Once enabled the WWDG cannot be disabled except by a system reset. + (+) If required by application, an Early Wakeup Interrupt can be triggered + in order to be warned before WWDG expiration. The Early Wakeup Interrupt + (EWI) can be used if specific safety operations or data logging must + be performed before the actual reset is generated. When the downcounter + reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt + line to be enabled in NVIC. Once enabled, EWI interrupt cannot be + disabled except by a system reset. (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG reset occurs. (+) The WWDG counter input clock is derived from the APB clock divided @@ -34,7 +41,8 @@ (+) Typical values: (++) Counter min (T[5;0] = 0x00) at 170MHz (PCLK1) with zero prescaler: max timeout before reset: approximately 24.09µs - (++) Counter max (T[5;0] = 0x3F) at 170MHz (PCLK1) with prescaler dividing by 128: + (++) Counter max (T[5;0] = 0x3F) at 170MHz (PCLK1) with prescaler + dividing by 128: max timeout before reset: approximately 197.38ms ##### How to use this driver ##### @@ -45,16 +53,16 @@ [..] (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). - (+) Set the WWDG prescaler, refresh window and counter value - using HAL_WWDG_Init() function. - (+) Start the WWDG using HAL_WWDG_Start() function. - When the WWDG is enabled the counter value should be configured to - a value greater than 0x40 to prevent generating an immediate reset. - (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is - generated when the counter reaches 0x40, and then start the WWDG using - HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can - add his own code by customization of callback HAL_WWDG_WakeupCallback. - Once enabled, EWI interrupt cannot be disabled except by a system reset. + (+) Configure the WWDG prescaler, refresh window value, counter value and early + interrupt status using HAL_WWDG_Init() function. This will automatically + enable WWDG and start its downcounter. Time reference can be taken from + function exit. Care must be taken to provide a counter value + greater than 0x40 to prevent generation of immediate reset. + (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is + generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is + triggered by the interrupt service routine, flag will be automatically + cleared and HAL_WWDG_WakeupCallback user callback will be executed. User + can add his own code by customization of callback HAL_WWDG_WakeupCallback. (+) Then the application program must refresh the WWDG counter at regular intervals during normal operation to prevent an MCU reset, using HAL_WWDG_Refresh() function. This operation must occur only when @@ -64,7 +72,7 @@ ============================= [..] - The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows + The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions HAL_WWDG_RegisterCallback() to register a user callback. @@ -96,7 +104,7 @@ *** WWDG HAL driver macros list *** =================================== [..] - Below the list of most used macros in WWDG HAL driver. + Below the list of available macros in WWDG HAL driver. (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.c index d5f4a17337..868fdc0fc9 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.c @@ -83,7 +83,7 @@ /* Check of parameters for configuration of ADC hierarchical scope: */ /* common to several ADC instances. */ #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ - ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ + (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ @@ -103,19 +103,19 @@ /* Check of parameters for configuration of ADC hierarchical scope: */ /* ADC instance. */ #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ - ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ + (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ ) #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ - ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ + (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ ) #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ - ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ + (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ ) @@ -123,7 +123,7 @@ /* ADC group regular */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ - ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ @@ -174,7 +174,7 @@ ) #elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ - ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ @@ -216,7 +216,7 @@ ) #elif defined(STM32G471xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ - ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ @@ -253,7 +253,7 @@ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ - ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ @@ -275,7 +275,7 @@ ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \ - ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ @@ -317,23 +317,23 @@ #endif #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ - ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ + (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ ) #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ - ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ + (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ ) #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ - ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ + (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ ) #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ - ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ + (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ @@ -352,7 +352,7 @@ ) #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ - ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ + (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ @@ -367,7 +367,7 @@ /* ADC group injected */ #if defined(STM32G474xx) || defined(STM32G484xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ - ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ @@ -417,7 +417,7 @@ ) #elif defined(STM32G473xx) || defined(STM32G483xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ - ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ @@ -457,7 +457,7 @@ ) #elif defined(STM32G471xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ - ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ @@ -493,7 +493,7 @@ ) #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ - ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ @@ -516,7 +516,7 @@ ) #elif defined(STM32G491xx) || defined(STM32G4A1xx) #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \ - ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ @@ -557,25 +557,25 @@ #endif #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ - ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ + (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ ) #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ - ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ + (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ ) #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ - ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ + (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ ) #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ - ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ + (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ ) @@ -583,7 +583,7 @@ /* Check of parameters for configuration of ADC hierarchical scope: */ /* multimode. */ #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ - ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ + (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ @@ -594,7 +594,7 @@ ) #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ - ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ + (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \ || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \ @@ -602,7 +602,7 @@ ) #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ - ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \ + (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \ || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \ @@ -617,7 +617,7 @@ ) #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ - ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ + (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ ) @@ -1128,6 +1128,7 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) /* Initialization error: ADC instance is not disabled. */ status = ERROR; } + return status; } @@ -1190,6 +1191,11 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + + /* ADC group regular continuous mode and discontinuous mode */ + /* can not be enabled simultenaeously */ + assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); } assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); @@ -1306,6 +1312,12 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); + * @note Caution if feature ADC group injected contexts queue is enabled + * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ): + * using successively several times this function will appear as + * having no effect. + * To set several features of ADC group injected, use + * function @ref LL_ADC_INJ_ConfigQueueContext(). * @param ADCx ADC instance * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure * @retval An ErrorStatus enumeration value: diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.h index beb7ba6305..ddedfbaca7 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_adc.h @@ -58,7 +58,8 @@ extern "C" { #define ADC_SQR3_REGOFFSET (0x00000200UL) #define ADC_SQR4_REGOFFSET (0x00000300UL) -#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) +#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \ + | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */ #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) @@ -95,7 +96,8 @@ extern "C" { #define ADC_JDR3_REGOFFSET (0x00000200UL) #define ADC_JDR4_REGOFFSET (0x00000300UL) -#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) +#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \ + | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */ @@ -178,7 +180,8 @@ extern "C" { #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH) #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH) #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos) -#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) +#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \ + | ADC_CHANNEL_ID_INTERNAL_CH_MASK) /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ @@ -200,24 +203,25 @@ extern "C" { /* Definition of channels ID number information to be inserted into */ /* channels literals definition. */ #define ADC_CHANNEL_0_NUMBER (0x00000000UL) -#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 ) -#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 ) -#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 ) -#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 ) -#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 ) -#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 ) -#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 ) -#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 ) -#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0) -#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 ) +#define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2) +#define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3) +#define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2) +#define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1) +#define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \ + ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4) +#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0) +#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1) /* Definition of channels ID bitfield information to be inserted into */ /* channels literals definition. */ @@ -321,7 +325,8 @@ extern "C" { #define ADC_OFR2_REGOFFSET (0x00000001UL) #define ADC_OFR3_REGOFFSET (0x00000002UL) #define ADC_OFR4_REGOFFSET (0x00000003UL) -#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) +#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \ + | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET) /* ADC registers bits positions */ @@ -347,7 +352,6 @@ extern "C" { #define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ - /** * @} */ @@ -615,7 +619,7 @@ typedef struct #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */ #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */ #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */ -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ @@ -648,7 +652,7 @@ typedef struct #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ #if defined(ADC_MULTIMODE_SUPPORT) #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} */ @@ -1515,19 +1519,19 @@ typedef struct /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tADCVREG_STUP"). */ /* Unit: us */ -#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ +#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ /* Delay for internal voltage reference stabilization time. */ /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tstart_vrefint"). */ /* Unit: us */ -#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */ /* Delay for temperature sensor stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */ /* Delay required between ADC end of calibration and ADC enable. */ /* Note: On this STM32 series, a minimum number of ADC clock cycles */ @@ -1536,7 +1540,7 @@ typedef struct /* equivalent number of CPU cycles, by taking into account */ /* ratio of CPU clock versus ADC clock prescalers. */ /* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */ /** * @} @@ -1634,10 +1638,10 @@ typedef struct * @retval Value between Min_Data=0 and Max_Data=18 */ #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \ - ? ( \ + ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \ + ( \ ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ - ) \ + ) \ : \ ( \ (uint32_t)POSITION_VAL((__CHANNEL__)) \ @@ -1698,12 +1702,12 @@ typedef struct * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) <= 9UL) \ - ? ( \ + (((__DECIMAL_NB__) <= 9UL) ? \ + ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \ (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ + ) \ : \ ( \ ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ @@ -2275,7 +2279,7 @@ typedef struct */ #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ #if defined(ADC_MULTIMODE_SUPPORT) /** @@ -2311,8 +2315,8 @@ typedef struct : \ (__ADCx__) \ ) -#endif -#endif +#endif /* ADC5 */ +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @brief Helper macro to select the ADC common instance @@ -2337,7 +2341,7 @@ typedef struct ) #else #define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON) -#endif +#endif /* ADC345_COMMON */ /** * @brief Helper macro to check if all ADC instances sharing the same * ADC common instance are disabled. @@ -2422,11 +2426,11 @@ typedef struct */ #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ __ADC_RESOLUTION_CURRENT__,\ - __ADC_RESOLUTION_TARGET__) \ - (((__DATA__) \ - << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ - >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ - ) + __ADC_RESOLUTION_TARGET__) \ +(((__DATA__) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \ +) /** * @brief Helper macro to calculate the voltage (unit: mVolt) @@ -2446,10 +2450,10 @@ typedef struct */ #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ __ADC_DATA__,\ - __ADC_RESOLUTION__) \ - ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - ) + __ADC_RESOLUTION__) \ +((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ +) /** * @brief Helper macro to calculate analog reference voltage (Vref+) @@ -2477,11 +2481,12 @@ typedef struct * @retval Analog reference voltage (unit: mV) */ #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ - / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B)) + __ADC_RESOLUTION__) \ +(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ + / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ +) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -2530,17 +2535,17 @@ typedef struct */ #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ - * (__VREFANALOG_VOLTAGE__)) \ - / TEMPSENSOR_CAL_VREFANALOG) \ - - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ - ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ - ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ - ) + TEMPSENSOR_CAL1_TEMP \ - ) + __ADC_RESOLUTION__) \ +(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ +) /** * @brief Helper macro to calculate the temperature (unit: degree Celsius) @@ -2591,18 +2596,17 @@ typedef struct __TEMPSENSOR_CALX_TEMP__,\ __VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - ((( ( \ - (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ - * 1000UL) \ - - \ - (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ - * 1000UL) \ - ) \ - ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ - ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ - ) + __ADC_RESOLUTION__) \ +(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000UL) \ + - \ + (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000UL) \ + ) \ + ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ +) /** * @} @@ -2682,7 +2686,7 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis /* Retrieve address of register DR */ return (uint32_t) &(ADCx->DR); } -#endif +#endif /* ADC_MULTIMODE_SUPPORT */ /** * @} @@ -2944,7 +2948,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t /* "SingleDiff". */ /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */ /* containing other bits reserved for other purpose. */ - return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); + return (uint32_t)(READ_BIT(ADCx->CALFACT, + (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> + ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)); } /** @@ -5716,7 +5722,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ /* containing other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); MODIFY_REG(*preg, (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), @@ -5848,7 +5854,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) { const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL)); uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); @@ -6026,7 +6032,8 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* "AWDThresholdsHighLow" and "AWDy". */ /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ /* containing other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, + ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); MODIFY_REG(*preg, AWDThresholdsHighLow, @@ -6063,12 +6070,13 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW */ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) { - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); + const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, + ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS)); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_TR1_LT1)) - >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1)) - ); + >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) + & ~(AWDThresholdsHighLow & ADC_TR1_LT1))); } /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_cordic.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_cordic.c index aad06544f2..8bf3949b1f 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_cordic.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_cordic.c @@ -25,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G4xx_LL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_cordic.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_cordic.h index 5e1126d578..ec3796f5ea 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_cordic.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_cordic.h @@ -95,15 +95,21 @@ extern "C" { #define LL_CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2)) #define LL_CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) #define LL_CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) -#define LL_CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) #define LL_CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3)) #define LL_CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0)) #define LL_CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1)) -#define LL_CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) #define LL_CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2)) -#define LL_CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) -#define LL_CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) -#define LL_CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) +#define LL_CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ + | CORDIC_CSR_PRECISION_0)) /** * @} */ @@ -127,8 +133,9 @@ extern "C" { * @{ */ #define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one - 32-bit data input (Q1.31 format), or two 16-bit - data input (Q1.15 format) packed in one 32 bits Data */ + 32-bit data input (Q1.31 format), or two + 16-bit data input (Q1.15 format) packed + in one 32 bits Data */ #define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input (Q1.31 format) */ /** @@ -139,8 +146,9 @@ extern "C" { * @{ */ #define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data output (Q1.31 format), or two 16-bit - data output (Q1.15 format) packed in one 32 bits Data */ + 32-bit data output (Q1.31 format), or two + 16-bit data output (Q1.15 format) packed + in one 32 bits Data */ #define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output (Q1.31 format) */ /** @@ -292,7 +300,8 @@ extern "C" { * @arg @ref LL_CORDIC_OUTSIZE_16BITS * @retval None */ -__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale, uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize) +__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale, + uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize) { MODIFY_REG(CORDICx->CSR, CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE | @@ -676,12 +685,12 @@ __STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint3 if (Direction == LL_CORDIC_DMA_REG_DATA_OUT) { /* return address of RDATA register */ - data_reg_addr = (uint32_t) & (CORDICx->RDATA); + data_reg_addr = (uint32_t) &(CORDICx->RDATA); } else { /* return address of WDATA register */ - data_reg_addr = (uint32_t) & (CORDICx->WDATA); + data_reg_addr = (uint32_t) &(CORDICx->WDATA); } return data_reg_addr; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.c index c7a8a92a55..73ca72800c 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.c @@ -26,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G4xx_LL_Driver * @{ @@ -176,17 +176,17 @@ #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ - || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ + || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ ) #define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__) \ ( ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \ - || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \ + || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \ ) #define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__) \ ( ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \ - || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \ + || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \ ) /** @@ -310,7 +310,7 @@ ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitType /* Note: Hardware constraint (refer to description of this function) */ /* DAC instance must be disabled. */ - if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U) + if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0UL) { /* Configuration of DAC channel: */ /* - TriggerSource */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.h index 1eaed748f6..2135c66c2a 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dac.h @@ -55,8 +55,10 @@ extern "C" { /* - channel register offset of data output register DORx */ /* - channel register offset of sample-and-hold sample time register SHSRx */ /* - channel register offset of sawtooth register STRx */ -#define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR, STMODR of channel 1 */ -#define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR, STMODR of channel 2 */ +#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers + CR, MCR, CCR, SHHR, SHRR, STMODR of channel 1 */ +#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers + CR, MCR, CCR, SHHR, SHRR, STMODR of channel 2 */ #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ @@ -67,39 +69,68 @@ extern "C" { #define DAC_SWTRB_CH2 (DAC_SWTRIGR_SWTRIGB2) /* Channel bit into register SWTRIGR of channel 2.*/ #define DAC_SWTRB_CHX_MASK (DAC_SWTRB_CH1 | DAC_SWTRB_CH2) -#define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ -#define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ -#define DAC_REG_DHR12R2_REGOFFSET 0x30000000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ -#define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ -#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000U -#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U -#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U -#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) +#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ +#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus + DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus + DHR12Rx channel 1 (shifted left of 24 bits) */ -#define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ -#define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */ +#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus + DHR12Rx channel 1 (shifted left of 28 bits) */ +#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus + DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus + DHR12Rx channel 1 (shifted left of 24 bits) */ + +#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL +#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL +#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL +#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ + | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) + +#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ + +#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus + DORx channel 2 (shifted left of 5 bits) */ #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) -#define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */ -#define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */ + +#define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */ +#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus + SHSRx channel 2 (shifted left of 6 bits) */ #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET) -#define DAC_REG_STR1_REGOFFSET 0x00000000U /* Register STRx channel 1 taken as reference */ -#define DAC_REG_STR2_REGOFFSET 0x00000080U /* Register offset of STRx channel 1 versus STRx channel 2 (shifted left of 7 bits) */ +#define DAC_REG_STR1_REGOFFSET 0x00000000UL /* Register STRx channel 1 taken as reference */ +#define DAC_REG_STR2_REGOFFSET 0x00000080UL /* Register offset of STRx channel 1 versus + STRx channel 2 (shifted left of 7 bits) */ #define DAC_REG_STRX_REGOFFSET_MASK (DAC_REG_STR1_REGOFFSET | DAC_REG_STR2_REGOFFSET) -#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ -#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */ -#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */ -#define DAC_REG_STRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of STRx registers offset when shifted to position 0 */ +#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, + DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ +#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted + to position 0 */ +#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted + to position 0 */ +#define DAC_REG_STRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of STRx registers offset when shifted + to position 0 */ -#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ -#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ -#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */ -#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6U /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */ -#define DAC_REG_STRX_REGOFFSET_BITOFFSET_POS 7U /* Position of bits register offset of STRx channel 1 or 2 versus STRx channel 1 (shifted left of 7 bits) */ +#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 28 bits) */ +#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 20 bits) */ +#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 24 bits) */ +#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx + channel 1 or 2 versus DORx channel 1 + (shifted left of 5 bits) */ +#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx + channel 1 or 2 versus SHSRx channel 1 + (shifted left of 6 bits) */ +#define DAC_REG_STRX_REGOFFSET_BITOFFSET_POS 7UL /* Position of bits register offset of STRx + channel 1 or 2 versus STRx channel 1 + (shifted left of 7 bits) */ /* DAC registers bits positions */ #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos @@ -107,7 +138,9 @@ extern "C" { #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos /* Miscellaneous data */ -#define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ +#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 + bits (voltage range determined by analog voltage + references Vref+ and Vref-, refer to reference manual) */ /** * @} @@ -126,9 +159,9 @@ extern "C" { * @param __REG__ Register basis from which the offset is applied. * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). * @retval Pointer to register address -*/ + */ #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) /** * @} @@ -146,48 +179,68 @@ extern "C" { */ typedef struct { - uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line). + uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: + internal (SW start) or from external peripheral + (timer event, external interrupt line). This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE - This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). - @note If waveform automatic generation mode is set to sawtooth, this parameter is used as sawtooth RESET trigger */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetTriggerSource(). + @note If waveform automatic generation mode is set to sawtooth, + this parameter is used as sawtooth RESET trigger */ - uint32_t TriggerSource2; /*!< Set the conversion secondary trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line). + uint32_t TriggerSource2; /*!< Set the conversion secondary trigger source for the selected DAC channel: + internal (SW start) or from external peripheral + (timer event, external interrupt line). This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE - This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource2(). - @note If waveform automatic generation mode is set to sawtooth, this parameter is used as sawtooth - step trigger */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetTriggerSource2(). + @note If waveform automatic generation mode is set to sawtooth, + this parameter is used as sawtooth step trigger */ uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE - This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetWaveAutoGeneration(). */ uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. - If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS - If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE - If waveform automatic generation mode is set to sawtooth, this parameter host the sawtooth configuration: polarity, reset data, increment data. Use __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG macro to - set this parameter value. - @note If waveform automatic generation mode is disabled, this parameter is discarded. + If waveform automatic generation mode is set to noise, this parameter + can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS + If waveform automatic generation mode is set to triangle, + this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE + If waveform automatic generation mode is set to sawtooth, this parameter + host the sawtooth configuration: polarity, reset data, increment data. + Use __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG macro to set this parameter value. + @note If waveform automatic generation mode is disabled, + this parameter is discarded. - This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude(), @ref LL_DAC_SetWaveSawtoothPolarity(), @ref LL_DAC_SetWaveSawtoothResetData() or @ref LL_DAC_SetWaveSawtoothStepData(), depending on the wave automatic generation selected. */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetWaveNoiseLFSR(), + @ref LL_DAC_SetWaveTriangleAmplitude(), + @ref LL_DAC_SetWaveSawtoothPolarity(), + @ref LL_DAC_SetWaveSawtoothResetData() + or @ref LL_DAC_SetWaveSawtoothStepData(), + depending on the wave automatic generation selected. */ uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER - This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ - + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetOutputBuffer(). */ uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION - This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetOutputConnection(). */ - uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel. - This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE + uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC + channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE - This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetOutputMode(). */ } LL_DAC_InitTypeDef; /** @@ -217,6 +270,7 @@ typedef struct #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */ #define LL_DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) /*!< DAC channel 2 flag ready */ #define LL_DAC_FLAG_DORSTAT2 (DAC_SR_DORSTAT2) /*!< DAC channel 2 flag output register */ + /** * @} */ @@ -226,7 +280,9 @@ typedef struct * @{ */ #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ + #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ + /** * @} */ @@ -241,10 +297,11 @@ typedef struct */ /** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode - * @brief High frequency interface mode defines that can be used with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode + * @brief High frequency interface mode defines that can be used + * with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode * @{ */ -#define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000U /*!< High frequency interface mode disabled */ +#define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */ #define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */ #define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */ /** @@ -254,7 +311,7 @@ typedef struct /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode * @{ */ -#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000U /*!< DAC channel in mode normal operation */ +#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */ #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */ /** * @} @@ -263,7 +320,7 @@ typedef struct /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source * @{ */ -#define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC (all) channel conversion trigger internal (SW start) */ +#define LL_DAC_TRIG_SOFTWARE 0x00000000UL /*!< DAC (all) channel conversion trigger internal (SW start) */ #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: TIM1 TRGO. */ #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC1/2/4 channel conversion trigger from external peripheral: TIM8 TRGO. Refer to device datasheet for DACx instance availability. */ #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM7 TRGO. */ @@ -296,7 +353,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode * @{ */ -#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ +#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */ #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ #define LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH (DAC_CR_WAVE1_1|DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated sawtooth waveform. */ @@ -307,7 +364,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits * @{ */ -#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ +#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ @@ -326,7 +383,7 @@ typedef struct /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude * @{ */ -#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ +#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ @@ -345,7 +402,7 @@ typedef struct /** @defgroup DAC_LL_EC_SAWTOOTH_POLARITY_MODE DAC wave generation - Sawtooth polarity mode * @{ */ -#define LL_DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000U /*!< Sawtooth wave generation, polarity is decrement */ +#define LL_DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL /*!< Sawtooth wave generation, polarity is decrement */ #define LL_DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */ /** * @} @@ -354,7 +411,7 @@ typedef struct /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode * @{ */ -#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000U /*!< The selected DAC channel output is on mode normal. */ +#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */ #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */ /** * @} @@ -363,7 +420,7 @@ typedef struct /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer * @{ */ -#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ +#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ /** * @} @@ -372,7 +429,7 @@ typedef struct /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection * @{ */ -#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /*!< The selected DAC channel output is connected to external pin */ +#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */ #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */ /** * @} @@ -381,7 +438,7 @@ typedef struct /** @defgroup DAC_LL_EC_SIGNED_FORMAT DAC channel signed format * @{ */ -#define LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000U /*!< The selected DAC channel data format is not signed */ +#define LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000UL /*!< The selected DAC channel data format is not signed */ #define LL_DAC_SIGNED_FORMAT_ENABLE (DAC_MCR_SINFORMAT1) /*!< The selected DAC channel data format is signed */ /** * @} @@ -390,8 +447,8 @@ typedef struct /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution * @{ */ -#define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ -#define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ +#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */ +#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */ /** * @} */ @@ -429,7 +486,7 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tWAKEUP"). */ /* Unit: us */ -#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ +#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ /* Delay for DAC channel voltage settling time. */ /* Note: DAC channel startup time depends on board application environment: */ @@ -442,7 +499,7 @@ typedef struct /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSETTLING"). */ /* Unit: us */ -#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3U /*!< Delay for DAC channel voltage settling time */ +#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */ /** * @} @@ -521,22 +578,8 @@ typedef struct * (1) On this STM32 series, parameter not available on all instances. * Refer to device datasheet for channels availability. */ -#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) == 1U) \ - ? ( \ - LL_DAC_CHANNEL_1 \ - ) \ - : \ - (((__DECIMAL_NB__) == 2U) \ - ? ( \ - LL_DAC_CHANNEL_2 \ - ) \ - : \ - ( \ - 0U \ - ) \ - ) \ - ) +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\ + (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL))) /** * @brief Helper macro to define the DAC conversion data full-scale digital @@ -550,7 +593,7 @@ typedef struct * @retval ADC conversion data equivalent voltage value (unit: mVolt) */ #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) + ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL)) /** * @brief Helper macro to calculate the DAC conversion data (unit: digital @@ -561,7 +604,7 @@ typedef struct * @ref LL_DAC_ConvertData12RightAligned(). * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel * (unit: mVolt). @@ -573,9 +616,9 @@ typedef struct #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ __DAC_VOLTAGE__,\ __DAC_RESOLUTION__) \ - ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - / (__VREFANALOG_VOLTAGE__) \ - ) +((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ +) /** * @brief Helper macro to format sawtooth wave generation configuration @@ -589,10 +632,10 @@ typedef struct #define __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG(__POLARITY__,\ __RESET_DATA__,\ __STEP_DATA__) \ - ( (((__STEP_DATA__) << DAC_STR1_STINCDATA1_Pos) & DAC_STR1_STINCDATA1_Msk) \ - | ((__POLARITY__) & DAC_STR1_STDIR1_Msk) \ - | (((__RESET_DATA__) << DAC_STR1_STRSTDATA1_Pos) & DAC_STR1_STRSTDATA1_Msk) \ - ) +( (((__STEP_DATA__) << DAC_STR1_STINCDATA1_Pos) & DAC_STR1_STINCDATA1_Msk) \ + | ((__POLARITY__) & DAC_STR1_STDIR1_Msk) \ + | (((__RESET_DATA__) << DAC_STR1_STRSTDATA1_Pos) & DAC_STR1_STRSTDATA1_Msk) \ +) /** * @} @@ -607,7 +650,7 @@ typedef struct /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions * @{ */ -/** @defgroup DAC_LL_EF_Configuration Configuration of DAC instance +/** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance * @{ */ /** @@ -1633,11 +1676,10 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); - MODIFY_REG(*preg, - DAC_SHSR1_TSAMPLE1, - SampleTime); + MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime); } /** @@ -1656,7 +1698,8 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32 */ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1); } @@ -1942,7 +1985,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(DAC_TypeDef *DACx, ui * LL_DMA_ConfigAddresses(DMA1, * LL_DMA_CHANNEL_1, * (uint32_t)&< array or variable >, - * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), + * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, + * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n @@ -1967,8 +2011,8 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C { /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ /* DAC channel selected. */ - return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, - ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); + return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); } /** * @} @@ -2211,11 +2255,10 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion2(DAC_TypeDef *DACx, uint32_t DAC_Ch */ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); - MODIFY_REG(*preg, - DAC_DHR12R1_DACC1DHR, - Data); + MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); } /** @@ -2236,11 +2279,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_ */ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); - MODIFY_REG(*preg, - DAC_DHR12L1_DACC1DHR, - Data); + MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); } /** @@ -2261,11 +2303,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); - MODIFY_REG(*preg, - DAC_DHR8R1_DACC1DHR, - Data); + MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); } @@ -2349,7 +2390,8 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint */ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); } @@ -2396,7 +2438,6 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); } - /** * @brief Get DAC busy writing sample time flag for DAC channel 2 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2 @@ -2456,7 +2497,6 @@ __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(DAC_TypeDef *DACx) return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL); } - /** * @brief Get DAC underrun flag for DAC channel 1 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dma.h index 0a4e3b3ec5..441a10dfdb 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dma.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_dma.h @@ -1933,6 +1933,10 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx) /** * @brief Clear Channel 1 global interrupt flag. + * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, + LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 * @param DMAx DMAx Instance * @retval None @@ -1944,6 +1948,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) /** * @brief Clear Channel 2 global interrupt flag. + * @note Do not Clear Channel 2 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, + LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 * @param DMAx DMAx Instance * @retval None @@ -1955,6 +1963,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) /** * @brief Clear Channel 3 global interrupt flag. + * @note Do not Clear Channel 3 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, + LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 * @param DMAx DMAx Instance * @retval None @@ -1966,6 +1978,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) /** * @brief Clear Channel 4 global interrupt flag. + * @note Do not Clear Channel 4 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, + LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 * @param DMAx DMAx Instance * @retval None @@ -1977,6 +1993,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) /** * @brief Clear Channel 5 global interrupt flag. + * @note Do not Clear Channel 5 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, + LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 * @param DMAx DMAx Instance * @retval None @@ -1988,6 +2008,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) /** * @brief Clear Channel 6 global interrupt flag. + * @note Do not Clear Channel 6 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, + LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 * @param DMAx DMAx Instance * @retval None @@ -2000,6 +2024,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) #if defined (DMA1_Channel7) /** * @brief Clear Channel 7 global interrupt flag. + * @note Do not Clear Channel 7 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, + LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 * @param DMAx DMAx Instance * @retval None @@ -2013,6 +2041,10 @@ __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) #if defined (DMA1_Channel8) /** * @brief Clear Channel 8 global interrupt flag. + * @note Do not Clear Channel 8 global interrupt flag when the channel in ON. + Instead clear specific flags transfer complete, half transfer & transfer + error flag with LL_DMA_ClearFlag_TC8, LL_DMA_ClearFlag_HT8, + LL_DMA_ClearFlag_TE8. bug id 2.3.1 in Product Errata Sheet. * @rmtoll IFCR CGIF8 LL_DMA_ClearFlag_GI8 * @param DMAx DMAx Instance * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.c index 7491be4533..da200b7bab 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.c @@ -24,7 +24,7 @@ #ifdef USE_FULL_ASSERT #include "stm32_assert.h" #else -#define assert_param(expr) ((void)0) +#define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ /** @addtogroup STM32G4xx_LL_Driver diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.h index 5d860c8fdb..d67834eea6 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmac.h @@ -201,7 +201,8 @@ __STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer * @brief Return X1 buffer size. * @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_GetX1BufferSize * @param FMACx FMAC instance - * @retval uint8_t Number of 16-bit words allocated to the input buffer (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF). + * @retval uint8_t Number of 16-bit words allocated to the input buffer + * (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx) { @@ -225,7 +226,8 @@ __STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base) * @brief Return X1 base. * @rmtoll X1BUFCFG X1_BASE LL_FMAC_GetX1Base * @param FMACx FMAC instance - * @retval uint8_t Base address of the input buffer (X1) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF). + * @retval uint8_t Base address of the input buffer (X1) within the internal memory + * (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx) { @@ -249,7 +251,8 @@ __STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t Buffer * @brief Return X2 buffer size. * @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_GetX2BufferSize * @param FMACx FMAC instance - * @retval uint8_t Number of 16-bit words allocated to the coefficient buffer (value between Min_Data=0x01 and Max_Data=0xFF). + * @retval uint8_t Number of 16-bit words allocated to the coefficient buffer + * (value between Min_Data=0x01 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx) { @@ -273,7 +276,8 @@ __STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base) * @brief Return X2 base. * @rmtoll X2BUFCFG X2_BASE LL_FMAC_GetX2Base * @param FMACx FMAC instance - * @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF). + * @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory + * (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx) { @@ -328,7 +332,8 @@ __STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferS * @brief Return Y buffer size. * @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_GetYBufferSize * @param FMACx FMAC instance - * @retval uint8_t Number of 16-bit words allocated to the output buffer (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF). + * @retval uint8_t Number of 16-bit words allocated to the output buffer + * (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx) { @@ -352,7 +357,8 @@ __STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base) * @brief Return Y base. * @rmtoll YBUFCFG Y_BASE LL_FMAC_GetYBase * @param FMACx FMAC instance - * @retval uint8_t Base address of the output buffer (Y) within the internal memory (value between Min_Data=0x00 and Max_Data=0xFF). + * @retval uint8_t Base address of the output buffer (Y) within the internal memory + * (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx) { @@ -490,7 +496,8 @@ __STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param) * @brief Return input parameter P. * @rmtoll PARAM P LL_FMAC_GetParamP * @param FMACx FMAC instance - * @retval uint8_t Parameter P (vector length, number of filter taps, etc.) (value between Min_Data=0x00 and Max_Data=0xFF). + * @retval uint8_t Parameter P (vector length, number of filter taps, etc.) + * (value between Min_Data=0x00 and Max_Data=0xFF). */ __STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx) { @@ -938,7 +945,8 @@ __STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx) __STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize) { MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM | FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE, - Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)); + Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) | + (((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)); } /** @@ -955,7 +963,8 @@ __STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, u __STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize) { MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE, - (((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)); + (((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) | + (((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)); } /** @@ -978,7 +987,8 @@ __STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t __STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize) { MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM | FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE, - Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) | (((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)); + Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) | + (((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos)); } /** @@ -1010,7 +1020,8 @@ __STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint uint8_t ParamQ, uint8_t ParamR) { MODIFY_REG(FMACx->PARAM, FMAC_PARAM_START | FMAC_PARAM_FUNC | FMAC_PARAM_P | FMAC_PARAM_Q | FMAC_PARAM_R, - (((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) | (((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos)); + (((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) | + (((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmc.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmc.c index 12439fe363..ac6521d81d 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmc.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmc.c @@ -16,7 +16,7 @@ ============================================================================== [..] The Flexible memory controller (FMC) includes following memory controllers: (+) The NOR/PSRAM memory controller - (+) The NAND memory controller + (+) The NAND memory controller [..] The FMC functional block makes the interface with synchronous and asynchronous static memories. Its main purposes are: @@ -58,6 +58,7 @@ /** @addtogroup STM32G4xx_HAL_Driver * @{ */ +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules @@ -86,9 +87,15 @@ /* --- BWTR Register ---*/ /* BWTR register clear mask */ +#if defined(FMC_BWTRx_BUSTURN) #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD)) +#else +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ + FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD |\ + FMC_BWTRx_DATAHLD)) +#endif /* FMC_BWTRx_BUSTURN */ #endif /* FMC_BANK1 */ #if defined(FMC_BANK3) @@ -173,9 +180,12 @@ * @param Init Pointer to NORSRAM Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init) +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; + uint32_t btcr_reg; + uint32_t mask; /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); @@ -210,40 +220,44 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; } - MODIFY_REG(Device->BTCR[Init->NSBank], - (FMC_BCRx_MBKEN | - FMC_BCRx_MUXEN | - FMC_BCRx_MTYP | - FMC_BCRx_MWID | - FMC_BCRx_FACCEN | - FMC_BCRx_BURSTEN | - FMC_BCRx_WAITPOL | - FMC_BCRx_WAITCFG | - FMC_BCRx_WREN | - FMC_BCRx_WAITEN | - FMC_BCRx_EXTMOD | - FMC_BCRx_ASYNCWAIT | - FMC_BCRx_CBURSTRW | - FMC_BCR1_CCLKEN | - FMC_BCR1_WFDIS | - FMC_BCRx_NBLSET | - FMC_BCRx_CPSIZE), - (flashaccess | - Init->DataAddressMux | - Init->MemoryType | - Init->MemoryDataWidth | - Init->BurstAccessMode | - Init->WaitSignalPolarity | - Init->WaitSignalActive | - Init->WriteOperation | - Init->WaitSignal | - Init->ExtendedMode | - Init->AsynchronousWait | - Init->WriteBurst | - Init->ContinuousClock | - Init->WriteFifo | - Init->NBLSetupTime | - Init->PageSize)); + btcr_reg = (flashaccess | \ + Init->DataAddressMux | \ + Init->MemoryType | \ + Init->MemoryDataWidth | \ + Init->BurstAccessMode | \ + Init->WaitSignalPolarity | \ + Init->WaitSignalActive | \ + Init->WriteOperation | \ + Init->WaitSignal | \ + Init->ExtendedMode | \ + Init->AsynchronousWait | \ + Init->WriteBurst); + + btcr_reg |= Init->ContinuousClock; + btcr_reg |= Init->WriteFifo; + btcr_reg |= Init->NBLSetupTime; + btcr_reg |= Init->PageSize; + + mask = (FMC_BCRx_MBKEN | + FMC_BCRx_MUXEN | + FMC_BCRx_MTYP | + FMC_BCRx_MWID | + FMC_BCRx_FACCEN | + FMC_BCRx_BURSTEN | + FMC_BCRx_WAITPOL | + FMC_BCRx_WAITCFG | + FMC_BCRx_WREN | + FMC_BCRx_WAITEN | + FMC_BCRx_EXTMOD | + FMC_BCRx_ASYNCWAIT | + FMC_BCRx_CBURSTRW); + + mask |= FMC_BCR1_CCLKEN; + mask |= FMC_BCR1_WFDIS; + mask |= FMC_BCRx_NBLSET; + mask |= FMC_BCRx_CPSIZE; + + MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) @@ -258,7 +272,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini } /* Check PSRAM chip select counter state */ - if(Init->MaxChipSelectPulse == ENABLE) + if (Init->MaxChipSelectPulse == ENABLE) { /* Check the parameters */ assert_param(IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(Init->MaxChipSelectPulseTime)); @@ -281,11 +295,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); break; - case FMC_NORSRAM_BANK4 : - SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); - break; - default : + SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); break; } } @@ -293,7 +304,6 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini return HAL_OK; } - /** * @brief DeInitialize the FMC_NORSRAM peripheral * @param Device Pointer to NORSRAM device instance @@ -301,7 +311,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); @@ -327,32 +338,28 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EX ExDevice->BWTR[Bank] = 0x0FFFFFFFU; /* De-initialize PSRAM chip select counter */ - switch (Bank) - { - case FMC_NORSRAM_BANK1 : - CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); - break; + switch (Bank) + { + case FMC_NORSRAM_BANK1 : + CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); + break; - case FMC_NORSRAM_BANK2 : - CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); - break; + case FMC_NORSRAM_BANK2 : + CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); + break; - case FMC_NORSRAM_BANK3 : - CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); - break; + case FMC_NORSRAM_BANK3 : + CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); + break; - case FMC_NORSRAM_BANK4 : - CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); - break; - - default : - break; - } + default : + CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); + break; + } return HAL_OK; } - /** * @brief Initialize the FMC_NORSRAM Timing according to the specified * parameters in the FMC_NORSRAM_TimingTypeDef @@ -361,7 +368,8 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EX * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { uint32_t tmpr; @@ -379,18 +387,18 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR /* Set FMC_NORSRAM device timing parameters */ MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | - ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) | - ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | - (Timing->AccessMode))); + ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | + ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) | + ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | + (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | + (Timing->AccessMode))); /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos)); + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); } @@ -410,7 +418,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR * @arg FMC_EXTENDED_MODE_ENABLE * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) { /* Check the parameters */ assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); @@ -424,7 +434,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); +#if defined(FMC_BWTRx_BUSTURN) assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); +#endif /* FMC_BWTRx_BUSTURN */ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); @@ -433,8 +445,12 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | ((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) | +#if defined(FMC_BWTRx_BUSTURN) Timing->AccessMode | ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); +#else + Timing->AccessMode)); +#endif /* FMC_BWTRx_BUSTURN */ } else { @@ -448,8 +464,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef */ /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### FMC_NORSRAM Control functions ##### @@ -535,8 +551,8 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device */ /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim ============================================================================== ##### Initialization and de_initialization functions ##### @@ -590,7 +606,8 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -600,6 +617,9 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); assert_param(IS_FMC_NAND_BANK(Bank)); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + /* NAND bank 3 registers configuration */ MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | @@ -617,7 +637,8 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -627,6 +648,9 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); assert_param(IS_FMC_NAND_BANK(Bank)); + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + /* NAND bank 3 registers configuration */ MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | @@ -652,6 +676,9 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) __FMC_NAND_DISABLE(Device, Bank); /* De-initialize the NAND Bank */ + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + /* Set the FMC_NAND_BANK3 registers to their reset values */ WRITE_REG(Device->PCR, 0x00000018U); WRITE_REG(Device->SR, 0x00000040U); @@ -694,6 +721,9 @@ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) assert_param(IS_FMC_NAND_BANK(Bank)); /* Enable ECC feature */ + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + SET_BIT(Device->PCR, FMC_PCR_ECCEN); return HAL_OK; @@ -713,6 +743,9 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) assert_param(IS_FMC_NAND_BANK(Bank)); /* Disable ECC feature */ + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); return HAL_OK; @@ -726,7 +759,8 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout) { uint32_t tickstart; @@ -750,6 +784,9 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui } } + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + /* Get the ECCR register value */ *ECCval = (uint32_t)Device->ECCR; @@ -771,6 +808,10 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui * @} */ +#endif /* HAL_NOR_MODULE_ENABLED */ +/** + * @} + */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmc.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmc.h index 8d974263d3..7084348957 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmc.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_fmc.h @@ -157,76 +157,75 @@ extern "C" { typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Write_FIFO */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ + This parameter can be a value of @ref FMC_Page_Size */ uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number - This parameter can be a value of @ref FMC_Byte_Lane */ + This parameter can be a value of @ref FMC_Byte_Lane */ - FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this NSBank - for PSRAM refresh. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this + NSBank for PSRAM refresh. + This parameter can be set to ENABLE or DISABLE */ - uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for synchronous - accesses and in HCLK cycles for asynchronous accesses, + uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for + synchronous accesses and in HCLK cycles for asynchronous accesses, valid only if MaxChipSelectPulse is ENABLE. This parameter can be a value between Min_Data = 1 and Max_Data = 65535. - @note: This parameter is common to all NSBank. */ - -}FMC_NORSRAM_InitTypeDef; + @note: This parameter is common to all NSBank. */ +} FMC_NORSRAM_InitTypeDef; /** * @brief FMC NORSRAM Timing parameters structure definition @@ -236,45 +235,46 @@ typedef struct uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between Min_Data = 1 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between Min_Data = 1 and Max_Data = 255. @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed - NOR Flash memories. */ + NOR Flash memories. */ uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the data hold time. This parameter can be a value between Min_Data = 0 and Max_Data = 3. - @note This parameter is used for used in asynchronous accesses. */ + @note This parameter is used for used in asynchronous accesses. */ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is only used for multiplexed NOR Flash memories. */ + @note This parameter is only used for multiplexed NOR Flash memories. */ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of - HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. + HCLK cycles. This parameter can be a value between Min_Data = 2 and + Max_Data = 16. @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM - accesses. */ + accesses. */ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories - with synchronous burst mode enable */ + - It may assume a value between Min_Data = 2 and Max_Data = 17 + in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ -}FMC_NORSRAM_TimingTypeDef; + This parameter can be a value of @ref FMC_Access_Mode */ +} FMC_NORSRAM_TimingTypeDef; #endif /* FMC_BANK1 */ #if defined(FMC_BANK3) @@ -284,19 +284,19 @@ typedef struct typedef struct { uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. - This parameter can be a value of @ref FMC_NAND_Bank */ + This parameter can be a value of @ref FMC_NAND_Bank */ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. - This parameter can be any value of @ref FMC_Wait_feature */ + This parameter can be any value of @ref FMC_Wait_feature */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FMC_NAND_Data_Width */ + This parameter can be any value of @ref FMC_NAND_Data_Width */ uint32_t EccComputation; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FMC_ECC */ + This parameter can be any value of @ref FMC_ECC */ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FMC_ECC_Page_Size */ + This parameter can be any value of @ref FMC_ECC_Page_Size */ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. @@ -305,8 +305,10 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ -}FMC_NAND_InitTypeDef; +} FMC_NAND_InitTypeDef; +#endif +#if defined(FMC_BANK3) /** * @brief FMC NAND Timing parameters structure definition */ @@ -336,9 +338,10 @@ typedef struct write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ -}FMC_NAND_PCC_TimingTypeDef; +} FMC_NAND_PCC_TimingTypeDef; #endif /* FMC_BANK3 */ + /** * @} */ @@ -356,10 +359,10 @@ typedef struct /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank * @{ */ -#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U) -#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U) -#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U) -#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U) +#define FMC_NORSRAM_BANK1 (0x00000000U) +#define FMC_NORSRAM_BANK2 (0x00000002U) +#define FMC_NORSRAM_BANK3 (0x00000004U) +#define FMC_NORSRAM_BANK4 (0x00000006U) /** * @} */ @@ -367,8 +370,8 @@ typedef struct /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing * @{ */ -#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U) -#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U) +#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) /** * @} */ @@ -376,9 +379,9 @@ typedef struct /** @defgroup FMC_Memory_Type FMC Memory Type * @{ */ -#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U) -#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U) -#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U) +#define FMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FMC_MEMORY_TYPE_NOR (0x00000008U) /** * @} */ @@ -386,9 +389,9 @@ typedef struct /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width * @{ */ -#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) -#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) -#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) /** * @} */ @@ -396,8 +399,8 @@ typedef struct /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access * @{ */ -#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U) -#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U) +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) /** * @} */ @@ -405,8 +408,8 @@ typedef struct /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode * @{ */ -#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U) -#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U) +#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) /** * @} */ @@ -414,8 +417,8 @@ typedef struct /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity * @{ */ -#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U) -#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U) +#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) /** * @} */ @@ -423,8 +426,8 @@ typedef struct /** @defgroup FMC_Wait_Timing FMC Wait Timing * @{ */ -#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U) -#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U) +#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) +#define FMC_WAIT_TIMING_DURING_WS (0x00000800U) /** * @} */ @@ -432,8 +435,8 @@ typedef struct /** @defgroup FMC_Write_Operation FMC Write Operation * @{ */ -#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U) -#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U) +#define FMC_WRITE_OPERATION_DISABLE (0x00000000U) +#define FMC_WRITE_OPERATION_ENABLE (0x00001000U) /** * @} */ @@ -441,8 +444,8 @@ typedef struct /** @defgroup FMC_Wait_Signal FMC Wait Signal * @{ */ -#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U) -#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U) +#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) /** * @} */ @@ -450,8 +453,8 @@ typedef struct /** @defgroup FMC_Extended_Mode FMC Extended Mode * @{ */ -#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U) -#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U) +#define FMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FMC_EXTENDED_MODE_ENABLE (0x00004000U) /** * @} */ @@ -459,8 +462,8 @@ typedef struct /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait * @{ */ -#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U) -#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U) +#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) /** * @} */ @@ -468,11 +471,12 @@ typedef struct /** @defgroup FMC_Page_Size FMC Page Size * @{ */ -#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U) -#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) -#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) -#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1)) -#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2) +#define FMC_PAGE_SIZE_NONE (0x00000000U) +#define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 +#define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 +#define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ + | FMC_BCRx_CPSIZE_1) +#define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 /** * @} */ @@ -480,8 +484,8 @@ typedef struct /** @defgroup FMC_Write_Burst FMC Write Burst * @{ */ -#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U) -#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U) +#define FMC_WRITE_BURST_DISABLE (0x00000000U) +#define FMC_WRITE_BURST_ENABLE (0x00080000U) /** * @} */ @@ -489,8 +493,8 @@ typedef struct /** @defgroup FMC_Continous_Clock FMC Continuous Clock * @{ */ -#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U) -#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) /** * @} */ @@ -498,8 +502,8 @@ typedef struct /** @defgroup FMC_Write_FIFO FMC Write FIFO * @{ */ -#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) -#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U) +#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS +#define FMC_WRITE_FIFO_ENABLE (0x00000000U) /** * @} */ @@ -507,10 +511,10 @@ typedef struct /** @defgroup FMC_Access_Mode FMC Access Mode * @{ */ -#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U) -#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U) -#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U) -#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U) +#define FMC_ACCESS_MODE_A (0x00000000U) +#define FMC_ACCESS_MODE_B (0x10000000U) +#define FMC_ACCESS_MODE_C (0x20000000U) +#define FMC_ACCESS_MODE_D (0x30000000U) /** * @} */ @@ -518,10 +522,10 @@ typedef struct /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup * @{ */ -#define FMC_NBL_SETUPTIME_0 ((uint32_t)0x00000000U) -#define FMC_NBL_SETUPTIME_1 ((uint32_t)0x00400000U) -#define FMC_NBL_SETUPTIME_2 ((uint32_t)0x00800000U) -#define FMC_NBL_SETUPTIME_3 ((uint32_t)0x00C00000U) +#define FMC_NBL_SETUPTIME_0 (0x00000000U) +#define FMC_NBL_SETUPTIME_1 (0x00400000U) +#define FMC_NBL_SETUPTIME_2 (0x00800000U) +#define FMC_NBL_SETUPTIME_3 (0x00C00000U) /** * @} */ @@ -539,7 +543,7 @@ typedef struct /** @defgroup FMC_NAND_Bank FMC NAND Bank * @{ */ -#define FMC_NAND_BANK3 ((uint32_t)0x00000100U) +#define FMC_NAND_BANK3 (0x00000100U) /** * @} */ @@ -547,8 +551,8 @@ typedef struct /** @defgroup FMC_Wait_feature FMC Wait feature * @{ */ -#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U) -#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U) +#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) +#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) /** * @} */ @@ -556,7 +560,7 @@ typedef struct /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type * @{ */ -#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U) +#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) /** * @} */ @@ -564,8 +568,8 @@ typedef struct /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width * @{ */ -#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U) -#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U) +#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) /** * @} */ @@ -573,8 +577,8 @@ typedef struct /** @defgroup FMC_ECC FMC ECC * @{ */ -#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U) -#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U) +#define FMC_NAND_ECC_DISABLE (0x00000000U) +#define FMC_NAND_ECC_ENABLE (0x00000040U) /** * @} */ @@ -582,12 +586,12 @@ typedef struct /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size * @{ */ -#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U) -#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U) -#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U) -#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U) -#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U) -#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U) +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) +#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) +#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) +#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) +#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) +#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) /** * @} */ @@ -602,9 +606,9 @@ typedef struct * @{ */ #if defined(FMC_BANK3) -#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U) -#define FMC_IT_LEVEL ((uint32_t)0x00000010U) -#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U) +#define FMC_IT_RISING_EDGE (0x00000008U) +#define FMC_IT_LEVEL (0x00000010U) +#define FMC_IT_FALLING_EDGE (0x00000020U) #endif /* FMC_BANK3 */ /** * @} @@ -614,14 +618,15 @@ typedef struct * @{ */ #if defined(FMC_BANK3) -#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U) -#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U) -#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U) -#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U) +#define FMC_FLAG_RISING_EDGE (0x00000001U) +#define FMC_FLAG_LEVEL (0x00000002U) +#define FMC_FLAG_FALLING_EDGE (0x00000004U) +#define FMC_FLAG_FEMPT (0x00000040U) #endif /* FMC_BANK3 */ /** * @} */ + /** * @} */ @@ -646,7 +651,8 @@ typedef struct * @param __BANK__ FMC_NORSRAM Bank * @retval None */ -#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN) +#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + |= FMC_BCRx_MBKEN) /** * @brief Disable the NORSRAM device access. @@ -654,7 +660,8 @@ typedef struct * @param __BANK__ FMC_NORSRAM Bank * @retval None */ -#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN) +#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + &= ~FMC_BCRx_MBKEN) /** * @} @@ -663,9 +670,9 @@ typedef struct #if defined(FMC_BANK3) /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros - * @brief macros to handle NAND device enable/disable - * @{ - */ + * @brief macros to handle NAND device enable/disable + * @{ + */ /** * @brief Enable the NAND device access. @@ -685,7 +692,9 @@ typedef struct /** * @} */ +#endif +#if defined(FMC_BANK3) /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt * @brief macros to handle NAND interrupts * @{ @@ -747,6 +756,7 @@ typedef struct */ #endif /* FMC_BANK3 */ + /** * @} */ @@ -767,10 +777,15 @@ typedef struct /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode); +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); /** * @} */ @@ -796,8 +811,10 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic * @{ */ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -808,7 +825,8 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_hrtim.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_hrtim.h index 2b974b2f19..d2437da0f8 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_hrtim.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_hrtim.h @@ -9644,10 +9644,10 @@ __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1))); __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2))); - uint64_t cfg = ((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */ - (((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */ - uint64_t mask = ((uint64_t)(HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe bit 0 */ - ((uint64_t)(HRTIM_FLT_SRC_1_MASK) << 32U) ; /* this for SouRCe bit 1 */ + uint64_t cfg = ( (uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 bit */ + (((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */ + uint64_t mask = ( (uint64_t)(HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe bit 0 */ + (((uint64_t)(HRTIM_FLTINR2_FLT1SRC_1) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe bit 1 */ MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg)); MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U)); diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_iwdg.h index 40f4ab8934..9a1b24ae64 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_iwdg.h @@ -304,8 +304,8 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) /** * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not * @rmtoll SR PVU LL_IWDG_IsReady\n - * SR WVU LL_IWDG_IsReady\n - * SR RVU LL_IWDG_IsReady + * SR RVU LL_IWDG_IsReady\n + * SR WVU LL_IWDG_IsReady * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ @@ -318,7 +318,6 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) * @} */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.c index c7de8d367c..5e2f14184b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.c @@ -48,22 +48,22 @@ * @{ */ #define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ - || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) + || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) #define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) #define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) + || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) #define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) + || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) /** * @} */ @@ -242,8 +242,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } - while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_CMPOK(LPTIMx); } diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.h index 1b0198add0..feb22f4c11 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lptim.h @@ -100,9 +100,9 @@ typedef struct * @{ */ #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */ +#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */ -#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ @@ -114,13 +114,13 @@ typedef struct * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions * @{ */ -#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */ -#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */ -#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */ -#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */ -#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */ -#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */ -#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */ +#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */ +#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */ +#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */ +#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */ +#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */ +#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */ +#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */ /** * @} */ @@ -1367,7 +1367,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) /** * @brief Enable autoreload register write completed interrupt (ARROKIE). - * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1378,7 +1378,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx) /** * @brief Disable autoreload register write completed interrupt (ARROKIE). - * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1389,7 +1389,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. - * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ @@ -1400,7 +1400,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) /** * @brief Enable direction change to up interrupt (UPIE). - * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP + * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1411,7 +1411,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx) /** * @brief Disable direction change to up interrupt (UPIE). - * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP + * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1422,7 +1422,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. - * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP + * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ @@ -1433,7 +1433,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) /** * @brief Enable direction change to down interrupt (DOWNIE). - * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1444,7 +1444,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx) /** * @brief Disable direction change to down interrupt (DOWNIE). - * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1455,7 +1455,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. - * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.c index 670fa9b8ab..7224eb1cfd 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.c @@ -274,7 +274,7 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) * @} */ -#endif /* defined (LPUART1) */ +#endif /* LPUART1 */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.h index 5ffe06bc9e..7abf32f91d 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_lpuart.h @@ -154,16 +154,16 @@ typedef struct * @brief Flags defines which can be used with LL_LPUART_WriteReg function * @{ */ -#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ -#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */ -#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ -#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ -#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ -#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ -#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ -#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ -#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ +#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ /** * @} */ @@ -172,27 +172,27 @@ typedef struct * @brief Flags defines which can be used with LL_LPUART_ReadReg function * @{ */ -#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ -#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ -#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ -#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ -#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ -#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ -#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ -#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ -#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ -#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ -#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ -#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ -#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ -#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ -#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ -#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ -#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ -#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ -#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ -#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ -#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ /** * @} */ @@ -201,19 +201,21 @@ typedef struct * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions * @{ */ -#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ -#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ -#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ -#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ -#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ -#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ -#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ -#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ -#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ -#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ -#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ -#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ -#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty + interrupt enable */ +#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO + not full interrupt enable */ +#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ /** * @} */ @@ -234,10 +236,10 @@ typedef struct /** @defgroup LPUART_LL_EC_DIRECTION Direction * @{ */ -#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ -#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ -#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ -#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ /** * @} */ @@ -245,9 +247,9 @@ typedef struct /** @defgroup LPUART_LL_EC_PARITY Parity Control * @{ */ -#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ -#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ -#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ /** * @} */ @@ -255,8 +257,8 @@ typedef struct /** @defgroup LPUART_LL_EC_WAKEUP Wakeup * @{ */ -#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ -#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ +#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ +#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ /** * @} */ @@ -264,9 +266,9 @@ typedef struct /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth * @{ */ -#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ -#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ -#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ /** * @} */ @@ -274,18 +276,27 @@ typedef struct /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler * @{ */ -#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ -#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ -#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ -#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ -#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ -#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ -#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ -#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ -#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ -#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ -#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ -#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ /** * @} */ @@ -293,8 +304,8 @@ typedef struct /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits * @{ */ -#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ -#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ /** * @} */ @@ -302,8 +313,8 @@ typedef struct /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap * @{ */ -#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ -#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ /** * @} */ @@ -311,8 +322,8 @@ typedef struct /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion * @{ */ -#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ -#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ /** * @} */ @@ -320,8 +331,8 @@ typedef struct /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion * @{ */ -#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ -#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ /** * @} */ @@ -329,8 +340,11 @@ typedef struct /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion * @{ */ -#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ -#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received + in positive/direct logic. (1=H, 0=L) */ +#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received + in negative/inverse logic. (1=L, 0=H). + The parity bit is also inverted. */ /** * @} */ @@ -338,8 +352,10 @@ typedef struct /** @defgroup LPUART_LL_EC_BITORDER Bit Order * @{ */ -#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ -#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, + following the start bit */ +#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, + following the start bit */ /** * @} */ @@ -347,8 +363,8 @@ typedef struct /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection * @{ */ -#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ -#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ /** * @} */ @@ -356,10 +372,12 @@ typedef struct /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control * @{ */ -#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ -#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ -#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ -#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested + when there is space in the receive buffer */ +#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted + when the nCTS input is asserted (tied to 0)*/ +#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ /** * @} */ @@ -367,9 +385,9 @@ typedef struct /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation * @{ */ -#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ -#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ -#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ /** * @} */ @@ -377,8 +395,8 @@ typedef struct /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity * @{ */ -#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ -#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ /** * @} */ @@ -386,8 +404,8 @@ typedef struct /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_opamp.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_opamp.h index dafdfa2883..88bd1658e4 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_opamp.h @@ -297,8 +297,11 @@ typedef struct /** @defgroup OPAMP_LL_EC_POWER_MODE OPAMP PowerMode * @{ */ -#define LL_OPAMP_POWERMODE_NORMAL (0x00000000UL) /*!< OPAMP output in normal mode */ +#define LL_OPAMP_POWERMODE_NORMALSPEED (0x00000000UL) /*!< OPAMP output in normal mode */ #define LL_OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_HIGHSPEEDEN /*!< OPAMP output in highspeed mode */ + +#define LL_OPAMP_POWERMODE_NORMAL LL_OPAMP_POWERMODE_NORMALSPEED /*!< OPAMP power mode normal - Old Naming for compatibility */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_rcc.c index 57f442d812..b83b468f1d 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_rcc.c @@ -96,13 +96,13 @@ /** @defgroup RCC_LL_Private_Functions RCC Private functions * @{ */ -uint32_t RCC_GetSystemClockFreq(void); -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); -uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); -uint32_t RCC_PLL_GetFreqDomain_SYS(void); -uint32_t RCC_PLL_GetFreqDomain_ADC(void); -uint32_t RCC_PLL_GetFreqDomain_48M(void); +static uint32_t RCC_GetSystemClockFreq(void); +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_PLL_GetFreqDomain_SYS(void); +static uint32_t RCC_PLL_GetFreqDomain_ADC(void); +static uint32_t RCC_PLL_GetFreqDomain_48M(void); /** * @} */ @@ -981,7 +981,7 @@ uint32_t LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource) * @brief Return SYSTEM clock frequency * @retval SYSTEM clock frequency (in Hz) */ -uint32_t RCC_GetSystemClockFreq(void) +static uint32_t RCC_GetSystemClockFreq(void) { uint32_t frequency; @@ -1013,7 +1013,7 @@ uint32_t RCC_GetSystemClockFreq(void) * @param SYSCLK_Frequency SYSCLK clock frequency * @retval HCLK clock frequency (in Hz) */ -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) { /* HCLK clock frequency */ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); @@ -1024,7 +1024,7 @@ uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) * @param HCLK_Frequency HCLK clock frequency * @retval PCLK1 clock frequency (in Hz) */ -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) { /* PCLK1 clock frequency */ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); @@ -1035,7 +1035,7 @@ uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) * @param HCLK_Frequency HCLK clock frequency * @retval PCLK2 clock frequency (in Hz) */ -uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) +static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) { /* PCLK2 clock frequency */ return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); @@ -1045,7 +1045,7 @@ uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) * @brief Return PLL clock frequency used for system domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_SYS(void) +static uint32_t RCC_PLL_GetFreqDomain_SYS(void) { uint32_t pllinputfreq, pllsource; @@ -1076,7 +1076,7 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) * @brief Return PLL clock frequency used for ADC domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_ADC(void) +static uint32_t RCC_PLL_GetFreqDomain_ADC(void) { uint32_t pllinputfreq, pllsource; @@ -1107,7 +1107,7 @@ uint32_t RCC_PLL_GetFreqDomain_ADC(void) * @brief Return PLL clock frequency used for 48 MHz domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_48M(void) +static uint32_t RCC_PLL_GetFreqDomain_48M(void) { uint32_t pllinputfreq, pllsource; diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_spi.c index 68e63c2a4d..dd49c5a8c4 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_spi.c @@ -245,6 +245,12 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) SPI_CR2_DS | SPI_CR2_SSOE, SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U)); + /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */ + if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT) + { + LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER); + } + /*---------------------------- SPIx CRCPR Configuration ---------------------- * Configure SPIx CRCPR with parameters: * - CRCPoly: CRCPOLY[15:0] bits diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_tim.h index c72956b21d..66d7b28ddc 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_tim.h @@ -605,8 +605,8 @@ typedef struct /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode * @{ */ -#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ -#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ @@ -2102,7 +2102,16 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo */ __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) { - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; } /** @@ -2606,8 +2615,8 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); @@ -2653,8 +2662,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } @@ -2694,8 +2703,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint */ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } @@ -2730,7 +2739,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); } @@ -2764,7 +2773,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -2803,7 +2812,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann */ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); } @@ -2837,7 +2846,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); } @@ -2862,8 +2871,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2888,8 +2897,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2914,9 +2923,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2940,8 +2949,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha */ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2965,8 +2974,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2990,9 +2999,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -3019,8 +3028,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -3046,8 +3055,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -3075,9 +3084,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -3432,8 +3441,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), @@ -3460,8 +3469,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 */ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -3484,8 +3493,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -3510,8 +3519,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch */ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -3535,8 +3544,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -3573,8 +3582,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -3610,8 +3619,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui */ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -3639,7 +3648,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), ICPolarity << SHIFT_TAB_CCxP[iChannel]); } @@ -3667,7 +3676,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -4610,7 +4619,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); SET_BIT(*pReg, Source); } @@ -4653,7 +4662,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B */ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); CLEAR_BIT(*pReg, Source); } @@ -4689,7 +4698,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity) { - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.c index 6a64c29a1d..97d36496d0 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.c @@ -66,9 +66,6 @@ /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) -/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ -#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) - #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ || ((__VALUE__) == LL_USART_DIRECTION_RX) \ || ((__VALUE__) == LL_USART_DIRECTION_TX) \ @@ -298,9 +295,6 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* Check BRR is greater than or equal to 16d */ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); - - /* Check BRR is lower than or equal to 0xFFFF */ - assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); } /*---------------------------- USART PRESC Configuration ----------------------- @@ -360,37 +354,25 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef CRx registers */ if (LL_USART_IsEnabled(USARTx) == 0U) { - /*---------------------------- USART CR2 Configuration -----------------------*/ - /* If Clock signal has to be output */ - if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) - { - /* Deactivate Clock signal delivery : - * - Disable Clock Output: USART_CR2_CLKEN cleared - */ - LL_USART_DisableSCLKOutput(USARTx); - } - else - { - /* Ensure USART instance is USART capable */ - assert_param(IS_USART_INSTANCE(USARTx)); + /* Ensure USART instance is USART capable */ + assert_param(IS_USART_INSTANCE(USARTx)); - /* Check clock related parameters */ - assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); - assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); - assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); + /* Check clock related parameters */ + assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); + assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); + assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); - /*---------------------------- USART CR2 Configuration ----------------------- - * Configure USARTx CR2 (Clock signal related bits) with parameters: - * - Enable Clock Output: USART_CR2_CLKEN set - * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value - * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value - * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. - */ - MODIFY_REG(USARTx->CR2, - USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, - USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | - USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); - } + /*---------------------------- USART CR2 Configuration ----------------------- + * Configure USARTx CR2 (Clock signal related bits) with parameters: + * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value + * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value + * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value + * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. + */ + MODIFY_REG(USARTx->CR2, + USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, + USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity | + USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); } /* Else (USART not in Disabled state => return ERROR */ else diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.h index f716e2eb4c..fd0fbd53b9 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usart.h @@ -184,21 +184,21 @@ typedef struct * @brief Flags defines which can be used with LL_USART_WriteReg function * @{ */ -#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ -#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected flag */ -#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ -#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ -#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ -#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ -#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */ -#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */ -#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ -#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */ -#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */ -#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun Clear flag */ -#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ -#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.c index 3611ad2791..2b2a7a68d4 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.c @@ -56,8 +56,8 @@ /** * @brief Initializes the USB Core - * @param USBx: USB Instance - * @param cfg : pointer to a USB_CfgTypeDef structure that contains + * @param USBx USB Instance + * @param cfg pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -78,7 +78,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) /** * @brief USB_EnableGlobalInt * Enables the controller's Global Int in the AHB Config reg - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) @@ -103,7 +103,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) /** * @brief USB_DisableGlobalInt * Disable the controller's Global Int in the AHB Config reg - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) @@ -123,11 +123,11 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) } /** - * @brief USB_SetCurrentMode : Set functional mode - * @param USBx : Selected device - * @param mode : current core mode + * @brief USB_SetCurrentMode Set functional mode + * @param USBx Selected device + * @param mode current core mode * This parameter can be one of the these values: - * @arg USB_DEVICE_MODE: Peripheral mode + * @arg USB_DEVICE_MODE Peripheral mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) @@ -144,10 +144,10 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) } /** - * @brief USB_DevInit : Initializes the USB controller registers + * @brief USB_DevInit Initializes the USB controller registers * for device mode - * @param USBx : Selected device - * @param cfg : pointer to a USB_CfgTypeDef structure that contains + * @param USBx Selected device + * @param cfg pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -157,13 +157,13 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) UNUSED(cfg); /* Init Device */ - /*CNTR_FRES = 1*/ + /* CNTR_FRES = 1 */ USBx->CNTR = (uint16_t)USB_CNTR_FRES; - /*CNTR_FRES = 0*/ + /* CNTR_FRES = 0 */ USBx->CNTR = 0U; - /*Clear pending interrupts*/ + /* Clear pending interrupts */ USBx->ISTR = 0U; /*Set Btable Address*/ @@ -172,71 +172,11 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) return HAL_OK; } -/** - * @brief USB_SetDevSpeed :Initializes the device speed - * depending on the PHY type and the enumeration speed of the device. - * @param USBx Selected device - * @param speed device speed - * @retval Hal status - */ -HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(speed); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - return HAL_OK; -} - -/** - * @brief USB_FlushTxFifo : Flush a Tx FIFO - * @param USBx : Selected device - * @param num : FIFO number - * This parameter can be a value from 1 to 15 - 15 means Flush all Tx FIFOs - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(num); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - return HAL_OK; -} - -/** - * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - return HAL_OK; -} - +#if defined (HAL_PCD_MODULE_ENABLED) /** * @brief Activate and configure an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) @@ -297,9 +237,11 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { /*Set the endpoint Receive buffer address */ PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); + /*Set the endpoint Receive buffer counter*/ PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); PCD_CLEAR_RX_DTOG(USBx, ep->num); + /* Configure VALID status for the Endpoint*/ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); } @@ -309,6 +251,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { /* Set the endpoint as double buffered */ PCD_SET_EP_DBUF(USBx, ep->num); + /* Set buffer address for double buffered mode */ PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); @@ -327,7 +270,6 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) { /* Configure NAK status for the Endpoint */ @@ -348,8 +290,8 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) /** * @brief De-activate and de-initialize an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) @@ -359,12 +301,14 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) if (ep->is_in != 0U) { PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Configure DISABLE status for the Endpoint*/ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } else { PCD_CLEAR_RX_DTOG(USBx, ep->num); + /* Configure DISABLE status for the Endpoint*/ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); } @@ -390,6 +334,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); PCD_RX_DTOG(USBx, ep->num); + /* Configure DISABLE status for the Endpoint*/ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); @@ -400,15 +345,15 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) } /** - * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @brief USB_EPStartXfer setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - uint16_t pmabuffer; uint32_t len; + uint16_t pmabuffer; uint16_t wEPVal; /* IN endpoint */ @@ -432,43 +377,43 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) } else { - /*double buffer bulk management */ + /* double buffer bulk management */ if (ep->type == EP_TYPE_BULK) { if (ep->xfer_len_db > ep->maxpacket) { - /*enable double buffer */ + /* enable double buffer */ PCD_SET_EP_DBUF(USBx, ep->num); - len = ep->maxpacket; - /*each Time to write in PMA xfer_len_db will */ + + /* each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; - /* Fill the two first buffer in the Buffer0 & Buffer1*/ + /* Fill the two first buffer in the Buffer0 & Buffer1 */ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr1; - /*Write the user buffer to USB PMA */ + /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); ep->xfer_buff += len; if (ep->xfer_len_db > ep->maxpacket) { - len = ep->maxpacket; ep->xfer_len_db -= len; } else { len = ep->xfer_len_db; - ep->xfer_len_db = 0; + ep->xfer_len_db = 0U; } /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr0; - /*Write the user buffer to USB PMA */ + + /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } else @@ -476,60 +421,116 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr0; - /*Write the user buffer to USB PMA */ + + /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); ep->xfer_buff += len; if (ep->xfer_len_db > ep->maxpacket) { - len = ep->maxpacket; ep->xfer_len_db -= len; } else { len = ep->xfer_len_db; - ep->xfer_len_db = 0; + ep->xfer_len_db = 0U; } /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr1; - /*Write the user buffer to USB PMA */ + + /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - /*auto Switch to single buffer mode when transfer xfer_len_db; - /*disable double buffer mode */ + + /* disable double buffer mode */ PCD_CLEAR_EP_DBUF(USBx, ep->num); - /*Set Tx count with nbre of byte to be transmitted */ + + /* Set Tx count with nbre of byte to be transmitted */ PCD_SET_EP_TX_CNT(USBx, ep->num, len); pmabuffer = ep->pmaaddr0; - /*Write the user buffer to USB PMA */ + + /* Write the user buffer to USB PMA */ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } - }/*end if bulk double buffer */ + }/* end if bulk double buffer */ - /*mange isochronous double buffer IN mode */ + /* manage isochronous double buffer IN mode */ else { - /* Write the data to the USB endpoint */ + /* enable double buffer */ + PCD_SET_EP_DBUF(USBx, ep->num); + + /* each Time to write in PMA xfer_len_db will */ + ep->xfer_len_db -= len; + + /* Fill the data buffer */ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + if (len > 0U) + { + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } } else { /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + if (len > 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } } - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); } } @@ -539,7 +540,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { - /* Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -551,21 +552,22 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) ep->xfer_len = 0U; } /* configure and validate Rx endpoint */ - /*Set RX buffer count*/ PCD_SET_EP_RX_CNT(USBx, ep->num, len); } else { - /*First Transfer Coming From HAL_PCD_EP_Receive & From ISR*/ - /*Set the Double buffer counter*/ + /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */ + /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /*Coming from ISR*/ + + /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state*/ + /* update last value to check if there is blocking state */ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); + /*Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) @@ -574,10 +576,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) } } } - /*iso out double */ + /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -602,54 +604,11 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) return HAL_OK; } -/** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated - * with the EP/channel - * @param USBx : Selected device - * @param src : pointer to source buffer - * @param ch_ep_num : endpoint or host channel number - * @param len : Number of bytes to write - * @retval HAL status - */ -HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(src); - UNUSED(ch_ep_num); - UNUSED(len); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return HAL_OK; -} /** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated - * with the EP/channel - * @param USBx : Selected device - * @param dest : destination pointer - * @param len : Number of bytes to read - * @retval pointer to destination buffer - */ -void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(dest); - UNUSED(len); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return ((void *)NULL); -} - -/** - * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @brief USB_EPSetStall set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) @@ -667,9 +626,9 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) } /** - * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @brief USB_EPClearStall Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) @@ -690,17 +649,18 @@ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { PCD_CLEAR_RX_DTOG(USBx, ep->num); - /* Configure VALID status for the Endpoint*/ + /* Configure VALID status for the Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); } } return HAL_OK; } +#endif /** - * @brief USB_StopDevice : Stop the usb device mode - * @param USBx : Selected device + * @brief USB_StopDevice Stop the usb device mode + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) @@ -718,9 +678,9 @@ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) } /** - * @brief USB_SetDevAddress : Stop the usb device mode - * @param USBx : Selected device - * @param address : new device address to be assigned + * @brief USB_SetDevAddress Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ @@ -736,8 +696,8 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) } /** - * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down - * @param USBx : Selected device + * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) @@ -749,8 +709,8 @@ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) } /** - * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx : Selected device + * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) @@ -762,8 +722,8 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) } /** - * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx : Selected device + * @brief USB_ReadInterrupts return the global USB interrupt status + * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) @@ -774,114 +734,9 @@ uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) return tmpreg; } -/** - * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return (0); -} - -/** - * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return (0); -} - -/** - * @brief Returns Device OUT EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device OUT EP Interrupt register - */ -uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(epnum); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return (0); -} - -/** - * @brief Returns Device IN EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device IN EP Interrupt register - */ -uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(epnum); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return (0); -} - -/** - * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx Selected device - * @param interrupt flag - * @retval None - */ -void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(interrupt); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ -} - -/** - * @brief Prepare the EP0 to start the first control setup - * @param USBx Selected device - * @param psetup pointer to setup packet - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(psetup); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return HAL_OK; -} - /** * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling - * @param USBx Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) @@ -892,13 +747,14 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) } /** - * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling - * @param USBx Selected device + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) { USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME); + return HAL_OK; } @@ -907,7 +763,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) * @param USBx USB peripheral instance register address. * @param pbUsrBuf pointer to user memory area. * @param wPMABufAddr address into PMA. - * @param wNBytes: no. of bytes to be copied. + * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) @@ -938,10 +794,10 @@ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui /** * @brief Copy data from packet memory area (PMA) to user memory buffer - * @param USBx: USB peripheral instance register address. + * @param USBx USB peripheral instance register address. * @param pbUsrBuf pointer to user memory area. * @param wPMABufAddr address into PMA. - * @param wNBytes: no. of bytes to be copied. + * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.h index 2620a8dd47..f527f66c98 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/STM32G4xx_HAL_Driver/stm32g4xx_ll_usb.h @@ -135,10 +135,10 @@ typedef struct /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define EP_MPS_64 0U -#define EP_MPS_32 1U -#define EP_MPS_16 2U -#define EP_MPS_8 3U +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U /** * @} */ @@ -163,10 +163,10 @@ typedef struct * @} */ -#define BTABLE_ADDRESS 0x000U +#define BTABLE_ADDRESS 0x000U #define PMA_ACCESS 1U -#define EP_ADDR_MSK 0x7U +#define EP_ADDR_MSK 0x7U /** * @} */ @@ -187,32 +187,28 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg); HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed); -HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num); + +#if defined (HAL_PCD_MODULE_ENABLED) HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); -void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len); HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); +#endif + HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address); HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup); uint32_t USB_ReadInterrupts(USB_TypeDef *USBx); -uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); -void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt); - HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx); -void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); + +void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, + uint16_t wPMABufAddr, uint16_t wNBytes); + +void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, + uint16_t wPMABufAddr, uint16_t wNBytes); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/stm32g4xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/stm32g4xx_hal_conf.h index f33cc15614..badba4251b 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/stm32g4xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/stm32g4xx_hal_conf.h @@ -79,119 +79,119 @@ extern "C" { */ #if !defined (USE_HAL_ADC_REGISTER_CALLBACKS) - #define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_COMP_REGISTER_CALLBACKS) - #define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_CORDIC_REGISTER_CALLBACKS) - #define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_CRYP_REGISTER_CALLBACKS) - #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_DAC_REGISTER_CALLBACKS) - #define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_EXTI_REGISTER_CALLBACKS) - #define USE_HAL_EXTI_REGISTER_CALLBACKS 0U +#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_FDCAN_REGISTER_CALLBACKS) - #define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_FMAC_REGISTER_CALLBACKS) - #define USE_HAL_FMAC_REGISTER_CALLBACKS 0U +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_HRTIM_REGISTER_CALLBACKS) - #define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_I2C_REGISTER_CALLBACKS) - #define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_I2S_REGISTER_CALLBACKS) - #define USE_HAL_I2S_REGISTER_CALLBACKS 0U +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_IRDA_REGISTER_CALLBACKS) - #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_LPTIM_REGISTER_CALLBACKS) - #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_NAND_REGISTER_CALLBACKS) - #define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_NOR_REGISTER_CALLBACKS) - #define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_OPAMP_REGISTER_CALLBACKS) - #define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_PCD_REGISTER_CALLBACKS) - #define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_QSPI_REGISTER_CALLBACKS) - #define USE_HAL_QSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_RNG_REGISTER_CALLBACKS) - #define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_RTC_REGISTER_CALLBACKS) - #define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_SAI_REGISTER_CALLBACKS) - #define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_SMARTCARD_REGISTER_CALLBACKS) - #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) - #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_SPI_REGISTER_CALLBACKS) - #define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_SRAM_REGISTER_CALLBACKS) - #define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_TIM_REGISTER_CALLBACKS) - #define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_UART_REGISTER_CALLBACKS) - #define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_USART_REGISTER_CALLBACKS) - #define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_WWDG_REGISTER_CALLBACKS) - #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U #endif /* ########################## Oscillator Values adaptation ####################*/ diff --git a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/system_stm32g4xx.c b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/system_stm32g4xx.c index cb1a0751c7..62a11aa421 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/system_stm32g4xx.c +++ b/targets/TARGET_STM/TARGET_STM32G4/STM32Cube_FW/system_stm32g4xx.c @@ -103,11 +103,27 @@ */ /************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00UL /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ /** * @} @@ -159,20 +175,20 @@ * @retval None */ -void SystemInit(void) +__weak void SystemInit(void) { +#include "nvic_addr.h" // MBED + SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED + /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ #endif /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else -#include "nvic_addr.h" // MBED - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED -#endif +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ } /** diff --git a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TARGET_NUCLEO_G474RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TARGET_NUCLEO_G474RE/PeripheralPins.c index f92db38c86..2792b486f9 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TARGET_NUCLEO_G474RE/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/TARGET_NUCLEO_G474RE/PeripheralPins.c @@ -246,15 +246,15 @@ MBED_WEAK const PinMap PinMap_PWM[] = { MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX - {PA_2_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to STDIO_UART_RX + {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to STDIO_UART_RX {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_14, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to T_SWCLK {PB_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to T_SWO {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, @@ -264,15 +264,15 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX - {PA_3_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to STDIO_UART_TX + {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, // Connected to STDIO_UART_TX {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PB_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_5, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_UART4)}, @@ -284,22 +284,22 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, {PB_4, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_6, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, + {PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_LPUART1)}, {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to T_SWDIO {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART4)}, {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32G4/i2c_device.c b/targets/TARGET_STM/TARGET_STM32G4/i2c_device.c new file mode 100755 index 0000000000..d32c413298 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32G4/i2c_device.c @@ -0,0 +1,149 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "i2c_device.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "stm32g4xx_ll_rcc.h" + +/* Define I2C Device */ +#if DEVICE_I2C + +/** + * @brief Get I2C clock source frequency according I2C instance used. + * @param i2c I2C instance name. + * @retval I2C clock source frequency in Hz. + */ +uint32_t i2c_get_pclk(I2CName i2c) +{ + uint32_t clocksource; + uint32_t pclk = 0; + if (i2c == I2C_1) { + clocksource = __HAL_RCC_GET_I2C1_SOURCE(); + switch (clocksource) { + case RCC_I2C1CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C1CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C1CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#if defined I2C2_BASE + else if (i2c == I2C_2) { + clocksource = __HAL_RCC_GET_I2C2_SOURCE(); + switch (clocksource) { + case RCC_I2C2CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C2CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C2CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif +#if defined I2C3_BASE + else if (i2c == I2C_3) { + clocksource = __HAL_RCC_GET_I2C3_SOURCE(); + switch (clocksource) { + case RCC_I2C3CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C3CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C3CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif +#if defined I2C4_BASE + else if (i2c == I2C_4) { + clocksource = __HAL_RCC_GET_I2C4_SOURCE(); + switch (clocksource) { + case RCC_I2C4CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C4CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C4CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif + else { + // should not happend + error("I2C: unknown instance"); + } + return pclk; +} + +/** + * @brief Provide the suitable timing depending on requested frequency + * @param hz Required I2C clock in Hz. + * @retval I2C timing or 0 in case of error. + */ +uint32_t i2c_get_timing(I2CName i2c, int hz) +{ + uint32_t tim; + uint32_t pclk; + pclk = i2c_get_pclk(i2c); + if (pclk == I2C_PCLK_DEF) { + switch (hz) { + case 100000: + tim = TIMING_VAL_DEFAULT_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_DEFAULT_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_DEFAULT_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } else { + /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. + User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. + Enabling this may impact performance*/ + MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO); +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + tim = i2c_compute_timing(pclk, hz); +#endif + } + return tim; +} +/** + * @} + */ +#endif // DEVICE_I2C diff --git a/targets/TARGET_STM/TARGET_STM32G4/i2c_device.h b/targets/TARGET_STM/TARGET_STM32G4/i2c_device.h index 35f5c320e1..5d61cf1f91 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32G4/i2c_device.h @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2015-2020 STMicroelectronics. + * Copyright (c) 2015-2021 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -16,14 +16,22 @@ #ifndef MBED_I2C_DEVICE_H #define MBED_I2C_DEVICE_H -#include "cmsis.h" +#include "PeripheralNames.h" #ifdef __cplusplus extern "C" { #endif +/* Define I2C Device */ #if DEVICE_I2C +// Common settings: I2C clock = 64 MHz, Analog filter = ON, Digital filter coefficient = 0 +#define TIMING_VAL_DEFAULT_CLK_100KHZ 0xC0311319 // Standard mode with Rise Time = 400ns and Fall Time = 100ns +#define TIMING_VAL_DEFAULT_CLK_400KHZ 0x10B1102E // Fast mode with Rise Time = 250ns and Fall Time = 100ns +#define TIMING_VAL_DEFAULT_CLK_1MHZ 0x00710B1E // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns +#define I2C_PCLK_DEF 160000000 // 160 MHz + +/* Define IP version */ #define I2C_IP_VERSION_V2 #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI) @@ -34,31 +42,18 @@ extern "C" { #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_SYSCLK #define I2CAPI_I2C4_CLKSRC RCC_I2C4CLKSOURCE_SYSCLK -/* Provide the suitable timing depending on requested frequencie */ -static inline uint32_t get_i2c_timing(int hz) -{ - uint32_t tim = 0; - // Common settings: I2C clock = 64 MHz, Analog filter = ON, Digital filter coefficient = 0 - switch (hz) { - case 100000: - tim = 0xC0311319; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - tim = 0x10B1102E; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - tim = 0x00710B1E; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - return tim; -} +uint32_t i2c_get_pclk(I2CName i2c); +uint32_t i2c_get_timing(I2CName i2c, int hz); + +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq); +void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t I2C_speed); +uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t I2C_speed); +#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +#endif // DEVICE_I2C #ifdef __cplusplus } #endif -#endif // DEVICE_I2C - #endif diff --git a/targets/TARGET_STM/TARGET_STM32G4/objects.h b/targets/TARGET_STM/TARGET_STM32G4/objects.h index c548ad77e4..bb466ce224 100644 --- a/targets/TARGET_STM/TARGET_STM32G4/objects.h +++ b/targets/TARGET_STM/TARGET_STM32G4/objects.h @@ -111,6 +111,9 @@ struct i2c_s { uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h723xx.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h723xx.h index 4e5a3e03a0..610abfdc5e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h723xx.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/CMSIS/stm32h723xx.h @@ -674,7 +674,7 @@ typedef struct __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */ __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */ __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */ - uint32_t RESERVED0; /*!< Reserved, 0x68 */ + uint32_t RESERVED0; /*!< Reserved, 0x6C */ __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */ __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */ }MDMA_Channel_TypeDef; @@ -924,6 +924,15 @@ __IO uint32_t EMR3; /*!< EXTI Event mask register, __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */ }EXTI_TypeDef; +/** + * @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2 + * with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2. + * Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register: + * IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7) + * C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4) + * Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only + */ + typedef struct { __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ @@ -1950,6 +1959,96 @@ typedef struct * @} */ +/** + * @brief Global Programmer View + */ + +typedef struct +{ + uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */ + __IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */ + uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */ + uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */ + uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */ + __IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */ + __IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */ + __IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */ + __IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */ + __IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */ + __IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */ + __IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */ + __IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */ + __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */ + __IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */ + __IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */ + uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */ + __IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */ + uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */ + __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */ + uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */ + __IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */ + __IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */ + uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */ + __IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */ + uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */ + __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */ + uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */ + __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */ + uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */ + __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */ + uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */ + __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */ + uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */ + __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */ + uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */ + __IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */ + __IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */ + uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */ + __IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */ + uint32_t RESERVED17[959]; /*!< Reserved, Address offset: 0x810C-0x9004 */ + __IO uint32_t AXI_TARG8_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 8 bus matrix issuing functionality register, Address offset: 0x9008 */ + uint32_t RESERVED117[6]; /*!< Reserved, Address offset: 0x900C-0x9020 */ + __IO uint32_t AXI_TARG8_FN_MOD2; /*!< AXI interconnect - TARG 8 bus matrix functionality 2 register, Address offset: 0x9024 */ + uint32_t RESERVED118[56]; /*!< Reserved, Address offset: 0x9028-0x9104 */ + __IO uint32_t AXI_TARG8_FN_MOD; /*!< AXI interconnect - TARG 8 issuing functionality modification register, Address offset: 0x9108 */ + uint32_t RESERVED119[58310]; /*!< Reserved, Address offset: 0x910C-0x42020 */ + __IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */ + __IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */ + uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */ + __IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */ + __IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */ + __IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */ + uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */ + __IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */ + __IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */ + __IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */ + uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */ + __IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */ + __IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */ + uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */ + __IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */ + __IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */ + __IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */ + uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */ + __IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */ + __IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */ + __IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */ + uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */ + __IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */ + __IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */ + __IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */ + uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */ + __IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */ + __IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */ + __IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */ + +} GPV_TypeDef; + /** @addtogroup Peripheral_memory_map * @{ */ @@ -2304,6 +2403,9 @@ typedef struct #define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL) + +#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */ + /** * @} */ @@ -2588,6 +2690,8 @@ typedef struct #define USB_OTG_HS USB1_OTG_HS #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE +#define GPV ((GPV_TypeDef *) GPV_BASE) + /** * @} */ @@ -2836,7 +2940,7 @@ typedef struct #define ADC3_CFGR_ALIGN_Pos (15U) #define ADC3_CFGR_ALIGN_Msk (0x1UL << ADC3_CFGR_ALIGN_Pos) /*!< 0x00008000 */ -#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignement */ +#define ADC3_CFGR_ALIGN ADC3_CFGR_ALIGN_Msk /*!< ADC data alignment */ /******************** Bit definition for ADC_CFGR2 register ********************/ #define ADC_CFGR2_ROVSE_Pos (0U) #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ @@ -3125,7 +3229,7 @@ typedef struct /******************** Bit definition for ADC_SQR1 register ********************/ #define ADC_SQR1_L_Pos (0U) #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ -#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ @@ -4061,7 +4165,7 @@ typedef struct /***************** Bit definition for FDCAN_ENDN register *******************/ #define FDCAN_ENDN_ETV_Pos (0U) #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */ -#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -10808,7 +10909,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -10903,7 +11004,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -11028,7 +11133,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -14185,7 +14294,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -11096,7 +11197,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -11221,7 +11326,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */ @@ -14378,7 +14483,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */ @@ -8836,7 +8964,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */ @@ -8837,7 +8965,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */ @@ -9090,7 +9218,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!> 1) /* 1 MB */ #define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */ #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */ @@ -9091,7 +9219,7 @@ typedef struct /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!CR, DBGMCU_CR_DBG_STOPD3); } + /** * @brief Disable the Debug Module during Domain3/SRDomain STOP mode * @retval None @@ -1037,7 +1039,9 @@ void HAL_DisableDomain3DBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); } +#endif /*DBGMCU_CR_DBG_STOPD3*/ +#if defined(DBGMCU_CR_DBG_STANDBYD3) /** * @brief Enable the Debug Module during Domain3/SRDomain STANDBY mode * @retval None @@ -1055,6 +1059,7 @@ void HAL_DisableDomain3DBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); } +#endif /*DBGMCU_CR_DBG_STANDBYD3*/ /** * @brief Set the FMC Memory Mapping Swapping config. diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.h index 8f9946f024..95a44bf59c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal.h @@ -69,10 +69,10 @@ typedef enum /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale * @{ */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 0 (VREF_OUT2) */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 1 (VREF_OUT1) */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 2 (VREF_OUT4) */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 3 (VREF_OUT3) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */ +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */ #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ @@ -1093,10 +1093,14 @@ void HAL_DisableDomain2DBGStopMode(void); void HAL_EnableDomain2DBGStandbyMode(void); void HAL_DisableDomain2DBGStandbyMode(void); #endif /*DUAL_CORE*/ +#if defined(DBGMCU_CR_DBG_STOPD3) void HAL_EnableDomain3DBGStopMode(void); void HAL_DisableDomain3DBGStopMode(void); +#endif /*DBGMCU_CR_DBG_STOPD3*/ +#if defined(DBGMCU_CR_DBG_STANDBYD3) void HAL_EnableDomain3DBGStandbyMode(void); void HAL_DisableDomain3DBGStandbyMode(void); +#endif /*DBGMCU_CR_DBG_STANDBYD3*/ void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge ); void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); #if defined(DUAL_CORE) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.c index 9c1b530bca..7803f9281e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.c @@ -3,7 +3,7 @@ * @file stm32h7xx_hal_adc.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) + * functionalities of the Analog to Digital Converter (ADC) * peripheral: * + Initialization and de-initialization functions * ++ Initialization and Configuration of ADC @@ -26,7 +26,7 @@ [..] (+) 16-bit, 14-bit, 12-bit, 10-bit or 8-bit configurable resolution. Note: On devices STM32H72xx and STM32H73xx, these resolution are applicable to instances ADC1 and ADC2. - ADC3 is featuring resolutions 12-bit, 10-bit, 8-bit, 6-bit. + ADC3 is featuring resolutions 12-bit, 10-bit, 8-bit, 6-bit. (+) Interrupt generation at the end of regular conversion and in case of analog watchdog or overrun events. @@ -510,7 +510,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -1054,32 +1054,31 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) */ ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc); - } - /* DeInit the low level hardware. + /* ========== Hard reset ADC peripheral ========== */ + /* Performs a global reset of the entire ADC peripherals instances */ + /* sharing the same common ADC instance: ADC state is forced to */ + /* a similar state as after device power-on. */ + /* Note: A possible implementation is to add RCC bus reset of ADC */ + /* (for example, using macro */ + /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */ + /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ - For example: - __HAL_RCC_ADC_FORCE_RESET(); - __HAL_RCC_ADC_RELEASE_RESET(); - __HAL_RCC_ADC_CLK_DISABLE(); - - Keep in mind that all ADCs use the same clock: disabling - the clock will reset all ADCs. - - */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - if (hadc->MspDeInitCallback == NULL) - { - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - } + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } - /* DeInit the low level hardware: RCC clock, NVIC */ - hadc->MspDeInitCallback(hadc); + /* DeInit the low level hardware: RCC clock, NVIC */ + hadc->MspDeInitCallback(hadc); #else - /* DeInit the low level hardware: RCC clock, NVIC */ - HAL_ADC_MspDeInit(hadc); + /* DeInit the low level hardware: RCC clock, NVIC */ + HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); @@ -1646,13 +1645,17 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -1757,13 +1760,17 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if(__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -2274,7 +2281,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { - /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */ + /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1, 0UL); /* Disable the DMA channel (in case of DMA in circular mode or stop */ @@ -3056,7 +3063,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -3124,7 +3131,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf * The setting of these parameters is conditioned to ADC state. * For parameters constraints, see comments of structure * "ADC_AnalogWDGConfTypeDef". - * @note On this STM32 serie, analog watchdog thresholds cannot be modified + * @note On this STM32 series, analog watchdog thresholds cannot be modified * while ADC conversion is on going. * @param hadc ADC handle * @param AnalogWDGConfig Structure of ADC analog watchdog configuration @@ -3641,13 +3648,17 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } @@ -3718,13 +3729,17 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -3779,13 +3794,17 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.h index 5be1e1a34a..155aaa7c7c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc.h @@ -128,11 +128,11 @@ typedef struct This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. This parameter can be set to ENABLE or DISABLE. - Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag - to free the IRQ vector sequencer. - Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: - use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. - (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ + Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). + Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). + Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: + and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, + use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, after the first ADC conversion start trigger occurred (software start or external trigger). @@ -163,7 +163,7 @@ typedef struct If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_regular_external_trigger_edge */ - uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register. + uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transferred to DFSDM register. Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. This parameter can be a value of @ref ADC_ConversionDataManagement. Note: This parameter must be modified when no conversion is on going on both regular and injected groups @@ -266,7 +266,7 @@ typedef struct This parameter is applied only for 16-bit or 8-bit resolution. This parameter can be set to ENABLE or DISABLE.*/ #if defined(ADC_VER_V5_V90) - uint32_t OffsetSign; /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data. + uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. This parameter can be a value of @ref ADCEx_OffsetSign. Note: - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled @@ -380,7 +380,7 @@ typedef struct external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ +#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ /* States of ADC group injected */ #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, @@ -533,7 +533,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define ADC3_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define ADC3_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ +#define ADC3_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} */ @@ -1773,7 +1773,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * connected to pin Vref+. * On devices with small package, the pin Vref+ is not present * and internally bonded to pin Vdda. - * @note On this STM32 serie, calibration data of internal voltage reference + * @note On this STM32 series, calibration data of internal voltage reference * VrefInt corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * internal voltage reference VrefInt. @@ -1821,7 +1821,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note On this STM32 serie, calibration data of temperature sensor + * @note On this STM32 series, calibration data of temperature sensor * corresponds to a resolution of 12 bits, * this is the recommended ADC resolution to convert voltage of * temperature sensor. diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.c index a325f76c8f..8e44bf1e6e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.c @@ -3,7 +3,7 @@ * @file stm32h7xx_hal_adc_ex.c * @author MCD Application Team * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) + * functionalities of the Analog to Digital Converter (ADC) * peripheral: * + Operation functions * ++ Start, stop, get result of conversions of ADC group injected, @@ -349,7 +349,7 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, /* Wait loop initialization and execution */ /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ - wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / (1000000UL * 2UL))); + wait_loop_index = ((ADC_STAB_DELAY_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -682,13 +682,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + if((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -1026,6 +1029,8 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t /* Process locked */ __HAL_LOCK(hadc); + tmphadcSlave.State = HAL_ADC_STATE_RESET; + tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -1141,6 +1146,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { + tmphadcSlave.State = HAL_ADC_STATE_RESET; + tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -1168,13 +1176,21 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + if((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } } tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); @@ -1623,6 +1639,9 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + tmphadcSlave.State = HAL_ADC_STATE_RESET; + tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -1650,13 +1669,21 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + if((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - return HAL_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } } tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); @@ -2234,7 +2261,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -2316,6 +2343,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ /* Process locked */ __HAL_LOCK(hadc); + tmphadcSlave.State = HAL_ADC_STATE_RESET; + tmphadcSlave.ErrorCode = HAL_ADC_ERROR_NONE; + ADC_MULTI_SLAVE(hadc, &tmphadcSlave); if (tmphadcSlave.Instance == NULL) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.h index b86c259ed1..ae185074db 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_adc_ex.h @@ -122,7 +122,7 @@ typedef struct This parameter is applied only for 16-bit or 8-bit resolution. This parameter can be set to ENABLE or DISABLE. */ #if defined(ADC_VER_V5_V90) - uint32_t InjectedOffsetSign; /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data. + uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. This parameter can be a value of @ref ADCEx_OffsetSign. Note: - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). @@ -295,7 +295,7 @@ typedef struct /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign * @{ */ -#define ADC3_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is substracted */ +#define ADC3_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ #define ADC3_OFFSET_SIGN_POSITIVE (ADC3_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ /** * @} @@ -415,7 +415,7 @@ typedef struct * @{ */ #define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */ -#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ +#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ /** * @} */ @@ -441,7 +441,7 @@ typedef struct * Usage of this macro is not the Standard way of multimode * configuration and can lead to have HAL ADC handles status * misaligned. Usage of this macro must be limited to cases - * mentionned above. + * mentioned above. * @param __HANDLE__ ADC handle. * @retval None */ @@ -1207,7 +1207,10 @@ typedef struct ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) + ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_9 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_10 ) || \ + ((__SHIFT__) == ADC_RIGHTBITSHIFT_11 )) /** * @brief Verify the ADC oversampling triggered mode. diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.c index 72ad84ea9c..d732a36d6a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.c @@ -822,19 +822,15 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* CEC TX byte request interrupt ------------------------------------------------*/ if ((reg & CEC_FLAG_TXBR) != 0U) { + --hcec->TxXferCount; if (hcec->TxXferCount == 0U) { /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ __HAL_CEC_LAST_BYTE_TX_SET(hcec); - hcec->Instance->TXDR = *hcec->pTxBuffPtr; - hcec->pTxBuffPtr++; - } - else - { - hcec->Instance->TXDR = *hcec->pTxBuffPtr; - hcec->pTxBuffPtr++; - hcec->TxXferCount--; } + /* In all cases transmit the byte */ + hcec->Instance->TXDR = *hcec->pTxBuffPtr; + hcec->pTxBuffPtr++; /* clear Tx-Byte request flag */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); } diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.h index 9b138bacf1..e4ff48d33e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cec.h @@ -121,7 +121,7 @@ typedef struct * b6 Error information * 0 : No Error * 1 : Error - * b5 IP initilisation status + * b5 IP initialization status * 0 : Reset (IP not initialized) * 1 : Init done (IP initialized. HAL CEC Init function already called) * b4-b3 (not used) @@ -138,7 +138,7 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initilisation status + * b5 IP initialization status * 0 : Reset (IP not initialized) * 1 : Init done (IP initialized) * b4-b2 (not used) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.c index aae1146145..59a2590ce8 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_comp.c @@ -372,7 +372,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles.*/ - wait_loop_index = (COMP_DELAY_VOLTAGE_SCALER_STAB_US * (SystemCoreClock / (1000000UL * 2UL))); + wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while(wait_loop_index != 0UL) { @@ -782,7 +782,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ - wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL))); + wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while(wait_loop_index != 0UL) { wait_loop_index--; @@ -879,7 +879,7 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles. */ - wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL))); + wait_loop_index = ((COMP_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while(wait_loop_index != 0UL) { wait_loop_index--; diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.c index 85c19c1fb5..37f70e7ef6 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.c @@ -363,7 +363,8 @@ __weak void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, void (* pCallback)(CORDIC_HandleTypeDef *_hcordic)) +HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, + void (* pCallback)(CORDIC_HandleTypeDef *_hcordic)) { HAL_StatusTypeDef status = HAL_OK; @@ -525,8 +526,8 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H */ /** @defgroup CORDIC_Exported_Functions_Group2 Peripheral Control functions - * @brief Control functions. - * + * @brief Control functions. + * @verbatim ============================================================================== ##### Peripheral Control functions ##### @@ -602,7 +603,8 @@ HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_Con * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout) +HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t Timeout) { uint32_t tickstart; uint32_t index; @@ -659,8 +661,7 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *p return HAL_ERROR; } } - } - while (HAL_IS_BIT_CLR(hcordic->Instance->CSR, CORDIC_CSR_RRDY)); + } while (HAL_IS_BIT_CLR(hcordic->Instance->CSR, CORDIC_CSR_RRDY)); /* Read output data from Read Data register, and increment output buffer pointer */ CORDIC_ReadOutDataIncrementPtr(hcordic, &p_tmp_out_buff); @@ -696,7 +697,8 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *p * @param Timeout Specify Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout) +HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t Timeout) { uint32_t tickstart; uint32_t index; @@ -788,7 +790,8 @@ HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t * @param NbCalc Number of CORDIC calculation to process. * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc) +HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc) { int32_t *tmp_pInBuff = pInBuff; @@ -879,7 +882,8 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t * DMA transfer to and from the Peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection) +HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t DMADirection) { uint32_t sizeinbuff; uint32_t sizeoutbuff; @@ -1026,8 +1030,8 @@ HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_ */ /** @defgroup CORDIC_Exported_Functions_Group3 Callback functions - * @brief Callback functions. - * + * @brief Callback functions. + * @verbatim ============================================================================== ##### Callback functions ##### @@ -1077,8 +1081,8 @@ __weak void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic) */ /** @defgroup CORDIC_Exported_Functions_Group4 IRQ handler management - * @brief IRQ handler. - * + * @brief IRQ handler. + * @verbatim ============================================================================== ##### IRQ handler management ##### @@ -1147,8 +1151,8 @@ void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic) */ /** @defgroup CORDIC_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim ============================================================================== ##### Peripheral State functions ##### diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.h index 1fb920883c..04e2d79b52 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cordic.h @@ -198,15 +198,21 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p #define CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2)) #define CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) #define CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) -#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) #define CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3)) #define CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0)) #define CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1)) -#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) #define CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2)) -#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) -#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) -#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) +#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) +#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ + |CORDIC_CSR_PRECISION_0)) /** * @} */ @@ -257,7 +263,8 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #define CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one 32-bit data input (Q1.31 format), or two 16-bit - data input (Q1.15 format) packed in one 32 bits Data */ + data input (Q1.15 format) packed in one 32 bits + Data */ #define CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input (Q1.31 format) */ /** @@ -268,8 +275,9 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @{ */ #define CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data ouput (Q1.31 format), or two 16-bit - data output (Q1.15 format) packed in one 32 bits Data */ + 32-bit data output (Q1.31 format), or two 16-bit + data output (Q1.15 format) packed in one 32 bits + Data */ #define CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output (Q1.31 format) */ /** @@ -329,9 +337,9 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p */ #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ + (__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET) @@ -346,7 +354,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @retval None */ #define __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__)) + (((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__)) /** * @brief Disable the CORDIC interrupt @@ -357,7 +365,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @retval None */ #define __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__)) + (((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__)) /** @brief Check whether the specified CORDIC interrupt occurred or not. Dummy macro as no interrupt status flag. @@ -383,7 +391,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @retval SET (flag is set) or RESET (flag is reset) */ #define __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__) \ - ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__)) + ((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear specified CORDIC status flag. Dummy macro as no flag can be cleared. @@ -403,7 +411,7 @@ typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< p * @retval FlagStatus */ #define __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__)) + (((__HANDLE__)->Instance->CSR) & (__INTERRUPT__)) /** * @} @@ -527,7 +535,8 @@ void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic); #if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1 /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, pCORDIC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID, + pCORDIC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID); /** * @} @@ -539,10 +548,14 @@ HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, H #endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */ /* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig); -HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout); -HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t Timeout); -HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc); -HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, uint32_t NbCalc, uint32_t DMADirection); +HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t Timeout); +HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t Timeout); +HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc); +HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff, + uint32_t NbCalc, uint32_t DMADirection); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.c index 6e5861b414..97e70c1491 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_crc_ex.c @@ -11,7 +11,7 @@ ##### How to use this driver ##### ================================================================================ [..] - (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set() + (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set() (+) Configure Input or Output data inversion @endverbatim diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c index 0407c65a23..c1febda0d0 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.c @@ -4357,10 +4357,23 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { uint32_t loopcounter; + uint32_t size_in_bytes; + uint32_t tmp; + uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU}; /***************************** Header phase for GCM/GMAC or CCM *********************************/ - if ((hcryp->Init.HeaderSize != 0U)) + + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + size_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + size_in_bytes = hcryp->Init.HeaderSize; + } + + if ((size_in_bytes != 0U)) { /* Select header phase */ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); @@ -4368,10 +4381,12 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u /* Enable the CRYP peripheral */ __HAL_CRYP_ENABLE(hcryp); - if ((hcryp->Init.HeaderSize % 4U) == 0U) + /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */ + if ((size_in_bytes % 16U) == 0U) { - /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) + /* No padding */ + for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U) + { hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; @@ -4400,8 +4415,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } else { - /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) + /* Write header block in the IN FIFO without last block */ + for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U) { hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; @@ -4428,16 +4443,34 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } } /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) + for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++) { hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } - while (loopcounter < 4U) + /* If the header size is a multiple of words */ + if ((size_in_bytes % 4U) == 0U) { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DIN = 0x0U; - loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DIN = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeroes */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[size_in_bytes % 4U]; + hcryp->Instance->DIN = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DIN = 0x0U; + loopcounter++; + } } /* Wait for CCF IFEM to be raised */ if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.h index fc24fbf09d..619c86285b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp.h @@ -61,9 +61,10 @@ typedef struct uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication, GCM : also known as Additional Authentication Data CCM : named B1 composed of the associated data length and Associated Data. */ - uint32_t HeaderSize; /*!< The size of header buffer in word */ + uint32_t HeaderSize; /*!< The size of header buffer */ uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ - uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ + uint32_t DataWidthUnit; /*!< Payload data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ + uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/ uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to configure Key and Initialization Vector only once and to skip configuration for consecutive processing. This parameter can be a value of @ref CRYP_Configuration_Skip */ @@ -212,6 +213,17 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point #define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */ #define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */ +/** + * @} + */ + +/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit + * @{ + */ + +#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */ +#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.c index a8a94aa018..ae24733635 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_cryp_ex.c @@ -113,9 +113,15 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u { uint32_t tickstart; uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */ - uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */ + uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */ uint32_t tagaddr = (uint32_t)AuthTag; + /* Correct header length if Init.HeaderSize is actually in bytes */ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE) + { + headerlength /= 4U; + } + if (hcryp->State == HAL_CRYP_STATE_READY) { /* Process locked */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.c index 89fbd803ea..db5ab8c7da 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.c @@ -693,7 +693,7 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u /* Enable the DAC DMA underrun interrupt */ __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); - /* Enable the DMA Stream */ + /* Enable the DMA Stream */ status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); } else @@ -734,8 +734,6 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, u */ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) { - HAL_StatusTypeDef status; - /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); @@ -751,7 +749,7 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) if (Channel == DAC_CHANNEL_1) { /* Disable the DMA Stream */ - status = HAL_DMA_Abort(hdac->DMA_Handle1); + (void)HAL_DMA_Abort(hdac->DMA_Handle1); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); @@ -759,26 +757,17 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) else /* Channel2 is used for */ { /* Disable the DMA Stream */ - status = HAL_DMA_Abort(hdac->DMA_Handle2); + (void)HAL_DMA_Abort(hdac->DMA_Handle2); /* Disable the DAC DMA underrun interrupt */ __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); } - /* Check if DMA Stream effectively disabled */ - if (status != HAL_OK) - { - /* Update DAC state machine to error */ - hdac->State = HAL_DAC_STATE_ERROR; - } - else - { - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - } + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -1085,9 +1074,11 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf } /* HoldTime */ - MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), + (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL)); /* RefreshTime */ - MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), + (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL)); } if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) @@ -1339,7 +1330,7 @@ HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_Call * @param hdac DAC handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID + * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.h index e248dd4a4c..fb2ff1bbae 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac.h @@ -79,17 +79,17 @@ typedef struct __IO uint32_t ErrorCode; /*!< DAC Error code */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); - void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); - void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac); + void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } DAC_HandleTypeDef; @@ -391,7 +391,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt * @retval State of interruption (SET or RESET) */ -#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Get the selected DAC's flag status. * @param __HANDLE__ specifies the DAC handle. diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.c index 15dc83eaee..50dd895d5b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dac_ex.c @@ -128,11 +128,11 @@ HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2); /* Check if software trigger enabled */ - if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_CR_TEN1) + if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) { tmp_swtrig |= DAC_SWTRIGR_SWTRIG1; } - if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == DAC_CR_TEN2) + if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL))) { tmp_swtrig |= DAC_SWTRIGR_SWTRIG2; } @@ -380,7 +380,8 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32 hdac->State = HAL_DAC_STATE_BUSY; /* Enable the triangle wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), + (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -429,7 +430,8 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t hdac->State = HAL_DAC_STATE_BUSY; /* Enable the noise wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), + (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.c index 46906e09b7..f9079cf41d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dcmi.c @@ -571,7 +571,7 @@ HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi) /* Change DCMI state */ hdcmi->State = HAL_DCMI_STATE_BUSY; - /* Disable Capture */ + /* Enable Capture */ hdcmi->Instance->CR |= DCMI_CR_CAPTURE; } /* Process Unlocked */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_def.h index d59c8c12bb..f7e3c1345c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_def.h @@ -107,7 +107,15 @@ typedef enum }while (0) #endif /* USE_RTOS */ -#if defined ( __GNUC__ ) + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif + #ifndef __packed + #define __packed __attribute__((packed)) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __weak #define __weak __attribute__((weak)) #endif /* __weak */ @@ -118,7 +126,14 @@ typedef enum /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) /* GNU Compiler */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ #ifndef __ALIGN_END #define __ALIGN_END __attribute__ ((aligned (4))) #endif /* __ALIGN_END */ @@ -130,7 +145,7 @@ typedef enum #define __ALIGN_END #endif /* __ALIGN_END */ #ifndef __ALIGN_BEGIN - #if defined (__CC_ARM) /* ARM Compiler */ + #if defined (__CC_ARM) /* ARM Compiler V5 */ #define __ALIGN_BEGIN __align(4) #elif defined (__ICCARM__) /* IAR Compiler */ #define __ALIGN_BEGIN @@ -150,9 +165,9 @@ typedef enum /** * @brief __RAM_FUNC definition */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- RAM functions are defined using the toolchain options. Functions that are executed in RAM should reside in a separate source module. Using the 'Options for File' dialog you can simply change the 'Code / Const' @@ -179,6 +194,24 @@ typedef enum #endif +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + + #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.h index 648ef949f7..189efd0c9e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dfsdm.h @@ -302,8 +302,8 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection * @{ */ -#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */ -#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ +#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for output clock is system clock */ +#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for output clock is audio clock */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.c index 6a8bce56e2..934400ce42 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.c @@ -292,7 +292,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) } /* Work around for Errata 2.22: UART/USART- DMA transfer lock: DMA stream could be - lock when transfering data to/from USART/UART */ + lock when transferring data to/from USART/UART */ #if (STM32H7_DEV_ID == 0x450UL) if((DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U) { @@ -967,7 +967,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param CompleteLevel: Specifies the DMA level complete. - * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. + * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. * This model could be used for debug purpose. * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). * @param Timeout: Timeout duration. diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.h index 3c1f6fe128..7da4420851 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma.h @@ -346,11 +346,11 @@ typedef struct __DMA_HandleTypeDef #if defined(HRTIM1) #define DMA_REQUEST_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */ -#define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */ -#define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */ -#define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */ -#define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */ -#define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */ +#define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 Timer A request 2 */ +#define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 Timer B request 3 */ +#define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 Timer C request 4 */ +#define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 Timer D request 5 */ +#define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 Timer E request 6*/ #endif /* HRTIM1 */ #define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.c index 1703055848..dcc18836fd 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.c @@ -201,7 +201,8 @@ /** @addtogroup DMA2D_Private_Functions DMA2D Private Functions * @{ */ -static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); +static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height); /** * @} */ @@ -213,8 +214,8 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ */ /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and Configuration functions ##### @@ -237,9 +238,9 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) { /* Check the DMA2D peripheral state */ - if(hdma2d == NULL) + if (hdma2d == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ @@ -258,7 +259,7 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */ hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; - if(hdma2d->MspInitCallback == NULL) + if (hdma2d->MspInitCallback == NULL) { hdma2d->MspInitCallback = HAL_DMA2D_MspInit; } @@ -267,7 +268,7 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) hdma2d->MspInitCallback(hdma2d); } #else - if(hdma2d->State == HAL_DMA2D_STATE_RESET) + if (hdma2d->State == HAL_DMA2D_STATE_RESET) { /* Allocate lock resource and initialize it */ hdma2d->Lock = HAL_UNLOCKED; @@ -283,12 +284,15 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode); /* DMA2D OPFCCR register configuration ---------------------------------------*/ - MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap); + MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, + hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap); /* DMA2D OOR register configuration ------------------------------------------*/ MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/ - MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos))); + MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS), + ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | \ + (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos))); /* Update error code */ @@ -312,9 +316,9 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) { /* Check the DMA2D peripheral state */ - if(hdma2d == NULL) + if (hdma2d == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Before aborting any DMA2D transfer or CLUT loading, check @@ -367,13 +371,13 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) - if(hdma2d->MspDeInitCallback == NULL) - { - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; - } + if (hdma2d->MspDeInitCallback == NULL) + { + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; + } - /* DeInit the low level hardware */ - hdma2d->MspDeInitCallback(hdma2d); + /* DeInit the low level hardware */ + hdma2d->MspDeInitCallback(hdma2d); #else /* Carry on with de-initialization of low level hardware */ @@ -398,7 +402,7 @@ HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) * the configuration information for the DMA2D. * @retval None */ -__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) +__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma2d); @@ -414,7 +418,7 @@ __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d) * the configuration information for the DMA2D. * @retval None */ -__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) +__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma2d); @@ -441,11 +445,12 @@ __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d) * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID * @retval status */ -HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, + pDMA2D_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; @@ -454,68 +459,68 @@ HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DM /* Process locked */ __HAL_LOCK(hdma2d); - if(HAL_DMA2D_STATE_READY == hdma2d->State) + if (HAL_DMA2D_STATE_READY == hdma2d->State) { switch (CallbackID) { - case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : - hdma2d->XferCpltCallback = pCallback; - break; + case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : + hdma2d->XferCpltCallback = pCallback; + break; - case HAL_DMA2D_TRANSFERERROR_CB_ID : - hdma2d->XferErrorCallback = pCallback; - break; + case HAL_DMA2D_TRANSFERERROR_CB_ID : + hdma2d->XferErrorCallback = pCallback; + break; - case HAL_DMA2D_LINEEVENT_CB_ID : - hdma2d->LineEventCallback = pCallback; - break; + case HAL_DMA2D_LINEEVENT_CB_ID : + hdma2d->LineEventCallback = pCallback; + break; - case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : - hdma2d->CLUTLoadingCpltCallback = pCallback; - break; + case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : + hdma2d->CLUTLoadingCpltCallback = pCallback; + break; - case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = pCallback; - break; + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = pCallback; + break; - case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = pCallback; - break; + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = pCallback; + break; - default : - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } - else if(HAL_DMA2D_STATE_RESET == hdma2d->State) + else if (HAL_DMA2D_STATE_RESET == hdma2d->State) { switch (CallbackID) { - case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = pCallback; - break; + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = pCallback; + break; - case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = pCallback; - break; + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = pCallback; + break; - default : - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else { /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; } /* Release Lock */ @@ -540,73 +545,73 @@ HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DM */ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID) { -HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hdma2d); - if(HAL_DMA2D_STATE_READY == hdma2d->State) + if (HAL_DMA2D_STATE_READY == hdma2d->State) { switch (CallbackID) { - case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : - hdma2d->XferCpltCallback = NULL; - break; + case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : + hdma2d->XferCpltCallback = NULL; + break; - case HAL_DMA2D_TRANSFERERROR_CB_ID : - hdma2d->XferErrorCallback = NULL; - break; + case HAL_DMA2D_TRANSFERERROR_CB_ID : + hdma2d->XferErrorCallback = NULL; + break; - case HAL_DMA2D_LINEEVENT_CB_ID : - hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; - break; + case HAL_DMA2D_LINEEVENT_CB_ID : + hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; + break; - case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : - hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; - break; + case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : + hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; + break; - case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ - break; + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; - case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ - break; + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; - default : - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } - else if(HAL_DMA2D_STATE_RESET == hdma2d->State) + else if (HAL_DMA2D_STATE_RESET == hdma2d->State) { switch (CallbackID) { - case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ - break; + case HAL_DMA2D_MSPINIT_CB_ID : + hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */ + break; - case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ - break; + case HAL_DMA2D_MSPDEINIT_CB_ID : + hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ + break; - default : - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else { - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; + /* Update the error code */ + hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; } /* Release Lock */ @@ -621,8 +626,8 @@ HAL_StatusTypeDef status = HAL_OK; /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * + * @brief IO operation functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -664,11 +669,13 @@ HAL_StatusTypeDef status = HAL_OK; * conversion mode is selected, or configure * the color value if Register-to-Memory mode is selected. * @param DstAddress The destination memory Buffer address. - * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Width The width of data to be transferred from source + * to destination (expressed in number of pixels per line). * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height) { /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); @@ -698,11 +705,13 @@ HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, u * conversion mode is selected, or configure * the color value if Register-to-Memory mode is selected. * @param DstAddress The destination memory Buffer address. - * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Width The width of data to be transferred from source + * to destination (expressed in number of pixels per line). * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height) { /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); @@ -718,7 +727,7 @@ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); /* Enable the transfer complete, transfer error and configuration error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE); /* Enable the Peripheral */ __HAL_DMA2D_ENABLE(hdma2d); @@ -733,11 +742,13 @@ HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata * @param SrcAddress1 The source memory Buffer address for the foreground layer. * @param SrcAddress2 The source memory Buffer address for the background layer. * @param DstAddress The destination memory Buffer address. - * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Width The width of data to be transferred from source + * to destination (expressed in number of pixels per line). * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) +HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, + uint32_t DstAddress, uint32_t Width, uint32_t Height) { /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); @@ -749,7 +760,7 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) + if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) { /*blending & fixed FG*/ WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1); @@ -765,11 +776,11 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t } else { - /* Configure DMA2D Stream source2 address */ - WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); + /* Configure DMA2D Stream source2 address */ + WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); - /* Configure the source, destination address and the data size */ - DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); + /* Configure the source, destination address and the data size */ + DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); } /* Enable the Peripheral */ @@ -785,11 +796,13 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t * @param SrcAddress1 The source memory Buffer address for the foreground layer. * @param SrcAddress2 The source memory Buffer address for the background layer. * @param DstAddress The destination memory Buffer address. - * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line). + * @param Width The width of data to be transferred from source + * to destination (expressed in number of pixels per line). * @param Height The height of data to be transferred from source to destination (expressed in number of lines). * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height) +HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, + uint32_t DstAddress, uint32_t Width, uint32_t Height) { /* Check the parameters */ assert_param(IS_DMA2D_LINE(Height)); @@ -801,7 +814,7 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32 /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) + if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) { /*blending & fixed FG*/ WRITE_REG(hdma2d->Instance->FGCOLR, SrcAddress1); @@ -824,7 +837,7 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32 } /* Enable the transfer complete, transfer error and configuration error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE); /* Enable the Peripheral */ __HAL_DMA2D_ENABLE(hdma2d); @@ -846,15 +859,15 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) /* START bit is reset to make sure not to set it again, in the event the HW clears it between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue) */ - MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT); + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT); /* Get tick */ tickstart = HAL_GetTick(); /* Check if the DMA2D is effectively disabled */ - while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) { - if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) + if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; @@ -870,7 +883,7 @@ HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) } /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE); + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE); /* Change the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; @@ -895,7 +908,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) /* START bit is reset to make sure not to set it again, in the event the HW clears it between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ - MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP); + MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP); /* Get tick */ tickstart = HAL_GetTick(); @@ -903,7 +916,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) /* Check if the DMA2D is effectively suspended */ while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START) { - if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) + if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; @@ -915,7 +928,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) } } - /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) { hdma2d->State = HAL_DMA2D_STATE_SUSPEND; @@ -923,7 +936,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) else { /* Make sure SUSP bit is cleared since it is meaningless - when no tranfer is on-going */ + when no transfer is on-going */ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); } @@ -939,7 +952,7 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) { /* Check the SUSP and START bits */ - if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START)) + if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START)) { /* Ongoing transfer is suspended: change the DMA2D state before resuming */ hdma2d->State = HAL_DMA2D_STATE_BUSY; @@ -949,7 +962,7 @@ HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) /* START bit is reset to make sure not to set it again, in the event the HW clears it between the register read and the register write by the CPU (writing 0 has no effect on START bitvalue). */ - CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START)); + CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START)); return HAL_OK; } @@ -975,7 +988,7 @@ HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t Lay /* Change DMA2D peripheral state */ hdma2d->State = HAL_DMA2D_STATE_BUSY; - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Enable the background CLUT loading */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -1014,14 +1027,14 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLU hdma2d->State = HAL_DMA2D_STATE_BUSY; /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT); /* Write background CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); /* Enable the CLUT loading for the background */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -1034,9 +1047,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLU /* Write foreground CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); - /* Enable the CLUT loading for the foreground */ + /* Enable the CLUT loading for the foreground */ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); } @@ -1054,7 +1067,8 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLU * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) * @retval HAL status */ -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); @@ -1068,17 +1082,17 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_ hdma2d->State = HAL_DMA2D_STATE_BUSY; /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT); /* Write background CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); /* Enable the CLUT loading for the background */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -1091,10 +1105,10 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_ /* Write foreground CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); /* Enable the CLUT loading for the foreground */ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); @@ -1131,14 +1145,14 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT hdma2d->State = HAL_DMA2D_STATE_BUSY; /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); /* Write background CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); /* Enable the CLUT loading for the background */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -1151,9 +1165,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgT /* Write foreground CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); - /* Enable the CLUT loading for the foreground */ + /* Enable the CLUT loading for the foreground */ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); } @@ -1188,17 +1202,17 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC hdma2d->State = HAL_DMA2D_STATE_BUSY; /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); /* Write background CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); /* Enable the CLUT loading for the background */ SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); @@ -1211,10 +1225,10 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC /* Write foreground CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); /* Enable the CLUT loading for the foreground */ SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); @@ -1235,13 +1249,13 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTC HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { uint32_t tickstart; - const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ + const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ /* Abort the CLUT loading */ SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT); /* If foreground CLUT loading is considered, update local variables */ - if(LayerIdx == DMA2D_FOREGROUND_LAYER) + if (LayerIdx == DMA2D_FOREGROUND_LAYER) { reg = &(hdma2d->Instance->FGPFCCR); } @@ -1251,9 +1265,9 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint3 tickstart = HAL_GetTick(); /* Check if the CLUT loading is aborted */ - while((*reg & DMA2D_BGPFCCR_START) != 0U) + while ((*reg & DMA2D_BGPFCCR_START) != 0U) { - if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT) + if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; @@ -1269,7 +1283,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint3 } /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE); + __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); /* Change the DMA2D state*/ hdma2d->State = HAL_DMA2D_STATE_READY; @@ -1293,13 +1307,13 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin { uint32_t tickstart; uint32_t loadsuspended; - const __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ + const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ /* Suspend the CLUT loading */ SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); /* If foreground CLUT loading is considered, update local variables */ - if(LayerIdx == DMA2D_FOREGROUND_LAYER) + if (LayerIdx == DMA2D_FOREGROUND_LAYER) { reg = &(hdma2d->Instance->FGPFCCR); } @@ -1308,11 +1322,13 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin tickstart = HAL_GetTick(); /* Check if the CLUT loading is suspended */ - loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/ - loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */ + /* 1st condition: Suspend Check */ + loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL; + /* 2nd condition: Not Start Check */ + loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL; while (loadsuspended == 0UL) { - if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND) + if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; @@ -1322,11 +1338,13 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin return HAL_TIMEOUT; } - loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/ - loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */ + /* 1st condition: Suspend Check */ + loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL; + /* 2nd condition: Not Start Check */ + loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL; } - /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ + /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ if ((*reg & DMA2D_BGPFCCR_START) != 0U) { hdma2d->State = HAL_DMA2D_STATE_SUSPEND; @@ -1334,7 +1352,7 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin else { /* Make sure SUSP bit is cleared since it is meaningless - when no tranfer is on-going */ + when no transfer is on-going */ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); } @@ -1353,18 +1371,18 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uin HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { /* Check the SUSP and START bits for background or foreground CLUT loading */ - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Background CLUT loading suspension check */ if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) { - if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) + if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) { - /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; + /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } } } - } else { /* Foreground CLUT loading suspension check */ @@ -1372,11 +1390,11 @@ HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint { if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) { - /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; + /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ + hdma2d->State = HAL_DMA2D_STATE_BUSY; + } } } - } /* Resume the CLUT loading */ CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); @@ -1400,15 +1418,15 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ __IO uint32_t isrflags = 0x0U; /* Polling for DMA2D transfer */ - if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) + if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) { - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); - while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U) + while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U) { isrflags = READ_REG(hdma2d->Instance->ISR); - if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U) + if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U) { if ((isrflags & DMA2D_FLAG_CE) != 0U) { @@ -1430,9 +1448,9 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ return HAL_ERROR; } /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; @@ -1456,10 +1474,10 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ /* Get tick */ tickstart = HAL_GetTick(); - while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U) + while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U) { isrflags = READ_REG(hdma2d->Instance->ISR); - if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U) + if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U) { if ((isrflags & DMA2D_FLAG_CAE) != 0U) { @@ -1477,7 +1495,7 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE); /* Change DMA2D state */ - hdma2d->State= HAL_DMA2D_STATE_ERROR; + hdma2d->State = HAL_DMA2D_STATE_ERROR; /* Process unlocked */ __HAL_UNLOCK(hdma2d); @@ -1485,15 +1503,15 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ return HAL_ERROR; } /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Update error code */ hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; /* Change the DMA2D state */ - hdma2d->State= HAL_DMA2D_STATE_TIMEOUT; + hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; /* Process unlocked */ __HAL_UNLOCK(hdma2d); @@ -1505,7 +1523,7 @@ HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_ } /* Clear the transfer complete and CLUT loading flags */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC); + __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC); /* Change DMA2D state */ hdma2d->State = HAL_DMA2D_STATE_READY; @@ -1546,7 +1564,7 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) /* Process Unlocked */ __HAL_UNLOCK(hdma2d); - if(hdma2d->XferErrorCallback != NULL) + if (hdma2d->XferErrorCallback != NULL) { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); @@ -1573,7 +1591,7 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) /* Process Unlocked */ __HAL_UNLOCK(hdma2d); - if(hdma2d->XferErrorCallback != NULL) + if (hdma2d->XferErrorCallback != NULL) { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); @@ -1600,7 +1618,7 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) /* Process Unlocked */ __HAL_UNLOCK(hdma2d); - if(hdma2d->XferErrorCallback != NULL) + if (hdma2d->XferErrorCallback != NULL) { /* Transfer error Callback */ hdma2d->XferErrorCallback(hdma2d); @@ -1647,7 +1665,7 @@ void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) /* Process Unlocked */ __HAL_UNLOCK(hdma2d); - if(hdma2d->XferCpltCallback != NULL) + if (hdma2d->XferCpltCallback != NULL) { /* Transfer complete Callback */ hdma2d->XferCpltCallback(hdma2d); @@ -1722,8 +1740,8 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) */ /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * + * @brief Peripheral Control functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -1753,15 +1771,16 @@ __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) { DMA2D_LayerCfgTypeDef *pLayerCfg; - uint32_t regMask, regValue; + uint32_t regMask; + uint32_t regValue; /* Check the parameters */ assert_param(IS_DMA2D_LAYER(LayerIdx)); assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset)); - if(hdma2d->Init.Mode != DMA2D_R2M) + if (hdma2d->Init.Mode != DMA2D_R2M) { assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode)); - if(hdma2d->Init.Mode != DMA2D_M2M) + if (hdma2d->Init.Mode != DMA2D_M2M) { assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode)); } @@ -1769,7 +1788,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted)); assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap)); - if((LayerIdx == DMA2D_FOREGROUND_LAYER) && (hdma2d->LayerCfg[LayerIdx].InputColorMode == DMA2D_INPUT_YCBCR)) + if ((LayerIdx == DMA2D_FOREGROUND_LAYER) && (hdma2d->LayerCfg[LayerIdx].InputColorMode == DMA2D_INPUT_YCBCR)) { assert_param(IS_DMA2D_CHROMA_SUB_SAMPLING(hdma2d->LayerCfg[LayerIdx].ChromaSubSampling)); } @@ -1783,7 +1802,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */ - regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\ + regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) | \ (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos); regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS); @@ -1794,11 +1813,11 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La } else { - regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos); + regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos); } /* Configure the background DMA2D layer */ - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write DMA2D BGPFCCR register */ MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); @@ -1809,20 +1828,21 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La /* DMA2D BGCOLR register configuration -------------------------------------*/ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) { - WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED)); + WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \ + DMA2D_BGCOLR_RED)); } } /* Configure the foreground DMA2D layer */ else { - if(pLayerCfg->InputColorMode == DMA2D_INPUT_YCBCR) + if (pLayerCfg->InputColorMode == DMA2D_INPUT_YCBCR) { regValue |= (pLayerCfg->ChromaSubSampling << DMA2D_FGPFCCR_CSS_Pos); regMask |= DMA2D_FGPFCCR_CSS; } - /* Write DMA2D FGPFCCR register */ + /* Write DMA2D FGPFCCR register */ MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); /* DMA2D FGOR register configuration -------------------------------------*/ @@ -1831,7 +1851,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La /* DMA2D FGCOLR register configuration -------------------------------------*/ if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) { - WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED)); + WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \ + DMA2D_FGCOLR_RED)); } } /* Initialize the DMA2D state*/ @@ -1871,24 +1892,24 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCf hdma2d->State = HAL_DMA2D_STATE_BUSY; /* Configure the CLUT of the background DMA2D layer */ - if(LayerIdx == DMA2D_BACKGROUND_LAYER) + if (LayerIdx == DMA2D_BACKGROUND_LAYER) { /* Write background CLUT memory address */ WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); /* Write background CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); - } - /* Configure the CLUT of the foreground DMA2D layer */ - else - { - /* Write foreground CLUT memory address */ + ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); + } + /* Configure the CLUT of the foreground DMA2D layer */ + else + { + /* Write foreground CLUT memory address */ WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); /* Write foreground CLUT size and CLUT color mode */ MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); + ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); } /* Set the DMA2D state to Ready*/ @@ -1914,8 +1935,6 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCf HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line) { /* Check the parameters */ - assert_param(IS_DMA2D_LINEWATERMARK(Line)); - if (Line > DMA2D_LWR_LW) { return HAL_ERROR; @@ -2022,8 +2041,8 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### @@ -2082,7 +2101,8 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) * @param Height The height of data to be transferred from source to destination. * @retval HAL status */ -static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height) +static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height) { uint32_t tmp; uint32_t tmp1; @@ -2091,7 +2111,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ uint32_t tmp4; /* Configure DMA2D data size */ - MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos))); + MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos))); /* Configure DMA2D destination address */ WRITE_REG(hdma2d->Instance->OMAR, DstAddress); @@ -2107,7 +2127,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ /* Prepare the value to be written to the OCOLR register according to the color mode */ if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888) { - tmp = (tmp3 | tmp2 | tmp1| tmp4); + tmp = (tmp3 | tmp2 | tmp1 | tmp4); } else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888) { @@ -2117,7 +2137,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ { tmp2 = (tmp2 >> 19U); tmp3 = (tmp3 >> 10U); - tmp4 = (tmp4 >> 3U ); + tmp4 = (tmp4 >> 3U); tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4); } else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555) @@ -2125,7 +2145,7 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ tmp1 = (tmp1 >> 31U); tmp2 = (tmp2 >> 19U); tmp3 = (tmp3 >> 11U); - tmp4 = (tmp4 >> 3U ); + tmp4 = (tmp4 >> 3U); tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4); } else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */ @@ -2133,15 +2153,15 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ tmp1 = (tmp1 >> 28U); tmp2 = (tmp2 >> 20U); tmp3 = (tmp3 >> 12U); - tmp4 = (tmp4 >> 4U ); + tmp4 = (tmp4 >> 4U); tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4); } /* Write to DMA2D OCOLR register */ WRITE_REG(hdma2d->Instance->OCOLR, tmp); } - else if(hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/ + else if (hdma2d->Init.Mode == DMA2D_M2M_BLEND_FG) /*M2M_blending with fixed color FG DMA2D Mode selected*/ { - WRITE_REG(hdma2d->Instance->BGMAR , pdata); + WRITE_REG(hdma2d->Instance->BGMAR, pdata); } else /* M2M, M2M_PFC,M2M_Blending or M2M_blending with fixed color BG DMA2D Mode */ { diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.h index ba16bef528..d5acb3f5fa 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dma2d.h @@ -22,7 +22,7 @@ #define STM32H7xx_HAL_DMA2D_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -71,7 +71,8 @@ typedef struct This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ uint32_t OutputOffset; /*!< Specifies the Offset value. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x3FFF. */ uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ @@ -95,7 +96,8 @@ typedef struct typedef struct { uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x3FFF. */ uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ @@ -103,9 +105,12 @@ typedef struct uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. This parameter can be one value of @ref DMA2D_Alpha_Mode. */ - uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. - @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between + uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value + in case of A8 or A4 color mode. + This parameter must be a number between Min_Data = 0x00 + and Max_Data = 0xFF except for the color modes detailed below. + @note In case of A8 or A4 color mode (ARGB), + this parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where - InputAlpha[24:31] is the alpha value ALPHA[0:7] - InputAlpha[16:23] is the red value RED[0:7] @@ -133,46 +138,46 @@ typedef enum HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ -}HAL_DMA2D_StateTypeDef; +} HAL_DMA2D_StateTypeDef; /** * @brief DMA2D handle Structure definition */ typedef struct __DMA2D_HandleTypeDef { - DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ + DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ - DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ + DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ - void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ + void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ - void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ + void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) - void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */ + void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ - void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */ + void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ - void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */ + void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ - void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */ + void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ - DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ + DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ - HAL_LockTypeDef Lock; /*!< DMA2D lock. */ + HAL_LockTypeDef Lock; /*!< DMA2D lock. */ - __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ + __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ - __IO uint32_t ErrorCode; /*!< DMA2D error code. */ + __IO uint32_t ErrorCode; /*!< DMA2D error code. */ } DMA2D_HandleTypeDef; #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) /** * @brief HAL DMA2D Callback pointer definition */ -typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */ +typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ /** * @} @@ -246,10 +251,10 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode * @{ */ -#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ +#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value - with original alpha channel value */ + with original alpha channel value */ /** * @} */ @@ -340,7 +345,8 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin /** @defgroup DMA2D_Aliases DMA2D API Aliases * @{ */ -#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ /** * @} */ @@ -357,7 +363,7 @@ typedef enum HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ -}HAL_DMA2D_CallbackIDTypeDef; +} HAL_DMA2D_CallbackIDTypeDef; #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ @@ -374,10 +380,10 @@ typedef enum * @retval None */ #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) -#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ +#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ }while(0) #else #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) @@ -483,12 +489,13 @@ typedef enum /* Initialization and de-initialization functions *******************************/ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); -HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); -void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); -void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); +HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); +void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, + pDMA2D_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ @@ -502,16 +509,22 @@ HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_ */ /* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); -HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); -HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); -HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, + uint32_t DstAddress, uint32_t Width, uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, + uint32_t Height); +HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, + uint32_t DstAddress, uint32_t Width, uint32_t Height); HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, + uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); @@ -631,14 +644,17 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); /** @defgroup DMA2D_Private_Macros DMA2D Private Macros * @{ */ -#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER)) +#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ + || ((LAYER) == DMA2D_FOREGROUND_LAYER)) #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) -#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ - ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ +#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ + ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) @@ -646,12 +662,18 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) -#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ - ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ - ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ - ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ - ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ - ((INPUT_CM) == DMA2D_INPUT_A4) || ((INPUT_CM) == DMA2D_INPUT_YCBCR)) +#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ + ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ + ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ + ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ + ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ + ((INPUT_CM) == DMA2D_INPUT_L8) || \ + ((INPUT_CM) == DMA2D_INPUT_AL44) || \ + ((INPUT_CM) == DMA2D_INPUT_AL88) || \ + ((INPUT_CM) == DMA2D_INPUT_L4) || \ + ((INPUT_CM) == DMA2D_INPUT_A8) || \ + ((INPUT_CM) == DMA2D_INPUT_A4) || \ + ((INPUT_CM) == DMA2D_INPUT_YCBCR)) #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ @@ -677,11 +699,11 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ - ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ - ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) + ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ + ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ - ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ - ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) + ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ + ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.c index 6b93e38d1a..073c2a6e4c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.c @@ -13,36 +13,57 @@ ============================================================================== ##### How to use this driver ##### ============================================================================== + [..] + The DSI HAL driver can be used as follows: + + (#) Declare a DSI_HandleTypeDef handle structure, for example: DSI_HandleTypeDef hdsi; + + (#) Initialize the DSI low level resources by implementing the HAL_DSI_MspInit() API: + (##) Enable the DSI interface clock + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the DSI interrupt priority + (+++) Enable the NVIC DSI IRQ Channel + + (#) Initialize the DSI Host peripheral, the required PLL parameters, number of lances and + TX Escape clock divider by calling the HAL_DSI_Init() API which calls HAL_DSI_MspInit(). + + *** Configuration *** + ========================= [..] - (#) Use @ref HAL_DSI_Init() function to initialize the DSI Host IP and program the required - PLL parameters, number of lanes and TX Escape clock divider. - (#) Use @ref HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted + (#) Use HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted command mode. - (#) When operating in video mode , use @ref HAL_DSI_ConfigVideoMode() to configure the DSI host. - (#) Function @ref HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode. - (#) To configure the DSI PHY timings parameters, use function @ref HAL_DSI_ConfigPhyTimer(). - (#) The DSI Host can be started/stopped using respectively functions @ref HAL_DSI_Start() and @ref HAL_DSI_Stop(). - Functions @ref HAL_DSI_ShortWrite(), @ref HAL_DSI_LongWrite() and @ref HAL_DSI_Read() allows respectively + + (#) When operating in video mode , use HAL_DSI_ConfigVideoMode() to configure the DSI host. + + (#) Function HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode. + + (#) To configure the DSI PHY timings parameters, use function HAL_DSI_ConfigPhyTimer(). + + (#) The DSI Host can be started/stopped using respectively functions HAL_DSI_Start() and HAL_DSI_Stop(). + Functions HAL_DSI_ShortWrite(), HAL_DSI_LongWrite() and HAL_DSI_Read() allows respectively to write DSI short packets, long packets and to read DSI packets. (#) The DSI Host Offers two Low power modes : - (+) Low Power Mode on data lanes only: Only DSI data lanes are shut down. - It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPMData() - and @ref HAL_DSI_ExitULPMData() + (++) Low Power Mode on data lanes only: Only DSI data lanes are shut down. + It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPMData() + and HAL_DSI_ExitULPMData() - (+) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes. - It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPM() - and @ref HAL_DSI_ExitULPM() - - (#) User can select the DSI errors to be reported/monitored using function @ref HAL_DSI_ConfigErrorMonitor() - When an error occurs, the callback @ref HAL_DSI_ErrorCallback() is asserted and then user can retrieve - the error code by calling function @ref HAL_DSI_GetError() + (++) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes. + It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPM() + and HAL_DSI_ExitULPM() (#) To control DSI state you can use the following function: HAL_DSI_GetState() - *** DSI HAL driver macros list *** - ============================================= - [..] + *** Error management *** + ======================== + [..] + (#) User can select the DSI errors to be reported/monitored using function HAL_DSI_ConfigErrorMonitor() + When an error occurs, the callback HAL_DSI_ErrorCallback() is asserted and then user can retrieve + the error code by calling function HAL_DSI_GetError() + + *** DSI HAL driver macros list *** + ============================================= + [..] Below the list of most used macros in DSI HAL driver. (+) __HAL_DSI_ENABLE: Enable the DSI Host. @@ -59,58 +80,63 @@ (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts. (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not. + [..] + (@) You can refer to the DSI HAL driver header file for more useful macros + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_DSI_RegisterCallback() to register a callback. - *** Callback registration *** - ============================================= + [..] + Function HAL_DSI_RegisterCallback() allows to register following callbacks: + (+) TearingEffectCallback : DSI Tearing Effect Callback. + (+) EndOfRefreshCallback : DSI End Of Refresh Callback. + (+) ErrorCallback : DSI Error Callback + (+) MspInitCallback : DSI MspInit. + (+) MspDeInitCallback : DSI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the callback ID + and a pointer to the user callback function. - The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_DSI_RegisterCallback() to register a callback. + [..] + Use function HAL_DSI_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the callback ID. + [..] + This function allows to reset following callbacks: + (+) TearingEffectCallback : DSI Tearing Effect Callback. + (+) EndOfRefreshCallback : DSI End Of Refresh Callback. + (+) ErrorCallback : DSI Error Callback + (+) MspInitCallback : DSI MspInit. + (+) MspDeInitCallback : DSI MspDeInit. - Function @ref HAL_DSI_RegisterCallback() allows to register following callbacks: - (+) TearingEffectCallback : DSI Tearing Effect Callback. - (+) EndOfRefreshCallback : DSI End Of Refresh Callback. - (+) ErrorCallback : DSI Error Callback - (+) MspInitCallback : DSI MspInit. - (+) MspDeInitCallback : DSI MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. + [..] + By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak (surcharged) functions in the HAL_DSI_Init() + and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - Use function @ref HAL_DSI_UnRegisterCallback() to reset a callback to the default - weak function. - @ref HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TearingEffectCallback : DSI Tearing Effect Callback. - (+) EndOfRefreshCallback : DSI End Of Refresh Callback. - (+) ErrorCallback : DSI Error Callback - (+) MspInitCallback : DSI MspInit. - (+) MspDeInitCallback : DSI MspDeInit. + [..] + Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_DSI_RegisterCallback() before calling HAL_DSI_DeInit() + or HAL_DSI_Init() function. - By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples @ref HAL_DSI_TearingEffectCallback(), @ref HAL_DSI_EndOfRefreshCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_DSI_Init/ @ref HAL_DSI_DeInit only when - these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_DSI_Init/ @ref HAL_DSI_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_DSI_RegisterCallback() before calling @ref HAL_DSI_DeInit - or HAL_DSI_Init function. - - When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - [..] - (@) You can refer to the DSI HAL driver header file for more useful macros + [..] + When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. @endverbatim ****************************************************************************** @@ -2263,7 +2289,7 @@ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) * @brief Custom lane pins configuration * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CustomLane Function to be applyed on selected lane. + * @param CustomLane Function to be applied on selected lane. * This parameter can be any value of @arg DSI_CustomLane * @param Lane select between clock or data lane 0 or data lane 1. * This parameter can be any value of @arg DSI_Lane_Select diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.h index a3894ec4e3..06d9ae5938 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_dsi.h @@ -25,10 +25,11 @@ extern "C" { #endif -#if defined(DSI) /* Includes ------------------------------------------------------------------*/ #include "stm32h7xx_hal_def.h" +#if defined(DSI) + /** @addtogroup STM32H7xx_HAL_Driver * @{ */ @@ -922,7 +923,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to /** * @brief Reset DSI handle state. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None */ #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.c index 033739e883..decff79455 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.c @@ -902,7 +902,7 @@ HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) /* Set the ETH peripheral state to BUSY */ heth->gState = HAL_ETH_STATE_BUSY; - /* Disable intrrupts: + /* Disable interrupts: - Tx complete interrupt - Rx complete interrupt - Fatal bus interrupt @@ -986,7 +986,7 @@ HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig * tickstart = HAL_GetTick(); - /* Wait for data to be transmitted or timeout occured */ + /* Wait for data to be transmitted or timeout occurred */ while((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)RESET) { if((heth->Instance->DMACSR & ETH_DMACSR_FBE) != (uint32_t)RESET) @@ -1232,7 +1232,7 @@ HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTyp } } - /* Get intermediate descriptors buffers: in case of the Packet is splitted into multi descriptors */ + /* Get intermediate descriptors buffers: in case of the Packet is split into multi descriptors */ for(index = 0; index < (dmarxdesclist->AppDescNbr - 1U); index++) { /* Get Address and length of the first buffer address */ @@ -1519,7 +1519,7 @@ void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) { heth->ErrorCode |= HAL_ETH_ERROR_DMA; - /* if fatal bus error occured */ + /* if fatal bus error occurred */ if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMACSR_FBE)) { /* Get DMA error code */ @@ -2242,7 +2242,7 @@ void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBit * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure - * that contains the Power Down configration + * that contains the Power Down configuration * @retval None. */ void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig) @@ -2702,7 +2702,7 @@ static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) WRITE_REG(dmarxdesc->BackupAddr0, 0x0); WRITE_REG(dmarxdesc->BackupAddr1, 0x0); - /* Set Rx descritors adresses */ + /* Set Rx descritors addresses */ WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); } @@ -2740,9 +2740,10 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer; + uint32_t bd_count = 0; /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ - if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) + if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL)) { return HAL_ETH_ERROR_BUSY; } @@ -2778,7 +2779,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket } } - /* if tcp segementation is enabled for this packet */ + /* if tcp segmentation is enabled for this packet */ if(READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != 0U) { /* Set MSS value */ @@ -2880,7 +2881,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl); } - /* only if the packet is splitted into more than one descriptors > 1 */ + /* only if the packet is split into more than one descriptors > 1 */ while (txbuffer->next != NULL) { /* Clear the LD bit of previous descriptor */ @@ -2894,7 +2895,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD); /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ - if(READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) + if((READ_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) || (dmatxdesclist->PacketAddress[descidx] != NULL)) { descidx = firstdescidx; dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; @@ -2958,6 +2959,7 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket } } + bd_count += 1U; /* Set Own bit */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); /* Mark it as NORMAL descriptor */ @@ -2966,20 +2968,31 @@ static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacket if(ItMode != ((uint32_t)RESET)) { - /* Set Interrupt on completition bit */ + /* Set Interrupt on completion bit */ SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC); } else { - /* Clear Interrupt on completition bit */ + /* Clear Interrupt on completion bit */ CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC); } /* Mark it as LAST descriptor */ SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD); + /* Save the current packet address to expose it to the application */ + dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress; dmatxdesclist->CurTxDesc = descidx; + /* disable the interrupt */ + __disable_irq(); + + dmatxdesclist->BuffersInUse += bd_count + 1U; + + /* Enable interrupts back */ + __enable_irq(); + + /* Return function status */ return HAL_ETH_ERROR_NONE; } diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.h index 039dc6641f..354ce3f5f8 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_eth.h @@ -89,10 +89,15 @@ typedef struct __ETH_BufferTypeDef */ typedef struct { - uint32_t TxDesc[ETH_TX_DESC_CNT]; /*Instance->TXBRP & BufferIndex) != 0U) { /* Update error code */ @@ -3311,7 +3311,7 @@ uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint3 */ uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex) { - /* Check pending transmittion request on the selected buffer */ + /* Check pending transmission request on the selected buffer */ if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U) { return 0; @@ -5059,14 +5059,14 @@ HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, ui if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U) { /* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register, - but interrupt will only occure if TC is enabled in IE register */ + but interrupt will only occur if TC is enabled in IE register */ SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes); } if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U) { /* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register, - but interrupt will only occure if TCF is enabled in IE register */ + but interrupt will only occur if TCF is enabled in IE register */ SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes); } diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.c index 6383da56e1..a73e8ed02e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash.c @@ -134,11 +134,16 @@ FLASH_ProcessTypeDef pFlash; */ /** - * @brief Program flash word at a specified address + * @brief Program a flash word at a specified address * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param FlashAddress specifies the address to be programmed. - * @param DataAddress specifies the address of data to be programmed + * This parameter shall be aligned to the Flash word: + * - 256 bits for STM32H74x/5X devices (8x 32bits words) + * - 128 bits for STM32H7Ax/BX devices (4x 32bits words) + * - 256 bits for STM32H72x/3X devices (8x 32bits words) + * @param DataAddress specifies the address of data to be programmed. + * This parameter shall be 32-bit aligned * * @retval HAL_StatusTypeDef HAL Status */ @@ -292,11 +297,16 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, } /** - * @brief Program flash words of 256 bits at a specified address with interrupt enabled. + * @brief Program a flash word at a specified address with interrupt enabled. * @param TypeProgram Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param FlashAddress specifies the address to be programmed. - * @param DataAddress specifies the address of data (256 bits) to be programmed + * This parameter shall be aligned to the Flash word: + * - 256 bits for STM32H74x/5X devices (8x 32bits words) + * - 128 bits for STM32H7Ax/BX devices (4x 32bits words) + * - 256 bits for STM32H72x/3X devices (8x 32bits words) + * @param DataAddress specifies the address of data to be programmed. + * This parameter shall be 32-bit aligned * * @retval HAL Status */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.c index dc45d4a190..d0219243d8 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.c @@ -22,7 +22,7 @@ (+) Global readout protection (RDP) (+) Write protection (+) Secure access only protection - (+) Bank / register swapping + (+) Bank / register swapping (when Dual-Bank) (+) Cyclic Redundancy Check (CRC) ##### How to use this driver ##### @@ -1813,7 +1813,7 @@ static void FLASH_OB_SharedRAM_Config(uint32_t SharedRamConfig) } /** - * @brief Get the TCM / AXI Shared RAM configurtion. + * @brief Get the TCM / AXI Shared RAM configuration. * @retval SharedRamConfig returns the TCM / AXI Shared RAM configuration. * This return value can be a value of @ref FLASHEx_OB_TCM_AXI_SHARED */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.h index 3c4c81a575..96119b9c86 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_flash_ex.h @@ -1,6 +1,6 @@ /** ****************************************************************************** - * @file stm32H7xx_hal_flash_ex.h + * @file stm32h7xx_hal_flash_ex.h * @author MCD Application Team * @brief Header file of FLASH HAL module. ****************************************************************************** @@ -276,16 +276,6 @@ typedef struct * @} */ -/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog - * @{ - */ -#define OB_WWDG_SW 0x10U /*!< Software WWDG selected */ -#define OB_WWDG_HW 0x00U /*!< Hardware WWDG selected */ -/** - * @} - */ - - /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog * @{ */ @@ -556,6 +546,7 @@ typedef struct */ #endif /* FLASH_OPTSR_NRST_STOP_D2 */ +#if defined (DUAL_BANK) /** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK * @{ */ @@ -564,6 +555,7 @@ typedef struct /** * @} */ +#endif /* DUAL_BANK */ /** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV * @{ @@ -643,19 +635,32 @@ typedef struct OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\ OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) #elif defined (FLASH_OPTSR_VDDMMC_HSLV) +#if defined (DUAL_BANK) #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\ OB_USER_VDDMMC_HSLV) +#else +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV |\ + OB_USER_VDDMMC_HSLV) +#endif /* DUAL_BANK */ #elif defined (FLASH_OPTSR2_TCM_AXI_SHARED) #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ OB_USER_SECURITY | OB_USER_IOHSLV |\ OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2) -#else +#else /* Single core */ +#if defined (DUAL_BANK) #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK ) +#else +#define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\ + OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\ + OB_USER_SECURITY | OB_USER_IOHSLV ) +#endif /* DUAL_BANK */ #endif /* DUAL_CORE */ /** * @} @@ -745,10 +750,10 @@ typedef struct * @{ */ /** - * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1) + * @brief Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1) * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) - * @retval The FLASH Boot Base Adress + * @retval The FLASH Boot Base Address */ #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U) /** @@ -866,8 +871,6 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ ((LEVEL) == OB_RDP_LEVEL_1) ||\ ((LEVEL) == OB_RDP_LEVEL_2)) -#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW)) - #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) @@ -912,7 +915,9 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_ #define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \ ((CONFIG) == OB_SECURE_RDP_ERASE)) +#if defined (DUAL_BANK) #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) +#endif /* DUAL_BANK */ #define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE)) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.c index d1bdcbd62f..bed9b624dd 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.c @@ -7,7 +7,7 @@ * + Initialization and De-initialization. * + LUT configuration. * + Force flush and/or invalidate of cache. - * + Modify physical buffer adresses. + * + Modify physical buffer addresses. * + Modify cache and pre-fetch parameters. * + Error management. * @@ -40,7 +40,7 @@ [..] (#) Use HAL_GFXMMU_ConfigForceCache() to flush and/or invalidate cache. - *** Modify physical buffer adresses *** + *** Modify physical buffer addresses *** ======================================= [..] (#) Use HAL_GFXMMU_ModifyBuffers() to modify physical buffer addresses. @@ -250,7 +250,7 @@ HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu) /* Configure default value on GFXMMU_DVR register */ hgfxmmu->Instance->DVR = hgfxmmu->Init.DefaultValue; - /* Configure physical buffer adresses on GFXMMU_BxCR registers */ + /* Configure physical buffer addresses on GFXMMU_BxCR registers */ hgfxmmu->Instance->B0CR = hgfxmmu->Init.Buffers.Buf0Address; hgfxmmu->Instance->B1CR = hgfxmmu->Init.Buffers.Buf1Address; hgfxmmu->Instance->B2CR = hgfxmmu->Init.Buffers.Buf2Address; @@ -501,7 +501,7 @@ HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef *hgf [..] This section provides functions allowing to: (+) Configure LUT. (+) Force flush and/or invalidate of cache. - (+) Modify physical buffer adresses. + (+) Modify physical buffer addresses. (+) Modify cache and pre-fetch parameters. (+) Manage error. @endverbatim @@ -713,7 +713,7 @@ HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU } else { - /* Modify physical buffer adresses on GFXMMU_BxCR registers */ + /* Modify physical buffer addresses on GFXMMU_BxCR registers */ hgfxmmu->Instance->B0CR = Buffers->Buf0Address; hgfxmmu->Instance->B1CR = Buffers->Buf1Address; hgfxmmu->Instance->B2CR = Buffers->Buf2Address; diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.h index 740f8082be..8248bede25 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gfxmmu.h @@ -69,15 +69,15 @@ typedef struct typedef struct { FunctionalState Activation; /*!< Cache and pre-fetch enable/disable. - @note: All following parameters are usefull only if cache and pre-fetch are enabled. */ + @note: All following parameters are useful only if cache and pre-fetch are enabled. */ uint32_t CacheLock; /*!< Locking the cache to a buffer. This parameter can be a value of @ref GFXMMU_CacheLock. */ uint32_t CacheLockBuffer; /*!< Buffer on which the cache is locked. This parameter can be a value of @ref GFXMMU_CacheLockBuffer. - @note: Usefull only when lock of the cache is enabled. */ + @note: Useful only when lock of the cache is enabled. */ uint32_t CacheForce; /*!< Forcing the cache regardless MPU attributes. This parameter can be a value of @ref GFXMMU_CacheForce. - @note: Usefull only when lock of the cache is enabled. */ + @note: Useful only when lock of the cache is enabled. */ uint32_t OutterBufferability; /*!< Bufferability of an access generated by the GFXMMU cache. This parameter can be a value of @ref GFXMMU_OutterBufferability. */ uint32_t OutterCachability; /*!< Cachability of an access generated by the GFXMMU cache. @@ -94,7 +94,7 @@ typedef struct FunctionalState Activation; /*!< Interrupts enable/disable */ uint32_t UsedInterrupts; /*!< Interrupts used. This parameter can be a values combination of @ref GFXMMU_Interrupts. - @note: Usefull only when interrupts are enabled. */ + @note: Useful only when interrupts are enabled. */ }GFXMMU_InterruptsTypeDef; /** @@ -214,7 +214,7 @@ typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu); * @} */ -/** @defgroup GFXMMU_OutterBufferability GFXMMU outter bufferability +/** @defgroup GFXMMU_OutterBufferability GFXMMU outer bufferability * @{ */ #define GFXMMU_OUTTER_BUFFERABILITY_DISABLE 0x00000000U /*!< No bufferable */ @@ -223,11 +223,11 @@ typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu); * @} */ -/** @defgroup GFXMMU_OutterCachability GFXMMU outter cachability +/** @defgroup GFXMMU_OutterCachability GFXMMU outer cachability * @{ */ -#define GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U /*!< No cachable */ -#define GFXMMU_OUTTER_CACHABILITY_ENABLE GFXMMU_CR_OC /*!< Cachable */ +#define GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U /*!< No cacheable */ +#define GFXMMU_OUTTER_CACHABILITY_ENABLE GFXMMU_CR_OC /*!< Cacheable */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.c index 25a19dea36..8d0a5f66b2 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_gpio.c @@ -447,17 +447,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin */ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { + uint32_t odr; + /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin) - { - GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; - } - else - { - GPIOx->BSRR = GPIO_Pin; - } + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); } /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.c index e900166e46..bdfea698e3 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash.c @@ -34,7 +34,7 @@ (+++) Associate the initialized DMA handle to the HASH DMA handle using __HAL_LINKDMA() (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the DMA Stream: use + interrupt on the DMA stream: use HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() @@ -71,10 +71,10 @@ well the computed digest. (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. - (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro. - From that point, each buffer can be fed to the Peripheral thru HAL_HASH_xxx_Start_DMA() API. + (+++) HASH processing: once initialization is done, MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro. + From that point, each buffer can be fed to the Peripheral through HAL_HASH_xxx_Start_DMA() API. Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() - macro then wrap-up the HASH processing in feeding the last input buffer thru the + macro then wrap-up the HASH processing in feeding the last input buffer through the same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to API HAL_HASH_xxx_Finish(). (+++) HMAC processing (requires to resort to extended functions): @@ -483,7 +483,7 @@ __weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) * @brief Input data transfer complete call back. * @note HAL_HASH_InCpltCallback() is called when the complete input message * has been fed to the Peripheral. This API is invoked only when input data are - * entered under interruption or thru DMA. + * entered under interruption or through DMA. * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set), * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding * to the Peripheral. @@ -1729,10 +1729,10 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) /* Configure the Number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(buffersize); - /* Set the HASH DMA transfert completion call back */ + /* Set the HASH DMA transfer completion call back */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; - /* Enable the DMA In DMA Stream */ + /* Enable the DMA In DMA stream */ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U))); /* Enable DMA requests */ @@ -2074,7 +2074,7 @@ static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) return HAL_OK; } - /* Enter input data in the Peripheral thru HASH_Write_Block_Data() call and + /* Enter input data in the Peripheral through HASH_Write_Block_Data() call and check whether the digest calculation has been triggered */ if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) { @@ -3006,7 +3006,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED } - /* Set the HASH DMA transfert complete callback */ + /* Set the HASH DMA transfer complete callback */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; /* Set the DMA error callback */ hhash->hdmain->XferErrorCallback = HASH_DMAError; @@ -3014,7 +3014,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /* Store number of words already pushed to manage proper DMA processing suspension */ hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); - /* Enable the DMA In DMA Stream */ + /* Enable the DMA In DMA stream */ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U))); /* Enable DMA requests */ @@ -3395,7 +3395,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED } - /* Set the HASH DMA transfert complete callback */ + /* Set the HASH DMA transfer complete callback */ hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; /* Set the DMA error callback */ hhash->hdmain->XferErrorCallback = HASH_DMAError; @@ -3403,7 +3403,7 @@ if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED /* Store number of words already pushed to manage proper DMA processing suspension */ hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); - /* Enable the DMA In DMA Stream */ + /* Enable the DMA In DMA stream */ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U))); /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.c index 1cf8a5c223..2ddac61211 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hash_ex.c @@ -5,7 +5,7 @@ * @brief Extended HASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the HASH peripheral for SHA-224 and SHA-256 - * alogrithms: + * algorithms: * + HASH or HMAC processing in polling mode * + HASH or HMAC processing in interrupt mode * + HASH or HMAC processing in DMA mode @@ -46,10 +46,10 @@ (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. - (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro. - From that point, each buffer can be fed to the Peripheral thru HAL_HASHEx_xxx_Start_DMA() API. + (+++) HASH processing: once initialization is done, MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro. + From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API. Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() - macro then wrap-up the HASH processing in feeding the last input buffer thru the + macro then wrap-up the HASH processing in feeding the last input buffer through the same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to API HAL_HASHEx_xxx_Finish(). @@ -388,7 +388,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @verbatim =============================================================================== - ##### DMA mode HASH extended processing functionss ##### + ##### DMA mode HASH extended processing functions ##### =============================================================================== [..] This section provides functions allowing to calculate in DMA mode the hash value using one of the following algorithms: diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.c index 45d8061f5b..1e5a89af1a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.c @@ -91,8 +91,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); */ /** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -185,9 +185,9 @@ HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) * This parameter can be a value from 0 to 255 * @param speed Current device speed. * This parameter can be one of these values: - * HCD_SPEED_HIGH: High speed mode, - * HCD_SPEED_FULL: Full speed mode, - * HCD_SPEED_LOW: Low speed mode + * HCD_DEVICE_SPEED_HIGH: High speed mode, + * HCD_DEVICE_SPEED_FULL: Full speed mode, + * HCD_DEVICE_SPEED_LOW: Low speed mode * @param ep_type Endpoint Type. * This parameter can be one of these values: * EP_TYPE_CTRL: Control type, @@ -566,6 +566,16 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); } + /* Handle Rx Queue Level Interrupts */ + if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) + { + USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + HCD_RXQLVL_IRQHandler(hhcd); + + USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + /* Handle Host channel Interrupt */ if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) { @@ -586,19 +596,10 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) } __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); } - - /* Handle Rx Queue Level Interrupts */ - if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) - { - USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - HCD_RXQLVL_IRQHandler(hhcd); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } } } + /** * @brief SOF callback. * @param hhcd HCD handle @@ -718,7 +719,9 @@ __weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -806,7 +809,7 @@ HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_Call /** * @brief Unregister an USB HCD Callback - * USB HCD callabck is redirected to the weak predefined callback + * USB HCD callback is redirected to the weak predefined callback * @param hhcd USB HCD handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -910,7 +913,8 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_Ca * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -945,7 +949,7 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * } /** - * @brief UnRegister the USB HCD Host Channel Notify URB Change Callback + * @brief Unregister the USB HCD Host Channel Notify URB Change Callback * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback * @param hhcd HCD handle * @retval HAL status @@ -982,8 +986,8 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef */ /** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions - * @brief Management functions - * + * @brief Management functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -1041,8 +1045,8 @@ HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) */ /** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -1192,10 +1196,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); hhcd->hc[ch_num].state = HC_DATATGLERR; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) + { + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); } else { @@ -1212,7 +1223,7 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { if (hhcd->Init.dma_enable != 0U) { - hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].xfer_len - \ + hhcd->hc[ch_num].xfer_count = hhcd->hc[ch_num].XferSize - \ (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); } @@ -1253,8 +1264,18 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { /* ... */ } - hhcd->hc[ch_num].toggle_in ^= 1U; + if (hhcd->Init.dma_enable == 1U) + { + if (((hhcd->hc[ch_num].XferSize / hhcd->hc[ch_num].max_packet) & 1U) != 0U) + { + hhcd->hc[ch_num].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[ch_num].toggle_in ^= 1U; + } } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { @@ -1262,17 +1283,17 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->hc[ch_num].state == HC_XFRC) { - hhcd->hc[ch_num].urb_state = URB_DONE; + hhcd->hc[ch_num].urb_state = URB_DONE; } else if (hhcd->hc[ch_num].state == HC_STALL) { - hhcd->hc[ch_num].urb_state = URB_STALL; + hhcd->hc[ch_num].urb_state = URB_STALL; } else if ((hhcd->hc[ch_num].state == HC_XACTERR) || (hhcd->hc[ch_num].state == HC_DATATGLERR)) { hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 3U) + if (hhcd->hc[ch_num].ErrCnt > 2U) { hhcd->hc[ch_num].ErrCnt = 0U; hhcd->hc[ch_num].urb_state = URB_ERROR; @@ -1280,18 +1301,19 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else { hhcd->hc[ch_num].urb_state = URB_NOTREADY; - } - /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + /* re-activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } } else if (hhcd->hc[ch_num].state == HC_NAK) { hhcd->hc[ch_num].urb_state = URB_NOTREADY; - /* re-activate the channel */ + + /* re-activate the channel */ tmpreg = USBx_HC(ch_num)->HCCHAR; tmpreg &= ~USB_OTG_HCCHAR_CHDIS; tmpreg |= USB_OTG_HCCHAR_CHENA; @@ -1309,14 +1331,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) - { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - hhcd->hc[ch_num].ErrCnt++; - hhcd->hc[ch_num].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); - } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) { if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) @@ -1362,6 +1376,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) uint32_t USBx_BASE = (uint32_t)USBx; uint32_t ch_num = (uint32_t)chnum; uint32_t tmpreg; + uint32_t num_packets; if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { @@ -1380,15 +1395,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } - else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) - { - hhcd->hc[ch_num].state = HC_NYET; - hhcd->hc[ch_num].do_ping = 1U; - hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); - } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); @@ -1398,11 +1404,27 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) { hhcd->hc[ch_num].ErrCnt = 0U; + + /* transaction completed with NYET state, update do ping state */ + if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + { + hhcd->hc[ch_num].do_ping = 1U; + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + } __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); hhcd->hc[ch_num].state = HC_XFRC; } + else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) + { + hhcd->hc[ch_num].state = HC_NYET; + hhcd->hc[ch_num].do_ping = 1U; + hhcd->hc[ch_num].ErrCnt = 0U; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); + } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); @@ -1417,7 +1439,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->hc[ch_num].do_ping == 0U) { - if (hhcd->hc[ch_num].speed == HCD_SPEED_HIGH) + if (hhcd->hc[ch_num].speed == HCD_DEVICE_SPEED_HIGH) { hhcd->hc[ch_num].do_ping = 1U; } @@ -1429,9 +1451,26 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - hhcd->hc[ch_num].state = HC_XACTERR; + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[ch_num].state = HC_XACTERR; + __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); + } + else + { + hhcd->hc[ch_num].ErrCnt++; + if (hhcd->hc[ch_num].ErrCnt > 2U) + { + hhcd->hc[ch_num].ErrCnt = 0U; + hhcd->hc[ch_num].urb_state = URB_ERROR; + HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); + } + else + { + hhcd->hc[ch_num].urb_state = URB_NOTREADY; + } + } __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) @@ -1452,7 +1491,22 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)) { - hhcd->hc[ch_num].toggle_out ^= 1U; + if (hhcd->Init.dma_enable == 1U) + { + if (hhcd->hc[ch_num].xfer_len > 0U) + { + num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet; + + if ((num_packets & 1U) != 0U) + { + hhcd->hc[ch_num].toggle_out ^= 1U; + } + } + } + else + { + hhcd->hc[ch_num].toggle_out ^= 1U; + } } } else if (hhcd->hc[ch_num].state == HC_NAK) @@ -1471,7 +1525,7 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) (hhcd->hc[ch_num].state == HC_DATATGLERR)) { hhcd->hc[ch_num].ErrCnt++; - if (hhcd->hc[ch_num].ErrCnt > 3U) + if (hhcd->hc[ch_num].ErrCnt > 2U) { hhcd->hc[ch_num].ErrCnt = 0U; hhcd->hc[ch_num].urb_state = URB_ERROR; @@ -1479,13 +1533,13 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) else { hhcd->hc[ch_num].urb_state = URB_NOTREADY; - } - /* re-activate the channel */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; + /* re-activate the channel */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + } } else { @@ -1512,14 +1566,15 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) uint32_t USBx_BASE = (uint32_t)USBx; uint32_t pktsts; uint32_t pktcnt; - uint32_t temp; + uint32_t GrxstspReg; + uint32_t xferSizePktCnt; uint32_t tmpreg; uint32_t ch_num; - temp = hhcd->Instance->GRXSTSP; - ch_num = temp & USB_OTG_GRXSTSP_EPNUM; - pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17; - pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + GrxstspReg = hhcd->Instance->GRXSTSP; + ch_num = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; + pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17; + pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4; switch (pktsts) { @@ -1527,20 +1582,31 @@ static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) /* Read the data into the host buffer. */ if ((pktcnt > 0U) && (hhcd->hc[ch_num].xfer_buff != (void *)0)) { - (void)USB_ReadPacket(hhcd->Instance, hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); - - /*manage multiple Xfer */ - hhcd->hc[ch_num].xfer_buff += pktcnt; - hhcd->hc[ch_num].xfer_count += pktcnt; - - if ((USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0U) + if ((hhcd->hc[ch_num].xfer_count + pktcnt) <= hhcd->hc[ch_num].xfer_len) { - /* re-activate the channel when more packets are expected */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; - hhcd->hc[ch_num].toggle_in ^= 1U; + (void)USB_ReadPacket(hhcd->Instance, + hhcd->hc[ch_num].xfer_buff, (uint16_t)pktcnt); + + /* manage multiple Xfer */ + hhcd->hc[ch_num].xfer_buff += pktcnt; + hhcd->hc[ch_num].xfer_count += pktcnt; + + /* get transfer size packet count */ + xferSizePktCnt = (USBx_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; + + if ((hhcd->hc[ch_num].max_packet == pktcnt) && (xferSizePktCnt > 0U)) + { + /* re-activate the channel when more packets are expected */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + hhcd->hc[ch_num].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[ch_num].urb_state = URB_ERROR; } } break; diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.h index fa00eccf1f..82862629ce 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hcd.h @@ -33,7 +33,7 @@ extern "C" { * @{ */ -/** @addtogroup HCD +/** @addtogroup HCD HCD * @{ */ @@ -112,6 +112,10 @@ typedef struct #define HCD_SPEED_FULL USBH_FSLS_SPEED #define HCD_SPEED_LOW USBH_FSLS_SPEED +#define HCD_DEVICE_SPEED_HIGH 0U +#define HCD_DEVICE_SPEED_FULL 1U +#define HCD_DEVICE_SPEED_LOW 2U + /** * @} */ @@ -143,9 +147,9 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ /** @defgroup HCD_Exported_Macros HCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ #define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) @@ -214,10 +218,16 @@ typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, * @} */ -HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID, + pHCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, + HAL_HCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, + pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ /** @@ -267,6 +277,7 @@ HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chn uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum); uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); + /** * @} */ @@ -277,38 +288,19 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); /* Private macros ------------------------------------------------------------*/ /** @defgroup HCD_Private_Macros HCD Private Macros - * @{ - */ - + * @{ + */ /** * @} */ - /* Private functions prototypes ----------------------------------------------*/ -/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes - * @{ - */ /** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup HCD_Private_Functions HCD Private Functions - * @{ - */ - + * @} + */ /** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ + * @} + */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.c index e10103ef3f..1d7efa1377 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.c @@ -1220,6 +1220,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, return HAL_BUSY; } + /* Process Locked */ + __HAL_LOCK(hhrtim); + /* Set HRTIM state */ hhrtim->State = HAL_HRTIM_STATE_BUSY; @@ -1341,6 +1344,9 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim, /* Set HRTIM state */ hhrtim->State = HAL_HRTIM_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hhrtim); + return HAL_OK; } @@ -1612,11 +1618,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel)); - if (hhrtim->State == HAL_HRTIM_STATE_BUSY) + if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) { return HAL_BUSY; } - if (hhrtim->State == HAL_HRTIM_STATE_READY) + if((hhrtim->State == HAL_HRTIM_STATE_READY)) { if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) { @@ -2229,11 +2235,11 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel)); - if (hhrtim->State == HAL_HRTIM_STATE_BUSY) + if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) { return HAL_BUSY; } - if (hhrtim->State == HAL_HRTIM_STATE_READY) + if((hhrtim->State == HAL_HRTIM_STATE_READY)) { if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U)) { @@ -2474,7 +2480,7 @@ HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2 * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure - * @note When the timer operates in simple capture mode the capture is trigerred + * @note When the timer operates in simple capture mode the capture is triggered * by the designated external event and GPIO input is implicitly used as event source. * The cature can be triggered by a rising edge, a falling edge or both * edges on event channel. @@ -5308,7 +5314,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERID_TIMER_D * @arg HRTIM_TIMERID_TIMER_E * @retval HAL status - * @note This function enables the dma request(s) mentionned in the timer + * @note This function enables the dma request(s) mentioned in the timer * configuration data structure for every timers to start. * @note The source memory address, the destination memory address and the * size of each DMA transfer are specified at timer configuration time @@ -5323,7 +5329,7 @@ HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMERID(Timers)); - if (hhrtim->State == HAL_HRTIM_STATE_BUSY) + if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) { return HAL_BUSY; } @@ -5652,7 +5658,7 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERUPDATE_D * @arg HRTIM_TIMERUPDATE_E * @retval HAL status - * @note The 'software update' bits in the HRTIM conrol register 2 register are + * @note The 'software update' bits in the HRTIM control register 2 register are * automatically reset by hardware */ HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim, @@ -5694,7 +5700,7 @@ HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim, * @arg HRTIM_TIMERRESET_TIMER_D * @arg HRTIM_TIMERRESET_TIMER_E * @retval HAL status - * @note The 'software reset' bits in the HRTIM conrol register 2 are + * @note The 'software reset' bits in the HRTIM control register 2 are * automatically reset by hardware */ HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim, @@ -5758,11 +5764,11 @@ HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, /* Check the parameters */ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx)); - if (hhrtim->State == HAL_HRTIM_STATE_BUSY) + if((hhrtim->State == HAL_HRTIM_STATE_BUSY)) { return HAL_BUSY; } - if (hhrtim->State == HAL_HRTIM_STATE_READY) + if((hhrtim->State == HAL_HRTIM_STATE_READY)) { if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U)) { @@ -6190,7 +6196,7 @@ uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET) { - /* Output is enabled: output in RUN state (whatever ouput disable status is)*/ + /* Output is enabled: output in RUN state (whatever output disable status is)*/ output_state = HRTIM_OUTPUTSTATE_RUN; } else @@ -7573,7 +7579,7 @@ static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim, hrtim_mcr &= ~(HRTIM_MCR_DACSYNC); hrtim_mcr |= pTimerCfg->DACSynchro; - /* Enable/Disable preload meachanism for timer registers */ + /* Enable/Disable preload mechanism for timer registers */ hrtim_mcr &= ~(HRTIM_MCR_PREEN); hrtim_mcr |= pTimerCfg->PreloadEnable; @@ -7636,7 +7642,7 @@ static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim, hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC); hrtim_timcr |= pTimerCfg->DACSynchro; - /* Enable/Disable preload meachanism for timer registers */ + /* Enable/Disable preload mechanism for timer registers */ hrtim_timcr &= ~(HRTIM_TIMCR_PREEN); hrtim_timcr |= pTimerCfg->PreloadEnable; @@ -8549,10 +8555,13 @@ static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim, */ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) { + uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); + uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); + /* Fault 1 event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET) + if((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1); @@ -8566,9 +8575,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 2 event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET) + if((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2); @@ -8582,9 +8591,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 3 event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET) + if((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3); @@ -8598,9 +8607,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 4 event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET) + if((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4); @@ -8614,9 +8623,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Fault 5 event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET) + if((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5); @@ -8630,9 +8639,9 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) } /* System fault event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET) + if((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT); @@ -8653,10 +8662,15 @@ static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim) */ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) { + uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR); + uint32_t ierits = READ_REG(hhrtim->Instance->sCommonRegs.IER); + uint32_t misrflags = READ_REG(hhrtim->Instance->sMasterRegs.MISR); + uint32_t mdierits = READ_REG(hhrtim->Instance->sMasterRegs.MDIER); + /* Burst mode period event */ - if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != (uint32_t)RESET) + if((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET) { - if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET) + if((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET) { __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER); @@ -8670,9 +8684,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 1 event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1); @@ -8686,9 +8700,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 2 event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2); @@ -8702,9 +8716,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 3 event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3); @@ -8718,9 +8732,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer compare 4 event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4); @@ -8734,9 +8748,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer repetition event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP); @@ -8750,9 +8764,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Synchronization input event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC); @@ -8766,9 +8780,9 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) } /* Master timer registers update event */ - if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) + if((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET) { - if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET) + if((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET) { __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD); @@ -8797,10 +8811,13 @@ static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim) static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, uint32_t TimerIdx) { + uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR); + uint32_t tdierits = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER); + /* Timer compare 1 event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1); @@ -8814,9 +8831,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 2 event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2); @@ -8830,9 +8847,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 3 event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3); @@ -8846,9 +8863,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer compare 4 event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4); @@ -8862,9 +8879,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer repetition event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP); @@ -8878,9 +8895,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer registers update event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD); @@ -8894,9 +8911,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 1 event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1); @@ -8910,9 +8927,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer capture 2 event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2); @@ -8926,9 +8943,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 set event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1); @@ -8942,9 +8959,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 1 reset event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1); @@ -8958,9 +8975,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 set event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2); @@ -8974,9 +8991,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer output 2 reset event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2); @@ -8990,9 +9007,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Timer reset event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST); @@ -9006,9 +9023,9 @@ static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim, } /* Delayed protection event */ - if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) + if((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET) { - if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET) + if((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET) { __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.h index c2be7a50a2..798ad823aa 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_hrtim.h @@ -946,7 +946,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< * @{ * @brief Constants defining the polarity of a timer output */ -#define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is acitve HIGH */ +#define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is active HIGH */ #define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.c index cecdbb4a93..09b3e2a156 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.c @@ -93,7 +93,7 @@ [..] (+) A specific option field manage the different steps of a sequential transfer (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address @@ -112,7 +112,7 @@ or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). - Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit without stopping the communication and so generate a restart condition. (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential interface. @@ -122,7 +122,7 @@ or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. - (+) Differents sequential I2C interfaces are listed below: + (+) Different sequential I2C interfaces are listed below: (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() or using @ref HAL_I2C_Master_Seq_Transmit_DMA() (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can @@ -390,8 +390,10 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); /* Private functions for I2C transfer IRQ handler */ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); @@ -400,7 +402,8 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); @@ -417,7 +420,8 @@ static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); /* Private function to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); /* Private function to Convert Specific options */ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); @@ -432,8 +436,8 @@ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); */ /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -672,7 +676,8 @@ __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -977,8 +982,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -1060,7 +1065,8 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1174,7 +1180,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1550,7 +1557,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; @@ -1786,7 +1794,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; @@ -1929,7 +1938,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; @@ -2280,7 +2290,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2372,8 +2383,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress } } - } - while (hi2c->XferCount > 0U); + } while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ @@ -2415,7 +2425,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -2507,8 +2518,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); } } - } - while (hi2c->XferCount > 0U); + } while (hi2c->XferCount > 0U); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is reset */ @@ -2548,7 +2558,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2639,7 +2650,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2729,7 +2741,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -2873,7 +2886,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param Size Amount of data to be read * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { uint32_t tickstart; uint32_t xfermode; @@ -3124,8 +3138,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Increment Trials */ I2C_Trials++; - } - while (I2C_Trials < Trials); + } while (I2C_Trials < Trials); /* Update I2C state */ hi2c->State = HAL_I2C_STATE_READY; @@ -3156,7 +3169,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; @@ -3240,7 +3254,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_WRITE; @@ -3402,7 +3417,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; @@ -3486,7 +3502,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t xfermode; uint32_t xferrequest = I2C_GENERATE_START_READ; @@ -3646,7 +3663,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3741,7 +3759,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { HAL_StatusTypeDef dmaxferstatus; @@ -3920,7 +3939,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_ * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -4015,7 +4035,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS * @retval HAL status */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { HAL_StatusTypeDef dmaxferstatus; @@ -4300,8 +4321,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA */ /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /** * @brief This function handles I2C event interrupt request. @@ -4539,8 +4560,8 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) */ /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @brief Peripheral State, Mode and Error functions - * + * @brief Peripheral State, Mode and Error functions + * @verbatim =============================================================================== ##### Peripheral State, Mode and Error functions ##### @@ -4577,11 +4598,11 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) } /** -* @brief Return the I2C error code. + * @brief Return the I2C error code. * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. -* @retval I2C Error Code -*/ + * @retval I2C Error Code + */ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) { return hi2c->ErrorCode; @@ -4767,7 +4788,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint /* So clear Flag NACKF only */ if (hi2c->XferCount == 0U) { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, tmpITFlags); @@ -4827,7 +4849,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint I2C_ITSlaveSeqCplt(hi2c); } } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) { I2C_ITAddrCplt(hi2c, tmpITFlags); } @@ -4835,7 +4858,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Datas have already been sent */ + /* Check if all data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hi2c->XferCount > 0U) { @@ -5063,7 +5086,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin if (treatdmanack == 1U) { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) { /* Call I2C Listen complete process */ I2C_ITListenCplt(hi2c, ITFlags); @@ -5151,7 +5175,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); @@ -5204,7 +5229,8 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) { I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); @@ -5719,7 +5745,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) } else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) { - /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */ + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ I2C_ITSlaveSeqCplt(hi2c); hi2c->XferOptions = I2C_NO_OPTION_FRAME; @@ -5856,7 +5882,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - /* If state is an abort treatment on goind, don't change state */ + /* If state is an abort treatment on going, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) { @@ -5868,7 +5894,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) /* Abort DMA TX transfer if any */ tmppreviousstate = hi2c->PreviousState; - if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) { if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) { @@ -5897,7 +5924,8 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) } } /* Abort DMA RX transfer if any */ - else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) { if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) { @@ -6210,7 +6238,8 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) { while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { @@ -6442,7 +6471,8 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) { /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); @@ -6450,8 +6480,11 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uin assert_param(IS_TRANSFER_REQUEST(Request)); /* update CR2 register */ - MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + MODIFY_REG(hi2c->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** @@ -6591,7 +6624,7 @@ static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) } /** - * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions. + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. * @param hi2c I2C handle. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.h index d510a6dca9..9962ac1327 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c.h @@ -495,7 +495,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified I2C flag is set or not. * @param __HANDLE__ specifies the I2C Handle. @@ -521,7 +522,8 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @retval The new state of __FLAG__ (SET or RESET). */ #define I2C_FLAG_MASK (0x0001FFFFU) -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the I2C Handle. @@ -541,7 +543,7 @@ typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t Trans * @retval None */ #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) + : ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified I2C peripheral. * @param __HANDLE__ specifies the I2C Handle. @@ -583,7 +585,8 @@ void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); @@ -598,49 +601,70 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); */ /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); /******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); /** * @} */ /** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); @@ -732,7 +756,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) #define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)) #define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)) @@ -743,13 +768,15 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) #define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) #define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) -#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) #define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.c index f568c3e7b5..26a046bdb8 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.c @@ -73,7 +73,7 @@ /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions * @brief Extended features functions - * + * @verbatim =============================================================================== ##### Extended features functions ##### diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.h index 797cd4c7ea..79099801b9 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_i2c_ex.h @@ -38,7 +38,6 @@ extern "C" { /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ - /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants * @{ */ @@ -78,24 +77,51 @@ extern "C" { */ /* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions * @{ */ -/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions +/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions * @{ */ - /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions + * @{ + */ HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions + * @{ + */ void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + + +/** + * @} + */ /* Private constants ---------------------------------------------------------*/ /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants @@ -111,7 +137,7 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @{ */ #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) @@ -146,9 +172,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1)) #endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */ - - - /** * @} */ @@ -170,14 +193,6 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @} */ -/** - * @} - */ - -/** - * @} - */ - #ifdef __cplusplus } #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.c index eec986d462..865e9c8164 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.c @@ -40,7 +40,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter), the normal or low power mode and the clock prescaler in the hirda handle Init structure. @@ -612,43 +613,45 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD switch (CallbackID) { case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : - hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_IRDA_TX_COMPLETE_CB_ID : - hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : - hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_IRDA_RX_COMPLETE_CB_ID : - hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_IRDA_ERROR_CB_ID : - hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_IRDA_ABORT_COMPLETE_CB_ID : - hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : - hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ break; case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : - hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_IRDA_MSPINIT_CB_ID : - hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ + hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_IRDA_MSPDEINIT_CB_ID : - hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -771,13 +774,16 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side. + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + Transfer is kept ongoing on IRDA side. If user wants to abort it, Abort services should be called by user. (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. + Error code is set to allow user to identify error type, and + HAL_IRDA_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -815,7 +821,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u hirda->ErrorCode = HAL_IRDA_ERROR_NONE; hirda->gState = HAL_IRDA_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); hirda->TxXferSize = Size; @@ -905,7 +911,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui hirda->ErrorCode = HAL_IRDA_ERROR_NONE; hirda->RxState = HAL_IRDA_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); hirda->RxXferSize = Size; @@ -1280,7 +1286,7 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_IRDA_CLEAR_OREFLAG(hirda); - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -1380,7 +1386,8 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \ + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Disable the IRDA DMA Tx request if enabled */ @@ -1578,7 +1585,8 @@ HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) uint32_t abortcplt = 1U; /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \ + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised @@ -2236,7 +2244,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) uint32_t tmpreg; IRDA_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; - const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; PLL2_ClocksTypeDef pll2_clocks; PLL3_ClocksTypeDef pll3_clocks; uint32_t pclk; @@ -2331,7 +2339,7 @@ static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) /* Initialize the IRDA ErrorCode */ hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ @@ -2386,7 +2394,8 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.h index 1a82ca01b4..869f840e13 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_irda.h @@ -78,7 +78,8 @@ typedef struct /** * @brief HAL IRDA State definition - * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition). + * @note HAL IRDA State value is a combination of 2 different substates: + * gState and RxState (see @ref IRDA_State_Definition). * - gState contains IRDA state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -89,7 +90,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called) + * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -106,7 +107,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -250,7 +251,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer Value is allowed for RxState only */ #define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ + Value is result of combination (Or) between + gState and RxState values */ #define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state Value is allowed for gState only */ #define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error @@ -262,15 +264,15 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer /** @defgroup IRDA_Error_Definition IRDA Error Code Definition * @{ */ -#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */ +#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */ #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ /** * @} @@ -573,9 +575,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((__HANDLE__)->Instance->CR3 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. * @param __HANDLE__ specifies the IRDA Handle. @@ -589,10 +596,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) - +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Check whether the specified IRDA interrupt has occurred or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -608,8 +619,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -623,9 +634,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \ + & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \ + & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the IRDA Handle. diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.c index d90bfb12c0..85548ac40d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.c @@ -48,7 +48,7 @@ [..] Default timeout value (necessary for IWDG_SR status register update): Constant LSI_VALUE is defined based on the nominal LSI clock frequency. - This frequency being subject to variations as mentioned above, the + This frequency being subject to variations as mentioned above, the default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT below) may become too short or too long. In such cases, this default timeout value can be tuned by redefining @@ -66,13 +66,13 @@ (++) Configure the IWDG prescaler and counter reload value. This reload value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. - (++) Wait for status flags to be reset. (++) Depending on window parameter: (+++) If Window Init parameter is same as Window register value, nothing more is done but reload counter value in order to exit function with exact time base. (+++) Else modify Window register. This will automatically reload watchdog counter. + (++) Wait for status flags to be reset. (#) Then the application program must refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using @@ -126,7 +126,8 @@ the LSI_VALUE constant. The value of this constant can be changed by the user to take into account possible LSI clock period variations. The timeout value is multiplied by 1000 to be converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) +#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) +#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} */ @@ -197,11 +198,14 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) tickstart = HAL_GetTick(); /* Wait for register to be updated */ - while (hiwdg->Instance->SR != 0x00u) + while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) { - return HAL_TIMEOUT; + if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) + { + return HAL_TIMEOUT; + } } } @@ -224,6 +228,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) return HAL_OK; } + /** * @} */ @@ -243,7 +248,6 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) * @{ */ - /** * @brief Refresh the IWDG. * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains @@ -259,6 +263,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) return HAL_OK; } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.h index 2157e774dc..93d30256cb 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_iwdg.h @@ -87,7 +87,6 @@ typedef struct #define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ #define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ #define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ - /** * @} */ @@ -100,7 +99,6 @@ typedef struct * @} */ - /** * @} */ @@ -138,7 +136,7 @@ typedef struct * @{ */ /* Initialization/Start functions ********************************************/ -HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); /** * @} */ @@ -147,7 +145,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); * @{ */ /* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.c index 160b0f46e7..ce873e28a9 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.c @@ -1284,7 +1284,7 @@ HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTy * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains - * The JPEG decoded header informations + * The JPEG decoded header information * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo) @@ -2313,7 +2313,7 @@ HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg) * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains - * The JPEG decoded header informations + * The JPEG decoded header information * @retval None */ __weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo) @@ -2524,7 +2524,7 @@ uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg) * @param Bits pointer to bits table * @param Huffsize pointer to sizes table * @param Huffcode pointer to codes table - * @param LastK pointer to last Coeff (table dimmension) + * @param LastK pointer to last Coeff (table dimension) * @retval HAL status */ static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK) @@ -3328,12 +3328,12 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) { uint32_t tmpContext; - /*End of header processing flag rised*/ + /*End of header processing flag */ if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) { if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL) { - /*Call Header parsing complet callback */ + /*Call Header parsing complete callback */ (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); /* Reset the ImageQuality */ hjpeg->Conf.ImageQuality = 0; @@ -3359,13 +3359,13 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) { if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != 0UL) { - /*Input FIFO threshold flag rised*/ + /*Input FIFO threshold flag */ /*JPEG_FIFO_TH_SIZE words can be written in */ JPEG_ReadInputData(hjpeg, JPEG_FIFO_TH_SIZE); } else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != 0UL) { - /*Input FIFO Not Full flag rised*/ + /*Input FIFO Not Full flag */ /*32-bit value can be written in */ JPEG_ReadInputData(hjpeg, 1); } @@ -3381,13 +3381,13 @@ static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) { if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != 0UL) { - /*Output FIFO threshold flag rised*/ + /*Output FIFO threshold flag */ /*JPEG_FIFO_TH_SIZE words can be read out */ JPEG_StoreOutputData(hjpeg, JPEG_FIFO_TH_SIZE); } else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL) { - /*Output FIFO Not Empty flag rised*/ + /*Output FIFO Not Empty flag */ /*32-bit value can be read out */ JPEG_StoreOutputData(hjpeg, 1); } @@ -3828,7 +3828,7 @@ static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg) hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; tmpContext = hjpeg->Context; - /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ + /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); /* Process Unlocked */ @@ -3927,7 +3927,7 @@ static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg) } tmpContext = hjpeg->Context; - /*Clear all context fileds execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ + /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); /* Process Unlocked */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.h index 846609a29a..16176c3459 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_jpeg.h @@ -399,7 +399,7 @@ typedef void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8 * @arg JPEG_IT_EOC : End of Conversion Interrupt * @arg JPEG_IT_HPD : Header Parsing Done Interrupt * - * @retval No retrun + * @retval No return */ #define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) ) @@ -417,7 +417,7 @@ typedef void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8 * * @note To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits * located in the same IT enable register (CR register). - * @retval No retrun + * @retval No return */ #define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.c index 0a579dcec7..5c396663dc 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.c @@ -197,8 +197,8 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t */ /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -235,19 +235,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); - } - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) - { assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); - assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); @@ -281,21 +279,18 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); } if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL)); - } - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) - { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); } - /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | + /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE)); /* Set initialization parameters */ @@ -314,19 +309,21 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) hlptim->Init.UltraLowPowerClock.SampleTime); } - /* Configure the active edge or edges used by the counter only if LPTIM is - * clocked by an external clock source - */ - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + /* Configure LPTIM external clock polarity and digital filter */ + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity); + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + hlptim->Init.UltraLowPowerClock.SampleTime); } + /* Configure LPTIM external trigger */ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ - tmpcfgr |= (hlptim->Init.Trigger.Source | - hlptim->Init.Trigger.ActiveEdge); + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge | + hlptim->Init.Trigger.SampleTime); } /* Write to LPTIMx CFGR */ @@ -443,8 +440,8 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions - * @brief Start-Stop operation functions. - * + * @brief Start-Stop operation functions. + * @verbatim ============================================================================== ##### LPTIM Start Stop operation functions ##### @@ -1563,7 +1560,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t hlptim->State = HAL_LPTIM_STATE_BUSY; /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1641,7 +1639,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 hlptim->State = HAL_LPTIM_STATE_BUSY; /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1729,8 +1728,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions - * @brief Read operation functions. - * + * @brief Read operation functions. + * @verbatim ============================================================================== ##### LPTIM Read operation functions ##### @@ -1787,8 +1786,8 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks - * @brief LPTIM IRQ handler. - * + * @brief LPTIM IRQ handler. + * @verbatim ============================================================================== ##### LPTIM IRQ handler and callbacks ##### @@ -2255,8 +2254,8 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti */ /** @defgroup LPTIM_Group5 Peripheral State functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim ============================================================================== ##### Peripheral State functions ##### @@ -2331,8 +2330,7 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t { result = HAL_TIMEOUT; } - } - while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); return result; } diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.h index 20fcffad44..7275614e9a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_lptim.h @@ -379,10 +379,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -532,7 +532,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @retval Interrupt status. */ -#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @} @@ -544,9 +545,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ /** @addtogroup LPTIM_Exported_Functions_Group1 - * @brief Initialization and Configuration functions. - * @{ - */ + * @brief Initialization and Configuration functions. + * @{ + */ /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); @@ -559,9 +560,9 @@ void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group2 - * @brief Start-Stop operation functions. - * @{ - */ + * @brief Start-Stop operation functions. + * @{ + */ /* Start/Stop operation functions *********************************************/ /* ################################# PWM Mode ################################*/ /* Blocking mode: Polling */ @@ -615,9 +616,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group3 - * @brief Read operation functions. - * @{ - */ + * @brief Read operation functions. + * @{ + */ /* Reading operation functions ************************************************/ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); @@ -627,9 +628,9 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group4 - * @brief LPTIM IRQ handler and callback functions. - * @{ - */ + * @brief LPTIM IRQ handler and callback functions. + * @{ + */ /* LPTIM IRQ functions *******************************************************/ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); @@ -644,7 +645,8 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, + pLPTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** @@ -652,9 +654,9 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_ */ /** @addtogroup LPTIM_Group5 - * @brief Peripheral State functions. - * @{ - */ + * @brief Peripheral State functions. + * @{ + */ /* Peripheral State functions ************************************************/ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** @@ -758,26 +760,26 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ - ((((__INSTANCE__) == LPTIM1) && \ - (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \ - || \ - (((__INSTANCE__) == LPTIM2) && \ - (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))) \ - || \ - (((__INSTANCE__) == LPTIM3) && \ - (((__SOURCE__) == LPTIM_INPUT1SOURCE_NOT_CONNECTED) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSA) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSB)))) + ((((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \ + || \ + (((__INSTANCE__) == LPTIM2) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))) \ + || \ + (((__INSTANCE__) == LPTIM3) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_NOT_CONNECTED) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSA) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSB)))) #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ - ((((__INSTANCE__) == LPTIM1) || \ - ((__INSTANCE__) == LPTIM2)) && \ - (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2))) + ((((__INSTANCE__) == LPTIM1) || \ + ((__INSTANCE__) == LPTIM2)) && \ + (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2))) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdios.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdios.c index 5ad0ff7ee7..834ffeb11e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdios.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdios.c @@ -55,8 +55,8 @@ (@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt and execute the previous callbacks - (#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API. - (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources + (#) Reset the MDIOS peripheral and all related resources by calling the HAL_MDIOS_DeInit() API. + (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level resources (GPIO, Clocks, NVIC configuration ...) *** Callback registration *** diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.c index 4e606000ef..1ce7664b28 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.c @@ -1475,14 +1475,14 @@ HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma) if((hmdma->Instance->CCR & MDMA_CCR_EN) == 0U) { - /* if no Transfer on going (MDMA enable bit not set) retrun error */ + /* if no Transfer on going (MDMA enable bit not set) return error */ hmdma->ErrorCode = HAL_MDMA_ERROR_NO_XFER; return HAL_ERROR; } else if(((hmdma->Instance->CISR & MDMA_CISR_CRQA) != 0U) || (request_mode == 0U)) { - /* if an MDMA ongoing request has not yet end or if request mode is not SW request retrun error */ + /* if an MDMA ongoing request has not yet end or if request mode is not SW request return error */ hmdma->ErrorCode = HAL_MDMA_ERROR_BUSY; return HAL_ERROR; @@ -1755,7 +1755,7 @@ uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma) * @param SrcAddress: The source memory Buffer address * @param DstAddress: The destination memory Buffer address * @param BlockDataLength : The length of a block transfer in bytes - * @param BlockCount: The number of blocks to be transfered + * @param BlockCount: The number of blocks to be transferred * @retval HAL status */ static void MDMA_SetConfig(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.h index afd2aeb4e3..2e5f8e1111 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mdma.h @@ -82,7 +82,7 @@ typedef struct this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/ uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers. - It specifies the amount of data to be transferred in a single non interruptable + It specifies the amount of data to be transferred in a single non interruptible transaction. This parameter can be a value of @ref MDMA_Source_burst @note : the burst may be FIXED/INCR based on SourceInc value , @@ -90,7 +90,7 @@ typedef struct BufferTransferLength */ uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers. - It specifies the amount of data to be transferred in a single non interruptable + It specifies the amount of data to be transferred in a single non interruptible transaction. This parameter can be a value of @ref MDMA_Destination_burst @note : the burst may be FIXED/INCR based on DestinationInc value , @@ -509,7 +509,7 @@ typedef struct __MDMA_HandleTypeDef #define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */ #define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */ #define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */ -#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */ +#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel request Active flag */ /** * @} @@ -549,7 +549,7 @@ typedef struct __MDMA_HandleTypeDef * @arg MDMA_FLAG_BRT : Block Repeat Transfer flag. * @arg MDMA_FLAG_BT : Block Transfer complete flag. * @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag. - * @arg MDMA_FLAG_CRQA : Channel ReQest Active flag. + * @arg MDMA_FLAG_CRQA : Channel request Active flag. * @retval The state of FLAG (SET or RESET). */ #define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__)) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.c index ad6933434c..07ec0b24de 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.c @@ -105,7 +105,7 @@ (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT(). This function allows the read of 512 bytes blocks. - You can choose either one block read operation or multiple block read operation + You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_MMC_GetCardState() function for MMC card state. @@ -129,18 +129,18 @@ by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_MMC_GetCardState() function for MMC card state. - You could also check the DMA transfer process through the MMC Tx interrupt event. + You could also check the DMA transfer process through the MMC Tx interrupt event. (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT(). This function allows the read of 512 bytes blocks. - You can choose either one block read operation or multiple block read operation + You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_MMC_GetCardState() function for MMC card state. You could also check the IT transfer process through the MMC Tx interrupt event. *** MMC card information *** - =========================== + =========================== [..] (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo(). It returns useful information about the MMC card such as block size, card type, @@ -260,7 +260,31 @@ /** @addtogroup MMC_Private_Defines * @{ */ +#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U) +#define MMC_VOLTAGE_RANGE MMC_LOW_VOLTAGE_RANGE +#define MMC_EXT_CSD_PWR_CL_26_INDEX 201 +#define MMC_EXT_CSD_PWR_CL_52_INDEX 200 +#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 238 + +#define MMC_EXT_CSD_PWR_CL_26_POS 8 +#define MMC_EXT_CSD_PWR_CL_52_POS 0 +#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16 +#else +#define MMC_VOLTAGE_RANGE MMC_HIGH_VOLTAGE_RANGE + +#define MMC_EXT_CSD_PWR_CL_26_INDEX 203 +#define MMC_EXT_CSD_PWR_CL_52_INDEX 202 +#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 239 + +#define MMC_EXT_CSD_PWR_CL_26_POS 24 +#define MMC_EXT_CSD_PWR_CL_52_POS 16 +#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24 +#endif + +/* Frequencies used in the driver for clock divider calculation */ +#define MMC_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */ +#define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */ /** * @} */ @@ -280,8 +304,9 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc); static void MMC_Read_IT(MMC_HandleTypeDef *hmmc); static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state); static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state); -HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout); - +static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, + uint32_t Timeout); +static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed); /** * @} @@ -292,8 +317,8 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, */ /** @addtogroup MMC_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions - * + * @brief Initialization and de-initialization functions + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -315,7 +340,7 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) { /* Check the MMC handle allocation */ - if(hmmc == NULL) + if (hmmc == NULL) { return HAL_ERROR; } @@ -328,7 +353,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl)); assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv)); - if(hmmc->State == HAL_MMC_STATE_RESET) + if (hmmc->State == HAL_MMC_STATE_RESET) { /* Allocate lock resource and initialize it */ hmmc->Lock = HAL_UNLOCKED; @@ -343,7 +368,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuf0CpltCallback; hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuf1CpltCallback; - if(hmmc->MspInitCallback == NULL) + if (hmmc->MspInitCallback == NULL) { hmmc->MspInitCallback = HAL_MMC_MspInit; } @@ -359,7 +384,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize the Card parameters */ - if(HAL_MMC_InitCard(hmmc) == HAL_ERROR) + if (HAL_MMC_InitCard(hmmc) == HAL_ERROR) { return HAL_ERROR; } @@ -373,6 +398,15 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) /* Initialize the MMC state */ hmmc->State = HAL_MMC_STATE_READY; + /* Configure bus width */ + if (hmmc->Init.BusWide != SDMMC_BUS_WIDE_1B) + { + if (HAL_MMC_ConfigWideBusOperation(hmmc, hmmc->Init.BusWide) != HAL_OK) + { + return HAL_ERROR; + } + } + return HAL_OK; } @@ -397,7 +431,17 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Init Clock should be less or equal to 400Khz*/ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); - Init.ClockDiv = sdmmc_clk/(2U*400000U); + if (sdmmc_clk == 0U) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; + return HAL_ERROR; + } + Init.ClockDiv = sdmmc_clk / (2U * MMC_INIT_FREQ); + +#if (USE_SD_TRANSCEIVER != 0U) + Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT; +#endif /* USE_SD_TRANSCEIVER */ /* Initialize SDMMC peripheral interface with default configuration */ (void)SDMMC_Init(hmmc->Instance, Init); @@ -407,20 +451,12 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /* wait 74 Cycles: required power up waiting time before starting the MMC initialization sequence */ - sdmmc_clk = sdmmc_clk/(2U*Init.ClockDiv); - - if(sdmmc_clk != 0U) - { - HAL_Delay(1U+ (74U*1000U/(sdmmc_clk))); - } - else - { - HAL_Delay(2U); - } + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); /* Identify card operating voltage */ errorstate = MMC_PowerON(hmmc); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->State = HAL_MMC_STATE_READY; hmmc->ErrorCode |= errorstate; @@ -429,7 +465,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Card initialization */ errorstate = MMC_InitCard(hmmc); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->State = HAL_MMC_STATE_READY; hmmc->ErrorCode |= errorstate; @@ -438,7 +474,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -458,7 +494,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) { /* Check the MMC handle allocation */ - if(hmmc == NULL) + if (hmmc == NULL) { return HAL_ERROR; } @@ -472,7 +508,7 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) MMC_PowerOFF(hmmc); #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - if(hmmc->MspDeInitCallback == NULL) + if (hmmc->MspDeInitCallback == NULL) { hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; } @@ -526,8 +562,8 @@ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) */ /** @addtogroup MMC_Exported_Functions_Group2 - * @brief Data transfer functions - * + * @brief Data transfer functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -552,7 +588,8 @@ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -561,22 +598,40 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui uint32_t add = BlockAdd; uint8_t *tempbuff = pData; - if(NULL == pData) + if (NULL == pData) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ @@ -595,10 +650,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; @@ -612,7 +667,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui /* Read Single Block command */ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); } - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -623,12 +678,13 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui /* Poll on SDMMC flags */ dataremaining = config.DataLength; - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) { /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = SDMMC_ReadFIFO(hmmc->Instance); *tempbuff = (uint8_t)(data & 0xFFU); @@ -643,23 +699,23 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui dataremaining -= 32U; } - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; - hmmc->State= HAL_MMC_STATE_READY; + hmmc->State = HAL_MMC_STATE_READY; return HAL_TIMEOUT; } } - __SDMMC_CMDTRANS_DISABLE( hmmc->Instance); + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); /* Send stop transmission command in case of multiblock read */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) { /* Send stop transmission command */ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -670,7 +726,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui } /* Get error state */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -678,7 +734,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -686,7 +742,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -725,7 +781,8 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -734,22 +791,40 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u uint32_t add = BlockAdd; uint8_t *tempbuff = pData; - if(NULL == pData) + if (NULL == pData) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ @@ -768,10 +843,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; @@ -785,7 +860,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); } - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -796,12 +871,13 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u /* Write block(s) in polling mode */ dataremaining = config.DataLength; - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) { /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = (uint32_t)(*tempbuff); tempbuff++; @@ -816,7 +892,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u dataremaining -= 32U; } - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -825,14 +901,14 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u return HAL_TIMEOUT; } } - __SDMMC_CMDTRANS_DISABLE( hmmc->Instance); + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); /* Send stop transmission command in case of multiblock write */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) { /* Send stop transmission command */ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -843,7 +919,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u } /* Get error state */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -851,7 +927,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -859,7 +935,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -899,28 +975,47 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, + uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ @@ -942,10 +1037,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); /* Read Blocks in IT mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT); @@ -960,7 +1055,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); } - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -969,7 +1064,8 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, return HAL_ERROR; } - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_RXFIFOHF)); return HAL_OK; } @@ -992,28 +1088,47 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, + uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ @@ -1036,12 +1151,12 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { - hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT); + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_IT); /* Write Multi Block command */ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); @@ -1053,7 +1168,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); } - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1063,7 +1178,8 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData } /* Enable transfer interrupts */ - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_TXFIFOHE)); return HAL_OK; } @@ -1086,28 +1202,47 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, + uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_DMA_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ @@ -1130,12 +1265,12 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); hmmc->Instance->IDMABASE0 = (uint32_t) pData ; hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; /* Read Blocks in DMA mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); @@ -1149,7 +1284,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData /* Read Single Block command */ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); } - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1182,28 +1317,47 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, + uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ @@ -1226,13 +1380,13 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); hmmc->Instance->IDMABASE0 = (uint32_t) pData ; hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); @@ -1246,7 +1400,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); } - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1281,26 +1435,37 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t start_add = BlockStartAdd; uint32_t end_add = BlockEndAdd; - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - if(end_add < start_add) + if (end_add < start_add) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(end_add > (hmmc->MmcCard.LogBlockNbr)) + if (end_add > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U)) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Check if the card command class supports erase command */ - if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) + if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1309,7 +1474,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, return HAL_ERROR; } - if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1326,7 +1491,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1337,7 +1502,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */ errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1348,7 +1513,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, /* Send CMD38 ERASE */ errorstate = SDMMC_CmdErase(hmmc->Instance, 0UL); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1378,33 +1543,33 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) uint32_t context = hmmc->Context; /* Check for SDMMC interrupt flags */ - if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) { MMC_Read_IT(hmmc); } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET) { __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND); - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ - SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ - SDMMC_IT_RXFIFOHF); + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \ + SDMMC_IT_RXFIFOHF); __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC); - __SDMMC_CMDTRANS_DISABLE( hmmc->Instance); + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); - if((context & MMC_CONTEXT_DMA) != 0U) + if ((context & MMC_CONTEXT_DMA) != 0U) { hmmc->Instance->DLEN = 0; hmmc->Instance->DCTRL = 0; hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ; /* Stop Transfer for Write Multi blocks or Read Multi blocks */ - if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) @@ -1419,7 +1584,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); hmmc->State = HAL_MMC_STATE_READY; - if(((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + if (((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->TxCpltCallback(hmmc); @@ -1427,7 +1592,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) HAL_MMC_TxCpltCallback(hmmc); #endif } - if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->RxCpltCallback(hmmc); @@ -1436,13 +1601,13 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) #endif } } - else if((context & MMC_CONTEXT_IT) != 0U) + else if ((context & MMC_CONTEXT_IT) != 0U) { /* Stop Transfer for Write Multi blocks or Read Multi blocks */ - if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) @@ -1457,7 +1622,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); hmmc->State = HAL_MMC_STATE_READY; - if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->RxCpltCallback(hmmc); @@ -1480,27 +1645,28 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) } } - else if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + else if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) { MMC_Write_IT(hmmc); } - else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL| SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL | + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) { /* Set Error code */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET) { hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; } - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET) { hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; } - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET) { hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; } - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET) { hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; } @@ -1509,17 +1675,17 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); /* Disable all interrupts */ - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); - __SDMMC_CMDTRANS_DISABLE( hmmc->Instance); + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; hmmc->Instance->CMD |= SDMMC_CMD_CMDSTOP; hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); hmmc->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP); __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DABORT); - if((context & MMC_CONTEXT_IT) != 0U) + if ((context & MMC_CONTEXT_IT) != 0U) { /* Set the MMC state to ready to be able to start again the process */ hmmc->State = HAL_MMC_STATE_READY; @@ -1529,9 +1695,9 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) HAL_MMC_ErrorCallback(hmmc); #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } - else if((context & MMC_CONTEXT_DMA) != 0U) + else if ((context & MMC_CONTEXT_DMA) != 0U) { - if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE) { /* Disable Internal DMA */ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC); @@ -1552,13 +1718,13 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) } } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET) { __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC); - if(READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) + if (READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) { /* Current buffer is buffer0, Transfer complete for buffer1 */ - if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + if ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->Write_DMADblBuf1CpltCallback(hmmc); @@ -1578,7 +1744,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) else /* MMC_DMA_BUFFER1 */ { /* Current buffer is buffer1, Transfer complete for buffer0 */ - if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + if ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->Write_DMADblBuf0CpltCallback(hmmc); @@ -1614,11 +1780,11 @@ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) } /** -* @brief Return the MMC error code -* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains + * @brief Return the MMC error code + * @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains * the configuration information. -* @retval MMC Error Code -*/ + * @retval MMC Error Code + */ uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) { return hmmc->ErrorCode; @@ -1704,11 +1870,12 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, + pMMC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; @@ -1718,64 +1885,64 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call /* Process locked */ __HAL_LOCK(hmmc); - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { switch (CallbackId) { - case HAL_MMC_TX_CPLT_CB_ID : - hmmc->TxCpltCallback = pCallback; - break; - case HAL_MMC_RX_CPLT_CB_ID : - hmmc->RxCpltCallback = pCallback; - break; - case HAL_MMC_ERROR_CB_ID : - hmmc->ErrorCallback = pCallback; - break; - case HAL_MMC_ABORT_CB_ID : - hmmc->AbortCpltCallback = pCallback; - break; - case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID : - hmmc->Read_DMADblBuf0CpltCallback = pCallback; - break; - case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID : - hmmc->Read_DMADblBuf1CpltCallback = pCallback; - break; - case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : - hmmc->Write_DMADblBuf0CpltCallback = pCallback; - break; - case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : - hmmc->Write_DMADblBuf1CpltCallback = pCallback; - break; - case HAL_MMC_MSP_INIT_CB_ID : - hmmc->MspInitCallback = pCallback; - break; - case HAL_MMC_MSP_DEINIT_CB_ID : - hmmc->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_MMC_TX_CPLT_CB_ID : + hmmc->TxCpltCallback = pCallback; + break; + case HAL_MMC_RX_CPLT_CB_ID : + hmmc->RxCpltCallback = pCallback; + break; + case HAL_MMC_ERROR_CB_ID : + hmmc->ErrorCallback = pCallback; + break; + case HAL_MMC_ABORT_CB_ID : + hmmc->AbortCpltCallback = pCallback; + break; + case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hmmc->Read_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hmmc->Read_DMADblBuf1CpltCallback = pCallback; + break; + case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hmmc->Write_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hmmc->Write_DMADblBuf1CpltCallback = pCallback; + break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = pCallback; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else if (hmmc->State == HAL_MMC_STATE_RESET) { switch (CallbackId) { - case HAL_MMC_MSP_INIT_CB_ID : - hmmc->MspInitCallback = pCallback; - break; - case HAL_MMC_MSP_DEINIT_CB_ID : - hmmc->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = pCallback; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1816,64 +1983,64 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca /* Process locked */ __HAL_LOCK(hmmc); - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { switch (CallbackId) { - case HAL_MMC_TX_CPLT_CB_ID : - hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; - break; - case HAL_MMC_RX_CPLT_CB_ID : - hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; - break; - case HAL_MMC_ERROR_CB_ID : - hmmc->ErrorCallback = HAL_MMC_ErrorCallback; - break; - case HAL_MMC_ABORT_CB_ID : - hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; - break; - case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID : - hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuf0CpltCallback; - break; - case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID : - hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuf1CpltCallback; - break; - case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : - hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuf0CpltCallback; - break; - case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : - hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuf1CpltCallback; - break; - case HAL_MMC_MSP_INIT_CB_ID : - hmmc->MspInitCallback = HAL_MMC_MspInit; - break; - case HAL_MMC_MSP_DEINIT_CB_ID : - hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; - break; - default : - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_MMC_TX_CPLT_CB_ID : + hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; + break; + case HAL_MMC_RX_CPLT_CB_ID : + hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; + break; + case HAL_MMC_ERROR_CB_ID : + hmmc->ErrorCallback = HAL_MMC_ErrorCallback; + break; + case HAL_MMC_ABORT_CB_ID : + hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; + break; + case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuf0CpltCallback; + break; + case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuf1CpltCallback; + break; + case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuf0CpltCallback; + break; + case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuf1CpltCallback; + break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = HAL_MMC_MspInit; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else if (hmmc->State == HAL_MMC_STATE_RESET) { switch (CallbackId) { - case HAL_MMC_MSP_INIT_CB_ID : - hmmc->MspInitCallback = HAL_MMC_MspInit; - break; - case HAL_MMC_MSP_DEINIT_CB_ID : - hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; - break; - default : - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = HAL_MMC_MspInit; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1895,8 +2062,8 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca */ /** @addtogroup MMC_Exported_Functions_Group3 - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### Peripheral Control functions ##### @@ -1980,12 +2147,12 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp pCSD->Reserved2 = 0U; /*!< Reserved */ - if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */ + if (MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */ { return HAL_ERROR; } - if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD) + if (hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD) { pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U)); @@ -2003,10 +2170,10 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); + hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); hmmc->MmcCard.LogBlockSize = 512U; } - else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD) + else if (hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD) { hmmc->MmcCard.BlockNbr = block_nbr; hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr; @@ -2034,7 +2201,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U); - pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U); + pCSD->MaxWrBlockLen = (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U); pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U); @@ -2052,7 +2219,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U); - pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U); + pCSD->ECC = (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U); pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U); @@ -2081,6 +2248,126 @@ HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoT return HAL_OK; } +/** + * @brief Returns information the information of the card which are stored on + * the Extended CSD register. + * @param hmmc Pointer to MMC handle + * @param pExtCSD Pointer to a memory area (512 bytes) that contains all + * Extended CSD register parameters + * @param Timeout Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t *tmp_buf; + + if (NULL == pExtCSD) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if (hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + /* Initiaize the destination pointer */ + tmp_buf = pExtCSD; + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 512; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_DISABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); + + /* Send ExtCSD Read command to Card */ + errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); + if (errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | + SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) + { + /* Read data from SDMMC Rx FIFO */ + for (count = 0U; count < 8U; count++) + { + *tmp_buf = SDMMC_ReadFIFO(hmmc->Instance); + tmp_buf++; + } + } + + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); + + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + hmmc->State = HAL_MMC_STATE_READY; + } + + return HAL_OK; +} + /** * @brief Enables wide bus operation for the requested card if supported by * card. @@ -2102,78 +2389,95 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 /* Check the parameters */ assert_param(IS_SDMMC_BUS_WIDE(WideMode)); - /* Chnage Satte */ + /* Change State */ hmmc->State = HAL_MMC_STATE_BUSY; - if(WideMode == SDMMC_BUS_WIDE_8B) + /* Check and update the power class if needed */ + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); - } - else if(WideMode == SDMMC_BUS_WIDE_4B) - { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); - } - else if(WideMode == SDMMC_BUS_WIDE_1B) - { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); - } - else - { - /* WideMode is not a valid argument*/ - errorstate = HAL_MMC_ERROR_PARAM; - } - - /* Check for switch error and violation of the trial number of sending CMD 13 */ - if(errorstate == HAL_MMC_ERROR_NONE) - { - /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - count = SDMMC_MAX_TRIAL; - do + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U) { - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) - { - break; - } - - /* Get command response */ - response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); - count--; - }while(((response & 0x100U) == 0U) && (count != 0U)); - - /* Check the status after the switch command execution */ - if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) - { - /* Check the bit SWITCH_ERROR of the device status */ - if ((response & 0x80U) != 0U) - { - errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; - } - else - { - /* Configure the SDMMC peripheral */ - Init.ClockEdge = hmmc->Init.ClockEdge; - Init.ClockPowerSave = hmmc->Init.ClockPowerSave; - Init.BusWide = WideMode; - Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl; - Init.ClockDiv = hmmc->Init.ClockDiv; - (void)SDMMC_Init(hmmc->Instance, Init); - } - } - else if (count == 0U) - { - errorstate = SDMMC_ERROR_TIMEOUT; + errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DDR); } else { - /* Nothing to do */ + errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_HIGH); + } + } + else + { + errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DEFAULT); + } + + if (errorstate == HAL_MMC_ERROR_NONE) + { + if (WideMode == SDMMC_BUS_WIDE_8B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); + } + else if (WideMode == SDMMC_BUS_WIDE_4B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); + } + else if (WideMode == SDMMC_BUS_WIDE_1B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); + } + else + { + /* WideMode is not a valid argument*/ + errorstate = HAL_MMC_ERROR_PARAM; + } + + /* Check for switch error and violation of the trial number of sending CMD 13 */ + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + else + { + /* Configure the SDMMC peripheral */ + Init = hmmc->Init; + Init.BusWide = WideMode; + (void)SDMMC_Init(hmmc->Instance, Init); + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } } } /* Change State */ hmmc->State = HAL_MMC_STATE_READY; - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -2205,14 +2509,13 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 /* Check the parameters */ assert_param(IS_SDMMC_SPEED_MODE(SpeedMode)); + /* Change State */ hmmc->State = HAL_MMC_STATE_BUSY; - if(MMC_ReadExtCSD(hmmc, &device_type, 196, 0x0FFFFFFFU) != HAL_OK) /* Field DEVICE_TYPE [196] */ - { - return HAL_ERROR; - } - + /* Field DEVICE_TYPE [196 = 49*4] of Extended CSD register */ + device_type = (hmmc->Ext_CSD[49] & 0x000000FFU); + switch (SpeedMode) { case SDMMC_SPEED_MODE_AUTO: @@ -2221,16 +2524,20 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed DDR mode allowed */ errorstate = MMC_HighSpeed(hmmc, ENABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } else { - errorstate = MMC_DDR_Mode(hmmc, ENABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U) { - hmmc->ErrorCode |= errorstate; + /* DDR mode not supported with CLKDIV = 0 */ + errorstate = MMC_DDR_Mode(hmmc, ENABLE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } } } } @@ -2238,7 +2545,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed mode allowed */ errorstate = MMC_HighSpeed(hmmc, ENABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } @@ -2255,16 +2562,20 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed DDR mode allowed */ errorstate = MMC_HighSpeed(hmmc, ENABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } else { - errorstate = MMC_DDR_Mode(hmmc, ENABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U) { - hmmc->ErrorCode |= errorstate; + /* DDR mode not supported with CLKDIV = 0 */ + errorstate = MMC_DDR_Mode(hmmc, ENABLE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } } } } @@ -2272,7 +2583,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed DDR mode not allowed */ hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE; - status = HAL_ERROR; + status = HAL_ERROR; } break; } @@ -2282,7 +2593,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed mode allowed */ errorstate = MMC_HighSpeed(hmmc, ENABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } @@ -2291,7 +2602,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed mode not allowed */ hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE; - status = HAL_ERROR; + status = HAL_ERROR; } break; } @@ -2301,7 +2612,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed DDR mode activated */ errorstate = MMC_DDR_Mode(hmmc, DISABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } @@ -2310,7 +2621,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed mode activated */ errorstate = MMC_HighSpeed(hmmc, DISABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } @@ -2352,7 +2663,7 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) uint32_t resp1 = 0U; errorstate = MMC_SendStatus(hmmc, &resp1); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } @@ -2373,8 +2684,8 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) HAL_MMC_CardStateTypeDef CardState; /* DIsable All interrupts */ - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); /* Clear All flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); @@ -2388,11 +2699,11 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) hmmc->Context = MMC_CONTEXT_NONE; CardState = HAL_MMC_GetCardState(hmmc); - if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) { hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); } - if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE) { return HAL_ERROR; } @@ -2410,8 +2721,8 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) HAL_MMC_CardStateTypeDef CardState; /* DIsable All interrupts */ - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); /* If IDMA Context, disable Internal DMA */ hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; @@ -2422,11 +2733,11 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) CardState = HAL_MMC_GetCardState(hmmc); hmmc->State = HAL_MMC_STATE_READY; - if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) { hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); } - if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE) { return HAL_ERROR; } @@ -2449,17 +2760,20 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) * @param hmmc Pointer to MMC handle * @param EraseType Specifies the type of erase to be performed * This parameter can be one of the following values: - * @arg HAL_MMC_ERASE Erase the erase groups identified by CMD35 & 36 - * @arg HAL_MMC_TRIM Erase the write blocks identified by CMD35 & 36 - * @arg HAL_MMC_DISCARD Discard the write blocks identified by CMD35 & 36 - * @arg HAL_MMC_SECURE_ERASE Perform a secure purge according SRT on the erase groups identified by CMD35 & 36 - * @arg HAL_MMC_SECURE_TRIM_STEP1 Mark the write blocks identified by CMD35 & 36 for secure erase - * @arg HAL_MMC_SECURE_TRIM_STEP2 Perform a secure purge according SRT on the write blocks previously identified + * @arg HAL_MMC_TRIM Erase the write blocks identified by CMD35 & 36 + * @arg HAL_MMC_ERASE Erase the erase groups identified by CMD35 & 36 + * @arg HAL_MMC_DISCARD Discard the write blocks identified by CMD35 & 36 + * @arg HAL_MMC_SECURE_ERASE Perform a secure purge according SRT on the erase groups identified + * by CMD35 & 36 + * @arg HAL_MMC_SECURE_TRIM_STEP1 Mark the write blocks identified by CMD35 & 36 for secure erase + * @arg HAL_MMC_SECURE_TRIM_STEP2 Perform a secure purge according SRT on the write blocks + * previously identified * @param BlockStartAdd Start Block address * @param BlockEndAdd End Block address * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, uint32_t BlockEndAdd) +HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, + uint32_t BlockStartAdd, uint32_t BlockEndAdd) { uint32_t errorstate; uint32_t start_add = BlockStartAdd; @@ -2470,34 +2784,45 @@ HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseT assert_param(IS_MMC_ERASE_TYPE(EraseType)); /* Check the coherence between start and end address */ - if(end_add < start_add) + if (end_add < start_add) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } /* Check that the end address is not out of range of device memory */ - if(end_add > (hmmc->MmcCard.LogBlockNbr)) + if (end_add > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U)) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + /* Check if the card command class supports erase command */ - if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) + if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) { hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; return HAL_ERROR; } /* Check the state of the driver */ - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { /* Change State */ hmmc->State = HAL_MMC_STATE_BUSY; /* Check that the card is not locked */ - if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED; hmmc->State = HAL_MMC_STATE_READY; @@ -2513,22 +2838,22 @@ HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseT /* Send CMD35 MMC_ERASE_GRP_START with start address as argument */ errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* Send CMD36 MMC_ERASE_GRP_END with end address as argument */ errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* Send CMD38 ERASE with erase type as argument */ errorstate = SDMMC_CmdErase(hmmc->Instance, EraseType); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { if ((EraseType == HAL_MMC_SECURE_ERASE) || (EraseType == HAL_MMC_SECURE_TRIM_STEP2)) { /* Wait that the device is ready by checking the D0 line */ - while((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) { - if((HAL_GetTick()-tickstart) >= SDMMC_MAXERASETIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT) { errorstate = HAL_MMC_ERROR_TIMEOUT; } @@ -2545,13 +2870,13 @@ HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseT hmmc->State = HAL_MMC_STATE_READY; /* Manage errors */ - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; - if(errorstate != HAL_MMC_ERROR_TIMEOUT) + if (errorstate != HAL_MMC_ERROR_TIMEOUT) { return HAL_ERROR; } @@ -2584,19 +2909,19 @@ HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc) uint32_t tickstart = HAL_GetTick(); /* Check the state of the driver */ - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { /* Change State */ hmmc->State = HAL_MMC_STATE_BUSY; /* Index : 165 - Value : 0x01 */ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03A50100U); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* Wait that the device is ready by checking the D0 line */ - while((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) { - if((HAL_GetTick()-tickstart) >= SDMMC_MAXERASETIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT) { errorstate = HAL_MMC_ERROR_TIMEOUT; } @@ -2605,14 +2930,14 @@ HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc) /* Clear the flag corresponding to end D0 bus line */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ count = SDMMC_MAX_TRIAL; do { errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { break; } @@ -2620,7 +2945,7 @@ HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc) /* Get command response */ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); count--; - }while(((response & 0x100U) == 0U) && (count != 0U)); + } while (((response & 0x100U) == 0U) && (count != 0U)); /* Check the status after the switch command execution */ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) @@ -2646,13 +2971,13 @@ HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc) hmmc->State = HAL_MMC_STATE_READY; /* Manage errors */ - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; - if(errorstate != HAL_MMC_ERROR_TIMEOUT) + if (errorstate != HAL_MMC_ERROR_TIMEOUT) { return HAL_ERROR; } @@ -2680,8 +3005,10 @@ HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc) * @param SRTMode Specifies the type of erase to be performed * This parameter can be one of the following values: * @arg HAL_MMC_SRT_ERASE Information removed by an erase - * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed by an erase - * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, its complement then a random character + * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character + * followed by an erase + * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, + * its complement then a random character * @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined * @retval HAL status */ @@ -2693,28 +3020,28 @@ HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t assert_param(IS_MMC_SRT_TYPE(SRTMode)); /* Check the state of the driver */ - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { /* Get the supported values by the device */ - if(HAL_MMC_GetSupportedSecRemovalType(hmmc, &srt) == HAL_OK) + if (HAL_MMC_GetSupportedSecRemovalType(hmmc, &srt) == HAL_OK) { /* Change State */ hmmc->State = HAL_MMC_STATE_BUSY; /* Check the value passed as parameter is supported by the device */ - if((SRTMode & srt) != 0U) + if ((SRTMode & srt) != 0U) { /* Index : 16 - Value : SRTMode */ srt |= ((POSITION_VAL(SRTMode)) << 4U); errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03100000U | (srt << 8U))); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ count = SDMMC_MAX_TRIAL; do { errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { break; } @@ -2722,7 +3049,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t /* Get command response */ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); count--; - }while(((response & 0x100U) == 0U) && (count != 0U)); + } while (((response & 0x100U) == 0U) && (count != 0U)); /* Check the status after the switch command execution */ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) @@ -2757,7 +3084,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t } /* Manage errors */ - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -2781,47 +3108,28 @@ HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t * @param SupportedSRT pointer for supported SRT value * This parameter is a bit field of the following values: * @arg HAL_MMC_SRT_ERASE Information removed by an erase - * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed by an erase - * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, its complement then a random character + * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed + * by an erase + * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, + * its complement then a random character * @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT) { - uint32_t srt = 0U; - uint32_t errorstate = SDMMC_ERROR_NONE; - /* Check the state of the driver */ - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { /* Change State */ hmmc->State = HAL_MMC_STATE_BUSY; - /* Read the Extended CSD register and get expected value */ - if(MMC_ReadExtCSD(hmmc, &srt, 16, 0x0FFFFFFFU) == HAL_OK) /* Field SECURE_REMOVAL_TYPE [16] */ - { - *SupportedSRT = (srt & 0x0000000FU); /* Bits [3:0] of field 16 */ - } - else - { - errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; - } + /* Read field SECURE_REMOVAL_TYPE [16 = 4*4] of the Extended CSD register */ + *SupportedSRT = (hmmc->Ext_CSD[4] & 0x0000000FU); /* Bits [3:0] of field 16 */ /* Change State */ hmmc->State = HAL_MMC_STATE_READY; - /* Manage errors */ - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - return HAL_ERROR; - } - else - { - return HAL_OK; - } + return HAL_OK; } else { @@ -2852,11 +3160,11 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) { HAL_MMC_CardCSDTypeDef CSD; uint32_t errorstate; - uint16_t mmc_rca = 1U; + uint16_t mmc_rca = 2U; MMC_InitTypeDef Init; /* Check the power State */ - if(SDMMC_GetPowerState(hmmc->Instance) == 0U) + if (SDMMC_GetPowerState(hmmc->Instance) == 0U) { /* Power off */ return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; @@ -2864,7 +3172,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Send CMD2 ALL_SEND_CID */ errorstate = SDMMC_CmdSendCID(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } @@ -2877,10 +3185,10 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); } - /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */ /* MMC Card publishes its RCA. */ - errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca); - if(errorstate != HAL_MMC_ERROR_NONE) + errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca); + if (errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } @@ -2890,7 +3198,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Send CMD9 SEND_CSD with argument as card's RCA */ errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } @@ -2906,9 +3214,9 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Get the Card Class */ hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U); - /* Select the Card */ + /* Select the Card */ errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } @@ -2921,17 +3229,28 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + + /* Get Extended CSD parameters */ + if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK) + { + return hmmc->ErrorCode; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } /* Configure the SDMMC peripheral */ - Init.ClockEdge = hmmc->Init.ClockEdge; - Init.ClockPowerSave = hmmc->Init.ClockPowerSave; - Init.BusWide = SDMMC_BUS_WIDE_1B; - Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl; - Init.ClockDiv = hmmc->Init.ClockDiv; + Init = hmmc->Init; + Init.BusWide = SDMMC_BUS_WIDE_1B; (void)SDMMC_Init(hmmc->Instance, Init); /* All cards are initialized */ @@ -2953,21 +3272,21 @@ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } - while(validvoltage == 0U) + while (validvoltage == 0U) { - if(count++ == SDMMC_MAX_VOLT_TRIAL) + if (count++ == SDMMC_MAX_VOLT_TRIAL) { return HAL_MMC_ERROR_INVALID_VOLTRANGE; } - /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */ - errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE); - if(errorstate != HAL_MMC_ERROR_NONE) + /* SEND CMD1 APP_CMD with voltage range as argument */ + errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE); + if (errorstate != HAL_MMC_ERROR_NONE) { return HAL_MMC_ERROR_UNSUPPORTED_FEATURE; } @@ -3014,14 +3333,14 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) { uint32_t errorstate; - if(pCardStatus == NULL) + if (pCardStatus == NULL) { return HAL_MMC_ERROR_PARAM; } /* Send Status command */ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } @@ -3040,7 +3359,8 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout) +static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, + uint16_t FieldIndex, uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -3065,7 +3385,7 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, /* Set Block Size for Card */ errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -3075,17 +3395,17 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, } /* Poll on SDMMC flags */ - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) { /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { tmp_data = SDMMC_ReadFIFO(hmmc->Instance); - /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ - /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */ - if ((i + count) == ((uint32_t)FieldIndex/4U)) + /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ + /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */ + if ((i + count) == ((uint32_t)FieldIndex / 4U)) { *pFieldData = tmp_data; } @@ -3093,19 +3413,49 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, i += 8U; } - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; - hmmc->State= HAL_MMC_STATE_READY; + hmmc->State = HAL_MMC_STATE_READY; return HAL_TIMEOUT; } } + /* Get error state */ + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } @@ -3127,14 +3477,14 @@ HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) { uint32_t count, data; - uint8_t* tmp; + uint8_t *tmp; tmp = hmmc->pRxBuffPtr; if (hmmc->RxXferSize >= 32U) { /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = SDMMC_ReadFIFO(hmmc->Instance); *tmp = (uint8_t)(data & 0xFFU); @@ -3161,14 +3511,14 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) { uint32_t count, data; - uint8_t* tmp; + uint8_t *tmp; tmp = hmmc->pTxBuffPtr; if (hmmc->TxXferSize >= 32U) { /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = (uint32_t)(*tmp); tmp++; @@ -3196,28 +3546,37 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) { uint32_t errorstate = HAL_MMC_ERROR_NONE; uint32_t response = 0U, count; + uint32_t sdmmc_clk; SDMMC_InitTypeDef Init; if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE)) { - /* Index : 185 - Value : 0 */ - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U); - } - - if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE)) - { - /* Index : 185 - Value : 1 */ - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U); + errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_DEFAULT); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Index : 185 - Value : 0 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U); + } } - if(errorstate == HAL_MMC_ERROR_NONE) + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE)) + { + errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_HIGH); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Index : 185 - Value : 1 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U); + } + } + + if (errorstate == HAL_MMC_ERROR_NONE) { /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ count = SDMMC_MAX_TRIAL; do { errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { break; } @@ -3225,7 +3584,7 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) /* Get command response */ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); count--; - }while(((response & 0x100U) == 0U) && (count != 0U)); + } while (((response & 0x100U) == 0U) && (count != 0U)); /* Check the status after the switch command execution */ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) @@ -3247,15 +3606,24 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) { Init.ClockDiv = hmmc->Init.ClockDiv; (void)SDMMC_Init(hmmc->Instance, Init); - + CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED); } else { - Init.ClockDiv = SDMMC_HSpeed_CLK_DIV; - (void)SDMMC_Init(hmmc->Instance, Init); - - SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED); + /* High Speed Clock should be less or equal to 52MHz*/ + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); + if (sdmmc_clk == 0U) + { + errorstate = SDMMC_ERROR_INVALID_PARAMETER; + } + else + { + Init.ClockDiv = sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ); + (void)SDMMC_Init(hmmc->Instance, Init); + + SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED); + } } } } @@ -3287,38 +3655,54 @@ static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) { if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U) { - /* Index : 183 - Value : 1 */ - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); + errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_HIGH); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Index : 183 - Value : 1 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); + } } else { - /* Index : 183 - Value : 2 */ - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); + errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_HIGH); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Index : 183 - Value : 2 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); + } } } - + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) && (state != DISABLE)) { if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U) { - /* Index : 183 - Value : 5 */ - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U); + errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_DDR); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Index : 183 - Value : 5 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U); + } } else { - /* Index : 183 - Value : 6 */ - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U); + errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_DDR); + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* Index : 183 - Value : 6 */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U); + } } } - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ count = SDMMC_MAX_TRIAL; do { errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { break; } @@ -3326,7 +3710,7 @@ static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) /* Get command response */ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); count--; - }while(((response & 0x100U) == 0U) && (count != 0U)); + } while (((response & 0x100U) == 0U) && (count != 0U)); /* Check the status after the switch command execution */ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) @@ -3362,6 +3746,109 @@ static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) return errorstate; } +/** + * @brief Update the power class of the device. + * @param hmmc MMC handle + * @param Wide Wide of MMC bus + * @param Speed Speed of the MMC bus + * @retval MMC Card error state + */ +static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed) +{ + uint32_t count; + uint32_t response = 0U; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t power_class, supported_pwr_class; + + if ((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B)) + { + power_class = 0U; /* Default value after power-on or software reset */ + + /* Read the PowerClass field of the Extended CSD register */ + if (MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */ + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + else + { + power_class = ((power_class >> 24U) & 0x000000FFU); + } + + /* Get the supported PowerClass field of the Extended CSD register */ + if (Speed == SDMMC_SPEED_MODE_DDR) + { + /* Field PWR_CL_DDR_52_xxx [238 or 239] */ + supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_DDR_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_DDR_52_POS) & + 0x000000FFU); + } + else if (Speed == SDMMC_SPEED_MODE_HIGH) + { + /* Field PWR_CL_52_xxx [200 or 202] */ + supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_52_POS) & + 0x000000FFU); + } + else + { + /* Field PWR_CL_26_xxx [201 or 203] */ + supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_26_POS) & + 0x000000FFU); + } + + if (errorstate == HAL_MMC_ERROR_NONE) + { + if (Wide == SDMMC_BUS_WIDE_8B) + { + /* Bit [7:4]: power class for 8-bits bus configuration - Bit [3:0]: power class for 4-bits bus configuration */ + supported_pwr_class = (supported_pwr_class >> 4U); + } + + if ((power_class & 0x0FU) != (supported_pwr_class & 0x0FU)) + { + /* Need to change current power class */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U))); + + if (errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if (errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + } while (((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + } + } + + return errorstate; +} + /** * @brief Read DMA Buffer 0 Transfer completed callbacks * @param hmmc: MMC handle diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.h index b3dc7cc114..db25542b36 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc.h @@ -15,14 +15,14 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32H7xx_HAL_MMC_H #define STM32H7xx_HAL_MMC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -52,9 +52,9 @@ typedef enum HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */ HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */ HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */ - HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */ + HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfer State */ HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */ -}HAL_MMC_StateTypeDef; +} HAL_MMC_StateTypeDef; /** * @} */ @@ -102,7 +102,7 @@ typedef struct uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ -}HAL_MMC_CardInfoTypeDef; +} HAL_MMC_CardInfoTypeDef; /** * @brief MMC handle Structure definition @@ -142,19 +142,19 @@ typedef struct uint32_t Ext_CSD[128]; #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* Read_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* Read_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* Write_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* Write_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* TxCpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* RxCpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* ErrorCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* AbortCpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* Read_DMADblBuf0CpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* Read_DMADblBuf1CpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* Write_DMADblBuf0CpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* Write_DMADblBuf1CpltCallback)(struct __MMC_HandleTypeDef *hmmc); - void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc); -#endif -}MMC_HandleTypeDef; + void (* MspInitCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* MspDeInitCallback)(struct __MMC_HandleTypeDef *hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ +} MMC_HandleTypeDef; /** @@ -204,7 +204,7 @@ typedef struct __IO uint8_t CSD_CRC; /*!< CSD CRC */ __IO uint8_t Reserved4; /*!< Always 1 */ -}HAL_MMC_CardCSDTypeDef; +} HAL_MMC_CardCSDTypeDef; /** * @} */ @@ -225,7 +225,7 @@ typedef struct __IO uint8_t CID_CRC; /*!< CID CRC */ __IO uint8_t Reserved2; /*!< Always 1 */ -}HAL_MMC_CardCIDTypeDef; +} HAL_MMC_CardCIDTypeDef; /** * @} */ @@ -247,7 +247,7 @@ typedef enum HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */ HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */ -}HAL_MMC_CallbackIDTypeDef; +} HAL_MMC_CallbackIDTypeDef; /** * @} */ @@ -255,11 +255,11 @@ typedef enum /** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition * @{ */ -typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); +typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); /** * @} */ -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @} */ @@ -282,13 +282,13 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); #define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ #define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ #define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ -#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the - number of transferred bytes does not match the block length */ +#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ +/*!< number of transferred bytes does not match the block length */ #define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ #define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ #define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ -#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock - command or if there was an attempt to access a locked card */ +#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ +/*!< command or if there was an attempt to access a locked card */ #define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ #define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ #define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ @@ -299,8 +299,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); #define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ #define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ #define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ -#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out - of erase sequence command was received */ +#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ +/*!< of erase sequence command was received */ #define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ #define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ #define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ @@ -313,7 +313,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) #define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @} */ @@ -339,10 +339,12 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); /** * @brief */ -#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */ -#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */ -#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */ -#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */ +#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */ +#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */ +#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */ +#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */ +#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */ +#define eMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */ #define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U /** * @} @@ -401,22 +403,22 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); /* Exported macro ------------------------------------------------------------*/ /** @defgroup MMC_Exported_macros MMC Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ /** @brief Reset MMC handle state. * @param __HANDLE__ MMC Handle. * @retval None */ #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) #define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_MMC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_MMC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET) -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @brief Enable the MMC device interrupt. @@ -630,7 +632,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); */ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc); HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc); void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc); void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); @@ -642,15 +644,21 @@ void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); * @{ */ /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout); HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); /* Non-Blocking mode: IT */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); @@ -662,9 +670,10 @@ void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc); #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) /* MMC callback registering/unregistering */ -HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, + pMMC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @} */ @@ -685,6 +694,7 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); /** * @} */ @@ -710,7 +720,8 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); /** @defgroup MMC_Exported_Functions_Group7 Peripheral Erase management * @{ */ -HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, + uint32_t BlockEndAdd); HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc); HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode); HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT); @@ -731,7 +742,8 @@ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, ui /** @defgroup MMC_Private_Defines MMC Private Defines * @{ */ - +#define MMC_EXT_CSD_DATA_SEC_SIZE_INDEX 61 +#define MMC_EXT_CSD_DATA_SEC_SIZE_POS 8 /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.c index 6c404ca86d..f392a54243 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.c @@ -15,7 +15,8 @@ The MMC Extension HAL driver can be used as follows: (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function. - (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions. + (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and + HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions. @endverbatim ****************************************************************************** @@ -60,8 +61,8 @@ /** @addtogroup MMCEx_Exported_Functions_Group1 - * @brief Multibuffer functions - * + * @brief Multibuffer functions + * @verbatim ============================================================================== ##### Multibuffer functions ##### @@ -77,18 +78,19 @@ /** * @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA. * @param hmmc: MMC handle - * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data - * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data + * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transferred data + * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transferred data * @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size. * @retval HAL status */ -HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize) +HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0, + uint32_t *pDataBuffer1, uint32_t BufferSize) { - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { - hmmc->Instance->IDMABASE0= (uint32_t) pDataBuffer0 ; - hmmc->Instance->IDMABASE1= (uint32_t) pDataBuffer1 ; - hmmc->Instance->IDMABSIZE= (uint32_t) (MMC_BLOCKSIZE * BufferSize); + hmmc->Instance->IDMABASE0 = (uint32_t) pDataBuffer0 ; + hmmc->Instance->IDMABASE1 = (uint32_t) pDataBuffer1 ; + hmmc->Instance->IDMABSIZE = (uint32_t)(MMC_BLOCKSIZE * BufferSize); return HAL_OK; } @@ -100,27 +102,48 @@ HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32 /** * @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1. - * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before + * call this function. * @param hmmc: MMC handle * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t DmaBase0_reg; + uint32_t DmaBase1_reg; uint32_t errorstate; uint32_t add = BlockAdd; - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + DmaBase0_reg = hmmc->Instance->IDMABASE0; DmaBase1_reg = hmmc->Instance->IDMABASE1; @@ -152,7 +175,7 @@ HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, ui hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; @@ -161,14 +184,15 @@ HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, ui /* Read Multi Block command */ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->State = HAL_MMC_STATE_READY; hmmc->ErrorCode |= errorstate; return HAL_ERROR; } - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); return HAL_OK; } @@ -180,28 +204,49 @@ HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, ui } /** - * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1. - * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function. + * @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before + * call this function. * @param hmmc: MMC handle * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status -*/ -HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks) + */ +HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; - uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t DmaBase0_reg; + uint32_t DmaBase1_reg; uint32_t add = BlockAdd; - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + DmaBase0_reg = hmmc->Instance->IDMABASE0; DmaBase1_reg = hmmc->Instance->IDMABASE1; @@ -232,7 +277,7 @@ HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, u config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; @@ -241,14 +286,15 @@ HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, u /* Write Multi Block command */ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->State = HAL_MMC_STATE_READY; hmmc->ErrorCode |= errorstate; return HAL_ERROR; } - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); return HAL_OK; } @@ -270,9 +316,10 @@ HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, u * transfer use BUFFER0. * @retval HAL status */ -HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer) +HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, + uint32_t *pDataBuffer) { - if(Buffer == MMC_DMA_BUFFER0) + if (Buffer == MMC_DMA_BUFFER0) { /* change the buffer0 address */ hmmc->Instance->IDMABASE0 = (uint32_t)pDataBuffer; diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.h index b5c9424666..256f986729 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_mmc_ex.h @@ -22,7 +22,7 @@ #define STM32H7xx_HAL_MMC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -50,7 +50,7 @@ typedef enum MMC_DMA_BUFFER0 = 0x00U, /*!< selects MMC internal DMA Buffer 0 */ MMC_DMA_BUFFER1 = 0x01U, /*!< selects MMC internal DMA Buffer 1 */ -}HAL_MMCEx_DMABuffer_MemoryTypeDef; +} HAL_MMCEx_DMABuffer_MemoryTypeDef; /** @@ -60,8 +60,6 @@ typedef enum /** * @} */ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions * @{ @@ -70,10 +68,14 @@ typedef enum /** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions * @{ */ -HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize); -HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer); +HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0, + uint32_t *pDataBuffer1, uint32_t BufferSize); +HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, + uint32_t *pDataBuffer); void HAL_MMCEx_Read_DMADoubleBuf0CpltCallback(MMC_HandleTypeDef *hmmc); void HAL_MMCEx_Read_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.c index 955556bc09..1b59059c3f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.c @@ -155,7 +155,8 @@ * @param AttSpace_Timing pointer to Attribute space timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, + FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) { /* Check the NAND handle state */ if (hnand == NULL) @@ -169,7 +170,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT hnand->Lock = HAL_UNLOCKED; #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - if(hnand->MspInitCallback == NULL) + if (hnand->MspInitCallback == NULL) { hnand->MspInitCallback = HAL_NAND_MspInit; } @@ -180,7 +181,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT #else /* Initialize the low level hardware (MSP) */ HAL_NAND_MspInit(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ } /* Initialize NAND control Interface */ @@ -194,7 +195,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT /* Enable the NAND device */ __FMC_NAND_ENABLE(hnand->Instance); - + /* Enable FMC Peripheral */ __FMC_ENABLE(); /* Update the NAND controller state */ @@ -212,7 +213,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) { #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - if(hnand->MspDeInitCallback == NULL) + if (hnand->MspDeInitCallback == NULL) { hnand->MspDeInitCallback = HAL_NAND_MspDeInit; } @@ -222,7 +223,7 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) #else /* Initialize the low level hardware (MSP) */ HAL_NAND_MspDeInit(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Configure the NAND registers with their reset values */ (void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank); @@ -274,7 +275,7 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status -*/ + */ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) { /* Check NAND interrupt Rising edge flag */ @@ -285,7 +286,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Rising edge pending bit */ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE); @@ -299,7 +300,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Level pending bit */ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL); @@ -313,7 +314,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Falling edge pending bit */ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE); @@ -327,7 +328,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt FIFO empty pending bit */ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT); @@ -381,7 +382,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN { __IO uint32_t data = 0; __IO uint32_t data1 = 0; - uint32_t deviceAddress; + uint32_t deviceaddress; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -397,18 +398,18 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Send Read ID command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; __DSB(); /* Read the electronic signature from NAND flash */ if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) { - data = *(__IO uint32_t *)deviceAddress; + data = *(__IO uint32_t *)deviceaddress; /* Return the data read */ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); @@ -418,8 +419,8 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN } else { - data = *(__IO uint32_t *)deviceAddress; - data1 = *((__IO uint32_t *)deviceAddress + 4); + data = *(__IO uint32_t *)deviceaddress; + data1 = *((__IO uint32_t *)deviceaddress + 4); /* Return the data read */ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); @@ -450,7 +451,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN */ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) { - uint32_t deviceAddress; + uint32_t deviceaddress; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -466,10 +467,10 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Send NAND reset command */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -515,12 +516,16 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesRead = 0U, nandAddress, nbpages = NumPageToRead; - uint8_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numpagesread = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -536,16 +541,16 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) read loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); /* Cards with page size <= 512 bytes */ @@ -553,22 +558,22 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -576,31 +581,31 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); @@ -625,25 +630,25 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint8_t *)deviceAddress; + *buff = *(uint8_t *)deviceaddress; buff++; } /* Increment read pages number */ - numPagesRead++; + numpagesread++; /* Decrement pages to read */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -669,12 +674,16 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead) +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToRead) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesRead = 0, nandAddress, nbpages = NumPageToRead; - uint16_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numpagesread = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -690,16 +699,16 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) read loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); /* Cards with page size <= 512 bytes */ @@ -707,22 +716,22 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -730,31 +739,31 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); if (hnand->Config.ExtraCommandEnable == ENABLE) @@ -778,25 +787,36 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } + /* Calculate PageSize */ + if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) + { + hnand->Config.PageSize = hnand->Config.PageSize / 2U; + } + else + { + /* Do nothing */ + /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ + } + /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint16_t *)deviceAddress; + *buff = *(uint16_t *)deviceaddress; buff++; } /* Increment read pages number */ - numPagesRead++; + numpagesread++; /* Decrement pages to read */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -822,12 +842,16 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite; - uint8_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numpageswritten = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -843,18 +867,18 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) write loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); /* Cards with page size <= 512 bytes */ @@ -862,22 +886,22 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -885,26 +909,26 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -912,12 +936,12 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address /* Write data to memory */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *(__IO uint8_t *)deviceAddress = *buff; + *(__IO uint8_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -939,13 +963,13 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address } /* Increment written pages number */ - numPagesWritten++; + numpageswritten++; /* Decrement pages to write */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -971,12 +995,16 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToWrite) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite; - uint16_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numpageswritten = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -992,18 +1020,18 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) write loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); /* Cards with page size <= 512 bytes */ @@ -1011,22 +1039,22 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1034,39 +1062,50 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } + /* Calculate PageSize */ + if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) + { + hnand->Config.PageSize = hnand->Config.PageSize / 2U; + } + else + { + /* Do nothing */ + /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ + } + /* Write data to memory */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *(__IO uint16_t *)deviceAddress = *buff; + *(__IO uint16_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -1088,13 +1127,13 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres } /* Increment written pages number */ - numPagesWritten++; + numpageswritten++; /* Decrement pages to write */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1119,13 +1158,18 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres * @param pBuffer pointer to source buffer to write * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) + */ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumSpareAreaToRead) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead; - uint8_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numsparearearead = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1141,78 +1185,78 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = COLUMN_ADDRESS(hnand); + columnaddress = COLUMN_ADDRESS(hnand); /* Spare area(s) read loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); if (hnand->Config.ExtraCommandEnable == ENABLE) @@ -1236,25 +1280,25 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint8_t *)deviceAddress; + *buff = *(uint8_t *)deviceaddress; buff++; } /* Increment read spare areas number */ - numSpareAreaRead++; + numsparearearead++; /* Decrement spare areas to read */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1279,13 +1323,18 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) + */ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaToRead) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead; - uint16_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numsparearearead = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1301,78 +1350,78 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U); + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); /* Spare area(s) read loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); if (hnand->Config.ExtraCommandEnable == ENABLE) @@ -1396,25 +1445,25 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint16_t *)deviceAddress; + *buff = *(uint16_t *)deviceaddress; buff++; } /* Increment read spare areas number */ - numSpareAreaRead++; + numsparearearead++; /* Decrement spare areas to read */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1440,12 +1489,17 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite; - uint8_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1461,77 +1515,77 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Page address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = COLUMN_ADDRESS(hnand); + columnaddress = COLUMN_ADDRESS(hnand); /* Spare area(s) write loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1539,12 +1593,12 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad /* Write data to memory */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *(__IO uint8_t *)deviceAddress = *buff; + *(__IO uint8_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -1566,13 +1620,13 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad } /* Increment written spare areas number */ - numSpareAreaWritten++; + numspareareawritten++; /* Decrement spare areas to write */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1598,12 +1652,17 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite; - uint16_t * buff = pBuffer; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1619,77 +1678,77 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U); + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); /* Spare area(s) write loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1697,12 +1756,12 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A /* Write data to memory */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *(__IO uint16_t *)deviceAddress = *buff; + *(__IO uint16_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -1724,13 +1783,13 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A } /* Increment written spare areas number */ - numSpareAreaWritten++; + numspareareawritten++; /* Decrement spare areas to write */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1756,7 +1815,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A */ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { - uint32_t DeviceAddress; + uint32_t deviceaddress; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1772,19 +1831,19 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - DeviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Send Erase block command sequence */ - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; __DSB(); /* Update the NAND controller state */ @@ -1851,11 +1910,12 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, + pNAND_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -1863,39 +1923,39 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND /* Process locked */ __HAL_LOCK(hnand); - if(hnand->State == HAL_NAND_STATE_READY) + if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = pCallback; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = pCallback; - break; - case HAL_NAND_IT_CB_ID : - hnand->ItCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = pCallback; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = pCallback; + break; + case HAL_NAND_IT_CB_ID : + hnand->ItCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hnand->State == HAL_NAND_STATE_RESET) + else if (hnand->State == HAL_NAND_STATE_RESET) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = pCallback; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = pCallback; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1920,46 +1980,46 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID * @retval status */ -HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hnand); - if(hnand->State == HAL_NAND_STATE_READY) + if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = HAL_NAND_MspInit; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = HAL_NAND_MspDeInit; - break; - case HAL_NAND_IT_CB_ID : - hnand->ItCallback = HAL_NAND_ITCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = HAL_NAND_MspInit; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = HAL_NAND_MspDeInit; + break; + case HAL_NAND_IT_CB_ID : + hnand->ItCallback = HAL_NAND_ITCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hnand->State == HAL_NAND_STATE_RESET) + else if (hnand->State == HAL_NAND_STATE_RESET) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = HAL_NAND_MspInit; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = HAL_NAND_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = HAL_NAND_MspInit; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = HAL_NAND_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1972,15 +2032,15 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NA __HAL_UNLOCK(hnand); return status; } -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### NAND Control functions ##### @@ -2100,8 +2160,8 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### NAND State functions ##### @@ -2134,17 +2194,17 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) { uint32_t data; - uint32_t DeviceAddress; + uint32_t deviceaddress; UNUSED(hnand); /* Identify the device address */ - DeviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Send Read status operation command */ - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; /* Read status register data */ - data = *(__IO uint8_t *)DeviceAddress; + data = *(__IO uint8_t *)deviceaddress; /* Return the status */ if ((data & NAND_ERROR) == NAND_ERROR) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.h index ccf984c4ea..3141ec9490 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nand.h @@ -89,10 +89,10 @@ typedef struct typedef struct { uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes - for 8 bits adressing or words for 16 bits addressing */ + for 8 bits addressing or words for 16 bits addressing */ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes - for 8 bits adressing or words for 16 bits addressing */ + for 8 bits addressing or words for 16 bits addressing */ uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ @@ -130,10 +130,10 @@ typedef struct NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */ - void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */ - void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */ -#endif + void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ + void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ + void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ } NAND_HandleTypeDef; #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) @@ -145,13 +145,13 @@ typedef enum HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ -}HAL_NAND_CallbackIDTypeDef; +} HAL_NAND_CallbackIDTypeDef; /** * @brief HAL NAND Callback pointer definition */ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} @@ -160,8 +160,8 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /** @defgroup NAND_Exported_Macros NAND Exported Macros - * @{ - */ + * @{ + */ /** @brief Reset NAND handle state * @param __HANDLE__ specifies the NAND handle. @@ -175,7 +175,7 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); } while(0) #else #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} @@ -191,7 +191,8 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, + FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); @@ -214,15 +215,23 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); /* IO operation functions ****************************************************/ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); @@ -230,9 +239,10 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressT #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /* NAND callback registering/unregistering */ -HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, + pNAND_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} @@ -277,19 +287,19 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); #define CMD_AREA (1UL<<16U) /* A16 = CLE high */ #define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ -#define NAND_CMD_AREA_A 0x00U -#define NAND_CMD_AREA_B 0x01U -#define NAND_CMD_AREA_C 0x50U -#define NAND_CMD_AREA_TRUE1 0x30U +#define NAND_CMD_AREA_A ((uint8_t)0x00) +#define NAND_CMD_AREA_B ((uint8_t)0x01) +#define NAND_CMD_AREA_C ((uint8_t)0x50) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) -#define NAND_CMD_WRITE0 0x80U -#define NAND_CMD_WRITE_TRUE1 0x10U -#define NAND_CMD_ERASE0 0x60U -#define NAND_CMD_ERASE1 0xD0U -#define NAND_CMD_READID 0x90U -#define NAND_CMD_STATUS 0x70U -#define NAND_CMD_LOCK_STATUS 0x7AU -#define NAND_CMD_RESET 0xFFU +#define NAND_CMD_WRITE0 ((uint8_t)0x80) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) +#define NAND_CMD_ERASE0 ((uint8_t)0x60) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0) +#define NAND_CMD_READID ((uint8_t)0x90) +#define NAND_CMD_STATUS ((uint8_t)0x70) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) +#define NAND_CMD_RESET ((uint8_t)0xFF) /* NAND memory status */ #define NAND_VALID_ADDRESS 0x00000100UL @@ -314,7 +324,8 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ - (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) + (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * \ + ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) /** * @brief NAND memory Column address computation. diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.c index 4a354aeb15..1fab108671 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.c @@ -150,9 +150,35 @@ #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 +#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF +#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040 +#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8 +#define NOR_CMD_CONFIRM (uint16_t)0x00D0 +#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020 +#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060 +#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070 +#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050 + /* Mask on NOR STATUS REGISTER */ +#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 +#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080 + +/* Address of the primary command set */ +#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013 + +/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */ +#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */ +#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */ +#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */ +#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */ +#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */ +#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */ +#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */ +#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */ +#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */ +#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */ /** * @} @@ -199,8 +225,11 @@ static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; * @param ExtTiming pointer to NOR extended mode timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming) { + uint32_t deviceaddress; + /* Check the NOR handle parameter */ if (hnor == NULL) { @@ -213,7 +242,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe hnor->Lock = HAL_UNLOCKED; #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - if(hnor->MspInitCallback == NULL) + if (hnor->MspInitCallback == NULL) { hnor->MspInitCallback = HAL_NOR_MspInit; } @@ -254,7 +283,29 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe /* Initialize the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; - return HAL_OK; + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Get the value of the command set */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + + return HAL_NOR_ReturnToReadMode(hnor); } /** @@ -266,7 +317,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) { #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - if(hnor->MspDeInitCallback == NULL) + if (hnor->MspDeInitCallback == NULL) { hnor->MspDeInitCallback = HAL_NOR_MspDeInit; } @@ -369,6 +420,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I { uint32_t deviceaddress; HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ state = hnor->State; @@ -403,15 +455,33 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I } /* Send read ID command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Read the NOR IDs */ - pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); - pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); - pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); - pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); + if (status != HAL_ERROR) + { + /* Read the NOR IDs */ + pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); + pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE1_ADDR); + pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE2_ADDR); + pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE3_ADDR); + } /* Check the NOR controller state */ hnor->State = state; @@ -424,7 +494,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -437,6 +507,7 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { uint32_t deviceaddress; HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ state = hnor->State; @@ -470,7 +541,19 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) deviceaddress = NOR_MEMORY_ADRESS4; } - NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } /* Check the NOR controller state */ hnor->State = state; @@ -483,7 +566,7 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -498,6 +581,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint { uint32_t deviceaddress; HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ state = hnor->State; @@ -532,12 +616,27 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint } /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Read the data */ - *pData = (uint16_t)(*(__IO uint32_t *)pAddress); + if (status != HAL_ERROR) + { + /* Read the data */ + *pData = (uint16_t)(*(__IO uint32_t *)pAddress); + } /* Check the NOR controller state */ hnor->State = state; @@ -550,7 +649,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -564,6 +663,7 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ if (hnor->State == HAL_NOR_STATE_BUSY) @@ -597,12 +697,27 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u } /* Send program data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } - /* Write the data */ - NOR_WRITE(pAddress, *pData); + if (status != HAL_ERROR) + { + /* Write the data */ + NOR_WRITE(pAddress, *pData); + } /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -615,7 +730,7 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -627,11 +742,15 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u * @param uwBufferSize number of Half word to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize) { - uint32_t deviceaddress, size = uwBufferSize, address = uwAddress; + uint32_t deviceaddress; + uint32_t size = uwBufferSize; + uint32_t address = uwAddress; uint16_t *data = pData; HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ state = hnor->State; @@ -666,17 +785,32 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress } /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); - - /* Read buffer */ - while (size > 0U) + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - *data = *(__IO uint16_t *)address; - data++; - address += 2U; - size--; + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + if (status != HAL_ERROR) + { + /* Read buffer */ + while (size > 0U) + { + *data = *(__IO uint16_t *)address; + data++; + address += 2U; + size--; + } } /* Check the NOR controller state */ @@ -690,7 +824,7 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -702,12 +836,14 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress * @param uwBufferSize Size of the buffer to write * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize) { uint16_t *p_currentaddress; const uint16_t *p_endaddress; uint16_t *data = pData; - uint32_t lastloadedaddress, deviceaddress; + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ if (hnor->State == HAL_NOR_STATE_BUSY) @@ -741,31 +877,51 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr } /* Initialize variables */ - p_currentaddress = (uint16_t *)(uwAddress); - p_endaddress = (const uint16_t *)(uwAddress + (uwBufferSize - 1U)); - lastloadedaddress = uwAddress; + p_currentaddress = (uint16_t *)(deviceaddress + uwAddress); + p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U))); - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - - /* Write Buffer Load Command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uint16_t)(uwBufferSize - 1U)); - - /* Load Data into NOR Buffer */ - while (p_currentaddress <= p_endaddress) + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - /* Store last loaded address & data value (for polling) */ - lastloadedaddress = (uint32_t)p_currentaddress; + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(p_currentaddress, *data); - - data++; - p_currentaddress ++; + /* Write Buffer Load Command */ + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); + NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + /* Write Buffer Load Command */ + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM); + NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; } - NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); + if (status != HAL_ERROR) + { + /* Load Data into NOR Buffer */ + while (p_currentaddress <= p_endaddress) + { + NOR_WRITE(p_currentaddress, *data); + + data++; + p_currentaddress ++; + } + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); + } + else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */ + { + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM); + } + } /* Check the NOR controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -778,7 +934,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr return HAL_ERROR; } - return HAL_OK; + return status; } @@ -793,6 +949,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) { uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; /* Check the NOR controller state */ if (hnor->State == HAL_NOR_STATE_BUSY) @@ -826,12 +983,30 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd } /* Send block erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK); + NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); + NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE); + NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -844,7 +1019,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd return HAL_ERROR; } - return HAL_OK; + return status; } @@ -858,6 +1033,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; UNUSED(Address); /* Check the NOR controller state */ @@ -892,12 +1068,23 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) } /* Send NOR chip erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } /* Check the NOR memory status and update the controller state */ hnor->State = HAL_NOR_STATE_READY; @@ -910,7 +1097,7 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) return HAL_ERROR; } - return HAL_OK; + return status; } /** @@ -992,12 +1179,13 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, + pNOR_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -1006,20 +1194,20 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal __HAL_LOCK(hnor); state = hnor->State; - if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) + if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_NOR_MSP_INIT_CB_ID : - hnor->MspInitCallback = pCallback; - break; - case HAL_NOR_MSP_DEINIT_CB_ID : - hnor->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NOR_MSP_INIT_CB_ID : + hnor->MspInitCallback = pCallback; + break; + case HAL_NOR_MSP_DEINIT_CB_ID : + hnor->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1043,7 +1231,7 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID * @retval status */ -HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; @@ -1052,20 +1240,20 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C __HAL_LOCK(hnor); state = hnor->State; - if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) + if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_NOR_MSP_INIT_CB_ID : - hnor->MspInitCallback = HAL_NOR_MspInit; - break; - case HAL_NOR_MSP_DEINIT_CB_ID : - hnor->MspDeInitCallback = HAL_NOR_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NOR_MSP_INIT_CB_ID : + hnor->MspInitCallback = HAL_NOR_MspInit; + break; + case HAL_NOR_MSP_DEINIT_CB_ID : + hnor->MspDeInitCallback = HAL_NOR_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1085,8 +1273,8 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C */ /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### NOR Control functions ##### @@ -1108,7 +1296,7 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) { /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_PROTECTED) + if (hnor->State == HAL_NOR_STATE_PROTECTED) { /* Process Locked */ __HAL_LOCK(hnor); @@ -1142,7 +1330,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) { /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_READY) + if (hnor->State == HAL_NOR_STATE_READY) { /* Process Locked */ __HAL_LOCK(hnor); @@ -1172,8 +1360,8 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) */ /** @defgroup NOR_Exported_Functions_Group4 NOR State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### NOR State functions ##### @@ -1209,7 +1397,8 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) { HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; - uint16_t tmpSR1, tmpSR2; + uint16_t tmpsr1; + uint16_t tmpsr2; uint32_t tickstart; /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ @@ -1219,45 +1408,84 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /* Get tick */ tickstart = HAL_GetTick(); - while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) + while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) { - status = HAL_NOR_STATUS_TIMEOUT; + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + status = HAL_NOR_STATUS_TIMEOUT; + } + } + + /* Read NOR status register (DQ6 and DQ5) */ + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) + { + return HAL_NOR_STATUS_SUCCESS ; + } + + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + { + status = HAL_NOR_STATUS_ONGOING; + } + + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) + { + return HAL_NOR_STATUS_SUCCESS; + } + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + { + return HAL_NOR_STATUS_ERROR; } } - - /* Read NOR status register (DQ6 and DQ5) */ - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; - - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + do { - return HAL_NOR_STATUS_SUCCESS ; - } + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + tmpsr2 = *(__IO uint16_t *)(Address); - if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) - { - status = HAL_NOR_STATUS_ONGOING; - } + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_NOR_STATUS_TIMEOUT; + } + } + } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U); - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; - - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + tmpsr1 = *(__IO uint16_t *)(Address); + if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U) { - return HAL_NOR_STATUS_SUCCESS; + /* Clear the Status Register */ + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + status = HAL_NOR_STATUS_ERROR; } - if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + else { - return HAL_NOR_STATUS_ERROR; + status = HAL_NOR_STATUS_SUCCESS; } } + else + { + /* Primary command set not supported by the driver */ + status = HAL_NOR_STATUS_ERROR; + } /* Return the operation status */ return status; diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.h index 04a3800716..d614cb0666 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_nor.h @@ -120,10 +120,12 @@ typedef struct __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ + uint32_t CommandSet; /*!< NOR algorithm command set and control */ + #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */ - void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */ -#endif + void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */ + void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */ +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ } NOR_HandleTypeDef; #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) @@ -134,13 +136,13 @@ typedef enum { HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */ HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */ -}HAL_NOR_CallbackIDTypeDef; +} HAL_NOR_CallbackIDTypeDef; /** * @brief HAL NOR Callback pointer definition */ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ @@ -162,7 +164,7 @@ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); } while(0) #else #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ @@ -177,7 +179,8 @@ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming); HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); @@ -196,8 +199,10 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); @@ -205,9 +210,10 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) /* NOR callback registering/unregistering */ -HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, + pNOR_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ @@ -251,23 +257,23 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres #define DEVICE_CODE3_ADDR ((uint16_t)0x000F) /* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x61) -#define CFI2_ADDRESS ((uint16_t)0x62) -#define CFI3_ADDRESS ((uint16_t)0x63) -#define CFI4_ADDRESS ((uint16_t)0x64) +#define CFI1_ADDRESS ((uint16_t)0x0061) +#define CFI2_ADDRESS ((uint16_t)0x0062) +#define CFI3_ADDRESS ((uint16_t)0x0063) +#define CFI4_ADDRESS ((uint16_t)0x0064) /* NOR operation wait timeout */ #define NOR_TMEOUT ((uint16_t)0xFFFF) /* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x0) -#define NOR_MEMORY_16B ((uint8_t)0x1) +#define NOR_MEMORY_8B ((uint8_t)0x00) +#define NOR_MEMORY_16B ((uint8_t)0x01) /* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000) -#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000) -#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000) -#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000) +#define NOR_MEMORY_ADRESS1 (0x60000000U) +#define NOR_MEMORY_ADRESS2 (0x64000000U) +#define NOR_MEMORY_ADRESS3 (0x68000000U) +#define NOR_MEMORY_ADRESS4 (0x6C000000U) /** * @} */ @@ -284,7 +290,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres * @retval NOR shifted address value */ #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ - ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ + ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.c index b76f805053..69cb96ecb1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.c @@ -23,201 +23,224 @@ *** Initialization *** ====================== [..] - (#) As prerequisite, fill in the HAL_OSPI_MspInit() : - (++) Enable OctoSPI and OctoSPIM clocks interface with __HAL_RCC_OSPIx_CLK_ENABLE(). - (++) Reset OctoSPI Peripheral with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET(). - (++) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). - (++) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init(). - (++) If interrupt or DMA mode is used, enable and configure OctoSPI global - interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (++) If DMA mode is used, enable the clocks for the OctoSPI DMA channel - with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), - link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure - DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (#) Configure the fifo threshold, the dual-quad mode, the memory type, the - device size, the CS high time, the free running clock, the clock mode, - the wrap size, the clock prescaler, the sample shifting, the hold delay - and the CS boundary using the HAL_OSPI_Init() function. - (#) When using Hyperbus, configure the RW recovery time, the access time, - the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg() - function. + As prerequisite, fill in the HAL_OSPI_MspInit() : + (+) Enable OctoSPI and OctoSPIM clocks interface with __HAL_RCC_OSPIx_CLK_ENABLE(). + (+) Reset OctoSPI Peripheral with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET(). + (+) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). + (+) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init(). + (+) If interrupt or DMA mode is used, enable and configure OctoSPI global + interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + (+) If DMA mode is used, enable the clocks for the OctoSPI DMA channel + with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), + link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure + DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). + [..] + Configure the fifo threshold, the dual-quad mode, the memory type, the + device size, the CS high time, the free running clock, the clock mode, + the wrap size, the clock prescaler, the sample shifting, the hold delay + and the CS boundary using the HAL_OSPI_Init() function. + [..] + When using Hyperbus, configure the RW recovery time, the access time, + the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg() + function. *** Indirect functional mode *** ================================ [..] - (#) In regular mode, configure the command sequence using the HAL_OSPI_Command() - or HAL_OSPI_Command_IT() functions : - (++) Instruction phase : the mode used and if present the size, the instruction - opcode and the DTR mode. - (++) Address phase : the mode used and if present the size, the address - value and the DTR mode. - (++) Alternate-bytes phase : the mode used and if present the size, the - alternate bytes values and the DTR mode. - (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). - (++) Data phase : the mode used and if present the number of bytes and the DTR mode. - (++) Data strobe (DQS) mode : the activation (or not) of this mode - (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. - (++) Flash identifier : in dual-quad mode, indicates which flash is concerned - (++) Operation type : always common configuration - (#) In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd() - function : - (++) Address space : indicate if the access will be done in register or memory - (++) Address size - (++) Number of data - (++) Data strobe (DQS) mode : the activation (or not) of this mode - (#) If no data is required for the command (only for regular mode, not for - Hyperbus mode), it is sent directly to the memory : - (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete. - (#) For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or - HAL_OSPI_Transmit_IT() after the command configuration : - (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold - is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and - HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. - (#) For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or - HAL_OSPI_Receive_IT() after the command configuration : - (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold - is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and - HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. + In regular mode, configure the command sequence using the HAL_OSPI_Command() + or HAL_OSPI_Command_IT() functions : + (+) Instruction phase : the mode used and if present the size, the instruction + opcode and the DTR mode. + (+) Address phase : the mode used and if present the size, the address + value and the DTR mode. + (+) Alternate-bytes phase : the mode used and if present the size, the + alternate bytes values and the DTR mode. + (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). + (+) Data phase : the mode used and if present the number of bytes and the DTR mode. + (+) Data strobe (DQS) mode : the activation (or not) of this mode + (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. + (+) Flash identifier : in dual-quad mode, indicates which flash is concerned + (+) Operation type : always common configuration + [..] + In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd() + function : + (+) Address space : indicate if the access will be done in register or memory + (+) Address size + (+) Number of data + (+) Data strobe (DQS) mode : the activation (or not) of this mode + [..] + If no data is required for the command (only for regular mode, not for + Hyperbus mode), it is sent directly to the memory : + (+) In polling mode, the output of the function is done when the transfer is complete. + (+) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete. + [..] + For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or + HAL_OSPI_Transmit_IT() after the command configuration : + (+) In polling mode, the output of the function is done when the transfer is complete. + (+) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. + (+) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and + HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. + [..] + For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or + HAL_OSPI_Receive_IT() after the command configuration : + (+) In polling mode, the output of the function is done when the transfer is complete. + (+) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold + is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. + (+) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and + HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. *** Auto-polling functional mode *** ==================================== [..] - (#) Configure the command sequence by the same way than the indirect mode - (#) Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling() - or HAL_OSPI_AutoPolling_IT() functions : - (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), - the polling interval and the automatic stop activation. - (#) After the configuration : - (++) In polling mode, the output of the function is done when the status match is reached. The - automatic stop is activated to avoid an infinite loop. - (++) In interrupt mode, HAL_OSPI_StatusMatchCallback() will be called each time the status match is reached. + Configure the command sequence by the same way than the indirect mode + [..] + Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling() + or HAL_OSPI_AutoPolling_IT() functions : + (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), + the polling interval and the automatic stop activation. + [..] + After the configuration : + (+) In polling mode, the output of the function is done when the status match is reached. The + automatic stop is activated to avoid an infinite loop. + (+) In interrupt mode, HAL_OSPI_StatusMatchCallback() will be called each time the status match is reached. + *** MDMA functional mode *** ==================================== [..] - (#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_OSPI_MspInit() function : - (++) MDMA settings for write operation : - (+) The DestinationInc should be MDMA_DEST_INC_DISABLE - (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD). - (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) + Configure the SourceInc and DestinationInc of MDMA parameters in the HAL_OSPI_MspInit() function : + (+) MDMA settings for write operation : + (++) The DestinationInc should be MDMA_DEST_INC_DISABLE + (++) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD). + (++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) aligned with @ref MDMA_Source_increment_mode . - (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) - (++) MDMA settings for read operation : - (+) The SourceInc should be MDMA_SRC_INC_DISABLE - (+) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD). - (+) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) . - (+) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) + (++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) + (+) MDMA settings for read operation : + (++) The SourceInc should be MDMA_SRC_INC_DISABLE + (++) The DestinationInc must be a value of @ref MDMA_Destination_increment_mode (Except the MDMA_DEST_INC_DOUBLEWORD). + (++) The SourceDataSize must be a value of @ref MDMA Source data size (Except the MDMA_SRC_DATASIZE_DOUBLEWORD) . + (++) The DestDataSize must be a value of @ref MDMA Destination data size (Except the MDMA_DEST_DATASIZE_DOUBLEWORD) aligned with @ref MDMA_Destination_increment_mode. - (++)The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Octospi. - (#)In case of wrong MDMA setting - (++) For write operation : - (+) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_OSPI_Transmit_DMA(). - (++) For read operation : - (+) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_OSPI_Receive_DMA(). + (+) The buffer Transfer Length (BufferTransferLength) = number of bytes in the FIFO (FifoThreshold) of the Octospi. + [..] + In case of wrong MDMA setting + (+) For write operation : + (++) If the DestinationInc is different to MDMA_DEST_INC_DISABLE , it will be disabled by the HAL_OSPI_Transmit_DMA(). + (+) For read operation : + (++) If the SourceInc is not set to MDMA_SRC_INC_DISABLE , it will be disabled by the HAL_OSPI_Receive_DMA(). *** Memory-mapped functional mode *** ===================================== [..] - (#) Configure the command sequence by the same way than the indirect mode except - for the operation type in regular mode : - (++) Operation type equals to read configuration : the command configuration - applies to read access in memory-mapped mode - (++) Operation type equals to write configuration : the command configuration - applies to write access in memory-mapped mode - (++) Both read and write configuration should be performed before activating - memory-mapped mode - (#) Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped() - functions : - (++) The timeout activation and the timeout period. - (#) After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on - the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires. + Configure the command sequence by the same way than the indirect mode except + for the operation type in regular mode : + (+) Operation type equals to read configuration : the command configuration + applies to read access in memory-mapped mode + (+) Operation type equals to write configuration : the command configuration + applies to write access in memory-mapped mode + (+) Both read and write configuration should be performed before activating + memory-mapped mode + [..] + Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped() + functions : + (+) The timeout activation and the timeout period. + [..] + After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on + the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires. *** Errors management and abort functionality *** ================================================= [..] - (#) HAL_OSPI_GetError() function gives the error raised during the last operation. - (#) HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and - flushes the fifo : - (++) In polling mode, the output of the function is done when the transfer - complete bit is set and the busy bit cleared. - (++) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when - the transfer complete bit is set. + HAL_OSPI_GetError() function gives the error raised during the last operation. + [..] + HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and + flushes the fifo : + (+) In polling mode, the output of the function is done when the transfer + complete bit is set and the busy bit cleared. + (+) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when + the transfer complete bit is set. *** Control functions *** ========================= [..] - (#) HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver. - (#) HAL_OSPI_SetTimeout() function configures the timeout value used in the driver. - (#) HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI Peripheral. - (#) HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold + HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver. + [..] + HAL_OSPI_SetTimeout() function configures the timeout value used in the driver. + [..] + HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI Peripheral. + [..] + HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold *** IO manager configuration functions *** ========================================== [..] - (#) HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance. + HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance. *** Callback registration *** ============================================= [..] - The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. + The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_OSPI_RegisterCallback() to register a user callback, - it allows to register following callbacks: - (+) ErrorCallback : callback when error occurs. - (+) AbortCpltCallback : callback when abort is completed. - (+) FifoThresholdCallback : callback when the fifo threshold is reached. - (+) CmdCpltCallback : callback when a command without data is completed. - (+) RxCpltCallback : callback when a reception transfer is completed. - (+) TxCpltCallback : callback when a transmission transfer is completed. - (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. - (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. - (+) StatusMatchCallback : callback when a status match occurs. - (+) TimeOutCallback : callback when the timeout perioed expires. - (+) MspInitCallback : OSPI MspInit. - (+) MspDeInitCallback : OSPI MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. + [..] + Use function HAL_OSPI_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : OSPI MspInit. + (+) MspDeInitCallback : OSPI MspDeInit. + [..] + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. - Use function @ref HAL_OSPI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: - (+) ErrorCallback : callback when error occurs. - (+) AbortCpltCallback : callback when abort is completed. - (+) FifoThresholdCallback : callback when the fifo threshold is reached. - (+) CmdCpltCallback : callback when a command without data is completed. - (+) RxCpltCallback : callback when a reception transfer is completed. - (+) TxCpltCallback : callback when a transmission transfer is completed. - (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. - (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. - (+) StatusMatchCallback : callback when a status match occurs. - (+) TimeOutCallback : callback when the timeout perioed expires. - (+) MspInitCallback : OSPI MspInit. - (+) MspDeInitCallback : OSPI MspDeInit. - This function) takes as parameters the HAL peripheral handle and the Callback ID. + [..] + Use function HAL_OSPI_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) FifoThresholdCallback : callback when the fifo threshold is reached. + (+) CmdCpltCallback : callback when a command without data is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. + (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. + (+) StatusMatchCallback : callback when a status match occurs. + (+) TimeOutCallback : callback when the timeout perioed expires. + (+) MspInitCallback : OSPI MspInit. + (+) MspDeInitCallback : OSPI MspDeInit. + [..] + This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_OSPI_Init and if the state is HAL_OSPI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_OSPI_Init - and @ref HAL_OSPI_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_OSPI_Init and @ref HAL_OSPI_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + [..] + By default, after the HAL_OSPI_Init() and if the state is HAL_OSPI_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the HAL_OSPI_Init() + and HAL_OSPI_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_OSPI_Init() and HAL_OSPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_OSPI_RegisterCallback before calling @ref HAL_OSPI_DeInit - or @ref HAL_OSPI_Init function. + [..] + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_OSPI_RegisterCallback() before calling HAL_OSPI_DeInit() + or HAL_OSPI_Init() function. - When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + [..] + When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. @endverbatim ****************************************************************************** @@ -280,7 +303,8 @@ static void OSPI_DMACplt (MDMA_HandleTypeDef *hmdma); static void OSPI_DMAError (MDMA_HandleTypeDef *hmdma); static void OSPI_DMAAbortCplt (MDMA_HandleTypeDef *hmdma); -static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, + uint32_t Tickstart, uint32_t Timeout); static HAL_StatusTypeDef OSPI_ConfigCmd (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); static HAL_StatusTypeDef OSPIM_GetConfig (uint8_t instance_nb, OSPIM_CfgTypeDef *cfg); /** @@ -374,7 +398,7 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) #else /* Initialization of the low level hardware */ HAL_OSPI_MspInit(hospi); -#endif +#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ /* Configure the default timeout for the OSPI memory access */ (void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); @@ -391,8 +415,9 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) /* Configure wrap size */ MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize); - /* Configure chip select boundary and maximun transfer */ - hospi->Instance->DCR3 = ((hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos) | (hospi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos)); + /* Configure chip select boundary and maximum transfer */ + hospi->Instance->DCR3 = ((hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos) | + (hospi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos)); /* Configure refresh */ hospi->Instance->DCR4 = hospi->Init.Refresh; @@ -406,13 +431,15 @@ HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi) if (status == HAL_OK) { /* Configure clock prescaler */ - MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos)); + MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, + ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos)); /* Configure Dual Quad mode */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DQM, hospi->Init.DualQuad); /* Configure sample shifting and delay hold quarter cycle */ - MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle)); + MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), + (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle)); /* Enable OctoSPI */ __HAL_OSPI_ENABLE(hospi); @@ -489,7 +516,7 @@ HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi) #else /* De-initialize the low-level hardware */ HAL_OSPI_MspDeInit(hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ /* Reset the driver state */ hospi->State = HAL_OSPI_STATE_RESET; @@ -584,7 +611,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->FifoThresholdCallback(hospi); #else HAL_OSPI_FifoThresholdCallback(hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ } /* OctoSPI transfer complete interrupt occurred ----------------------------*/ else if (((flag & HAL_OSPI_FLAG_TC) != 0U) && ((itsource & HAL_OSPI_IT_TC) != 0U)) @@ -614,7 +641,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->RxCpltCallback(hospi); #else HAL_OSPI_RxCpltCallback(hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ } else { @@ -639,7 +666,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->TxCpltCallback(hospi); #else HAL_OSPI_TxCpltCallback(hospi); -#endif +#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ } else if (currentstate == HAL_OSPI_STATE_BUSY_CMD) { @@ -648,7 +675,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->CmdCpltCallback(hospi); #else HAL_OSPI_CmdCpltCallback(hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ } else if (currentstate == HAL_OSPI_STATE_ABORT) { @@ -660,7 +687,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->AbortCpltCallback(hospi); #else HAL_OSPI_AbortCpltCallback(hospi); -#endif +#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ } else { @@ -670,7 +697,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->ErrorCallback(hospi); #else HAL_OSPI_ErrorCallback(hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ } } else @@ -700,7 +727,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->StatusMatchCallback(hospi); #else HAL_OSPI_StatusMatchCallback(hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ } /* OctoSPI transfer error interrupt occurred -------------------------------*/ else if (((flag & HAL_OSPI_FLAG_TE) != 0U) && ((itsource & HAL_OSPI_IT_TE) != 0U)) @@ -732,7 +759,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->ErrorCallback(hospi); #else HAL_OSPI_ErrorCallback(hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ } } else @@ -745,7 +772,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->ErrorCallback(hospi); #else HAL_OSPI_ErrorCallback(hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ } } /* OctoSPI timeout interrupt occurred --------------------------------------*/ @@ -759,7 +786,7 @@ void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) hospi->TimeOutCallback(hospi); #else HAL_OSPI_TimeOutCallback(hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ } else { @@ -826,8 +853,10 @@ HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTyp /* Check the state of the driver */ state = hospi->State; if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) || - ((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG) || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) || - ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG)))) + ((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG) + || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) || + ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) || + (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG)))) { /* Wait till busy flag is reset */ status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); @@ -1457,16 +1486,16 @@ HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pDat /* Enable the transmit MDMA Channel */ if (HAL_MDMA_Start_IT(hospi->hmdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize,1) == HAL_OK) - { - /* Enable the transfer error interrupt */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); - - /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/ - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_DMA; + { + /* Enable the transfer error interrupt */ + __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); + + /* Enable the MDMA transfer by setting the DMAEN bit not needed for MDMA*/ + } + else + { + status = HAL_ERROR; + hospi->ErrorCode = HAL_OSPI_ERROR_DMA; hospi->State = HAL_OSPI_STATE_READY; } } @@ -1618,7 +1647,7 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPolli uint32_t ir_reg = hospi->Instance->IR; #ifdef USE_FULL_ASSERT uint32_t dlr_reg = hospi->Instance->DLR; -#endif +#endif /* USE_FULL_ASSERT */ /* Check the parameters of the autopolling configuration structure */ assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode)); @@ -1696,7 +1725,7 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPo uint32_t ir_reg = hospi->Instance->IR; #ifdef USE_FULL_ASSERT uint32_t dlr_reg = hospi->Instance->DLR; -#endif +#endif /* USE_FULL_ASSERT */ /* Check the parameters of the autopolling configuration structure */ assert_param(IS_OSPI_MATCH_MODE (cfg->MatchMode)); @@ -1983,7 +2012,8 @@ __weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi) * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, + pOSPI_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -2171,7 +2201,7 @@ HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OS return status; } -#endif +#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ /** * @} @@ -2302,7 +2332,7 @@ HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi) hospi->AbortCpltCallback(hospi); #else HAL_OSPI_AbortCpltCallback(hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ } } else @@ -2328,7 +2358,7 @@ HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi) hospi->AbortCpltCallback(hospi); #else HAL_OSPI_AbortCpltCallback(hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ } } } @@ -2442,7 +2472,9 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * { HAL_StatusTypeDef status = HAL_OK; uint32_t instance; - uint8_t index, ospi_enabled = 0U, other_instance; + uint8_t index; + uint8_t ospi_enabled = 0U; + uint8_t other_instance; OSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE]; /* Prevent unused argument(s) compilation warning */ @@ -2450,7 +2482,7 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * /* Check the parameters of the OctoSPI IO Manager configuration structure */ assert_param(IS_OSPIM_PORT(cfg->ClkPort)); - assert_param(IS_OSPIM_PORT(cfg->DQSPort)); + assert_param(IS_OSPIM_DQS_PORT(cfg->DQSPort)); assert_param(IS_OSPIM_PORT(cfg->NCSPort)); assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort)); assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort)); @@ -2500,20 +2532,38 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * if (other_instance == 1U) { - SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKSRC); - SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSSRC); - SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLSRC_1); - SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHSRC_1); + SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKSRC); + if (IOM_cfg[other_instance].DQSPort != 0U) + { + SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSSRC); + } + if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE) + { + SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLSRC_1); + } + if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE) + { + SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHSRC_1); + } } } else { if (IOM_cfg[instance].ClkPort != 0U) { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); + if (IOM_cfg[instance].DQSPort != 0U) + { + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); + } + if (IOM_cfg[instance].IOLowPort != HAL_OSPIM_IOPORT_NONE) + { + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); + } + if (IOM_cfg[instance].IOHighPort != HAL_OSPIM_IOPORT_NONE) + { + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); + } } } @@ -2522,24 +2572,38 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { - if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && - (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) + if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && + (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && + (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && + (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) { /* Multiplexing should be performed */ SET_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN); } else { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort-1U)], OCTOSPIM_PCR_CLKEN); + if (IOM_cfg[other_instance].DQSPort != 0U) + { + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort-1U)], OCTOSPIM_PCR_DQSEN); + } + CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort-1U)], OCTOSPIM_PCR_NCSEN); + if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE) + { + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort-1U)& OSPI_IOM_PORT_MASK)], + OCTOSPIM_PCR_IOLEN); + } + if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE) + { + CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort-1U)& OSPI_IOM_PORT_MASK)], + OCTOSPIM_PCR_IOHEN); + } } } /******************** Activation of new configuration *********************/ - MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort-1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort - 1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), + (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos))); if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos)) { @@ -2549,51 +2613,83 @@ HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef * if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U) { MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN); - MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN); + if (cfg->DQSPort != 0U) + { + MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN); + } if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN); + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN); + } + else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE) + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN); } else { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN); + /* Nothing to do */ } if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0)); + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0)); + } + else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE) + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0)); } else { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0)); + /* Nothing to do */ } } else { - MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); - MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); + MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort-1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), + (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); + if (cfg->DQSPort != 0U) + { + MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort-1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), + (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); + } if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), - (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); + } + else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE) + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); } else { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), - (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); + /* Nothing to do */ } if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), - (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), + (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos+1U)))); + } + else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE) + { + MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), + (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); } else { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort-1U)& OSPI_IOM_PORT_MASK)], (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), - (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos+1U)))); + /* Nothing to do */ } } @@ -2667,7 +2763,7 @@ static void OSPI_DMAError(MDMA_HandleTypeDef *hmdma) hospi->ErrorCallback(hospi); #else HAL_OSPI_ErrorCallback(hospi); -#endif +#endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ } } @@ -2706,7 +2802,7 @@ static void OSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma) hospi->AbortCpltCallback(hospi); #else HAL_OSPI_AbortCpltCallback(hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ } } else @@ -2720,7 +2816,7 @@ static void OSPI_DMAAbortCplt(MDMA_HandleTypeDef *hmdma) hospi->ErrorCallback(hospi); #else HAL_OSPI_ErrorCallback(hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ } } @@ -2763,7 +2859,10 @@ static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hosp static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd) { HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t *ccr_reg, *tcr_reg, *ir_reg, *abr_reg; + __IO uint32_t *ccr_reg; + __IO uint32_t *tcr_reg; + __IO uint32_t *ir_reg; + __IO uint32_t *abr_reg; /* Re-initialize the value of the functional mode */ MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U); @@ -2941,7 +3040,8 @@ static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularC static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg) { HAL_StatusTypeDef status = HAL_OK; - uint32_t reg, value = 0U; + uint32_t reg; + uint32_t value = 0U; uint32_t index; if ((instance_nb == 0U) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL)) @@ -2962,7 +3062,8 @@ static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef * { if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U) { - value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1); + value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC + | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1); } else { diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.h index 35da48497e..6d7471ffc3 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ospi.h @@ -48,52 +48,52 @@ */ typedef struct { - uint32_t FifoThreshold; /* This is the threshold used by the Peripheral to generate the interrupt - indicating that data are available in reception or free place - is available in transmission. - This parameter can be a value between 1 and 32 */ - uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access up to - quad mode on two different devices to increase the throughput. - This parameter can be a value of @ref OSPI_DualQuad */ - uint32_t MemoryType; /* It indicates the external device type connected to the OSPI. - This parameter can be a value of @ref OSPI_MemoryType */ - uint32_t DeviceSize; /* It defines the size of the external device connected to the OSPI, - it corresponds to the number of address bits required to access - the external device. - This parameter can be a value between 1 and 32 */ - uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip select - must remain high between commands. - This parameter can be a value between 1 and 8 */ - uint32_t FreeRunningClock; /* It enables or not the free running clock. - This parameter can be a value of @ref OSPI_FreeRunningClock */ - uint32_t ClockMode; /* It indicates the level of clock when the chip select is released. - This parameter can be a value of @ref OSPI_ClockMode */ - uint32_t WrapSize; /* It indicates the wrap-size corresponding the external device configuration. - This parameter can be a value of @ref OSPI_WrapSize */ - uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating - the external clock based on the AHB clock. - This parameter can be a value between 1 and 256 */ - uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order - to take in account external signal delays. - This parameter can be a value of @ref OSPI_SampleShifting */ - uint32_t DelayHoldQuarterCycle; /* It allows to hold to 1/4 cycle the data. - This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ - uint32_t ChipSelectBoundary; /* It enables the transaction boundary feature and - defines the boundary of bytes to release the chip select. - This parameter can be a value between 0 and 31 */ - uint32_t ClkChipSelectHighTime; /* It defines the number of clocks provided on the CLK/nCLK pins when - the chip select is set to high at the end of a transaction. - This parameter can be a value between 0 and 7 */ - uint32_t DelayBlockBypass; /* It enables the delay block bypass, so the sampling is not affected - by the delay block. - This parameter can be a value of @ref OSPI_DelayBlockBypass */ - uint32_t MaxTran; /* It enables the communication regulation feature. The chip select is - released every MaxTran+1 bytes when the other OctoSPI request the access - to the bus. - This parameter can be a value between 0 and 255 */ - uint32_t Refresh; /* It enables the refresh rate feature. The chip select is released every - Refresh+1 clock cycles. - This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt + indicating that data are available in reception or free place + is available in transmission. + This parameter can be a value between 1 and 32 */ + uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to + quad mode on two different devices to increase the throughput. + This parameter can be a value of @ref OSPI_DualQuad */ + uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI. + This parameter can be a value of @ref OSPI_MemoryType */ + uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI, + it corresponds to the number of address bits required to access + the external device. + This parameter can be a value between 1 and 32 */ + uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select + must remain high between commands. + This parameter can be a value between 1 and 8 */ + uint32_t FreeRunningClock; /*!< It enables or not the free running clock. + This parameter can be a value of @ref OSPI_FreeRunningClock */ + uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. + This parameter can be a value of @ref OSPI_ClockMode */ + uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. + This parameter can be a value of @ref OSPI_WrapSize */ + uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating + the external clock based on the AHB clock. + This parameter can be a value between 1 and 256 */ + uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order + to take in account external signal delays. + This parameter can be a value of @ref OSPI_SampleShifting */ + uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. + This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ + uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and + defines the boundary of bytes to release the chip select. + This parameter can be a value between 0 and 31 */ + uint32_t ClkChipSelectHighTime; /*!< It defines the number of clocks provided on the CLK/nCLK pins when + the chip select is set to high at the end of a transaction. + This parameter can be a value between 0 and 7 */ + uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected + by the delay block. + This parameter can be a value of @ref OSPI_DelayBlockBypass */ + uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is + released every MaxTran+1 bytes when the other OctoSPI request the access + to the bus. + This parameter can be a value between 0 and 255 */ + uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every + Refresh+1 clock cycles. + This parameter can be a value between 0 and 0xFFFFFFFF */ }OSPI_InitTypeDef; /** @@ -103,17 +103,17 @@ typedef struct typedef struct __OSPI_HandleTypeDef #else typedef struct -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ { - OCTOSPI_TypeDef *Instance; /* OSPI registers base address */ - OSPI_InitTypeDef Init; /* OSPI initialization parameters */ - uint8_t *pBuffPtr; /* Address of the OSPI buffer for transfer */ - __IO uint32_t XferSize; /* Number of data to transfer */ - __IO uint32_t XferCount; /* Counter of data transferred */ - MDMA_HandleTypeDef *hmdma; /* Handle of the MDMA channel used for the transfer */ - __IO uint32_t State; /* Internal state of the OSPI HAL driver */ - __IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */ - uint32_t Timeout; /* Timeout used for the OSPI external device access */ + OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */ + OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */ + uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */ + __IO uint32_t XferSize; /*!< Number of data to transfer */ + __IO uint32_t XferCount; /*!< Counter of data transferred */ + MDMA_HandleTypeDef *hmdma; /*!< Handle of the MDMA channel used for the transfer */ + __IO uint32_t State; /*!< Internal state of the OSPI HAL driver */ + __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ + uint32_t Timeout; /*!< Timeout used for the OSPI external device access */ #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi); void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi); @@ -128,7 +128,7 @@ typedef struct void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi); void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ }OSPI_HandleTypeDef; /** @@ -136,50 +136,50 @@ typedef struct */ typedef struct { - uint32_t OperationType; /* It indicates if the configuration applies to the common regsiters or - to the registers for the write operation (these registers are only - used for memory-mapped mode). - This parameter can be a value of @ref OSPI_OperationType */ - uint32_t FlashId; /* It indicates which external device is selected for this command (it - applies only if Dualquad is disabled in the initialization structure). - This parameter can be a value of @ref OSPI_FlashId */ - uint32_t Instruction; /* It contains the instruction to be sent to the device. - This parameter can be a value between 0 and 0xFFFFFFFF */ - uint32_t InstructionMode; /* It indicates the mode of the instruction. - This parameter can be a value of @ref OSPI_InstructionMode */ - uint32_t InstructionSize; /* It indicates the size of the instruction. - This parameter can be a value of @ref OSPI_InstructionSize */ - uint32_t InstructionDtrMode; /* It enables or not the DTR mode for the instruction phase. - This parameter can be a value of @ref OSPI_InstructionDtrMode */ - uint32_t Address; /* It contains the address to be sent to the device. - This parameter can be a value between 0 and 0xFFFFFFFF */ - uint32_t AddressMode; /* It indicates the mode of the address. - This parameter can be a value of @ref OSPI_AddressMode */ - uint32_t AddressSize; /* It indicates the size of the address. - This parameter can be a value of @ref OSPI_AddressSize */ - uint32_t AddressDtrMode; /* It enables or not the DTR mode for the address phase. - This parameter can be a value of @ref OSPI_AddressDtrMode */ - uint32_t AlternateBytes; /* It contains the alternate bytes to be sent to the device. - This parameter can be a value between 0 and 0xFFFFFFFF */ - uint32_t AlternateBytesMode; /* It indicates the mode of the alternate bytes. - This parameter can be a value of @ref OSPI_AlternateBytesMode */ - uint32_t AlternateBytesSize; /* It indicates the size of the alternate bytes. - This parameter can be a value of @ref OSPI_AlternateBytesSize */ - uint32_t AlternateBytesDtrMode; /* It enables or not the DTR mode for the alternate bytes phase. - This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ - uint32_t DataMode; /* It indicates the mode of the data. - This parameter can be a value of @ref OSPI_DataMode */ - uint32_t NbData; /* It indicates the number of data transferred with this command. - This field is only used for indirect mode. - This parameter can be a value between 1 and 0xFFFFFFFF */ - uint32_t DataDtrMode; /* It enables or not the DTR mode for the data phase. - This parameter can be a value of @ref OSPI_DataDtrMode */ - uint32_t DummyCycles; /* It indicates the number of dummy cycles inserted before data phase. - This parameter can be a value between 0 and 31 */ - uint32_t DQSMode; /* It enables or not the data strobe management. - This parameter can be a value of @ref OSPI_DQSMode */ - uint32_t SIOOMode; /* It enables or not the SIOO mode. - This parameter can be a value of @ref OSPI_SIOOMode */ + uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or + to the registers for the write operation (these registers are only + used for memory-mapped mode). + This parameter can be a value of @ref OSPI_OperationType */ + uint32_t FlashId; /*!< It indicates which external device is selected for this command (it + applies only if Dualquad is disabled in the initialization structure). + This parameter can be a value of @ref OSPI_FlashID */ + uint32_t Instruction; /*!< It contains the instruction to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t InstructionMode; /*!< It indicates the mode of the instruction. + This parameter can be a value of @ref OSPI_InstructionMode */ + uint32_t InstructionSize; /*!< It indicates the size of the instruction. + This parameter can be a value of @ref OSPI_InstructionSize */ + uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase. + This parameter can be a value of @ref OSPI_InstructionDtrMode */ + uint32_t Address; /*!< It contains the address to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AddressMode; /*!< It indicates the mode of the address. + This parameter can be a value of @ref OSPI_AddressMode */ + uint32_t AddressSize; /*!< It indicates the size of the address. + This parameter can be a value of @ref OSPI_AddressSize */ + uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase. + This parameter can be a value of @ref OSPI_AddressDtrMode */ + uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. + This parameter can be a value of @ref OSPI_AlternateBytesMode */ + uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes. + This parameter can be a value of @ref OSPI_AlternateBytesSize */ + uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase. + This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ + uint32_t DataMode; /*!< It indicates the mode of the data. + This parameter can be a value of @ref OSPI_DataMode */ + uint32_t NbData; /*!< It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFF */ + uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase. + This parameter can be a value of @ref OSPI_DataDtrMode */ + uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. + This parameter can be a value between 0 and 31 */ + uint32_t DQSMode; /*!< It enables or not the data strobe management. + This parameter can be a value of @ref OSPI_DQSMode */ + uint32_t SIOOMode; /*!< It enables or not the SIOO mode. + This parameter can be a value of @ref OSPI_SIOOMode */ }OSPI_RegularCmdTypeDef; /** @@ -187,14 +187,14 @@ typedef struct */ typedef struct { - uint32_t RWRecoveryTime; /* It indicates the number of cycles for the device read write recovery time. - This parameter can be a value between 0 and 255 */ - uint32_t AccessTime; /* It indicates the number of cycles for the device acces time. - This parameter can be a value between 0 and 255 */ - uint32_t WriteZeroLatency; /* It enables or not the latency for the write access. - This parameter can be a value of @ref OSPI_WriteZeroLatency */ - uint32_t LatencyMode; /* It configures the latency mode. - This parameter can be a value of @ref OSPI_LatencyMode */ + uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time. + This parameter can be a value between 0 and 255 */ + uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time. + This parameter can be a value between 0 and 255 */ + uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. + This parameter can be a value of @ref OSPI_WriteZeroLatency */ + uint32_t LatencyMode; /*!< It configures the latency mode. + This parameter can be a value of @ref OSPI_LatencyMode */ }OSPI_HyperbusCfgTypeDef; /** @@ -202,18 +202,18 @@ typedef struct */ typedef struct { - uint32_t AddressSpace; /* It indicates the address space accessed by the command. - This parameter can be a value of @ref OSPI_AddressSpace */ - uint32_t Address; /* It contains the address to be sent tot he device. - This parameter can be a value between 0 and 0xFFFFFFFF */ - uint32_t AddressSize; /* It indicates the size of the address. - This parameter can be a value of @ref OSPI_AddressSize */ - uint32_t NbData; /* It indicates the number of data transferred with this command. - This field is only used for indirect mode. - This parameter can be a value between 1 and 0xFFFFFFFF - In case of autopolling mode, this parameter can be any value between 1 and 4 */ - uint32_t DQSMode; /* It enables or not the data strobe management. - This parameter can be a value of @ref OSPI_DQSMode */ + uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. + This parameter can be a value of @ref OSPI_AddressSpace */ + uint32_t Address; /*!< It contains the address to be sent tot he device. + This parameter can be a value between 0 and 0xFFFFFFFF */ + uint32_t AddressSize; /*!< It indicates the size of the address. + This parameter can be a value of @ref OSPI_AddressSize */ + uint32_t NbData; /*!< It indicates the number of data transferred with this command. + This field is only used for indirect mode. + This parameter can be a value between 1 and 0xFFFFFFFF + In case of autopolling mode, this parameter can be any value between 1 and 4 */ + uint32_t DQSMode; /*!< It enables or not the data strobe management. + This parameter can be a value of @ref OSPI_DQSMode */ }OSPI_HyperbusCmdTypeDef; /** @@ -221,16 +221,16 @@ typedef struct */ typedef struct { - uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. - This parameter can be any value between 0 and 0xFFFFFFFF */ - uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. - This parameter can be any value between 0 and 0xFFFFFFFF */ - uint32_t MatchMode; /* Specifies the method used for determining a match. - This parameter can be a value of @ref OSPI_MatchMode */ - uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. - This parameter can be a value of @ref OSPI_AutomaticStop */ - uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. - This parameter can be any value between 0 and 0xFFFF */ + uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match. + This parameter can be any value between 0 and 0xFFFFFFFF */ + uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received. + This parameter can be any value between 0 and 0xFFFFFFFF */ + uint32_t MatchMode; /*!< Specifies the method used for determining a match. + This parameter can be a value of @ref OSPI_MatchMode */ + uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. + This parameter can be a value of @ref OSPI_AutomaticStop */ + uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases. + This parameter can be any value between 0 and 0xFFFF */ }OSPI_AutoPollingTypeDef; /** @@ -238,10 +238,10 @@ typedef struct */ typedef struct { - uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. - This parameter can be a value of @ref OSPI_TimeOutActivation */ - uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. - This parameter can be any value between 0 and 0xFFFF */ + uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. + This parameter can be a value of @ref OSPI_TimeOutActivation */ + uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select. + This parameter can be any value between 0 and 0xFFFF */ }OSPI_MemoryMappedTypeDef; /** @@ -249,19 +249,19 @@ typedef struct */ typedef struct { - uint32_t ClkPort; /* It indicates which port of the OSPI IO Manager is used for the CLK pins. - This parameter can be a value between 1 and 8 */ - uint32_t DQSPort; /* It indicates which port of the OSPI IO Manager is used for the DQS pin. - This parameter can be a value between 1 and 8 */ - uint32_t NCSPort; /* It indicates which port of the OSPI IO Manager is used for the NCS pin. - This parameter can be a value between 1 and 8 */ - uint32_t IOLowPort; /* It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. - This parameter can be a value of @ref OSPIM_IOPort */ - uint32_t IOHighPort; /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. - This parameter can be a value of @ref OSPIM_IOPort */ - uint32_t Req2AckTime; /* It indicates the minimum switching duration (in number of clock cycles) expected - if some signals are multiplexed in the OSPI IO Manager with the other OSPI. - This parameter can be a value between 1 and 256 */ + uint32_t ClkPort; /*!< It indicates which port of the OSPI IO Manager is used for the CLK pins. + This parameter can be a value between 1 and 8 */ + uint32_t DQSPort; /*!< It indicates which port of the OSPI IO Manager is used for the DQS pin. + This parameter can be a value between 0 and 8, 0 means that signal not used */ + uint32_t NCSPort; /*!< It indicates which port of the OSPI IO Manager is used for the NCS pin. + This parameter can be a value between 1 and 8 */ + uint32_t IOLowPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. + This parameter can be a value of @ref OSPIM_IOPort */ + uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. + This parameter can be a value of @ref OSPIM_IOPort */ + uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected + if some signals are multiplexed in the OSPI IO Manager with the other OSPI. + This parameter can be a value between 1 and 256 */ }OSPIM_CfgTypeDef; #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) @@ -289,7 +289,7 @@ typedef enum * @brief HAL OSPI Callback pointer definition */ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ /** * @} */ @@ -330,7 +330,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) #define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ /** * @} */ @@ -658,6 +658,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port * @{ */ +#define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U) /*!< IOs not used */ #define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */ #define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */ #define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */ @@ -697,7 +698,7 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); } while(0) #else #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) -#endif +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ /** @brief Enable the OSPI peripheral. * @param __HANDLE__ specifies the OSPI Handle. @@ -749,7 +750,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ + == (__INTERRUPT__)) /** * @brief Check whether the selected OSPI flag is set or not. @@ -764,7 +766,8 @@ typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag * @retval None */ -#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) +#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ + != 0U) ? SET : RESET) /** @brief Clears the specified OSPI's flag status. * @param __HANDLE__ specifies the OSPI Handle. @@ -808,22 +811,22 @@ void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi); void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi); /* OSPI command configuration functions */ -HAL_StatusTypeDef HAL_OSPI_Command (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_Command_IT (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); -HAL_StatusTypeDef HAL_OSPI_HyperbusCfg (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_HyperbusCmd (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); +HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); /* OSPI indirect mode functions */ -HAL_StatusTypeDef HAL_OSPI_Transmit (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_Receive (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_Transmit_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); -HAL_StatusTypeDef HAL_OSPI_Receive_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); -HAL_StatusTypeDef HAL_OSPI_Transmit_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); -HAL_StatusTypeDef HAL_OSPI_Receive_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); +HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); /* OSPI status flag polling mode functions */ -HAL_StatusTypeDef HAL_OSPI_AutoPolling (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); +HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); /* OSPI memory-mapped mode functions */ HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); @@ -848,9 +851,10 @@ void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) /* OSPI callback registering/unregistering */ -HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); -#endif +HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, + pOSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); +#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ /** * @} */ @@ -875,7 +879,7 @@ uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi); /** @addtogroup OSPI_Exported_Functions_Group4 * @{ */ -HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); +HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); /** * @} @@ -1033,7 +1037,10 @@ HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) -#define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ +#define IS_OSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 8U) + +#define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_NONE) || \ + ((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ ((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.c index a54882ece4..2b3fd1bd5b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.c @@ -305,7 +305,8 @@ __weak void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID, pOTFDEC_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID, + pOTFDEC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -644,10 +645,14 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_ * the configuration information for OTFDEC module * @param RegionIndex index of region the mode of which is set * @param mode This parameter can be only: - * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY Only instruction accesses are decrypted - * @arg @ref OTFDEC_REG_MODE_DATA_ACCESSES_ONLY Only data accesses are decrypted - * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES All read accesses are decrypted (instruction or data) - * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER Only instruction accesses are decrypted with proprietary cipher activated + * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY + Only instruction accesses are decrypted + * @arg @ref OTFDEC_REG_MODE_DATA_ACCESSES_ONLY + Only data accesses are decrypted + * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES + All read accesses are decrypted (instruction or data) + * @arg @ref OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER + Only instruction accesses are decrypted with proprietary cipher activated * @retval HAL state */ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode) @@ -689,7 +694,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32 * @arg @ref OTFDEC_REG_CONFIGR_LOCK_ENABLE OTFDEC region configuration is locked * @retval HAL state */ -HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config, uint32_t lock) +HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, + OTFDEC_RegionConfigTypeDef *Config, uint32_t lock) { OTFDEC_Region_TypeDef * region; uint32_t address; @@ -723,7 +729,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_ WRITE_REG( region->REG_END_ADDR, Config->EndAddress); /* Write Version */ - MODIFY_REG( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION, (uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos ); + MODIFY_REG( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_VERSION, + (uint32_t)(Config->Version) << OTFDEC_REG_CONFIGR_VERSION_Pos ); /* Enable region deciphering or enciphering (depending of OTFDEC_CR ENC bit setting) */ SET_BIT( region->REG_CONFIGR, OTFDEC_REG_CONFIGR_REG_ENABLE); @@ -754,7 +761,9 @@ uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey) uint32_t key_strobe[4] = {0xAA55AA55U, 0x3U, 0x18U, 0xC0U}; uint8_t i; uint8_t crc = 0; - uint32_t j, keyval, k; + uint32_t j; + uint32_t keyval; + uint32_t k; uint32_t * temp = pKey; for (j = 0U; j < 4U; j++) @@ -935,7 +944,8 @@ uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t Regi * @param Config pointer on structure that will be filled up with the region configuration parameters * @retval HAL state */ -HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config) +HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, + OTFDEC_RegionConfigTypeDef *Config) { OTFDEC_Region_TypeDef * region; uint32_t address; @@ -965,7 +975,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint Config->EndAddress = READ_REG(region->REG_END_ADDR); /* Read Version */ - Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) & OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos; + Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) & + OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos; /* Release Lock */ __HAL_UNLOCK(hotfdec); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.h index ebd4ea744f..3a49ef2ac0 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_otfdec.h @@ -281,7 +281,7 @@ typedef void (*pOTFDEC_CallbackTypeDef)(OTFDEC_HandleTypeDef *hotfdec); /*!< po * @arg @ref OTFDEC_ALL_INT OTFDEC all interrupts flags * @retval The state of __FLAG__ (TRUE or FALSE). */ - #define __HAL_OTFDEC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) +#define __HAL_OTFDEC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified combination of OTFDEC interrupt flags. * @param __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains @@ -342,7 +342,8 @@ void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec); HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode); -HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); +HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, + OTFDEC_RegionConfigTypeDef *Config, uint32_t lock); uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey); HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); @@ -355,7 +356,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32 */ HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec); uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex); -HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config); +HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, + OTFDEC_RegionConfigTypeDef *Config); /** * @} */ @@ -422,9 +424,9 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) */ #define IS_OTFDEC_REGION_OPERATING_MODE(__MODE__) (((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY) || \ - ((__MODE__) == OTFDEC_REG_MODE_DATA_ACCESSES_ONLY) || \ - ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \ - ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER)) + ((__MODE__) == OTFDEC_REG_MODE_DATA_ACCESSES_ONLY) || \ + ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \ + ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER)) /** * @brief Verify the OTFDEC region index. diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.c index 031f01fd60..e577f400c0 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.c @@ -102,8 +102,8 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint */ /** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -230,7 +230,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { (void)HAL_PCDEx_ActivateLPM(hpcd); } - + (void)USB_DevDisconnect(hpcd->Instance); return HAL_OK; @@ -252,7 +252,10 @@ HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) hpcd->State = HAL_PCD_STATE_BUSY; /* Stop Device */ - (void)HAL_PCD_Stop(hpcd); + if (USB_StopDevice(hpcd->Instance) != HAL_OK) + { + return HAL_ERROR; + } #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) if (hpcd->MspDeInitCallback == NULL) @@ -321,7 +324,9 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -531,7 +536,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca * @param pCallback pointer to the USB PCD Data OUT Stage Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -566,7 +572,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, } /** - * @brief UnRegister the USB PCD Data OUT Stage Callback + * @brief Unregister the USB PCD Data OUT Stage Callback * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -604,7 +610,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd * @param pCallback pointer to the USB PCD Data IN Stage Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -639,7 +646,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, p } /** - * @brief UnRegister the USB PCD Data IN Stage Callback + * @brief Unregister the USB PCD Data IN Stage Callback * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -677,7 +684,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -712,7 +720,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, } /** - * @brief UnRegister the USB PCD Iso OUT incomplete Callback + * @brief Unregister the USB PCD Iso OUT incomplete Callback * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -750,7 +758,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -785,7 +794,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, p } /** - * @brief UnRegister the USB PCD Iso IN incomplete Callback + * @brief Unregister the USB PCD Iso IN incomplete Callback * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -858,7 +867,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdC } /** - * @brief UnRegister the USB PCD BCD Callback + * @brief Unregister the USB PCD BCD Callback * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -931,7 +940,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmC } /** - * @brief UnRegister the USB PCD LPM Callback + * @brief Unregister the USB PCD LPM Callback * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback * @param hpcd PCD handle * @retval HAL status @@ -968,8 +977,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -989,22 +998,21 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) { -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ __HAL_LOCK(hpcd); -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if ((hpcd->Init.battery_charging_enable == 1U) && (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; } -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - (void)USB_DevConnect(hpcd->Instance); + __HAL_PCD_ENABLE(hpcd); + (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1015,20 +1023,26 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) { + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + __HAL_LOCK(hpcd); __HAL_PCD_DISABLE(hpcd); + (void)USB_DevDisconnect(hpcd->Instance); - if (USB_StopDevice(hpcd->Instance) != HAL_OK) + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + if ((hpcd->Init.battery_charging_enable == 1U) && + (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) { - __HAL_UNLOCK(hpcd); - return HAL_ERROR; + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); } - (void)USB_DevDisconnect(hpcd->Instance); __HAL_UNLOCK(hpcd); return HAL_OK; } + #if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** * @brief Handles PCD interrupt request. @@ -1058,7 +1072,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); } - /* Handle RxQLevel Interrupt */ + /* Handle RxQLevel Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); @@ -1243,7 +1257,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); } - + /* Handle LPM Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) { @@ -1269,7 +1283,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } } - + /* Handle Reset Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) { @@ -1593,8 +1607,8 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * + * @brief management functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -1614,21 +1628,19 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) { -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ __HAL_LOCK(hpcd); -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if ((hpcd->Init.battery_charging_enable == 1U) && (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; } -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1639,9 +1651,20 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) { + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + __HAL_LOCK(hpcd); (void)USB_DevDisconnect(hpcd->Instance); + + if ((hpcd->Init.battery_charging_enable == 1U) && + (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) + { + /* Disable USB Transceiver */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + } + __HAL_UNLOCK(hpcd); + return HAL_OK; } @@ -1657,6 +1680,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) hpcd->USB_Address = address; (void)USB_SetDevAddress(hpcd->Instance, address); __HAL_UNLOCK(hpcd); + return HAL_OK; } /** @@ -1667,7 +1691,8 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) * @param ep_type endpoint type * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type) { HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; @@ -1852,10 +1877,12 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) __HAL_LOCK(hpcd); (void)USB_EPSetStall(hpcd->Instance, ep); + if ((ep_addr & EP_ADDR_MSK) == 0U) { (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); } + __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1946,8 +1973,8 @@ HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) */ /** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State functions ##### diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.h index 821f8d96a3..7236566114 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd.h @@ -187,9 +187,9 @@ typedef struct /* Exported macros -----------------------------------------------------------*/ /** @defgroup PCD_Exported_Macros PCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ #if defined (USB_OTG_FS) || defined (USB_OTG_HS) #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) @@ -199,12 +199,11 @@ typedef struct #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) -#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \ - ~(USB_OTG_PCGCCTL_STOPCLK) +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) -#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) @@ -271,25 +270,41 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType * @} */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, + pPCD_BcdCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, + pPCD_LpmCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /** @@ -328,16 +343,24 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type); + HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint8_t *pBuf, uint32_t len); + +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint8_t *pBuf, uint32_t len); + + HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); + +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); /** * @} */ @@ -403,8 +426,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); /* Private macros ------------------------------------------------------------*/ /** @defgroup PCD_Private_Macros PCD Private Macros - * @{ - */ + * @{ + */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd_ex.c index a2a30eb741..5debbe016d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pcd_ex.c @@ -49,7 +49,7 @@ /** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions * @brief PCDEx control functions - * + * @verbatim =============================================================================== ##### Extended features functions ##### @@ -260,7 +260,7 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); - /* Power Down USB tranceiver */ + /* Power Down USB transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); /* Enable Battery charging */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.h index 922fafa95c..cd5023447f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pssi.h @@ -232,7 +232,7 @@ typedef enum #define PSSI_CR_OUTEN_OUTPUT PSSI_CR_OUTEN /*!< Output Mode */ #define PSSI_CR_DMA_ENABLE PSSI_CR_DMAEN /*!< DMA Mode Enable */ -#define PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN) /*!< DMA Mode Disble */ +#define PSSI_CR_DMA_DISABLE (~PSSI_CR_DMAEN) /*!< DMA Mode Disable */ #define PSSI_CR_16BITS PSSI_CR_EDM /*!< 16 Lines Mode */ #define PSSI_CR_8BITS (~PSSI_CR_EDM) /*!< 8 Lines Mode */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.c index 88c8d1aa52..0de6bb2a19 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr.c @@ -36,7 +36,7 @@ memory and peripherals. The SmartRun domain contains the system control, I/O logic and low-power peripherals. - (#) Every entity have low power mode as decribed below : + (#) Every entity have low power mode as described below : (#) The CPU low power modes are : (+) CPU CRUN. (+) CPU CSLEEP. @@ -587,7 +587,7 @@ void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry) /** * @brief Enter STOP mode. * @note For single core devices, this API will enter the system in STOP mode - * with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR regiter is + * with all domains in DSTOP, if RUN_D3/RUN_SRD bit in CPUCR register is * cleared. * For dual core devices, this API will enter the domain (containing * Cortex-Mx that executing this function) in DSTOP mode. If all @@ -672,7 +672,7 @@ void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry) * @brief Enter STANDBY mode. * @note For single core devices, this API will enter the system in STANDBY * mode with all domains in DSTANDBY, if RUN_D3/RUN_SRD bit in CPUCR - * regiter is cleared. + * register is cleared. * For dual core devices, this API will enter the domain (containing * Cortex-Mx that executing this function) in DSTANDBY mode. If all * Cortex-Mx domains are in DSTANDBY and RUN_D3 bit in CPUCR register diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.c index 77cd3374f4..aaa58099c7 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.c @@ -102,7 +102,7 @@ (#) Call HAL_PWREx_EnableUSBReg(), HAL_PWREx_DisableUSBReg(), HAL_PWREx_EnableUSBVoltageDetector() and HAL_PWREx_DisableUSBVoltageDetector() functions to manage USB power - regulation functionnalities. + regulation functionalities. (#) Call HAL_PWREx_EnableBatteryCharging() and HAL_PWREx_DisableBatteryCharging() functions to enable and disable the diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.h index 563a8750d8..12f557a170 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_pwr_ex.h @@ -233,13 +233,13 @@ typedef enum /** @defgroup PWREx_Supply_configuration PWREx Supply configuration * @{ */ -#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are suppplied from the LDO */ +#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */ #if defined (SMPS) -#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are suppplied from the SMPS only */ +#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS only */ #define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ #define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ -#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */ -#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */ +#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ #define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ #define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ #endif /* defined (SMPS) */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.c index 0587b0b57c..12214968cb 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_qspi.c @@ -90,7 +90,7 @@ *** MDMA functional mode *** ==================================== [..] - (#) Configure the SourceInc and DestinationInc of MDMA paramters in the HAL_QSPI_MspInit() function : + (#) Configure the SourceInc and DestinationInc of MDMA parameters in the HAL_QSPI_MspInit() function : (++) MDMA settings for write operation : (+) The DestinationInc should be MDMA_DEST_INC_DISABLE (+) The SourceInc must be a value of @ref MDMA_Source_increment_mode (Except the MDMA_SRC_INC_DOUBLEWORD). @@ -569,7 +569,8 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) { if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); /* Disable the MDMA channel */ @@ -591,7 +592,8 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) { if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); /* Disable the MDMA channel */ @@ -715,7 +717,8 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); /* Disable the MDMA channel */ @@ -1332,7 +1335,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /* Enable the QSPI transfer error Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */ + /* Enable using MDMA by setting DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); } else @@ -1446,7 +1450,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* Enable the QSPI transfer error Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - /* Enable the MDMA transfer by setting the DMAEN bit in the QSPI CR register */ + /* Enable using MDMA by setting DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); } else @@ -2160,7 +2165,8 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); /* Abort MDMA */ @@ -2221,7 +2227,8 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ + /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); /* Abort MDMA channel */ @@ -2396,7 +2403,8 @@ static void QSPI_DMAError(MDMA_HandleTypeDef *hmdma) hqspi->TxXferCount = 0U; hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - /* Disable the MDMA transfer by clearing the DMAEN bit in the QSPI CR register */ + /* Disable using MDMA by clearing DMAEN, note that DMAEN bit is "reserved" + but no impact on H7 HW and it minimize the cost in the footprint */ CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); /* Abort the QSPI */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.c index 0ee2e2a660..54491f939c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.c @@ -7,14 +7,14 @@ * functionalities of the RAM ECC monitoring (RAMECC) peripheral: * + Initialization and de-initialization functions * + Monitoring operation functions - * + Error informations functions + * + Error information functions * + State and error functions @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== [..] - (#) Enable and latch error informations through HAL_RAMECC_Init(). + (#) Enable and latch error information through HAL_RAMECC_Init(). (#) For a given Monitor, enable and disable interrupt through HAL_RAMECC_EnableNotifiaction(). @@ -39,7 +39,7 @@ HAL_NVIC_SetPriority(). (+) Enable the RAMECC IRQ handler using HAL_NVIC_EnableIRQ(). - *** Failing informations *** + *** Failing information *** ====================== [..] (#) Use HAL_RAMECC_GetFailingAddress() function to return the RAMECC @@ -230,7 +230,7 @@ HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc) ##### Monitoring operation functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Configure latching error informations. + (+) Configure latching error information. (+) Configure RAMECC Global/Monitor interrupts. (+) Register and Unregister RAMECC callbacks (+) Handle RAMECC interrupt request @@ -278,7 +278,7 @@ HAL_StatusTypeDef HAL_RAMECC_StartMonitor (RAMECC_HandleTypeDef *hramecc) /** - * @brief Stop the RAMECC latching error informations. + * @brief Stop the RAMECC latching error information. * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains * the configuration information for the specified RAMECC * Monitor. @@ -494,7 +494,7 @@ void HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc) /* Clear active flags */ __HAL_RAMECC_CLEAR_FLAG (hramecc, (((ier_reg | cr_reg) & sr_reg) >> 1U)); - /* Check if a valid double error callback is registred */ + /* Check if a valid double error callback is registered */ if (hramecc->DetectErrorCallback != NULL) { /* Error detection callback */ @@ -507,7 +507,7 @@ void HAL_RAMECC_IRQHandler (RAMECC_HandleTypeDef *hramecc) * @verbatim =============================================================================== - ##### Error informations functions ##### + ##### Error information functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Get failing address. @@ -589,7 +589,7 @@ uint32_t HAL_RAMECC_GetHammingErrorCode (RAMECC_HandleTypeDef *hramecc) } /** - * @brief Check if an ECC single error was occured. + * @brief Check if an ECC single error was occurred. * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains * the configuration information for the specified RAMECC * Monitor. @@ -605,7 +605,7 @@ uint32_t HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc) } /** - * @brief Check if an ECC double error was occured. + * @brief Check if an ECC double error was occurred. * @param hramecc Pointer to a RAMECC_HandleTypeDef structure that contains * the configuration information for the specified RAMECC * Monitor. diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.h index 56250f8103..1046ca85ee 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_ramecc.h @@ -264,8 +264,8 @@ HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback (RAMECC_HandleTypeDef *hramecc) * @} */ -/** @defgroup RAMECC_Exported_Functions_Group3 Error informations functions - * @brief Error informations functions +/** @defgroup RAMECC_Exported_Functions_Group3 Error information functions + * @brief Error information functions * @{ */ uint32_t HAL_RAMECC_GetFailingAddress (RAMECC_HandleTypeDef *hramecc); @@ -278,8 +278,8 @@ uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc); * @} */ -/** @defgroup RAMECC_Exported_Functions_Group3 Error informations functions - * @brief Error informations functions +/** @defgroup RAMECC_Exported_Functions_Group3 Error information functions + * @brief Error information functions * @{ */ HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c index 17c241b8d6..b5e93c78b9 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.c @@ -355,6 +355,11 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) /* Reset PLL3FRACR register */ CLEAR_REG(RCC->PLL3FRACR); +#if defined(RCC_CR_HSEEXT) + /* Reset HSEEXT */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); +#endif /* RCC_CR_HSEEXT */ + /* Reset HSEBYP bit */ CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); @@ -746,6 +751,8 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc { /* Check the parameters */ assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLRGE_VALUE(RCC_OscInitStruct->PLL.PLLRGE)); + assert_param(IS_RCC_PLLVCO_VALUE(RCC_OscInitStruct->PLL.PLLVCOSEL)); assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.h index f4d896dc85..6a589ee132 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.h @@ -7295,9 +7295,9 @@ typedef struct /** * @brief Macro to configure the External High Speed oscillator (__HSE__). - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. + * @note After enabling the HSE (RCC_HSE_ON, RCC_HSE_BYPASS or RCC_HSE_BYPASS_DIGITAL), + * the application software should wait on HSERDY flag to be set indicating + * that HSE clock is stable and can be used to clock the PLL and/or system clock. * @note HSE state can not be changed if it is used directly or through the * PLL as system clock. In this case, you have to select another source * of the system clock then change the HSE state (ex. disable it). @@ -7311,6 +7311,9 @@ typedef struct * 6 HSE oscillator clock cycles. * @arg RCC_HSE_ON: turn ON the HSE oscillator. * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. + * @arg RCC_HSE_BYPASS_DIGITAL: HSE oscillator bypassed with digital external clock. (*) + * + * (*): Only available on stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines. */ #if defined(RCC_CR_HSEEXT) #define __HAL_RCC_HSE_CONFIG(__STATE__) \ @@ -8070,6 +8073,16 @@ void HAL_RCC_CCSCallback(void); ((SOURCE) == RCC_PLLSOURCE_HSI) || \ ((SOURCE) == RCC_PLLSOURCE_NONE) || \ ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLL1VCIRANGE_0) || \ + ((VALUE) == RCC_PLL1VCIRANGE_1) || \ + ((VALUE) == RCC_PLL1VCIRANGE_2) || \ + ((VALUE) == RCC_PLL1VCIRANGE_3)) + +#define IS_RCC_PLLVCO_VALUE(VALUE) (((VALUE) == RCC_PLL1VCOWIDE) || ((VALUE) == RCC_PLL1VCOMEDIUM)) + +#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U) + #define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U)) #if !defined(RCC_VER_2_0) #define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.c index 508dd9d75f..afde46b3b8 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.c @@ -1566,6 +1566,16 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_CLKP_CONFIG(PeriphClkInit->CkperClockSelection); } + /*------------------------------ CEC Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC interface clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } + if (status == HAL_OK) { return HAL_OK; @@ -1779,7 +1789,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) PLL2_ClocksTypeDef pll2_clocks; PLL3_ClocksTypeDef pll3_clocks; - /* This variable is used to store the SAI clock frequency (value in Hz) */ + /* This variable is used to store the clock frequency (value in Hz) */ uint32_t frequency; /* This variable is used to store the SAI and CKP clock source */ uint32_t saiclocksource; @@ -1795,21 +1805,42 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { case RCC_SAI1CLKSOURCE_PLL: /* PLL1 is the clock source for SAI1 */ { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } break; } case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI1 */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } break; } case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI1 */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } break; } @@ -1818,19 +1849,19 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - if(ckpclocksource== RCC_CLKPSOURCE_HSI) + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) { /* In Case the CKPER Source is HSI */ - frequency = HSI_VALUE; + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); } - else if(ckpclocksource== RCC_CLKPSOURCE_CSI) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; } - else if (ckpclocksource== RCC_CLKPSOURCE_HSE) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; @@ -1866,23 +1897,44 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) switch (saiclocksource) { - case 0: /* PLL1 is the clock source for SAI2/3 */ + case RCC_SAI23CLKSOURCE_PLL: /* PLL1 is the clock source for SAI2/3 */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } break; } case RCC_SAI23CLKSOURCE_PLL2: /* PLL2 is the clock source for SAI2/3 */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } break; } case RCC_SAI23CLKSOURCE_PLL3: /* PLL3 is the clock source for SAI2/3 */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } break; } @@ -1891,19 +1943,19 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - if(ckpclocksource== RCC_CLKPSOURCE_HSI) + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) { /* In Case the CKPER Source is HSI */ - frequency = HSI_VALUE; + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); } - else if(ckpclocksource== RCC_CLKPSOURCE_CSI) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; } - else if (ckpclocksource== RCC_CLKPSOURCE_HSE) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; @@ -1940,23 +1992,44 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) switch (saiclocksource) { - case 0: /* PLL1 is the clock source for SAI2A */ + case RCC_SAI2ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI2A */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } break; } case RCC_SAI2ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2A */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } break; } case RCC_SAI2ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2A */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } break; } @@ -1965,19 +2038,19 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - if(ckpclocksource== RCC_CLKPSOURCE_HSI) + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) { /* In Case the CKPER Source is HSI */ - frequency = HSI_VALUE; + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); } - else if(ckpclocksource== RCC_CLKPSOURCE_CSI) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; } - else if (ckpclocksource== RCC_CLKPSOURCE_HSE) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; @@ -2016,23 +2089,44 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) switch (saiclocksource) { - case 0: /* PLL1 is the clock source for SAI2B */ + case RCC_SAI2BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI2B */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } break; } case RCC_SAI2BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI2B */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } break; } case RCC_SAI2BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI2B */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } break; } @@ -2041,19 +2135,19 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - if(ckpclocksource== RCC_CLKPSOURCE_HSI) + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) { /* In Case the CKPER Source is HSI */ - frequency = HSI_VALUE; + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); } - else if(ckpclocksource== RCC_CLKPSOURCE_CSI) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; } - else if (ckpclocksource== RCC_CLKPSOURCE_HSE) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; @@ -2090,44 +2184,65 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) switch (saiclocksource) { - case 0: /* PLL1 is the clock source for SAI4A */ + case RCC_SAI4ACLKSOURCE_PLL: /* PLL1 is the clock source for SAI4A */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } break; } - case RCC_D3CCIPR_SAI4ASEL_0: /* PLLI2 is the clock source for SAI4A */ + case RCC_SAI4ACLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4A */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } break; } - case RCC_D3CCIPR_SAI4ASEL_1: /* PLLI3 is the clock source for SAI4A */ + case RCC_SAI4ACLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4A */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } break; } - case RCC_D3CCIPR_SAI4ASEL_2: /* CKPER is the clock source for SAI4A*/ + case RCC_SAI4ACLKSOURCE_CLKP: /* CKPER is the clock source for SAI4A*/ { ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - if(ckpclocksource== RCC_CLKPSOURCE_HSI) + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) { /* In Case the CKPER Source is HSI */ - frequency = HSI_VALUE; + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); } - else if(ckpclocksource== RCC_CLKPSOURCE_CSI) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; } - else if (ckpclocksource== RCC_CLKPSOURCE_HSE) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; @@ -2142,7 +2257,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } - case (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1 ): /* External clock is the clock source for SAI4A */ + case RCC_SAI4ACLKSOURCE_PIN: /* External clock is the clock source for SAI4A */ { frequency = EXTERNAL_CLOCK_VALUE; break; @@ -2163,44 +2278,65 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) switch (saiclocksource) { - case 0: /* PLL1 is the clock source for SAI4B */ + case RCC_SAI4BCLKSOURCE_PLL: /* PLL1 is the clock source for SAI4B */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } break; } - case RCC_D3CCIPR_SAI4BSEL_0: /* PLLI2 is the clock source for SAI4B */ + case RCC_SAI4BCLKSOURCE_PLL2: /* PLLI2 is the clock source for SAI4B */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } break; } - case RCC_D3CCIPR_SAI4BSEL_1: /* PLLI3 is the clock source for SAI4B */ + case RCC_SAI4BCLKSOURCE_PLL3: /* PLLI3 is the clock source for SAI4B */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } break; } - case RCC_D3CCIPR_SAI4BSEL_2: /* CKPER is the clock source for SAI4B*/ + case RCC_SAI4BCLKSOURCE_CLKP: /* CKPER is the clock source for SAI4B*/ { ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - if(ckpclocksource== RCC_CLKPSOURCE_HSI) + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) { /* In Case the CKPER Source is HSI */ - frequency = HSI_VALUE; + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); } - else if(ckpclocksource== RCC_CLKPSOURCE_CSI) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; } - else if (ckpclocksource== RCC_CLKPSOURCE_HSE) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; @@ -2215,7 +2351,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) break; } - case (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1 ): /* External clock is the clock source for SAI4B */ + case RCC_SAI4BCLKSOURCE_PIN: /* External clock is the clock source for SAI4B */ { frequency = EXTERNAL_CLOCK_VALUE; break; @@ -2236,44 +2372,65 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) switch (srcclk) { - case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for I2S */ + case RCC_SPI123CLKSOURCE_PLL: /* PLL1 is the clock source for SPI123 */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } break; } - case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for I2S */ + case RCC_SPI123CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI123 */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } break; } - case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for I2S */ + case RCC_SPI123CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI123 */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_P_Frequency; + } + else + { + frequency = 0; + } break; } - case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for I2S */ + case RCC_SPI123CLKSOURCE_CLKP: /* CKPER is the clock source for SPI123 */ { ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - if(ckpclocksource== RCC_CLKPSOURCE_HSI) + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) { /* In Case the CKPER Source is HSI */ - frequency = HSI_VALUE; + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); } - else if(ckpclocksource== RCC_CLKPSOURCE_CSI) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; } - else if (ckpclocksource== RCC_CLKPSOURCE_HSE) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; @@ -2309,14 +2466,28 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { case RCC_ADCCLKSOURCE_PLL2: { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_P_Frequency; + } + else + { + frequency = 0; + } break; } case RCC_ADCCLKSOURCE_PLL3: { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_R_Frequency; + } + else + { + frequency = 0; + } break; } @@ -2325,19 +2496,19 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) ckpclocksource= __HAL_RCC_GET_CLKP_SOURCE(); - if(ckpclocksource== RCC_CLKPSOURCE_HSI) + if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSI)) { /* In Case the CKPER Source is HSI */ - frequency = HSI_VALUE; + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); } - else if(ckpclocksource== RCC_CLKPSOURCE_CSI) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) && (ckpclocksource == RCC_CLKPSOURCE_CSI)) { /* In Case the CKPER Source is CSI */ frequency = CSI_VALUE; } - else if (ckpclocksource== RCC_CLKPSOURCE_HSE) + else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (ckpclocksource == RCC_CLKPSOURCE_HSE)) { /* In Case the CKPER Source is HSE */ frequency = HSE_VALUE; @@ -2368,14 +2539,28 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) { case RCC_SDMMCCLKSOURCE_PLL: /* PLL1 is the clock source for SDMMC */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } break; } case RCC_SDMMCCLKSOURCE_PLL2: /* PLL2 is the clock source for SDMMC */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_R_Frequency; + } + else + { + frequency = 0; + } break; } @@ -2400,29 +2585,64 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } case RCC_SPI6CLKSOURCE_PLL2: /* PLL2 is the clock source for SPI6 */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } break; } case RCC_SPI6CLKSOURCE_PLL3: /* PLL3 is the clock source for SPI6 */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3RDY)) + { HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); frequency = pll3_clocks.PLL3_Q_Frequency; + } + else + { + frequency = 0; + } break; } case RCC_SPI6CLKSOURCE_HSI: /* HSI is the clock source for SPI6 */ { - frequency = HSI_VALUE; + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) + { + frequency = (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3)); + } + else + { + frequency = 0; + } break; } case RCC_SPI6CLKSOURCE_CSI: /* CSI is the clock source for SPI6 */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_CSIRDY)) + { frequency = CSI_VALUE; + } + else + { + frequency = 0; + } break; } case RCC_SPI6CLKSOURCE_HSE: /* HSE is the clock source for SPI6 */ { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { frequency = HSE_VALUE; + } + else + { + frequency = 0; + } break; } #if defined(RCC_SPI6CLKSOURCE_PIN) @@ -2439,6 +2659,58 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) } } } + else if (PeriphClk == RCC_PERIPHCLK_FDCAN) + { + /* Get FDCAN clock source */ + srcclk= __HAL_RCC_GET_FDCAN_SOURCE(); + + switch (srcclk) + { + case RCC_FDCANCLKSOURCE_HSE: /* HSE is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + { + frequency = HSE_VALUE; + } + else + { + frequency = 0; + } + break; + } + case RCC_FDCANCLKSOURCE_PLL: /* PLL is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL1RDY)) + { + HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); + frequency = pll1_clocks.PLL1_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + case RCC_FDCANCLKSOURCE_PLL2: /* PLL2 is the clock source for FDCAN */ + { + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL2RDY)) + { + HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); + frequency = pll2_clocks.PLL2_Q_Frequency; + } + else + { + frequency = 0; + } + break; + } + default : + { + frequency = 0; + break; + } + } + } else { frequency = 0; @@ -2668,7 +2940,7 @@ void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks) break; default: - pll1vco = ((float_t)CSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); break; } diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.h index 5740ad45e9..a08e3dba5f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc_ex.h @@ -3210,7 +3210,7 @@ typedef struct MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) #else #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \ - MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) + MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__)) #endif /* RCC_D2CCIP2R_CECSEL */ /** @brief macro to get the CEC clock source. @@ -4303,8 +4303,6 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); #define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) || \ ((VALUE) == RCC_PLL3VCOMEDIUM)) -#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U) - #define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \ ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) || \ ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) || \ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.c index 09aa1e88aa..ff1cf102d9 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.c @@ -114,12 +114,12 @@ * @{ */ /* Health test control register information to use in CCM algorithm */ -#define RNG_HTCFG_1 0x17590ABCU /*!< magic number */ +#define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ #if defined(RNG_VER_3_1) || defined(RNG_VER_3_0) -#define RNG_HTCFG 0x000CAA74U /*!< for best latency and To be compliant with NIST */ -#else /*RNG_VER_3_2*/ -#define RNG_HTCFG 0x00007274U /*!< for best latency and To be compliant with NIST */ -#endif +#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */ +#else /* RNG_VER_3_2 */ +#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */ +#endif /* RNG_VER_3_1 || RNG_VER_3_0 */ /** * @} */ @@ -134,7 +134,6 @@ */ /* Private macros ------------------------------------------------------------*/ /* Private functions prototypes ----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup RNG_Exported_Functions @@ -142,8 +141,8 @@ */ /** @addtogroup RNG_Exported_Functions_Group1 - * @brief Initialization and configuration functions - * + * @brief Initialization and configuration functions + * @verbatim =============================================================================== ##### Initialization and configuration functions ##### @@ -220,9 +219,9 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1); /* for best latency and to be compliant with NIST */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG); -#endif +#endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */ - /* Writing bits CONDRST=0*/ + /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); /* Get tick */ @@ -241,7 +240,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) #else /* Clock Error Detection Configuration */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED, hrng->Init.ClockErrorDetection); -#endif /* end of RNG_CR_CONDRST */ +#endif /* RNG_CR_CONDRST */ /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); @@ -297,7 +296,7 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) /* Clear Clock Error Detection bit when CONDRT bit is set to 1 */ MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_CED_ENABLE | RNG_CR_CONDRST); - /* Writing bits CONDRST=0*/ + /* Writing bit CONDRST=0 */ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); /* Get tick */ @@ -395,7 +394,8 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -614,8 +614,8 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) */ /** @addtogroup RNG_Exported_Functions_Group2 - * @brief Peripheral Control functions - * + * @brief Peripheral Control functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -660,6 +660,20 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t { /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; +#if defined(RNG_CR_CONDRST) + /* Check if there is a seed error */ + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + /* Reset from seed error */ + status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + return status; + } + } +#endif /* RNG_CR_CONDRST */ /* Get tick */ tickstart = HAL_GetTick(); @@ -679,8 +693,24 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t /* Get a 32bit Random number */ hrng->RandomNumber = hrng->Instance->DR; +#if defined(RNG_CR_CONDRST) + /* In case of seed error, the value available in the RNG_DR register must not + be used as it may not have enough entropy */ + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + /* Clear bit DRDY */ + CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY); + } + else /* No seed error */ + { + *random32bit = hrng->RandomNumber; + } +#else *random32bit = hrng->RandomNumber; +#endif /* RNG_CR_CONDRST */ hrng->State = HAL_RNG_STATE_READY; } else @@ -763,9 +793,21 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) } else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) { - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_SEED; - rngclockerror = 1U; + /* Check if Seed Error Current Status (SECS) is set */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET) + { + /* RNG IP performed the reset automatically (auto-reset) */ + /* Clear bit SEIS */ + CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI); + } + else + { + /* Seed Error has not been recovered : Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_SEED; + rngclockerror = 1U; + /* Disable the IT */ + __HAL_RNG_DISABLE_IT(hrng); + } } else { @@ -787,6 +829,8 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) /* Clear the clock error flag */ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI); + + return; } /* Check RNG data ready interrupt occurred */ @@ -869,8 +913,8 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) /** @addtogroup RNG_Exported_Functions_Group3 - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -898,7 +942,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @brief Return the RNG handle error code. * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval RNG Error Code -*/ + */ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) { /* Return RNG Error Code */ @@ -911,6 +955,96 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) /** * @} */ +#if defined(RNG_CR_CONDRST) +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup RNG_Private_Functions + * @{ + */ + +/** + * @brief RNG sequence to recover from a seed error + * @param hrng pointer to a RNG_HandleTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng) +{ + __IO uint32_t count = 0U; + + /*Check if seed error current status (SECS)is set */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET) + { + /* RNG performed the reset automatically (auto-reset) */ + /* Clear bit SEIS */ + CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI); + } + else /* Sequence to fully recover from a seed error*/ + { + /* Writing bit CONDRST=1*/ + SET_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + /* Writing bit CONDRST=0*/ + CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); + + /* Wait for conditioning reset process to be completed */ + count = RNG_TIMEOUT_VALUE; + do + { + count-- ; + if (count == 0U) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Error callback */ + hrng->ErrorCallback(hrng); +#else + /* Call legacy weak Error callback */ + HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + return HAL_ERROR; + } + } + while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)); + + if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) + { + /* Clear bit SEIS */ + CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI); + } + + /* Wait for SECS to be cleared */ + count = RNG_TIMEOUT_VALUE; + do + { + count-- ; + if (count == 0U) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); +#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) + /* Call registered Error callback */ + hrng->ErrorCallback(hrng); +#else + /* Call legacy weak Error callback */ + HAL_RNG_ErrorCallback(hrng); +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ + return HAL_ERROR; + } + } + while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS)); + } + /* Update the error code */ + hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED; + return HAL_OK; +} + +/** + * @} + */ +#endif /* RNG_CR_CONDRST */ #endif /* HAL_RNG_MODULE_ENABLED */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.h index c8b3608d76..fc4de1ae8c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng.h @@ -81,7 +81,7 @@ typedef enum typedef struct __RNG_HandleTypeDef #else typedef struct -#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ { RNG_TypeDef *Instance; /*!< Register base address */ @@ -91,7 +91,7 @@ typedef struct __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ - __IO uint32_t ErrorCode; /*!< RNG Error code */ + __IO uint32_t ErrorCode; /*!< RNG Error code */ uint32_t RandomNumber; /*!< Last Generated RNG Data */ @@ -171,14 +171,14 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t /** @defgroup RNG_Error_Definition RNG Error Definition * @{ */ -#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) #define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */ #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ -#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ +#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ -#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ /** * @} */ @@ -204,7 +204,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t } while(0U) #else #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) -#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /** * @brief Enables the RNG peripheral. @@ -285,9 +285,9 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t */ #if defined (RNG_CR_CONDRST) -/* Include HASH HAL Extended module */ +/* Include RNG HAL Extended module */ #include "stm32h7xx_hal_rng_ex.h" -#endif /* CONDRST */ +#endif /* RNG_CR_CONDRST */ /* Exported functions --------------------------------------------------------*/ /** @defgroup RNG_Exported_Functions RNG Exported Functions * @{ @@ -303,7 +303,8 @@ void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback); @@ -350,8 +351,8 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); ((IT) == RNG_IT_SEI)) #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \ - ((FLAG) == RNG_FLAG_CECS) || \ - ((FLAG) == RNG_FLAG_SECS)) + ((FLAG) == RNG_FLAG_CECS) || \ + ((FLAG) == RNG_FLAG_SECS)) /** * @brief Verify the RNG Clock Error Detection mode. @@ -364,6 +365,16 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); * @} */ +#if defined(RNG_CR_CONDRST) +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RNG_Private_Functions RNG Private functions + * @{ + */ +HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng); +/** + * @} + */ +#endif /* RNG_CR_CONDRST */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.c index dad4322461..4377a04088 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.c @@ -29,7 +29,7 @@ * @{ */ -#if defined (RNG) +#if defined(RNG) /** @addtogroup RNGEx * @brief RNG Extended HAL module driver. @@ -37,19 +37,19 @@ */ #ifdef HAL_RNG_MODULE_ENABLED -#if defined (RNG_CR_CONDRST) +#if defined(RNG_CR_CONDRST) /* Private types -------------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /** @defgroup RNGEx_Private_Defines RNGEx Private Defines * @{ */ /* Health test control register information to use in CCM algorithm */ -#define RNG_HTCFG_1 0x17590ABCU /*!< magic number */ +#define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ #if defined(RNG_VER_3_1) || defined(RNG_VER_3_0) -#define RNG_HTCFG 0x000CAA74U /*!< for best latency and To be compliant with NIST */ -#else /*RNG_VER_3_2*/ -#define RNG_HTCFG 0x00007274U /*!< for best latency and To be compliant with NIST */ -#endif +#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */ +#else /* RNG_VER_3_2 */ +#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */ +#endif /* RNG_VER_3_1 || RNG_VER_3_0 */ /** * @} */ @@ -64,7 +64,7 @@ */ /* Private macros ------------------------------------------------------------*/ /* Private functions prototypes ----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @addtogroup RNGEx_Exported_Functions @@ -72,8 +72,8 @@ */ /** @addtogroup RNGEx_Exported_Functions_Group1 - * @brief Configuration functions - * + * @brief Configuration functions + * @verbatim =============================================================================== ##### Configuration and lock functions ##### @@ -95,7 +95,7 @@ * the configuration information for RNG module * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf) { uint32_t tickstart; @@ -144,9 +144,9 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1); /* for best latency and to be compliant with NIST */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG); -#endif +#endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */ - /* Writing bits CONDRST=0*/ + /* Writing bit CONDRST=0*/ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST); /* Get tick */ tickstart = HAL_GetTick(); @@ -190,7 +190,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef * the configuration information for RNG module * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf) { @@ -234,12 +234,12 @@ HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef /** * @brief RNG current configuration lock. * @note This function allows to lock RNG peripheral configuration. - * Once locked, HW RNG reset has to be perfomed prior any further + * Once locked, HW RNG reset has to be performed prior any further * configuration update. * @param hrng pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) { HAL_StatusTypeDef status; @@ -280,11 +280,63 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ +/** @addtogroup RNGEx_Exported_Functions_Group2 + * @brief Recover from seed error function + * +@verbatim + =============================================================================== + ##### Configuration and lock functions ##### + =============================================================================== + [..] This section provide function allowing to: + (+) Recover from a seed error + +@endverbatim + * @{ + */ + +/** + * @brief RNG sequence to recover from a seed error + * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) +{ + HAL_StatusTypeDef status; + + /* Check the RNG handle allocation */ + if (hrng == NULL) + { + return HAL_ERROR; + } + + /* Check RNG peripheral state */ + if (hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* sequence to fully recover from a seed error */ + status = RNG_RecoverSeedError(hrng); + } + else + { + hrng->ErrorCode = HAL_RNG_ERROR_BUSY; + status = HAL_ERROR; + } + + /* Return the function status */ + return status; +} + /** * @} */ -#endif /* CONDRST */ +/** + * @} + */ + +#endif /* RNG_CR_CONDRST */ #endif /* HAL_RNG_MODULE_ENABLED */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.h index 4e47abb1f5..1f7fc848bd 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rng_ex.h @@ -32,8 +32,8 @@ extern "C" { * @{ */ -#if defined (RNG) -#if defined (RNG_CR_CONDRST) +#if defined(RNG) +#if defined(RNG_CR_CONDRST) /** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver @@ -71,7 +71,7 @@ typedef struct */ /** @defgroup RNGEX_Clock_Divider_Factor Value used to configure an internal - * programmable divider acting on the incoming RNG clock + * programmable divider acting on the incoming RNG clock * @{ */ #define RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */ @@ -184,8 +184,8 @@ typedef struct /** - * @} - */ + * @} + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup RNGEx_Private_Functions RNGEx Private Functions @@ -212,6 +212,11 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ +/** @addtogroup RNGEx_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); + /** * @} */ @@ -224,7 +229,11 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -#endif /* CONDRST */ +/** + * @} + */ + +#endif /* RNG_CR_CONDRST */ #endif /* RNG */ /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc_ex.h index 947671835e..833ae6f9c7 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rtc_ex.h @@ -638,7 +638,7 @@ typedef struct * @} */ -/** @defgroup RTCEx_Tamper_DetectionOutput_Definitions RTC Tamper Detection Ouput Definitions +/** @defgroup RTCEx_Tamper_DetectionOutput_Definitions RTC Tamper Detection Output Definitions * @{ */ #if defined(RTC_CR_TAMPOE) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.c index bdbdb62b39..fefb0116e0 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sai.c @@ -1687,7 +1687,7 @@ HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, /* Enable SAI Tx DMA Request */ hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - /* Wait untill FIFO is not empty */ + /* Wait until FIFO is not empty */ while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY) { /* Check for the Timeout */ @@ -1886,7 +1886,7 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) uint32_t cr1config = hsai->Instance->CR1; uint32_t tmperror; - /* SAI Fifo request interrupt occured ------------------------------------*/ + /* SAI Fifo request interrupt occurred ------------------------------------*/ if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) { hsai->InterruptServiceRoutine(hsai); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.c index b2467ca30f..6bf4dcc5d2 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.c @@ -268,38 +268,42 @@ /** @addtogroup SD_Private_Defines * @{ */ +/* Frequencies used in the driver for clock divider calculation */ +#define SD_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */ +#define SD_NORMAL_SPEED_FREQ 25000000U /* Normal speed phase : 25 MHz max */ +#define SD_HIGH_SPEED_FREQ 50000000U /* High speed phase : 50 MHz max */ +/* Private macro -------------------------------------------------------------*/ +#if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2) +#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)? \ + DLYB_SDMMC1 : DLYB_SDMMC2 ) +#elif defined (DLYB_SDMMC1) +#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 ) +#endif /* (DLYB_SDMMC1) && defined (DLYB_SDMMC2) */ /** * @} */ -/* Private macro -------------------------------------------------------------*/ -#if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2) -#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)? \ - DLYB_SDMMC1 : DLYB_SDMMC2 ) -#elif defined (DLYB_SDMMC1) -#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 ) -#endif /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup SD_Private_Functions SD Private Functions * @{ */ -static uint32_t SD_InitCard (SD_HandleTypeDef *hsd); -static uint32_t SD_PowerON (SD_HandleTypeDef *hsd); -static uint32_t SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus); -static uint32_t SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus); -static uint32_t SD_WideBus_Enable (SD_HandleTypeDef *hsd); +static uint32_t SD_InitCard(SD_HandleTypeDef *hsd); +static uint32_t SD_PowerON(SD_HandleTypeDef *hsd); +static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); +static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd); static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); -static uint32_t SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR); -static void SD_PowerOFF (SD_HandleTypeDef *hsd); -static void SD_Write_IT (SD_HandleTypeDef *hsd); -static void SD_Read_IT (SD_HandleTypeDef *hsd); -static uint32_t SD_HighSpeed (SD_HandleTypeDef *hsd); +static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); +static void SD_PowerOFF(SD_HandleTypeDef *hsd); +static void SD_Write_IT(SD_HandleTypeDef *hsd); +static void SD_Read_IT(SD_HandleTypeDef *hsd); +static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd); #if (USE_SD_TRANSCEIVER != 0U) -static uint32_t SD_UltraHighSpeed (SD_HandleTypeDef *hsd); -static uint32_t SD_DDR_Mode (SD_HandleTypeDef *hsd); +static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd); +static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd); #endif /* USE_SD_TRANSCEIVER */ /** * @} @@ -311,8 +315,8 @@ static uint32_t SD_DDR_Mode (SD_HandleTypeDef *hsd); */ /** @addtogroup SD_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions - * + * @brief Initialization and de-initialization functions + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -334,11 +338,12 @@ static uint32_t SD_DDR_Mode (SD_HandleTypeDef *hsd); HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) { HAL_SD_CardStatusTypeDef CardStatus; - uint32_t speedgrade, unitsize; + uint32_t speedgrade; + uint32_t unitsize; uint32_t tickstart; /* Check the SD handle allocation */ - if(hsd == NULL) + if (hsd == NULL) { return HAL_ERROR; } @@ -351,7 +356,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv)); - if(hsd->State == HAL_SD_STATE_RESET) + if (hsd->State == HAL_SD_STATE_RESET) { /* Allocate lock resource and initialize it */ hsd->Lock = HAL_UNLOCKED; @@ -362,7 +367,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) { hsd->Init.TranceiverPresent = SDMMC_TRANSCEIVER_PRESENT; } -#endif +#endif /*USE_SD_TRANSCEIVER */ #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) /* Reset Callback pointers in HAL_SD_STATE_RESET only */ hsd->TxCpltCallback = HAL_SD_TxCpltCallback; @@ -380,7 +385,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) } #endif /* USE_SD_TRANSCEIVER */ - if(hsd->MspInitCallback == NULL) + if (hsd->MspInitCallback == NULL) { hsd->MspInitCallback = HAL_SD_MspInit; } @@ -401,7 +406,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) return HAL_ERROR; } - if( HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK) + if (HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK) { return HAL_ERROR; } @@ -425,19 +430,19 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) } /* Configure the bus wide */ - if(HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK) + if (HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK) { return HAL_ERROR; } /* Verify that SD card is ready to use after Initialization */ tickstart = HAL_GetTick(); - while((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) + while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) { - if((HAL_GetTick()-tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State= HAL_SD_STATE_READY; + hsd->State = HAL_SD_STATE_READY; return HAL_TIMEOUT; } } @@ -475,17 +480,25 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /* Init Clock should be less or equal to 400Khz*/ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); - Init.ClockDiv = sdmmc_clk/(2U*400000U); + if (sdmmc_clk == 0U) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; + return HAL_ERROR; + } + Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ); #if (USE_SD_TRANSCEIVER != 0U) + Init.TranceiverPresent = hsd->Init.TranceiverPresent; + if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) { /* Set Transceiver polarity */ hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; } #elif defined (USE_SD_DIRPOL) - /* Set Transceiver polarity */ - hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; + /* Set Transceiver polarity */ + hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; #endif /* USE_SD_TRANSCEIVER */ /* Initialize SDMMC peripheral interface with default configuration */ @@ -496,20 +509,12 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /* wait 74 Cycles: required power up waiting time before starting the SD initialization sequence */ - sdmmc_clk = sdmmc_clk/(2U*Init.ClockDiv); - - if(sdmmc_clk != 0U) - { - HAL_Delay(1U+ (74U*1000U/(sdmmc_clk))); - } - else - { - HAL_Delay(2U); - } + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); /* Identify card operating voltage */ errorstate = SD_PowerON(hsd); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->State = HAL_SD_STATE_READY; hsd->ErrorCode |= errorstate; @@ -518,7 +523,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /* Card initialization */ errorstate = SD_InitCard(hsd); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->State = HAL_SD_STATE_READY; hsd->ErrorCode |= errorstate; @@ -527,7 +532,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -547,7 +552,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) { /* Check the SD handle allocation */ - if(hsd == NULL) + if (hsd == NULL) { return HAL_ERROR; } @@ -558,11 +563,11 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) hsd->State = HAL_SD_STATE_BUSY; #if (USE_SD_TRANSCEIVER != 0U) - /* Desactivate the 1.8V Mode */ + /* Deactivate the 1.8V Mode */ if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - if(hsd->DriveTransceiver_1_8V_Callback == NULL) + if (hsd->DriveTransceiver_1_8V_Callback == NULL) { hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback; } @@ -577,7 +582,7 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) SD_PowerOFF(hsd); #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - if(hsd->MspDeInitCallback == NULL) + if (hsd->MspDeInitCallback == NULL) { hsd->MspDeInitCallback = HAL_SD_MspDeInit; } @@ -631,8 +636,8 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) */ /** @addtogroup SD_Exported_Functions_Group2 - * @brief Data transfer functions - * + * @brief Data transfer functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -657,26 +662,29 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, + uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count, data, dataremaining; + uint32_t count; + uint32_t data; + uint32_t dataremaining; uint32_t add = BlockAdd; uint8_t *tempbuff = pData; - if(NULL == pData) + if (NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -687,7 +695,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 /* Initialize data control register */ hsd->Instance->DCTRL = 0U; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -700,10 +708,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; @@ -717,7 +725,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 /* Read Single Block command */ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); } - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -729,12 +737,12 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 /* Poll on SDMMC flags */ dataremaining = config.DataLength; - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) { /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = SDMMC_ReadFIFO(hsd->Instance); *tempbuff = (uint8_t)(data & 0xFFU); @@ -749,26 +757,26 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 dataremaining -= 32U; } - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; - hsd->State= HAL_SD_STATE_READY; + hsd->State = HAL_SD_STATE_READY; hsd->Context = SD_CONTEXT_NONE; return HAL_TIMEOUT; } } - __SDMMC_CMDTRANS_DISABLE( hsd->Instance); + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); /* Send stop transmission command in case of multiblock read */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) { - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { /* Send stop transmission command */ errorstate = SDMMC_CmdStopTransfer(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -781,7 +789,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 } /* Get error state */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -790,7 +798,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -799,7 +807,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -839,26 +847,29 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, + uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count, data, dataremaining; + uint32_t count; + uint32_t data; + uint32_t dataremaining; uint32_t add = BlockAdd; uint8_t *tempbuff = pData; - if(NULL == pData) + if (NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -869,7 +880,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint /* Initialize data control register */ hsd->Instance->DCTRL = 0U; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -882,10 +893,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; @@ -899,7 +910,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -911,12 +922,13 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint /* Write block(s) in polling mode */ dataremaining = config.DataLength; - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + SDMMC_FLAG_DATAEND)) { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) { /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = (uint32_t)(*tempbuff); tempbuff++; @@ -931,7 +943,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint dataremaining -= 32U; } - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -941,16 +953,16 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint return HAL_TIMEOUT; } } - __SDMMC_CMDTRANS_DISABLE( hsd->Instance); + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); /* Send stop transmission command in case of multiblock write */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) { - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { /* Send stop transmission command */ errorstate = SDMMC_CmdStopTransfer(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -963,7 +975,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint } /* Get error state */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -972,7 +984,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -981,7 +993,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1022,23 +1034,24 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1052,7 +1065,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui hsd->pRxBuffPtr = pData; hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -1065,10 +1078,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); /* Read Blocks in IT mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT); @@ -1082,7 +1095,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui /* Read Single Block command */ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); } - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1092,7 +1105,8 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui return HAL_ERROR; } - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_RXFIFOHF)); return HAL_OK; } @@ -1115,23 +1129,24 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1145,7 +1160,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u hsd->pTxBuffPtr = pData; hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -1159,12 +1174,12 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { - hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT); + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_IT); /* Write Multi Block command */ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); @@ -1176,7 +1191,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1187,7 +1202,8 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u } /* Enable transfer interrupts */ - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_TXFIFOHE)); return HAL_OK; } @@ -1210,23 +1226,24 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1240,7 +1257,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u hsd->pRxBuffPtr = pData; hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -1254,12 +1271,12 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); hsd->Instance->IDMABASE0 = (uint32_t) pData ; hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; /* Read Blocks in DMA mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); @@ -1273,7 +1290,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Read Single Block command */ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); } - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1308,23 +1325,24 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1338,7 +1356,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, hsd->pTxBuffPtr = pData; hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -1353,13 +1371,13 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); hsd->Instance->IDMABASE0 = (uint32_t) pData ; hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); @@ -1373,7 +1391,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1409,17 +1427,17 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui uint32_t start_add = BlockStartAdd; uint32_t end_add = BlockEndAdd; - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if(end_add < start_add) + if (end_add < start_add) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(end_add > (hsd->SdCard.LogBlockNbr)) + if (end_add > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1428,7 +1446,7 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui hsd->State = HAL_SD_STATE_BUSY; /* Check if the card command class supports erase command */ - if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U) + if (((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1437,7 +1455,7 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui return HAL_ERROR; } - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1447,18 +1465,18 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui } /* Get start and end block for high capacity cards */ - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { start_add *= 512U; end_add *= 512U; } /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1469,7 +1487,7 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1481,7 +1499,7 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui /* Send CMD38 ERASE */ errorstate = SDMMC_CmdErase(hsd->Instance, 0UL); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1511,28 +1529,28 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) uint32_t context = hsd->Context; /* Check for SDMMC interrupt flags */ - if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) { SD_Read_IT(hsd); } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ - SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ - SDMMC_IT_RXFIFOHF); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \ + SDMMC_IT_RXFIFOHF); __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); - __SDMMC_CMDTRANS_DISABLE( hsd->Instance); + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); - if((context & SD_CONTEXT_IT) != 0U) + if ((context & SD_CONTEXT_IT) != 0U) { - if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) @@ -1548,7 +1566,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) hsd->State = HAL_SD_STATE_READY; hsd->Context = SD_CONTEXT_NONE; - if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->RxCpltCallback(hsd); @@ -1565,17 +1583,17 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } - else if((context & SD_CONTEXT_DMA) != 0U) + else if ((context & SD_CONTEXT_DMA) != 0U) { hsd->Instance->DLEN = 0; hsd->Instance->DCTRL = 0; hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; /* Stop Transfer for Write Multi blocks or Read Multi blocks */ - if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) @@ -1588,7 +1606,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) hsd->State = HAL_SD_STATE_READY; hsd->Context = SD_CONTEXT_NONE; - if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->TxCpltCallback(hsd); @@ -1596,7 +1614,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) HAL_SD_TxCpltCallback(hsd); #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } - if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->RxCpltCallback(hsd); @@ -1611,27 +1629,28 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } } - else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + else if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) { SD_Write_IT(hsd); } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | + SDMMC_FLAG_TXUNDERR) != RESET) { /* Set Error code */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET) { hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET) { hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET) { hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET) { hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; } @@ -1640,17 +1659,17 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Disable all interrupts */ - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); - __SDMMC_CMDTRANS_DISABLE( hsd->Instance); + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP; hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP); __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT); - if((context & SD_CONTEXT_IT) != 0U) + if ((context & SD_CONTEXT_IT) != 0U) { /* Set the SD state to ready to be able to start again the process */ hsd->State = HAL_SD_STATE_READY; @@ -1661,9 +1680,9 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) HAL_SD_ErrorCallback(hsd); #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } - else if((context & SD_CONTEXT_DMA) != 0U) + else if ((context & SD_CONTEXT_DMA) != 0U) { - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if (hsd->ErrorCode != HAL_SD_ERROR_NONE) { /* Disable Internal DMA */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); @@ -1684,13 +1703,13 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC); - if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) + if (READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) { /* Current buffer is buffer0, Transfer complete for buffer1 */ - if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->Write_DMADblBuf1CpltCallback(hsd); @@ -1710,7 +1729,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) else /* SD_DMA_BUFFER1 */ { /* Current buffer is buffer1, Transfer complete for buffer0 */ - if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->Write_DMADblBuf0CpltCallback(hsd); @@ -1745,11 +1764,11 @@ HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) } /** -* @brief Return the SD error code -* @param hsd : Pointer to a SD_HandleTypeDef structure that contains + * @brief Return the SD error code + * @param hsd : Pointer to a SD_HandleTypeDef structure that contains * the configuration information. -* @retval SD Error Code -*/ + * @retval SD Error Code + */ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) { return hsd->ErrorCode; @@ -1851,11 +1870,12 @@ __weak void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status) * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, + pSD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; @@ -1865,64 +1885,64 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback /* Process locked */ __HAL_LOCK(hsd); - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { switch (CallbackID) { - case HAL_SD_TX_CPLT_CB_ID : - hsd->TxCpltCallback = pCallback; - break; - case HAL_SD_RX_CPLT_CB_ID : - hsd->RxCpltCallback = pCallback; - break; - case HAL_SD_ERROR_CB_ID : - hsd->ErrorCallback = pCallback; - break; - case HAL_SD_ABORT_CB_ID : - hsd->AbortCpltCallback = pCallback; - break; - case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : - hsd->Read_DMADblBuf0CpltCallback = pCallback; - break; - case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : - hsd->Read_DMADblBuf1CpltCallback = pCallback; - break; - case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : - hsd->Write_DMADblBuf0CpltCallback = pCallback; - break; - case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : - hsd->Write_DMADblBuf1CpltCallback = pCallback; - break; - case HAL_SD_MSP_INIT_CB_ID : - hsd->MspInitCallback = pCallback; - break; - case HAL_SD_MSP_DEINIT_CB_ID : - hsd->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = pCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = pCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = pCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = pCallback; + break; + case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Read_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Read_DMADblBuf1CpltCallback = pCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Write_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Write_DMADblBuf1CpltCallback = pCallback; + break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else if (hsd->State == HAL_SD_STATE_RESET) { switch (CallbackID) { - case HAL_SD_MSP_INIT_CB_ID : - hsd->MspInitCallback = pCallback; - break; - case HAL_SD_MSP_DEINIT_CB_ID : - hsd->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1963,64 +1983,64 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba /* Process locked */ __HAL_LOCK(hsd); - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { switch (CallbackID) { - case HAL_SD_TX_CPLT_CB_ID : - hsd->TxCpltCallback = HAL_SD_TxCpltCallback; - break; - case HAL_SD_RX_CPLT_CB_ID : - hsd->RxCpltCallback = HAL_SD_RxCpltCallback; - break; - case HAL_SD_ERROR_CB_ID : - hsd->ErrorCallback = HAL_SD_ErrorCallback; - break; - case HAL_SD_ABORT_CB_ID : - hsd->AbortCpltCallback = HAL_SD_AbortCallback; - break; - case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : - hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuf0CpltCallback; - break; - case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : - hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuf1CpltCallback; - break; - case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : - hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuf0CpltCallback; - break; - case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : - hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuf1CpltCallback; - break; - case HAL_SD_MSP_INIT_CB_ID : - hsd->MspInitCallback = HAL_SD_MspInit; - break; - case HAL_SD_MSP_DEINIT_CB_ID : - hsd->MspDeInitCallback = HAL_SD_MspDeInit; - break; - default : - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = HAL_SD_TxCpltCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = HAL_SD_RxCpltCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = HAL_SD_ErrorCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = HAL_SD_AbortCallback; + break; + case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuf0CpltCallback; + break; + case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuf1CpltCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuf0CpltCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuf1CpltCallback; + break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else if (hsd->State == HAL_SD_STATE_RESET) { switch (CallbackID) { - case HAL_SD_MSP_INIT_CB_ID : - hsd->MspInitCallback = HAL_SD_MspInit; - break; - case HAL_SD_MSP_DEINIT_CB_ID : - hsd->MspDeInitCallback = HAL_SD_MspDeInit; - break; - default : - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -2048,7 +2068,7 @@ HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_ { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; @@ -2058,7 +2078,7 @@ HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_ /* Process locked */ __HAL_LOCK(hsd); - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->DriveTransceiver_1_8V_Callback = pCallback; } @@ -2088,7 +2108,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) /* Process locked */ __HAL_LOCK(hsd); - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback; } @@ -2112,8 +2132,8 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) */ /** @addtogroup SD_Exported_Functions_Group3 - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### Peripheral Control functions ##### @@ -2195,7 +2215,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef pCSD->Reserved2 = 0U; /*!< Reserved */ - if(hsd->SdCard.CardType == CARD_SDSC) + if (hsd->SdCard.CardType == CARD_SDSC) { pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)); @@ -2213,10 +2233,10 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); hsd->SdCard.LogBlockSize = 512U; } - else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) + else if (hsd->SdCard.CardType == CARD_SDHC_SDXC) { /* Byte 7 */ pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)); @@ -2247,7 +2267,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); - pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); + pCSD->MaxWrBlockLen = (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); @@ -2265,7 +2285,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); - pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); + pCSD->ECC = (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); @@ -2288,7 +2308,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT HAL_StatusTypeDef status = HAL_OK; errorstate = SD_SendSDStatus(hsd, sd_status); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2326,7 +2346,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2374,6 +2394,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t { SDMMC_InitTypeDef Init; uint32_t errorstate; + uint32_t sdmmc_clk; HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ @@ -2382,19 +2403,19 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t /* Change State */ hsd->State = HAL_SD_STATE_BUSY; - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { - if(WideMode == SDMMC_BUS_WIDE_8B) + if (WideMode == SDMMC_BUS_WIDE_8B) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; } - else if(WideMode == SDMMC_BUS_WIDE_4B) + else if (WideMode == SDMMC_BUS_WIDE_4B) { errorstate = SD_WideBus_Enable(hsd); hsd->ErrorCode |= errorstate; } - else if(WideMode == SDMMC_BUS_WIDE_1B) + else if (WideMode == SDMMC_BUS_WIDE_1B) { errorstate = SD_WideBus_Disable(hsd); @@ -2412,7 +2433,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; } - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if (hsd->ErrorCode != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2420,39 +2441,94 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t } else { - /* Configure the SDMMC peripheral */ - Init.ClockEdge = hsd->Init.ClockEdge; - Init.ClockPowerSave = hsd->Init.ClockPowerSave; - Init.BusWide = WideMode; - Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC); + if (sdmmc_clk != 0U) + { + /* Configure the SDMMC peripheral */ + Init.ClockEdge = hsd->Init.ClockEdge; + Init.ClockPowerSave = hsd->Init.ClockPowerSave; + Init.BusWide = WideMode; + Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; - /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */ - if(hsd->Init.ClockDiv >= SDMMC_NSpeed_CLK_DIV) - { - Init.ClockDiv = hsd->Init.ClockDiv; - } - else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) - { - /* UltraHigh speed SD card,user Clock div */ - Init.ClockDiv = hsd->Init.ClockDiv; - } - else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) - { - /* High speed SD card, Max Frequency = 50Mhz */ - Init.ClockDiv = SDMMC_HSpeed_CLK_DIV; + /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */ + if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ))) + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) + { + /* UltraHigh speed SD card,user Clock div */ + Init.ClockDiv = hsd->Init.ClockDiv; + } + else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) + { + /* High speed SD card, Max Frequency = 50Mhz */ + if (hsd->Init.ClockDiv == 0U) + { + if (sdmmc_clk > SD_HIGH_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + else + { + if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + } + else + { + /* No High speed SD card, Max Frequency = 25Mhz */ + if (hsd->Init.ClockDiv == 0U) + { + if (sdmmc_clk > SD_NORMAL_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + else + { + if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + } + +#if (USE_SD_TRANSCEIVER != 0U) + Init.TranceiverPresent = hsd->Init.TranceiverPresent; +#endif /* USE_SD_TRANSCEIVER */ + + (void)SDMMC_Init(hsd->Instance, Init); } else { - /* No High speed SD card, Max Frequency = 25Mhz */ - Init.ClockDiv = SDMMC_NSpeed_CLK_DIV; + hsd->ErrorCode |= SDMMC_ERROR_INVALID_PARAMETER; + status = HAL_ERROR; } - - (void)SDMMC_Init(hsd->Instance, Init); } /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2494,7 +2570,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t { switch (SpeedMode) { - case SDMMC_SPEED_MODE_AUTO: + case SDMMC_SPEED_MODE_AUTO: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardType == CARD_SDHC_SDXC)) @@ -2525,7 +2601,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_ULTRA: + case SDMMC_SPEED_MODE_ULTRA: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardType == CARD_SDHC_SDXC)) @@ -2545,7 +2621,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_DDR: + case SDMMC_SPEED_MODE_DDR: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardType == CARD_SDHC_SDXC)) @@ -2565,11 +2641,11 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_HIGH: + case SDMMC_SPEED_MODE_HIGH: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) @@ -2585,23 +2661,23 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_DEFAULT: - break; - default: - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - status = HAL_ERROR; - break; + case SDMMC_SPEED_MODE_DEFAULT: + break; + default: + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + status = HAL_ERROR; + break; } } else { switch (SpeedMode) { - case SDMMC_SPEED_MODE_AUTO: + case SDMMC_SPEED_MODE_AUTO: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) @@ -2616,11 +2692,11 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_HIGH: + case SDMMC_SPEED_MODE_HIGH: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) @@ -2636,23 +2712,23 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_DEFAULT: - break; - case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ - default: - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - status = HAL_ERROR; - break; + case SDMMC_SPEED_MODE_DEFAULT: + break; + case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ + default: + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + status = HAL_ERROR; + break; } } #else switch (SpeedMode) { - case SDMMC_SPEED_MODE_AUTO: + case SDMMC_SPEED_MODE_AUTO: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) @@ -2667,11 +2743,11 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_HIGH: + case SDMMC_SPEED_MODE_HIGH: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) @@ -2687,13 +2763,13 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_DEFAULT: - break; - case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ - default: - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - status = HAL_ERROR; - break; + case SDMMC_SPEED_MODE_DEFAULT: + break; + case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ + default: + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + status = HAL_ERROR; + break; } #endif /* USE_SD_TRANSCEIVER */ @@ -2711,7 +2787,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2736,7 +2812,7 @@ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) uint32_t resp1 = 0; errorstate = SD_SendStatus(hsd, &resp1); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; } @@ -2757,8 +2833,8 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) HAL_SD_CardStateTypeDef CardState; /* DIsable All interrupts */ - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); /* Clear All flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); @@ -2772,11 +2848,11 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) hsd->Context = SD_CONTEXT_NONE; CardState = HAL_SD_GetCardState(hsd); - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); } - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if (hsd->ErrorCode != HAL_SD_ERROR_NONE) { return HAL_ERROR; } @@ -2794,8 +2870,8 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) HAL_SD_CardStateTypeDef CardState; /* Disable All interrupts */ - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); /* If IDMA Context, disable Internal DMA */ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; @@ -2806,12 +2882,12 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) CardState = HAL_SD_GetCardState(hsd); hsd->State = HAL_SD_STATE_READY; - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); } - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if (hsd->ErrorCode != HAL_SD_ERROR_NONE) { return HAL_ERROR; } @@ -2853,17 +2929,17 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) uint16_t sd_rca = 1U; /* Check the power State */ - if(SDMMC_GetPowerState(hsd->Instance) == 0U) + if (SDMMC_GetPowerState(hsd->Instance) == 0U) { /* Power off */ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { /* Send CMD2 ALL_SEND_CID */ errorstate = SDMMC_CmdSendCID(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -2877,24 +2953,24 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) } } - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { /* Send CMD3 SET_REL_ADDR with argument 0 */ /* SD Card publishes its RCA. */ errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } } - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { /* Get the SD card RCA */ hsd->SdCard.RelCardAdd = sd_rca; /* Send CMD9 SEND_CSD with argument as card's RCA */ errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -2919,7 +2995,7 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) /* Select the Card */ errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -2938,7 +3014,8 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { __IO uint32_t count = 0U; - uint32_t response = 0U, validvoltage = 0U; + uint32_t response = 0U; + uint32_t validvoltage = 0U; uint32_t errorstate; #if (USE_SD_TRANSCEIVER != 0U) uint32_t tickstart = HAL_GetTick(); @@ -2946,19 +3023,19 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ errorstate = SDMMC_CmdOperCond(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->SdCard.CardVersion = CARD_V1_X; /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -2969,29 +3046,30 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) hsd->SdCard.CardVersion = CARD_V2_X; } - if( hsd->SdCard.CardVersion == CARD_V2_X) + if (hsd->SdCard.CardVersion == CARD_V2_X) { /* SEND CMD55 APP_CMD with RCA as 0 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return HAL_SD_ERROR_UNSUPPORTED_FEATURE; } } /* SD CARD */ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) + while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) { /* SEND CMD55 APP_CMD with RCA as 0 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send CMD41 */ - errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY); - if(errorstate != HAL_SD_ERROR_NONE) + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | + SD_SWITCH_1_8V_CAPACITY); + if (errorstate != HAL_SD_ERROR_NONE) { return HAL_SD_ERROR_UNSUPPORTED_FEATURE; } @@ -3005,18 +3083,18 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) count++; } - if(count >= SDMMC_MAX_VOLT_TRIAL) + if (count >= SDMMC_MAX_VOLT_TRIAL) { return HAL_SD_ERROR_INVALID_VOLTRANGE; } - if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ { hsd->SdCard.CardType = CARD_SDHC_SDXC; #if (USE_SD_TRANSCEIVER != 0U) if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) { - if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY) + if ((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY) { hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; @@ -3025,15 +3103,15 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Send CMD11 to switch 1.8V mode */ errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Check to CKSTOP */ - while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP) + while ((hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP) { - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3043,7 +3121,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) hsd->Instance->ICR = SDMMC_FLAG_CKSTOP; /* Check to BusyD0 */ - if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0) + if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0) { /* Error when activate Voltage Switch in SDMMC Peripheral */ return SDMMC_ERROR_UNSUPPORTED_FEATURE; @@ -3061,9 +3139,9 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) hsd->Instance->POWER |= SDMMC_POWER_VSWITCH; /* Check VSWEND Flag */ - while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND) + while ((hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND) { - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3073,7 +3151,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) hsd->Instance->ICR = SDMMC_FLAG_VSWEND; /* Check BusyD0 status */ - if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0) + if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0) { /* Error when enabling 1.8V mode */ return HAL_SD_ERROR_INVALID_VOLTRANGE; @@ -3121,14 +3199,14 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) uint32_t *pData = pSDstatus; /* Check SD response */ - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } /* Set block size for card if it is not equal to current block size for card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_NONE; return errorstate; @@ -3136,7 +3214,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) /* Send CMD55 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_NONE; return errorstate; @@ -3153,39 +3231,39 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ errorstate = SDMMC_CmdStatusRegister(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_NONE; return errorstate; } /* Get status data */ - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { *pData = SDMMC_ReadFIFO(hsd->Instance); pData++; } } - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { return HAL_SD_ERROR_DATA_TIMEOUT; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) { return HAL_SD_ERROR_DATA_CRC_FAIL; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) { return HAL_SD_ERROR_RX_OVERRUN; } @@ -3199,7 +3277,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) *pData = SDMMC_ReadFIFO(hsd->Instance); pData++; - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3222,14 +3300,14 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) { uint32_t errorstate; - if(pCardStatus == NULL) + if (pCardStatus == NULL) { return HAL_SD_ERROR_PARAM; } /* Send Status command */ errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3250,31 +3328,31 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) uint32_t scr[2U] = {0UL, 0UL}; uint32_t errorstate; - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* If requested card supports wide bus operation */ - if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) + if ((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA.*/ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3297,31 +3375,31 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) uint32_t scr[2U] = {0UL, 0UL}; uint32_t errorstate; - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* If requested card supports 1 bit mode operation */ - if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) + if ((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3352,14 +3430,14 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /* Set Block Size To 8 Bytes */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send CMD55 APP_CMD with argument as card's RCA */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3374,14 +3452,15 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ errorstate = SDMMC_CmdSendSCR(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | + SDMMC_FLAG_DATAEND)) { - if((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U)) + if ((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U)) { tempscr[0] = SDMMC_ReadFIFO(hsd->Instance); tempscr[1] = SDMMC_ReadFIFO(hsd->Instance); @@ -3389,25 +3468,25 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) } - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); return HAL_SD_ERROR_DATA_TIMEOUT; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); return HAL_SD_ERROR_DATA_CRC_FAIL; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); @@ -3419,10 +3498,10 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \ ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); scr++; - *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \ ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); } @@ -3438,15 +3517,16 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) */ static void SD_Read_IT(SD_HandleTypeDef *hsd) { - uint32_t count, data; - uint8_t* tmp; + uint32_t count; + uint32_t data; + uint8_t *tmp; tmp = hsd->pRxBuffPtr; if (hsd->RxXferSize >= 32U) { /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = SDMMC_ReadFIFO(hsd->Instance); *tmp = (uint8_t)(data & 0xFFU); @@ -3472,15 +3552,16 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd) */ static void SD_Write_IT(SD_HandleTypeDef *hsd) { - uint32_t count, data; - uint8_t* tmp; + uint32_t count; + uint32_t data; + uint8_t *tmp; tmp = hsd->pTxBuffPtr; if (hsd->TxXferSize >= 32U) { /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = (uint32_t)(*tmp); tmp++; @@ -3511,16 +3592,17 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) uint32_t errorstate = HAL_SD_ERROR_NONE; SDMMC_DataInitTypeDef sdmmc_datainitstructure; uint32_t SD_hs[16] = {0}; - uint32_t count, loop = 0 ; + uint32_t count; + uint32_t loop = 0 ; uint32_t Timeout = HAL_GetTick(); - if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) { - /* Standard Speed Card <= 12.5Mhz */ - return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } - if(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) + if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) { /* Initialize the Data control register */ hsd->Instance->DCTRL = 0; @@ -3542,27 +3624,28 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); - errorstate = SDMMC_CmdSwitch(hsd->Instance,SDMMC_SDR25_SWITCH_PATTERN); - if(errorstate != HAL_SD_ERROR_NONE) + errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR25_SWITCH_PATTERN); + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND )) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | + SDMMC_FLAG_DATAEND)) { if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { for (count = 0U; count < 8U; count++) { - SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance); + SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance); } loop ++; } - if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State= HAL_SD_STATE_READY; + hsd->State = HAL_SD_STATE_READY; return HAL_SD_ERROR_TIMEOUT; } } @@ -3598,7 +3681,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Test if the switch mode HS is ok */ - if ((((uint8_t*)SD_hs)[13] & 2U) != 2U) + if ((((uint8_t *)SD_hs)[13] & 2U) != 2U) { errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; } @@ -3622,16 +3705,17 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) uint32_t errorstate = HAL_SD_ERROR_NONE; SDMMC_DataInitTypeDef sdmmc_datainitstructure; uint32_t SD_hs[16] = {0}; - uint32_t count, loop = 0 ; + uint32_t count; + uint32_t loop = 0 ; uint32_t Timeout = HAL_GetTick(); - if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) { - /* Standard Speed Card <= 12.5Mhz */ - return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } - if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) + if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) { /* Initialize the Data control register */ hsd->Instance->DCTRL = 0; @@ -3650,32 +3734,33 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) + if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) { return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); } errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND )) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | + SDMMC_FLAG_DATAEND)) { if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { for (count = 0U; count < 8U; count++) { - SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance); + SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance); } loop ++; } - if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State= HAL_SD_STATE_READY; + hsd->State = HAL_SD_STATE_READY; return HAL_SD_ERROR_TIMEOUT; } } @@ -3711,7 +3796,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Test if the switch mode HS is ok */ - if ((((uint8_t*)SD_hs)[13] & 2U) != 2U) + if ((((uint8_t *)SD_hs)[13] & 2U) != 2U) { errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; } @@ -3725,7 +3810,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) #if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) /* Enable DelayBlock Peripheral */ /* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */ - MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_1); + MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_1); if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK) { return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); @@ -3750,16 +3835,17 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) uint32_t errorstate = HAL_SD_ERROR_NONE; SDMMC_DataInitTypeDef sdmmc_datainitstructure; uint32_t SD_hs[16] = {0}; - uint32_t count, loop = 0 ; + uint32_t count; + uint32_t loop = 0 ; uint32_t Timeout = HAL_GetTick(); - if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) { - /* Standard Speed Card <= 12.5Mhz */ - return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } - if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) + if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) { /* Initialize the Data control register */ hsd->Instance->DCTRL = 0; @@ -3778,32 +3864,33 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) + if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) { return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); } errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_DDR50_SWITCH_PATTERN); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND )) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | + SDMMC_FLAG_DATAEND)) { if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { for (count = 0U; count < 8U; count++) { - SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance); + SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance); } loop ++; } - if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State= HAL_SD_STATE_READY; + hsd->State = HAL_SD_STATE_READY; return HAL_SD_ERROR_TIMEOUT; } } @@ -3839,7 +3926,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Test if the switch mode is ok */ - if ((((uint8_t*)SD_hs)[13] & 2U) != 2U) + if ((((uint8_t *)SD_hs)[13] & 2U) != 2U) { errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; } @@ -3853,7 +3940,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) #if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) /* Enable DelayBlock Peripheral */ /* SDMMC_CKin feedback clock selected as receive clock, for DDR50 */ - MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_0); + MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_0); if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK) { return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.h index dd06788c8c..83c97aba1a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd.h @@ -22,7 +22,7 @@ #define STM32H7xx_HAL_SD_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -56,9 +56,9 @@ typedef enum HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */ HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */ HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receiving State */ - HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */ + HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfer State */ HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */ -}HAL_SD_StateTypeDef; +} HAL_SD_StateTypeDef; /** * @} */ @@ -110,7 +110,7 @@ typedef struct uint32_t CardSpeed; /*!< Specifies the card Speed */ -}HAL_SD_CardInfoTypeDef; +} HAL_SD_CardInfoTypeDef; /** * @brief SD handle Structure definition @@ -148,22 +148,22 @@ typedef struct uint32_t CID[4]; /*!< SD card identification number table */ #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd); - void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* Read_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* Read_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* Write_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* Write_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* TxCpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* RxCpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* ErrorCallback)(struct __SD_HandleTypeDef *hsd); + void (* AbortCpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* Read_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* Read_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* Write_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* Write_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd); #if (USE_SD_TRANSCEIVER != 0U) - void (* DriveTransceiver_1_8V_Callback) (FlagStatus status); + void (* DriveTransceiver_1_8V_Callback)(FlagStatus status); #endif /* USE_SD_TRANSCEIVER */ - void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd); - void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd); + void (* MspInitCallback)(struct __SD_HandleTypeDef *hsd); + void (* MspDeInitCallback)(struct __SD_HandleTypeDef *hsd); #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ -}SD_HandleTypeDef; +} SD_HandleTypeDef; /** * @} @@ -211,7 +211,7 @@ typedef struct __IO uint8_t ECC; /*!< ECC code */ __IO uint8_t CSD_CRC; /*!< CSD CRC */ __IO uint8_t Reserved4; /*!< Always 1 */ -}HAL_SD_CardCSDTypeDef; +} HAL_SD_CardCSDTypeDef; /** * @} */ @@ -232,7 +232,7 @@ typedef struct __IO uint8_t CID_CRC; /*!< CID CRC */ __IO uint8_t Reserved2; /*!< Always 1 */ -}HAL_SD_CardCIDTypeDef; +} HAL_SD_CardCIDTypeDef; /** * @} */ @@ -255,7 +255,7 @@ typedef struct __IO uint8_t UhsSpeedGrade; /*!< Carries information about the speed grade of UHS card */ __IO uint8_t UhsAllocationUnitSize; /*!< Carries information about the UHS card's allocation unit size */ __IO uint8_t VideoSpeedClass; /*!< Carries information about the Video Speed Class of UHS card */ -}HAL_SD_CardStatusTypeDef; +} HAL_SD_CardStatusTypeDef; /** * @} */ @@ -277,7 +277,7 @@ typedef enum HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */ HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */ -}HAL_SD_CallbackIDTypeDef; +} HAL_SD_CallbackIDTypeDef; /** * @} */ @@ -285,7 +285,7 @@ typedef enum /** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition * @{ */ -typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); +typedef void (*pSD_CallbackTypeDef)(SD_HandleTypeDef *hsd); #if (USE_SD_TRANSCEIVER != 0U) typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #endif /* USE_SD_TRANSCEIVER */ @@ -315,13 +315,13 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ #define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ #define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ -#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the - number of transferred bytes does not match the block length */ +#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ + /*!< number of transferred bytes does not match the block length */ #define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ #define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ #define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ -#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock - command or if there was an attempt to access a locked card */ +#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ + /*!< command or if there was an attempt to access a locked card */ #define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ #define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ #define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ @@ -332,8 +332,8 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ #define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ #define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ -#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out - of erase sequence command was received */ +#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ + /*!< of erase sequence command was received */ #define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ #define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ #define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ @@ -342,7 +342,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ #define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ #define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ -#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) #define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ @@ -397,9 +397,9 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); /* Exported macro ------------------------------------------------------------*/ /** @defgroup SD_Exported_macros SD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ /** @brief Reset SD handle state. * @param __HANDLE__ SD Handle. * @retval None @@ -620,10 +620,10 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ -HAL_StatusTypeDef HAL_SD_Init (SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_InitCard (SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); -void HAL_SD_MspInit (SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd); +void HAL_SD_MspInit(SD_HandleTypeDef *hsd); void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); /** * @} @@ -633,23 +633,29 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); * @{ */ /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_SD_Erase (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); /* Non-Blocking mode: IT */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); -void HAL_SD_IRQHandler (SD_HandleTypeDef *hsd); +void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); /* Callback in non blocking modes (DMA) */ -void HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd); -void HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd); -void HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd); -void HAL_SD_AbortCallback (SD_HandleTypeDef *hsd); +void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd); +void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd); #if (USE_SD_TRANSCEIVER != 0U) /* Callback to switch in 1.8V mode */ @@ -658,11 +664,12 @@ void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status); #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) /* SD callback registering/unregistering */ -HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, + pSD_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID); #if (USE_SD_TRANSCEIVER != 0U) -HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback (SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd); #endif /* USE_SD_TRANSCEIVER */ #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ @@ -684,10 +691,10 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t * @{ */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); -HAL_StatusTypeDef HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); -HAL_StatusTypeDef HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} */ @@ -704,7 +711,7 @@ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); /** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management * @{ */ -HAL_StatusTypeDef HAL_SD_Abort (SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd); HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.c index d18122d771..67124cb771 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.c @@ -14,7 +14,8 @@ [..] The SD Extension HAL driver can be used as follows: (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function. - (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions. + (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() + and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions. @endverbatim ****************************************************************************** @@ -57,8 +58,8 @@ */ /** @addtogroup SDEx_Exported_Functions_Group1 - * @brief Multibuffer functions - * + * @brief Multibuffer functions + * @verbatim ============================================================================== ##### Multibuffer functions ##### @@ -74,18 +75,19 @@ /** * @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA. * @param hsd: SD handle - * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data - * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data + * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transferred data + * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transferred data * @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, + uint32_t BufferSize) { - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { - hsd->Instance->IDMABASE0= (uint32_t) pDataBuffer0; - hsd->Instance->IDMABASE1= (uint32_t) pDataBuffer1; - hsd->Instance->IDMABSIZE= (uint32_t) (BLOCKSIZE * BufferSize); + hsd->Instance->IDMABASE0 = (uint32_t) pDataBuffer0; + hsd->Instance->IDMABASE1 = (uint32_t) pDataBuffer1; + hsd->Instance->IDMABSIZE = (uint32_t)(BLOCKSIZE * BufferSize); return HAL_OK; } @@ -97,7 +99,8 @@ HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t /** * @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1. - * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before + * call this function. * @param hsd: SD handle * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Total number of blocks to read @@ -107,12 +110,13 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 { SDMMC_DataInitTypeDef config; uint32_t errorstate; - uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t DmaBase0_reg; + uint32_t DmaBase1_reg; uint32_t add = BlockAdd; - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -135,7 +139,7 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_BUSY; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -151,7 +155,7 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; @@ -160,14 +164,15 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 /* Read Multi Block command */ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->State = HAL_SD_STATE_READY; hsd->ErrorCode |= errorstate; return HAL_ERROR; } - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC)); + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | + SDMMC_IT_IDMABTC)); return HAL_OK; } @@ -179,23 +184,25 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 } /** - * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1. - * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function. + * @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before + * call this function. * @param hsd: SD handle * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; - uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t DmaBase0_reg; + uint32_t DmaBase1_reg; uint32_t add = BlockAdd; - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -216,7 +223,7 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint hsd->State = HAL_SD_STATE_BUSY; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -230,7 +237,7 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; @@ -239,14 +246,15 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint /* Write Multi Block command */ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->State = HAL_SD_STATE_READY; hsd->ErrorCode |= errorstate; return HAL_ERROR; } - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC)); + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | + SDMMC_IT_IDMABTC)); return HAL_OK; } @@ -268,9 +276,10 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint * transfer use BUFFER0. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer) +HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, + uint32_t *pDataBuffer) { - if(Buffer == SD_DMA_BUFFER0) + if (Buffer == SD_DMA_BUFFER0) { /* change the buffer0 address */ hsd->Instance->IDMABASE0 = (uint32_t)pDataBuffer; @@ -303,4 +312,8 @@ HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABu * @} */ +/** + * @} + */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.h index 800434e89c..9c71954d93 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sd_ex.h @@ -22,7 +22,7 @@ #define STM32H7xx_HAL_SD_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -50,17 +50,15 @@ typedef enum SD_DMA_BUFFER0 = 0x00U, /*!< selects SD internal DMA Buffer 0 */ SD_DMA_BUFFER1 = 0x01U, /*!< selects SD internal DMA Buffer 1 */ -}HAL_SDEx_DMABuffer_MemoryTypeDef; +} HAL_SDEx_DMABuffer_MemoryTypeDef; /** * @} */ - /** * @} */ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ + /* Exported functions --------------------------------------------------------*/ /** @defgroup SDEx_Exported_Functions SDEx Exported Functions * @{ @@ -70,10 +68,12 @@ typedef enum * @{ */ -HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, + uint32_t BufferSize); HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks); HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer); +HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, + uint32_t *pDataBuffer); void HAL_SDEx_Read_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd); void HAL_SDEx_Read_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.c index 8d71bc2b19..47c34a5d8d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.c @@ -126,20 +126,14 @@ * @{ */ -/** - @cond 0 - */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void SDRAM_DMACplt (MDMA_HandleTypeDef *hmdma); +static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma); static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma); -static void SDRAM_DMAError (MDMA_HandleTypeDef *hmdma); -/** - @endcond - */ +static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma); /* Exported functions --------------------------------------------------------*/ /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions @@ -181,7 +175,7 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy /* Allocate lock resource and initialize it */ hsdram->Lock = HAL_UNLOCKED; #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - if(hsdram->MspInitCallback == NULL) + if (hsdram->MspInitCallback == NULL) { hsdram->MspInitCallback = HAL_SDRAM_MspInit; } @@ -194,7 +188,7 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy #else /* Initialize the low level hardware (MSP) */ HAL_SDRAM_MspInit(hsdram); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } /* Initialize the SDRAM controller state */ @@ -223,7 +217,7 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) { #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - if(hsdram->MspDeInitCallback == NULL) + if (hsdram->MspDeInitCallback == NULL) { hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; } @@ -233,7 +227,7 @@ HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) #else /* Initialize the low level hardware (MSP) */ HAL_SDRAM_MspDeInit(hsdram); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /* Configure the SDRAM registers with their reset values */ (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); @@ -284,7 +278,7 @@ __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval HAL status -*/ + */ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) { /* Check SDRAM interrupt Rising edge flag */ @@ -295,7 +289,7 @@ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) hsdram->RefreshErrorCallback(hsdram); #else HAL_SDRAM_RefreshErrorCallback(hsdram); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /* Clear SDRAM refresh error interrupt pending bit */ __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); @@ -376,11 +370,12 @@ __weak void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma) * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; - uint8_t * pdestbuff = pDstBuffer; + uint8_t *pdestbuff = pDstBuffer; HAL_SDRAM_StateTypeDef state = hsdram->State; /* Check the SDRAM controller state */ @@ -427,12 +422,13 @@ HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddr * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; - uint8_t * psrcbuff = pSrcBuffer; - + uint8_t *psrcbuff = pSrcBuffer; + /* Check the SDRAM controller state */ if (hsdram->State == HAL_SDRAM_STATE_BUSY) { @@ -456,7 +452,7 @@ HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /* Update the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsdram); } @@ -477,7 +473,8 @@ HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint32_t *pSdramAddress = pAddress; @@ -498,7 +495,7 @@ HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd hsdram->State = HAL_SDRAM_STATE_BUSY; /* Read data from memory */ - for (size = BufferSize; size >= 2U ; size-=2U) + for (size = BufferSize; size >= 2U ; size -= 2U) { *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); pdestbuff++; @@ -508,7 +505,7 @@ HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd } /* Read last 16-bits if size is not 32-bits multiple */ - if ((BufferSize % 2U)!= 0U) + if ((BufferSize % 2U) != 0U) { *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); } @@ -536,12 +533,13 @@ HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint32_t *psdramaddress = pAddress; - uint16_t * psrcbuff = pSrcBuffer; - + uint16_t *psrcbuff = pSrcBuffer; + /* Check the SDRAM controller state */ if (hsdram->State == HAL_SDRAM_STATE_BUSY) { @@ -554,9 +552,9 @@ HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd /* Update the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_BUSY; - + /* Write data to memory */ - for (size = BufferSize; size >= 2U ; size-=2U) + for (size = BufferSize; size >= 2U ; size -= 2U) { *psdramaddress = (uint32_t)(*psrcbuff); psrcbuff++; @@ -566,14 +564,14 @@ HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd } /* Write last 16-bits if size is not 32-bits multiple */ - if ((BufferSize % 2U)!= 0U) + if ((BufferSize % 2U) != 0U) { *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U); } /* Update the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsdram); } @@ -594,11 +592,12 @@ HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; - uint32_t * pdestbuff = pDstBuffer; + uint32_t *pdestbuff = pDstBuffer; HAL_SDRAM_StateTypeDef state = hsdram->State; /* Check the SDRAM controller state */ @@ -645,11 +644,12 @@ HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint32_t *pSdramAddress = pAddress; - uint32_t * psrcbuff = pSrcBuffer; + uint32_t *psrcbuff = pSrcBuffer; /* Check the SDRAM controller state */ if (hsdram->State == HAL_SDRAM_STATE_BUSY) @@ -674,7 +674,7 @@ HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd /* Update the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hsdram); } @@ -695,7 +695,8 @@ HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { HAL_StatusTypeDef status; HAL_SDRAM_StateTypeDef state = hsdram->State; @@ -703,7 +704,7 @@ HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd /* Check the SDRAM controller state */ if (state == HAL_SDRAM_STATE_BUSY) { - return HAL_BUSY; + status = HAL_BUSY; } else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { @@ -724,15 +725,15 @@ HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd } hsdram->hmdma->XferErrorCallback = SDRAM_DMAError; - /* Enable the DMA Stream */ - status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1); + /* Enable the DMA Stream */ + status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1); /* Process Unlocked */ __HAL_UNLOCK(hsdram); } else { - return HAL_ERROR; + status = HAL_ERROR; } return status; @@ -747,14 +748,15 @@ HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { HAL_StatusTypeDef status; /* Check the SDRAM controller state */ if (hsdram->State == HAL_SDRAM_STATE_BUSY) { - return HAL_BUSY; + status = HAL_BUSY; } else if (hsdram->State == HAL_SDRAM_STATE_READY) { @@ -768,15 +770,15 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt; hsdram->hmdma->XferErrorCallback = SDRAM_DMAError; - /* Enable the DMA Stream */ - status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1); + /* Enable the DMA Stream */ + status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1); /* Process Unlocked */ __HAL_UNLOCK(hsdram); } else { - return HAL_ERROR; + status = HAL_ERROR; } return status; @@ -795,53 +797,54 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SDRAM_StateTypeDef state; - - if(pCallback == NULL) + + if (pCallback == NULL) { return HAL_ERROR; } /* Process locked */ __HAL_LOCK(hsdram); - + state = hsdram->State; - if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { switch (CallbackId) { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = pCallback; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = pCallback; - break; - case HAL_SDRAM_REFRESH_ERR_CB_ID : - hsdram->RefreshErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hsdram->State == HAL_SDRAM_STATE_RESET) + else if (hsdram->State == HAL_SDRAM_STATE_RESET) { switch (CallbackId) { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = pCallback; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -868,54 +871,54 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_S * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID * @retval status */ -HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; HAL_SDRAM_StateTypeDef state; - + /* Process locked */ __HAL_LOCK(hsdram); state = hsdram->State; - if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { switch (CallbackId) { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = HAL_SDRAM_MspInit; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; - break; - case HAL_SDRAM_REFRESH_ERR_CB_ID : - hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; - break; - case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : - hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; - break; - case HAL_SDRAM_DMA_XFER_ERR_CB_ID : - hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; + break; + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hsdram->State == HAL_SDRAM_STATE_RESET) + else if (hsdram->State == HAL_SDRAM_STATE_RESET) { switch (CallbackId) { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = HAL_SDRAM_MspInit; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -940,12 +943,13 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_DmaCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SDRAM_StateTypeDef state; - - if(pCallback == NULL) + + if (pCallback == NULL) { return HAL_ERROR; } @@ -954,20 +958,20 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL __HAL_LOCK(hsdram); state = hsdram->State; - if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { switch (CallbackId) { - case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : - hsdram->DmaXferCpltCallback = pCallback; - break; - case HAL_SDRAM_DMA_XFER_ERR_CB_ID : - hsdram->DmaXferErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = pCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -980,15 +984,15 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL __HAL_UNLOCK(hsdram); return status; } -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup SDRAM_Exported_Functions_Group3 Control functions - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### SDRAM Control functions ##### @@ -1042,7 +1046,7 @@ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) { HAL_SDRAM_StateTypeDef state = hsdram->State; - + /* Check the SDRAM controller state */ if (state == HAL_SDRAM_STATE_BUSY) { @@ -1075,16 +1079,17 @@ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, + uint32_t Timeout) { HAL_SDRAM_StateTypeDef state = hsdram->State; - + /* Check the SDRAM controller state */ if (state == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - else if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED)) + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED)) { /* Update the SDRAM state */ hsdram->State = HAL_SDRAM_STATE_BUSY; @@ -1193,8 +1198,8 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) */ /** @defgroup SDRAM_Exported_Functions_Group4 State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### SDRAM State functions ##### @@ -1226,9 +1231,6 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) * @} */ -/** - @cond 0 - */ /** * @brief MDMA SDRAM process complete callback. * @param hmdma : MDMA handle @@ -1236,7 +1238,7 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) */ static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma) { - SDRAM_HandleTypeDef* hsdram = ( SDRAM_HandleTypeDef* )(hmdma->Parent); + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ __HAL_MDMA_DISABLE(hmdma); @@ -1248,7 +1250,7 @@ static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma) hsdram->DmaXferCpltCallback(hmdma); #else HAL_SDRAM_DMA_XferCpltCallback(hmdma); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } /** @@ -1258,7 +1260,7 @@ static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma) */ static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) { - SDRAM_HandleTypeDef* hsdram = ( SDRAM_HandleTypeDef* )(hmdma->Parent); + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ __HAL_MDMA_DISABLE(hmdma); @@ -1270,7 +1272,7 @@ static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) hsdram->DmaXferCpltCallback(hmdma); #else HAL_SDRAM_DMA_XferCpltCallback(hmdma); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } /** @@ -1280,7 +1282,7 @@ static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) */ static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma) { - SDRAM_HandleTypeDef* hsdram = ( SDRAM_HandleTypeDef* )(hmdma->Parent); + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ __HAL_MDMA_DISABLE(hmdma); @@ -1292,11 +1294,8 @@ static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma) hsdram->DmaXferErrorCallback(hmdma); #else HAL_SDRAM_DMA_XferErrorCallback(hmdma); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } -/** - @endcond - */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.h index e53ade3898..ba189d4398 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sdram.h @@ -77,12 +77,12 @@ typedef struct MDMA_HandleTypeDef *hmdma; /*!< Pointer DMA handler */ #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp Init callback */ - void (* MspDeInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp DeInit callback */ - void (* RefreshErrorCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Refresh Error callback */ - void (* DmaXferCpltCallback) ( MDMA_HandleTypeDef * hmdma); /*!< SDRAM DMA Xfer Complete callback */ - void (* DmaXferErrorCallback) ( MDMA_HandleTypeDef * hmdma); /*!< SDRAM DMA Xfer Error callback */ -#endif + void (* MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp Init callback */ + void (* MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp DeInit callback */ + void (* RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Refresh Error callback */ + void (* DmaXferCpltCallback)(MDMA_HandleTypeDef *hmdma); /*!< SDRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(MDMA_HandleTypeDef *hmdma); /*!< SDRAM DMA Xfer Error callback */ +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } SDRAM_HandleTypeDef; #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) @@ -96,14 +96,14 @@ typedef enum HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */ HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */ HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */ -}HAL_SDRAM_CallbackIDTypeDef; +} HAL_SDRAM_CallbackIDTypeDef; /** * @brief HAL SDRAM Callback pointer definition */ typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram); typedef void (*pSDRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /** * @} */ @@ -127,7 +127,7 @@ typedef void (*pSDRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma); } while(0) #else #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /** * @} */ @@ -161,22 +161,32 @@ void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma); * @{ */ /* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) /* SDRAM callback registering/unregistering */ -HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId); -HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback); -#endif +HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_DmaCallbackTypeDef pCallback); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /** * @} @@ -188,7 +198,8 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL /* SDRAM Control functions *****************************************************/ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram); HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram); -HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, + uint32_t Timeout); HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate); HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber); uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.c index 2440595f45..900480304c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.c @@ -35,7 +35,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission @@ -198,23 +199,24 @@ /** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants * @{ */ -#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ +#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ - USART_CR1_FIFOEN )) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \ + USART_CR1_RE | USART_CR1_OVER8| \ + USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \ - USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ +#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ + USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ -#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \ + USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \ - USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | USART_CR3_SCARCNT | \ + USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ -#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ +#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ -#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ +#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ /** * @} */ @@ -483,7 +485,8 @@ __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback) + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -618,43 +621,45 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma switch (CallbackID) { case HAL_SMARTCARD_TX_COMPLETE_CB_ID : - hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_SMARTCARD_RX_COMPLETE_CB_ID : - hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_SMARTCARD_ERROR_CB_ID : - hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : - hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : - hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback*/ break; case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : - hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID : - hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ break; case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID : - hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ break; case HAL_SMARTCARD_MSPINIT_CB_ID : - hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ + hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_SMARTCARD_MSPDEINIT_CB_ID : - hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ + hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -766,7 +771,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma (##) HAL_SMARTCARD_AbortTransmit_IT() (##) HAL_SMARTCARD_AbortReceive_IT() - (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), + a set of Abort Complete Callbacks are provided: (##) HAL_SMARTCARD_AbortCpltCallback() (##) HAL_SMARTCARD_AbortTransmitCpltCallback() (##) HAL_SMARTCARD_AbortReceiveCpltCallback() @@ -774,13 +780,17 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, + Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. If user wants to abort it, Abort services should be called by user. (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed. + This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt + mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, + and HAL_SMARTCARD_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -828,7 +838,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui the bidirectional line to detect a NACK signal in case of parity error. Therefore, the receiver block must be enabled as well (RE bit must be set). */ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } @@ -855,8 +865,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); ptmpdata++; } - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, - Timeout) != HAL_OK) + if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, + tickstart, Timeout) != HAL_OK) { return HAL_TIMEOUT; } @@ -864,14 +874,14 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, ui /* Disable the Peripheral first to update mode */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { /* In case of TX only mode, if NACK is enabled, receiver block has been enabled for Transmit phase. Disable this receiver block. */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) - || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); @@ -1001,7 +1011,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, the bidirectional line to detect a NACK signal in case of parity error. Therefore, the receiver block must be enabled as well (RE bit must be set). */ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } @@ -1158,7 +1168,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard the bidirectional line to detect a NACK signal in case of parity error. Therefore, the receiver block must be enabled as well (RE bit must be set). */ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } @@ -1311,7 +1321,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, */ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) { - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and + ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); @@ -1373,8 +1384,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1465,7 +1476,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcar HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ @@ -1505,8 +1517,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1533,14 +1545,16 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) { uint32_t abortcplt = 1U; - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and + ERR (Frame error, noise error, overrun error) interrupts */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); - /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ + /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, + DMA Abort complete callbacks should be initialised before any call + to DMA Abort functions */ /* DMA Tx Handle is valid */ if (hsmartcard->hdmatx != NULL) { @@ -1634,8 +1648,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -1767,7 +1781,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmart HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) { /* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); + CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | + USART_CR1_EOBIE)); CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ @@ -1806,8 +1821,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -1832,8 +1847,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartc /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | + SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -2304,14 +2319,18 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard) void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard) { /* Init the SMARTCARD Callback settings */ - hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ - hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ - hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ - hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ - hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ - hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ + hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak + RxFifoFullCallback */ + hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak + TxFifoEmptyCallback */ } #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ @@ -2327,7 +2346,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard uint32_t tmpreg; SMARTCARD_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; - const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; PLL2_ClocksTypeDef pll2_clocks; PLL3_ClocksTypeDef pll3_clocks; uint32_t pclk; @@ -2354,8 +2373,8 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * Configure the Parity and Mode: * set PS bit according to hsmartcard->Init.Parity value * set TE and RE bits according to hsmartcard->Init.Mode value */ - tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode; - tmpreg |= (uint32_t) hsmartcard->Init.WordLength | hsmartcard->FifoMode; + tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) | + ((uint32_t)hsmartcard->Init.WordLength)); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ @@ -2403,35 +2422,44 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard { case SMARTCARD_CLOCKSOURCE_D2PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_D2PCLK2: pclk = HAL_RCC_GetPCLK2Freq(); - tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_PLL2Q: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - tmpreg = (uint16_t)(((pll2_clocks.PLL2_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((pll2_clocks.PLL2_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_PLL3Q: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - tmpreg = (uint16_t)(((pll3_clocks.PLL3_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((pll3_clocks.PLL3_Q_Frequency / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) { - tmpreg = (uint16_t)((((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)((((HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER() >> 3U)) / + SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); } else { - tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); } break; case SMARTCARD_CLOCKSOURCE_CSI: - tmpreg = (uint16_t)(((CSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((CSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; case SMARTCARD_CLOCKSOURCE_LSE: - tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); + tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); break; default: ret = HAL_ERROR; @@ -2592,7 +2620,8 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); @@ -2786,8 +2815,8 @@ static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2835,8 +2864,8 @@ static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ hsmartcard->gState = HAL_SMARTCARD_STATE_READY; @@ -2897,8 +2926,8 @@ static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /* Clear the Error flags in the ICR register */ __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | - SMARTCARD_CLEAR_EOBF); + SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | + SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); /* Restore hsmartcard->RxState to Ready */ hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; @@ -3004,14 +3033,14 @@ static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) /* Disable the Peripheral first to update mode */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { /* In case of TX only mode, if NACK is enabled, receiver block has been enabled for Transmit phase. Disable this receiver block. */ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); } if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) - || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) + || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) { /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.h index fae3bd4ae6..1c7aee87ea 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard.h @@ -52,7 +52,8 @@ typedef struct where usart_ker_ckpres is the USART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */ + This parameter @ref SMARTCARD_Word_Length can only be + set to 9 (8 data + 1 parity bits). */ uint32_t StopBits; /*!< Specifies the number of stop bits. This parameter can be a value of @ref SMARTCARD_Stop_Bits. */ @@ -76,13 +77,14 @@ typedef struct data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref SMARTCARD_Last_Bit */ - uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ + uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote + is selected. Selecting the single sample method increases + the receiver tolerance to clock deviations. This parameter can be a value + of @ref SMARTCARD_OneBit_Sampling. */ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. - This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied - by 2 to give the division factor of the source clock frequency */ + This parameter can be any value from 0x01 to 0x1F. Prescaler value is + multiplied by 2 to give the division factor of the source clock frequency */ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ @@ -111,7 +113,7 @@ typedef struct } SMARTCARD_InitTypeDef; /** - * @brief SMARTCARD advanced features initalization structure definition + * @brief SMARTCARD advanced features initialization structure definition */ typedef struct { @@ -141,14 +143,16 @@ typedef struct uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. This parameter can be a value of @ref SMARTCARD_MSB_First */ - uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when - relevant flag is available) or once guard time period has elapsed. - This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */ + uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when + relevant flag is available) or once guard time period has elapsed. + This parameter can be a value + of @ref SMARTCARDEx_Transmission_Completion_Indication. */ } SMARTCARD_AdvFeatureInitTypeDef; /** * @brief HAL SMARTCARD State definition - * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition). + * @note HAL SMARTCARD State value is a combination of 2 different substates: + * gState and RxState (see @ref SMARTCARD_State_Definition). * - gState contains SMARTCARD state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -159,7 +163,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called) + * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -176,7 +180,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -215,7 +219,8 @@ typedef struct __SMARTCARD_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. - This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */ + This parameter can be a value of + @ref SMARTCARDEx_FIFO_mode. */ void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ @@ -227,12 +232,14 @@ typedef struct __SMARTCARD_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global + Handle management and also related to Tx operations. + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO uint32_t ErrorCode; /*!< SmartCard Error code */ @@ -314,23 +321,26 @@ typedef enum /** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition * @{ */ -#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ -#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value + is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for + use. Value is allowed for gState + and RxState */ #define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing Value is allowed for RxState only */ -#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ +#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception + process is ongoing Not to be used for + neither gState nor RxState. + Value is result of combination (Or) + between gState and RxState values */ #define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error - Value is allowed for gState only */ + Value is allowed for gState only */ /** * @} */ @@ -338,15 +348,15 @@ typedef enum /** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition * @{ */ -#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */ +#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */ #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) -#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** * @} @@ -666,7 +676,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before + * guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -679,9 +690,16 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -691,7 +709,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard + * time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -704,9 +723,16 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -716,7 +742,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -729,8 +756,10 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\ + (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\ + & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\ + ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -740,7 +769,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -753,9 +783,16 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x01U)?\ + (__HANDLE__)->Instance->CR1 : \ + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x02U)?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) &\ + (0x01UL << (((uint16_t)(__INTERRUPT__))\ + & SMARTCARD_IT_MASK))) != 0U)\ + ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -1293,7 +1330,8 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard_ex.c index 704357587d..35505d8b1a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smartcard_ex.c @@ -458,8 +458,8 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE) { @@ -472,8 +472,10 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) tx_fifo_depth = TX_FIFO_DEPTH; rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; - hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; + hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \ + (uint16_t)denominator[tx_fifo_threshold]; + hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \ + (uint16_t)denominator[rx_fifo_threshold]; } } diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.c index 6840ad9d03..3d0c843705 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.c @@ -203,7 +203,8 @@ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions * @{ */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, + uint32_t Timeout); static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); @@ -214,7 +215,8 @@ static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); /** * @} */ @@ -226,8 +228,8 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre */ /** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -579,7 +581,8 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, + pSMBUS_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -858,8 +861,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) */ /** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### IO operation functions ##### @@ -911,7 +914,8 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -950,7 +954,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE); } else { @@ -1010,7 +1015,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) { uint32_t tmp; @@ -1050,7 +1056,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); + SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ); } else { @@ -1165,7 +1172,8 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_ * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -1213,7 +1221,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) { - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, + SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP); } else { @@ -1259,7 +1268,8 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) { /* Check the parameters */ assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -1417,7 +1427,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) { uint32_t tickstart; @@ -1526,8 +1537,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Increment Trials */ SMBUS_Trials++; - } - while (SMBUS_Trials < Trials); + } while (SMBUS_Trials < Trials); hsmbus->State = HAL_SMBUS_STATE_READY; @@ -1549,8 +1559,8 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t */ /** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /** * @brief Handle SMBUS event interrupt request. @@ -1566,7 +1576,12 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1); /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) @@ -1585,7 +1600,12 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Receiver ----------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { /* Slave mode selected */ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) @@ -1604,7 +1624,12 @@ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) } /* SMBUS in mode Listener Only --------------------------------------------------*/ - if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) + if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || + (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && + ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || + (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) { if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) { @@ -1744,8 +1769,8 @@ __weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) */ /** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * + * @brief Peripheral State and Errors functions + * @verbatim =============================================================================== ##### Peripheral State and Errors functions ##### @@ -1771,11 +1796,11 @@ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) } /** -* @brief Return the SMBUS error code. + * @brief Return the SMBUS error code. * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains * the configuration information for the specified SMBUS. -* @retval SMBUS Error Code -*/ + * @retval SMBUS Error Code + */ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) { return hsmbus->ErrorCode; @@ -1790,7 +1815,7 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus) */ /** @addtogroup SMBUS_Private_Functions SMBUS Private Functions - * @brief Data transfers Private functions + * @brief Data transfers Private functions * @{ */ @@ -1854,7 +1879,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t /* Process Unlocked */ __HAL_UNLOCK(hsmbus); - /* REenable the selected SMBUS peripheral */ + /* Re-enable the selected SMBUS peripheral */ __HAL_SMBUS_ENABLE(hsmbus); /* Call the corresponding callback to inform upper layer of End of Transfer */ @@ -1941,7 +1966,8 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t if (hsmbus->XferCount > MAX_NBYTE_SIZE) { - SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, + (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else @@ -2155,7 +2181,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ } - else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) + else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || + (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) { if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) { @@ -2210,7 +2237,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S { if (hsmbus->XferCount > MAX_NBYTE_SIZE) { - SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP); + SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), + SMBUS_NO_STARTSTOP); hsmbus->XferSize = MAX_NBYTE_SIZE; } else @@ -2554,7 +2582,8 @@ static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout) +static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, + uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2603,7 +2632,8 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) +static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) { /* Check the parameters */ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); @@ -2611,12 +2641,16 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); /* update CR2 register */ - MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + MODIFY_REG(hsmbus->Instance->CR2, + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ + (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); } /** - * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions. + * @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions. * @param hsmbus SMBUS handle. * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.h index c82c44b25a..426760dc69 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_smbus.h @@ -65,7 +65,7 @@ typedef struct uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected This parameter can be a value of @ref SMBUS_own_address2_masks. */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. @@ -358,7 +358,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE #define SMBUS_IT_RXI I2C_CR1_RXIE #define SMBUS_IT_TXI I2C_CR1_TXIE -#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) +#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | \ + SMBUS_IT_TXI) #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) @@ -408,10 +409,10 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t */ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) #endif @@ -462,7 +463,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SMBUS flag is set or not. * @param __HANDLE__ specifies the SMBUS Handle. @@ -488,7 +490,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t * @retval The new state of __FLAG__ (SET or RESET). */ #define SMBUS_FLAG_MASK (0x0001FFFFU) -#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) +#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ + (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the SMBUS Handle. @@ -539,15 +542,15 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t */ #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ - ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) + ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ - ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) + ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) + ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ ((MASK) == SMBUS_OA2_MASK01) || \ @@ -565,47 +568,49 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ - ((PEC) == SMBUS_PEC_ENABLE)) + ((PEC) == SMBUS_PEC_ENABLE)) -#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) +#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ + ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) -#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ - ((MODE) == SMBUS_AUTOEND_MODE) || \ - ((MODE) == SMBUS_SOFTEND_MODE) || \ - ((MODE) == SMBUS_SENDPEC_MODE) || \ - ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) +#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ + ((MODE) == SMBUS_AUTOEND_MODE) || \ + ((MODE) == SMBUS_SOFTEND_MODE) || \ + ((MODE) == SMBUS_SENDPEC_MODE) || \ + ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ + ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ - ((REQUEST) == SMBUS_GENERATE_START_READ) || \ - ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ - ((REQUEST) == SMBUS_NO_STARTSTOP)) + ((REQUEST) == SMBUS_GENERATE_START_READ) || \ + ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == SMBUS_NO_STARTSTOP)) -#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ - ((REQUEST) == SMBUS_FIRST_FRAME) || \ - ((REQUEST) == SMBUS_NEXT_FRAME) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) +#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ + ((REQUEST) == SMBUS_FIRST_FRAME) || \ + ((REQUEST) == SMBUS_NEXT_FRAME) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) -#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) -#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ + (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) +#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) @@ -613,7 +618,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) -#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) +#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ + ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) @@ -629,8 +635,8 @@ typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t */ /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ + * @{ + */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); @@ -642,7 +648,8 @@ HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uin /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, + pSMBUS_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); @@ -653,28 +660,33 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ + * @{ + */ /* IO operation functions *****************************************************/ /** @addtogroup Blocking_mode_Polling Blocking mode Polling - * @{ - */ + * @{ + */ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); /** * @} */ /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt - * @{ - */ + * @{ + */ /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); -HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); @@ -685,8 +697,8 @@ HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ + * @{ + */ /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); @@ -703,8 +715,8 @@ void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); */ /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @{ - */ + * @{ + */ /* Peripheral State and Errors functions **************************************************/ uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spdifrx.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spdifrx.c index 1f787273a0..e0536b6459 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spdifrx.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spdifrx.c @@ -93,7 +93,7 @@ The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use HAL_SPDIFRX_RegisterCallback() funtion to register an interrupt callback. + Use HAL_SPDIFRX_RegisterCallback() function to register an interrupt callback. The HAL_SPDIFRX_RegisterCallback() function allows to register the following callbacks: (+) RxHalfCpltCallback : SPDIFRX Data flow half completed callback. diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.c index 90efc7a1ea..95f6c25022 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.c @@ -146,6 +146,7 @@ * @{ */ #define SPI_DEFAULT_TIMEOUT 100UL +#define MAX_FIFO_LENGTH 16UL /** * @} */ @@ -233,7 +234,11 @@ static uint32_t SPI_GetPacketSize(SPI_HandleTypeDef *hspi); */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { +#if (USE_SPI_CRC != 0UL) + uint32_t crc_length; +#else uint32_t crc_length = 0UL; +#endif uint32_t packet_length; /* Check the SPI handle allocation */ @@ -310,6 +315,10 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) return HAL_ERROR; } } + else + { + crc_length = hspi->Init.DataSize << SPI_CFG1_CRCSIZE_Pos; + } #endif /* USE_SPI_CRC */ if (hspi->State == HAL_SPI_STATE_RESET) @@ -350,7 +359,9 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, Communication speed, First bit, CRC calculation state, CRC Length */ - if ((hspi->Init.NSS == SPI_NSS_SOFT) && (hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) + /* SPIx NSS Software Management Configuration */ + if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \ + ((hspi->Init.Mode == SPI_MODE_SLAVE) && (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH)))) { SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI); } @@ -1327,10 +1338,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Call standard close procedure with error check */ SPI_CloseTransfer(hspi); - + /* Process Unlocked */ __HAL_UNLOCK(hspi); - + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); hspi->State = HAL_SPI_STATE_READY; return HAL_ERROR; @@ -1698,7 +1709,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p { HAL_SPI_StateTypeDef tmp_state; HAL_StatusTypeDef errorcode = HAL_OK; - + uint32_t max_fifo_length = 0UL; + uint32_t tmp_TxXferCount; + #if defined (__GNUC__) + __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); + #endif /* __GNUC__ */ uint32_t tmp_mode; /* Check Direction parameter */ @@ -1740,6 +1755,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; + tmp_TxXferCount = hspi->TxXferCount; /* Set the function for IT treatment */ if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) @@ -1764,8 +1780,83 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); - /* Enable EOT, RXP, TXP, DXP, UDR, OVR, FRE, MODF and TSERF interrupts */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF)); + /* Fill in the TxFIFO */ + while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL)) + { + if (max_fifo_length < MAX_FIFO_LENGTH) + { + /* Transmit data in 32 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + /* Transmit data in 16 Bit mode */ + else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount -= (uint16_t)2UL; + tmp_TxXferCount = hspi->TxXferCount; + } + else + { +#if defined (__GNUC__) + *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) + { + *((__IO uint32_t *)&hspi->Instance->TXDR) = *((uint32_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint32_t); + hspi->TxXferCount -= (uint16_t)4UL; + tmp_TxXferCount = hspi->TxXferCount; + } + else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) + { +#if defined (__GNUC__) + *ptxdr_16bits = *((uint16_t *)hspi->pTxBuffPtr); +#else + *((__IO uint16_t *)&hspi->Instance->TXDR) = *((uint16_t *)hspi->pTxBuffPtr); +#endif /* __GNUC__ */ + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= (uint16_t)2UL; + tmp_TxXferCount = hspi->TxXferCount; + } + else + { + *((__IO uint8_t *)&hspi->Instance->TXDR) = *((uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint8_t); + hspi->TxXferCount--; + tmp_TxXferCount = hspi->TxXferCount; + } + } + + max_fifo_length++; + } + else + { + errorcode = HAL_BUSY; + __HAL_UNLOCK(hspi); + return errorcode; + } + } + + /* Enable EOT, DXP, UDR, OVR, FRE, MODF and TSERF interrupts */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_TSERF)); if (hspi->Init.Mode == SPI_MODE_MASTER) { @@ -2890,11 +2981,11 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) { HAL_SPI_TxCpltCallback(hspi); } +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ else { - /* end of the appropriate call */ + /* End of the appropriate call */ } -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ return; } @@ -3464,7 +3555,7 @@ static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi) /* Disable RXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); } -#else +#else /* Disable RXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); #endif /* USE_HSPI_RELOAD_TRANSFER */ @@ -3507,7 +3598,7 @@ static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi) /* Disable RXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); } -#else +#else /* Disable RXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); #endif /* USE_HSPI_RELOAD_TRANSFER */ @@ -3544,7 +3635,7 @@ static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi) /* Disable RXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); } -#else +#else /* Disable RXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); #endif /* USE_HSPI_RELOAD_TRANSFER */ @@ -3581,7 +3672,7 @@ static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi) /* Disable TXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); } -#else +#else /* Disable TXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); #endif /* USE_HSPI_RELOAD_TRANSFER */ @@ -3623,7 +3714,7 @@ static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) /* Disable TXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); } -#else +#else /* Disable TXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); #endif /* USE_HSPI_RELOAD_TRANSFER */ @@ -3659,7 +3750,7 @@ static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi) /* Disable TXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); } -#else +#else /* Disable TXP interrupts */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); #endif /* USE_HSPI_RELOAD_TRANSFER */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.h index c7aa15473a..fb4e2c5e55 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_spi.h @@ -274,7 +274,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to #define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */ #define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */ #define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */ -#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknow error */ +#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */ #define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000800UL) /*!< Invalid Callback error */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.c index 6da1757d89..daf8e3f969 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.c @@ -127,20 +127,14 @@ * @{ */ -/** - @cond 0 - */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void SRAM_DMACplt (MDMA_HandleTypeDef *hmdma); +static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma); static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma); -static void SRAM_DMAError (MDMA_HandleTypeDef *hmdma); -/** - @endcond - */ +static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma); /* Exported functions --------------------------------------------------------*/ @@ -170,7 +164,8 @@ static void SRAM_DMAError (MDMA_HandleTypeDef *hmdma); * @param ExtTiming Pointer to SRAM extended mode timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming) { /* Check the SRAM handle parameter */ if (hsram == NULL) @@ -184,7 +179,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp hsram->Lock = HAL_UNLOCKED; #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - if(hsram->MspInitCallback == NULL) + if (hsram->MspInitCallback == NULL) { hsram->MspInitCallback = HAL_SRAM_MspInit; } @@ -196,7 +191,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp #else /* Initialize the low level hardware (MSP) */ HAL_SRAM_MspInit(hsram); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } /* Initialize SRAM control Interface */ @@ -206,7 +201,8 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); /* Initialize SRAM extended mode timing Interface */ - (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); + (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, + hsram->Init.ExtendedMode); /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); @@ -229,7 +225,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) { #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - if(hsram->MspDeInitCallback == NULL) + if (hsram->MspDeInitCallback == NULL) { hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; } @@ -239,7 +235,7 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) #else /* De-Initialize the low level hardware (MSP) */ HAL_SRAM_MspDeInit(hsram); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /* Configure the SRAM registers with their reset values */ (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); @@ -344,11 +340,12 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma) * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint8_t *psramaddress = (uint8_t *)pAddress; - uint8_t * pdestbuff = pDstBuffer; + uint8_t *pdestbuff = pDstBuffer; HAL_SRAM_StateTypeDef state = hsram->State; /* Check the SRAM controller state */ @@ -391,11 +388,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint8_t *psramaddress = (uint8_t *)pAddress; - uint8_t * psrcbuff = pSrcBuffer; + uint8_t *psrcbuff = pSrcBuffer; /* Check the SRAM controller state */ if (hsram->State == HAL_SRAM_STATE_READY) @@ -437,7 +435,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint32_t *psramaddress = pAddress; @@ -454,11 +453,11 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; - /* Check if the size is a 32-bits mulitple */ + /* Check if the size is a 32-bits multiple */ limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); /* Read data from memory */ - for (size = BufferSize; size != limit; size-=2U) + for (size = BufferSize; size != limit; size -= 2U) { *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); pdestbuff++; @@ -496,11 +495,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize) { uint32_t size; __IO uint32_t *psramaddress = pAddress; - uint16_t * psrcbuff = pSrcBuffer; + uint16_t *psrcbuff = pSrcBuffer; uint8_t limit; /* Check the SRAM controller state */ @@ -512,11 +512,11 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre /* Update the SRAM controller state */ hsram->State = HAL_SRAM_STATE_BUSY; - /* Check if the size is a 32-bits mulitple */ + /* Check if the size is a 32-bits multiple */ limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); /* Write data to memory */ - for (size = BufferSize; size != limit; size-=2U) + for (size = BufferSize; size != limit; size -= 2U) { *psramaddress = (uint32_t)(*psrcbuff); psrcbuff++; @@ -554,11 +554,12 @@ HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { uint32_t size; - __IO uint32_t * psramaddress = pAddress; - uint32_t * pdestbuff = pDstBuffer; + __IO uint32_t *psramaddress = pAddress; + uint32_t *pdestbuff = pDstBuffer; HAL_SRAM_StateTypeDef state = hsram->State; /* Check the SRAM controller state */ @@ -601,11 +602,12 @@ HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { uint32_t size; - __IO uint32_t * psramaddress = pAddress; - uint32_t * psrcbuff = pSrcBuffer; + __IO uint32_t *psramaddress = pAddress; + uint32_t *psrcbuff = pSrcBuffer; /* Check the SRAM controller state */ if (hsram->State == HAL_SRAM_STATE_READY) @@ -647,7 +649,8 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { HAL_StatusTypeDef status; HAL_SRAM_StateTypeDef state = hsram->State; @@ -680,7 +683,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres } else { - return HAL_ERROR; + status = HAL_ERROR; } return status; @@ -695,7 +698,8 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { HAL_StatusTypeDef status; @@ -720,7 +724,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre } else { - return HAL_ERROR; + status = HAL_ERROR; } return status; @@ -738,12 +742,13 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -752,20 +757,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = pCallback; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = pCallback; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -791,7 +796,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID * @retval status */ -HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; @@ -800,42 +805,42 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = HAL_SRAM_MspInit; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; - break; - case HAL_SRAM_DMA_XFER_CPLT_CB_ID : - hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - break; - case HAL_SRAM_DMA_XFER_ERR_CB_ID : - hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(state == HAL_SRAM_STATE_RESET) + else if (state == HAL_SRAM_STATE_RESET) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = HAL_SRAM_MspInit; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -860,12 +865,13 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -874,20 +880,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_DMA_XFER_CPLT_CB_ID : - hsram->DmaXferCpltCallback = pCallback; - break; - case HAL_SRAM_DMA_XFER_ERR_CB_ID : - hsram->DmaXferErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = pCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -900,15 +906,15 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR __HAL_UNLOCK(hsram); return status; } -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} */ /** @defgroup SRAM_Exported_Functions_Group3 Control functions - * @brief Control functions - * + * @brief Control functions + * @verbatim ============================================================================== ##### SRAM Control functions ##### @@ -930,7 +936,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) { /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) + if (hsram->State == HAL_SRAM_STATE_PROTECTED) { /* Process Locked */ __HAL_LOCK(hsram); @@ -964,7 +970,7 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) { /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_READY) + if (hsram->State == HAL_SRAM_STATE_READY) { /* Process Locked */ __HAL_LOCK(hsram); @@ -994,8 +1000,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) */ /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim ============================================================================== ##### SRAM State functions ##### @@ -1027,9 +1033,6 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) * @} */ -/** - @cond 0 - */ /** * @brief MDMA SRAM process complete callback. * @param hmdma : MDMA handle @@ -1037,7 +1040,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) */ static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma) { - SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent); + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ __HAL_MDMA_DISABLE(hmdma); @@ -1049,7 +1052,7 @@ static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma) hsram->DmaXferCpltCallback(hmdma); #else HAL_SRAM_DMA_XferCpltCallback(hmdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } /** @@ -1059,7 +1062,7 @@ static void SRAM_DMACplt(MDMA_HandleTypeDef *hmdma) */ static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) { - SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent); + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ __HAL_MDMA_DISABLE(hmdma); @@ -1071,7 +1074,7 @@ static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) hsram->DmaXferCpltCallback(hmdma); #else HAL_SRAM_DMA_XferCpltCallback(hmdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } /** @@ -1081,7 +1084,7 @@ static void SRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) */ static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma) { - SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hmdma->Parent); + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hmdma->Parent); /* Disable the MDMA channel */ __HAL_MDMA_DISABLE(hmdma); @@ -1093,11 +1096,8 @@ static void SRAM_DMAError(MDMA_HandleTypeDef *hmdma) hsram->DmaXferErrorCallback(hmdma); #else HAL_SRAM_DMA_XferErrorCallback(hmdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } -/** - @endcond - */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.h index d8d44f1af1..6384026daf 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_sram.h @@ -61,7 +61,7 @@ typedef enum typedef struct __SRAM_HandleTypeDef #else typedef struct -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ { FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ @@ -76,11 +76,11 @@ typedef struct MDMA_HandleTypeDef *hmdma; /*!< Pointer DMA handler */ #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */ - void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */ - void (* DmaXferCpltCallback) ( MDMA_HandleTypeDef * hmdma); /*!< SRAM DMA Xfer Complete callback */ - void (* DmaXferErrorCallback) ( MDMA_HandleTypeDef * hmdma); /*!< SRAM DMA Xfer Error callback */ -#endif + void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ + void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ + void (* DmaXferCpltCallback)(MDMA_HandleTypeDef *hmdma); /*!< SRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(MDMA_HandleTypeDef *hmdma); /*!< SRAM DMA Xfer Error callback */ +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } SRAM_HandleTypeDef; #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) @@ -93,14 +93,14 @@ typedef enum HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ -}HAL_SRAM_CallbackIDTypeDef; +} HAL_SRAM_CallbackIDTypeDef; /** * @brief HAL SRAM Callback pointer definition */ typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); typedef void (*pSRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} */ @@ -109,8 +109,8 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma); /* Exported macro ------------------------------------------------------------*/ /** @defgroup SRAM_Exported_Macros SRAM Exported Macros - * @{ - */ + * @{ + */ /** @brief Reset SRAM handle state * @param __HANDLE__ SRAM handle @@ -124,7 +124,7 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma); } while(0) #else #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} @@ -136,11 +136,12 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma); */ /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ + * @{ + */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming); HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); @@ -150,36 +151,46 @@ void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); */ /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions - * @{ - */ + * @{ + */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma); void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma); #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) /* SRAM callback registering/unregistering */ -HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); -HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback); -#endif +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} */ /** @addtogroup SRAM_Exported_Functions_Group3 Control functions - * @{ - */ + * @{ + */ /* SRAM Control functions ****************************************************/ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); @@ -190,8 +201,8 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); */ /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions - * @{ - */ + * @{ + */ /* SRAM State functions ******************************************************/ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_swpmi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_swpmi.c index f90aec773f..839af3ba12 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_swpmi.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_swpmi.c @@ -1745,7 +1745,7 @@ static void SWPMI_DMATransmitCplt(DMA_HandleTypeDef *hdma) in the SWPMI CR register */ CLEAR_BIT(hswpmi->Instance->CR, SWPMI_CR_TXDMA); - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); /* Wait the TXBEF */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.c index 678efc9fe3..5dc8d353d1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.c @@ -416,8 +416,15 @@ HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) htim->State = HAL_TIM_STATE_BUSY; /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -471,8 +478,15 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -490,7 +504,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - + /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); @@ -549,6 +563,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -556,8 +571,15 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -792,8 +814,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -910,8 +939,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1044,6 +1080,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1064,6 +1101,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1084,6 +1122,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1103,6 +1142,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1124,8 +1164,15 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1408,8 +1455,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1525,8 +1579,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1659,6 +1720,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1679,6 +1741,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1698,6 +1761,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Capture/Compare 3 request */ @@ -1717,6 +1781,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1738,8 +1803,15 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -2005,7 +2077,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2018,8 +2090,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -2080,7 +2159,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2126,8 +2205,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -2225,12 +2311,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Set the TIM channel state */ if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { @@ -2261,6 +2347,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -2280,6 +2367,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -2299,6 +2387,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -2318,6 +2407,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -2333,8 +2423,15 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -2593,11 +2690,12 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2612,9 +2710,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2629,7 +2727,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2649,11 +2747,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2665,7 +2764,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2691,11 +2790,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2710,9 +2810,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2727,7 +2827,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2753,11 +2853,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2775,7 +2876,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -3047,7 +3148,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3060,7 +3161,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3073,9 +3174,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3165,7 +3266,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - else + else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -3201,7 +3302,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3214,7 +3315,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3227,9 +3328,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3327,7 +3428,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - else + else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -3367,12 +3468,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch if (Channel == TIM_CHANNEL_1) { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData1 == NULL) && (Length > 0U)) { @@ -3392,12 +3493,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData2 == NULL) && (Length > 0U)) { @@ -3417,16 +3518,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) { @@ -3460,6 +3561,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3484,6 +3586,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3509,6 +3612,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -3522,6 +3626,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the Peripheral */ @@ -3600,7 +3705,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - else + else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -4441,8 +4546,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4458,8 +4564,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4475,8 +4582,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4492,8 +4600,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4509,8 +4618,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4526,8 +4636,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4543,8 +4654,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4570,7 +4682,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { - HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4579,54 +4690,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B { case TIM_DMA_UPDATE: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -4770,8 +4878,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4787,8 +4896,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4804,8 +4914,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4821,8 +4932,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4838,8 +4950,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4855,8 +4968,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4872,8 +4986,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4900,7 +5015,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { - HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4909,54 +5023,51 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu { case TIM_DMA_UPDATE: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); break; } case TIM_DMA_CC1: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); break; } case TIM_DMA_CC2: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); break; } case TIM_DMA_CC3: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); break; } case TIM_DMA_CC4: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); break; } case TIM_DMA_COM: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); break; } case TIM_DMA_TRIGGER: { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); break; } default: break; } - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); /* Change the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; /* Return function status */ - return status; + return HAL_OK; } /** @@ -5298,13 +5409,13 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_ITR6: case TIM_CLOCKSOURCE_ITR7: case TIM_CLOCKSOURCE_ITR8: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } default: break; @@ -6270,12 +6381,12 @@ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; - + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - + return channel_state; } @@ -6288,7 +6399,7 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - + return htim->DMABurstState; } @@ -6352,14 +6463,14 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) * @param hdma pointer to DMA handle. * @retval None */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); @@ -6368,7 +6479,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -6377,7 +6488,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); @@ -6386,7 +6497,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); @@ -6457,7 +6568,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); @@ -6467,7 +6578,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -6477,7 +6588,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); @@ -6487,7 +6598,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); @@ -6672,7 +6783,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) /** * @brief Timer Output Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6747,7 +6858,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6823,7 +6934,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6897,7 +7008,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -6957,7 +7068,7 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) /** * @brief Timer Output Compare 5 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, @@ -7010,7 +7121,7 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, /** * @brief Timer Output Compare 6 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config The ouput configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, @@ -7114,7 +7225,7 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) { return HAL_ERROR; } @@ -7176,11 +7287,11 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, case TIM_TS_ITR11: case TIM_TS_ITR12: case TIM_TS_ITR13: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - break; - } + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } default: break; diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.h index aee9f743ca..2e93e31a61 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim.h @@ -396,35 +396,35 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ - ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ - ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ - ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ - ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ - ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ - ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ - ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ - ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ - ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ - ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ - ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ } HAL_TIM_CallbackIDTypeDef; /** @@ -907,7 +907,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ /** * @} @@ -1066,24 +1066,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ @@ -2062,7 +2062,7 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ (__HANDLE__)->ChannelState[5]) - + #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ @@ -2085,7 +2085,7 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ (__HANDLE__)->ChannelNState[3]) - + #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim_ex.c index d1cb18c33e..d929a23e32 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_tim_ex.c @@ -322,9 +322,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -334,14 +334,21 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - + /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -395,9 +402,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -416,8 +423,15 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -474,12 +488,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Set the TIM channel state */ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - ||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { @@ -509,14 +523,22 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Enable the DMA stream for Capture 1*/ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the capture compare 1 Interrupt */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -603,7 +625,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { return HAL_ERROR; } - + /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); @@ -614,8 +636,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -721,8 +750,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -853,6 +889,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -872,6 +909,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -891,6 +929,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -909,8 +948,15 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1048,8 +1094,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1153,8 +1206,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1286,6 +1346,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -1305,6 +1366,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1324,6 +1386,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1342,8 +1405,15 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha __HAL_TIM_MOE_ENABLE(htim); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } @@ -1439,8 +1509,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1449,22 +1521,28 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); - HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); @@ -1480,8 +1558,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1505,8 +1585,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1515,8 +1597,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1525,22 +1609,28 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); - HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -1562,8 +1652,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1593,8 +1685,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -2042,10 +2136,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, /* Set the break input polarity */ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } /* Set TIMx_AF1 */ htim->Instance->AF1 = tmporx; @@ -2062,10 +2156,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, /* Set the break input polarity */ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } /* Set TIMx_AF2 */ htim->Instance->AF2 = tmporx; @@ -2426,12 +2520,12 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; - + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); - + return channel_state; } /** @@ -2498,7 +2592,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); @@ -2507,7 +2601,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -2516,7 +2610,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); @@ -2525,7 +2619,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); @@ -2550,7 +2644,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) * @param hdma pointer to DMA handle. * @retval None */ -void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -2573,13 +2667,13 @@ void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) { /* nothing to do */ } - + #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.c index 0810120f1e..218b9b598e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.c @@ -39,7 +39,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. @@ -113,6 +114,10 @@ (+) MspInitCallback : UART MspInit. (+) MspDeInitCallback : UART MspDeInit. + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback(). + [..] By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: @@ -172,27 +177,23 @@ /** @defgroup UART_Private_Constants UART Private Constants * @{ */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8| \ - USART_CR1_FIFOEN )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT| \ - USART_CR3_TXFTCFG | USART_CR3_RXFTCFG )) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ + USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ #define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ #define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ #define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ #define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ - /** * @} */ /* Private macros ------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; - /* Private function prototypes -----------------------------------------------*/ /** @addtogroup UART_Private_Functions * @{ @@ -222,6 +223,15 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); * @} */ +/* Exported Constants --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Constants + * @{ + */ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @defgroup UART_Exported_Functions UART Exported Functions @@ -645,6 +655,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; __HAL_UNLOCK(huart); @@ -844,55 +855,57 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR switch (CallbackID) { case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ break; case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_UART_WAKEUP_CB_ID : - huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ break; case HAL_UART_RX_FIFO_FULL_CB_ID : - huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ break; case HAL_UART_TX_FIFO_EMPTY_CB_ID : - huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ break; case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -932,6 +945,74 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR return status; } + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(huart); + + if (huart->gState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(huart); + return status; +} + #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** @@ -997,16 +1078,23 @@ HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UAR (+) HAL_UART_AbortTransmitCpltCallback() (+) HAL_UART_AbortReceiveCpltCallback() + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: + (+) HAL_UARTEx_RxEventCallback() + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. If user wants to abort it, Abort services should be called by user. (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -1049,7 +1137,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); huart->TxXferSize = Size; @@ -1138,8 +1226,9 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); huart->RxXferSize = Size; @@ -1290,58 +1379,20 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, __HAL_LOCK(huart); - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = Size; - huart->RxISR = NULL; + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Configure Rx interrupt processing*/ - if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + if (!(IS_LPUART_INSTANCE(huart->Instance))) { - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) { - huart->RxISR = UART_RxISR_16BIT_FIFOEN; + /* Enable the UART Receiver Timeout Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } - else - { - huart->RxISR = UART_RxISR_8BIT_FIFOEN; - } - - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - } - else - { - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->RxISR = UART_RxISR_16BIT; - } - else - { - huart->RxISR = UART_RxISR_8BIT; - } - - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); } - return HAL_OK; + return (UART_Start_Receive_IT(huart, pData, Size)); } else { @@ -1447,53 +1498,20 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData __HAL_LOCK(huart); - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - if (huart->hdmarx != NULL) + if (!(IS_LPUART_INSTANCE(huart->Instance))) { - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - __HAL_UNLOCK(huart); - - /* Restore huart->gState to ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_ERROR; + /* Enable the UART Receiver Timeout Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); } } - __HAL_UNLOCK(huart); - /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; + return (UART_Start_Receive_DMA(huart, pData, Size)); } else { @@ -1554,7 +1572,7 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) /* Clear the Overrun flag before resuming the Rx transfer */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); SET_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -1650,9 +1668,16 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | + USART_CR1_TCIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { @@ -1722,6 +1747,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -1804,6 +1830,12 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { @@ -1840,6 +1872,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; return HAL_OK; } @@ -1863,9 +1896,16 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) uint32_t abortcplt = 1U; /* Disable interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE)); + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised before any call to DMA Abort functions */ /* DMA Tx Handle is valid */ @@ -1974,6 +2014,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* As no DMA to be aborted, call directly user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -2098,6 +2139,12 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { @@ -2133,6 +2180,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* As no DMA to be aborted, call directly user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -2157,6 +2205,7 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* As no DMA to be aborted, call directly user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -2339,6 +2388,93 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* End if some error occurs */ + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + } + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + } + } + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) { @@ -2523,6 +2659,24 @@ __weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) */ } +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + /** * @} */ @@ -2845,6 +2999,7 @@ void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ } #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -2893,7 +3048,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - tmpreg |= (uint32_t)huart->FifoMode; MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ @@ -2978,7 +3132,7 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { /* Check computed UsartDiv value is in allocated range (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ - usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, (uint64_t)huart->Init.BaudRate, huart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) { huart->Instance->BRR = usartdiv; @@ -2987,7 +3141,8 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { ret = HAL_ERROR; } - } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ } /* if (pclk != 0) */ } /* Check UART Over Sampling to set Baud Rate Register */ @@ -3199,7 +3354,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ @@ -3227,6 +3382,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; __HAL_UNLOCK(huart); @@ -3253,7 +3409,8 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3272,7 +3429,8 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE)); CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3291,6 +3449,134 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ return HAL_OK; } +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + } + + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + __HAL_UNLOCK(huart); + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + __HAL_UNLOCK(huart); + + /* Enable the UART Parity Error Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + /** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). @@ -3319,8 +3605,15 @@ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Reset RxIsr function pointer */ huart->RxISR = NULL; @@ -3403,15 +3696,37 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } } + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } /** @@ -3423,13 +3738,29 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Half complete callback*/ - huart->RxHalfCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else - /*Call legacy weak Rx Half complete callback*/ - HAL_UART_RxHalfCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } } /** @@ -3534,6 +3865,7 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Call user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -3585,6 +3917,7 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) /* Restore huart->gState and huart->RxState to Ready */ huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Call user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -3652,6 +3985,7 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) /* Restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; /* Call user Abort complete callback */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) @@ -3664,7 +3998,7 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) } /** - * @brief TX interrrupt handler for 7 or 8 bits data word length . + * @brief TX interrupt handler for 7 or 8 bits data word length . * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3693,7 +4027,7 @@ static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) } /** - * @brief TX interrrupt handler for 9 bits data word length. + * @brief TX interrupt handler for 9 bits data word length. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3725,7 +4059,7 @@ static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) } /** - * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3765,7 +4099,7 @@ static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) } /** - * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled. + * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT(). * @param huart UART handle. @@ -3833,7 +4167,7 @@ static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 7 or 8 bits data word length . + * @brief RX interrupt handler for 7 or 8 bits data word length . * @param huart UART handle. * @retval None */ @@ -3864,13 +4198,33 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } else @@ -3881,7 +4235,7 @@ static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 9 bits data word length . + * @brief RX interrupt handler for 9 bits data word length . * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. @@ -3916,13 +4270,33 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } else @@ -3933,7 +4307,7 @@ static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. @@ -3943,25 +4317,74 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) { uint16_t uhMask = huart->Mask; uint16_t uhdata; - uint16_t nb_rx_data; + uint16_t nb_rx_data; uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) { - for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); huart->pRxBuffPtr++; huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ @@ -3970,13 +4393,33 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } @@ -4005,7 +4448,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) } /** - * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled. + * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled. * @note Function is called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() * @param huart UART handle. @@ -4016,26 +4459,75 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) uint16_t *tmp; uint16_t uhMask = huart->Mask; uint16_t uhdata; - uint16_t nb_rx_data; + uint16_t nb_rx_data; uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); /* Check that a Rx process is ongoing */ if (huart->RxState == HAL_UART_STATE_BUSY_RX) { - for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--) + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) { uhdata = (uint16_t) READ_REG(huart->Instance->RDR); tmp = (uint16_t *) huart->pRxBuffPtr ; *tmp = (uint16_t)(uhdata & uhMask); huart->pRxBuffPtr += 2U; huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } if (huart->RxXferCount == 0U) { /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Rx process is completed, restore huart->RxState to Ready */ @@ -4044,13 +4536,33 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) /* Clear RxISR function pointer */ huart->RxISR = NULL; + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Disable IDLE interrupt */ + CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; } } diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.h index a7075833bf..103cb1b33f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart.h @@ -46,51 +46,54 @@ extern "C" { */ typedef struct { - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate register is computed using the following formula: - LPUART: - ======= - Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1 - where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + LPUART: + ======= + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler + UART: + ===== + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length. */ + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits. */ + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode. */ + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. */ + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ - uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ - uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. - This parameter can be a value of @ref UART_ClockPrescaler. */ + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ } UART_InitTypeDef; @@ -101,7 +104,8 @@ typedef struct { uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several Advanced Features may be initialized at the same time . - This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */ + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. This parameter can be a value of @ref UART_Tx_Inv. */ @@ -135,7 +139,8 @@ typedef struct /** * @brief HAL UART State definition - * @note HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition). + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). * - gState contains UART state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -146,7 +151,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -163,7 +168,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -190,6 +195,17 @@ typedef enum UART_CLOCKSOURCE_UNDEFINED = 0x80U /*!< Undefined clock source */ } UART_ClockSourceTypeDef; +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * It is expected to admit following values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + /** * @brief UART handle Structure definition */ @@ -222,6 +238,8 @@ typedef struct __UART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ @@ -233,11 +251,11 @@ typedef struct __UART_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ __IO uint32_t ErrorCode; /*!< UART Error code */ @@ -253,6 +271,7 @@ typedef struct __UART_HandleTypeDef void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ @@ -286,7 +305,9 @@ typedef enum /** * @brief HAL UART Callback pointer definition */ -typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -313,8 +334,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer #define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing Value is allowed for RxState only */ #define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ #define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state Value is allowed for gState only */ #define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error @@ -326,16 +347,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_Error_Definition UART Error Definition * @{ */ -#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ -#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -432,10 +453,14 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode * @{ */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection on 0x7F frame detection */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection on 0x55 frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ /** * @} */ @@ -597,8 +622,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_MSB_First UART Advanced Feature MSB First * @{ */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ -#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ /** * @} */ @@ -624,7 +651,7 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register * @{ */ -#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ /** * @} */ @@ -632,9 +659,10 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection * @{ */ -#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ -#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ -#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ /** * @} */ @@ -651,7 +679,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB position in CR1 register */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ /** * @} */ @@ -659,7 +688,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register * @{ */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB position in CR1 register */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ /** * @} */ @@ -734,28 +764,28 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * - ZZZZ : Flag position in the ISR register(4bits) * @{ */ -#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ -#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ -#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ -#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ -#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ -#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ -#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ -#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ -#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ -#define UART_IT_CM 0x112EU /*!< UART character match interruption */ -#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ -#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ -#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ -#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ -#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ -#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ +#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ +#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ +#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ -#define UART_IT_ERR 0x0060U /*!< UART error interruption */ +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ -#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ -#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ -#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ /** * @} */ @@ -779,6 +809,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @} */ +/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ /** * @} @@ -930,10 +970,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK)))) - +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Disable the specified UART interrupt. * @param __HANDLE__ specifies the UART Handle. @@ -958,9 +1003,15 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval None */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK)))) +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) /** @brief Check whether the specified UART interrupt has occurred or not. * @param __HANDLE__ specifies the UART Handle. @@ -1011,9 +1062,13 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK))) != RESET) ? SET : RESET) +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) /** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the UART Handle. @@ -1080,8 +1135,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1098,8 +1154,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1116,8 +1173,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1134,8 +1192,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). * @param __HANDLE__ specifies the UART Handle. * @retval None */ @@ -1170,15 +1229,16 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) - /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. * @param __BAUD__ Baud rate set by the user. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)\ - + (uint32_t)((__BAUD__)/2U)) / (__BAUD__))) +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \ + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \ + ) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1186,8 +1246,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U)\ - + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode. * @param __PCLK__ UART clock. @@ -1195,8 +1255,8 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __CLOCKPRESCALER__ UART prescaler value. * @retval Division result */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])\ - + ((__BAUD__)/2U)) / (__BAUD__)) +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Check whether or not UART instance is Low Power UART. * @param __HANDLE__ specifies the UART Handle. @@ -1437,8 +1497,9 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer * @param __AUTOBAUDRATE__ UART auto Baud rate state. * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ - ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) /** * @brief Ensure that UART DMA enabling or disabling on error setting is valid. @@ -1514,12 +1575,6 @@ typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer /* Include UART HAL Extended module */ #include "stm32h7xx_hal_uart_ex.h" - -/* Prescaler Table used in BRR computation macros. - Declared as extern here to allow use of private UART macros, outside of HAL UART fonctions */ -extern const uint16_t UARTPrescTable[12]; - - /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ @@ -1543,6 +1598,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** @@ -1581,6 +1639,8 @@ void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + /** * @} */ @@ -1626,13 +1686,28 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); * @{ */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + +/** + * @} + */ + +/* Private variables -----------------------------------------------------------*/ +/** @defgroup UART_Private_variables UART Private variables + * @{ + */ +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; + /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.c index 3a899a1e76..bd57fecb6a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.c @@ -332,6 +332,41 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (+) Detection of inactivity period (RX line has not been active for a given period). + (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (+) Detection that a specific character has been received. + + (#) There are two mode of transfer: + (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (+) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (+) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (+) HAL_UARTEx_ReceiveToIdle_DMA() + @endverbatim * @{ */ @@ -416,7 +451,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Wait until REACK flag is set */ @@ -652,6 +687,259 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3 return HAL_OK; } +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + __HAL_UNLOCK(huart); + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + status = UART_Start_Receive_IT(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + __HAL_LOCK(huart); + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + /** * @} */ @@ -694,8 +982,8 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) { @@ -708,8 +996,10 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) tx_fifo_depth = TX_FIFO_DEPTH; rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; - huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; } } /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.h index a875a0092f..eb437f3b00 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_uart_ex.h @@ -99,12 +99,12 @@ typedef struct * @brief UART TXFIFO threshold level * @{ */ -#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ -#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ /** * @} */ @@ -113,12 +113,12 @@ typedef struct * @brief UART RXFIFO threshold level * @{ */ -#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ -#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ /** * @} */ @@ -174,6 +174,12 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.c index caf70aa771..f27e32f517 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.c @@ -39,7 +39,8 @@ (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. (+++) Configure the DMA Tx/Rx channel. (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode (Receiver/Transmitter) in the husart handle Init structure. @@ -532,9 +533,9 @@ HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_US } /** - * @brief Unregister an UART Callback - * UART callaback is redirected to the weak predefined callback - * @param husart uart handle + * @brief Unregister an USART Callback + * USART callaback is redirected to the weak predefined callback + * @param husart usart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID @@ -562,47 +563,47 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ switch (CallbackID) { case HAL_USART_TX_HALFCOMPLETE_CB_ID : - husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_USART_TX_COMPLETE_CB_ID : - husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_USART_RX_HALFCOMPLETE_CB_ID : - husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_USART_RX_COMPLETE_CB_ID : - husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_USART_TX_RX_COMPLETE_CB_ID : - husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ break; case HAL_USART_ERROR_CB_ID : - husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_USART_ABORT_COMPLETE_CB_ID : - husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_USART_RX_FIFO_FULL_CB_ID : - husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ break; case HAL_USART_TX_FIFO_EMPTY_CB_ID : - husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ break; case HAL_USART_MSPINIT_CB_ID : - husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ + husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_USART_MSPDEINIT_CB_ID : - husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ + husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -721,13 +722,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side. + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify + error type, and HAL_USART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on USART side. If user wants to abort it, Abort services should be called by user. (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed. + Error code is set to allow user to identify error type, + and HAL_USART_ErrorCallback() user callback is executed. @endverbatim * @{ @@ -735,7 +739,7 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ /** * @brief Simplex send an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart USART handle. @@ -763,7 +767,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); husart->TxXferSize = Size; @@ -832,7 +836,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa /** * @brief Receive an amount of data in blocking mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart USART handle. @@ -861,7 +865,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); husart->RxXferSize = Size; @@ -943,7 +947,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat /** * @brief Full-Duplex Send and Receive an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart USART handle. @@ -977,7 +981,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); husart->RxXferSize = Size; @@ -1092,7 +1096,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t /** * @brief Send an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart USART handle. @@ -1175,7 +1179,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT /** * @brief Receive an amount of data in interrupt mode. * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart USART handle. @@ -1278,7 +1282,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /** * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart USART handle. @@ -1377,7 +1381,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /** * @brief Send an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data is handled as a set of u16. In this case, Size must indicate the number * of u16 provided through pTxData. * @param husart USART handle. @@ -1462,7 +1466,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p * @note When the USART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the received data is handled as a set of u16. In this case, Size must indicate the number * of u16 available through pRxData. * @param husart USART handle. @@ -1578,7 +1582,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /** * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number * of u16 available through pTxData and through pRxData. * @param husart USART handle. @@ -1769,7 +1773,7 @@ HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) /* Clear the Overrun flag before resuming the Rx transfer*/ __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -2092,7 +2096,8 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) uint32_t errorcode; /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | USART_ISR_UDR)); + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | + USART_ISR_UDR)); if (errorflags == 0U) { /* USART in mode Receiver ---------------------------------------------------*/ @@ -2906,11 +2911,13 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) break; case USART_CLOCKSOURCE_PLL2: HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll2_clocks.PLL2_Q_Frequency, husart->Init.BaudRate, + husart->Init.ClockPrescaler)); break; case USART_CLOCKSOURCE_PLL3: HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, husart->Init.BaudRate, husart->Init.ClockPrescaler)); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pll3_clocks.PLL3_Q_Frequency, husart->Init.BaudRate, + husart->Init.ClockPrescaler)); break; case USART_CLOCKSOURCE_HSI: if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) @@ -2968,7 +2975,7 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) /* Initialize the USART ErrorCode */ husart->ErrorCode = HAL_USART_ERROR_NONE; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); /* Check if the Transmitter is enabled */ @@ -3437,7 +3444,8 @@ static void USART_RxISR_8BIT_FIFOEN(USART_HandleTypeDef *husart) /* Disable the USART Parity Error Interrupt */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Clear RxISR function pointer */ @@ -3571,7 +3579,8 @@ static void USART_RxISR_16BIT_FIFOEN(USART_HandleTypeDef *husart) /* Disable the USART Parity Error Interrupt */ CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); /* Clear RxISR function pointer */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.h index 15b610e812..6092ebe312 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart.h @@ -48,11 +48,15 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. The baud rate is computed using the following formula: - Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[15:4] = ((2 * fclk_pres) / + ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 - where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler. - @note Oversampling by 8 is systematically applied to achieve high baud rates. */ + Baud Rate Register[2:0] = (((2 * fclk_pres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where fclk_pres is the USART input clock frequency (fclk) + divided by a prescaler. + @note Oversampling by 8 is systematically applied to + achieve high baud rates. */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USARTEx_Word_Length. */ @@ -218,17 +222,17 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin /** @defgroup USART_Error_Definition USART Error Definition * @{ */ -#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ -#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U) /*!< SPI slave underrun error */ +#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ -#define HAL_USART_ERROR_RTO ((uint32_t)0x00000080U) /*!< Receiver Timeout error */ +#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */ /** * @} */ @@ -264,15 +268,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @} */ -/** @defgroup USART_Over_Sampling USART Over Sampling - * @{ - */ -#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - /** @defgroup USART_Clock USART Clock * @{ */ @@ -552,9 +547,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -574,10 +572,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) - +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. @@ -600,7 +600,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) + & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ + USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__ specifies the USART Handle. @@ -622,10 +623,13 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) - +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + USART_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the USART Handle. @@ -709,11 +713,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. * @param __BAUD__ Baud rate set by the user. - * @param __CLOCKPRESCALER__ UART prescaler value. + * @param __CLOCKPRESCALER__ USART prescaler value. * @retval Division result */ -#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ - + ((__BAUD__)/2U)) / (__BAUD__)) +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\ + (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Report the USART clock source. * @param __HANDLE__ specifies the USART Handle. @@ -1014,14 +1019,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) -/** - * @brief Ensure that USART oversampling is valid. - * @param __SAMPLING__ USART oversampling. - * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ -#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == USART_OVERSAMPLING_8)) - /** * @brief Ensure that USART clock state is valid. * @param __CLOCK__ USART clock state. diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.c index ac5badea9d..2bdc87e21d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.c @@ -503,8 +503,8 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (husart->FifoMode == USART_FIFOMODE_DISABLE) { @@ -515,10 +515,14 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) { rx_fifo_depth = RX_FIFO_DEPTH; tx_fifo_depth = TX_FIFO_DEPTH; - rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU); - tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU); - husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; - husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; + rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU); + tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, + USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU); + husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; } } /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.h index b6987263df..769132696f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_usart_ex.h @@ -45,9 +45,9 @@ extern "C" { /** @defgroup USARTEx_Word_Length USARTEx Word Length * @{ */ -#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ #define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ +#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.c index 94db743d10..43b55b2035 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.c @@ -21,6 +21,13 @@ before the counter has reached the refresh window value. This implies that the counter must be refreshed in a limited window. (+) Once enabled the WWDG cannot be disabled except by a system reset. + (+) If required by application, an Early Wakeup Interrupt can be triggered + in order to be warned before WWDG expiration. The Early Wakeup Interrupt + (EWI) can be used if specific safety operations or data logging must + be performed before the actual reset is generated. When the downcounter + reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt + line to be enabled in NVIC. Once enabled, EWI interrupt cannot be + disabled except by a system reset. (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG reset occurs. (+) The WWDG counter input clock is derived from the APB clock divided @@ -47,7 +54,6 @@ (++) Counter max (T[5;0] = 0x3F) @125MHz (PCLK1) with prescaler dividing by 128: max timeout before reset: approximately 268.43ms - ============================================================================== ##### How to use this driver ##### ============================================================================== @@ -56,16 +62,16 @@ [..] (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). - (+) Set the WWDG prescaler, refresh window and counter value - using HAL_WWDG_Init() function. - (+) Start the WWDG using HAL_WWDG_Start() function. - When the WWDG is enabled the counter value should be configured to - a value greater than 0x40 to prevent generating an immediate reset. - (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is - generated when the counter reaches 0x40, and then start the WWDG using - HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can - add his own code by customization of callback HAL_WWDG_WakeupCallback. - Once enabled, EWI interrupt cannot be disabled except by a system reset. + (+) Configure the WWDG prescaler, refresh window value, counter value and early + interrupt status using HAL_WWDG_Init() function. This will automatically + enable WWDG and start its downcounter. Time reference can be taken from + function exit. Care must be taken to provide a counter value + greater than 0x40 to prevent generation of immediate reset. + (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is + generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is + triggered by the interrupt service routine, flag will be automatically + cleared and HAL_WWDG_WakeupCallback user callback will be executed. User + can add his own code by customization of callback HAL_WWDG_WakeupCallback. (+) Then the application program must refresh the WWDG counter at regular intervals during normal operation to prevent an MCU reset, using HAL_WWDG_Refresh() function. This operation must occur only when @@ -75,28 +81,28 @@ ============================= [..] - The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows + The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. Use Functions - @ref HAL_WWDG_RegisterCallback() to register a user callback. + HAL_WWDG_RegisterCallback() to register a user callback. - (+) Function @ref HAL_WWDG_RegisterCallback() allows to register following + (+) Function HAL_WWDG_RegisterCallback() allows to register following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. (++) MspInitCallback : WWDG MspInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - (+) Use function @ref HAL_WWDG_UnRegisterCallback() to reset a callback to - the default weak (surcharged) function. @ref HAL_WWDG_UnRegisterCallback() + (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to + the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. This function allows to reset following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. (++) MspInitCallback : WWDG MspInit. [..] - When calling @ref HAL_WWDG_Init function, callbacks are reset to the + When calling HAL_WWDG_Init function, callbacks are reset to the corresponding legacy weak (surcharged) functions: - @ref HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have + HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have not been registered before. [..] @@ -107,7 +113,7 @@ *** WWDG HAL driver macros list *** =================================== [..] - Below the list of most used macros in WWDG HAL driver. + Below the list of available macros in WWDG HAL driver. (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags @@ -208,7 +214,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) #else /* Init the low level hardware */ HAL_WWDG_MspInit(hwwdg); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /* Set WWDG Counter */ WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); @@ -253,7 +259,8 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -314,7 +321,7 @@ HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWD return status; } -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} @@ -382,7 +389,7 @@ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) #else /* Early Wakeup callback */ HAL_WWDG_EarlyWakeupCallback(hwwdg); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ } } } diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.h index c124855734..061a62fc4e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_wwdg.h @@ -56,7 +56,7 @@ typedef struct uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ - uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not. + uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not. This parameter can be a value of @ref WWDG_EWI_Mode */ } WWDG_InitTypeDef; @@ -68,17 +68,17 @@ typedef struct typedef struct __WWDG_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ { WWDG_TypeDef *Instance; /*!< Register base address */ WWDG_InitTypeDef Init; /*!< WWDG required parameters */ #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) - void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ + void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ - void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ -#endif + void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ } WWDG_HandleTypeDef; #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) @@ -87,8 +87,8 @@ typedef struct */ typedef enum { - HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */ - HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */ + HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */ + HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */ } HAL_WWDG_CallbackIDTypeDef; /** @@ -96,7 +96,7 @@ typedef enum */ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */ -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} */ @@ -268,9 +268,10 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, + pWWDG_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID); -#endif +#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.c index df018877fe..1ce67c4330 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.c @@ -317,7 +317,7 @@ * the same ADC common instance to their default reset values. * @note This function is performing a hard reset, using high level * clock source RCC ADC reset. - * Caution: On this STM32 serie, if several ADC instances are available + * Caution: On this STM32 series, if several ADC instances are available * on the selected device, RCC ADC reset will reset * all ADC instances belonging to the common ADC instance. * To de-initialize only 1 ADC instance, use @@ -387,7 +387,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* Note: Hardware constraint (refer to description of functions */ /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ - /* On this STM32 serie, setting of these features is conditioned to */ + /* On this STM32 series, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) @@ -468,7 +468,7 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) * is in an unknown state. * In this case, perform a hard reset using high level * clock source RCC ADC reset. - * Caution: On this STM32 serie, if several ADC instances are available + * Caution: On this STM32 series, if several ADC instances are available * on the selected device, RCC ADC reset will reset * all ADC instances belonging to the common ADC instance. * Refer to function @ref LL_ADC_CommonDeInit(). @@ -758,10 +758,10 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) /* ADC instance is in an unknown state */ /* Need to performing a hard reset of ADC instance, using high level */ /* clock source RCC ADC reset. */ - /* Caution: On this STM32 serie, if several ADC instances are available */ + /* Caution: On this STM32 series, if several ADC instances are available */ /* on the selected device, RCC ADC reset will reset */ /* all ADC instances belonging to the common ADC instance. */ - /* Caution: On this STM32 serie, if several ADC instances are available */ + /* Caution: On this STM32 series, if several ADC instances are available */ /* on the selected device, RCC ADC reset will reset */ /* all ADC instances belonging to the common ADC instance. */ status = ERROR; @@ -918,7 +918,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* - Set ADC group regular conversion data transfer: no transfer or */ /* transfer by DMA, and DMA requests mode */ /* - Set ADC group regular overrun behavior */ - /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { @@ -978,7 +978,7 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) { /* Set ADC_REG_InitStruct fields to default values */ /* Set fields of ADC group regular */ - /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; @@ -1045,7 +1045,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* - Set ADC group injected sequencer discontinuous mode */ /* - Set ADC group injected conversion trigger: independent or */ /* from ADC group regular */ - /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */ + /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */ /* setting of trigger source to SW start. */ if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.h index f7e8c9c1de..f12b52a703 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_adc.h @@ -371,7 +371,7 @@ extern "C" { /* Internal voltage reference VrefInt */ #if defined(ADC_VER_V5_3) #define VREFINT_CAL_ADDR ((uint16_t*) (0x8fff810UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ - /* Adress related to STM32H7A3 */ + /* Address related to STM32H7A3 */ #else /* ADC_VER_V5_90 || ADC_VER_V5_X */ #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ #endif /* ADC_VER_V5_3 */ @@ -380,7 +380,7 @@ extern "C" { #if defined(ADC_VER_V5_3) #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x8fff814UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x8fff818UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ - /* Adresses related to STM32H7A3 */ + /* Addresses related to STM32H7A3 */ #else /* ADC_VER_V5_90 || ADC_VER_V5_X */ #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ @@ -444,7 +444,7 @@ typedef struct { uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE - @note On this STM32 serie, if ADC group injected is used, some + @note On this STM32 series, if ADC group injected is used, some clock ratio constraints between ADC clock and AHB clock must be respected. Refer to reference manual. @@ -527,7 +527,7 @@ typedef struct { uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE - @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge + @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). @@ -587,7 +587,7 @@ typedef struct { uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line). This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE - @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge + @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge(). @@ -725,7 +725,7 @@ typedef struct /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */ #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */ @@ -785,7 +785,7 @@ typedef struct #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 8 bits */ #else #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_2 ) /*!< ADC resolution 8 bits */ - /*!< The resolution setting is managed internaly in the driver: + /*!< The resolution setting is managed internally in the driver: "LL_ADC_RESOLUTION_8B" definition: keep using the "100b" value (corresponding to STM32H74x/5x rev Y). Rev.V value "111b" is handled through functions "LL_ADC_SetResolution/LL_ADC_GetResolution" with a dedicated check on DBGMCU IDCODE register */ #endif @@ -801,7 +801,7 @@ typedef struct * @{ */ #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define LL_ADC_DATA_ALIGN_LEFT (ADC3_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC3_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ /** * @} */ @@ -811,22 +811,22 @@ typedef struct /** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT ADC left Shift * @{ */ -#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC convesion data */ -#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC convesion data */ +#define LL_ADC_LEFT_BIT_SHIFT_NONE (0x00000000UL) /*!< ADC no bit shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_1 (ADC_CFGR2_LSHIFT_0) /*!< ADC 1 bit shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_2 (ADC_CFGR2_LSHIFT_1) /*!< ADC 2 bits shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_3 (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 3 bits shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_4 (ADC_CFGR2_LSHIFT_2) /*!< ADC 4 bits shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_5 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 5 bits shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_6 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 6 bits shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_7 (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 7 bits shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_8 (ADC_CFGR2_LSHIFT_3) /*!< ADC 8 bits shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_9 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0) /*!< ADC 9 bits shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_10 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1) /*!< ADC 10 bits shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_11 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 11 bits shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_12 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2) /*!< ADC 12 bits shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_13 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0) /*!< ADC 13 bits shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_14 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1) /*!< ADC 14 bits shift left applied on the final ADC conversion data */ +#define LL_ADC_LEFT_BIT_SHIFT_15 (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0) /*!< ADC 15 bits shift left applied on the final ADC conversion data */ /** * @} */ @@ -864,7 +864,7 @@ typedef struct * @{ */ #define LL_ADC_OFFSET_RSHIFT_DISABLE (0x00000000UL) /*!< ADC offset right shift is disabled (among ADC selected offset number 1, 2, 3 or 4) */ -#define LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1) /*!< ADC offset right shif is enabled (among ADC selected offset number 1, 2, 3 or 4) */ +#define LL_ADC_OFFSET_RSHIFT_ENABLE (ADC_CFGR2_RSHIFT1) /*!< ADC offset right shift is enabled (among ADC selected offset number 1, 2, 3 or 4) */ /** * @} */ @@ -1501,7 +1501,7 @@ typedef struct /* configuration (system clock versus ADC clock), */ /* and therefore must be defined in user application. */ /* Indications for estimation of ADC timeout delays, for this */ -/* STM32 serie: */ +/* STM32 series: */ /* - ADC calibration time: maximum delay is 16384/fADC. */ /* (refer to device datasheet, parameter "tCAL") */ /* - ADC enable time: maximum delay is 1 conversion cycle. */ @@ -1532,7 +1532,7 @@ typedef struct #define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 26UL) /*!< Delay for temperature sensor stabilization time */ /* Delay required between ADC end of calibration and ADC enable. */ -/* Note: On this STM32 serie, a minimum number of ADC clock cycles */ +/* Note: On this STM32 series, a minimum number of ADC clock cycles */ /* are required between ADC end of calibration and ADC enable. */ /* Wait time can be computed in user application by waiting for the */ /* equivalent number of CPU cycles, by taking into account */ @@ -2388,7 +2388,7 @@ typedef struct * connected to pin Vref+. * On devices with small package, the pin Vref+ is not present * and internally bonded to pin Vdda. - * @note On this STM32 serie, calibration data of internal voltage reference + * @note On this STM32 series, calibration data of internal voltage reference * VrefInt corresponds to a resolution of 16 bits, * this is the recommended ADC resolution to convert voltage of * internal voltage reference VrefInt. @@ -2439,7 +2439,7 @@ typedef struct * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note On this STM32 serie, calibration data of temperature sensor + * @note On this STM32 series, calibration data of temperature sensor * corresponds to a resolution of 16 bits, * this is the recommended ADC resolution to convert voltage of * temperature sensor. @@ -2611,11 +2611,11 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Regis /** * @brief Set parameter common to several ADC: Clock source and prescaler. - * @note On this STM32 serie, if ADC group injected is used, some + * @note On this STM32 series, if ADC group injected is used, some * clock ratio constraints between ADC clock and AHB clock * must be respected. * Refer to reference manual. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -2693,7 +2693,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) * For ADC conversion of internal channels, * a sampling time minimum value is required. * Refer to device datasheet. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -2766,7 +2766,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCx * both calibration factors must be concatenated. * To perform this processing, use helper macro * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled, without calibration on going, without conversion * on going on group regular. @@ -2829,7 +2829,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui * @note This function is intended to set linear calibration parameters * without having to perform a new calibration using * @ref LL_ADC_StartCalibration(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled, without calibration on going, without conversion * on going on group regular. @@ -2904,7 +2904,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, ui * @brief Set ADC resolution. * Refer to reference manual for alignments formats * dependencies to ADC resolutions. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3041,9 +3041,12 @@ __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -3061,7 +3064,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) * Therefore, the ADC conversion data may be outdated: does not * correspond to the current voltage level on the selected * ADC channel. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3094,9 +3097,12 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * Moreover, this avoids risk of overrun for low frequency * applications. * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. + * - It is not recommended to use with interruption or DMA + * since these modes have to clear immediately the EOC flag + * (by CPU to free the IRQ pending event or by DMA). + * Auto wait will work but fort a very short time, discarding + * its intended benefit (except specific case of high load of CPU + * or DMA transfers which can justify usage of auto wait). * - Do use with polling: 1. Start conversion, * 2. Later on, when conversion data is needed: poll for end of * conversion to ensure that conversion is completed and @@ -3185,7 +3191,7 @@ __STATIC_INLINE void LL_ADC_SetChannelPreSelection(ADC_TypeDef *ADCx, uint32_t C * to disable state using function LL_ADC_SetOffsetState(). * @note If a channel is mapped on several offsets numbers, only the offset * with the lowest value is considered for the subtraction. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3468,7 +3474,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uin /** * @brief Set for the ADC selected offset number 1, 2, 3 or 4: * choose offset saturation mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3532,7 +3538,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t /** * @brief Set for the ADC selected offset number 1, 2, 3 or 4: * choose offset sign. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3601,7 +3607,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offset * @note This function should be needed only in case of offset to be * enabled-disabled dynamically, and should not be needed in other cases: * function LL_ADC_SetOffset() automatically enables the offset. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -3681,7 +3687,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offse * @brief Set ADC group regular conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). - * @note On this STM32 serie, setting trigger source to external trigger + * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). @@ -3689,7 +3695,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offse * function @ref LL_ADC_REG_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3800,7 +3806,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) /** * @brief Set ADC group regular conversion trigger polarity. * @note Applicable only for trigger source set to external trigger. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3837,8 +3843,8 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) * @brief Set ADC sampling mode. * @note This function set the ADC conversion sampling mode * @note This mode applies to regular group only. - * @note Set sampling mode is appied to all conversion of regular group. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note Set sampling mode is applied to all conversion of regular group. + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3893,7 +3899,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t Samp * function "LL_ADC_REG_SetSequencerChannels()". * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -3985,7 +3991,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) * continuous mode and sequencer discontinuous mode. * @note It is not possible to enable both ADC auto-injected mode * and ADC group regular sequencer discontinuous mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -4038,17 +4044,17 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * @note This function performs configuration of: * - Channels ordering into each rank of scan sequence: * whatever channel can be placed into whatever rank. - * @note On this STM32 serie, ADC group regular sequencer is + * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -4135,7 +4141,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /** * @brief Get ADC group regular sequence: channel on the selected * scan sequence rank. - * @note On this STM32 serie, ADC group regular sequencer is + * @note On this STM32 series, ADC group regular sequencer is * fully configurable: sequencer length and each rank * affectation to a channel are configurable. * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). @@ -4239,7 +4245,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ * conversions launched successively automatically. * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -4275,9 +4281,9 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) * @brief Set ADC data transfer mode * @note Conversion data can be either: * - Available in Data Register - * - Transfered by DMA in one shot mode - * - Transfered by DMA in circular mode - * - Transfered to DFSDM data register + * - Transferred by DMA in one shot mode + * - Transferred by DMA in circular mode + * - Transferred to DFSDM data register * @rmtoll CFGR DMNGT LL_ADC_REG_SetDataTransferMode * @param ADCx ADC instance * @param DataTransferMode Select Data Management configuration @@ -4331,7 +4337,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledDMAReq (ADC_TypeDef *ADCx) * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). * @note To configure DMA source address (peripheral address), * use function @ref LL_ADC_DMA_GetRegAddr(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4400,9 +4406,9 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransferMode(ADC_TypeDef *ADCx) * @brief Get ADC data transfer mode * @note Conversion data can be either: * - Available in Data Register - * - Transfered by DMA in one shot mode - * - Transfered by DMA in circular mode - * - Transfered to DFSDM data register + * - Transferred by DMA in one shot mode + * - Transferred by DMA in circular mode + * - Transferred to DFSDM data register * @rmtoll CFGR DMNGT LL_ADC_REG_GetDataTransferMode * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -4426,7 +4432,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx) * The default setting of overrun is data preserved. * Therefore, for compatibility with all devices, parameter * overrun should be set to data overwritten. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. @@ -4468,7 +4474,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) * @brief Set ADC group injected conversion trigger source: * internal (SW start) or from external peripheral (timer event, * external interrupt line). - * @note On this STM32 serie, setting trigger source to external trigger + * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other * STM32 families having this setting set by HW default value). @@ -4476,7 +4482,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) * function @ref LL_ADC_INJ_SetTriggerEdge(). * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4587,7 +4593,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) /** * @brief Set ADC group injected conversion trigger polarity. * Applicable only for trigger source set to external trigger. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4627,7 +4633,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) * scan direction is forward (from rank 1 to rank n). * @note Sequencer disabled is equivalent to sequencer of 1 rank: * ADC conversion on only 1 channel. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4704,13 +4710,13 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * sequence rank. * @note Depending on devices and packages, some channels may not be available. * Refer to device datasheet for channels availability. - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On STM32H7, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN0..5). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -4856,7 +4862,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ * from ADC group regular. * @note It is not possible to enable both ADC group injected * auto-injected mode and sequencer discontinuous mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4914,7 +4920,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) * on either groups regular or injected. * @note A modification of the context mode (bit JQDIS) causes the contexts * queue to be flushed and the register JSQR is cleared. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -4964,13 +4970,13 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_INJ_GetTriggerSource() * @arg @ref LL_ADC_INJ_GetTriggerEdge() * @arg @ref LL_ADC_INJ_GetSequencerRanks() - * @note On this STM32 serie, to measure internal channels (VrefInt, + * @note On this STM32 series, to measure internal channels (VrefInt, * TempSensor, ...), measurement paths to internal channels must be * enabled separately. * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). * @note On STM32H7, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN0..5). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. @@ -5198,7 +5204,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * Refer to device datasheet for timings values (parameters TS_vrefint, * TS_temp, ...). * @note Conversion time is the addition of sampling time and processing time. - * On this STM32 serie, ADC processing time is: + * On this STM32 series, ADC processing time is: * - 12.5 ADC clock cycles at ADC resolution 12 bits * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits @@ -5207,7 +5213,7 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * temperature sensor, ...), a sampling time minimum value * is required. * Refer to device datasheet. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -5292,7 +5298,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @note On this device, sampling time is on channel scope: independently * of channel mapped on ADC group regular or injected. * @note Conversion time is the addition of sampling time and processing time. - * On this STM32 serie, ADC processing time is: + * On this STM32 series, ADC processing time is: * - 12.5 ADC clock cycles at ADC resolution 12 bits * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits @@ -5391,7 +5397,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * @note For ADC channels configured in differential mode, both inputs * should be biased at (Vref+)/2 +/-200mV. * (Vref+ is the analog voltage reference) - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @note One or several values can be selected. @@ -5516,7 +5522,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * @note In case of need to define a single channel to monitor * with analog watchdog from sequencer channel definition, * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -5537,7 +5543,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -5667,7 +5673,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * Applicable only when the analog watchdog is set to monitor * one channel. - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -5688,7 +5694,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * - resolution: resolution is limited to 8 bits: if ADC resolution is * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits * the 2 LSB are ignored. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -5839,7 +5845,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -5865,7 +5871,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint * on oversampling intermediate computation (after ratio, before shift * application): intermediate register bitfield [32:7] * (26 most significant bits). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either ADC groups regular or injected. @@ -5979,7 +5985,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_ * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this STM32 serie, there are 2 kinds of analog watchdog + * @note On this STM32 series, there are 2 kinds of analog watchdog * instance: * - AWD standard (instance AWD1): * - channels monitored: can monitor 1 channel or all channels. @@ -6047,12 +6053,12 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /** * @brief Set ADC analog watchdog filtering configuration - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. * Applicable on ADC3 of devices STM32H72xx and STM32H73xx. - * @note On this STM32 serie, this feature is only available on first + * @note On this STM32 series, this feature is only available on first * analog watchdog (AWD1) * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration * @param ADCx ADC instance @@ -6081,7 +6087,7 @@ __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint /** * @brief Get ADC analog watchdog filtering configuration - * @note On this STM32 serie, this feature is only available on first + * @note On this STM32 series, this feature is only available on first * analog watchdog (AWD1) * Applicable on ADC3 of devices STM32H72xx and STM32H73xx. * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration @@ -6130,7 +6136,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, * the oversampling on ADC group regular is either * temporary stopped and continued, or resumed from start * (oversampler buffer reset). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -6184,11 +6190,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) * are done from 1 trigger) * - discontinuous mode (each conversion of oversampling ratio * needs a trigger) - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @note On this STM32 serie, oversampling discontinuous mode + * @note On this STM32 series, oversampling discontinuous mode * (triggered mode) can be used only when oversampling is * set on group regular only and in resumed mode. * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont @@ -6228,7 +6234,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) * @note This function set the 2 items of oversampling configuration: * - ratio * - shift - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. @@ -6301,7 +6307,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) */ /** * @brief Set ADC boost mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC boost must be configured, without calibration on going, without conversion * on going on group regular. @@ -6337,7 +6343,7 @@ __STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode) /** * @brief Get ADC boost mode. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC boost must be configured, without calibration on going, without conversion * on going on group regular. @@ -6363,7 +6369,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx) * @note If multimode configuration: the selected ADC instance is * either master or slave depending on hardware. * Refer to reference manual. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -6442,7 +6448,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) * A macro is available to get the conversion data of * ADC master or ADC slave: see helper macro * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled * or enabled without conversion on going on group regular. @@ -6510,7 +6516,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_CO * - ADC resolution 10 bits can have maximum delay of 10 cycles. * - ADC resolution 8 bits can have maximum delay of 8 cycles. * - ADC resolution 6 bits can have maximum delay of 6 cycles. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * All ADC instances of the ADC common group must be disabled. * This check can be done with function @ref LL_ADC_IsEnabled() for each @@ -6594,7 +6600,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADC * state, the internal analog calibration is lost. After exiting from * deep power down, calibration must be relaunched or calibration factor * (preliminarily saved) must be set back into calibration register. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown @@ -6617,7 +6623,7 @@ __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx) * state, the internal analog calibration is lost. After exiting from * deep power down, calibration must be relaunched or calibration factor * (preliminarily saved) must be set back into calibration register. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown @@ -6645,12 +6651,12 @@ __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx) /** * @brief Enable ADC instance internal voltage regulator. - * @note On this STM32 serie, after ADC internal voltage regulator enable, + * @note On this STM32 series, after ADC internal voltage regulator enable, * a delay for ADC internal voltage regulator stabilization * is required before performing a ADC calibration or ADC enable. * Refer to device datasheet, parameter tADCVREG_STUP. * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator @@ -6669,7 +6675,7 @@ __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) /** * @brief Disable ADC internal voltage regulator. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator @@ -6694,14 +6700,14 @@ __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) /** * @brief Enable the selected ADC instance. - * @note On this STM32 serie, after ADC enable, a delay for + * @note On this STM32 series, after ADC enable, a delay for * ADC internal analog stabilization is required before performing a * ADC conversion start. * Refer to device datasheet, parameter tSTAB. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled and ADC internal voltage regulator enabled. * @rmtoll CR ADEN LL_ADC_Enable @@ -6720,7 +6726,7 @@ __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) /** * @brief Disable the selected ADC instance. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be not disabled. Must be enabled without conversion on going * on either groups regular or injected. @@ -6740,7 +6746,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) /** * @brief Get the selected ADC instance enable state. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll CR ADEN LL_ADC_IsEnabled @@ -6766,7 +6772,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) /** * @brief Start ADC calibration in the mode single-ended * or differential (for devices with differential mode available). - * @note On this STM32 serie, a minimum number of ADC clock cycles + * @note On this STM32 series, a minimum number of ADC clock cycles * are required between ADC end of calibration and ADC enable. * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. * @note Calibration duration: @@ -6781,7 +6787,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) * Calibration of linearity is common to both * single-ended and differential modes * (calibration run can be performed only once). - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. * @rmtoll CR ADCAL LL_ADC_StartCalibration\n @@ -6827,14 +6833,14 @@ __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) /** * @brief Start ADC group regular conversion. - * @note On this STM32 serie, this function is relevant for both + * @note On this STM32 series, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion * will start at next trigger event (on the selected trigger edge) * following the ADC start conversion command. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group regular, * without conversion stop command on going on group regular, @@ -6855,7 +6861,7 @@ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) /** * @brief Stop ADC group regular conversion. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled with conversion on going on group regular, * without ADC disable command on going. @@ -7022,14 +7028,14 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef /** * @brief Start ADC group injected conversion. - * @note On this STM32 serie, this function is relevant for both + * @note On this STM32 series, this function is relevant for both * internal trigger (SW start) and external trigger: * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion * will start at next trigger event (on the selected trigger edge) * following the ADC start conversion command. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled without conversion on going on group injected, * without conversion stop command on going on group injected, @@ -7050,7 +7056,7 @@ __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx) /** * @brief Stop ADC group injected conversion. - * @note On this STM32 serie, setting of this feature is conditioned to + * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be enabled with conversion on going on group injected, * without ADC disable command on going. @@ -7261,7 +7267,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 /** * @brief Get flag ADC ready. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY @@ -7385,7 +7391,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) /** * @brief Clear flag ADC ready. - * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC + * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC * is enabled and when conversion clock is active. * (not only core clock: this ADC has a dual clock domain) * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.h index 9faa900b8c..36910f2772 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_bdma.h @@ -1090,7 +1090,7 @@ __STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32 /** * @brief Configure the Source and Destination addresses. * @note This API must not be called when the BDMA channel is enabled. - * @note Each IP using BDMA provides an API to get directly the register adress (LL_PPP_BDMA_GetRegAddr). + * @note Each IP using BDMA provides an API to get directly the register address (LL_PPP_BDMA_GetRegAddr). * @rmtoll CPAR PA LL_BDMA_ConfigAddresses\n * CMAR MA LL_BDMA_ConfigAddresses * @param BDMAx BDMA Instance diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.c index 38c6c7f610..ad5d4d50f3 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.c @@ -55,7 +55,7 @@ || ((__POWER_MODE__) == LL_COMP_POWERMODE_ULTRALOWPOWER) \ ) -/* Note: On this STM32 serie, comparator input plus parameters are */ +/* Note: On this STM32 series, comparator input plus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ @@ -70,7 +70,7 @@ || ((__INPUT_PLUS__) == LL_COMP_INPUT_PLUS_IO2)) #endif -/* Note: On this STM32 serie, comparator input minus parameters are */ +/* Note: On this STM32 series, comparator input minus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ /* compatibility with other STM32 families. */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.h index e75c0bd614..beedbac038 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_comp.h @@ -321,7 +321,7 @@ typedef struct */ __STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode) { - /* Note: On this STM32 serie, window mode can be set only */ + /* Note: On this STM32 series, window mode can be set only */ /* from COMP instance: COMP2. */ MODIFY_REG(COMPxy_COMMON->CFGR, COMP_CFGRx_WINMODE, WindowMode); } @@ -391,7 +391,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx) * @note In case of comparator input selected to be connected to IO: * GPIO pins are specific to each comparator instance. * Refer to description of parameters or to reference manual. - * @note On this STM32 serie, scaler bridge is configurable: + * @note On this STM32 series, scaler bridge is configurable: * to optimize power consumption, this function enables the * voltage scaler bridge only when required * (when selecting comparator input based on VrefInt: VrefInt or @@ -489,7 +489,7 @@ __STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx) * @note In case of comparator input selected to be connected to IO: * GPIO pins are specific to each comparator instance. * Refer to description of parameters or to reference manual. - * @note On this STM32 serie, scaler bridge is configurable: + * @note On this STM32 series, scaler bridge is configurable: * to optimize power consumption, this function enables the * voltage scaler bridge only when required * (when selecting comparator input based on VrefInt: VrefInt or diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.c index da5b22b57f..7166551051 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.c @@ -25,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32H7xx_LL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.h index b46705f551..848a5dcf8d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_cordic.h @@ -95,15 +95,21 @@ extern "C" { #define LL_CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2)) #define LL_CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) #define LL_CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) -#define LL_CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) #define LL_CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3)) #define LL_CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0)) #define LL_CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1)) -#define LL_CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) #define LL_CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2)) -#define LL_CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) -#define LL_CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) -#define LL_CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0)) +#define LL_CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1)) +#define LL_CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\ + | CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\ + | CORDIC_CSR_PRECISION_0)) /** * @} */ @@ -127,8 +133,9 @@ extern "C" { * @{ */ #define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one - 32-bit data input (Q1.31 format), or two 16-bit - data input (Q1.15 format) packed in one 32 bits Data */ + 32-bit data input (Q1.31 format), or two + 16-bit data input (Q1.15 format) packed + in one 32 bits Data */ #define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input (Q1.31 format) */ /** @@ -139,8 +146,9 @@ extern "C" { * @{ */ #define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one - 32-bit data ouput (Q1.31 format), or two 16-bit - data output (Q1.15 format) packed in one 32 bits Data */ + 32-bit data output (Q1.31 format), or two + 16-bit data output (Q1.15 format) packed + in one 32 bits Data */ #define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output (Q1.31 format) */ /** @@ -240,7 +248,7 @@ extern "C" { * CSR NARGS LL_CORDIC_Configure\n * CSR NRES LL_CORDIC_Configure\n * CSR ARGSIZE LL_CORDIC_Configure\n - * CSR RESSIZE LL_CORDIC_Configure + * CSR RESIZE LL_CORDIC_Configure * @param CORDICx CORDIC instance * @param Function parameter can be one of the following values: * @arg @ref LL_CORDIC_FUNCTION_COSINE @@ -292,7 +300,8 @@ extern "C" { * @arg @ref LL_CORDIC_OUTSIZE_16BITS * @retval None */ -__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale, uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize) +__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale, + uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize) { MODIFY_REG(CORDICx->CSR, CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE | @@ -519,7 +528,7 @@ __STATIC_INLINE uint32_t LL_CORDIC_GetInSize(CORDIC_TypeDef *CORDICx) /** * @brief Configure width of output data. - * @rmtoll CSR RESSIZE LL_CORDIC_SetOutSize + * @rmtoll CSR RESIZE LL_CORDIC_SetOutSize * @param CORDICx CORDIC Instance * @param OutSize parameter can be one of the following values: * @arg @ref LL_CORDIC_OUTSIZE_32BITS @@ -533,7 +542,7 @@ __STATIC_INLINE void LL_CORDIC_SetOutSize(CORDIC_TypeDef *CORDICx, uint32_t OutS /** * @brief Return width of output data. - * @rmtoll CSR RESSIZE LL_CORDIC_GetOutSize + * @rmtoll CSR RESIZE LL_CORDIC_GetOutSize * @param CORDICx CORDIC Instance * @retval Returned value can be one of the following values: * @arg @ref LL_CORDIC_OUTSIZE_32BITS @@ -676,12 +685,12 @@ __STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint3 if (Direction == LL_CORDIC_DMA_REG_DATA_OUT) { /* return address of RDATA register */ - data_reg_addr = (uint32_t) & (CORDICx->RDATA); + data_reg_addr = (uint32_t) &(CORDICx->RDATA); } else { /* return address of WDATA register */ - data_reg_addr = (uint32_t) & (CORDICx->WDATA); + data_reg_addr = (uint32_t) &(CORDICx->WDATA); } return data_reg_addr; diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.h index 14218c8b54..85e0fe7c87 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_crs.h @@ -94,7 +94,7 @@ extern "C" { /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source * @{ */ -#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal soucre GPIO */ +#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.c index f5983de035..c27d64b452 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.c @@ -26,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32H7xx_LL_Driver * @{ @@ -46,10 +46,9 @@ /** @addtogroup DAC_LL_Private_Macros * @{ */ -#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \ - ( \ - ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ - || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ +#define IS_LL_DAC_CHANNEL(__DAC_CHANNEL__) \ + ( ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ + || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ ) #if defined (HRTIM1) @@ -104,56 +103,56 @@ ) #endif -#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ - ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ +#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ + ( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ + || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ ) #define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \ ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ - ) \ - ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ - && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ + && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ ) \ + ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ + && ( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ + || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ + ) \ ) #define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ ( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ - || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ + || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ ) #define IS_LL_DAC_OUTPUT_CONNECTION(__OUTPUT_CONNECTION__) \ ( ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_GPIO) \ - || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \ + || ((__OUTPUT_CONNECTION__) == LL_DAC_OUTPUT_CONNECT_INTERNAL) \ ) #define IS_LL_DAC_OUTPUT_MODE(__OUTPUT_MODE__) \ ( ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_NORMAL) \ - || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \ + || ((__OUTPUT_MODE__) == LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD) \ ) /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.h index 5870a17250..d0c74210bf 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dac.h @@ -53,8 +53,10 @@ extern "C" { /* - channel register offset of data holding register DHRx */ /* - channel register offset of data output register DORx */ /* - channel register offset of sample-and-hold sample time register SHSRx */ -#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ -#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ +#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers + CR, MCR, CCR, SHHR, SHRR of channel 1 */ +#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers + CR, MCR, CCR, SHHR, SHRR of channel 2 */ #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ @@ -62,33 +64,54 @@ extern "C" { #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ -#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ -#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ -#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus + DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus + DHR12Rx channel 1 (shifted left of 24 bits) */ +#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus + DHR12Rx channel 1 (shifted left of 28 bits) */ +#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus + DHR12Rx channel 1 (shifted left of 20 bits) */ +#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus + DHR12Rx channel 1 (shifted left of 24 bits) */ #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL -#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) +#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ + | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ -#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */ +#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus + DORx channel 2 (shifted left of 5 bits) */ #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */ -#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */ +#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus + SHSRx channel 2 (shifted left of 6 bits) */ #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET) -#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ -#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted to position 0 */ -#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted to position 0 */ +#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, + DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ +#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted + to position 0 */ +#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted + to position 0 */ -#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */ -#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ -#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */ -#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */ +#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 28 bits) */ +#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 20 bits) */ +#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx + channel 1 or 2 versus DHR12Rx channel 1 + (shifted left of 24 bits) */ +#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx + channel 1 or 2 versus DORx channel 1 + (shifted left of 5 bits) */ +#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx + channel 1 or 2 versus SHSRx channel 1 + (shifted left of 6 bits) */ /* DAC registers bits positions */ #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos @@ -96,7 +119,9 @@ extern "C" { #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos /* Miscellaneous data */ -#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ +#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 + bits (voltage range determined by analog voltage + references Vref+ and Vref-, refer to reference manual) */ /** * @} @@ -115,7 +140,7 @@ extern "C" { * @param __REG__ Register basis from which the offset is applied. * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). * @retval Pointer to register address -*/ + */ #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) @@ -135,38 +160,50 @@ extern "C" { */ typedef struct { - uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line). + uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: + internal (SW start) or from external peripheral + (timer event, external interrupt line). This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE - This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetTriggerSource(). */ uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE - This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetWaveAutoGeneration(). */ uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. - If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS - If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE - @note If waveform automatic generation mode is disabled, this parameter is discarded. + If waveform automatic generation mode is set to noise, this parameter + can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS + If waveform automatic generation mode is set to triangle, + this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE + @note If waveform automatic generation mode is disabled, + this parameter is discarded. - This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude() + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetWaveNoiseLFSR(), + @ref LL_DAC_SetWaveTriangleAmplitude() depending on the wave automatic generation selected. */ uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER - This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetOutputBuffer(). */ uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION - This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetOutputConnection(). */ - uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel. - This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE + uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC + channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE - This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */ + This feature can be modified afterwards using unitary + function @ref LL_DAC_SetOutputMode(). */ } LL_DAC_InitTypeDef; /** @@ -326,7 +363,7 @@ typedef struct * @{ */ #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */ -#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */ +#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */ /** * @} */ @@ -479,22 +516,8 @@ typedef struct * @arg @ref LL_DAC_CHANNEL_1 * @arg @ref LL_DAC_CHANNEL_2 */ -#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) == 1UL) \ - ? ( \ - LL_DAC_CHANNEL_1 \ - ) \ - : \ - (((__DECIMAL_NB__) == 2UL) \ - ? ( \ - LL_DAC_CHANNEL_2 \ - ) \ - : \ - ( \ - 0UL \ - ) \ - ) \ - ) +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\ + (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL))) /** * @brief Helper macro to define the DAC conversion data full-scale digital @@ -519,7 +542,7 @@ typedef struct * @ref LL_DAC_ConvertData12RightAligned(). * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE(). * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel * (unit: mVolt). @@ -531,9 +554,9 @@ typedef struct #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ __DAC_VOLTAGE__,\ __DAC_RESOLUTION__) \ - ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - / (__VREFANALOG_VOLTAGE__) \ - ) +((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ +) /** * @} @@ -665,12 +688,12 @@ __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC * @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO (3) * @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO (4) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) - * (2) On this STM32 serie, parameter only available on DAC2. - * (3) On this STM32 serie, parameter not available on all devices. + * (2) On this STM32 series, parameter only available on DAC2. + * (3) On this STM32 series, parameter not available on all devices. * Only available if TIM23 feature is supported (refer to device datasheet for supported features list) - * (4) On this STM32 serie, parameter not available on all devices. + * (4) On this STM32 series, parameter not available on all devices. * Only available if TIM24 feature is supported (refer to device datasheet for supported features list) * @retval None */ @@ -712,12 +735,12 @@ __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Cha * @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO (3) * @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO (4) * - * (1) On this STM32 serie, parameter not available on all devices. + * (1) On this STM32 series, parameter not available on all devices. * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) - * (2) On this STM32 serie, parameter only available on DAC2. - * (3) On this STM32 serie, parameter not available on all devices. + * (2) On this STM32 series, parameter only available on DAC2. + * (3) On this STM32 series, parameter not available on all devices. * Only available if TIM23 feature is supported (refer to device datasheet for supported features list) - * (4) On this STM32 serie, parameter not available on all devices. + * (4) On this STM32 series, parameter not available on all devices. * Only available if TIM24 feature is supported (refer to device datasheet for supported features list) */ __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) @@ -914,7 +937,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint * - @ref LL_DAC_SetOutputBuffer() * - @ref LL_DAC_SetOutputMode() * - @ref LL_DAC_SetOutputConnection() - * @note On this STM32 serie, output connection depends on output mode + * @note On this STM32 series, output connection depends on output mode * (normal or sample and hold) and output buffer state. * - if output connection is set to internal path and output buffer * is enabled (whatever output mode): @@ -1003,7 +1026,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Ch /** * @brief Set the output buffer for the selected DAC channel. - * @note On this STM32 serie, when buffer is enabled, its offset can be + * @note On this STM32 series, when buffer is enabled, its offset can be * trimmed: factory calibration default values can be * replaced by user trimming values, using function * @ref LL_DAC_SetTrimmingValue(). @@ -1046,7 +1069,7 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_ /** * @brief Set the output connection for the selected DAC channel. - * @note On this STM32 serie, output connection depends on output mode (normal or + * @note On this STM32 series, output connection depends on output mode (normal or * sample and hold) and output buffer state. * - if output connection is set to internal path and output buffer * is enabled (whatever output mode): @@ -1076,7 +1099,7 @@ __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_ /** * @brief Get the output connection for the selected DAC channel. - * @note On this STM32 serie, output connection depends on output mode (normal or + * @note On this STM32 series, output connection depends on output mode (normal or * sample and hold) and output buffer state. * - if output connection is set to internal path and output buffer * is enabled (whatever output mode): @@ -1121,11 +1144,10 @@ __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); - MODIFY_REG(*preg, - DAC_SHSR1_TSAMPLE1, - SampleTime); + MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime); } /** @@ -1141,7 +1163,8 @@ __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32 */ __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1); } @@ -1295,7 +1318,8 @@ __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_ * LL_DMA_ConfigAddresses(DMA1, * LL_DMA_CHANNEL_1, * (uint32_t)&< array or variable >, - * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), + * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, + * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n @@ -1317,8 +1341,8 @@ __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_C { /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ /* DAC channel selected. */ - return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, - ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); + return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); } /** * @} @@ -1481,11 +1505,10 @@ __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Cha */ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); - MODIFY_REG(*preg, - DAC_DHR12R1_DACC1DHR, - Data); + MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); } /** @@ -1503,11 +1526,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_ */ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); - MODIFY_REG(*preg, - DAC_DHR12L1_DACC1DHR, - Data); + MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); } /** @@ -1525,11 +1547,10 @@ __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t */ __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) { - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); + __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); - MODIFY_REG(*preg, - DAC_DHR8R1_DACC1DHR, - Data); + MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); } @@ -1610,7 +1631,8 @@ __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint */ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) { - __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); + __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) + & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); } diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.c index 4209a17676..0805f0075f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.c @@ -25,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32H7xx_LL_Driver * @{ @@ -175,9 +175,12 @@ ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct) { ErrorStatus status = ERROR; - LL_DMA2D_ColorTypeDef DMA2D_ColorStruct; - uint32_t tmp, tmp1, tmp2; - uint32_t regMask, regValue; + LL_DMA2D_ColorTypeDef dma2d_colorstruct; + uint32_t tmp; + uint32_t tmp1; + uint32_t tmp2; + uint32_t regMask; + uint32_t regValue; /* Check the parameters */ assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); @@ -228,12 +231,12 @@ ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_Ini LL_DMA2D_SetOutputMemAddr(DMA2Dx, DMA2D_InitStruct->OutputMemoryAddress); /* DMA2D OCOLR register configuration ------------------------------------------*/ - DMA2D_ColorStruct.ColorMode = DMA2D_InitStruct->ColorMode; - DMA2D_ColorStruct.OutputBlue = DMA2D_InitStruct->OutputBlue; - DMA2D_ColorStruct.OutputGreen = DMA2D_InitStruct->OutputGreen; - DMA2D_ColorStruct.OutputRed = DMA2D_InitStruct->OutputRed; - DMA2D_ColorStruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha; - LL_DMA2D_ConfigOutputColor(DMA2Dx, &DMA2D_ColorStruct); + dma2d_colorstruct.ColorMode = DMA2D_InitStruct->ColorMode; + dma2d_colorstruct.OutputBlue = DMA2D_InitStruct->OutputBlue; + dma2d_colorstruct.OutputGreen = DMA2D_InitStruct->OutputGreen; + dma2d_colorstruct.OutputRed = DMA2D_InitStruct->OutputRed; + dma2d_colorstruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha; + LL_DMA2D_ConfigOutputColor(DMA2Dx, &dma2d_colorstruct); status = SUCCESS; } @@ -333,9 +336,9 @@ void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D (DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_RBS | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_CSS | DMA2D_FGPFCCR_AM | \ DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \ ((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \ - DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->ChromaSubSampling | \ - DMA2D_LayerCfg->AlphaMode | (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | \ - DMA2D_LayerCfg->CLUTColorMode | DMA2D_LayerCfg->ColorMode)); + DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->ChromaSubSampling | \ + DMA2D_LayerCfg->AlphaMode | (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | \ + DMA2D_LayerCfg->CLUTColorMode | DMA2D_LayerCfg->ColorMode)); /* Configure the foreground color */ LL_DMA2D_FGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.h index 6bfc467991..583a04ea29 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dma2d.h @@ -66,91 +66,125 @@ typedef struct uint32_t Mode; /*!< Specifies the DMA2D transfer mode. - This parameter can be one value of @ref DMA2D_LL_EC_MODE. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/ + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetMode(). */ uint32_t ColorMode; /*!< Specifies the color format of the output image. - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */ + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputColorMode(). */ uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputGreen; /*!< Specifies the Green value of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputRed; /*!< Specifies the Red value of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter is not considered if RGB888 or RGB565 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputMemoryAddress; /*!< Specifies the memory address. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */ + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */ uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image. - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */ + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */ uint32_t LineOffsetMode; /*!< Specifies the output line offset mode. - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */ + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */ uint32_t LineOffset; /*!< Specifies the output line offset value. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */ + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetLineOffset(). */ uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFF. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */ + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetNbrOfLines(). */ - uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered. + uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */ + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */ uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode. - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */ + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */ uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode. - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */ + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */ } LL_DMA2D_InitTypeDef; @@ -160,7 +194,8 @@ typedef struct typedef struct { uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. This parameter can be modified afterwards using unitary functions - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer, @@ -230,7 +265,8 @@ typedef struct - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */ uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. + - This parameter must be a number between: + Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. This parameter can be modified afterwards using unitary functions - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer, @@ -267,45 +303,68 @@ typedef struct uint32_t ColorMode; /*!< Specifies the color format of the output image. - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */ + This parameter can be modified afterwards using + unitary function @ref LL_DMA2D_SetOutputColorMode(). */ uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards using, + unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputGreen; /*!< Specifies the Green value of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputRed; /*!< Specifies the Red value of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. + - This parameter must be a number between: + Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - This parameter is not considered if RGB888 or RGB565 color mode is selected. - This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration + This parameter can be modified afterwards, + using unitary function @ref LL_DMA2D_SetOutputColor() or configuration function @ref LL_DMA2D_ConfigOutputColor(). */ } LL_DMA2D_ColorTypeDef; @@ -396,9 +455,11 @@ typedef struct * @{ */ #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */ -#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */ -#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value - with original alpha channel value */ +#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by + programmed alpha value */ +#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by + programmed alpha value with, + original alpha channel value */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dmamux.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dmamux.h index 24cb55570c..9592307d5f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dmamux.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_dmamux.h @@ -249,11 +249,11 @@ extern "C" { #define LL_DMAMUX1_REQ_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request */ #if defined (HRTIM1) #define LL_DMAMUX1_REQ_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */ -#define LL_DMAMUX1_REQ_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */ -#define LL_DMAMUX1_REQ_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */ -#define LL_DMAMUX1_REQ_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */ -#define LL_DMAMUX1_REQ_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */ -#define LL_DMAMUX1_REQ_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 Timer A request 2 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 Timer B request 3 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 Timer C request 4 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 Timer D request 5 */ +#define LL_DMAMUX1_REQ_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 Timer E request 6 */ #endif /* HRTIM1 */ #define LL_DMAMUX1_REQ_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM1 Filter0 request */ #define LL_DMAMUX1_REQ_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM1 Filter1 request */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.c index 3d1d792425..b9ecde5e08 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_exti.c @@ -111,12 +111,12 @@ ErrorStatus LL_EXTI_DeInit(void) LL_EXTI_WriteReg(D3PCR2H, 0x00000000U); LL_EXTI_WriteReg(D3PCR3H, 0x00000000U); - /* Interrupt mask register set to default reset values */ + /* Interrupt mask register reset */ LL_EXTI_WriteReg(IMR1, 0x00000000U); LL_EXTI_WriteReg(IMR2, 0x00000000U); LL_EXTI_WriteReg(IMR3, 0x00000000U); - /* Event mask register set to default reset values */ + /* Event mask register reset */ LL_EXTI_WriteReg(EMR1, 0x00000000U); LL_EXTI_WriteReg(EMR2, 0x00000000U); LL_EXTI_WriteReg(EMR3, 0x00000000U); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.c index 320fcf04aa..452d5e965b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.c @@ -16,7 +16,7 @@ ============================================================================== [..] The Flexible memory controller (FMC) includes following memory controllers: (+) The NOR/PSRAM memory controller - (+) The NAND memory controller + (+) The NAND memory controller (+) The Synchronous DRAM (SDRAM) controller [..] The FMC functional block makes the interface with synchronous and asynchronous static @@ -60,13 +60,13 @@ /** @addtogroup STM32H7xx_HAL_Driver * @{ */ -#if (((defined HAL_NOR_MODULE_ENABLED || defined HAL_SRAM_MODULE_ENABLED)) || defined HAL_NAND_MODULE_ENABLED || defined HAL_SDRAM_MODULE_ENABLED) +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules * @{ */ - + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -88,14 +88,9 @@ /* --- BWTR Register ---*/ /* BWTR register clear mask */ -#if defined(FMC_BWTRx_BUSTURN) #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ FMC_BWTRx_ACCMOD)) -#else -#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ - FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD)) -#endif /* FMC_BWTRx_BUSTURN */ /* --- PCR Register ---*/ /* PCR register clear mask */ @@ -191,7 +186,8 @@ * @param Init Pointer to NORSRAM Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init) +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; uint32_t btcr_reg; @@ -287,7 +283,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); @@ -323,7 +320,8 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EX * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { uint32_t tmpr; @@ -340,17 +338,17 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR /* Set FMC_NORSRAM device timing parameters */ MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | - ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | - (Timing->AccessMode))); + ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) | + ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) | + (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) | + (Timing->AccessMode))); /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos)); + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); } @@ -370,7 +368,9 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR * @arg FMC_EXTENDED_MODE_ENABLE * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) { /* Check the parameters */ assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); @@ -383,9 +383,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); -#if defined(FMC_BWTRx_BUSTURN) assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); -#endif /* FMC_BWTRx_BUSTURN */ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); @@ -393,12 +391,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | -#if defined(FMC_BWTRx_BUSTURN) Timing->AccessMode | ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); -#else - Timing->AccessMode)); -#endif /* FMC_BWTRx_BUSTURN */ } else { @@ -412,8 +406,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef */ /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### FMC_NORSRAM Control functions ##### @@ -497,8 +491,8 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device */ /** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim ============================================================================== ##### Initialization and de_initialization functions ##### @@ -552,7 +546,8 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -582,7 +577,8 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -703,7 +699,8 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout) { uint32_t tickstart; @@ -850,7 +847,8 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe * @param Bank SDRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -979,7 +977,8 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, u * @param Timeout Timeout wait value * @retval HAL state */ -HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -989,10 +988,10 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Com assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); /* Set command register */ - SET_BIT(Device->SDCMR, ((Command->CommandMode) | - (Command->CommandTarget) | - (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) | - ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos))); + MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | + FMC_SDCMR_NRFS | FMC_SDCMR_MRD), ((Command->CommandMode) | + (Command->CommandTarget) | (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) | + ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos))); /* Prevent unused argument(s) compilation warning */ UNUSED(Timeout); return HAL_OK; @@ -1022,7 +1021,8 @@ HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32 * @param AutoRefreshNumber Specifies the auto Refresh number. * @retval None */ -HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, + uint32_t AutoRefreshNumber) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); @@ -1086,5 +1086,8 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) /** * @} */ +/** + * @} + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.h index 124f5cdbc8..687775a585 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_fmc.h @@ -116,8 +116,8 @@ extern "C" { #define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32)) + ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32)) #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ @@ -150,19 +150,19 @@ extern "C" { #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U) #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) #define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \ - ((__BANK__) == FMC_SDRAM_BANK2)) + ((__BANK__) == FMC_SDRAM_BANK2)) #define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ - ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ - ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ - ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11)) + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11)) #define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \ - ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \ - ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13)) + ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \ + ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13)) #define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ - ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4)) + ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4)) #define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \ - ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \ - ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3)) + ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \ + ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3)) /** @@ -191,62 +191,62 @@ extern "C" { typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Write_FIFO */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ -}FMC_NORSRAM_InitTypeDef; + This parameter can be a value of @ref FMC_Page_Size */ +} FMC_NORSRAM_InitTypeDef; /** * @brief FMC NORSRAM Timing parameters structure definition @@ -256,40 +256,41 @@ typedef struct uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between Min_Data = 1 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between Min_Data = 1 and Max_Data = 255. @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed - NOR Flash memories. */ + NOR Flash memories. */ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is only used for multiplexed NOR Flash memories. */ + @note This parameter is only used for multiplexed NOR Flash memories. */ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of - HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. + HCLK cycles. This parameter can be a value between Min_Data = 2 and + Max_Data = 16. @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM - accesses. */ + accesses. */ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories - with synchronous burst mode enable */ + - It may assume a value between Min_Data = 2 and Max_Data = 17 + in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ -}FMC_NORSRAM_TimingTypeDef; + This parameter can be a value of @ref FMC_Access_Mode */ +} FMC_NORSRAM_TimingTypeDef; /** * @brief FMC NAND Configuration Structure definition @@ -297,19 +298,19 @@ typedef struct typedef struct { uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. - This parameter can be a value of @ref FMC_NAND_Bank */ + This parameter can be a value of @ref FMC_NAND_Bank */ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. - This parameter can be any value of @ref FMC_Wait_feature */ + This parameter can be any value of @ref FMC_Wait_feature */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FMC_NAND_Data_Width */ + This parameter can be any value of @ref FMC_NAND_Data_Width */ uint32_t EccComputation; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FMC_ECC */ + This parameter can be any value of @ref FMC_ECC */ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FMC_ECC_Page_Size */ + This parameter can be any value of @ref FMC_ECC_Page_Size */ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. @@ -318,7 +319,7 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ -}FMC_NAND_InitTypeDef; +} FMC_NAND_InitTypeDef; /** * @brief FMC NAND Timing parameters structure definition @@ -349,7 +350,7 @@ typedef struct write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ -}FMC_NAND_PCC_TimingTypeDef; +} FMC_NAND_PCC_TimingTypeDef; /** @@ -388,7 +389,7 @@ typedef struct uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ -}FMC_SDRAM_InitTypeDef; +} FMC_SDRAM_InitTypeDef; /** * @brief FMC SDRAM Timing parameters structure definition @@ -422,7 +423,7 @@ typedef struct uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ -}FMC_SDRAM_TimingTypeDef; +} FMC_SDRAM_TimingTypeDef; /** * @brief SDRAM command parameters structure definition @@ -440,7 +441,7 @@ typedef struct This parameter can be a value between Min_Data = 1 and Max_Data = 15 */ uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ -}FMC_SDRAM_CommandTypeDef; +} FMC_SDRAM_CommandTypeDef; /** * @} */ @@ -457,10 +458,10 @@ typedef struct /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank * @{ */ -#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) -#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) -#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) -#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) +#define FMC_NORSRAM_BANK1 (0x00000000U) +#define FMC_NORSRAM_BANK2 (0x00000002U) +#define FMC_NORSRAM_BANK3 (0x00000004U) +#define FMC_NORSRAM_BANK4 (0x00000006U) /** * @} */ @@ -468,8 +469,8 @@ typedef struct /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing * @{ */ -#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) -#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002) +#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) /** * @} */ @@ -477,9 +478,9 @@ typedef struct /** @defgroup FMC_Memory_Type FMC Memory Type * @{ */ -#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) -#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004) -#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008) +#define FMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FMC_MEMORY_TYPE_NOR (0x00000008U) /** * @} */ @@ -487,9 +488,9 @@ typedef struct /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width * @{ */ -#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) -#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) -#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) /** * @} */ @@ -497,8 +498,8 @@ typedef struct /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access * @{ */ -#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040) -#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) /** * @} */ @@ -506,8 +507,8 @@ typedef struct /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode * @{ */ -#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) -#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100) +#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) /** * @} */ @@ -515,8 +516,8 @@ typedef struct /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity * @{ */ -#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) -#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200) +#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) /** * @} */ @@ -524,8 +525,8 @@ typedef struct /** @defgroup FMC_Wait_Timing FMC Wait Timing * @{ */ -#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) -#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800) +#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) +#define FMC_WAIT_TIMING_DURING_WS (0x00000800U) /** * @} */ @@ -533,8 +534,8 @@ typedef struct /** @defgroup FMC_Write_Operation FMC Write Operation * @{ */ -#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) -#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000) +#define FMC_WRITE_OPERATION_DISABLE (0x00000000U) +#define FMC_WRITE_OPERATION_ENABLE (0x00001000U) /** * @} */ @@ -542,8 +543,8 @@ typedef struct /** @defgroup FMC_Wait_Signal FMC Wait Signal * @{ */ -#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) -#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000) +#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) /** * @} */ @@ -551,8 +552,8 @@ typedef struct /** @defgroup FMC_Extended_Mode FMC Extended Mode * @{ */ -#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) -#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000) +#define FMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FMC_EXTENDED_MODE_ENABLE (0x00004000U) /** * @} */ @@ -560,8 +561,8 @@ typedef struct /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait * @{ */ -#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) -#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000) +#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) /** * @} */ @@ -569,11 +570,12 @@ typedef struct /** @defgroup FMC_Page_Size FMC Page Size * @{ */ -#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) -#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) -#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) -#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1)) -#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2) +#define FMC_PAGE_SIZE_NONE (0x00000000U) +#define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 +#define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 +#define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ + | FMC_BCRx_CPSIZE_1) +#define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 /** * @} */ @@ -581,8 +583,8 @@ typedef struct /** @defgroup FMC_Write_Burst FMC Write Burst * @{ */ -#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) -#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000) +#define FMC_WRITE_BURST_DISABLE (0x00000000U) +#define FMC_WRITE_BURST_ENABLE (0x00080000U) /** * @} */ @@ -590,8 +592,8 @@ typedef struct /** @defgroup FMC_Continous_Clock FMC Continuous Clock * @{ */ -#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) -#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000) +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) /** * @} */ @@ -599,19 +601,19 @@ typedef struct /** @defgroup FMC_Write_FIFO FMC Write FIFO * @{ */ -#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) -#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000) +#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS +#define FMC_WRITE_FIFO_ENABLE (0x00000000U) /** * @} */ - /** @defgroup FMC_Access_Mode FMC Access Mode +/** @defgroup FMC_Access_Mode FMC Access Mode * @{ */ -#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) -#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000) -#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000) -#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000) +#define FMC_ACCESS_MODE_A (0x00000000U) +#define FMC_ACCESS_MODE_B (0x10000000U) +#define FMC_ACCESS_MODE_C (0x20000000U) +#define FMC_ACCESS_MODE_D (0x30000000U) /** * @} */ @@ -627,7 +629,7 @@ typedef struct /** @defgroup FMC_NAND_Bank FMC NAND Bank * @{ */ -#define FMC_NAND_BANK3 ((uint32_t)0x00000100) +#define FMC_NAND_BANK3 (0x00000100U) /** * @} */ @@ -635,8 +637,8 @@ typedef struct /** @defgroup FMC_Wait_feature FMC Wait feature * @{ */ -#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) -#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) +#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) +#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) /** * @} */ @@ -644,7 +646,7 @@ typedef struct /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type * @{ */ -#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008) +#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) /** * @} */ @@ -652,8 +654,8 @@ typedef struct /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width * @{ */ -#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) -#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) +#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) /** * @} */ @@ -661,8 +663,8 @@ typedef struct /** @defgroup FMC_ECC FMC ECC * @{ */ -#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) -#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040) +#define FMC_NAND_ECC_DISABLE (0x00000000U) +#define FMC_NAND_ECC_ENABLE (0x00000040U) /** * @} */ @@ -670,12 +672,12 @@ typedef struct /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size * @{ */ -#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) -#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000) -#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000) -#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000) -#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000) -#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000) +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) +#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) +#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) +#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) +#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) +#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) /** * @} */ @@ -690,8 +692,8 @@ typedef struct /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank * @{ */ -#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000) -#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001) +#define FMC_SDRAM_BANK1 (0x00000000U) +#define FMC_SDRAM_BANK2 (0x00000001U) /** * @} */ @@ -699,10 +701,10 @@ typedef struct /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number * @{ */ -#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000) -#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001) -#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002) -#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003) +#define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U) +#define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U) +#define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U) +#define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U) /** * @} */ @@ -710,9 +712,9 @@ typedef struct /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number * @{ */ -#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000) -#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004) -#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008) +#define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U) +#define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U) +#define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U) /** * @} */ @@ -720,9 +722,9 @@ typedef struct /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width * @{ */ -#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) -#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) -#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) +#define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U) /** * @} */ @@ -730,8 +732,8 @@ typedef struct /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number * @{ */ -#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000) -#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040) +#define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U) +#define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U) /** * @} */ @@ -739,9 +741,9 @@ typedef struct /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency * @{ */ -#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080) -#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100) -#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180) +#define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U) +#define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U) +#define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U) /** * @} */ @@ -749,8 +751,8 @@ typedef struct /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection * @{ */ -#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000) -#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200) +#define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U) +#define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U) /** * @} */ @@ -758,9 +760,9 @@ typedef struct /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period * @{ */ -#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000) -#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800) -#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00) +#define FMC_SDRAM_CLOCK_DISABLE (0x00000000U) +#define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U) +#define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U) /** * @} */ @@ -768,8 +770,8 @@ typedef struct /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst * @{ */ -#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000) -#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000) +#define FMC_SDRAM_RBURST_DISABLE (0x00000000U) +#define FMC_SDRAM_RBURST_ENABLE (0x00001000U) /** * @} */ @@ -777,9 +779,9 @@ typedef struct /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay * @{ */ -#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000) -#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000) -#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000) +#define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U) +#define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U) +#define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U) /** * @} */ @@ -787,13 +789,13 @@ typedef struct /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode * @{ */ -#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000) -#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001) -#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002) -#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003) -#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004) -#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005) -#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006) +#define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U) +#define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U) +#define FMC_SDRAM_CMD_PALL (0x00000002U) +#define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U) +#define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U) +#define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U) +#define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U) /** * @} */ @@ -803,7 +805,7 @@ typedef struct */ #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 -#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018) +#define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U) /** * @} */ @@ -811,7 +813,7 @@ typedef struct /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status * @{ */ -#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000) +#define FMC_SDRAM_NORMAL_MODE (0x00000000U) #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 /** @@ -826,10 +828,10 @@ typedef struct /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition * @{ */ -#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008) -#define FMC_IT_LEVEL ((uint32_t)0x00000010) -#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020) -#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000) +#define FMC_IT_RISING_EDGE (0x00000008U) +#define FMC_IT_LEVEL (0x00000010U) +#define FMC_IT_FALLING_EDGE (0x00000020U) +#define FMC_IT_REFRESH_ERROR (0x00004000U) /** * @} */ @@ -837,10 +839,10 @@ typedef struct /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition * @{ */ -#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001) -#define FMC_FLAG_LEVEL ((uint32_t)0x00000002) -#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004) -#define FMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define FMC_FLAG_RISING_EDGE (0x00000001U) +#define FMC_FLAG_LEVEL (0x00000002U) +#define FMC_FLAG_FALLING_EDGE (0x00000004U) +#define FMC_FLAG_FEMPT (0x00000040U) #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE @@ -855,12 +857,12 @@ typedef struct /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros * @{ */ - /** +/** * @brief Enable the FMC Peripheral. * @retval None */ @@ -882,7 +884,8 @@ typedef struct * @param __BANK__ FMC_NORSRAM Bank * @retval None */ -#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN) +#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + |= FMC_BCRx_MBKEN) /** * @brief Disable the NORSRAM device access. @@ -890,16 +893,17 @@ typedef struct * @param __BANK__ FMC_NORSRAM Bank * @retval None */ -#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN) +#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + &= ~FMC_BCRx_MBKEN) /** * @} */ /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros - * @brief macros to handle NAND device enable/disable - * @{ - */ + * @brief macros to handle NAND device enable/disable + * @{ + */ /** * @brief Enable the NAND device access. @@ -1050,10 +1054,15 @@ typedef struct /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode); +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); /** * @} */ @@ -1077,8 +1086,10 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic * @{ */ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -1089,7 +1100,8 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout); /** * @} */ @@ -1105,7 +1117,8 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u * @{ */ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); -HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} @@ -1116,9 +1129,11 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); -HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, + uint32_t AutoRefreshNumber); uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.h index 4b67d6cd15..cf032aa297 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_gpio.h @@ -942,7 +942,8 @@ __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMas */ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) { - WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.h index 69d00fceef..36a12353f7 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_hrtim.h @@ -803,7 +803,7 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] = * @brief Constants defining the registers that can be written during a burst DMA operation. */ #define LL_HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */ -#define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */ +#define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */ #define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */ #define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */ #define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */ @@ -997,37 +997,37 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] = * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output. */ #define LL_HRTIM_CROSSBAR_NONE 0x00000000U /*!< Reset the output set crossbar */ -#define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transision */ -#define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transision */ -#define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transision */ -#define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transision */ -#define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transision */ -#define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transision */ -#define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transision */ +#define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transition */ +#define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transition */ +#define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transition */ +#define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transition */ +#define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transition */ +#define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transition */ +#define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transition */ /** * @} */ @@ -1036,7 +1036,7 @@ static const uint8_t REG_SHIFT_TAB_FLTxE[] = * @{ * @brief Constants defining the polarity of a timer output. */ -#define LL_HRTIM_OUT_POSITIVE_POLARITY 0x00000000U /*!< Output is acitve HIGH */ +#define LL_HRTIM_OUT_POSITIVE_POLARITY 0x00000000U /*!< Output is active HIGH */ #define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /*!< Output is active LOW */ /** * @} @@ -7286,7 +7286,7 @@ __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx) */ __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx) { - uint32_t temp; /* MISRAC-2012 compliancy */ + uint32_t temp; /* MISRAC-2012 compliance */ temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN); return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.h index d91b7c2f7e..c698b7ae3a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_i2c.h @@ -360,11 +360,11 @@ typedef struct * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ - (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ - (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) /** * @} */ @@ -583,12 +583,12 @@ __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direc if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) { /* return address of TXDR register */ - data_reg_addr = (uint32_t) & (I2Cx->TXDR); + data_reg_addr = (uint32_t) &(I2Cx->TXDR); } else { /* return address of RXDR register */ - data_reg_addr = (uint32_t) & (I2Cx->RXDR); + data_reg_addr = (uint32_t) &(I2Cx->RXDR); } return data_reg_addr; @@ -1163,7 +1163,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout } /** - * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting. + * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not * SMBus feature is supported by the I2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB @@ -2090,7 +2090,9 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, uint32_t TransferSize, uint32_t EndMode, uint32_t Request) { - MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); } @@ -2157,7 +2159,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) * @rmtoll PECR PEC LL_I2C_GetSMBusPEC * @param I2Cx I2C Instance. * @retval Value between Min_Data=0x00 and Max_Data=0xFF -*/ + */ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) { return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_iwdg.h index cf94fd72c8..8e22e3d7f5 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_iwdg.h @@ -304,8 +304,8 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) /** * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not * @rmtoll SR PVU LL_IWDG_IsReady\n - * SR WVU LL_IWDG_IsReady\n - * SR RVU LL_IWDG_IsReady + * SR RVU LL_IWDG_IsReady\n + * SR WVU LL_IWDG_IsReady * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ @@ -318,7 +318,6 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) * @} */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.c index ff1ee656cc..bf08c4620c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.c @@ -48,22 +48,22 @@ * @{ */ #define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ - || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) + || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) #define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) #define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) + || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) #define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) + || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) /** * @} */ @@ -296,8 +296,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } - while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_CMPOK(LPTIMx); } diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.h index 2529003767..a2ee75c665 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lptim.h @@ -100,9 +100,9 @@ typedef struct * @{ */ #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */ +#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */ -#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ @@ -114,13 +114,13 @@ typedef struct * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions * @{ */ -#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */ -#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */ -#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */ -#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */ -#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */ -#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */ -#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */ +#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */ +#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */ +#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */ +#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */ +#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */ +#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */ +#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */ /** * @} */ @@ -155,7 +155,7 @@ typedef struct /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type * @{ */ -#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!HardwareFlowControl value. + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according + * to LPUART_InitStruct->HardwareFlowControl value. */ LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl); @@ -271,7 +274,7 @@ void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) * @} */ -#endif /* defined (LPUART1) */ +#endif /* LPUART1 */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lpuart.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lpuart.h index 1471bdd162..64e17f9c70 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lpuart.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_lpuart.h @@ -100,36 +100,43 @@ typedef struct uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetPrescaler().*/ uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetBaudRate().*/ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetDataWidth().*/ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref LPUART_LL_EC_STOPBITS. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetStopBitsLength().*/ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref LPUART_LL_EC_PARITY. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetParity().*/ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of @ref LPUART_LL_EC_DIRECTION. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetTransferDirection().*/ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL. - This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetHWFlowCtrl().*/ } LL_LPUART_InitTypeDef; @@ -147,16 +154,16 @@ typedef struct * @brief Flags defines which can be used with LL_LPUART_WriteReg function * @{ */ -#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ -#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */ -#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ -#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ -#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ -#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ -#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ -#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ -#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ +#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ /** * @} */ @@ -165,27 +172,27 @@ typedef struct * @brief Flags defines which can be used with LL_LPUART_ReadReg function * @{ */ -#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ -#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ -#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ -#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ -#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ -#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ -#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ -#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ -#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ -#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ -#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ -#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ -#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ -#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ -#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ -#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ -#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ -#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ -#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ -#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ -#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ /** * @} */ @@ -194,19 +201,21 @@ typedef struct * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions * @{ */ -#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ -#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ -#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ -#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ -#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ -#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ -#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ -#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ -#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ -#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ -#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ -#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ -#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty + interrupt enable */ +#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO + not full interrupt enable */ +#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ /** * @} */ @@ -227,10 +236,10 @@ typedef struct /** @defgroup LPUART_LL_EC_DIRECTION Direction * @{ */ -#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ -#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ -#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ -#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ /** * @} */ @@ -238,9 +247,9 @@ typedef struct /** @defgroup LPUART_LL_EC_PARITY Parity Control * @{ */ -#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ -#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ -#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ /** * @} */ @@ -248,8 +257,8 @@ typedef struct /** @defgroup LPUART_LL_EC_WAKEUP Wakeup * @{ */ -#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ -#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ +#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ +#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ /** * @} */ @@ -257,9 +266,9 @@ typedef struct /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth * @{ */ -#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ -#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ -#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ /** * @} */ @@ -267,18 +276,27 @@ typedef struct /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler * @{ */ -#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */ -#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */ -#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */ -#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */ -#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */ -#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */ -#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */ -#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */ -#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */ -#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */ -#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */ -#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ /** * @} */ @@ -286,8 +304,8 @@ typedef struct /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits * @{ */ -#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ -#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ /** * @} */ @@ -295,8 +313,8 @@ typedef struct /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap * @{ */ -#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ -#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ /** * @} */ @@ -304,8 +322,8 @@ typedef struct /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion * @{ */ -#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ -#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ /** * @} */ @@ -313,8 +331,8 @@ typedef struct /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion * @{ */ -#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ -#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ /** * @} */ @@ -322,8 +340,11 @@ typedef struct /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion * @{ */ -#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ -#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received + in positive/direct logic. (1=H, 0=L) */ +#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received + in negative/inverse logic. (1=L, 0=H). + The parity bit is also inverted. */ /** * @} */ @@ -331,8 +352,10 @@ typedef struct /** @defgroup LPUART_LL_EC_BITORDER Bit Order * @{ */ -#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ -#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, + following the start bit */ +#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, + following the start bit */ /** * @} */ @@ -340,8 +363,8 @@ typedef struct /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection * @{ */ -#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ -#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ /** * @} */ @@ -349,10 +372,12 @@ typedef struct /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control * @{ */ -#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ -#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ -#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ -#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested + when there is space in the receive buffer */ +#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted + when the nCTS input is asserted (tied to 0)*/ +#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ /** * @} */ @@ -360,9 +385,9 @@ typedef struct /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation * @{ */ -#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ -#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ -#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ /** * @} */ @@ -370,8 +395,8 @@ typedef struct /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity * @{ */ -#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ -#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ /** * @} */ @@ -379,8 +404,8 @@ typedef struct /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ /** * @} */ @@ -442,8 +467,9 @@ typedef struct * @param __BAUDRATE__ Baud Rate value to achieve * @retval LPUARTDIV value to be used for BRR register filling */ -#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\ - + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\ + ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\ + * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) /** * @} @@ -629,7 +655,8 @@ __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) */ __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos)); + MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ + (RXThreshold << USART_CR3_RXFTCFG_Pos)); } /** @@ -1345,7 +1372,10 @@ __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate) { - LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); + if (BaudRate != 0U) + { + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); + } } /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.h index 18609ad3e6..38d08f2e91 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_mdma.h @@ -279,7 +279,7 @@ typedef struct /** @defgroup MDMA_LL_EC_WORD_ENDIANNESS Word Endianness * @{ */ -#define LL_MDMA_WORD_ENDIANNESS_PRESERVE 0x00000000U /*!< Little endianess preserved for words */ +#define LL_MDMA_WORD_ENDIANNESS_PRESERVE 0x00000000U /*!< Little endianness preserved for words */ #define LL_MDMA_WORD_ENDIANNESS_EXCHANGE MDMA_CCR_WEX /*!< word order exchanged when destination data size is double word */ /** @@ -289,7 +289,7 @@ typedef struct /** @defgroup MDMA_LL_EC_HALFWORD_ENDIANNESS Half Word Endianness * @{ */ -#define LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE 0x00000000U /*!< Little endianess preserved for half words */ +#define LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE 0x00000000U /*!< Little endianness preserved for half words */ #define LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE MDMA_CCR_HEX /*!< half word order exchanged when destination data size is word or double word */ /** @@ -299,7 +299,7 @@ typedef struct /** @defgroup MDMA_LL_EC_BYTE_ENDIANNESS Byte Endianness * @{ */ -#define LL_MDMA_BYTE_ENDIANNESS_PRESERVE 0x00000000U /*!< Little endianess preserved for bytes */ +#define LL_MDMA_BYTE_ENDIANNESS_PRESERVE 0x00000000U /*!< Little endianness preserved for bytes */ #define LL_MDMA_BYTE_ENDIANNESS_EXCHANGE MDMA_CCR_BEX /*!< byte order exchanged when destination data size is half word , word or double word */ /** @@ -787,7 +787,7 @@ __STATIC_INLINE void LL_MDMA_GenerateSWRequest(MDMA_TypeDef *MDMAx, uint32_t Cha } /** - * @brief Configure Transfer endianness paremeters : Word, Half word and Bytes Endianess. + * @brief Configure Transfer endianness parameters : Word, Half word and Bytes Endianness. * @rmtoll CCR WEX LL_MDMA_ConfigXferEndianness\n * @rmtoll CCR HEX LL_MDMA_ConfigXferEndianness\n * @rmtoll CCR BEX LL_MDMA_ConfigXferEndianness @@ -824,7 +824,7 @@ __STATIC_INLINE void LL_MDMA_ConfigXferEndianness(MDMA_TypeDef *MDMAx, uint32_t } /** - * @brief Set Words Endianess. + * @brief Set Words Endianness. * @rmtoll CCR WEX LL_MDMA_SetWordEndianness * @param MDMAx MDMAx Instance * @param Channel This parameter can be one of the following values: @@ -857,7 +857,7 @@ __STATIC_INLINE void LL_MDMA_SetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Cha } /** - * @brief Get Words Endianess. + * @brief Get Words Endianness. * @rmtoll CCR WEX LL_MDMA_GetWordEndianness * @param MDMAx MDMAx Instance * @param Channel This parameter can be one of the following values: @@ -890,7 +890,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t } /** - * @brief Set Half Words Endianess. + * @brief Set Half Words Endianness. * @rmtoll CCR HEX LL_MDMA_SetHalfWordEndianness * @param MDMAx MDMAx Instance * @param Channel This parameter can be one of the following values: @@ -923,7 +923,7 @@ __STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t } /** - * @brief Get Half Words Endianess. + * @brief Get Half Words Endianness. * @rmtoll CCR HEX LL_MDMA_GetHalfWordEndianness * @param MDMAx MDMAx Instance * @param Channel This parameter can be one of the following values: @@ -956,7 +956,7 @@ __STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint } /** - * @brief Set Bytes Endianess. + * @brief Set Bytes Endianness. * @rmtoll CCR BEX LL_MDMA_SetByteEndianness * @param MDMAx MDMAx Instance * @param Channel This parameter can be one of the following values: @@ -989,7 +989,7 @@ __STATIC_INLINE void LL_MDMA_SetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Cha } /** - * @brief Get Bytes Endianess. + * @brief Get Bytes Endianness. * @rmtoll CCR BEX LL_MDMA_GetByteEndianness * @param MDMAx MDMAx Instance * @param Channel This parameter can be one of the following values: diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.h index 9808ab1e37..b6d4d3eb88 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_opamp.h @@ -191,10 +191,10 @@ typedef struct */ #define LL_OPAMP_INPUT_NONINVERT_IO0 0x00000000U /*!< OPAMP non inverting input connected to I/O VINP0 (PB0 for OPAMP1, PE9 for OPAMP2) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define LL_OPAMP_INPUT_NONINVERT_DAC OPAMP_CSR_VPSEL_0 /*!< OPAMP non inverting input connected internally to DAC channel (DAC1_CH1 for OPAMP1, DAC1_CH2 for OPAMP2) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #if defined(DAC2) #define LL_OPAMP_INPUT_NONINVERT_DAC2 OPAMP_CSR_VPSEL_1 /*!< OPAMP non inverting input connected internally to DAC2 channel (DAC3 only for OPAMP2)*/ @@ -211,12 +211,12 @@ typedef struct */ #define LL_OPAMP_INPUT_INVERT_IO0 0x00000000U /*!< OPAMP inverting input connected to I/O VINM0 (PC5 for OPAMP1, PE8 for OPAMP2) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define LL_OPAMP_INPUT_INVERT_IO1 OPAMP_CSR_VMSEL_0 /*!< OPAMP inverting input connected to I/0 VINM1 (PA7 for OPAMP1, PG1 for OPAMP2) - Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ + Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */ #define LL_OPAMP_INPUT_INVERT_CONNECT_NO OPAMP_CSR_VMSEL_1 /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA with positive gain without bias). - Note: On this STM32 serie, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */ + Note: On this STM32 series, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */ /** * @} */ @@ -751,7 +751,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32 /** * @brief Enable OPAMP instance. * @note After enable from off state, OPAMP requires a delay - * to fullfill wake up time specification. + * to fulfill wake up time specification. * Refer to device datasheet, parameter "tWAKEUP". * @rmtoll CSR OPAMPXEN LL_OPAMP_Enable * @param OPAMPx OPAMP instance diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.h index 98602e2296..a7f82057c2 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_pwr.h @@ -294,13 +294,13 @@ extern "C" { /** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration * @{ */ -#define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are suppplied from the LDO */ +#define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */ #if defined (SMPS) -#define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are suppplied from the SMPS */ +#define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS */ #define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ #define LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ -#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */ -#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */ +#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ +#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ #define LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ #define LL_PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ #endif /* SMPS */ @@ -537,7 +537,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void) #if defined (PWR_CR1_AVD_READY) /** - * @brief Enable the Analog Voltage Ready to isolate the BOOST IP untill VDDA will be ready + * @brief Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready * @rmtoll CR1 AVD_READY LL_PWR_EnableAnalogVoltageReady * @retval None */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.c index 282b9abae7..68ed42ac55 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.c @@ -83,12 +83,12 @@ const uint8_t LL_RCC_PrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, /** @defgroup RCC_LL_Private_Functions RCC Private functions * @{ */ -uint32_t RCC_GetSystemClockFreq(void); -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); -uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); -uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency); -uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetSystemClockFreq(void); +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency); /** * @} @@ -1681,7 +1681,7 @@ uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource) * @brief Return SYSTEM clock frequency * @retval SYSTEM clock frequency (in Hz) */ -uint32_t RCC_GetSystemClockFreq(void) +static uint32_t RCC_GetSystemClockFreq(void) { uint32_t frequency = 0U; LL_PLL_ClocksTypeDef PLL_Clocks; @@ -1720,7 +1720,7 @@ uint32_t RCC_GetSystemClockFreq(void) * @param SYSCLK_Frequency SYSCLK clock frequency * @retval HCLK clock frequency (in Hz) */ -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) { /* HCLK clock frequency */ return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); @@ -1731,7 +1731,7 @@ uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) * @param HCLK_Frequency HCLK clock frequency * @retval PCLK1 clock frequency (in Hz) */ -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) { /* PCLK1 clock frequency */ return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); @@ -1742,7 +1742,7 @@ uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) * @param HCLK_Frequency HCLK clock frequency * @retval PCLK2 clock frequency (in Hz) */ -uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) +static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) { /* PCLK2 clock frequency */ return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); @@ -1753,7 +1753,7 @@ uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) * @param HCLK_Frequency HCLK clock frequency * @retval PCLK3 clock frequency (in Hz) */ -uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency) +static uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency) { /* PCLK3 clock frequency */ return LL_RCC_CALC_PCLK3_FREQ(HCLK_Frequency, LL_RCC_GetAPB3Prescaler()); @@ -1764,7 +1764,7 @@ uint32_t RCC_GetPCLK3ClockFreq(uint32_t HCLK_Frequency) * @param HCLK_Frequency HCLK clock frequency * @retval PCLK4 clock frequency (in Hz) */ -uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency) +static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency) { /* PCLK4 clock frequency */ return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler()); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.h index ed63ebf55b..2ab40eb0f6 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rcc.h @@ -64,13 +64,13 @@ extern const uint8_t LL_RCC_PrescTable[16]; --------------------------------------------------------*/ #if defined(RCC_VER_2_0) -/* Clock source register offset Vs CDCCIPR regsiter */ +/* Clock source register offset Vs CDCCIPR register */ #define CDCCIP 0x0UL #define CDCCIP1 0x4UL #define CDCCIP2 0x8UL #define SRDCCIP 0xCUL #else -/* Clock source register offset Vs D1CCIPR regsiter */ +/* Clock source register offset Vs D1CCIPR register */ #define D1CCIP 0x0UL #define D2CCIP1 0x4UL #define D2CCIP2 0x8UL @@ -4594,7 +4594,9 @@ __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M) * @brief Set PLL1 P Coefficient * @note This API shall be called only when PLL1 is disabled. * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_SetP - * @param P parameter can be a value between 2 and 128 (ODD division factor not supportted) + * @param P parameter can be a value between 2 (or 1*) and 128 (ODD division factor not supported) + * + * (*) : For stm32h72xxx and stm32h73xxx family lines. */ __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P) { diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.c index d3d34521cb..a98addf20e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.c @@ -26,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32H7xx_LL_Driver * @{ @@ -53,7 +53,7 @@ #define IS_LL_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == LL_RNG_NIST_COMPLIANT) || \ - ((__NIST_COMPLIANCE__) == LL_RNG_NOTNIST_COMPLIANT)) + ((__NIST_COMPLIANCE__) == LL_RNG_NOTNIST_COMPLIANT)) #define IS_LL_RNG_CONFIG1 (__CONFIG1__) ((__CONFIG1__) <= 0x3FUL) diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.h index ab89a18575..1b98dd0fb7 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_rng.h @@ -57,8 +57,8 @@ typedef struct { uint32_t ClockErrorDetection; /*!< Clock error detection. This parameter can be one value of @ref RNG_LL_CED. - - This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */ + This parameter can be modified using unitary + functions @ref LL_RNG_EnableClkErrorDetect(). */ } LL_RNG_InitTypeDef; /** @@ -81,7 +81,7 @@ typedef struct #if defined(RNG_CR_CONDRST) /** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal - * programmable divider acting on the incoming RNG clock + * programmable divider acting on the incoming RNG clock * @{ */ #define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */ @@ -114,7 +114,7 @@ typedef struct * @} */ -#endif/*RNG_CR_CONDRST*/ +#endif /* RNG_CR_CONDRST */ /** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines * @brief Flags defines which can be used with LL_RNG_ReadReg function * @{ @@ -645,7 +645,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx) /** * @} */ -#endif /*End of RNG_VER_3_2, RNG_VER_3_1 or RNG_VER_3_0*/ +#endif /* RNG_VER_3_2, RNG_VER_3_1 or RNG_VER_3_0 */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.c index 4c2e72d728..36c52c328d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.c @@ -170,11 +170,6 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx); -static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); -static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); -static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); -static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); -static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); /* Exported functions --------------------------------------------------------*/ @@ -183,8 +178,8 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ */ /** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization/de-initialization functions ##### @@ -215,12 +210,12 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv)); /* Set SDMMC configuration parameters */ - tmpreg |= (Init.ClockEdge |\ - Init.ClockPowerSave |\ - Init.BusWide |\ - Init.HardwareFlowControl |\ + tmpreg |= (Init.ClockEdge | \ + Init.ClockPowerSave | \ + Init.BusWide | \ + Init.HardwareFlowControl | \ Init.ClockDiv - ); + ); /* Write to SDMMC CLKCR */ MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); @@ -234,8 +229,8 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) */ /** @defgroup HAL_SDMMC_LL_Group2 IO operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### I/O operation functions ##### @@ -278,8 +273,8 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) */ /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions - * @brief management functions - * + * @brief management functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -367,9 +362,9 @@ HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef SDMMCx->ARG = Command->Argument; /* Set SDMMC command parameters */ - tmpreg |= (uint32_t)(Command->CmdIndex |\ - Command->Response |\ - Command->WaitForInterrupt |\ + tmpreg |= (uint32_t)(Command->CmdIndex | \ + Command->Response | \ + Command->WaitForInterrupt | \ Command->CPSM); /* Write to SDMMC CMD register */ @@ -421,7 +416,7 @@ uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) * that contains the configuration information for the SDMMC data. * @retval HAL status */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data) +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data) { uint32_t tmpreg = 0; @@ -439,9 +434,9 @@ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* SDMMCx->DLEN = Data->DataLength; /* Set the SDMMC data configuration parameters */ - tmpreg |= (uint32_t)(Data->DataBlockSize |\ - Data->TransferDir |\ - Data->TransferMode |\ + tmpreg |= (uint32_t)(Data->DataBlockSize | \ + Data->TransferDir | \ + Data->TransferMode | \ Data->DPSM); /* Write to SDMMC DCTRL */ @@ -497,8 +492,8 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM /** @defgroup HAL_SDMMC_LL_Group4 Command management functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### Commands management functions ##### @@ -511,7 +506,7 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM */ /** - * @brief Send the Data Block Lenght command and check the response + * @brief Send the Data Block Length command and check the response * @param SDMMCx: Pointer to SDMMC register base * @retval HAL status */ @@ -793,7 +788,7 @@ uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) * @param addr: Address of the card to be selected * @retval HAL status */ -uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) +uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; @@ -1039,6 +1034,31 @@ uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) return errorstate; } +/** + * @brief Send the Set Relative Address command to MMC card (not SD card). + * @param SDMMCx Pointer to SDMMC register base + * @param RCA Card RCA + * @retval HAL status + */ +uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD3 SD_CMD_SET_REL_ADDR */ + sdmmc_cmdinit.Argument = ((uint32_t)RCA << 16U); + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_REL_ADDR, SDMMC_CMDTIMEOUT); + + return errorstate; +} + /** * @brief Send the Status command and check the response. * @param SDMMCx: Pointer to SDMMC register base @@ -1112,7 +1132,7 @@ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) } /** - * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand + * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command * @param SDMMCx: Pointer to SDMMC register base * @parame Argument: Argument used for the command * @retval HAL status @@ -1181,61 +1201,43 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT); + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD, SDMMC_CMDTIMEOUT); return errorstate; } - /** * @} */ -/* Private function ----------------------------------------------------------*/ -/** @addtogroup SD_Private_Functions + +/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions + * @brief Responses functions + * +@verbatim + =============================================================================== + ##### Responses management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed responses. + +@endverbatim * @{ */ - -/** - * @brief Checks for error conditions for CMD0. - * @param hsd: SD handle - * @retval SD Card error state - */ -static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) -{ - /* 8 is the number of required instructions cycles for the below loop statement. - The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); - - do - { - if (count-- == 0U) - { - return SDMMC_ERROR_TIMEOUT; - } - - }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); - - /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); - - return SDMMC_ERROR_NONE; -} - /** * @brief Checks for error conditions for R1 response. * @param hsd: SD handle * @param SD_CMD: The sent command index * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout) +uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout) { uint32_t response_r1; uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The Timeout is expressed in ms */ - uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); + uint32_t count = Timeout * (SystemCoreClock / 8U / 1000U); do { @@ -1244,16 +1246,16 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ return SDMMC_ERROR_TIMEOUT; } sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_BUSYD0END)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT | + SDMMC_FLAG_BUSYD0END)) == 0U) || ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); return SDMMC_ERROR_CMD_RSP_TIMEOUT; } - else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); @@ -1268,7 +1270,7 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); /* Check response received is of desired command */ - if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) + if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) { return SDMMC_ERROR_CMD_CRC_FAIL; } @@ -1276,79 +1278,79 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ /* We have received response, retrieve it for analysis */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); - if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) + if ((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) { return SDMMC_ERROR_NONE; } - else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) + else if ((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) { return SDMMC_ERROR_ADDR_OUT_OF_RANGE; } - else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) + else if ((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) { return SDMMC_ERROR_ADDR_MISALIGNED; } - else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) + else if ((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) { return SDMMC_ERROR_BLOCK_LEN_ERR; } - else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) + else if ((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) { return SDMMC_ERROR_ERASE_SEQ_ERR; } - else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) + else if ((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) { return SDMMC_ERROR_BAD_ERASE_PARAM; } - else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) + else if ((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) { return SDMMC_ERROR_WRITE_PROT_VIOLATION; } - else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) + else if ((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) { return SDMMC_ERROR_LOCK_UNLOCK_FAILED; } - else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) + else if ((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) { return SDMMC_ERROR_COM_CRC_FAILED; } - else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) + else if ((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) { return SDMMC_ERROR_ILLEGAL_CMD; } - else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) + else if ((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) { return SDMMC_ERROR_CARD_ECC_FAILED; } - else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) + else if ((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) { return SDMMC_ERROR_CC_ERR; } - else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) + else if ((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) { return SDMMC_ERROR_STREAM_READ_UNDERRUN; } - else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) + else if ((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) { return SDMMC_ERROR_STREAM_WRITE_OVERRUN; } - else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) + else if ((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) { return SDMMC_ERROR_CID_CSD_OVERWRITE; } - else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) + else if ((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) { return SDMMC_ERROR_WP_ERASE_SKIP; } - else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) + else if ((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) { return SDMMC_ERROR_CARD_ECC_DISABLED; } - else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) + else if ((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) { return SDMMC_ERROR_ERASE_RESET; } - else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) + else if ((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) { return SDMMC_ERROR_AKE_SEQ_ERR; } @@ -1363,12 +1365,12 @@ static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_ * @param hsd: SD handle * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) { uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); do { @@ -1377,8 +1379,8 @@ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_TIMEOUT; } sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { @@ -1407,12 +1409,12 @@ static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) * @param hsd: SD handle * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) { uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); do { @@ -1421,10 +1423,10 @@ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_TIMEOUT; } sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); @@ -1447,14 +1449,14 @@ static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) * address RCA * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA) +uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA) { uint32_t response_r1; uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); do { @@ -1463,16 +1465,16 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ return SDMMC_ERROR_TIMEOUT; } sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); return SDMMC_ERROR_CMD_RSP_TIMEOUT; } - else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); @@ -1484,7 +1486,7 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ } /* Check response received is of desired command */ - if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) + if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) { return SDMMC_ERROR_CMD_CRC_FAIL; } @@ -1495,17 +1497,18 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ /* We have received response, retrieve it. */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); - if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) + if ((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | + SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) { - *pRCA = (uint16_t) (response_r1 >> 16); + *pRCA = (uint16_t)(response_r1 >> 16); return SDMMC_ERROR_NONE; } - else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) + else if ((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) { return SDMMC_ERROR_ILLEGAL_CMD; } - else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) + else if ((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) { return SDMMC_ERROR_COM_CRC_FAILED; } @@ -1520,12 +1523,12 @@ static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_ * @param hsd: SD handle * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) +uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) { uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); do { @@ -1534,10 +1537,10 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_TIMEOUT; } sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { /* Card is SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); @@ -1545,7 +1548,7 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_CMD_RSP_TIMEOUT; } - else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) { /* Card is SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); @@ -1557,7 +1560,7 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) /* Nothing to do */ } - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) { /* Card is SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); @@ -1567,6 +1570,41 @@ static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) } +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief Checks for error conditions for CMD0. + * @param hsd: SD handle + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + + } while (!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + return SDMMC_ERROR_NONE; +} + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.h index 8b91c6cbc3..fd210d3885 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_sdmmc.h @@ -22,7 +22,7 @@ #define STM32H7xx_LL_SDMMC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -63,10 +63,10 @@ typedef struct This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ #if (USE_SD_TRANSCEIVER != 0U) - uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Tranceiver/Switcher. - This parameter can be a value of @ref SDMMC_LL_TRANCEIVER_PRESENT */ + uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher. + This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */ #endif /* USE_SD_TRANSCEIVER */ -}SDMMC_InitTypeDef; +} SDMMC_InitTypeDef; /** @@ -92,7 +92,7 @@ typedef struct uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) is enabled or disabled. This parameter can be a value of @ref SDMMC_LL_CPSM_State */ -}SDMMC_CmdInitTypeDef; +} SDMMC_CmdInitTypeDef; /** @@ -117,7 +117,7 @@ typedef struct uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) is enabled or disabled. This parameter can be a value of @ref SDMMC_LL_DPSM_State */ -}SDMMC_DataInitTypeDef; +} SDMMC_DataInitTypeDef; /** * @} @@ -135,13 +135,13 @@ typedef struct #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ -#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the - number of transferred bytes does not match the block length */ +#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the */ + /*!< number of transferred bytes does not match the block length */ #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ -#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock - command or if there was an attempt to access a locked card */ +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock */ + /*!< command or if there was an attempt to access a locked card */ #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ @@ -152,8 +152,8 @@ typedef struct #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ -#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out - of erase sequence command was received */ +#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out */ + /*!< of erase sequence command was received */ #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ @@ -172,12 +172,12 @@ typedef struct #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ -#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its - operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its */ + /*!< operating condition register (OCR) content in the response on the CMD line. */ #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information - and asks the card whether card supports voltage. */ +#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information */ + /*!< and asks the card whether card supports voltage. */ #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ @@ -185,18 +185,18 @@ typedef struct #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ -#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands - (read, write, lock). Default block length is fixed to 512 Bytes. Not effective - for SDHS and SDXC. */ -#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by - STOP_TRANSMISSION command. */ +#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands */ + /*!< (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ +/*!< for SDHS and SDXC. */ +#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of */ + /*!< fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by */ + /*!< STOP_TRANSMISSION command. */ #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ -#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of */ + /*!< fixed 512 bytes in case of SDHC and SDXC. */ #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ @@ -205,32 +205,32 @@ typedef struct #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command - system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. - Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command */ + /*!< system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. */ + /*!< Reserved for each command system set by switch function command (CMD6). */ #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by - the SET_BLOCK_LEN command. */ -#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather - than a standard command. */ -#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card - for general purpose/application specific commands. */ +#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by */ + /*!< the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather */ + /*!< than a standard command. */ +#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card */ + /*!< for general purpose/application specific commands. */ #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ /** * @brief Following commands are SD Card Specific commands. * SDMMC_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus - widths are given in SCR register. */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus */ + /*!< widths are given in SCR register. */ #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ -#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with - 32bit+CRC data block. */ -#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to - send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with */ + /*!< 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to */ + /*!< send its operating condition register (OCR) content in the response on the CMD line. */ #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ @@ -370,11 +370,11 @@ typedef struct #define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U) #define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U) -#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ - ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ - ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ - ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ - ((MODE) == SDMMC_SPEED_MODE_DDR)) +#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \ + ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \ + ((MODE) == SDMMC_SPEED_MODE_HIGH) || \ + ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \ + ((MODE) == SDMMC_SPEED_MODE_DDR)) /** * @} @@ -401,7 +401,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Tranceiver Present +/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Transceiver Present * @{ */ #define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U) @@ -485,7 +485,7 @@ typedef struct * @} */ -/** @defgroup SDMMC_LL_Data_Length Data Lenght +/** @defgroup SDMMC_LL_Data_Length Data Length * @{ */ #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) @@ -503,14 +503,18 @@ typedef struct #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) -#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) +#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0| \ + SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) -#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0| \ + SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) -#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) -#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0| \ + SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1| \ + SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ @@ -642,21 +646,21 @@ typedef struct #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC -#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ - SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ - SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ - SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ - SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ - SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ - SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) +#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ + SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ + SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ + SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ + SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ + SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) -#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ - SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) +#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ + SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) -#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ - SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ - SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ - SDMMC_FLAG_IDMABTC)) +#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ + SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ + SDMMC_FLAG_IDMABTC)) /** * @} */ @@ -707,9 +711,9 @@ typedef struct */ /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ /** * @brief Enable the SDMMC device interrupt. @@ -1034,14 +1038,20 @@ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); /* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); /* SDMMC Cards mode management functions */ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); +/** + * @} + */ -/* SDMMC Commands management functions */ +/* SDMMC Commands management functions ******************************************/ +/** @addtogroup HAL_SDMMC_LL_Group4 + * @{ + */ uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); @@ -1053,7 +1063,7 @@ uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType); uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr); +uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr); uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); @@ -1063,13 +1073,26 @@ uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); +uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +/** + * @} + */ +/* SDMMC Responses management functions *****************************************/ +/** @addtogroup HAL_SDMMC_LL_Group5 + * @{ + */ +uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); +uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); +uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); /** * @} */ @@ -1087,7 +1110,7 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); * @} */ - /** +/** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.c index 44a95c1256..57f63a7cdd 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.c @@ -371,6 +371,12 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH); } + /* Checks to setup Internal SS signal to the active level in Slave Mode */ + if ((LL_SPI_GetNSSPolarity(SPIx) == LL_SPI_NSS_POLARITY_HIGH) && (tmp_nss == LL_SPI_NSS_SOFT) && (tmp_mode == LL_SPI_MODE_SLAVE)) + { + LL_SPI_SetInternalSSLevel(SPIx, LL_SPI_SS_LEVEL_HIGH); + } + /*---------------------------- SPIx CFG2 Configuration ------------------------ * Configure SPIx CFG2 with parameters: * - NSS management : SPI_CFG2_SSM, SPI_CFG2_SSOE bits @@ -656,7 +662,7 @@ ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) i2sdiv = tmp / 2UL; } - /* Test if the obtain values are forbiden or out of range */ + /* Test if the obtain values are forbidden or out of range */ if (((i2sodd == 1UL) && (i2sdiv == 1UL)) || (i2sdiv > 0xFFUL)) { /* Set the default values */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.h index e611b58d45..4dd1c2d92b 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_spi.h @@ -964,7 +964,7 @@ __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx) /** * @brief Check if there is an unfinished master transfer - * @rmtoll CR1 CSTART LL_SPI_IsMasterTransferActive + * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer * @param SPIx SPI Instance * @retval State of bit (1 or 0) */ @@ -1685,7 +1685,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx) } /** - * @brief Check that end of transfer event occured + * @brief Check that end of transfer event occurred * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT * @param SPIx SPI Instance * @retval State of bit (1 or 0). @@ -2818,7 +2818,7 @@ __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) /** * @brief Set I2S Channel Length Type - * @note This feature is usefull with SLAVE only + * @note This feature is useful with SLAVE only * @rmtoll I2SCFGR FIXCH LL_I2S_SetChannelLengthType * @param SPIx SPI Handle * @param ChannelLengthType This parameter can be one of the following values: @@ -2833,7 +2833,7 @@ __STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t Cha /** * @brief Get I2S Channel Length Type - * @note This feature is usefull with SLAVE only + * @note This feature is useful with SLAVE only * @rmtoll I2SCFGR FIXCH LL_I2S_GetChannelLengthType * @param SPIx SPI Handle * @retval Return value can be one of the following values: @@ -3247,7 +3247,7 @@ __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) } /** - * @brief Disable the Master Clock Ouput (Pin MCK) + * @brief Disable the Master Clock Output (Pin MCK) * @rmtoll I2SCFGR MCKOE LL_I2S_DisableMasterClock * @param SPIx SPI Handle * @retval None diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_system.h index df3fe3bd02..b4326b5d60 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_system.h @@ -135,7 +135,7 @@ extern "C" { * @{ */ #define LL_SYSCFG_ETH_MII 0x00000000U /*!< ETH Media MII interface */ -#define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL /*!< ETH Media RMII interface */ +#define LL_SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< ETH Media RMII interface */ /** * @} */ @@ -770,7 +770,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) * @brief Enable the Compensation Cell * @rmtoll CCCSR EN LL_SYSCFG_EnableCompensationCell * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. * @retval None */ __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) @@ -782,7 +782,7 @@ __STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) * @brief Disable the Compensation Cell * @rmtoll CCCSR EN LL_SYSCFG_DisableCompensationCell * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V + * voltage ranges from 1.62 to 2.0 V and from 2.7 to 3.6 V. * @retval None */ __STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) @@ -1917,6 +1917,7 @@ __STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void) #endif /* DUAL_CORE */ +#if defined(DBGMCU_CR_DBG_STOPD3) /** * @brief Enable D3 Domain/SRDomain debug during STOP mode * @rmtoll DBGMCU_CR DBGSTOP_D3/DBGSTOP_SRD LL_DBGMCU_EnableD3DebugInStopMode @@ -1936,7 +1937,9 @@ __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3); } +#endif /*DBGMCU_CR_DBG_STOPD3*/ +#if defined(DBGMCU_CR_DBG_STANDBYD3) /** * @brief Enable D3 Domain/SRDomain debug during STANDBY mode * @rmtoll DBGMCU_CR DBGSTBY_D3/DBGSTBY_SRD LL_DBGMCU_EnableD3DebugInStandbyMode @@ -1956,6 +1959,7 @@ __STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3); } +#endif /*DBGMCU_CR_DBG_STANDBYD3*/ /** * @brief Enable the trace port clock diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.h index 3bbdaa1912..4ec1297f69 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_tim.h @@ -565,8 +565,8 @@ typedef struct /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode * @{ */ -#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ -#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ @@ -1241,9 +1241,6 @@ typedef struct #define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /* !< TIM24 input 1 is connected to CAN TMP */ #define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /* !< TIM24 input 1 is connected to CAN RTP */ #define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */ -/** - * @} - */ #if defined(TIM_BREAK_INPUT_SUPPORT) /** Legacy definitions for compatibility purpose @@ -1564,7 +1561,16 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo */ __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) { - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; } /** @@ -2019,8 +2025,8 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); @@ -2064,8 +2070,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } @@ -2103,8 +2109,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint */ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } @@ -2137,7 +2143,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); } @@ -2169,7 +2175,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -2206,7 +2212,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann */ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); } @@ -2238,7 +2244,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); } @@ -2263,8 +2269,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2289,8 +2295,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2315,9 +2321,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2341,8 +2347,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha */ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2366,8 +2372,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2391,9 +2397,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2420,8 +2426,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2447,8 +2453,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2476,9 +2482,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2747,8 +2753,8 @@ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t G */ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), @@ -2775,8 +2781,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 */ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2799,8 +2805,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2825,8 +2831,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch */ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2850,8 +2856,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2888,8 +2894,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2925,8 +2931,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui */ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2954,7 +2960,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), ICPolarity << SHIFT_TAB_CCxP[iChannel]); } @@ -2982,7 +2988,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -3435,7 +3441,6 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u */ __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) { - MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource); } @@ -3695,7 +3700,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); SET_BIT(*pReg, Source); } @@ -3724,7 +3729,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B */ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); CLEAR_BIT(*pReg, Source); } @@ -3754,7 +3759,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity) { - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); } #endif /* TIM_BREAK_INPUT_SUPPORT */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.c index cd044ca5bd..2dc28f06bc 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.c @@ -66,9 +66,6 @@ /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) -/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ -#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) - #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ || ((__VALUE__) == LL_USART_DIRECTION_RX) \ || ((__VALUE__) == LL_USART_DIRECTION_TX) \ @@ -231,8 +228,9 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) /** * @brief Initialize USART registers according to the specified * parameters in USART_InitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). * @param USARTx USART Instance * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure @@ -283,7 +281,8 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /*---------------------------- USART CR3 Configuration --------------------- * Configure USARTx CR3 (Hardware Flow Control) with parameters: - * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value. + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to + * USART_InitStruct->HardwareFlowControl value. */ LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); @@ -356,9 +355,6 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* Check BRR is greater than or equal to 16d */ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); - - /* Check BRR is lower than or equal to 0xFFFF */ - assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); } /*---------------------------- USART PRESC Configuration ----------------------- @@ -395,13 +391,15 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) /** * @brief Initialize USART Clock related settings according to the * specified parameters in the USART_ClockInitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in USART configuration registers can only be written when + * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling + * this function. Otherwise, ERROR result will be returned. * @param USARTx USART Instance * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure * that contains the Clock configuration information for the specified USART peripheral. * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content + * - SUCCESS: USART registers related to Clock settings are initialized according + * to USART_ClockInitStruct content * - ERROR: Problem occurred during USART Registers initialization */ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) @@ -416,37 +414,25 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef CRx registers */ if (LL_USART_IsEnabled(USARTx) == 0U) { - /*---------------------------- USART CR2 Configuration -----------------------*/ - /* If Clock signal has to be output */ - if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) - { - /* Deactivate Clock signal delivery : - * - Disable Clock Output: USART_CR2_CLKEN cleared - */ - LL_USART_DisableSCLKOutput(USARTx); - } - else - { - /* Ensure USART instance is USART capable */ - assert_param(IS_USART_INSTANCE(USARTx)); + /* Ensure USART instance is USART capable */ + assert_param(IS_USART_INSTANCE(USARTx)); - /* Check clock related parameters */ - assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); - assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); - assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); + /* Check clock related parameters */ + assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); + assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); + assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); - /*---------------------------- USART CR2 Configuration ----------------------- - * Configure USARTx CR2 (Clock signal related bits) with parameters: - * - Enable Clock Output: USART_CR2_CLKEN set - * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value - * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value - * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. - */ - MODIFY_REG(USARTx->CR2, - USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, - USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | - USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); - } + /*---------------------------- USART CR2 Configuration ----------------------- + * Configure USARTx CR2 (Clock signal related bits) with parameters: + * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value + * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value + * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value + * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. + */ + MODIFY_REG(USARTx->CR2, + USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, + USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity | + USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); } /* Else (USART not in Disabled state => return ERROR */ else @@ -467,9 +453,12 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) { /* Set LL_USART_ClockInitStruct fields with default values */ USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; - USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = + LL_USART_CLOCK_DISABLE */ } /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.h index 7b4121e2c5..4a164ba3f1 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usart.h @@ -88,41 +88,49 @@ typedef struct uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. This parameter can be a value of @ref USART_LL_EC_PRESCALER. - This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetPrescaler().*/ uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. - This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. This parameter can be a value of @ref USART_LL_EC_STOPBITS. - This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ uint32_t Parity; /*!< Specifies the parity mode. This parameter can be a value of @ref USART_LL_EC_PARITY. - This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. This parameter can be a value of @ref USART_LL_EC_DIRECTION. - This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. This parameter can be a value of @ref USART_LL_EC_HWCONTROL. - This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. - This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ } LL_USART_InitTypeDef; @@ -141,20 +149,23 @@ typedef struct uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. This parameter can be a value of @ref USART_LL_EC_POLARITY. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). For more details, refer to description of this function. */ uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref USART_LL_EC_PHASE. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). For more details, refer to description of this function. */ uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). For more details, refer to description of this function. */ } LL_USART_ClockInitTypeDef; @@ -173,21 +184,21 @@ typedef struct * @brief Flags defines which can be used with LL_USART_WriteReg function * @{ */ -#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ -#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected flag */ -#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ -#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ -#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ -#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ -#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */ -#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */ -#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ -#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */ -#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */ -#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun Clear flag */ -#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ -#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ /** * @} */ @@ -357,18 +368,18 @@ typedef struct /** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler * @{ */ -#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */ -#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */ -#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */ -#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */ -#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */ -#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */ -#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */ -#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */ -#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */ -#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */ -#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */ -#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */ +#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ /** * @} */ @@ -563,8 +574,9 @@ typedef struct * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case */ -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ - + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) /** * @brief Compute USARTDIV value according to Peripheral Clock and @@ -586,8 +598,9 @@ typedef struct * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case */ -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ - + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) /** * @} @@ -785,7 +798,8 @@ __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos)); + MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | + (RXThreshold << USART_CR3_RXFTCFG_Pos)); } /** @@ -1870,6 +1884,10 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph { /* Do not overstep the size of USART_PRESCALER_TAB */ } + else if (BaudRate == 0U) + { + /* Can Not divide per 0 */ + } else if (OverSampling == LL_USART_OVERSAMPLING_8) { usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.c index 986ba4fc60..48940661ea 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.c @@ -61,8 +61,8 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); */ /** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization/de-initialization functions ##### @@ -96,7 +96,8 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; } - /* Reset after a PHY select */ + + /* Reset after a PHY select */ ret = USB_CoreReset(USBx); } else /* FS interface (embedded Phy) */ @@ -104,7 +105,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c /* Select FS Embedded PHY */ USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - /* Reset after a PHY select and set Host mode */ + /* Reset after a PHY select */ ret = USB_CoreReset(USBx); if (cfg.battery_charging_enable == 0U) @@ -121,6 +122,10 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c if (cfg.dma_enable == 1U) { + /* make sure to reserve 18 fifo Locations for DMA buffers */ + USBx->GDFIFOCFG &= ~(0xFFFFU << 16); + USBx->GDFIFOCFG |= 0x3EEU << 16; + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; } @@ -229,7 +234,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) * Disable the controller's Global Int in the AHB Config reg * @param USBx Selected device * @retval HAL status -*/ + */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) { USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; @@ -237,13 +242,12 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) } /** - * @brief USB_SetCurrentMode : Set functional mode + * @brief USB_SetCurrentMode Set functional mode * @param USBx Selected device - * @param mode current core mode + * @param mode current core mode * This parameter can be one of these values: - * @arg USB_DEVICE_MODE: Peripheral mode - * @arg USB_HOST_MODE: Host mode - * @arg USB_DRD_MODE: Dual Role Device mode + * @arg USB_DEVICE_MODE Peripheral mode + * @arg USB_HOST_MODE Host mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) @@ -268,7 +272,7 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTy } /** - * @brief USB_DevInit : Initializes the USB_OTG controller registers + * @brief USB_DevInit Initializes the USB_OTG controller registers * for device mode * @param USBx Selected device * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains @@ -442,8 +446,7 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { return HAL_TIMEOUT; } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); return HAL_OK; } @@ -465,8 +468,7 @@ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { return HAL_TIMEOUT; } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); return HAL_OK; } @@ -495,8 +497,8 @@ HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed) * @param USBx Selected device * @retval speed device speed * This parameter can be one of these values: - * @arg PCD_SPEED_HIGH: High speed mode - * @arg PCD_SPEED_FULL: Full speed mode + * @arg USBD_HS_SPEED: High speed mode + * @arg USBD_FS_SPEED: Full speed mode */ uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx) { @@ -935,10 +937,11 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe * 1 : DMA feature used * @retval HAL status */ -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t *pSrc = (uint32_t *)src; + uint8_t *pSrc = src; uint32_t count32b, i; if (dma == 0U) @@ -948,6 +951,9 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); pSrc++; + pSrc++; + pSrc++; + pSrc++; } } @@ -964,14 +970,34 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uin void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t *pDest = (uint32_t *)dest; + uint8_t *pDest = dest; + uint32_t pData; uint32_t i; - uint32_t count32b = ((uint32_t)len + 3U) / 4U; + uint32_t count32b = (uint32_t)len >> 2U; + uint16_t remaining_bytes = len % 4U; for (i = 0U; i < count32b; i++) { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); pDest++; + pDest++; + pDest++; + pDest++; + } + + /* When Number of data is not word aligned, read the remaining byte */ + if (remaining_bytes != 0U) + { + i = 0U; + __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); + + do + { + *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); + i++; + pDest++; + remaining_bytes--; + } while (remaining_bytes != 0U); } return ((void *)pDest); @@ -1095,7 +1121,7 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t addres } /** - * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down + * @brief USB_DevConnect : Connect the USB device by enabling Rpu * @param USBx Selected device * @retval HAL status */ @@ -1103,14 +1129,16 @@ HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; - HAL_Delay(3U); return HAL_OK; } /** - * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down + * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu * @param USBx Selected device * @retval HAL status */ @@ -1118,8 +1146,10 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; - HAL_Delay(3U); return HAL_OK; } @@ -1212,7 +1242,7 @@ uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) /** * @brief USB_ClearInterrupts: clear a USB interrupt * @param USBx Selected device - * @param interrupt interrupt flag + * @param interrupt flag * @retval None */ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) @@ -1304,8 +1334,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { return HAL_TIMEOUT; } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); /* Core Soft Reset */ count = 0U; @@ -1317,8 +1346,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { return HAL_TIMEOUT; } - } - while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); return HAL_OK; } @@ -1450,7 +1478,7 @@ HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq) } /** -* @brief USB_OTG_ResetPort : Reset Host Port + * @brief USB_OTG_ResetPort : Reset Host Port * @param USBx Selected device * @retval HAL status * @note (1)The application must wait at least 10 ms @@ -1479,10 +1507,10 @@ HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx) * @brief USB_DriveVbus : activate or de-activate vbus * @param state VBUS state * This parameter can be one of these values: - * 0 : VBUS Active - * 1 : VBUS Inactive + * 0 : Deactivate VBUS + * 1 : Activate VBUS * @retval HAL status -*/ + */ HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1526,7 +1554,7 @@ uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx) * @brief Return Host Current Frame number * @param USBx Selected device * @retval current frame number -*/ + */ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) { uint32_t USBx_BASE = (uint32_t)USBx; @@ -1555,20 +1583,17 @@ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx) * @arg EP_TYPE_BULK: Bulk type * @arg EP_TYPE_INTR: Interrupt type * @param mps Max Packet Size - * This parameter can be a value from 0 to32K + * This parameter can be a value from 0 to 32K * @retval HAL state */ -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, - uint8_t ch_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps) { HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t HCcharEpDir, HCcharLowSpeed; + uint32_t HostCoreSpeed; /* Clear old interrupt conditions for this host channel. */ USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; @@ -1593,7 +1618,8 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, { if ((USBx->CID & (0x1U << 8)) != 0U) { - USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM; } } break; @@ -1647,7 +1673,10 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, HCcharEpDir = 0U; } - if (speed == HPRT0_PRTSPD_LOW_SPEED) + HostCoreSpeed = USB_GetHostSpeed(USBx); + + /* LS device plugged to HUB */ + if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) { HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; } @@ -1683,7 +1712,7 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t ch_num = (uint32_t)hc->ch_num; - static __IO uint32_t tmpreg = 0U; + __IO uint32_t tmpreg; uint8_t is_oddframe; uint16_t len_words; uint16_t num_packets; @@ -1691,20 +1720,20 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED)) { + /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ + if ((dma == 1U) && ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK))) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NAKM); + } + if ((dma == 0U) && (hc->do_ping == 1U)) { (void)USB_DoPing(USBx, hc->ch_num); return HAL_OK; } - else if (dma == 1U) - { - USBx_HC(ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM); - hc->do_ping = 0U; - } - else - { - /* ... */ - } + } /* Compute the expected number of packets associated to the transfer */ @@ -1715,20 +1744,29 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe if (num_packets > max_hc_pkt_count) { num_packets = max_hc_pkt_count; - hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; } } else { num_packets = 1U; } + + /* + * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of + * max_packet size. + */ if (hc->ep_is_in != 0U) { - hc->xfer_len = (uint32_t)num_packets * hc->max_packet; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; } /* Initialize the HCTSIZn register */ - USBx_HC(ch_num)->HCTSIZ = (hc->xfer_len & USB_OTG_HCTSIZ_XFRSIZ) | + USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) | (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); @@ -1758,45 +1796,47 @@ HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDe tmpreg |= USB_OTG_HCCHAR_CHENA; USBx_HC(ch_num)->HCCHAR = tmpreg; - if (dma == 0U) /* Slave mode */ + if (dma != 0U) /* dma mode */ { - if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + return HAL_OK; + } + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U)) + { + switch (hc->ep_type) { - switch (hc->ep_type) - { - /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: - len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); - /* check if there is enough space in FIFO space */ - if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) - { - /* need to process data in nptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; - } - break; + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); - /* check if there is enough space in FIFO space */ - if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; - } - break; + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; - default: - break; - } - - /* Write packet into the Tx FIFO. */ - (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); + default: + break; } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); } return HAL_OK; @@ -1827,29 +1867,38 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) uint32_t hcnum = (uint32_t)hc_num; uint32_t count = 0U; uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; + + if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && + (ChannelEna == 0U)) + { + return HAL_OK; + } /* Check for space in the request queue to issue the halt. */ if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) { USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) { - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; - do + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) { - if (++count > 1000U) + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; + do { - break; - } + if (++count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } - while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - else - { - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; } } else @@ -1867,8 +1916,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { break; } - } - while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } else { @@ -1948,8 +1996,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) { break; } - } - while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); } /* Clear any pending Host interrupts */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.h index 8970cfba2f..5ee7cf7053 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_usb.h @@ -81,7 +81,7 @@ typedef enum } USB_OTG_HCStateTypeDef; /** - * @brief USB OTG Initialization Structure definition + * @brief USB Instance Initialization Structure definition */ typedef struct { @@ -94,14 +94,14 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed_ */ + This parameter can be any value of @ref USB_Core_Speed */ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY_ */ + This parameter can be any value of @ref USB_Core_PHY */ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ @@ -116,6 +116,7 @@ typedef struct uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + } USB_OTG_CfgTypeDef; typedef struct @@ -185,6 +186,8 @@ typedef struct uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + uint32_t XferSize; /*!< OTG Channel transfer size. */ + uint32_t xfer_len; /*!< Current transfer length. */ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ @@ -197,13 +200,13 @@ typedef struct uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ - uint32_t ErrCnt; /*!< Host channel error count.*/ + uint32_t ErrCnt; /*!< Host channel error count. */ USB_OTG_URBStateTypeDef urb_state; /*!< URB state. This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ USB_OTG_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ + This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ } USB_OTG_HCTypeDef; #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -313,10 +316,10 @@ typedef struct /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define DEP0CTL_MPS_64 0U -#define DEP0CTL_MPS_32 1U -#define DEP0CTL_MPS_16 2U -#define DEP0CTL_MPS_8 3U +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U /** * @} */ @@ -402,7 +405,7 @@ typedef struct #define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#define EP_ADDR_MSK 0xFU +#define EP_ADDR_MSK 0xFU /** * @} */ @@ -442,7 +445,9 @@ HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); +HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma); + void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); @@ -470,7 +475,9 @@ uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, uint8_t epnum, uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, + USB_OTG_HCTypeDef *hc, uint8_t dma); + uint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.c index a24c6be993..00c397507e 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_ll_utils.c @@ -272,7 +272,7 @@ static ErrorStatus UTILS_IsPLLsReady(void); * @note CPU_Frequency can be calculated thanks to RCC helper macro or function * @ref LL_RCC_GetSystemClocksFreq * LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency - * and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency. + * and __LL_RCC_CALC_HCLK_FREQ is used to calculate the CM4 clock frequency. * @retval None */ #else @@ -458,7 +458,7 @@ void LL_mDelay(uint32_t Delay) * @note CPU_Frequency can be calculated thanks to RCC helper macro or function * @ref LL_RCC_GetSystemClocksFreq * LL_RCC_GetSystemClocksFreq() is used to calculate the CM7 clock frequency - * and __LL_RCC_CALC_HCLK_FREQ is used to caluclate the CM4 clock frequency. + * and __LL_RCC_CALC_HCLK_FREQ is used to calculate the CM4 clock frequency. * @retval None */ #else diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h index 40a8485586..afcfc24210 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/stm32h7xx_hal_conf.h @@ -108,7 +108,7 @@ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -170,195 +170,195 @@ #define USE_SPI_CRC 1U /*!< use CRC in SPI */ #if !defined (USE_HAL_ADC_REGISTER_CALLBACKS) - #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ #endif #if !defined (USE_HAL_CEC_REGISTER_CALLBACKS) - #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ #endif #if !defined (USE_HAL_COMP_REGISTER_CALLBACKS) - #define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ #endif #if !defined (USE_HAL_CORDIC_REGISTER_CALLBACKS) - #define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */ +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */ #endif #if !defined (USE_HAL_CRYP_REGISTER_CALLBACKS) - #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ #endif #if !defined (USE_HAL_DAC_REGISTER_CALLBACKS) - #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ #endif #if !defined (USE_HAL_DCMI_REGISTER_CALLBACKS) - #define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ #endif #if !defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) - #define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ #endif #if !defined (USE_HAL_DMA2D_REGISTER_CALLBACKS) - #define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ #endif #if !defined (USE_HAL_DSI_REGISTER_CALLBACKS) - #define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ #endif #if !defined (USE_HAL_DTS_REGISTER_CALLBACKS) - #define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ #endif #if !defined (USE_HAL_ETH_REGISTER_CALLBACKS) - #define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ #endif #if !defined (USE_HAL_FDCAN_REGISTER_CALLBACKS) - #define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ #endif #if !defined (USE_HAL_FMAC_REGISTER_CALLBACKS) - #define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ #endif #if !defined (USE_HAL_NAND_REGISTER_CALLBACKS) - #define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ #endif #if !defined (USE_HAL_NOR_REGISTER_CALLBACKS) - #define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ #endif #if !defined (USE_HAL_SDRAM_REGISTER_CALLBACKS) - #define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ #endif #if !defined (USE_HAL_SRAM_REGISTER_CALLBACKS) - #define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ #endif #if !defined (USE_HAL_HASH_REGISTER_CALLBACKS) - #define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ #endif #if !defined (USE_HAL_HCD_REGISTER_CALLBACKS) - #define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ #endif #if !defined (USE_HAL_GFXMMU_REGISTER_CALLBACKS) - #define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ +#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ #endif #if !defined (USE_HAL_HRTIM_REGISTER_CALLBACKS) - #define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ +#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */ #endif #if !defined (USE_HAL_I2C_REGISTER_CALLBACKS) - #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ #endif #if !defined (USE_HAL_I2S_REGISTER_CALLBACKS) - #define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ #endif #if !defined (USE_HAL_IRDA_REGISTER_CALLBACKS) - #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ #endif #if !defined (USE_HAL_JPEG_REGISTER_CALLBACKS) - #define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ #endif #if !defined (USE_HAL_LPTIM_REGISTER_CALLBACKS) - #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ #endif #if !defined (USE_HAL_LTDC_REGISTER_CALLBACKS) - #define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ #endif #if !defined (USE_HAL_MDIOS_REGISTER_CALLBACKS) - #define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ #endif #if !defined (USE_HAL_MMC_REGISTER_CALLBACKS) - #define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ #endif #if !defined (USE_HAL_OPAMP_REGISTER_CALLBACKS) - #define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ #endif #if !defined (USE_HAL_OSPI_REGISTER_CALLBACKS) - #define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */ +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */ #endif #if !defined (USE_HAL_OTFDEC_REGISTER_CALLBACKS) - #define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ +#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ #endif #if !defined (USE_HAL_PCD_REGISTER_CALLBACKS) - #define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ #endif #if !defined (USE_HAL_QSPI_REGISTER_CALLBACKS) - #define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ #endif #if !defined (USE_HAL_RNG_REGISTER_CALLBACKS) - #define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ #endif #if !defined (USE_HAL_RTC_REGISTER_CALLBACKS) - #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ #endif #if !defined (USE_HAL_SAI_REGISTER_CALLBACKS) - #define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ #endif #if !defined (USE_HAL_SD_REGISTER_CALLBACKS) - #define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ #endif #if !defined (USE_HAL_SMARTCARD_REGISTER_CALLBACKS) - #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ #endif #if !defined (USE_HAL_SPDIFRX_REGISTER_CALLBACKS) - #define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ #endif #if !defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) - #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ #endif #if !defined (USE_HAL_SPI_REGISTER_CALLBACKS) - #define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ #endif #if !defined (USE_HAL_SWPMI_REGISTER_CALLBACKS) - #define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ +#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */ #endif #if !defined (USE_HAL_TIM_REGISTER_CALLBACKS) - #define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ #endif #if !defined (USE_HAL_UART_REGISTER_CALLBACKS) - #define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ #endif #if !defined (USE_HAL_USART_REGISTER_CALLBACKS) - #define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ #endif #if !defined (USE_HAL_WWDG_REGISTER_CALLBACKS) - #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ #endif /* ########################### Ethernet Configuration ######################### */ diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c index 325916047b..8e0017de2a 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_dualcore_boot_cm4_cm7.c @@ -141,7 +141,7 @@ * @param None * @retval None */ -void SystemInit (void) +__weak void SystemInit (void) { /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) @@ -351,7 +351,8 @@ void SystemCoreClockUpdate (void) break; default: - pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); break; } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; @@ -364,7 +365,7 @@ void SystemCoreClockUpdate (void) break; default: - common_system_clock = CSI_VALUE; + common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); break; } @@ -384,7 +385,7 @@ void SystemCoreClockUpdate (void) #endif /* DUAL_CORE && CORE_CM4 */ } -#endif /* DUAL_CORE */ +#endif /* DUAL_CORE */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_singlecore.c b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_singlecore.c index f2d2109457..69f4cea288 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_singlecore.c +++ b/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/system_stm32h7xx_singlecore.c @@ -49,6 +49,7 @@ #include "stm32h7xx.h" + #if !defined(DUAL_CORE) #include @@ -143,7 +144,7 @@ * @param None * @retval None */ -void SystemInit (void) +__weak void SystemInit (void) { #if defined (DATA_IN_D2_SRAM) __IO uint32_t tmpreg; @@ -355,7 +356,8 @@ void SystemCoreClockUpdate (void) break; default: - pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); break; } pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; @@ -368,7 +370,7 @@ void SystemCoreClockUpdate (void) break; default: - SystemCoreClock = CSI_VALUE; + SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); break; } @@ -390,7 +392,7 @@ void SystemCoreClockUpdate (void) #endif } -#endif /* not DUAL_CORE */ +#endif /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PeripheralPins.c index f74c5bcdbe..289f00870d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PeripheralPins.c @@ -1,33 +1,18 @@ /* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2018, STMicroelectronics + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2021 STMicroelectronics. * All rights reserved. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + ****************************************************************************** * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - * - * Automatically generated from STM32H743ZITx.xml + * Automatically generated from STM32CubeMX/db/mcu/STM32H743ZITx.xml */ #include "PeripheralPins.h" @@ -89,8 +74,8 @@ MBED_WEAK const PinMap PinMap_ADC[] = { {PC_1_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 // Connected to ETH_MDC {PC_1_ALT3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INN10 // Connected to ETH_MDC {PC_1_ALT4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 // Connected to ETH_MDC - {PC_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 - {PC_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 + {PC_2C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 + {PC_3C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 // Connected to ETH_RXD0 {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 // Connected to ETH_RXD0 {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INN4 // Connected to ETH_RXD1 @@ -164,6 +149,7 @@ MBED_WEAK const PinMap PinMap_I2C_SCL[] = { //*** PWM *** // TIM5 cannot be used because already used by the us_ticker +// (update us_ticker_data.h file if another timer is chosen) MBED_WEAK const PinMap PinMap_PWM[] = { {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 @@ -249,96 +235,96 @@ MBED_WEAK const PinMap PinMap_PWM[] = { //*** SERIAL *** MBED_WEAK const PinMap PinMap_UART_TX[] = { - {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_MDIO - {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_VBUS + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_MDIO + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_VBUS {PA_9_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to USB_OTG_FS_VBUS - {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to USB_OTG_FS_DP - {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to USB_OTG_FS_DP + {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, {PB_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, - {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ETH_TXD1 - {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // Connected to LD3 [Red Led] - {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX - {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to LD2 [Yellow Led] - {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, // Connected to ETH_TXD1 + {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, // Connected to LD3 [Red Led] + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_TX + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, // Connected to LD2 [Yellow Led] + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_RX[] = { - {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ETH_REF_CLK - {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, // Connected to USB_OTG_FS_SOF - {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to ETH_REF_CLK + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, // Connected to USB_OTG_FS_SOF + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, - {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to USB_OTG_FS_DM - {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, - {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, // Connected to USB_OTG_FS_DM + {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, - {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, - {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, - {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX - {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to STDIO_UART_RX + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_RTS[] = { - {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_REF_CLK - {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_DP + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to ETH_REF_CLK + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_DP {PA_12_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to USB_OTG_FS_DP - {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD3 [Red Led] - {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LD3 [Red Led] - {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, - {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD3 [Red Led] + {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LD3 [Red Led] + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_UART_CTS[] = { - {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_DM + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to USB_OTG_FS_DM {PA_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, // Connected to USB_OTG_FS_DM - {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LD1 [Green Led] - {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ETH_TXD1 - {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, - {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, - {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, - {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, - {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, - {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to ETH_TXD0 - {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // Connected to LD1 [Green Led] + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to ETH_TXD1 + {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, // Connected to ETH_TXD0 + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, {NC, NC, 0} }; @@ -353,7 +339,7 @@ MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { {PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to ETH_MDC - {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_3C, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, @@ -371,8 +357,8 @@ MBED_WEAK const PinMap PinMap_SPI_MISO[] = { {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PB_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, - {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LD3 [Red] - {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LD3 [Red Led] + {PC_2C, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, @@ -514,8 +500,8 @@ MBED_WEAK const PinMap PinMap_USB_HS[] = { {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D5 {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D6 // Connected to ETH_TXD1 {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_STP - {PC_2, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR - {PC_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT + {PC_2C, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR + {PC_3C, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT #endif /* MBED_CONF_TARGET_USB_SPEED */ {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h index fdf95bbc56..1fb109f69c 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/PinNames.h @@ -27,7 +27,7 @@ extern "C" { #endif -#define ALTC 0xF00 +#define DUAL_PAD 0xF00 typedef enum { ALT0 = 0x100, @@ -39,9 +39,7 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0C = PA_0 | ALTC, // dual pad PA_1 = 0x01, - PA_1C = PA_1 | ALTC, // dual pad PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW PA_2 = 0x02, PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW @@ -120,10 +118,10 @@ typedef enum { PC_1_ALT3 = PC_1 | ALT3, // same pin used for alternate HW PC_1_ALT4 = PC_1 | ALT4, // same pin used for alternate HW PC_2 = 0x22, - PC_2C = PC_2 | ALTC, // dual pad + PC_2C = PC_2 | DUAL_PAD, // dual pad PC_2C_ALT0 = PC_2C | ALT0, // same pin used for alternate HW PC_3 = 0x23, - PC_3C = PC_3 | ALTC, // dual pad + PC_3C = PC_3 | DUAL_PAD, // dual pad PC_4 = 0x24, PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW PC_5 = 0x25, @@ -230,9 +228,9 @@ typedef enum { // Arduino Uno (Rev3) pins ARDUINO_UNO_A0 = PA_3, ARDUINO_UNO_A1 = PC_0, - ARDUINO_UNO_A2 = PC_3, + ARDUINO_UNO_A2 = PC_3C, ARDUINO_UNO_A3 = PB_1, - ARDUINO_UNO_A4 = PC_2, + ARDUINO_UNO_A4 = PC_2C, ARDUINO_UNO_A5 = PF_10, ARDUINO_UNO_D0 = PB_7, @@ -416,8 +414,8 @@ typedef enum { } PinName; // Standardized LED and button names -#define LED1 PB_0 // LD1 -#define LED2 PE_1 // Yellow +#define LED1 PB_0 // LD1 [Green] +#define LED2 PE_1 // LD2 [Yellow] #define LED3 PB_14 // LD3 [Red] #define BUTTON1 PC_13 // USER_Btn [B1] diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h index ae90154283..1a6dccb193 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PinNames.h @@ -27,7 +27,7 @@ extern "C" { #endif -#define ALTC 0xF00 +#define DUAL_PAD 0xF00 typedef enum { ALT0 = 0x100, @@ -39,12 +39,12 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0C = PA_0 | ALTC, // dual pad + PA_0C = PA_0 | DUAL_PAD, // dual pad PA_0C_ALT0 = PA_0C | ALT0, // same pin used for alternate HW PA_0C_ALT1 = PA_0C | ALT1, // same pin used for alternate HW PA_0C_ALT2 = PA_0C | ALT2, // same pin used for alternate HW PA_1 = 0x01, - PA_1C = PA_1 | ALTC, // dual pad + PA_1C = PA_1 | DUAL_PAD, // dual pad PA_1C_ALT0 = PA_1C | ALT0, // same pin used for alternate HW PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW PA_2 = 0x02, @@ -124,7 +124,7 @@ typedef enum { PC_1_ALT3 = PC_1 | ALT3, // same pin used for alternate HW PC_1_ALT4 = PC_1 | ALT4, // same pin used for alternate HW PC_2 = 0x22, - PC_2C = PC_2 | ALTC, // dual pad + PC_2C = PC_2 | DUAL_PAD, // dual pad PC_2C_ALT0 = PC_2C | ALT0, // same pin used for alternate HW PC_2_ALT0 = PC_2 | ALT0, // same pin used for alternate HW PC_2_ALT1 = PC_2 | ALT1, // same pin used for alternate HW @@ -132,7 +132,7 @@ typedef enum { PC_2_ALT3 = PC_2 | ALT3, // same pin used for alternate HW PC_2_ALT4 = PC_2 | ALT4, // same pin used for alternate HW PC_3 = 0x23, - PC_3C = PC_3 | ALTC, // dual pad + PC_3C = PC_3 | DUAL_PAD, // dual pad PC_3_ALT0 = PC_3 | ALT0, // same pin used for alternate HW PC_3_ALT1 = PC_3 | ALT1, // same pin used for alternate HW PC_3_ALT2 = PC_3 | ALT2, // same pin used for alternate HW diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h index 220284ae17..585fb0ea8f 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h @@ -43,7 +43,7 @@ extern "C" { #endif -#define ALTC 0xF00 +#define DUAL_PAD 0xF00 typedef enum { ALT0 = 0x100, @@ -55,12 +55,12 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0C = PA_0 | ALTC, // dual pad + PA_0C = PA_0 | DUAL_PAD, // dual pad PA_0C_ALT0 = PA_0C | ALT0, // same pin used for alternate HW PA_0C_ALT1 = PA_0C | ALT1, // same pin used for alternate HW PA_0C_ALT2 = PA_0C | ALT2, // same pin used for alternate HW PA_1 = 0x01, - PA_1C = PA_1 | ALTC, // dual pad + PA_1C = PA_1 | DUAL_PAD, // dual pad PA_1C_ALT0 = PA_1C | ALT0, // same pin used for alternate HW PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW PA_2 = 0x02, @@ -140,7 +140,7 @@ typedef enum { PC_1_ALT3 = PC_1 | ALT3, // same pin used for alternate HW PC_1_ALT4 = PC_1 | ALT4, // same pin used for alternate HW PC_2 = 0x22, - PC_2C = PC_2 | ALTC, // dual pad + PC_2C = PC_2 | DUAL_PAD, // dual pad PC_2C_ALT0 = PC_2C | ALT0, // same pin used for alternate HW PC_2_ALT0 = PC_2 | ALT0, // same pin used for alternate HW PC_2_ALT1 = PC_2 | ALT1, // same pin used for alternate HW @@ -148,7 +148,7 @@ typedef enum { PC_2_ALT3 = PC_2 | ALT3, // same pin used for alternate HW PC_2_ALT4 = PC_2 | ALT4, // same pin used for alternate HW PC_3 = 0x23, - PC_3C = PC_3 | ALTC, // dual pad + PC_3C = PC_3 | DUAL_PAD, // dual pad PC_3_ALT0 = PC_3 | ALT0, // same pin used for alternate HW PC_3_ALT1 = PC_3 | ALT1, // same pin used for alternate HW PC_3_ALT2 = PC_3 | ALT2, // same pin used for alternate HW diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp index 0d430bfc95..13ba1042de 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp @@ -26,27 +26,27 @@ ******************************************************************************/ void enableEthPowerSupply(void) { - /* Ensure ETH power supply */ - mbed::I2C i2c(PB_7, PB_6); - - char data[2]; + /* Ensure ETH power supply */ + mbed::I2C i2c(PB_7, PB_6); - // LDO3 to 1.2V - data[0]=0x52; - data[1]=0x9; - i2c.write(8 << 1, data, sizeof(data)); - data[0]=0x53; - data[1]=0xF; - i2c.write(8 << 1, data, sizeof(data)); - - // SW2 to 3.3V (SW2_VOLT) - data[0]=0x3B; - data[1]=0xF; - i2c.write(8 << 1, data, sizeof(data)); + char data[2]; + + // LDO3 to 1.2V + data[0] = 0x52; + data[1] = 0x9; + i2c.write(8 << 1, data, sizeof(data)); + data[0] = 0x53; + data[1] = 0xF; + i2c.write(8 << 1, data, sizeof(data)); + + // SW2 to 3.3V (SW2_VOLT) + data[0] = 0x3B; + data[1] = 0xF; + i2c.write(8 << 1, data, sizeof(data)); + + // SW1 to 3.0V (SW1_VOLT) + data[0] = 0x35; + data[1] = 0xF; + i2c.write(8 << 1, data, sizeof(data)); - // SW1 to 3.0V (SW1_VOLT) - data[0]=0x35; - data[1]=0xF; - i2c.write(8 << 1, data, sizeof(data)); - } diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c index 3b2a530462..ae7821ede0 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c @@ -68,9 +68,9 @@ uint8_t SetSysClock_PLL_HSI(void); void SetSysClock(void) { - bool lowspeed = false; + bool lowspeed = false; #if defined(LOWSPEED) && (LOWSPEED == 1) - lowspeed = true; + lowspeed = true; #endif #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) @@ -95,17 +95,19 @@ void SetSysClock(void) } static const uint32_t _keep; -bool isBootloader() { - return ((uint32_t)&_keep < 0x8040000); +bool isBootloader() +{ + return ((uint32_t)&_keep < 0x8040000); } -bool isBetaBoard() { - uint8_t* bootloader_data = (uint8_t*)(0x801F000); - if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) { - return true; - } else { - return (bootloader_data[10] == 27); - } +bool isBetaBoard() +{ + uint8_t *bootloader_data = (uint8_t *)(0x801F000); + if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) { + return true; + } else { + return (bootloader_data[10] == 27); + } } #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) @@ -118,14 +120,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed) RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - // If we are reconfiguring the clock, select CSI as system clock source to allow modification of the PLL configuration + // If we are reconfiguring the clock, select CSI as system clock source to allow modification of the PLL configuration if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) { - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) - { - return 0; - } + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + return 0; + } } /* Enable oscillator pin */ @@ -148,9 +149,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed) /* Configure the main internal regulator output voltage */ if (lowspeed) { - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); } else { - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); } while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} @@ -167,17 +168,17 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed) RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = 5; if (lowspeed) { - RCC_OscInitStruct.PLL.PLLN = 40; + RCC_OscInitStruct.PLL.PLLN = 40; } else { - RCC_OscInitStruct.PLL.PLLN = 160; + RCC_OscInitStruct.PLL.PLLN = 160; } #if HSE_VALUE == 27000000 RCC_OscInitStruct.PLL.PLLM = 9; if (lowspeed) { - RCC_OscInitStruct.PLL.PLLN = 80; + RCC_OscInitStruct.PLL.PLLN = 80; } else { - RCC_OscInitStruct.PLL.PLLN = 300; + RCC_OscInitStruct.PLL.PLLN = 300; } #endif @@ -203,11 +204,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed) RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; if (lowspeed) { - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) - return 0; // FAIL + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) { + return 0; // FAIL + } } else { - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) - return 0; // FAIL + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } } // HAL_RCCEx_EnableBootCore(RCC_BOOT_C2); @@ -294,13 +297,13 @@ uint8_t SetSysClock_PLL_HSI(void) #if defined (CORE_CM4) void HSEM2_IRQHandler(void) { - HAL_HSEM_IRQHandler(); + HAL_HSEM_IRQHandler(); } #endif #if defined (CORE_CM7) void HSEM1_IRQHandler(void) { - HAL_HSEM_IRQHandler(); + HAL_HSEM_IRQHandler(); } #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PeripheralPins.c index b3ace7ef7a..5d48f57d75 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PeripheralPins.c @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2016-2020 STMicroelectronics. + * Copyright (c) 2016-2021 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -326,6 +326,7 @@ MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { {PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_3C, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, @@ -344,6 +345,7 @@ MBED_WEAK const PinMap PinMap_SPI_MISO[] = { {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PB_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to LD3 (Red Led) + {PC_2C, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, @@ -418,6 +420,7 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = { MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { {PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {PC_3C, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 @@ -434,6 +437,7 @@ MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { {PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 + {PC_2C, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 {NC, NC, 0} @@ -468,6 +472,7 @@ MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { MBED_WEAK const PinMap PinMap_OSPI_DATA0[] = { {PB_1, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 + {PC_3C, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 {PC_9, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 {PD_11, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 {PF_8, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 @@ -484,6 +489,7 @@ MBED_WEAK const PinMap PinMap_OSPI_DATA1[] = { MBED_WEAK const PinMap PinMap_OSPI_DATA2[] = { {PA_7, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 + {PC_2C, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 {PE_2, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 {PF_7, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 {NC, NC, 0} @@ -505,12 +511,14 @@ MBED_WEAK const PinMap PinMap_OSPI_DATA4[] = { }; MBED_WEAK const PinMap PinMap_OSPI_DATA5[] = { + {PC_2C, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO5 {PD_5, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO5 {PE_8, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO5 {NC, NC, 0} }; MBED_WEAK const PinMap PinMap_OSPI_DATA6[] = { + {PC_3C, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO6 {PD_6, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO6 {PE_9, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO6 {PG_9, OSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO6 @@ -571,6 +579,8 @@ MBED_WEAK const PinMap PinMap_USB_HS[] = { {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_D5 {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_D6 {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_STP + {PC_2C, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_DIR + {PC_3C, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_HS)}, // USB_OTG_HS_ULPI_NXT #endif /* MBED_CONF_TARGET_USB_SPEED */ {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h index 5712c3b152..94ccfc23fa 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TARGET_NUCLEO_H7A3ZI_Q/PinNames.h @@ -27,7 +27,7 @@ extern "C" { #endif -#define ALTC 0xF00 +#define DUAL_PAD 0xF00 typedef enum { ALT0 = 0x100, @@ -37,9 +37,7 @@ typedef enum { typedef enum { PA_0 = 0x00, - PA_0C = PA_0 | ALTC, // dual pad PA_1 = 0x01, - PA_1C = PA_1 | ALTC, // dual pad PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW PA_2 = 0x02, PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW @@ -113,10 +111,10 @@ typedef enum { PC_1_ALT1 = PC_1 | ALT1, // same pin used for alternate HW PC_1_ALT2 = PC_1 | ALT2, // same pin used for alternate HW PC_2 = 0x22, - PC_2C = PC_2 | ALTC, // dual pad + PC_2C = PC_2 | DUAL_PAD, // dual pad PC_2C_ALT0 = PC_2C | ALT0, // same pin used for alternate HW PC_3 = 0x23, - PC_3C = PC_3 | ALTC, // dual pad + PC_3C = PC_3 | DUAL_PAD, // dual pad PC_4 = 0x24, PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW PC_5 = 0x25, diff --git a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c index 7d9ec34e8a..3fb41a7997 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c @@ -77,21 +77,6 @@ void analogin_init(analogin_t *obj, PinName pin) MBED_ASSERT(obj->handle.Instance != (ADC_TypeDef *)NC); MBED_ASSERT(function != (uint32_t)NC); -#if defined(ALTC) - if (pin == PA_0C) { - HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PA0, SYSCFG_SWITCH_PA0_OPEN); - } - if (pin == PA_1C) { - HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PA1, SYSCFG_SWITCH_PA1_OPEN); - } - if (pin == PC_2C) { - HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_OPEN); - } - if (pin == PC_3C) { - HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_OPEN); - } -#endif /* ALTC */ - obj->channel = STM_PIN_CHANNEL(function); obj->differential = STM_PIN_INVERTED(function); diff --git a/targets/TARGET_STM/TARGET_STM32H7/flash_api.c b/targets/TARGET_STM/TARGET_STM32H7/flash_api.c index 179f9e3b05..984c183c67 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32H7/flash_api.c @@ -148,6 +148,8 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, #if defined(CORE_CM7) SCB_CleanInvalidateDCache_by_Addr((uint32_t *)StartAddress, FullSize); SCB_InvalidateICache(); +#else /* CORE_CM4 */ + __HAL_ART_ENABLE(); #endif /* CORE_CM7 */ #else /* DUAL_CORE */ SCB_CleanInvalidateDCache_by_Addr((uint32_t *)StartAddress, FullSize); diff --git a/targets/TARGET_STM/TARGET_STM32H7/i2c_device.c b/targets/TARGET_STM/TARGET_STM32H7/i2c_device.c old mode 100644 new mode 100755 index b1a9e8b182..ae3f562357 --- a/targets/TARGET_STM/TARGET_STM32H7/i2c_device.c +++ b/targets/TARGET_STM/TARGET_STM32H7/i2c_device.c @@ -2,8 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2015-2020 STMicroelectronics. - * Copyright (c) 2020, Arduino SA. + * Copyright (c) 2021 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -19,313 +18,20 @@ #include "mbed_error.h" #include "stm32h7xx_ll_rcc.h" +/* Define I2C Device */ #if DEVICE_I2C -/** @defgroup I2C_DEVICE_Private_Constants I2C_DEVICE Private Constants - * @{ - */ -#ifndef I2C_VALID_TIMING_NBR -#define I2C_VALID_TIMING_NBR 128U -#endif -#define I2C_SPEED_FREQ_STANDARD 0U /* 100 kHz */ -#define I2C_SPEED_FREQ_FAST 1U /* 400 kHz */ -#define I2C_SPEED_FREQ_FAST_PLUS 2U /* 1 MHz */ -#define I2C_ANALOG_FILTER_DELAY_MIN 50U /* ns */ -#define I2C_ANALOG_FILTER_DELAY_MAX 260U /* ns */ -#define I2C_USE_ANALOG_FILTER 1U -#define I2C_DIGITAL_FILTER_COEF 0U -#define I2C_PRESC_MAX 16U -#define I2C_SCLDEL_MAX 16U -#define I2C_SDADEL_MAX 16U -#define I2C_SCLH_MAX 256U -#define I2C_SCLL_MAX 256U -#define SEC2NSEC 1000000000UL -/** - * @} - */ - -/** @defgroup I2C_DEVICE_Private_Types I2C_DEVICE Private Types - * @{ - */ -typedef struct { - uint32_t freq; /* Frequency in Hz */ - uint32_t freq_min; /* Minimum frequency in Hz */ - uint32_t freq_max; /* Maximum frequency in Hz */ - uint32_t hddat_min; /* Minimum data hold time in ns */ - uint32_t vddat_max; /* Maximum data valid time in ns */ - uint32_t sudat_min; /* Minimum data setup time in ns */ - uint32_t lscl_min; /* Minimum low period of the SCL clock in ns */ - uint32_t hscl_min; /* Minimum high period of SCL clock in ns */ - uint32_t trise; /* Rise time in ns */ - uint32_t tfall; /* Fall time in ns */ - uint32_t dnf; /* Digital noise filter coefficient */ -} I2C_Charac_t; - -typedef struct { - uint32_t presc; /* Timing prescaler */ - uint32_t tscldel; /* SCL delay */ - uint32_t tsdadel; /* SDA delay */ - uint32_t sclh; /* SCL high period */ - uint32_t scll; /* SCL low period */ -} I2C_Timings_t; -/** - * @} - */ - -/** @defgroup I2C_DEVICE_Private_Constants I2C_DEVICE Private Constants - * @{ - */ -static const I2C_Charac_t I2C_Charac[] = { - [I2C_SPEED_FREQ_STANDARD] = - { - .freq = 100000, - .freq_min = 80000, - .freq_max = 120000, - .hddat_min = 0, - .vddat_max = 3450, - .sudat_min = 250, - .lscl_min = 4700, - .hscl_min = 4000, - .trise = 640, - .tfall = 20, - .dnf = I2C_DIGITAL_FILTER_COEF, - }, - [I2C_SPEED_FREQ_FAST] = - { - .freq = 400000, - .freq_min = 320000, - .freq_max = 480000, - .hddat_min = 0, - .vddat_max = 900, - .sudat_min = 100, - .lscl_min = 1300, - .hscl_min = 600, - .trise = 250, - .tfall = 100, - .dnf = I2C_DIGITAL_FILTER_COEF, - }, - [I2C_SPEED_FREQ_FAST_PLUS] = - { - .freq = 1000000, - .freq_min = 800000, - .freq_max = 1200000, - .hddat_min = 0, - .vddat_max = 450, - .sudat_min = 50, - .lscl_min = 500, - .hscl_min = 260, - .trise = 60, - .tfall = 100, - .dnf = I2C_DIGITAL_FILTER_COEF, - }, -}; -/** - * @} - */ - -/** @defgroup I2C_DEVICE_Private_Variables I2C_DEVICE Private Variables -* @{ -*/ -static I2C_Timings_t I2c_valid_timing[I2C_VALID_TIMING_NBR]; -static uint32_t I2c_valid_timing_nbr = 0; -/** - * @} - */ - -/** @defgroup I2C_DEVICE_Private_Functions I2C_DEVICE Private Functions - * @{ - */ -/** - * @brief Compute PRESC, SCLDEL and SDADEL. - * @param clock_src_freq I2C source clock in HZ. - * @param I2C_speed I2C frequency (index). - * @retval None. - */ -static void I2C_Compute_PRESC_SCLDEL_SDADEL(uint32_t clock_src_freq, uint32_t I2C_speed) -{ - uint32_t prev_presc = I2C_PRESC_MAX; - uint32_t ti2cclk; - int32_t tsdadel_min, tsdadel_max; - int32_t tscldel_min; - uint32_t presc, scldel, sdadel; - uint32_t tafdel_min, tafdel_max; - - ti2cclk = (SEC2NSEC + (clock_src_freq / 2U)) / clock_src_freq; - - tafdel_min = (I2C_USE_ANALOG_FILTER == 1U) ? I2C_ANALOG_FILTER_DELAY_MIN : 0U; - tafdel_max = (I2C_USE_ANALOG_FILTER == 1U) ? I2C_ANALOG_FILTER_DELAY_MAX : 0U; - - /* tDNF = DNF x tI2CCLK - tPRESC = (PRESC+1) x tI2CCLK - SDADEL >= {tf +tHD;DAT(min) - tAF(min) - tDNF - [3 x tI2CCLK]} / {tPRESC} - SDADEL <= {tVD;DAT(max) - tr - tAF(max) - tDNF- [4 x tI2CCLK]} / {tPRESC} */ - - tsdadel_min = (int32_t)I2C_Charac[I2C_speed].tfall + (int32_t)I2C_Charac[I2C_speed].hddat_min - - (int32_t)tafdel_min - (int32_t)(((int32_t)I2C_Charac[I2C_speed].dnf + 3) * (int32_t)ti2cclk); - - tsdadel_max = (int32_t)I2C_Charac[I2C_speed].vddat_max - (int32_t)I2C_Charac[I2C_speed].trise - - (int32_t)tafdel_max - (int32_t)(((int32_t)I2C_Charac[I2C_speed].dnf + 4) * (int32_t)ti2cclk); - - - /* {[tr+ tSU;DAT(min)] / [tPRESC]} - 1 <= SCLDEL */ - tscldel_min = (int32_t)I2C_Charac[I2C_speed].trise + (int32_t)I2C_Charac[I2C_speed].sudat_min; - - if (tsdadel_min <= 0) { - tsdadel_min = 0; - } - - if (tsdadel_max <= 0) { - tsdadel_max = 0; - } - - for (presc = 0; presc < I2C_PRESC_MAX; presc++) { - for (scldel = 0; scldel < I2C_SCLDEL_MAX; scldel++) { - /* TSCLDEL = (SCLDEL+1) * (PRESC+1) * TI2CCLK */ - uint32_t tscldel = (scldel + 1U) * (presc + 1U) * ti2cclk; - - if (tscldel >= (uint32_t)tscldel_min) { - for (sdadel = 0; sdadel < I2C_SDADEL_MAX; sdadel++) { - /* TSDADEL = SDADEL * (PRESC+1) * TI2CCLK */ - uint32_t tsdadel = (sdadel * (presc + 1U)) * ti2cclk; - - if ((tsdadel >= (uint32_t)tsdadel_min) && (tsdadel <= (uint32_t)tsdadel_max)) { - if (presc != prev_presc) { - I2c_valid_timing[I2c_valid_timing_nbr].presc = presc; - I2c_valid_timing[I2c_valid_timing_nbr].tscldel = scldel; - I2c_valid_timing[I2c_valid_timing_nbr].tsdadel = sdadel; - prev_presc = presc; - I2c_valid_timing_nbr ++; - - if (I2c_valid_timing_nbr >= I2C_VALID_TIMING_NBR) { - return; - } - } - } - } - } - } - } -} - -/** - * @brief Calculate SCLL and SCLH and find best configuration. - * @param clock_src_freq I2C source clock in HZ. - * @param I2C_speed I2C frequency (index). - * @retval config index (0 to I2C_VALID_TIMING_NBR], 0xFFFFFFFF for no valid config. - */ -static uint32_t I2C_Compute_SCLL_SCLH(uint32_t clock_src_freq, uint32_t I2C_speed) -{ - uint32_t ret = 0xFFFFFFFFU; - uint32_t ti2cclk; - uint32_t ti2cspeed; - uint32_t prev_error; - uint32_t dnf_delay; - uint32_t clk_min, clk_max; - uint32_t scll, sclh; - uint32_t tafdel_min; - - ti2cclk = (SEC2NSEC + (clock_src_freq / 2U)) / clock_src_freq; - ti2cspeed = (SEC2NSEC + (I2C_Charac[I2C_speed].freq / 2U)) / I2C_Charac[I2C_speed].freq; - - tafdel_min = (I2C_USE_ANALOG_FILTER == 1U) ? I2C_ANALOG_FILTER_DELAY_MIN : 0U; - - /* tDNF = DNF x tI2CCLK */ - dnf_delay = I2C_Charac[I2C_speed].dnf * ti2cclk; - - clk_max = SEC2NSEC / I2C_Charac[I2C_speed].freq_min; - clk_min = SEC2NSEC / I2C_Charac[I2C_speed].freq_max; - - prev_error = ti2cspeed; - - for (uint32_t count = 0; count < I2c_valid_timing_nbr; count++) { - /* tPRESC = (PRESC+1) x tI2CCLK*/ - uint32_t tpresc = (I2c_valid_timing[count].presc + 1U) * ti2cclk; - - for (scll = 0; scll < I2C_SCLL_MAX; scll++) { - /* tLOW(min) <= tAF(min) + tDNF + 2 x tI2CCLK + [(SCLL+1) x tPRESC ] */ - uint32_t tscl_l = tafdel_min + dnf_delay + (2U * ti2cclk) + ((scll + 1U) * tpresc); - - - /* The I2CCLK period tI2CCLK must respect the following conditions: - tI2CCLK < (tLOW - tfilters) / 4 and tI2CCLK < tHIGH */ - if ((tscl_l > I2C_Charac[I2C_speed].lscl_min) && (ti2cclk < ((tscl_l - tafdel_min - dnf_delay) / 4U))) { - for (sclh = 0; sclh < I2C_SCLH_MAX; sclh++) { - /* tHIGH(min) <= tAF(min) + tDNF + 2 x tI2CCLK + [(SCLH+1) x tPRESC] */ - uint32_t tscl_h = tafdel_min + dnf_delay + (2U * ti2cclk) + ((sclh + 1U) * tpresc); - - /* tSCL = tf + tLOW + tr + tHIGH */ - uint32_t tscl = tscl_l + tscl_h + I2C_Charac[I2C_speed].trise + I2C_Charac[I2C_speed].tfall; - - if ((tscl >= clk_min) && (tscl <= clk_max) && (tscl_h >= I2C_Charac[I2C_speed].hscl_min) && (ti2cclk < tscl_h)) { - int32_t error = (int32_t)tscl - (int32_t)ti2cspeed; - - if (error < 0) { - error = -error; - } - - /* look for the timings with the lowest clock error */ - if ((uint32_t)error < prev_error) { - prev_error = (uint32_t)error; - I2c_valid_timing[count].scll = scll; - I2c_valid_timing[count].sclh = sclh; - ret = count; - } - } - } - } - } - } - - return ret; -} - -/** - * @brief Compute I2C timing according current I2C clock source and required I2C clock. - * @param clock_src_freq I2C clock source in Hz. - * @param i2c_freq Required I2C clock in Hz. - * @retval I2C timing or 0 in case of error. - */ -static uint32_t I2C_ComputeTiming(uint32_t clock_src_freq, uint32_t i2c_freq) -{ - uint32_t ret = 0; - uint32_t speed; - uint32_t idx; - - - if ((clock_src_freq != 0U) && (i2c_freq != 0U)) { - for (speed = 0 ; speed <= (uint32_t)I2C_SPEED_FREQ_FAST_PLUS ; speed++) { - if ((i2c_freq >= I2C_Charac[speed].freq_min) && - (i2c_freq <= I2C_Charac[speed].freq_max)) { - I2C_Compute_PRESC_SCLDEL_SDADEL(clock_src_freq, speed); - idx = I2C_Compute_SCLL_SCLH(clock_src_freq, speed); - - if (idx < I2C_VALID_TIMING_NBR) { - ret = ((I2c_valid_timing[idx].presc & 0x0FU) << 28) | \ - ((I2c_valid_timing[idx].tscldel & 0x0FU) << 20) | \ - ((I2c_valid_timing[idx].tsdadel & 0x0FU) << 16) | \ - ((I2c_valid_timing[idx].sclh & 0xFFU) << 8) | \ - ((I2c_valid_timing[idx].scll & 0xFFU) << 0); - } - break; - } - } - } - - return ret; -} - /** * @brief Get I2C clock source frequency according I2C instance used. * @param i2c I2C instance name. * @retval I2C clock source frequency in Hz. */ -static uint32_t I2C_GetPclk(I2CName i2c) +uint32_t i2c_get_pclk(I2CName i2c) { uint32_t clocksource; uint32_t pclk = 0; PLL3_ClocksTypeDef pll3_clocks; - - if (i2c == I2C_1 || i2c == I2C_2 || i2c == I2C_3) { + if ((i2c == I2C_1) || (i2c == I2C_2) || (i2c == I2C_3)) { clocksource = __HAL_RCC_GET_I2C123_SOURCE(); switch (clocksource) { case RCC_I2C123CLKSOURCE_D2PCLK1: @@ -346,7 +52,9 @@ static uint32_t I2C_GetPclk(I2CName i2c) error("I2C123: Invalid clock source"); break; } - } else if (i2c == I2C_4) { + } +#if defined I2C4_BASE + else if (i2c == I2C_4) { clocksource = __HAL_RCC_GET_I2C4_SOURCE(); switch (clocksource) { case RCC_I2C4CLKSOURCE_D3PCLK1: @@ -367,11 +75,12 @@ static uint32_t I2C_GetPclk(I2CName i2c) error("I2C4: Invalid clock source"); break; } - } else { + } +#endif + else { // should not happend error("I2C: unknown instance"); } - return pclk; } /** @@ -386,17 +95,35 @@ static uint32_t I2C_GetPclk(I2CName i2c) * @param hz Required I2C clock in Hz. * @retval I2C timing or 0 in case of error. */ -uint32_t get_i2c_timing(I2CName i2c, int hz) +uint32_t i2c_get_timing(I2CName i2c, int hz) { uint32_t tim; uint32_t pclk; - - I2c_valid_timing_nbr = 0; - - pclk = I2C_GetPclk(i2c); - - tim = I2C_ComputeTiming(pclk, hz); - + pclk = i2c_get_pclk(i2c); + if (pclk == I2C_PCLK_DEF) { + switch (hz) { + case 100000: + tim = TIMING_VAL_DEFAULT_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_DEFAULT_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_DEFAULT_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } else { + /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. + User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. + Enabling this may impact performance*/ + MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO); +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + tim = i2c_compute_timing(pclk, hz); +#endif + } return tim; } /** diff --git a/targets/TARGET_STM/TARGET_STM32H7/i2c_device.h b/targets/TARGET_STM/TARGET_STM32H7/i2c_device.h index 829290d9c6..655d697a29 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32H7/i2c_device.h @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2015-2020 STMicroelectronics. + * Copyright (c) 2015-2021 STMicroelectronics. * Copyright (c) 2020, Arduino SA. * All rights reserved. * @@ -23,10 +23,17 @@ extern "C" { #endif +/* Define I2C Device */ #if DEVICE_I2C +/* Define IP version */ #define I2C_IP_VERSION_V2 +#define TIMING_VAL_DEFAULT_CLK_100KHZ 0x40E15676 // Standard mode with Rise Time = 400ns and Fall Time = 100ns +#define TIMING_VAL_DEFAULT_CLK_400KHZ 0x20C11434 // Fast mode with Rise Time = 250ns and Fall Time = 100ns +#define TIMING_VAL_DEFAULT_CLK_1MHZ 0x00C31536 // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns +#define I2C_PCLK_DEF 120000000 // 120 MHz + #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI) /* Family specifc settings for clock source */ @@ -35,14 +42,19 @@ extern "C" { #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_D2PCLK1 #define I2CAPI_I2C4_CLKSRC RCC_I2C4CLKSOURCE_D3PCLK1 -/* Provide the suitable timing depending on requested frequency */ -extern uint32_t get_i2c_timing(I2CName i2c, int hz); +uint32_t i2c_get_pclk(I2CName i2c); +uint32_t i2c_get_timing(I2CName i2c, int hz); +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq); +void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t I2C_speed); +uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t I2C_speed); +#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + +#endif // DEVICE_I2C #ifdef __cplusplus } #endif -#endif // DEVICE_I2C - #endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/objects.h b/targets/TARGET_STM/TARGET_STM32H7/objects.h index c07ced56dc..727d0e1033 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/objects.h +++ b/targets/TARGET_STM/TARGET_STM32H7/objects.h @@ -29,6 +29,7 @@ #include "stm32h7xx_ll_cortex.h" #endif /* CONFIG_STM32H7_DUAL_CORE */ #include "stm32h7xx_ll_pwr.h" +#include "stm32h7xx_ll_system.h" #ifdef __cplusplus extern "C" { @@ -117,6 +118,9 @@ struct i2c_s { uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32L0/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L0/CMakeLists.txt index fbeb9c20d8..a9a2a6c5d3 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32L0/CMakeLists.txt @@ -17,6 +17,7 @@ target_sources(mbed-stm32l0 analogout_device.c flash_api.c gpio_irq_device.c + i2c_device.c pwmout_device.c serial_device.c spi_api.c diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L073xZ/system_clock.c b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L073xZ/system_clock.c index ac0a521108..919a9f76ba 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L073xZ/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L073xZ/system_clock.c @@ -104,7 +104,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_HSI48; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; if (bypass == 0) { RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ } else { diff --git a/targets/TARGET_STM/TARGET_STM32L0/i2c_device.c b/targets/TARGET_STM/TARGET_STM32L0/i2c_device.c new file mode 100755 index 0000000000..0628b2658f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L0/i2c_device.c @@ -0,0 +1,120 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "i2c_device.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "stm32l0xx_ll_rcc.h" + +/* Define I2C Device */ +#if DEVICE_I2C + +/** + * @brief Get I2C clock source frequency according I2C instance used. + * @param i2c I2C instance name. + * @retval I2C clock source frequency in Hz. + */ +uint32_t i2c_get_pclk(I2CName i2c) +{ + uint32_t clocksource; + uint32_t pclk = 0; + if (i2c == I2C_1) { + clocksource = __HAL_RCC_GET_I2C1_SOURCE(); + switch (clocksource) { + case RCC_I2C1CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C1CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C1CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#if defined I2C3_BASE + else if (i2c == I2C_3) { + clocksource = __HAL_RCC_GET_I2C3_SOURCE(); + switch (clocksource) { + case RCC_I2C3CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C3CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C3CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif + else { + // should not happend + error("I2C: unknown instance"); + } + return pclk; +} +/** + * @} + */ + +/** @defgroup I2C_DEVICE_Exported_Functions I2C_DEVICE Exported Functions + * @{ + */ +/** + * @brief Provide the suitable timing depending on requested frequency + * @param hz Required I2C clock in Hz. + * @retval I2C timing or 0 in case of error. + */ +uint32_t i2c_get_timing(I2CName i2c, int hz) +{ + uint32_t tim; + uint32_t pclk; + pclk = i2c_get_pclk(i2c); + if (pclk == I2C_PCLK_DEF) { + switch (hz) { + case 100000: + tim = TIMING_VAL_DEFAULT_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_DEFAULT_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_DEFAULT_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } else { + /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. + User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. + Enabling this may impact performance*/ + MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO); +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + tim = i2c_compute_timing(pclk, hz); +#endif + } + return tim; +} +/** + * @} + */ + +#endif // DEVICE_I2C diff --git a/targets/TARGET_STM/TARGET_STM32L0/i2c_device.h b/targets/TARGET_STM/TARGET_STM32L0/i2c_device.h index 175bde9f2d..f4aac1f738 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32L0/i2c_device.h @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2016-2020 STMicroelectronics. + * Copyright (c) 2016-2021 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -12,17 +12,20 @@ * ****************************************************************************** */ + #ifndef MBED_I2C_DEVICE_H #define MBED_I2C_DEVICE_H -#include "cmsis.h" +#include "PeripheralNames.h" #ifdef __cplusplus extern "C" { #endif +/* Define I2C Device */ #if DEVICE_I2C +/* Define IP version */ #define I2C_IP_VERSION_V2 #if defined I2C1_BASE @@ -38,6 +41,11 @@ extern "C" { #define I2C3_ER_IRQn I2C3_IRQn #endif +#define TIMING_VAL_DEFAULT_CLK_100KHZ 0x20602938 // Standard mode with Rise Time = 400ns and Fall Time = 100ns +#define TIMING_VAL_DEFAULT_CLK_400KHZ 0x00B0122A // Fast mode with Rise Time = 250ns and Fall Time = 100ns +#define TIMING_VAL_DEFAULT_CLK_1MHZ 0x0030040E // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns +#define I2C_PCLK_DEF 32000000 // 32 MHz + #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI) /* Family specifc settings for clock source */ @@ -45,31 +53,19 @@ extern "C" { #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_SYSCLK #define I2CAPI_I2C4_CLKSRC RCC_I2C4CLKSOURCE_SYSCLK -/* Provide the suitable timing depending on requested frequencie */ -static inline uint32_t get_i2c_timing(int hz) -{ - uint32_t tim = 0; +uint32_t i2c_get_pclk(I2CName i2c); +uint32_t i2c_get_timing(I2CName i2c, int hz); - switch (hz) { - case 100000: - tim = 0x20602938; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - tim = 0x00B0122A; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - tim = 0x0030040E; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - return tim; -} +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq); +void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t I2C_speed); +uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t I2C_speed); +#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + +#endif // DEVICE_I2C #ifdef __cplusplus } #endif -#endif // DEVICE_I2C - #endif diff --git a/targets/TARGET_STM/TARGET_STM32L0/objects.h b/targets/TARGET_STM/TARGET_STM32L0/objects.h index ca3b5b4221..642a202c18 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/objects.h +++ b/targets/TARGET_STM/TARGET_STM32L0/objects.h @@ -114,6 +114,9 @@ struct i2c_s { uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32L0/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L0/us_ticker_data.h index 7dafadfae9..5c6d27792a 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/us_ticker_data.h +++ b/targets/TARGET_STM/TARGET_STM32L0/us_ticker_data.h @@ -17,7 +17,7 @@ #define __US_TICKER_DATA_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #include "stm32l0xx.h" diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xB/cmsis_nvic.h index d67e5d3b11..605a4ee13e 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xB/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xB/cmsis_nvic.h @@ -31,8 +31,8 @@ #if !defined(MBED_RAM_SIZE) #define MBED_RAM_SIZE 0x8000 // 32 KB - // 0x4000 // 16 KB STM32L151CB STM32L151RB STM32L151VB - // 0x8000 // 32 KB STM32L151CBxxA STM32L151RBxxA STM32L151VBxxA +// 0x4000 // 16 KB STM32L151CB STM32L151RB STM32L151VB +// 0x8000 // 32 KB STM32L151CBxxA STM32L151RBxxA STM32L151VBxxA #warning "check MBED_RAM_SIZE value in cmsis_nvic.h" #endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xC/TARGET_XDOT_L151CC/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xC/TARGET_XDOT_L151CC/system_clock.c index 66a6421aeb..638e2f4b2c 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xC/TARGET_XDOT_L151CC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L151xC/TARGET_XDOT_L151CC/system_clock.c @@ -63,7 +63,7 @@ uint8_t SetSysClock_PLL_HSI(void); * @param None * @retval None */ -void SystemInit (void) +void SystemInit(void) { /*!< Set MSION bit */ RCC->CR |= (uint32_t)0x00000100; @@ -131,7 +131,7 @@ void SetSysClock(void) { /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { - while(1) { + while (1) { // [TODO] Put something here to tell the user that a problem occured... } } diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xB/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xB/cmsis_nvic.h index 2220a436e8..65294f7e49 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xB/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xB/cmsis_nvic.h @@ -31,8 +31,8 @@ #if !defined(MBED_RAM_SIZE) #define MBED_RAM_SIZE 0x8000 // 32 KB - // 0x4000 // 16 KB STM32L152CB STM32L152RB STM32L152VB - // 0x8000 // 32 KB STM32L152CBxxA STM32L152RBxxA STM32L152VBxxA +// 0x4000 // 16 KB STM32L152CB STM32L152RB STM32L152VB +// 0x8000 // 32 KB STM32L152CBxxA STM32L152RBxxA STM32L152VBxxA #warning "check MBED_RAM_SIZE value in cmsis_nvic.h" #endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xC/TARGET_MOTE_L152RC/system_clock.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xC/TARGET_MOTE_L152RC/system_clock.c index 9c66425f2b..b197f9418f 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xC/TARGET_MOTE_L152RC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xC/TARGET_MOTE_L152RC/system_clock.c @@ -63,7 +63,7 @@ uint8_t SetSysClock_PLL_HSI(void); * @param None * @retval None */ -void SystemInit (void) +void SystemInit(void) { /*!< Set MSION bit */ RCC->CR |= (uint32_t)0x00000100; @@ -117,7 +117,7 @@ void SetSysClock(void) { /* 3- If fail start with HSI clock */ if (SetSysClock_PLL_HSI() == 0) { - while(1) { + while (1) { // [TODO] Put something here to tell the user that a problem occured... } } @@ -137,8 +137,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; - if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) - return 1; // already on HSE PLL, could occur from deepsleep waking + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) { + return 1; // already on HSE PLL, could occur from deepsleep waking + } /* Used to gain time after DeepSleep in case HSI is used */ if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xE/TARGET_NUCLEO_L152RE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xE/TARGET_NUCLEO_L152RE/PeripheralPins.c index 5b4d5fb5e3..3f1562c956 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xE/TARGET_NUCLEO_L152RE/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_STM32L152xE/TARGET_NUCLEO_L152RE/PeripheralPins.c @@ -63,7 +63,7 @@ MBED_WEAK const PinMap PinMap_ADC[] = { {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC_IN7 {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC_IN8 {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC_IN9 - {PB_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0b + {PB_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG_ADC_CHANNEL_BANK_B, GPIO_NOPULL, 0, 0, 0)}, // ADC_IN0b {PB_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18 {PB_13, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC_IN19 {PB_14, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC_IN20 diff --git a/targets/TARGET_STM/TARGET_STM32L1/analogin_device.c b/targets/TARGET_STM/TARGET_STM32L1/analogin_device.c old mode 100644 new mode 100755 index 72c294132d..eae2117e52 --- a/targets/TARGET_STM/TARGET_STM32L1/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32L1/analogin_device.c @@ -62,7 +62,6 @@ void analogin_init(analogin_t *obj, PinName pin) obj->handle.Init.EOCSelection = EOC_SINGLE_CONV; // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example). obj->handle.Init.LowPowerAutoWait = ADC_AUTOWAIT_UNTIL_DATA_READ; // Enable the dynamic low power Auto Delay: new conversion start only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software. obj->handle.Init.LowPowerAutoPowerOff = ADC_AUTOPOWEROFF_IDLE_PHASE; // Enable the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). - obj->handle.Init.ChannelsBank = ADC_CHANNELS_BANK_A; obj->handle.Init.ContinuousConvMode = DISABLE; // Continuous mode disabled to have only 1 conversion at each conversion trig obj->handle.Init.NbrOfConversion = 1; // Parameter discarded because sequencer is disabled obj->handle.Init.DiscontinuousConvMode = DISABLE; // Parameter discarded because sequencer is disabled @@ -71,6 +70,16 @@ void analogin_init(analogin_t *obj, PinName pin) obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; obj->handle.Init.DMAContinuousRequests = DISABLE; +#if defined ADC_CHANNELS_BANK_B + if (STM_PIN_ANALOG_CHANNEL_BANK_B(function)) { + obj->handle.Init.ChannelsBank = ADC_CHANNELS_BANK_B; + } else { + obj->handle.Init.ChannelsBank = ADC_CHANNELS_BANK_A; + } +#else + obj->handle.Init.ChannelsBank = ADC_CHANNELS_BANK_A; +#endif + __HAL_RCC_ADC1_CLK_ENABLE(); if (HAL_ADC_Init(&obj->handle) != HAL_OK) { diff --git a/targets/TARGET_STM/TARGET_STM32L1/i2c_device.h b/targets/TARGET_STM/TARGET_STM32L1/i2c_device.h index 742727e89c..39a831aece 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32L1/i2c_device.h @@ -31,4 +31,8 @@ extern "C" { #endif // DEVICE_I2C +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32L1/objects.h b/targets/TARGET_STM/TARGET_STM32L1/objects.h index 9f5619ca87..91589c9a5b 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/objects.h +++ b/targets/TARGET_STM/TARGET_STM32L1/objects.h @@ -110,6 +110,9 @@ struct i2c_s { uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32L1/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L1/us_ticker_data.h index 3cb73e3aca..c32116dd87 100644 --- a/targets/TARGET_STM/TARGET_STM32L1/us_ticker_data.h +++ b/targets/TARGET_STM/TARGET_STM32L1/us_ticker_data.h @@ -17,13 +17,13 @@ #define __US_TICKER_DATA_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #include "stm32l1xx.h" #include "stm32l1xx_ll_tim.h" #include "cmsis_nvic.h" - + #define TIM_MST TIM5 #define TIM_MST_IRQ TIM5_IRQn #define TIM_MST_RCC __TIM5_CLK_ENABLE() diff --git a/targets/TARGET_STM/TARGET_STM32L4/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L4/CMakeLists.txt index 0642e934d0..6664473031 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32L4/CMakeLists.txt @@ -23,6 +23,7 @@ target_sources(mbed-stm32l4 analogout_device.c flash_api.c gpio_irq_device.c + i2c_device.c pwmout_device.c serial_device.c spi_api.c diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/PeripheralPins.c index 92cdf8990a..cef7824a58 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L452xE/TARGET_NUCLEO_L452RE_P/PeripheralPins.c @@ -170,12 +170,12 @@ MBED_WEAK const PinMap PinMap_PWM[] = { MBED_WEAK const PinMap PinMap_UART_TX[] = { {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX - {PA_2_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX + {PA_2_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_11, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, - {PC_1, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_4, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, @@ -185,13 +185,13 @@ MBED_WEAK const PinMap PinMap_UART_TX[] = { MBED_WEAK const PinMap PinMap_UART_RX[] = { {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX - {PA_3_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_RX + {PA_3_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_RX {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PA_15, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_10, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PC_0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PC_0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {NC, NC, 0} @@ -203,9 +203,9 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { {PA_15, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {PA_15_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PB_1, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, - {PB_1_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_1_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, - {PB_12, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, {NC, NC, 0} }; @@ -213,12 +213,12 @@ MBED_WEAK const PinMap PinMap_UART_RTS[] = { MBED_WEAK const PinMap PinMap_UART_CTS[] = { {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, {PA_6, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to SMPS_PG [ADP5301ACBZ_OUTOK] - {PA_6_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SMPS_PG [ADP5301ACBZ_OUTOK] + {PA_6_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to SMPS_PG [ADP5301ACBZ_OUTOK] {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, {PB_7, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LD4 [green Led] - {PB_13_ALT0, LPUART_1,STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD4 [green Led] + {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD4 [green Led] {NC, NC, 0} }; diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4S5xI/TARGET_B_L4S5I_IOT01A/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4S5xI/TARGET_B_L4S5I_IOT01A/PinNames.h index 0b92191285..f130662ac1 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4S5xI/TARGET_B_L4S5I_IOT01A/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4S5xI/TARGET_B_L4S5I_IOT01A/PinNames.h @@ -234,7 +234,7 @@ typedef enum { SYS_WKUP4 = PA_2, SYS_WKUP5 = PC_5, - /**** QSPI FLASH pins ****/ + /**** QSPI FLASH pins ****/ QSPI_FLASH1_IO0 = PE_12, QSPI_FLASH1_IO1 = PE_13, QSPI_FLASH1_IO2 = PE_14, diff --git a/targets/TARGET_STM/TARGET_STM32L4/can_device.h b/targets/TARGET_STM/TARGET_STM32L4/can_device.h index 3a21300705..9759d2ac21 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32L4/can_device.h @@ -42,4 +42,8 @@ extern "C" { #endif // DEVICE_CAN +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/i2c_device.c b/targets/TARGET_STM/TARGET_STM32L4/i2c_device.c new file mode 100755 index 0000000000..bb5df31cbd --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L4/i2c_device.c @@ -0,0 +1,185 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "i2c_device.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "stm32l4xx_ll_rcc.h" + +/* Define I2C Device */ +#if DEVICE_I2C + +/** + * @brief Get I2C clock source frequency according I2C instance used. + * @param i2c I2C instance name. + * @retval I2C clock source frequency in Hz. + */ +uint32_t i2c_get_pclk(I2CName i2c) +{ + uint32_t clocksource; + uint32_t pclk = 0; + if (i2c == I2C_1) { + clocksource = __HAL_RCC_GET_I2C1_SOURCE(); + switch (clocksource) { + case RCC_I2C1CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C1CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C1CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#if defined I2C2_BASE + else if (i2c == I2C_2) { + clocksource = __HAL_RCC_GET_I2C2_SOURCE(); + switch (clocksource) { + case RCC_I2C2CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C2CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C2CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif +#if defined I2C3_BASE + else if (i2c == I2C_3) { + clocksource = __HAL_RCC_GET_I2C3_SOURCE(); + switch (clocksource) { + case RCC_I2C3CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C3CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C3CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif +#if defined I2C4_BASE + else if (i2c == I2C_4) { + clocksource = __HAL_RCC_GET_I2C4_SOURCE(); + switch (clocksource) { + case RCC_I2C4CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case RCC_I2C4CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C4CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif + else { + // should not happend + error("I2C: unknown instance"); + } + return pclk; +} +/** + * @} + */ + +/** @defgroup I2C_DEVICE_Exported_Functions I2C_DEVICE Exported Functions + * @{ + */ +/** + * @brief Provide the suitable timing depending on requested frequency + * @param hz Required I2C clock in Hz. + * @retval I2C timing or 0 in case of error. + */ +uint32_t i2c_get_timing(I2CName i2c, int hz) +{ + uint32_t tim; + uint32_t pclk; + pclk = i2c_get_pclk(i2c); + if (pclk == I2C_PCLK_80M) { + switch (hz) { + case 100000: + tim = TIMING_VAL_80M_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_80M_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_80M_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } else if (pclk == I2C_PCLK_48M) { + switch (hz) { + case 100000: + tim = TIMING_VAL_48M_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_48M_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_48M_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } else if (pclk == I2C_PCLK_120M) { + switch (hz) { + case 100000: + tim = TIMING_VAL_120M_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_120M_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_120M_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } else { + /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. + User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. + Enabling this may impact performance*/ + MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO); +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + tim = i2c_compute_timing(pclk, hz); +#endif + } + return tim; +} +/** + * @} + */ + +#endif // DEVICE_I2C diff --git a/targets/TARGET_STM/TARGET_STM32L4/i2c_device.h b/targets/TARGET_STM/TARGET_STM32L4/i2c_device.h index 6368b4c53b..8ee0014015 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32L4/i2c_device.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2016-2020 STMicroelectronics + * Copyright (c) 2016-2021 STMicroelectronics * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,17 +18,36 @@ #ifndef MBED_I2C_DEVICE_H #define MBED_I2C_DEVICE_H -#include "cmsis.h" -#include "mbed_error.h" +#include "PeripheralNames.h" #ifdef __cplusplus extern "C" { #endif +/* Define I2C Device */ #if DEVICE_I2C +/* Define IP version */ #define I2C_IP_VERSION_V2 +// Common settings: I2C clock = 80 MHz, Analog filter = ON, Digital filter coefficient = 0 +#define TIMING_VAL_80M_CLK_100KHZ 0x30C14E6B // Standard mode with Rise Time = 400ns and Fall Time = 100ns +#define TIMING_VAL_80M_CLK_400KHZ 0x10D1143A // Fast mode with Rise Time = 250ns and Fall Time = 100ns +#define TIMING_VAL_80M_CLK_1MHZ 0x00810E27 // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns +#define I2C_PCLK_80M 80000000 // 80 MHz + +// Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0 +#define TIMING_VAL_48M_CLK_100KHZ 0x20A03E55 // Standard mode with Rise Time = 400ns and Fall Time = 100ns +#define TIMING_VAL_48M_CLK_400KHZ 0x10800C21 // Fast mode with Rise Time = 250ns and Fall Time = 100ns +#define TIMING_VAL_48M_CLK_1MHZ 0x00500816 // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns +#define I2C_PCLK_48M 48000000 // 48 MHz + +// Common settings: I2C clock = 120 MHz, Analog filter = ON, Digital filter coefficient = 0 +#define TIMING_VAL_120M_CLK_100KHZ 0x107075B0 // Standard mode with Rise Time = 400ns and Fall Time = 100ns +#define TIMING_VAL_120M_CLK_400KHZ 0x00501E6C // Fast mode with Rise Time = 250ns and Fall Time = 100ns +#define TIMING_VAL_120M_CLK_1MHZ 0x00200A26 // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns +#define I2C_PCLK_120M 120000000 // 120 MHz + #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI) /* Family specifc settings for clock source */ @@ -37,65 +56,19 @@ extern "C" { #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_SYSCLK #define I2CAPI_I2C4_CLKSRC RCC_I2C4CLKSOURCE_SYSCLK -/* Provide the suitable timing depending on requested frequencie */ -static inline uint32_t get_i2c_timing(int hz) -{ - uint32_t tim = 0; - if (SystemCoreClock == 80000000) { - // Common settings: I2C clock = 80 MHz, Analog filter = ON, Digital filter coefficient = 0 - switch (hz) { - case 100000: - tim = 0x30C14E6B; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - tim = 0x10D1143A; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - tim = 0x00810E27; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - } else if (SystemCoreClock == 48000000) { - // Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0 - switch (hz) { - case 100000: - tim = 0x20A03E55; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - tim = 0x10800C21; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - tim = 0x00500816; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - } else if (SystemCoreClock == 120000000) { - // Common settings: I2C clock = 120 MHz, Analog filter = ON, Digital filter coefficient = 0 - switch (hz) { - case 100000: - tim = 0x107075B0; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - tim = 0x00501E6C; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - tim = 0x00200A26; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - } else { - error("get_i2c_timing error\n"); - } - return tim; -} +uint32_t i2c_get_pclk(I2CName i2c); +uint32_t i2c_get_timing(I2CName i2c, int hz); + +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq); +void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t I2C_speed); +uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t I2C_speed); +#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + +#endif // DEVICE_I2C #ifdef __cplusplus } #endif -#endif // DEVICE_I2C - #endif diff --git a/targets/TARGET_STM/TARGET_STM32L4/objects.h b/targets/TARGET_STM/TARGET_STM32L4/objects.h index eab7c0543a..aeb3b7a5f2 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/objects.h +++ b/targets/TARGET_STM/TARGET_STM32L4/objects.h @@ -110,6 +110,9 @@ struct i2c_s { uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32L4/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32L4/us_ticker_data.h index 42d9bad21e..fa83d6b2a0 100644 --- a/targets/TARGET_STM/TARGET_STM32L4/us_ticker_data.h +++ b/targets/TARGET_STM/TARGET_STM32L4/us_ticker_data.h @@ -19,7 +19,7 @@ #define __US_TICKER_DATA_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif #include "stm32l4xx.h" diff --git a/targets/TARGET_STM/TARGET_STM32L5/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L5/CMakeLists.txt index fe6e123def..54a213bb2b 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32L5/CMakeLists.txt @@ -14,6 +14,7 @@ target_sources(mbed-stm32l5 analogout_device.c flash_api.c gpio_irq_device.c + i2c_device.c pwmout_device.c serial_device.c system_clock.c diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l552xx.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l552xx.h index 527d55569a..410710e2ef 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l552xx.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l552xx.h @@ -164,8 +164,8 @@ typedef enum HASH_IRQn = 96, /*!< HASH global interrupt */ LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ SPI3_IRQn = 99, /*!< SPI3 global interrupt */ - I2C4_EV_IRQn = 100, /*!< I2C4 Event interrupt */ - I2C4_ER_IRQn = 101, /*!< I2C4 Error interrupt */ + I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ + I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ DFSDM1_FLT0_IRQn = 102, /*!< DFSDM1 Filter 0 global interrupt */ DFSDM1_FLT1_IRQn = 103, /*!< DFSDM1 Filter 1 global interrupt */ DFSDM1_FLT2_IRQn = 104, /*!< DFSDM1 Filter 2 global interrupt */ @@ -1022,7 +1022,9 @@ typedef struct __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ - uint32_t RESERVED1[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ + __IO uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x50 */ + uint32_t RESERVED2[43];/*!< Reserved, Address offset: 0x54 -- 0xFC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ @@ -13974,9 +13976,20 @@ typedef struct #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) -#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ -#define TAMP_COUNTR TAMP_COUNTR_Msk +#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_CFGR register *****************/ +#define TAMP_CFGR_TMONEN_Pos (1U) +#define TAMP_CFGR_TMONEN_Msk (0x1UL << TAMP_CFGR_TMONEN_Pos) /*!< 0x00000002 */ +#define TAMP_CFGR_TMONEN TAMP_CFGR_TMONEN_Msk +#define TAMP_CFGR_VMONEN_Pos (2U) +#define TAMP_CFGR_VMONEN_Msk (0x1UL << TAMP_CFGR_VMONEN_Pos) /*!< 0x00000004 */ +#define TAMP_CFGR_VMONEN TAMP_CFGR_VMONEN_Msk +#define TAMP_CFGR_WUTMONEN_Pos (3U) +#define TAMP_CFGR_WUTMONEN_Msk (0x1UL << TAMP_CFGR_WUTMONEN_Pos) /*!< 0x00000008 */ +#define TAMP_CFGR_WUTMONEN TAMP_CFGR_WUTMONEN_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ #define TAMP_BKP0R_Pos (0U) diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l562xx.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l562xx.h index 0de40f1845..879379e17f 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l562xx.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l562xx.h @@ -166,8 +166,8 @@ typedef enum PKA_IRQn = 97, /*!< PKA global interrupt */ LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ SPI3_IRQn = 99, /*!< SPI3 global interrupt */ - I2C4_EV_IRQn = 100, /*!< I2C4 Event interrupt */ - I2C4_ER_IRQn = 101, /*!< I2C4 Error interrupt */ + I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ + I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ DFSDM1_FLT0_IRQn = 102, /*!< DFSDM1 Filter 0 global interrupt */ DFSDM1_FLT1_IRQn = 103, /*!< DFSDM1 Filter 1 global interrupt */ DFSDM1_FLT2_IRQn = 104, /*!< DFSDM1 Filter 2 global interrupt */ @@ -1096,7 +1096,9 @@ typedef struct __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ - uint32_t RESERVED1[47];/*!< Reserved, Address offset: 0x54 -- 0xFC */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ + __IO uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x50 */ + uint32_t RESERVED2[43];/*!< Reserved, Address offset: 0x54 -- 0xFC */ __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ @@ -14713,9 +14715,20 @@ typedef struct #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk /******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) -#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ -#define TAMP_COUNTR TAMP_COUNTR_Msk +#define TAMP_COUNTR_Pos (16U) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_CFGR register *****************/ +#define TAMP_CFGR_TMONEN_Pos (1U) +#define TAMP_CFGR_TMONEN_Msk (0x1UL << TAMP_CFGR_TMONEN_Pos) /*!< 0x00000002 */ +#define TAMP_CFGR_TMONEN TAMP_CFGR_TMONEN_Msk +#define TAMP_CFGR_VMONEN_Pos (2U) +#define TAMP_CFGR_VMONEN_Msk (0x1UL << TAMP_CFGR_VMONEN_Pos) /*!< 0x00000004 */ +#define TAMP_CFGR_VMONEN TAMP_CFGR_VMONEN_Msk +#define TAMP_CFGR_WUTMONEN_Pos (3U) +#define TAMP_CFGR_WUTMONEN_Msk (0x1UL << TAMP_CFGR_WUTMONEN_Pos) /*!< 0x00000008 */ +#define TAMP_CFGR_WUTMONEN TAMP_CFGR_WUTMONEN_Msk /******************** Bits definition for TAMP_BKP0R register ***************/ #define TAMP_BKP0R_Pos (0U) diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l5xx.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l5xx.h index 6a1f21b507..5838b81a58 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l5xx.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMSIS/stm32l5xx.h @@ -79,7 +79,7 @@ */ #define __STM32L5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32L5_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ -#define __STM32L5_CMSIS_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ +#define __STM32L5_CMSIS_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */ #define __STM32L5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32L5_CMSIS_VERSION ((__STM32L5_CMSIS_VERSION_MAIN << 24U)\ |(__STM32L5_CMSIS_VERSION_SUB1 << 16U)\ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMakeLists.txt index ecb41313b5..5888ebb8a1 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/CMakeLists.txt @@ -61,6 +61,7 @@ target_sources(mbed-stm32l5cube-fw STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard.c STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard_ex.c STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus.c + STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus_ex.c STM32L5xx_HAL_Driver/stm32l5xx_hal_spi.c STM32L5xx_HAL_Driver/stm32l5xx_hal_spi_ex.c STM32L5xx_HAL_Driver/stm32l5xx_hal_sram.c @@ -82,6 +83,7 @@ target_sources(mbed-stm32l5cube-fw STM32L5xx_HAL_Driver/stm32l5xx_ll_fmc.c STM32L5xx_HAL_Driver/stm32l5xx_ll_gpio.c STM32L5xx_HAL_Driver/stm32l5xx_ll_i2c.c + STM32L5xx_HAL_Driver/stm32l5xx_ll_icache.c STM32L5xx_HAL_Driver/stm32l5xx_ll_lptim.c STM32L5xx_HAL_Driver/stm32l5xx_ll_lpuart.c STM32L5xx_HAL_Driver/stm32l5xx_ll_opamp.c diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/Legacy/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/Legacy/stm32_hal_legacy.h index e57e8237ae..5ade8e11dd 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/Legacy/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/Legacy/stm32_hal_legacy.h @@ -23,7 +23,7 @@ #define STM32_HAL_LEGACY #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -38,7 +38,6 @@ #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - /** * @} */ @@ -383,7 +382,6 @@ #define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT #endif /* STM32H7 */ - /** * @} */ @@ -604,16 +602,16 @@ #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ #if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH +#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #endif /* STM32L1 */ #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH +#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW +#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM +#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 @@ -774,49 +772,6 @@ #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) -/** @brief Constants defining the events that can be selected to configure the - * set/reset crossbar of a timer output - */ -#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) -#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) -#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) -#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) -#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) -#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) -#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) -#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) -#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) - -#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) -#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) -#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) -#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) -#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) -#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) -#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) -#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) -#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) - -/** @brief Constants defining the event filtering applied to external events - * by a timer - */ -#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) - /** @brief Constants defining the DLL calibration periods (in micro seconds) */ #define HRTIM_CALIBRATIONRATE_7300 0x00000000U @@ -896,7 +851,6 @@ #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - /** * @} */ @@ -969,6 +923,11 @@ #define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID #endif +#if defined(STM32L4) || defined(STM32L5) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER +#elif defined(STM32G4) +#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED +#endif /** * @} @@ -980,15 +939,15 @@ #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS #if defined(STM32H7) - #define I2S_IT_TXE I2S_IT_TXP - #define I2S_IT_RXNE I2S_IT_RXP +#define I2S_IT_TXE I2S_IT_TXP +#define I2S_IT_RXNE I2S_IT_RXP - #define I2S_FLAG_TXE I2S_FLAG_TXP - #define I2S_FLAG_RXNE I2S_FLAG_RXP +#define I2S_FLAG_TXE I2S_FLAG_TXP +#define I2S_FLAG_RXNE I2S_FLAG_RXP #endif #if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL +#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL #endif /** * @} @@ -1023,7 +982,7 @@ /** * @} */ - + /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose * @{ */ @@ -1123,16 +1082,16 @@ #if defined(STM32H7) - #define SPI_FLAG_TXE SPI_FLAG_TXP - #define SPI_FLAG_RXNE SPI_FLAG_RXP +#define SPI_FLAG_TXE SPI_FLAG_TXP +#define SPI_FLAG_RXNE SPI_FLAG_RXP - #define SPI_IT_TXE SPI_IT_TXP - #define SPI_IT_RXNE SPI_IT_RXP +#define SPI_IT_TXE SPI_IT_TXP +#define SPI_IT_RXNE SPI_IT_RXP - #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET - #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET - #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET - #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET +#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET +#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET +#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET +#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET #endif /* STM32H7 */ @@ -1459,7 +1418,7 @@ #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY -#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) +#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) #define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt #define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End @@ -1481,7 +1440,7 @@ #define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT #define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT -#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */ +#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ /** * @} */ @@ -1495,7 +1454,8 @@ #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1503,7 +1463,8 @@ #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) #if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode @@ -1526,9 +1487,9 @@ #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - /** +/** * @} - */ + */ /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose * @{ @@ -1538,7 +1499,8 @@ #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ + )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT @@ -1563,9 +1525,9 @@ #define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA #define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA #endif /* STM32F4 */ - /** +/** * @} - */ + */ /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose * @{ @@ -1620,9 +1582,9 @@ #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - /** +/** * @} - */ + */ /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ @@ -1871,15 +1833,15 @@ #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC #if defined(STM32H7) - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 #else - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG #endif /* STM32H7 */ #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT @@ -2090,8 +2052,8 @@ */ #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) /** * @} @@ -2147,7 +2109,7 @@ #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT #if defined(STM32H7) - #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG +#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG #endif /** @@ -2284,7 +2246,8 @@ #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ + )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -3252,7 +3215,7 @@ #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3381,7 +3344,7 @@ /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3401,19 +3364,19 @@ #else #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) + (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ #define IS_ALARM IS_RTC_ALARM @@ -3597,6 +3560,13 @@ #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) +#define USART_OVERSAMPLING_16 0x00000000U +#define USART_OVERSAMPLING_8 USART_CR1_OVER8 + +#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == USART_OVERSAMPLING_8)) +#endif /* STM32F0 || STM32F3 || STM32F7 */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal.c index 605fdaf1d8..702a47bafb 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal.c @@ -49,11 +49,11 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32L5xx HAL Driver version number - */ + * @brief STM32L5xx HAL Driver version number + */ #define STM32L5XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define STM32L5XX_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ -#define STM32L5XX_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */ +#define STM32L5XX_HAL_VERSION_SUB2 (0x04U) /*!< [15:8] sub2 version */ #define STM32L5XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define STM32L5XX_HAL_VERSION ((STM32L5XX_HAL_VERSION_MAIN << 24U)\ |(STM32L5XX_HAL_VERSION_SUB1 << 16U)\ @@ -89,8 +89,8 @@ HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ */ /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions - * + * @brief Initialization and de-initialization functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -269,8 +269,8 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) */ /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * + * @brief HAL Control functions + * @verbatim =============================================================================== ##### HAL Control functions ##### @@ -293,7 +293,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) * used as application time base. * @note In the default implementation, this variable is incremented each 1ms * in SysTick ISR. - * @note This function is declared as __weak to be overwritten in case of other + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ @@ -435,7 +435,7 @@ uint32_t HAL_GetHalVersion(void) */ uint32_t HAL_GetREVID(void) { - return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); + return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); } /** @@ -444,7 +444,7 @@ uint32_t HAL_GetREVID(void) */ uint32_t HAL_GetDEVID(void) { - return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); + return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); } /** @@ -453,7 +453,7 @@ uint32_t HAL_GetDEVID(void) */ uint32_t HAL_GetUIDw0(void) { - return(READ_REG(*((uint32_t *)UID_BASE))); + return (READ_REG(*((uint32_t *)UID_BASE))); } /** @@ -462,7 +462,7 @@ uint32_t HAL_GetUIDw0(void) */ uint32_t HAL_GetUIDw1(void) { - return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); + return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); } /** @@ -471,7 +471,7 @@ uint32_t HAL_GetUIDw1(void) */ uint32_t HAL_GetUIDw2(void) { - return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); + return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); } /** @@ -479,8 +479,8 @@ uint32_t HAL_GetUIDw2(void) */ /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions - * @brief HAL Debug functions - * + * @brief HAL Debug functions + * @verbatim =============================================================================== ##### HAL Debug functions ##### @@ -534,8 +534,8 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void) */ /** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions - * @brief HAL SYSCFG configuration functions - * + * @brief HAL SYSCFG configuration functions + * @verbatim =============================================================================== ##### HAL SYSCFG configuration functions ##### @@ -644,9 +644,9 @@ HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) tickstart = HAL_GetTick(); /* Wait for VRR bit */ - while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U) + while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U) { - if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -710,8 +710,8 @@ void HAL_SYSCFG_DisableIOAnalogSwitchVdd(void) */ /** @defgroup HAL_Exported_Functions_Group5 HAL SYSCFG lock management functions - * @brief SYSCFG lock management functions. - * + * @brief SYSCFG lock management functions. + * @verbatim =============================================================================== ##### SYSCFG lock functions ##### @@ -755,7 +755,7 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem) uint32_t tmp_lock; /* Check null pointer */ - if(pItem == NULL) + if (pItem == NULL) { return HAL_ERROR; } @@ -782,8 +782,8 @@ HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem) /** @defgroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions - * @brief SYSCFG attributes management functions. - * + * @brief SYSCFG attributes management functions. + * @verbatim =============================================================================== ##### SYSCFG attributes functions ##### @@ -813,7 +813,7 @@ void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes) tmp = SYSCFG_S->SECCFGR; /* Set or reset Item */ - if((Attributes & SYSCFG_SEC) != 0x00U) + if ((Attributes & SYSCFG_SEC) != 0x00U) { tmp |= Item; } @@ -837,7 +837,7 @@ void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes) HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) { /* Check null pointer */ - if(pAttributes == NULL) + if (pAttributes == NULL) { return HAL_ERROR; } @@ -846,7 +846,7 @@ HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttri assert_param(IS_SYSCFG_ITEMS_ATTRIBUTES(Item)); /* Get the secure attribute state */ - if((SYSCFG_S->SECCFGR & Item) != 0U) + if ((SYSCFG_S->SECCFGR & Item) != 0U) { *pAttributes = SYSCFG_SEC; } diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal.h index a587772f94..b80a29865d 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal.h @@ -23,7 +23,7 @@ #define STM32L5xx_HAL_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -204,8 +204,8 @@ typedef enum #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ /** - * @} - */ + * @} + */ /** @defgroup SYSCFG_Lock_items SYSCFG Lock items * @brief SYSCFG items to set lock on @@ -395,7 +395,7 @@ typedef enum */ #define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ - }while(0) + }while(0) /** @brief SRAM2 page 32 to 63 write protection enable macro * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 @@ -403,7 +403,7 @@ typedef enum */ #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\ - }while(0) + }while(0) /** @brief SRAM2 page write protection unlock prior to erase * @note Writing a wrong key reactivates the write protection @@ -422,11 +422,11 @@ typedef enum */ #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ - }while(0) + }while(0) #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ - }while(0) + }while(0) /** @brief SYSCFG Break ECC lock. * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. @@ -459,7 +459,8 @@ typedef enum * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U) +#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\ + & (__FLAG__))!= 0U) ? 1U : 0U) /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. */ @@ -587,7 +588,7 @@ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); void HAL_MspInit(void); void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_adc.c index 45199418d1..7e3065b6cd 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_adc.c @@ -499,7 +499,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while (wait_loop_index != 0UL) { wait_loop_index--; @@ -857,31 +857,28 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) */ ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc); - } - /* DeInit the low level hardware. - - For example: - __HAL_RCC_ADC_FORCE_RESET(); - __HAL_RCC_ADC_RELEASE_RESET(); - __HAL_RCC_ADC_CLK_DISABLE(); - - Keep in mind that all ADCs use the same clock: disabling - the clock will reset all ADCs. - - */ + /* ========== Hard reset ADC peripheral ========== */ + /* Performs a global reset of the entire ADC peripherals instances */ + /* sharing the same common ADC instance: ADC state is forced to */ + /* a similar state as after device power-on. */ + /* Note: A possible implementation is to add RCC bus reset of ADC */ + /* (for example, using macro */ + /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */ + /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - if (hadc->MspDeInitCallback == NULL) - { - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - } + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } - /* DeInit the low level hardware */ - hadc->MspDeInitCallback(hadc); + /* DeInit the low level hardware */ + hadc->MspDeInitCallback(hadc); #else - /* DeInit the low level hardware */ - HAL_ADC_MspDeInit(hadc); + /* DeInit the low level hardware */ + HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); @@ -1483,13 +1480,17 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Ti { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -1599,13 +1600,17 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventTy { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -2400,44 +2405,46 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) /* group having no further conversion upcoming (same conditions as */ /* regular group interruption disabling above), */ /* and if injected scan sequence is completed. */ - if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL) || - ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) && - ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && - (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))) + if (tmp_adc_inj_is_trigger_source_sw_start != 0UL) { - /* If End of Sequence is reached, disable interrupts */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) + if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) || + ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) && + (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))) { - /* Particular case if injected contexts queue is enabled: */ - /* when the last context has been fully processed, JSQR is reset */ - /* by the hardware. Even if no injected conversion is planned to come */ - /* (queue empty, triggers are ignored), it can start again */ - /* immediately after setting a new context (JADSTART is still set). */ - /* Therefore, state of HAL ADC injected group is kept to busy. */ - if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) + /* If End of Sequence is reached, disable interrupts */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) { - /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ - /* JADSTART==0 (no conversion on going) */ - if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) + /* Particular case if injected contexts queue is enabled: */ + /* when the last context has been fully processed, JSQR is reset */ + /* by the hardware. Even if no injected conversion is planned to come */ + /* (queue empty, triggers are ignored), it can start again */ + /* immediately after setting a new context (JADSTART is still set). */ + /* Therefore, state of HAL ADC injected group is kept to busy. */ + if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL) { - /* Disable ADC end of sequence conversion interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ + /* JADSTART==0 (no conversion on going) */ + if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL) { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* Disable ADC end of sequence conversion interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } } } } @@ -2857,7 +2864,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while(wait_loop_index != 0UL) { wait_loop_index--; @@ -3334,13 +3341,17 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } @@ -3403,13 +3414,17 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -3463,13 +3478,17 @@ HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - return HAL_ERROR; + return HAL_ERROR; + } } } } diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_adc_ex.c index f0aefc12c5..279638cc5d 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_adc_ex.c @@ -516,13 +516,17 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, u { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } } @@ -878,6 +882,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t /* Process locked */ __HAL_LOCK(hadc); + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -993,6 +1001,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* Disable ADC peripheral if conversions are effectively stopped */ if (tmp_hal_status == HAL_OK) { + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -1020,13 +1032,20 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_ERROR; + return HAL_ERROR; + } } tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); @@ -1477,6 +1496,10 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) /* Clear HAL_ADC_STATE_REG_BUSY bit */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); @@ -1504,13 +1527,20 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc) { if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + /* New check to avoid false timeout detection in case of preemption */ + tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); + if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL) + || (tmphadcSlave_conversion_on_going == 1UL) + ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Process unlocked */ + __HAL_UNLOCK(hadc); - return HAL_ERROR; + return HAL_ERROR; + } } tmphadcSlave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmphadcSlave)->Instance); @@ -2015,7 +2045,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I /* Note: Variable divided by 2 to compensate partially */ /* CPU processing cycles, scaling in us split to not */ /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); + wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); while(wait_loop_index != 0UL) { wait_loop_index--; @@ -2083,7 +2113,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; - ADC_HandleTypeDef tmphadcSlave; + ADC_HandleTypeDef tmphadcSlave; uint32_t tmphadcSlave_conversion_on_going; /* Check the parameters */ @@ -2098,6 +2128,10 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_ /* Process locked */ __HAL_LOCK(hadc); + /* Temporary handle minimum initialization */ + __HAL_ADC_RESET_HANDLE_STATE(&tmphadcSlave); + ADC_CLEAR_ERRORCODE(&tmphadcSlave); + ADC_MULTI_SLAVE(hadc, &tmphadcSlave); if (tmphadcSlave.Instance == NULL) diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cortex.c index 9fc53eb0e8..a8260cdf75 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cortex.c @@ -115,7 +115,18 @@ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup CORTEX_Private_Functions CORTEX Private Functions + * @{ + */ +#if (__MPU_PRESENT == 1) +static void MPU_ConfigRegion(MPU_Type* MPUx, MPU_Region_InitTypeDef *MPU_RegionInit); +static void MPU_ConfigMemoryAttributes(MPU_Type* MPUx, MPU_Attributes_InitTypeDef *MPU_AttributesInit); +#endif /* __MPU_PRESENT */ +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup CORTEX_Exported_Functions @@ -142,15 +153,15 @@ /** * @brief Set the priority grouping field (pre-emption priority and subpriority) * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. + * @param PriorityGroup The priority grouping bits length. * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, + * @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority, * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, + * @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority, * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, + * @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority, * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, + * @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority, * 0 bit for subpriority * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. @@ -167,13 +178,13 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) /** * @brief Set the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l5xxxx.h)) - * @param PreemptPriority: The pre-emption priority for the IRQn channel. + * @param PreemptPriority The pre-emption priority for the IRQn channel. * This parameter can be a value between 0 and 7 * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. + * @param SubPriority The subpriority level for the IRQ channel. * This parameter can be a value between 0 and 7 * A lower priority value indicates a higher priority. * @retval None @@ -238,7 +249,7 @@ void HAL_NVIC_SystemReset(void) /** * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ @@ -259,7 +270,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) ============================================================================== [..] This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK) functionalities. + (NVIC, SYSTICK, MPU) functionalities. @endverbatim @@ -278,21 +289,21 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void) /** * @brief Get the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l5xxxx.h)) * @param PriorityGroup: the priority grouping bits length. * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, + * @arg NVIC_PRIORITYGROUP_0 0 bit for pre-emption priority, * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, + * @arg NVIC_PRIORITYGROUP_1 1 bit for pre-emption priority, * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, + * @arg NVIC_PRIORITYGROUP_2 2 bits for pre-emption priority, * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, + * @arg NVIC_PRIORITYGROUP_3 3 bits for pre-emption priority, * 0 bit for subpriority - * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). * @retval None */ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) @@ -345,8 +356,8 @@ void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) } /** - * @brief Get active interrupt (read the active register in NVIC and return the active bit). - * @param IRQn External interrupt number + * @brief Get active interrupt (read the active register in NVIC and return the active bit). + * @param IRQn External interrupt number * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l5xxxx.h)) * @retval status: - 0 Interrupt status is not pending. @@ -360,8 +371,8 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) /** * @brief Configure the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. * @retval None @@ -400,15 +411,219 @@ __weak void HAL_SYSTICK_Callback(void) */ } +#if (__MPU_PRESENT == 1) + +/** + * @brief Enable the MPU. + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged accessto the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Follow ARM recommendation with */ + /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */ + __DMB(); /* Force memory writes before continuing */ + __ISB(); /* Flush and refill pipeline with updated permissions */ +} + +/** + * @brief Disable the MPU. + * @retval None + */ +void HAL_MPU_Disable(void) +{ + __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + + /* Disable the MPU */ + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** + * @brief Initialize and configure the Region and the memory to be protected. + * @param MPU_RegionInit Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit) +{ + MPU_ConfigRegion(MPU, MPU_RegionInit); +} + +/** + * @brief Initialize and configure the memory attributes. + * @param MPU_AttributesInit Pointer to a MPU_Attributes_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit) +{ + MPU_ConfigMemoryAttributes(MPU, MPU_AttributesInit); +} + +#ifdef MPU_NS +/** + * @brief Enable the non-secure MPU. + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged accessto the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable_NS(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Follow ARM recommendation with */ + /* - Data Memory Barrier and Instruction Synchronization to insure MPU usage */ + __DMB(); /* Force memory writes before continuing */ + __ISB(); /* Flush and refill pipeline with updated permissions */ +} + +/** + * @brief Disable the non-secure MPU. + * @retval None + */ +void HAL_MPU_Disable_NS(void) +{ + __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ + + /* Disable the MPU */ + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** + * @brief Initialize and configure the Region and the memory to be protected for non-secure MPU. + * @param MPU_RegionInit Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit) +{ + MPU_ConfigRegion(MPU_NS, MPU_RegionInit); +} + +/** + * @brief Initialize and configure the memory attributes for non-secure MPU. + * @param MPU_AttributesInit Pointer to a MPU_Attributes_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit) +{ + MPU_ConfigMemoryAttributes(MPU_NS, MPU_AttributesInit); +} +#endif /* MPU_NS */ + +#endif /* __MPU_PRESENT */ + /** * @} */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup CORTEX_Private_Functions + * @{ + */ + +#if (__MPU_PRESENT == 1) + +static void MPU_ConfigRegion(MPU_Type* MPUx, MPU_Region_InitTypeDef *MPU_RegionInit) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_RegionInit->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_RegionInit->Enable)); + + /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */ + __DMB(); + + /* Set the Region number */ + MPUx->RNR = MPU_RegionInit->Number; + + if (MPU_RegionInit->Enable != MPU_REGION_DISABLE) + { + /* Check the parameters */ + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_RegionInit->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_RegionInit->AccessPermission)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_RegionInit->IsShareable)); + + MPUx->RBAR = (((uint32_t)MPU_RegionInit->BaseAddress & 0xFFFFFFE0U) | + ((uint32_t)MPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | + ((uint32_t)MPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | + ((uint32_t)MPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); + + MPUx->RLAR = (((uint32_t)MPU_RegionInit->LimitAddress & 0xFFFFFFE0U) | + ((uint32_t)MPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | + ((uint32_t)MPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); + } + else + { + MPUx->RBAR = 0U; + MPUx->RLAR = 0U; + } +} + +static void MPU_ConfigMemoryAttributes(MPU_Type* MPUx, MPU_Attributes_InitTypeDef *MPU_AttributesInit) +{ + __IO uint32_t *mair; + uint32_t attr_values; + uint32_t attr_number; + + /* Check the parameters */ + assert_param(IS_MPU_ATTRIBUTES_NUMBER(MPU_AttributesInit->Number)); + /* No need to check Attributes value as all 0x0..0xFF possible */ + + /* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */ + __DMB(); + + if(MPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4) + { + /* Program MPU_MAIR0 */ + mair = &(MPUx->MAIR0); + attr_number = MPU_AttributesInit->Number; + } + else + { + /* Program MPU_MAIR1 */ + mair = &(MPUx->MAIR1); + attr_number = (uint32_t)MPU_AttributesInit->Number - 4U; + } + + attr_values = *(mair); + attr_values &= ~(0xFFU << (attr_number * 8U)); + *(mair) = attr_values | ((uint32_t)MPU_AttributesInit->Attributes << (attr_number * 8U)); +} + +#endif /* __MPU_PRESENT */ + /** * @} */ #endif /* HAL_CORTEX_MODULE_ENABLED */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cortex.h index 2f32f53751..568fd186e4 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cortex.h @@ -37,6 +37,57 @@ */ /* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types CORTEX Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ + uint8_t AttributesIndex; /*!< Specifies the memory attributes index. + This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ +} MPU_Region_InitTypeDef; +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes Initialization Structure Definition + * @{ + */ +typedef struct +{ + uint8_t Number; /*!< Specifies the number of the memory attributes to configure. + This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ + + uint8_t Attributes; /*!< Specifies the memory attributes vue. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + +} MPU_Attributes_InitTypeDef; +/** + * @} + */ + +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants @@ -67,6 +118,115 @@ * @} */ +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE 0U +#define MPU_HARDFAULT_NMI 2U +#define MPU_PRIVILEGED_DEFAULT 4U +#define MPU_HFNMI_PRIVDEF 6U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE 1U +#define MPU_REGION_DISABLE 0U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_NOT_SHAREABLE 0U +#define MPU_ACCESS_OUTER_SHAREABLE 1U +#define MPU_ACCESS_INNER_SHAREABLE 3U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_PRIV_RW 0U +#define MPU_REGION_ALL_RW 1U +#define MPU_REGION_PRIV_RO 2U +#define MPU_REGION_ALL_RO 3U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 0U +#define MPU_REGION_NUMBER1 1U +#define MPU_REGION_NUMBER2 2U +#define MPU_REGION_NUMBER3 3U +#define MPU_REGION_NUMBER4 4U +#define MPU_REGION_NUMBER5 5U +#define MPU_REGION_NUMBER6 6U +#define MPU_REGION_NUMBER7 7U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number + * @{ + */ +#define MPU_ATTRIBUTES_NUMBER0 0U +#define MPU_ATTRIBUTES_NUMBER1 1U +#define MPU_ATTRIBUTES_NUMBER2 2U +#define MPU_ATTRIBUTES_NUMBER3 3U +#define MPU_ATTRIBUTES_NUMBER4 4U +#define MPU_ATTRIBUTES_NUMBER5 5U +#define MPU_ATTRIBUTES_NUMBER6 6U +#define MPU_ATTRIBUTES_NUMBER7 7U +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes + * @{ + */ +#define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ +#define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ +#define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ +#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ + +#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ +#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ +#define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ + +#define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ +#define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ + +#define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ +#define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ +#define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ +#define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ + +#define OUTER(__ATTR__) ((__ATTR__) << 4U) +#define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) +/** + * @} + */ + +#endif /* __MPU_PRESENT */ + /** * @} */ @@ -96,7 +256,6 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_SystemReset(void); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); - /** * @} */ @@ -115,6 +274,19 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); + +#if (__MPU_PRESENT == 1) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_RegionInit); +void HAL_MPU_ConfigMemoryAttributes(MPU_Attributes_InitTypeDef *MPU_AttributesInit); +#ifdef MPU_NS +void HAL_MPU_Enable_NS(uint32_t MPU_Control); +void HAL_MPU_Disable_NS(void); +void HAL_MPU_ConfigRegion_NS(MPU_Region_InitTypeDef *MPU_RegionInit); +void HAL_MPU_ConfigMemoryAttributes_NS(MPU_Attributes_InitTypeDef *MPU_AttributesInit); +#endif /* MPU_NS */ +#endif /* __MPU_PRESENT */ /** * @} */ @@ -144,6 +316,42 @@ void HAL_SYSTICK_Callback(void); #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_ALL_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_ALL_RO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ + ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) + +#endif /* __MPU_PRESENT */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cryp.c index dcb46b5456..50186bf153 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cryp.c @@ -6,7 +6,7 @@ * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: * + Initialization, de-initialization, set config and get config functions - * + DES/TDES, AES processing functions + * + AES processing functions * + DMA callback functions * + CRYP IRQ handler management * + Peripheral State functions @@ -32,8 +32,8 @@ (+++) Associate the initialized DMA handle to the CRYP DMA handle using __HAL_LINKDMA() (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() + interrupt on the two DMA channels. The output channel should have higher + priority than the input channel HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). (#)Initialize the CRYP according to the specified parameters : (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit. @@ -198,11 +198,11 @@ [..] The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() + Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() to register an interrupt callback. [..] - Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks: + Function HAL_CRYP_RegisterCallback() allows to register following callbacks: (+) InCpltCallback : Input FIFO transfer completed callback. (+) OutCpltCallback : Output FIFO transfer completed callback. (+) ErrorCallback : callback for error detection. @@ -212,9 +212,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default + Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) InCpltCallback : Input FIFO transfer completed callback. @@ -224,13 +224,13 @@ (+) MspDeInitCallback : CRYP MspDeInit. [..] - By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET + By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET all callbacks are set to the corresponding weak functions : - examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback(). + examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when + reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit() keep and use the user MspInit/MspDeInit functions (registered beforehand) [..] @@ -239,8 +239,8 @@ in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit() - or @ref HAL_CRYP_Init() function. + using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit() + or HAL_CRYP_Init() function. [..] When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or @@ -325,6 +325,7 @@ #define CRYP_PHASE_HEADER_SUSPENDED 0x00000004U /*!< GCM/GMAC/CCM header phase is suspended */ #define CRYP_PHASE_PAYLOAD_SUSPENDED 0x00000005U /*!< GCM/CCM payload phase is suspended */ #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ +#define CRYP_PHASE_HEADER_DMA_FEED 0x00000006U /*!< GCM/GMAC/CCM header is fed to the peripheral in DMA mode */ #define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */ #define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */ @@ -349,9 +350,7 @@ * @{ */ -#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\ - (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\ - }while(0U) +#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__)) /** * @} @@ -365,6 +364,7 @@ */ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); +static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size); static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); static void CRYP_DMAError(DMA_HandleTypeDef *hdma); @@ -374,6 +374,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp); +static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); @@ -387,6 +388,7 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp); static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); +static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) static void CRYP_Read_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Output); static void CRYP_Write_IVRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input); @@ -422,13 +424,13 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp); (+) DeInitialize the CRYP MSP (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef Parameters which are configured in This section are : - (+) Key size - (+) Data Type : 32,16, 8 or 1bit - (+) AlgoMode : - - for CRYP1 peripheral : + (++) Key size + (++) Data Type : 32,16, 8 or 1bit + (++) AlgoMode : + (+++) for CRYP1 peripheral : ECB and CBC in DES/TDES Standard ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard. - - for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported. + (+++) for TinyAES2 peripheral, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported. (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef @endverbatim @@ -585,15 +587,17 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD __HAL_LOCK(hcryp); /* Set CRYP parameters */ - hcryp->Init.DataType = pConf->DataType; - hcryp->Init.pKey = pConf->pKey; - hcryp->Init.Algorithm = pConf->Algorithm; - hcryp->Init.KeySize = pConf->KeySize; - hcryp->Init.pInitVect = pConf->pInitVect; - hcryp->Init.Header = pConf->Header; - hcryp->Init.HeaderSize = pConf->HeaderSize; - hcryp->Init.B0 = pConf->B0; - hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; + hcryp->Init.DataType = pConf->DataType; + hcryp->Init.pKey = pConf->pKey; + hcryp->Init.Algorithm = pConf->Algorithm; + hcryp->Init.KeySize = pConf->KeySize; + hcryp->Init.pInitVect = pConf->pInitVect; + hcryp->Init.Header = pConf->Header; + hcryp->Init.HeaderSize = pConf->HeaderSize; + hcryp->Init.B0 = pConf->B0; + hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; + hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; + hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; /* Set the key size (This bit field is do not care in the DES or TDES modes), data type and operating mode*/ MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); @@ -659,7 +663,9 @@ HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD pConf->Header = hcryp->Init.Header ; pConf->HeaderSize = hcryp->Init.HeaderSize; pConf->B0 = hcryp->Init.B0; - pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; + pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit; + pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip; /* Process Unlocked */ __HAL_UNLOCK(hcryp); @@ -691,8 +697,8 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspInit could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspInit can be implemented in the user file */ } @@ -707,8 +713,8 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspDeInit could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspDeInit can be implemented in the user file */ } @@ -1873,7 +1879,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) /* Clear computation complete flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) + if ((hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) || (hcryp->Init.Algorithm == CRYP_AES_CCM)) { /* if header phase */ @@ -1886,18 +1892,6 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); } } - else if (hcryp->Init.Algorithm == CRYP_AES_CCM) - { - /* if header phase */ - if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount) - { - CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); - } - else /* if payload phase */ - { - CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); - } - } else /* AES Algorithm ECB,CBC or CTR*/ { CRYP_AES_IT(hcryp); @@ -1939,8 +1933,8 @@ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_InCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_InCpltCallback can be implemented in the user file */ } @@ -1955,8 +1949,8 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_OutCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_OutCpltCallback can be implemented in the user file */ } @@ -1971,8 +1965,8 @@ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) /* Prevent unused argument(s) compilation warning */ UNUSED(hcryp); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_ErrorCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_ErrorCallback can be implemented in the user file */ } /** @@ -2506,18 +2500,105 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) { CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + uint32_t loopcounter; + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ /* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); - /* Call input data transfer complete callback */ + if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) + { + /* DMA is disabled, CCF is meaningful. Wait for computation completion before moving forward */ + CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + + if ((headersize_in_bytes % 16U) != 0U) + { + /* Write last words that couldn't be fed by DMA */ + hcryp->CrypHeaderCount = (uint16_t)((headersize_in_bytes / 16U) * 4U); + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + + /* Wait for computation completion before moving forward */ + CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); + } /* if ((headersize_in_bytes % 16U) != 0U) */ + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Initiate payload DMA IN and processed data DMA OUT transfers */ + (void)CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp); + } + else + { + uint32_t algo; + /* ECB, CBC or CTR end of input data feeding + or + end of GCM/CCM payload data feeding through DMA */ + algo = hcryp->Instance->CR & AES_CR_CHMOD; + + /* Don't call input data transfer complete callback only if + it remains some input data to write to the peripheral. + This case can only occur for GCM and CCM with a payload length + not a multiple of 16 bytes */ + if (!(((algo == CRYP_AES_GCM_GMAC) || (algo == CRYP_AES_CCM)) && \ + (((hcryp->Size) % 16U) != 0U))) + { + /* Call input data transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } /* if (hcryp->Phase == CRYP_PHASE_HEADER_DMA_FEED) */ } /** @@ -2530,7 +2611,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) uint32_t count; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp; /* Temporary CrypOutBuff */ + uint32_t temp[4]; /* Temporary CrypOutBuff */ uint32_t mode; CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -2581,46 +2662,31 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) hcryp->Instance->DINR = 0x0U; count++; } + /* Call input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + CRYP_ClearCCFlagWhenHigh(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE); /*Read the output block from the output FIFO */ for (count = 0U; count < 4U; count++) { /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp = hcryp->Instance->DOUTR; + temp[count] = hcryp->Instance->DOUTR; + } - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp; + count = 0U; + while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (count<4U)) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[count]; hcryp->CrypOutCount++; + count++; } } @@ -2679,7 +2745,7 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param inputaddr address of the input buffer - * @param Size size of the input buffer, must be a multiple of 16. + * @param Size size of the input and output buffers in words, must be a multiple of 4 * @param outputaddr address of the output buffer * @retval None */ @@ -2737,6 +2803,43 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); } +/** + * @brief Set the DMA configuration and start the header DMA transfer + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @param inputaddr address of the input buffer + * @param Size size of the input buffer in words, must be a multiple of 4 + * @retval None + */ +static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size) +{ + /* Set the CRYP DMA transfer complete callback */ + hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt; + + /* Set the DMA input error callback */ + hcryp->hdmain->XferErrorCallback = CRYP_DMAError; + + /* Mark that header is fed to the peripheral in DMA mode */ + hcryp->Phase = CRYP_PHASE_HEADER_DMA_FEED; + /* Enable the DMA input stream */ + if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK) + { + /* DMA error code field */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + /* Call error callback */ + } + + /* Enable IN DMA requests */ + SET_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); + + return HAL_OK; +} + /** * @brief Process Data: Write Input data in polling mode and used in AES functions. * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -3166,6 +3269,12 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t lastwordsize; uint32_t npblb; uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -3175,6 +3284,17 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) } #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ + /* Manage header size given in bytes to handle cases where + header size is not a multiple of 4 bytes */ + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } + if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) { if (hcryp->KeyIVConfig == 1U) @@ -3288,7 +3408,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3339,42 +3459,58 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } - else if ((hcryp->Init.HeaderSize) < 4U) + /* Enter header data */ + /* Cher first whether header length is small enough to enter the full header in one shot */ + else if (headersize_in_bytes <= 16U) { - for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++) + /* Write header data, padded with zeros if need be */ + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + hcryp->CrypHeaderCount++ ; + /* Pad the data with zeros to have a complete block */ while (loopcounter < 4U) { - /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; loopcounter++; + hcryp->CrypHeaderCount++; + } } - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - - /* Call Input transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } else { - /* Write the input block in the IN FIFO */ + /* Write the first input header block in the Input FIFO, + the following header data will be fed after interrupt occurrence */ hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); @@ -3419,7 +3555,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) @@ -3470,6 +3606,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -3486,12 +3630,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) */ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) { - __IO uint32_t count; - uint16_t wordsize = hcryp->Size / 4U ; - uint32_t index; - uint32_t npblb; - uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t count; uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) @@ -3570,122 +3709,16 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) return HAL_ERROR; } - /************************ Payload phase ************************************/ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - + } + else + { + /* Initialization and header phases already done, only do payload phase */ + if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } } /* if (DoKeyIVConfig == 1U) */ - if (hcryp->Size == 0U) - { - /* Process unLocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state and phase */ - hcryp->State = HAL_CRYP_STATE_READY; - } - else if (hcryp->Size >= 16U) - { - /*DMA transfer must not include the last block in case of Size is not %16 */ - wordsize = wordsize - (wordsize % 4U); - - /*DMA transfer */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr)); - } - else /* length of input data is < 16 */ - { - /* Compute the number of padding bytes in last block of payload */ - npblb = 16U - (uint32_t)hcryp->Size; - - /* Set Npblb in case of AES GCM payload encryption to get right tag*/ - if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) - { - /* Specify the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); - } - - /* Enable CRYP to start the final phase */ - __HAL_CRYP_ENABLE(hcryp); - - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } - - /* last block optionally pad the data with zeros*/ - for (index = 0U; index < lastwordsize; index ++) - { - /* Write the last Input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (index < 4U) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0U; - index++; - } - /* Wait for CCF flag to be raised */ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /*Read the output block from the output FIFO */ - for (index = 0U; index < 4U; index++) - { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp[index] = hcryp->Instance->DOUTR; - } - for (index = 0U; index < lastwordsize; index++) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; - hcryp->CrypOutCount++; - } - - /* Change the CRYP state to ready */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } - /* Return function status */ return HAL_OK; } @@ -4079,6 +4112,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } else if ((hcryp->Init.HeaderSize) < 4U) /*HeaderSize < 4 */ @@ -4184,6 +4225,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call Input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } @@ -4200,12 +4249,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) */ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) { - __IO uint32_t count = 0U; - uint16_t wordsize = hcryp->Size / 4U ; - uint32_t index; - uint32_t npblb; - uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t count; uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) @@ -4286,119 +4330,16 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) return HAL_ERROR; } - /******************** Payload phase *****************************************/ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Set to 0 the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); - - /* Select payload phase once the header phase is performed */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); - + } + else + { + /* Initialization and header phases already done, only do payload phase */ + if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } } /* if (DoKeyIVConfig == 1U) */ - if (hcryp->Size == 0U) - { - /* Process unLocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state and phase */ - hcryp->State = HAL_CRYP_STATE_READY; - } - else if (hcryp->Size >= 16U) - { - /*DMA transfer must not include the last block in case of Size is not %16 */ - wordsize = wordsize - (wordsize % 4U); - - /*DMA transfer */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr)); - } - else /* length of input data is < 16 */ - { - /* Compute the number of padding bytes in last block of payload */ - npblb = 16U - (uint32_t)hcryp->Size; - - /* Set Npblb in case of AES CCM payload decryption to get right tag*/ - if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) - { - /* Specify the number of non-valid bytes using NPBLB register*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); - } - - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } - - /* last block optionally pad the data with zeros*/ - for (index = 0U; index < lastwordsize; index ++) - { - /* Write the last Input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (index < 4U) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0U; - index++; - } - /* Wait for CCF flag to be raised */ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /*Read the output block from the output FIFO */ - for (index = 0U; index < 4U; index++) - { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - temp[index] = hcryp->Instance->DOUTR; - } - for (index = 0U; index < lastwordsize; index++) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; - hcryp->CrypOutCount++; - } - - /* Change the CRYP state to ready */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } - /* Return function status */ return HAL_OK; } @@ -4497,9 +4438,9 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; - if ((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { - /* Call output transfer complete callback */ + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) /*Call registered Input complete callback*/ hcryp->InCpltCallback(hcryp); @@ -4545,10 +4486,151 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call input transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } +/** + * @brief Sets the payload phase in DMA mode + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval state + */ +static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcryp) +{ + uint16_t wordsize = hcryp->Size / 4U ; + uint32_t index; + uint32_t npblb; + uint32_t lastwordsize; + uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t count; + uint32_t reg; + + /************************ Payload phase ************************************/ + if (hcryp->Size == 0U) + { + /* Process unLocked */ + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state and phase */ + hcryp->State = HAL_CRYP_STATE_READY; + } + else if (hcryp->Size >= 16U) + { + /*DMA transfer must not include the last block in case of Size is not %16 */ + wordsize = wordsize - (wordsize % 4U); + + /*DMA transfer */ + CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), wordsize, (uint32_t)(hcryp->pCrypOutBuffPtr)); + } + else /* length of input data is < 16 */ + { + /* Compute the number of padding bytes in last block of payload */ + npblb = 16U - (uint32_t)hcryp->Size; + + /* Set Npblb in case of AES GCM payload encryption or AES CCM payload decryption to get right tag*/ + reg = hcryp->Instance->CR & (AES_CR_CHMOD|AES_CR_MODE); + if ((reg == (CRYP_AES_GCM_GMAC|CRYP_OPERATINGMODE_ENCRYPT)) ||\ + (reg == (CRYP_AES_CCM|CRYP_OPERATINGMODE_DECRYPT))) + { + /* Specify the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb << 20U); + } + + /* Number of valid words (lastwordsize) in last block */ + if ((npblb % 4U) == 0U) + { + lastwordsize = (16U - npblb) / 4U; + } + else + { + lastwordsize = ((16U - npblb) / 4U) + 1U; + } + + /* last block optionally pad the data with zeros*/ + for (index = 0U; index < lastwordsize; index ++) + { + /* Write the last Input block in the IN FIFO */ + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->CrypInCount++; + } + while (index < 4U) + { + /* pad the data with zeros to have a complete block */ + hcryp->Instance->DINR = 0U; + index++; + } + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + /* Wait for CCF flag to be raised */ + count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + + /*Read the output block from the output FIFO */ + for (index = 0U; index < 4U; index++) + { + /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ + temp[index] = hcryp->Instance->DOUTR; + } + for (index = 0U; index < lastwordsize; index++) + { + *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index]; + hcryp->CrypOutCount++; + } + + /* Change the CRYP state to ready */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + + /* Call Output transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Output complete callback*/ + hcryp->OutCpltCallback(hcryp); +#else + /*Call legacy weak Output complete callback*/ + HAL_CRYP_OutCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + /** * @brief Sets the header phase in polling mode * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains @@ -4561,7 +4643,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u uint32_t loopcounter; uint32_t size_in_bytes; uint32_t tmp; - uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU}; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -4663,9 +4747,9 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } else { - /* Enter last bytes, padded with zeroes */ + /* Enter last bytes, padded with zeros */ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[size_in_bytes % 4U]; + tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; hcryp->Instance->DINR = tmp; loopcounter++; /* Pad the data with zeros to have a complete block */ @@ -4695,17 +4779,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u } else { - if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) - { - /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); + /*Workaround 1: only AES, before re-enabling the peripheral, datatype can be configured.*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - } + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); } /* Return function status */ return HAL_OK; @@ -4719,143 +4800,112 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u */ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp) { - __IO uint32_t count = 0U; uint32_t loopcounter; + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ /***************************** Header phase for GCM/GMAC or CCM *********************************/ - if ((hcryp->Init.HeaderSize != 0U)) + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) { - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); + /* Select header phase */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - if ((hcryp->Init.HeaderSize % 4U) == 0U) + /* Enable the CRYP peripheral */ + __HAL_CRYP_ENABLE(hcryp); + + /* Set the phase */ + hcryp->Phase = CRYP_PHASE_PROCESS; + + /* If header size is at least equal to 16 bytes, feed the header through DMA. + If size_in_bytes is not a multiple of blocks (is not a multiple of four 32-bit words ), + last bytes feeding and padding will be done in CRYP_DMAInCplt() */ + if (headersize_in_bytes >= 16U) + { + /* Initiate header DMA transfer */ + if (CRYP_SetHeaderDMAConfig(hcryp, (uint32_t)(hcryp->Init.Header), (uint16_t)((headersize_in_bytes / 16U) * 4U)) != HAL_OK) { - /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) - { - /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - } - else - { - /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) - { - /* Write the Input block in the Data Input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - while (loopcounter < 4U) - { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - - /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + return HAL_ERROR; } } else { - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); + if (headersize_in_bytes != 0U) + { + /* Header length is larger than 0 and strictly less than 16 bytes */ + /* Write last complete words */ + for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter++) + { + hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + hcryp->CrypHeaderCount++ ; + } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + } + } + + if (CRYP_WaitOnCCFlag(hcryp, CRYP_TIMEOUT_GCMCCMHEADERPHASE) != HAL_OK) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; + } + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); + } /* if (headersize_in_bytes != 0U) */ + + /* Move to payload phase if header length is null or + if the header length was less than 16 and header written by software instead of DMA */ + + /* Set to 0 the number of non-valid bytes using NPBLB register*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U); + + /* Select payload phase once the header phase is performed */ + CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); + + /* Initiate payload DMA IN and processed data DMA OUT transfers */ + if (CRYP_GCMCCM_SetPayloadPhase_DMA(hcryp) != HAL_OK) + { + return HAL_ERROR; + } + } /* if (headersize_in_bytes >= 16U) */ - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - } /* Return function status */ return HAL_OK; } @@ -4872,9 +4922,25 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) uint32_t lastwordsize; uint32_t npblb; uint32_t mode; + uint32_t headersize_in_bytes; + uint32_t tmp; + uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ + + if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) + { + headersize_in_bytes = hcryp->Init.HeaderSize * 4U; + } + else + { + headersize_in_bytes = hcryp->Init.HeaderSize; + } /***************************** Header phase *********************************/ - if (hcryp->Init.HeaderSize == hcryp->CrypHeaderCount) + /* Test whether or not the header phase is over. + If the test below is true, move to payload phase */ + if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U)) { /* Set the phase */ hcryp->Phase = CRYP_PHASE_PROCESS; @@ -4957,11 +5023,19 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = 0x0U; loopcounter++; } + /* Call the input data transfer complete callback */ +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); +#else + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ } } - else if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U)) + else if ((((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)) { - + /* Can enter full 4 header words */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) /* If suspension flag has been raised, suspend processing only if not already at the end of the header */ @@ -4996,19 +5070,40 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->CrypHeaderCount++; } } - else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/ + else /* Write last header block (4 words), padded with zeros if needed */ { - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < (hcryp->Init.HeaderSize % 4U); loopcounter++) + + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; } + /* If the header size is a multiple of words */ + if ((headersize_in_bytes % 4U) == 0U) + { + /* Pad the data with zeros to have a complete block */ + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; + hcryp->CrypHeaderCount++; + } + } + else + { + /* Enter last bytes, padded with zeros */ + tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); + tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; + hcryp->Instance->DINR = tmp; + loopcounter++; + hcryp->CrypHeaderCount++; + /* Pad the data with zeros to have a complete block */ while (loopcounter < 4U) { - /* pad the data with zeros to have a complete block */ hcryp->Instance->DINR = 0x0U; loopcounter++; + hcryp->CrypHeaderCount++; + } } } } @@ -5018,6 +5113,7 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @param Timeout Timeout duration. + * @note This function can only be used in thread mode. * @retval HAL status */ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) @@ -5041,6 +5137,47 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T return HAL_OK; } +/** + * @brief Wait for Computation Complete Flag (CCF) to raise then clear it. + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module. + * @param Timeout Timeout duration. + * @note This function can be used in thread or handler mode. + * @retval HAL status + */ +static void CRYP_ClearCCFlagWhenHigh(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) +{ + uint32_t count = Timeout; + + do + { + count-- ; + if (count == 0U) + { + /* Disable the CRYP peripheral clock */ + __HAL_CRYP_DISABLE(hcryp); + + /* Change state */ + hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; + + /* Process unlocked */ + __HAL_UNLOCK(hcryp); + hcryp->State = HAL_CRYP_STATE_READY; + +#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) + /*Call registered error callback*/ + hcryp->ErrorCallback(hcryp); +#else + /*Call legacy weak error callback*/ + HAL_CRYP_ErrorCallback(hcryp); +#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ + } + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + + /* Clear CCF flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); +} #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) /** @@ -5345,9 +5482,9 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) hcryp->CrypInCount++; hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); hcryp->CrypInCount++; - if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) + if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) { - /* Call output transfer complete callback */ + /* Call input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) /*Call registered Input complete callback*/ hcryp->InCpltCallback(hcryp); diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cryp.h index 24db3c77d9..f024357a74 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_cryp.h @@ -109,7 +109,7 @@ typedef struct __CRYP_HandleTypeDef typedef struct #endif { - AES_TypeDef *Instance; /*!< AES Register base address */ + AES_TypeDef *Instance; /*!< AES Register base address */ CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */ @@ -120,13 +120,13 @@ typedef struct uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - __IO uint16_t CrypHeaderCount; /*!< Counter of header data */ + __IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */ - __IO uint16_t CrypInCount; /*!< Counter of input data */ + __IO uint16_t CrypInCount; /*!< Counter of input data in words */ - __IO uint16_t CrypOutCount; /*!< Counter of output data */ + __IO uint16_t CrypOutCount; /*!< Counter of output data in words */ - uint16_t Size; /*!< length of input data in words */ + uint16_t Size; /*!< Length of input data */ uint32_t Phase; /*!< CRYP peripheral phase */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_dac.c index 200c86b72d..512af62c33 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_dac.c @@ -1052,13 +1052,17 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { - /* Update error code */ - SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if(((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL) + { + /* Update error code */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); - /* Change the DMA state */ - hdac->State = HAL_DAC_STATE_TIMEOUT; + /* Change the DMA state */ + hdac->State = HAL_DAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } HAL_Delay(1); @@ -1072,13 +1076,17 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConf /* Check for the Timeout */ if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { - /* Update error code */ - SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); + /* New check to avoid false timeout detection in case of preemption */ + if(((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL) + { + /* Update error code */ + SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); - /* Change the DMA state */ - hdac->State = HAL_DAC_STATE_TIMEOUT; + /* Change the DMA state */ + hdac->State = HAL_DAC_STATE_TIMEOUT; - return HAL_TIMEOUT; + return HAL_TIMEOUT; + } } } HAL_Delay(1U); diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_def.h index a0082332ca..227247a111 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_def.h @@ -23,7 +23,7 @@ #define STM32L5xx_HAL_DEF_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -67,10 +67,10 @@ typedef enum #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ - (__DMA_HANDLE__).Parent = (__HANDLE__); \ - } while(0) + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) /** @brief Reset the Handle's State field. * @param __HANDLE__ specifies the Peripheral Handle. @@ -90,68 +90,68 @@ typedef enum #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) #if (USE_RTOS == 1) - /* Reserved for future use */ - #error " USE_RTOS should be 0 in the current HAL release " +/* Reserved for future use */ +#error " USE_RTOS should be 0 in the current HAL release " #else - #define __HAL_LOCK(__HANDLE__) \ - do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ - { \ - return HAL_BUSY; \ - } \ - else \ - { \ - (__HANDLE__)->Lock = HAL_LOCKED; \ - } \ - }while (0) +#define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0) - #define __HAL_UNLOCK(__HANDLE__) \ - do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0) +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) #endif /* USE_RTOS */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ - #ifndef __weak - #define __weak __attribute__((weak)) - #endif - #ifndef __packed - #define __packed __attribute__((packed)) - #endif +#ifndef __weak +#define __weak __attribute__((weak)) +#endif +#ifndef __packed +#define __packed __attribute__((packed)) +#endif #elif defined (__GNUC__) /* GNU Compiler */ - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ #endif /* __GNUC__ */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__((aligned (4))) - #endif +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__((aligned (4))) +#endif #elif defined (__GNUC__) /* GNU Compiler */ - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__((aligned (4))) - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif /* __ALIGN_BEGIN */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__((aligned (4))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ #else - #ifndef __ALIGN_END - #define __ALIGN_END - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #if defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #endif /* __ICCARM__ */ - #endif /* __ALIGN_BEGIN */ +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#if defined (__ICCARM__) /* IAR Compiler */ +#define __ALIGN_BEGIN +#endif /* __ICCARM__ */ +#endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ /** diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_exti.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_exti.c index 77902b8d35..549b7b55fb 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_exti.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_exti.c @@ -4,7 +4,8 @@ * @author MCD Application Team * @brief EXTI HAL module driver. * This file provides firmware functions to manage the following - * functionalities of the General Purpose Input/Output (EXTI) peripheral: + * functionalities of the Extended Interrupts and event controller + * (EXTI) peripheral: * + Initialization and de-initialization functions * + IO operation functions * @@ -25,7 +26,7 @@ (++) Falling (++) Both of them - (+) When set in interrupt mode, configurable Exti lines have two diffenrents + (+) When set in interrupt mode, configurable Exti lines have two different interrupt pending registers which allow to distinguish which transition occurs: (++) Rising edge pending interrupt diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_exti.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_exti.h index 9e6f6fc4c5..12228c3c41 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_exti.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_exti.h @@ -252,22 +252,22 @@ typedef struct /** @defgroup EXTI_Private_Macros EXTI Private Macros * @{ */ -#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \ - ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ - (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ - (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ - (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ (((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U)))) -#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00U) && \ - (((__LINE__) & ~EXTI_MODE_MASK) == 0x00U)) +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U)) -#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) -#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_RISING) || \ - ((__LINE__) == EXTI_TRIGGER_FALLING)) +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \ + ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING)) -#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00U) +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U) #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ ((__PORT__) == EXTI_GPIOB) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_gtzc.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_gtzc.c index 54c00d6bb9..bfa6c7371f 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_gtzc.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_gtzc.c @@ -110,8 +110,8 @@ /* Private constants ---------------------------------------------------------*/ /** @defgroup GTZC_Private_Constants GTZC Private Constants - * @{ - */ + * @{ + */ /* Definitions for GTZC_TZSC_MPCWM */ #define GTZC_TZSC_MPCWM1_MEM_SIZE 0x10000000U /* 256MB max size */ @@ -153,25 +153,25 @@ /* Private macros ------------------------------------------------------------*/ /** @defgroup GTZC_Private_Macros GTZC Private Macros - * @{ - */ + * @{ + */ #define IS_ADDRESS_IN(mem, address)\ -( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ - && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \ - || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ - && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) ) + ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ + && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \ + || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ + && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) ) #define IS_ADDRESS_IN_S(mem, address)\ -( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ - && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) + ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ + && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) #define IS_ADDRESS_IN_NS(mem, address)\ -( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ - && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) + ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ + && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) #define GTZC_BASE_ADDRESS(mem)\ -( mem ## _BASE ) + ( mem ## _BASE ) /** * @} @@ -219,10 +219,9 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, uint32_t register_address; /* check entry parameters */ - if ( (PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV)) - || ( HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER) - || ( ((PeriphId & GTZC_PERIPH_ALL) != 0U) - && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) + if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV)) + || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) { return HAL_ERROR; } @@ -271,8 +270,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* secure configuration */ - register_address = (uint32_t)&(GTZC_TZSC->SECCFGR1) - + (4U * GTZC_GET_REG_INDEX(PeriphId)); + register_address = (uint32_t) &(GTZC_TZSC->SECCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC) { SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); @@ -288,8 +286,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ /* privilege configuration */ - register_address = (uint32_t)&(GTZC_TZSC->PRIVCFGR1) - + (4U * GTZC_GET_REG_INDEX(PeriphId)); + register_address = (uint32_t) &(GTZC_TZSC->PRIVCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV) { SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); @@ -326,10 +323,9 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, uint32_t register_address; /* check entry parameters */ - if ( (PeriphAttributes == NULL) - || ( HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER) - || ( ((PeriphId & GTZC_PERIPH_ALL) != 0U) - && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) + if ((PeriphAttributes == NULL) + || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) { return HAL_ERROR; } @@ -342,7 +338,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, reg_value = READ_REG(GTZC_TZSC->SECCFGR1); for (i = 0U; i < 32U; i++) { - if(((reg_value & (1UL << i)) >> i) != 0U) + if (((reg_value & (1UL << i)) >> i) != 0U) { PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; } @@ -355,7 +351,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, reg_value = READ_REG(GTZC_TZSC->SECCFGR2); for (/*i = 32U*/; i < GTZC_TZSC_PERIPH_NUMBER; i++) { - if(((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U) + if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U) { PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; } @@ -371,7 +367,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, reg_value = READ_REG(GTZC_TZSC->PRIVCFGR1); for (i = 0U; i < 32U; i++) { - if(((reg_value & (1UL << i)) >> i) != 0U) + if (((reg_value & (1UL << i)) >> i) != 0U) { PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; } @@ -384,7 +380,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, reg_value = READ_REG(GTZC_TZSC->PRIVCFGR2); for (/*i = 32U*/; i < GTZC_TZSC_PERIPH_NUMBER; i++) { - if(((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U) + if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U) { PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; } @@ -400,11 +396,10 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, /* common case where only one peripheral is configured */ /* secure configuration */ - register_address = (uint32_t)&(GTZC_TZSC->SECCFGR1) - + (4U * GTZC_GET_REG_INDEX(PeriphId)); + register_address = (uint32_t) &(GTZC_TZSC->SECCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); - if(((READ_BIT(*(__IO uint32_t *)register_address, - 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId)) + if (((READ_BIT(*(__IO uint32_t *)register_address, + 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId)) != 0U) { *PeriphAttributes = GTZC_TZSC_PERIPH_SEC; @@ -415,11 +410,10 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, } /* privilege configuration */ - register_address = (uint32_t)&(GTZC_TZSC->PRIVCFGR1) - + (4U * GTZC_GET_REG_INDEX(PeriphId)); + register_address = (uint32_t) &(GTZC_TZSC->PRIVCFGR1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); - if(((READ_BIT(*(__IO uint32_t *)register_address, - 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId)) + if (((READ_BIT(*(__IO uint32_t *)register_address, + 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId)) != 0U) { *PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV; @@ -459,9 +453,8 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, * The structure description is available in @ref GTZC_Exported_Types. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( - uint32_t MemBaseAddress, - MPCWM_ConfigTypeDef *pMPCWM_Desc) +HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, + MPCWM_ConfigTypeDef *pMPCWM_Desc) { uint32_t register_address; uint32_t reg_value; @@ -470,11 +463,10 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( uint32_t length_pos, length_msk; /* check entry parameters */ - if ( (pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2) - || ( (MemBaseAddress == FMC_BANK3) - && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2)) - || (( pMPCWM_Desc->Offset % GTZC_TZSC_MPCWM_GRANULARITY) != 0U) - || (( pMPCWM_Desc->Length % GTZC_TZSC_MPCWM_GRANULARITY) != 0U)) + if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2) + || ((MemBaseAddress == FMC_BANK3) && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2)) + || ((pMPCWM_Desc->Offset % GTZC_TZSC_MPCWM_GRANULARITY) != 0U) + || ((pMPCWM_Desc->Length % GTZC_TZSC_MPCWM_GRANULARITY) != 0U)) { return HAL_ERROR; } @@ -486,44 +478,44 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( size = GTZC_TZSC_MPCWM1_MEM_SIZE; if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) { - register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM1_NSWMR1); - start_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Pos; - start_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Msk; - length_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Pos; - length_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Msk; + register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR1); + start_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Pos; + start_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Msk; + length_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Pos; + length_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Msk; } else { - /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 - * (Parameter already checked) - */ - register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM1_NSWMR2); - start_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Pos; - start_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Msk; - length_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Pos; - length_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Msk; + /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 + * (Parameter already checked) + */ + register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR2); + start_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Pos; + start_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Msk; + length_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Pos; + length_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Msk; } break; case FMC_BANK1: size = GTZC_TZSC_MPCWM1_MEM_SIZE; if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) { - register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM2_NSWMR1); - start_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Pos; - start_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Msk; - length_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Pos; - length_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Msk; + register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR1); + start_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Pos; + start_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Msk; + length_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Pos; + length_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Msk; } else { - /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 - * (Parameter already checked) - */ - register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM2_NSWMR2); - start_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Pos; - start_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Msk; - length_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Pos; - length_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Msk; + /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 + * (Parameter already checked) + */ + register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR2); + start_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Pos; + start_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Msk; + length_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Pos; + length_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Msk; } break; case FMC_BANK3: @@ -531,7 +523,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( * (Parameter already checked) */ size = GTZC_TZSC_MPCWM3_MEM_SIZE; - register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM3_NSWMR1); + register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM3_NSWMR1); start_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Pos; start_msk = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Msk; length_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Pos; @@ -542,10 +534,8 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( break; } - if ( (pMPCWM_Desc->Offset > size) - || ( ( pMPCWM_Desc->Offset - + pMPCWM_Desc->Length) - > size)) + if ((pMPCWM_Desc->Offset > size) + || ((pMPCWM_Desc->Offset + pMPCWM_Desc->Length) > size)) { return HAL_ERROR; } @@ -565,9 +555,8 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( * The structure description is available in @ref GTZC_Exported_Types. * @retval HAL status. */ -HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes( - uint32_t MemBaseAddress, - MPCWM_ConfigTypeDef *pMPCWM_Desc) +HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, + MPCWM_ConfigTypeDef *pMPCWM_Desc) { uint32_t register_address; uint32_t reg_value; @@ -578,21 +567,21 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes( switch (MemBaseAddress) { case OCTOSPI1_BASE: - register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM1_NSWMR1); + register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR1); start_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Pos; start_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1STRT_Msk; length_pos = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Pos; length_msk = GTZC_TZSC_MPCWM1_NSWMR1_NSWM1LGTH_Msk; break; case FMC_BANK1: - register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM2_NSWMR1); + register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR1); start_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Pos; start_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1STRT_Msk; length_pos = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Pos; length_msk = GTZC_TZSC_MPCWM2_NSWMR1_NSWM1LGTH_Msk; break; case FMC_BANK3: - register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM3_NSWMR1); + register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM3_NSWMR1); start_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Pos; start_msk = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1STRT_Msk; length_pos = GTZC_TZSC_MPCWM3_NSWMR1_NSWM1LGTH_Pos; @@ -618,14 +607,14 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes( switch (MemBaseAddress) { case OCTOSPI1_BASE: - register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM1_NSWMR2); + register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM1_NSWMR2); start_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Pos; start_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2STRT_Msk; length_pos = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Pos; length_msk = GTZC_TZSC_MPCWM1_NSWMR2_NSWM2LGTH_Msk; break; case FMC_BANK1: - register_address = (uint32_t)&(GTZC_TZSC_S->MPCWM2_NSWMR2); + register_address = (uint32_t) &(GTZC_TZSC_S->MPCWM2_NSWMR2); start_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Pos; start_msk = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2STRT_Msk; length_pos = GTZC_TZSC_MPCWM2_NSWMR2_NSWM2LGTH_Pos; @@ -729,16 +718,12 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, uint32_t i; /* check entry parameters */ - if ( ( !(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) - && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))) - || ( ( pMPCBB_desc->SecureRWIllegalMode - != GTZC_MPCBB_SRWILADIS_ENABLE) - && ( pMPCBB_desc->SecureRWIllegalMode - != GTZC_MPCBB_SRWILADIS_DISABLE)) - || ( ( pMPCBB_desc->InvertSecureState - != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) - && ( pMPCBB_desc->InvertSecureState - != GTZC_MPCBB_INVSECSTATE_INVERTED))) + if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))) + || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE) + && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE)) + || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) + && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED))) { return HAL_ERROR; } @@ -795,8 +780,8 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, uint32_t i; /* check entry parameters */ - if ( !(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) - && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))) + if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) + && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))) { return HAL_ERROR; } @@ -820,8 +805,7 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk); size_mask = (1UL << (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE)) - 1U; /* limitation: code not portable with memory > 256K */ - pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->LCKVTR1) - & size_mask; + pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->LCKVTR1)& size_mask; /* read vector register information */ size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); @@ -860,26 +844,26 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, /* check entry parameters and deduce physical base address */ end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U; - if ( ( (IS_ADDRESS_IN_NS(SRAM1, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U ) + if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U) { mpcbb_ptr = GTZC_MPCBB1_S; base_address = SRAM1_BASE_NS; } - else if ( ( (IS_ADDRESS_IN_S(SRAM1, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U ) + else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U) { mpcbb_ptr = GTZC_MPCBB1_S; base_address = SRAM1_BASE_S; } - else if ( ( (IS_ADDRESS_IN_NS(SRAM2, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U ) + else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress)) + && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U) { mpcbb_ptr = GTZC_MPCBB2_S; base_address = SRAM2_BASE_NS; } - else if ( ( (IS_ADDRESS_IN_S(SRAM2, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U ) + else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress)) + && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U) { mpcbb_ptr = GTZC_MPCBB2_S; base_address = SRAM2_BASE_S; @@ -955,25 +939,25 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, /* check entry parameters and deduce physical base address */ end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U; - if ( (IS_ADDRESS_IN_NS(SRAM1, MemAddress)) + if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM1, end_address))) { mpcbb_ptr = GTZC_MPCBB1_S; base_address = SRAM1_BASE_NS; } - else if ( (IS_ADDRESS_IN_S(SRAM1, MemAddress)) + else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress)) && (IS_ADDRESS_IN_S(SRAM1, end_address))) { mpcbb_ptr = GTZC_MPCBB1_S; base_address = SRAM1_BASE_S; } - else if ( (IS_ADDRESS_IN_NS(SRAM2, MemAddress)) + else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress)) && (IS_ADDRESS_IN_NS(SRAM2, end_address))) { mpcbb_ptr = GTZC_MPCBB2_S; base_address = SRAM2_BASE_NS; } - else if ( (IS_ADDRESS_IN_S(SRAM2, MemAddress)) + else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress)) && (IS_ADDRESS_IN_S(SRAM2, end_address))) { mpcbb_ptr = GTZC_MPCBB2_S; @@ -991,8 +975,8 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, for (i = 0U; i < NbBlocks; i++) { - pMemAttributes[i] = READ_BIT(mpcbb_ptr->VCTR[offset_reg_start], - 1UL << (offset_bit_start % 32U)) + pMemAttributes[i] = READ_BIT(mpcbb_ptr->VCTR[offset_reg_start], + 1UL << (offset_bit_start % 32U)) >> (offset_bit_start % 32U); offset_bit_start++; @@ -1034,20 +1018,19 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, } /* check entry parameters */ - if ( (IS_ADDRESS_IN(SRAM1, MemAddress)) + if ((IS_ADDRESS_IN(SRAM1, MemAddress)) && (IS_ADDRESS_IN(SRAM1, (MemAddress - + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM1); /* limitation: code not portable with memory > 256K */ reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->LCKVTR1; } - else if ( (IS_ADDRESS_IN(SRAM2, MemAddress)) + else if ((IS_ADDRESS_IN(SRAM2, MemAddress)) && (IS_ADDRESS_IN(SRAM2, (MemAddress - + ( NbSuperBlocks - * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM2); /* limitation: code not portable with memory > 256K */ @@ -1117,20 +1100,19 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, } /* check entry parameters */ - if ( (IS_ADDRESS_IN(SRAM1, MemAddress)) + if ((IS_ADDRESS_IN(SRAM1, MemAddress)) && (IS_ADDRESS_IN(SRAM1, (MemAddress - + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM1); /* limitation: code not portable with memory > 256K */ reg_mpcbb = GTZC_MPCBB1_S->LCKVTR1; } - else if ( (IS_ADDRESS_IN(SRAM2, MemAddress)) + else if ((IS_ADDRESS_IN(SRAM2, MemAddress)) && (IS_ADDRESS_IN(SRAM2, (MemAddress - + ( NbSuperBlocks - * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) + + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) + - 1U)))) { base_address = GTZC_BASE_ADDRESS(SRAM2); /* limitation: code not portable with memory > 256K */ @@ -1147,8 +1129,8 @@ HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, for (i = 0U; i < NbSuperBlocks; i++) { - pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U))) - >> (offset_bit_start % 32U); + pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U))) + >> (offset_bit_start % 32U); offset_bit_start++; } @@ -1235,9 +1217,8 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId) uint32_t register_address; /* check entry parameters */ - if ( ( HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) - || ( ((PeriphId & GTZC_PERIPH_ALL) != 0U) - && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) + if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) { return HAL_ERROR; } @@ -1252,8 +1233,7 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId) else { /* common case where only one peripheral is configured */ - register_address = (uint32_t)&(GTZC_TZIC->IER1) - + (4U * GTZC_GET_REG_INDEX(PeriphId)); + register_address = (uint32_t) &(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); } @@ -1272,9 +1252,8 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId) uint32_t register_address; /* check entry parameters */ - if ( ( HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) - || ( ((PeriphId & GTZC_PERIPH_ALL) != 0U) - && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) + if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) { return HAL_ERROR; } @@ -1289,8 +1268,7 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId) else { /* common case where only one peripheral is configured */ - register_address = (uint32_t)&(GTZC_TZIC->IER1) - + (4U * GTZC_GET_REG_INDEX(PeriphId)); + register_address = (uint32_t) &(GTZC_TZIC->IER1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); } @@ -1317,9 +1295,8 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag) uint32_t register_address; /* check entry parameters */ - if ( ( HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) - || ( ((PeriphId & GTZC_PERIPH_ALL) != 0U) - && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) + if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) { return HAL_ERROR; } @@ -1348,10 +1325,9 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag) else { /* common case where only one peripheral is concerned */ - register_address = (uint32_t)&(GTZC_TZIC->SR1) - + (4U * GTZC_GET_REG_INDEX(PeriphId)); + register_address = (uint32_t) &(GTZC_TZIC->SR1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); *pFlag = READ_BIT(*(__IO uint32_t *)register_address, - 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId); + 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId); } return HAL_OK; @@ -1369,9 +1345,8 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId) uint32_t register_address; /* check entry parameters */ - if ( ( HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) - || ( ((PeriphId & GTZC_PERIPH_ALL) != 0U) - && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) + if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) + || (((PeriphId & GTZC_PERIPH_ALL) != 0U) && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U))) { return HAL_ERROR; } @@ -1386,8 +1361,7 @@ HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId) else { /* common case where only one peripheral is configured */ - register_address = (uint32_t)&(GTZC_TZIC->FCR1) - + (4U * GTZC_GET_REG_INDEX(PeriphId)); + register_address = (uint32_t) &(GTZC_TZIC->FCR1) + (4U * GTZC_GET_REG_INDEX(PeriphId)); SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); } @@ -1428,7 +1402,7 @@ void HAL_GTZC_IRQHandler(void) /* Get Mask interrupt and then clear them */ flag = ier_itsources & sr_flags; - if(flag != 0U) + if (flag != 0U) { WRITE_REG(GTZC_TZIC->FCR1, flag); @@ -1452,7 +1426,7 @@ void HAL_GTZC_IRQHandler(void) /* Get Mask interrupt and then clear them */ flag = ier_itsources & sr_flags; - if(flag != 0U) + if (flag != 0U) { WRITE_REG(GTZC_TZIC->FCR2, flag); @@ -1476,7 +1450,7 @@ void HAL_GTZC_IRQHandler(void) /* Get Mask interrupt and then clear them */ flag = ier_itsources & sr_flags; - if(flag != 0U) + if (flag != 0U) { WRITE_REG(GTZC_TZIC->FCR3, flag); diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_gtzc.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_gtzc.h index cb20b3a5a1..3e1b2cec57 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_gtzc.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_gtzc.h @@ -348,8 +348,8 @@ typedef struct /* Private macros ------------------------------------------------------------*/ /** @defgroup GTZC_Private_Macros GTZC Private Macros - * @{ - */ + * @{ + */ /* retrieve information to access register for a specific PeriphId */ #define GTZC_GET_REG_INDEX(periph_id)\ @@ -376,15 +376,15 @@ typedef struct /* Exported macros -----------------------------------------------------------*/ /** @defgroup GTZC_Exported_Macros GTZC Exported Macros - * @{ - */ + * @{ + */ /* user-oriented macro to get array index of a specific PeriphId - * in case of GTZC_PERIPH_ALL usage in the two following functions: - * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() - */ + * in case of GTZC_PERIPH_ALL usage in the two following functions: + * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() + */ #define HAL_GTZC_GET_ARRAY_INDEX(periph_id)\ -( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) ) + ( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) ) /** * @} @@ -417,12 +417,10 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, * @{ */ -HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes( - uint32_t MemBaseAddress, - MPCWM_ConfigTypeDef *pMPCWM_Desc); -HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes( - uint32_t MemBaseAddress, - MPCWM_ConfigTypeDef *pMPCWM_Desc); +HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, + MPCWM_ConfigTypeDef *pMPCWM_Desc); +HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, + MPCWM_ConfigTypeDef *pMPCWM_Desc); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_icache.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_icache.c index 469018d4d1..afa6e23423 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_icache.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_icache.c @@ -44,7 +44,8 @@ @ref HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate procedure is complete. The function @ref HAL_ICACHE_WaitForInvalidateComplete() may be called to wait for the end of the invalidate procedure automatically - initiated when disabling the Instruction Cache with @ref HAL_ICACHE_Disable() + initiated when disabling the Instruction Cache with @ref HAL_ICACHE_Disable(). + The cache operation is bypassed during the invalidation procedure. (#) Use the performance monitoring counters for Hit and Miss with the following functions: @ref HAL_ICACHE_Monitor_Start(), @ref HAL_ICACHE_Monitor_Stop(), @@ -216,8 +217,12 @@ HAL_StatusTypeDef HAL_ICACHE_Disable(void) { if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; - break; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) + { + status = HAL_TIMEOUT; + break; + } } } @@ -306,8 +311,12 @@ HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void) { if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; - break; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) + { + status = HAL_TIMEOUT; + break; + } } } } diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_icache.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_icache.h index fffefd47ec..90bb947626 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_icache.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_icache.h @@ -187,7 +187,7 @@ typedef struct * @retval The state of __INTERRUPT__ (0 or 1). */ #define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \ - ((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U) + ((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U) /** @brief Check whether the selected ICACHE flag is set or not. * @param __FLAG__ specifies the flag to check. diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_irda.c index 6b3ac439f6..533c84fe09 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_irda.c @@ -613,43 +613,45 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD switch (CallbackID) { case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : - hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ break; case HAL_IRDA_TX_COMPLETE_CB_ID : - hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ break; case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : - hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ break; case HAL_IRDA_RX_COMPLETE_CB_ID : - hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ break; case HAL_IRDA_ERROR_CB_ID : - hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ + hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ break; case HAL_IRDA_ABORT_COMPLETE_CB_ID : - hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ break; case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : - hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ break; case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : - hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ break; case HAL_IRDA_MSPINIT_CB_ID : - hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ + hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ break; case HAL_IRDA_MSPDEINIT_CB_ID : - hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ + hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ break; default : @@ -2242,7 +2244,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) uint32_t tmpreg; IRDA_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; - const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + static const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; uint32_t pclk; /* Check the communication parameters */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_irda.h index 84194c193a..d2aef0d356 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_irda.h @@ -90,7 +90,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL IRDA Init function already called) + * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -107,7 +107,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_iwdg.c index 2897c5ad08..c6ec541574 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_iwdg.c @@ -47,7 +47,7 @@ [..] Default timeout value (necessary for IWDG_SR status register update): Constant LSI_VALUE is defined based on the nominal LSI clock frequency. - This frequency being subject to variations as mentioned above, the + This frequency being subject to variations as mentioned above, the default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT below) may become too short or too long. In such cases, this default timeout value can be tuned by redefining @@ -65,13 +65,13 @@ (++) Configure the IWDG prescaler and counter reload value. This reload value will be loaded in the IWDG counter each time the watchdog is reloaded, then the IWDG will start counting down from this value. - (++) Wait for status flags to be reset. (++) Depending on window parameter: (+++) If Window Init parameter is same as Window register value, nothing more is done but reload counter value in order to exit function with exact time base. (+++) Else modify Window register. This will automatically reload watchdog counter. + (++) Wait for status flags to be reset. (#) Then the application program must refresh the IWDG counter at regular intervals during normal operation to prevent an MCU reset, using @@ -125,7 +125,8 @@ the LSI_VALUE constant. The value of this constant can be changed by the user to take into account possible LSI clock period variations. The timeout value is multiplied by 1000 to be converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) +#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) +#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) /** * @} */ @@ -196,11 +197,14 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) tickstart = HAL_GetTick(); /* Wait for register to be updated */ - while (hiwdg->Instance->SR != 0x00u) + while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) { if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) { - return HAL_TIMEOUT; + if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) + { + return HAL_TIMEOUT; + } } } @@ -223,6 +227,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) return HAL_OK; } + /** * @} */ @@ -242,7 +247,6 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) * @{ */ - /** * @brief Refresh the IWDG. * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains @@ -258,6 +262,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) return HAL_OK; } + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_iwdg.h index d1a84d21e0..e37423e7ce 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_iwdg.h @@ -87,7 +87,6 @@ typedef struct #define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ #define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ #define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ - /** * @} */ @@ -100,7 +99,6 @@ typedef struct * @} */ - /** * @} */ @@ -138,7 +136,7 @@ typedef struct * @{ */ /* Initialization/Start functions ********************************************/ -HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); /** * @} */ @@ -147,7 +145,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); * @{ */ /* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); +HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_lptim.c index 2bb1654921..ed74a34627 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_lptim.c @@ -189,12 +189,12 @@ * @{ */ #define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(__INSTANCE__) \ - (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() :\ - ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT()) + (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() :\ + ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() : __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT()) #define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(__INSTANCE__) \ - (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() :\ - ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT()) + (((__INSTANCE__) == LPTIM1) ? __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() :\ + ((__INSTANCE__) == LPTIM2) ? __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() : __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT()) /** * @} */ @@ -213,8 +213,8 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t */ /** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -251,19 +251,17 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); - } - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) - { assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); - assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); } assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); @@ -322,21 +320,18 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); } if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRIGSEL)); - } - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) - { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_CKFLT)); + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); } - /* Clear CKSEL, CKPOL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_CKPOL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | + /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ + tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE)); /* Set initialization parameters */ @@ -355,19 +350,21 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) hlptim->Init.UltraLowPowerClock.SampleTime); } - /* Configure the active edge or edges used by the counter only if LPTIM is - * clocked by an external clock source - */ - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + /* Configure LPTIM external clock polarity and digital filter */ + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity); + tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | + hlptim->Init.UltraLowPowerClock.SampleTime); } + /* Configure LPTIM external trigger */ if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable External trigger and set the trigger source */ - tmpcfgr |= (hlptim->Init.Trigger.Source | - hlptim->Init.Trigger.ActiveEdge); + tmpcfgr |= (hlptim->Init.Trigger.Source | + hlptim->Init.Trigger.ActiveEdge | + hlptim->Init.Trigger.SampleTime); } /* Write to LPTIMx CFGR */ @@ -481,8 +478,8 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions - * @brief Start-Stop operation functions. - * + * @brief Start-Stop operation functions. + * @verbatim ============================================================================== ##### LPTIM Start Stop operation functions ##### @@ -1631,7 +1628,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t hlptim->State = HAL_LPTIM_STATE_BUSY; /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1712,7 +1710,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(hlptim->Instance); /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) + && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { /* Check if clock is prescaled */ assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); @@ -1815,8 +1814,8 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions - * @brief Read operation functions. - * + * @brief Read operation functions. + * @verbatim ============================================================================== ##### LPTIM Read operation functions ##### @@ -1873,8 +1872,8 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) */ /** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks - * @brief LPTIM IRQ handler. - * + * @brief LPTIM IRQ handler. + * @verbatim ============================================================================== ##### LPTIM IRQ handler and callbacks ##### @@ -2426,8 +2425,8 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti */ /** @defgroup LPTIM_Group5 Peripheral State functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim ============================================================================== ##### Peripheral State functions ##### @@ -2504,8 +2503,7 @@ static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t { result = HAL_TIMEOUT; } - } - while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); + } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); return result; } diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_lptim.h index c1a2b83c2d..6ab891b305 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_lptim.h @@ -394,10 +394,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -573,7 +573,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @retval Interrupt status. */ -#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @brief Enable the LPTIM1 EXTI line in interrupt mode. @@ -585,7 +586,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Disable the LPTIM1 EXTI line in interrupt mode. * @retval None */ -#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR2 &= ~(LPTIM_EXTI_LINE_LPTIM1)) +#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR2\ + &= ~(LPTIM_EXTI_LINE_LPTIM1)) /** @@ -598,7 +600,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Disable the LPTIM1 EXTI line in event mode. * @retval None */ -#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT() (EXTI->EMR2 &= ~(LPTIM_EXTI_LINE_LPTIM1)) +#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT() (EXTI->EMR2\ + &= ~(LPTIM_EXTI_LINE_LPTIM1)) /** * @brief Enable the LPTIM2 EXTI line in interrupt mode. @@ -610,7 +613,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Disable the LPTIM2 EXTI line in interrupt mode. * @retval None */ -#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR2 &= ~(LPTIM_EXTI_LINE_LPTIM2)) +#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR2\ + &= ~(LPTIM_EXTI_LINE_LPTIM2)) /** @@ -623,7 +627,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Disable the LPTIM2 EXTI line in event mode. * @retval None */ -#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT() (EXTI->EMR2 &= ~(LPTIM_EXTI_LINE_LPTIM2)) +#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT() (EXTI->EMR2\ + &= ~(LPTIM_EXTI_LINE_LPTIM2)) /** * @brief Enable the LPTIM3 EXTI line in interrupt mode. @@ -635,7 +640,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Disable the LPTIM3 EXTI line in interrupt mode. * @retval None */ -#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() (EXTI->IMR2 &= ~(LPTIM_EXTI_LINE_LPTIM3)) +#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT() (EXTI->IMR2\ + &= ~(LPTIM_EXTI_LINE_LPTIM3)) /** @@ -648,7 +654,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Disable the LPTIM3 EXTI line in event mode. * @retval None */ -#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_EVENT() (EXTI->EMR2 &= ~(LPTIM_EXTI_LINE_LPTIM3)) +#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_EVENT() (EXTI->EMR2\ + &= ~(LPTIM_EXTI_LINE_LPTIM3)) /** * @} @@ -660,9 +667,9 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin */ /** @addtogroup LPTIM_Exported_Functions_Group1 - * @brief Initialization and Configuration functions. - * @{ - */ + * @brief Initialization and Configuration functions. + * @{ + */ /* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); @@ -675,9 +682,9 @@ void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group2 - * @brief Start-Stop operation functions. - * @{ - */ + * @brief Start-Stop operation functions. + * @{ + */ /* Start/Stop operation functions *********************************************/ /* ################################# PWM Mode ################################*/ /* Blocking mode: Polling */ @@ -731,9 +738,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group3 - * @brief Read operation functions. - * @{ - */ + * @brief Read operation functions. + * @{ + */ /* Reading operation functions ************************************************/ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); @@ -743,9 +750,9 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); */ /** @addtogroup LPTIM_Exported_Functions_Group4 - * @brief LPTIM IRQ handler and callback functions. - * @{ - */ + * @brief LPTIM IRQ handler and callback functions. + * @{ + */ /* LPTIM IRQ functions *******************************************************/ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); @@ -762,7 +769,8 @@ void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, + pLPTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** @@ -770,9 +778,9 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_ */ /** @addtogroup LPTIM_Group5 - * @brief Peripheral State functions. - * @{ - */ + * @brief Peripheral State functions. + * @{ + */ /* Peripheral State functions ************************************************/ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** @@ -878,26 +886,26 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_REPETITION(__REPETITION__) ((__REPETITION__) <= 0x000000FFUL) #define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \ - ((((__INSTANCE__) == LPTIM1) && \ - (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \ - || \ - (((__INSTANCE__) == LPTIM2) && \ - (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))) \ - || \ - (((__INSTANCE__) == LPTIM3) && \ - (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \ - ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2)))) + ((((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \ + || \ + (((__INSTANCE__) == LPTIM2) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))) \ + || \ + (((__INSTANCE__) == LPTIM3) && \ + (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \ + ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2)))) #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \ - (((__INSTANCE__) == LPTIM1) && \ - (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ - ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2))) + (((__INSTANCE__) == LPTIM1) && \ + (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \ + ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2))) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc.c index 91285707ea..44d48a2318 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc.c @@ -105,7 +105,7 @@ (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT(). This function allows the read of 512 bytes blocks. - You can choose either one block read operation or multiple block read operation + You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_MMC_GetCardState() function for MMC card state. @@ -129,18 +129,18 @@ by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_MMC_GetCardState() function for MMC card state. - You could also check the DMA transfer process through the MMC Tx interrupt event. + You could also check the DMA transfer process through the MMC Tx interrupt event. (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT(). This function allows the read of 512 bytes blocks. - You can choose either one block read operation or multiple block read operation + You can choose either one block read operation or multiple block read operation by adjusting the "NumberOfBlocks" parameter. After this, you have to ensure that the transfer is done correctly. The check is done through HAL_MMC_GetCardState() function for MMC card state. You could also check the IT transfer process through the MMC Tx interrupt event. *** MMC card information *** - =========================== + =========================== [..] (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo(). It returns useful information about the MMC card such as block size, card type, @@ -281,6 +281,10 @@ #define MMC_EXT_CSD_PWR_CL_52_POS 16 #define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24 #endif + +/* Frequencies used in the driver for clock divider calculation */ +#define MMC_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */ +#define MMC_HIGH_SPEED_FREQ 52000000U /* High speed phase : 52 MHz max */ /** * @} */ @@ -300,7 +304,8 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc); static void MMC_Read_IT(MMC_HandleTypeDef *hmmc); static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state); static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state); -static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout); +static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, + uint32_t Timeout); static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed); /** @@ -312,8 +317,8 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 */ /** @addtogroup MMC_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions - * + * @brief Initialization and de-initialization functions + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -335,7 +340,7 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) { /* Check the MMC handle allocation */ - if(hmmc == NULL) + if (hmmc == NULL) { return HAL_ERROR; } @@ -348,7 +353,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl)); assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv)); - if(hmmc->State == HAL_MMC_STATE_RESET) + if (hmmc->State == HAL_MMC_STATE_RESET) { /* Allocate lock resource and initialize it */ hmmc->Lock = HAL_UNLOCKED; @@ -363,7 +368,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuf0CpltCallback; hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuf1CpltCallback; - if(hmmc->MspInitCallback == NULL) + if (hmmc->MspInitCallback == NULL) { hmmc->MspInitCallback = HAL_MMC_MspInit; } @@ -379,7 +384,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize the Card parameters */ - if(HAL_MMC_InitCard(hmmc) == HAL_ERROR) + if (HAL_MMC_InitCard(hmmc) == HAL_ERROR) { return HAL_ERROR; } @@ -428,11 +433,15 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1); if (sdmmc_clk == 0U) { - hmmc->State = HAL_MMC_STATE_READY; - hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; - return HAL_ERROR; + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; + return HAL_ERROR; } - Init.ClockDiv = sdmmc_clk/(2U*400000U); + Init.ClockDiv = sdmmc_clk / (2U * MMC_INIT_FREQ); + +#if (USE_SD_TRANSCEIVER != 0U) + Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT; +#endif /* USE_SD_TRANSCEIVER */ /* Initialize SDMMC peripheral interface with default configuration */ (void)SDMMC_Init(hmmc->Instance, Init); @@ -442,12 +451,12 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /* wait 74 Cycles: required power up waiting time before starting the MMC initialization sequence */ - sdmmc_clk = sdmmc_clk/(2U*Init.ClockDiv); - HAL_Delay(1U+ (74U*1000U/(sdmmc_clk))); + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); /* Identify card operating voltage */ errorstate = MMC_PowerON(hmmc); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->State = HAL_MMC_STATE_READY; hmmc->ErrorCode |= errorstate; @@ -456,7 +465,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Card initialization */ errorstate = MMC_InitCard(hmmc); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->State = HAL_MMC_STATE_READY; hmmc->ErrorCode |= errorstate; @@ -465,7 +474,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -485,7 +494,7 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) { /* Check the MMC handle allocation */ - if(hmmc == NULL) + if (hmmc == NULL) { return HAL_ERROR; } @@ -499,7 +508,7 @@ HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) MMC_PowerOFF(hmmc); #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - if(hmmc->MspDeInitCallback == NULL) + if (hmmc->MspDeInitCallback == NULL) { hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; } @@ -553,8 +562,8 @@ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) */ /** @addtogroup MMC_Exported_Functions_Group2 - * @brief Data transfer functions - * + * @brief Data transfer functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -579,7 +588,8 @@ __weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -588,22 +598,40 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui uint32_t add = BlockAdd; uint8_t *tempbuff = pData; - if(NULL == pData) + if (NULL == pData) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ @@ -622,10 +650,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; @@ -639,7 +667,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui /* Read Single Block command */ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); } - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -650,12 +678,13 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui /* Poll on SDMMC flags */ dataremaining = config.DataLength; - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) { /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = SDMMC_ReadFIFO(hmmc->Instance); *tempbuff = (uint8_t)(data & 0xFFU); @@ -670,23 +699,23 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui dataremaining -= 32U; } - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; - hmmc->State= HAL_MMC_STATE_READY; + hmmc->State = HAL_MMC_STATE_READY; return HAL_TIMEOUT; } } - __SDMMC_CMDTRANS_DISABLE( hmmc->Instance); + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); /* Send stop transmission command in case of multiblock read */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) { /* Send stop transmission command */ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -697,7 +726,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui } /* Get error state */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -705,7 +734,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -713,7 +742,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -752,7 +781,8 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, ui * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -761,22 +791,40 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u uint32_t add = BlockAdd; uint8_t *tempbuff = pData; - if(NULL == pData) + if (NULL == pData) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ @@ -795,10 +843,10 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; @@ -812,7 +860,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); } - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -823,12 +871,13 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u /* Write block(s) in polling mode */ dataremaining = config.DataLength; - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, + SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) { /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = (uint32_t)(*tempbuff); tempbuff++; @@ -843,7 +892,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u dataremaining -= 32U; } - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -852,14 +901,14 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u return HAL_TIMEOUT; } } - __SDMMC_CMDTRANS_DISABLE( hmmc->Instance); + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); /* Send stop transmission command in case of multiblock write */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) { /* Send stop transmission command */ errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -870,7 +919,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u } /* Get error state */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -878,7 +927,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -886,7 +935,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -926,28 +975,47 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, u * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, + uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ @@ -969,10 +1037,10 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); /* Read Blocks in IT mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT); @@ -987,7 +1055,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); } - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -996,7 +1064,8 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, return HAL_ERROR; } - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_RXFIFOHF)); return HAL_OK; } @@ -1019,28 +1088,47 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, + uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ @@ -1063,12 +1151,12 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { - hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT); + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_IT); /* Write Multi Block command */ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); @@ -1080,7 +1168,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); } - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1090,7 +1178,8 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData } /* Enable transfer interrupts */ - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_TXFIFOHE)); return HAL_OK; } @@ -1113,28 +1202,47 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, + uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_DMA_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ @@ -1157,12 +1265,12 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); hmmc->Instance->IDMABASE0 = (uint32_t) pData ; hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; /* Read Blocks in DMA mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); @@ -1176,7 +1284,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData /* Read Single Block command */ errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); } - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1209,28 +1317,47 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, + uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Initialize data control register */ @@ -1253,13 +1380,13 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); hmmc->Instance->IDMABASE0 = (uint32_t) pData ; hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); @@ -1273,7 +1400,7 @@ HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pDat /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); } - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1308,26 +1435,37 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t start_add = BlockStartAdd; uint32_t end_add = BlockEndAdd; - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - if(end_add < start_add) + if (end_add < start_add) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(end_add > (hmmc->MmcCard.LogBlockNbr)) + if (end_add > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U)) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + hmmc->State = HAL_MMC_STATE_BUSY; /* Check if the card command class supports erase command */ - if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) + if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1336,7 +1474,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, return HAL_ERROR; } - if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1353,7 +1491,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1364,7 +1502,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */ errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1375,7 +1513,7 @@ HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, /* Send CMD38 ERASE */ errorstate = SDMMC_CmdErase(hmmc->Instance, 0UL); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -1405,33 +1543,33 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) uint32_t context = hmmc->Context; /* Check for SDMMC interrupt flags */ - if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) { MMC_Read_IT(hmmc); } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET) { __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND); - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ - SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ - SDMMC_IT_RXFIFOHF); + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \ + SDMMC_IT_RXFIFOHF); __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC); - __SDMMC_CMDTRANS_DISABLE( hmmc->Instance); + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); - if((context & MMC_CONTEXT_DMA) != 0U) + if ((context & MMC_CONTEXT_DMA) != 0U) { hmmc->Instance->DLEN = 0; hmmc->Instance->DCTRL = 0; hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA ; /* Stop Transfer for Write Multi blocks or Read Multi blocks */ - if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) @@ -1446,7 +1584,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); hmmc->State = HAL_MMC_STATE_READY; - if(((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + if (((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->TxCpltCallback(hmmc); @@ -1454,7 +1592,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) HAL_MMC_TxCpltCallback(hmmc); #endif } - if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->RxCpltCallback(hmmc); @@ -1463,13 +1601,13 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) #endif } } - else if((context & MMC_CONTEXT_IT) != 0U) + else if ((context & MMC_CONTEXT_IT) != 0U) { /* Stop Transfer for Write Multi blocks or Read Multi blocks */ - if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + if (((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) @@ -1484,7 +1622,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); hmmc->State = HAL_MMC_STATE_READY; - if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + if (((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->RxCpltCallback(hmmc); @@ -1507,27 +1645,28 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) } } - else if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + else if ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) { MMC_Write_IT(hmmc); } - else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL| SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL | + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) { /* Set Error code */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DCRCFAIL) != RESET) { hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; } - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_DTIMEOUT) != RESET) { hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; } - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_RXOVERR) != RESET) { hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; } - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_IT_TXUNDERR) != RESET) { hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; } @@ -1536,17 +1675,17 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); /* Disable all interrupts */ - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); - __SDMMC_CMDTRANS_DISABLE( hmmc->Instance); + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; hmmc->Instance->CMD |= SDMMC_CMD_CMDSTOP; hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); hmmc->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP); __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DABORT); - if((context & MMC_CONTEXT_IT) != 0U) + if ((context & MMC_CONTEXT_IT) != 0U) { /* Set the MMC state to ready to be able to start again the process */ hmmc->State = HAL_MMC_STATE_READY; @@ -1556,9 +1695,9 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) HAL_MMC_ErrorCallback(hmmc); #endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ } - else if((context & MMC_CONTEXT_DMA) != 0U) + else if ((context & MMC_CONTEXT_DMA) != 0U) { - if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE) { /* Disable Internal DMA */ __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_IDMABTC); @@ -1579,13 +1718,13 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) } } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_IDMABTC) != RESET) { __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_IT_IDMABTC); - if(READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) + if (READ_BIT(hmmc->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) { /* Current buffer is buffer0, Transfer complete for buffer1 */ - if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + if ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->Write_DMADblBuf1CpltCallback(hmmc); @@ -1605,7 +1744,7 @@ void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) else /* MMC_DMA_BUFFER1 */ { /* Current buffer is buffer1, Transfer complete for buffer0 */ - if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + if ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) hmmc->Write_DMADblBuf0CpltCallback(hmmc); @@ -1641,11 +1780,11 @@ HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) } /** -* @brief Return the MMC error code -* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains + * @brief Return the MMC error code + * @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains * the configuration information. -* @retval MMC Error Code -*/ + * @retval MMC Error Code + */ uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) { return hmmc->ErrorCode; @@ -1731,11 +1870,12 @@ __weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, + pMMC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; @@ -1745,64 +1885,64 @@ HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Call /* Process locked */ __HAL_LOCK(hmmc); - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { switch (CallbackId) { - case HAL_MMC_TX_CPLT_CB_ID : - hmmc->TxCpltCallback = pCallback; - break; - case HAL_MMC_RX_CPLT_CB_ID : - hmmc->RxCpltCallback = pCallback; - break; - case HAL_MMC_ERROR_CB_ID : - hmmc->ErrorCallback = pCallback; - break; - case HAL_MMC_ABORT_CB_ID : - hmmc->AbortCpltCallback = pCallback; - break; - case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID : - hmmc->Read_DMADblBuf0CpltCallback = pCallback; - break; - case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID : - hmmc->Read_DMADblBuf1CpltCallback = pCallback; - break; - case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : - hmmc->Write_DMADblBuf0CpltCallback = pCallback; - break; - case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : - hmmc->Write_DMADblBuf1CpltCallback = pCallback; - break; - case HAL_MMC_MSP_INIT_CB_ID : - hmmc->MspInitCallback = pCallback; - break; - case HAL_MMC_MSP_DEINIT_CB_ID : - hmmc->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_MMC_TX_CPLT_CB_ID : + hmmc->TxCpltCallback = pCallback; + break; + case HAL_MMC_RX_CPLT_CB_ID : + hmmc->RxCpltCallback = pCallback; + break; + case HAL_MMC_ERROR_CB_ID : + hmmc->ErrorCallback = pCallback; + break; + case HAL_MMC_ABORT_CB_ID : + hmmc->AbortCpltCallback = pCallback; + break; + case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hmmc->Read_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hmmc->Read_DMADblBuf1CpltCallback = pCallback; + break; + case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hmmc->Write_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hmmc->Write_DMADblBuf1CpltCallback = pCallback; + break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = pCallback; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else if (hmmc->State == HAL_MMC_STATE_RESET) { switch (CallbackId) { - case HAL_MMC_MSP_INIT_CB_ID : - hmmc->MspInitCallback = pCallback; - break; - case HAL_MMC_MSP_DEINIT_CB_ID : - hmmc->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = pCallback; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1843,64 +1983,64 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca /* Process locked */ __HAL_LOCK(hmmc); - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { switch (CallbackId) { - case HAL_MMC_TX_CPLT_CB_ID : - hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; - break; - case HAL_MMC_RX_CPLT_CB_ID : - hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; - break; - case HAL_MMC_ERROR_CB_ID : - hmmc->ErrorCallback = HAL_MMC_ErrorCallback; - break; - case HAL_MMC_ABORT_CB_ID : - hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; - break; - case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID : - hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuf0CpltCallback; - break; - case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID : - hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuf1CpltCallback; - break; - case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : - hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuf0CpltCallback; - break; - case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : - hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuf1CpltCallback; - break; - case HAL_MMC_MSP_INIT_CB_ID : - hmmc->MspInitCallback = HAL_MMC_MspInit; - break; - case HAL_MMC_MSP_DEINIT_CB_ID : - hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; - break; - default : - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_MMC_TX_CPLT_CB_ID : + hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; + break; + case HAL_MMC_RX_CPLT_CB_ID : + hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; + break; + case HAL_MMC_ERROR_CB_ID : + hmmc->ErrorCallback = HAL_MMC_ErrorCallback; + break; + case HAL_MMC_ABORT_CB_ID : + hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; + break; + case HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hmmc->Read_DMADblBuf0CpltCallback = HAL_MMCEx_Read_DMADoubleBuf0CpltCallback; + break; + case HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hmmc->Read_DMADblBuf1CpltCallback = HAL_MMCEx_Read_DMADoubleBuf1CpltCallback; + break; + case HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hmmc->Write_DMADblBuf0CpltCallback = HAL_MMCEx_Write_DMADoubleBuf0CpltCallback; + break; + case HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hmmc->Write_DMADblBuf1CpltCallback = HAL_MMCEx_Write_DMADoubleBuf1CpltCallback; + break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = HAL_MMC_MspInit; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else if (hmmc->State == HAL_MMC_STATE_RESET) { switch (CallbackId) { - case HAL_MMC_MSP_INIT_CB_ID : - hmmc->MspInitCallback = HAL_MMC_MspInit; - break; - case HAL_MMC_MSP_DEINIT_CB_ID : - hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; - break; - default : - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = HAL_MMC_MspInit; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1922,8 +2062,8 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca */ /** @addtogroup MMC_Exported_Functions_Group3 - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### Peripheral Control functions ##### @@ -2007,12 +2147,12 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp pCSD->Reserved2 = 0U; /*!< Reserved */ - if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */ + if (MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */ { return HAL_ERROR; } - if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD) + if (hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD) { pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U)); @@ -2030,10 +2170,10 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); + hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); hmmc->MmcCard.LogBlockSize = 512U; } - else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD) + else if (hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD) { hmmc->MmcCard.BlockNbr = block_nbr; hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr; @@ -2061,7 +2201,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U); - pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U); + pCSD->MaxWrBlockLen = (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U); pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U); @@ -2079,7 +2219,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U); - pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U); + pCSD->ECC = (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U); pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U); @@ -2112,7 +2252,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoT * @brief Returns information the information of the card which are stored on * the Extended CSD register. * @param hmmc Pointer to MMC handle - * @param pExtCSD Pointer to a memory area (512 bytes) that contains all + * @param pExtCSD Pointer to a memory area (512 bytes) that contains all * Extended CSD register parameters * @param Timeout Specify timeout value * @retval HAL status @@ -2125,13 +2265,13 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC uint32_t count; uint32_t *tmp_buf; - if(NULL == pExtCSD) + if (NULL == pExtCSD) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { hmmc->ErrorCode = HAL_MMC_ERROR_NONE; @@ -2151,11 +2291,11 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); /* Send ExtCSD Read command to Card */ errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -2165,32 +2305,33 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC } /* Poll on SDMMC flags */ - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | + SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) { /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { *tmp_buf = SDMMC_ReadFIFO(hmmc->Instance); tmp_buf++; } } - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; - hmmc->State= HAL_MMC_STATE_READY; + hmmc->State = HAL_MMC_STATE_READY; return HAL_TIMEOUT; } } - __SDMMC_CMDTRANS_DISABLE( hmmc->Instance); + __SDMMC_CMDTRANS_DISABLE(hmmc->Instance); /* Get error state */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -2198,7 +2339,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -2206,7 +2347,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtC hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -2268,17 +2409,17 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DEFAULT); } - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { - if(WideMode == SDMMC_BUS_WIDE_8B) + if (WideMode == SDMMC_BUS_WIDE_8B) { errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); } - else if(WideMode == SDMMC_BUS_WIDE_4B) + else if (WideMode == SDMMC_BUS_WIDE_4B) { errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); } - else if(WideMode == SDMMC_BUS_WIDE_1B) + else if (WideMode == SDMMC_BUS_WIDE_1B) { errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); } @@ -2289,14 +2430,14 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 } /* Check for switch error and violation of the trial number of sending CMD 13 */ - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ count = SDMMC_MAX_TRIAL; do { errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { break; } @@ -2304,7 +2445,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 /* Get command response */ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); count--; - }while(((response & 0x100U) == 0U) && (count != 0U)); + } while (((response & 0x100U) == 0U) && (count != 0U)); /* Check the status after the switch command execution */ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) @@ -2336,7 +2477,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 /* Change State */ hmmc->State = HAL_MMC_STATE_READY; - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -2383,16 +2524,20 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed DDR mode allowed */ errorstate = MMC_HighSpeed(hmmc, ENABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } else { - errorstate = MMC_DDR_Mode(hmmc, ENABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U) { - hmmc->ErrorCode |= errorstate; + /* DDR mode not supported with CLKDIV = 0 */ + errorstate = MMC_DDR_Mode(hmmc, ENABLE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } } } } @@ -2400,7 +2545,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed mode allowed */ errorstate = MMC_HighSpeed(hmmc, ENABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } @@ -2417,16 +2562,20 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed DDR mode allowed */ errorstate = MMC_HighSpeed(hmmc, ENABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } else { - errorstate = MMC_DDR_Mode(hmmc, ENABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_CLKDIV) != 0U) { - hmmc->ErrorCode |= errorstate; + /* DDR mode not supported with CLKDIV = 0 */ + errorstate = MMC_DDR_Mode(hmmc, ENABLE); + if (errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } } } } @@ -2444,7 +2593,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed mode allowed */ errorstate = MMC_HighSpeed(hmmc, ENABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } @@ -2463,7 +2612,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed DDR mode activated */ errorstate = MMC_DDR_Mode(hmmc, DISABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } @@ -2472,7 +2621,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint3 { /* High Speed mode activated */ errorstate = MMC_HighSpeed(hmmc, DISABLE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } @@ -2514,7 +2663,7 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) uint32_t resp1 = 0U; errorstate = MMC_SendStatus(hmmc, &resp1); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } @@ -2535,8 +2684,8 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) HAL_MMC_CardStateTypeDef CardState; /* DIsable All interrupts */ - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); /* Clear All flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); @@ -2550,11 +2699,11 @@ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) hmmc->Context = MMC_CONTEXT_NONE; CardState = HAL_MMC_GetCardState(hmmc); - if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) { hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); } - if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE) { return HAL_ERROR; } @@ -2572,8 +2721,8 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) HAL_MMC_CardStateTypeDef CardState; /* DIsable All interrupts */ - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); /* If IDMA Context, disable Internal DMA */ hmmc->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; @@ -2584,11 +2733,11 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) CardState = HAL_MMC_GetCardState(hmmc); hmmc->State = HAL_MMC_STATE_READY; - if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + if ((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) { hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); } - if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + if (hmmc->ErrorCode != HAL_MMC_ERROR_NONE) { return HAL_ERROR; } @@ -2611,17 +2760,20 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) * @param hmmc Pointer to MMC handle * @param EraseType Specifies the type of erase to be performed * This parameter can be one of the following values: - * @arg HAL_MMC_ERASE Erase the erase groups identified by CMD35 & 36 - * @arg HAL_MMC_TRIM Erase the write blocks identified by CMD35 & 36 - * @arg HAL_MMC_DISCARD Discard the write blocks identified by CMD35 & 36 - * @arg HAL_MMC_SECURE_ERASE Perform a secure purge according SRT on the erase groups identified by CMD35 & 36 - * @arg HAL_MMC_SECURE_TRIM_STEP1 Mark the write blocks identified by CMD35 & 36 for secure erase - * @arg HAL_MMC_SECURE_TRIM_STEP2 Perform a secure purge according SRT on the write blocks previously identified + * @arg HAL_MMC_TRIM Erase the write blocks identified by CMD35 & 36 + * @arg HAL_MMC_ERASE Erase the erase groups identified by CMD35 & 36 + * @arg HAL_MMC_DISCARD Discard the write blocks identified by CMD35 & 36 + * @arg HAL_MMC_SECURE_ERASE Perform a secure purge according SRT on the erase groups identified + * by CMD35 & 36 + * @arg HAL_MMC_SECURE_TRIM_STEP1 Mark the write blocks identified by CMD35 & 36 for secure erase + * @arg HAL_MMC_SECURE_TRIM_STEP2 Perform a secure purge according SRT on the write blocks + * previously identified * @param BlockStartAdd Start Block address * @param BlockEndAdd End Block address * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, uint32_t BlockEndAdd) +HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, + uint32_t BlockStartAdd, uint32_t BlockEndAdd) { uint32_t errorstate; uint32_t start_add = BlockStartAdd; @@ -2632,34 +2784,45 @@ HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseT assert_param(IS_MMC_ERASE_TYPE(EraseType)); /* Check the coherence between start and end address */ - if(end_add < start_add) + if (end_add < start_add) { hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; return HAL_ERROR; } /* Check that the end address is not out of range of device memory */ - if(end_add > (hmmc->MmcCard.LogBlockNbr)) + if (end_add > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if (((start_add % 8U) != 0U) || ((end_add % 8U) != 0U)) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + /* Check if the card command class supports erase command */ - if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) + if (((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) { hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; return HAL_ERROR; } /* Check the state of the driver */ - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { /* Change State */ hmmc->State = HAL_MMC_STATE_BUSY; /* Check that the card is not locked */ - if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + if ((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED; hmmc->State = HAL_MMC_STATE_READY; @@ -2675,22 +2838,22 @@ HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseT /* Send CMD35 MMC_ERASE_GRP_START with start address as argument */ errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* Send CMD36 MMC_ERASE_GRP_END with end address as argument */ errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* Send CMD38 ERASE with erase type as argument */ errorstate = SDMMC_CmdErase(hmmc->Instance, EraseType); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { if ((EraseType == HAL_MMC_SECURE_ERASE) || (EraseType == HAL_MMC_SECURE_TRIM_STEP2)) { /* Wait that the device is ready by checking the D0 line */ - while((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) { - if((HAL_GetTick()-tickstart) >= SDMMC_MAXERASETIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT) { errorstate = HAL_MMC_ERROR_TIMEOUT; } @@ -2707,13 +2870,13 @@ HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseT hmmc->State = HAL_MMC_STATE_READY; /* Manage errors */ - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; - if(errorstate != HAL_MMC_ERROR_TIMEOUT) + if (errorstate != HAL_MMC_ERROR_TIMEOUT) { return HAL_ERROR; } @@ -2746,19 +2909,19 @@ HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc) uint32_t tickstart = HAL_GetTick(); /* Check the state of the driver */ - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { /* Change State */ hmmc->State = HAL_MMC_STATE_BUSY; /* Index : 165 - Value : 0x01 */ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03A50100U); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* Wait that the device is ready by checking the D0 line */ - while((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) + while ((!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_BUSYD0END)) && (errorstate == HAL_MMC_ERROR_NONE)) { - if((HAL_GetTick()-tickstart) >= SDMMC_MAXERASETIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_MAXERASETIMEOUT) { errorstate = HAL_MMC_ERROR_TIMEOUT; } @@ -2767,14 +2930,14 @@ HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc) /* Clear the flag corresponding to end D0 bus line */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_BUSYD0END); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ count = SDMMC_MAX_TRIAL; do { errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { break; } @@ -2782,7 +2945,7 @@ HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc) /* Get command response */ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); count--; - }while(((response & 0x100U) == 0U) && (count != 0U)); + } while (((response & 0x100U) == 0U) && (count != 0U)); /* Check the status after the switch command execution */ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) @@ -2808,13 +2971,13 @@ HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc) hmmc->State = HAL_MMC_STATE_READY; /* Manage errors */ - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); hmmc->ErrorCode |= errorstate; - if(errorstate != HAL_MMC_ERROR_TIMEOUT) + if (errorstate != HAL_MMC_ERROR_TIMEOUT) { return HAL_ERROR; } @@ -2842,8 +3005,10 @@ HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc) * @param SRTMode Specifies the type of erase to be performed * This parameter can be one of the following values: * @arg HAL_MMC_SRT_ERASE Information removed by an erase - * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed by an erase - * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, its complement then a random character + * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character + * followed by an erase + * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, + * its complement then a random character * @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined * @retval HAL status */ @@ -2855,28 +3020,28 @@ HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t assert_param(IS_MMC_SRT_TYPE(SRTMode)); /* Check the state of the driver */ - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { /* Get the supported values by the device */ - if(HAL_MMC_GetSupportedSecRemovalType(hmmc, &srt) == HAL_OK) + if (HAL_MMC_GetSupportedSecRemovalType(hmmc, &srt) == HAL_OK) { /* Change State */ hmmc->State = HAL_MMC_STATE_BUSY; /* Check the value passed as parameter is supported by the device */ - if((SRTMode & srt) != 0U) + if ((SRTMode & srt) != 0U) { /* Index : 16 - Value : SRTMode */ srt |= ((POSITION_VAL(SRTMode)) << 4U); errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03100000U | (srt << 8U))); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ count = SDMMC_MAX_TRIAL; do { errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { break; } @@ -2884,7 +3049,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t /* Get command response */ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); count--; - }while(((response & 0x100U) == 0U) && (count != 0U)); + } while (((response & 0x100U) == 0U) && (count != 0U)); /* Check the status after the switch command execution */ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) @@ -2919,7 +3084,7 @@ HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t } /* Manage errors */ - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -2943,15 +3108,17 @@ HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t * @param SupportedSRT pointer for supported SRT value * This parameter is a bit field of the following values: * @arg HAL_MMC_SRT_ERASE Information removed by an erase - * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed by an erase - * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, its complement then a random character + * @arg HAL_MMC_SRT_WRITE_CHAR_ERASE Information removed by an overwriting with a character followed + * by an erase + * @arg HAL_MMC_SRT_WRITE_CHAR_COMPL_RANDOM Information removed by an overwriting with a character, + * its complement then a random character * @arg HAL_MMC_SRT_VENDOR_DEFINED Information removed using a vendor defined * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT) { /* Check the state of the driver */ - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { /* Change State */ hmmc->State = HAL_MMC_STATE_BUSY; @@ -2997,7 +3164,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) MMC_InitTypeDef Init; /* Check the power State */ - if(SDMMC_GetPowerState(hmmc->Instance) == 0U) + if (SDMMC_GetPowerState(hmmc->Instance) == 0U) { /* Power off */ return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; @@ -3005,7 +3172,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Send CMD2 ALL_SEND_CID */ errorstate = SDMMC_CmdSendCID(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } @@ -3021,7 +3188,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */ /* MMC Card publishes its RCA. */ errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } @@ -3031,7 +3198,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Send CMD9 SEND_CSD with argument as card's RCA */ errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } @@ -3047,9 +3214,9 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Get the Card Class */ hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U); - /* Select the Card */ + /* Select the Card */ errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } @@ -3062,12 +3229,12 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } - + /* Get Extended CSD parameters */ if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK) { @@ -3076,7 +3243,7 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } @@ -3105,21 +3272,21 @@ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } - while(validvoltage == 0U) + while (validvoltage == 0U) { - if(count++ == SDMMC_MAX_VOLT_TRIAL) + if (count++ == SDMMC_MAX_VOLT_TRIAL) { return HAL_MMC_ERROR_INVALID_VOLTRANGE; } /* SEND CMD1 APP_CMD with voltage range as argument */ errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { return HAL_MMC_ERROR_UNSUPPORTED_FEATURE; } @@ -3166,14 +3333,14 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) { uint32_t errorstate; - if(pCardStatus == NULL) + if (pCardStatus == NULL) { return HAL_MMC_ERROR_PARAM; } /* Send Status command */ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { return errorstate; } @@ -3192,7 +3359,8 @@ static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) * @param Timeout: Specify timeout value * @retval HAL status */ -static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout) +static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, + uint16_t FieldIndex, uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; @@ -3217,7 +3385,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel /* Set Block Size for Card */ errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -3227,17 +3395,17 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel } /* Poll on SDMMC flags */ - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) { /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { tmp_data = SDMMC_ReadFIFO(hmmc->Instance); - /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ - /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */ - if ((i + count) == ((uint32_t)FieldIndex/4U)) + /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ + /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */ + if ((i + count) == ((uint32_t)FieldIndex / 4U)) { *pFieldData = tmp_data; } @@ -3245,18 +3413,18 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel i += 8U; } - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; - hmmc->State= HAL_MMC_STATE_READY; + hmmc->State = HAL_MMC_STATE_READY; return HAL_TIMEOUT; } } /* Get error state */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -3264,7 +3432,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -3272,7 +3440,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel hmmc->State = HAL_MMC_STATE_READY; return HAL_ERROR; } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) + else if (__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) { /* Clear all the static flags */ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); @@ -3287,7 +3455,7 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->ErrorCode |= errorstate; } @@ -3309,14 +3477,14 @@ static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFiel static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) { uint32_t count, data; - uint8_t* tmp; + uint8_t *tmp; tmp = hmmc->pRxBuffPtr; if (hmmc->RxXferSize >= 32U) { /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = SDMMC_ReadFIFO(hmmc->Instance); *tmp = (uint8_t)(data & 0xFFU); @@ -3343,14 +3511,14 @@ static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) { uint32_t count, data; - uint8_t* tmp; + uint8_t *tmp; tmp = hmmc->pTxBuffPtr; if (hmmc->TxXferSize >= 32U) { /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = (uint32_t)(*tmp); tmp++; @@ -3378,36 +3546,37 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) { uint32_t errorstate = HAL_MMC_ERROR_NONE; uint32_t response = 0U, count; + uint32_t sdmmc_clk; SDMMC_InitTypeDef Init; if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE)) { errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_DEFAULT); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* Index : 185 - Value : 0 */ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U); } } - + if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE)) { errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_HIGH); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* Index : 185 - Value : 1 */ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U); } } - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ count = SDMMC_MAX_TRIAL; do { errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { break; } @@ -3415,7 +3584,7 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) /* Get command response */ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); count--; - }while(((response & 0x100U) == 0U) && (count != 0U)); + } while (((response & 0x100U) == 0U) && (count != 0U)); /* Check the status after the switch command execution */ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) @@ -3437,15 +3606,24 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) { Init.ClockDiv = hmmc->Init.ClockDiv; (void)SDMMC_Init(hmmc->Instance, Init); - + CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED); } else { - Init.ClockDiv = SDMMC_HSpeed_CLK_DIV; - (void)SDMMC_Init(hmmc->Instance, Init); - - SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED); + /* High Speed Clock should be less or equal to 52MHz*/ + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1); + if (sdmmc_clk == 0U) + { + errorstate = SDMMC_ERROR_INVALID_PARAMETER; + } + else + { + Init.ClockDiv = sdmmc_clk / (2U * MMC_HIGH_SPEED_FREQ); + (void)SDMMC_Init(hmmc->Instance, Init); + + SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_BUSSPEED); + } } } } @@ -3478,7 +3656,7 @@ static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U) { errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_HIGH); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* Index : 183 - Value : 1 */ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); @@ -3487,7 +3665,7 @@ static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) else { errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_HIGH); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* Index : 183 - Value : 2 */ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); @@ -3500,7 +3678,7 @@ static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U) { errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_DDR); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* Index : 183 - Value : 5 */ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U); @@ -3509,7 +3687,7 @@ static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) else { errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_DDR); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* Index : 183 - Value : 6 */ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U); @@ -3517,14 +3695,14 @@ static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) } } - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ count = SDMMC_MAX_TRIAL; do { errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { break; } @@ -3532,7 +3710,7 @@ static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state) /* Get command response */ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); count--; - }while(((response & 0x100U) == 0U) && (count != 0U)); + } while (((response & 0x100U) == 0U) && (count != 0U)); /* Check the status after the switch command execution */ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) @@ -3582,12 +3760,12 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 uint32_t errorstate = HAL_MMC_ERROR_NONE; uint32_t power_class, supported_pwr_class; - if((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B)) + if ((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B)) { power_class = 0U; /* Default value after power-on or software reset */ /* Read the PowerClass field of the Extended CSD register */ - if(MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */ + if (MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */ { errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; } @@ -3600,24 +3778,27 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 if (Speed == SDMMC_SPEED_MODE_DDR) { /* Field PWR_CL_DDR_52_xxx [238 or 239] */ - supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_DDR_52_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_DDR_52_POS) & 0x000000FFU); + supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_DDR_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_DDR_52_POS) & + 0x000000FFU); } else if (Speed == SDMMC_SPEED_MODE_HIGH) { /* Field PWR_CL_52_xxx [200 or 202] */ - supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_52_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_52_POS) & 0x000000FFU); + supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_52_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_52_POS) & + 0x000000FFU); } else { /* Field PWR_CL_26_xxx [201 or 203] */ - supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_26_POS) & 0x000000FFU); + supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX / 4)] >> MMC_EXT_CSD_PWR_CL_26_POS) & + 0x000000FFU); } - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { - if(Wide == SDMMC_BUS_WIDE_8B) + if (Wide == SDMMC_BUS_WIDE_8B) { - /* Bit [7:4] : power class for 8-bits bus configuration - Bit [3:0] : power class for 4-bits bus configuration */ + /* Bit [7:4]: power class for 8-bits bus configuration - Bit [3:0]: power class for 4-bits bus configuration */ supported_pwr_class = (supported_pwr_class >> 4U); } @@ -3626,14 +3807,14 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 /* Need to change current power class */ errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U))); - if(errorstate == HAL_MMC_ERROR_NONE) + if (errorstate == HAL_MMC_ERROR_NONE) { /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ count = SDMMC_MAX_TRIAL; do { errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { break; } @@ -3641,7 +3822,7 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 /* Get command response */ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); count--; - }while(((response & 0x100U) == 0U) && (count != 0U)); + } while (((response & 0x100U) == 0U) && (count != 0U)); /* Check the status after the switch command execution */ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc.h index 0acdd1409d..cc9c9fbe91 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc.h @@ -15,14 +15,14 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef STM32L5xx_HAL_MMC_H #define STM32L5xx_HAL_MMC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -54,7 +54,7 @@ typedef enum HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */ HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfer State */ HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */ -}HAL_MMC_StateTypeDef; +} HAL_MMC_StateTypeDef; /** * @} */ @@ -102,7 +102,7 @@ typedef struct uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ -}HAL_MMC_CardInfoTypeDef; +} HAL_MMC_CardInfoTypeDef; /** * @brief MMC handle Structure definition @@ -142,19 +142,19 @@ typedef struct uint32_t Ext_CSD[128]; #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* Read_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* Read_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* Write_DMADblBuf0CpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* Write_DMADblBuf1CpltCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* TxCpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* RxCpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* ErrorCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* AbortCpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* Read_DMADblBuf0CpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* Read_DMADblBuf1CpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* Write_DMADblBuf0CpltCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* Write_DMADblBuf1CpltCallback)(struct __MMC_HandleTypeDef *hmmc); - void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc); -#endif -}MMC_HandleTypeDef; + void (* MspInitCallback)(struct __MMC_HandleTypeDef *hmmc); + void (* MspDeInitCallback)(struct __MMC_HandleTypeDef *hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ +} MMC_HandleTypeDef; /** @@ -204,7 +204,7 @@ typedef struct __IO uint8_t CSD_CRC; /*!< CSD CRC */ __IO uint8_t Reserved4; /*!< Always 1 */ -}HAL_MMC_CardCSDTypeDef; +} HAL_MMC_CardCSDTypeDef; /** * @} */ @@ -225,7 +225,7 @@ typedef struct __IO uint8_t CID_CRC; /*!< CID CRC */ __IO uint8_t Reserved2; /*!< Always 1 */ -}HAL_MMC_CardCIDTypeDef; +} HAL_MMC_CardCIDTypeDef; /** * @} */ @@ -247,7 +247,7 @@ typedef enum HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */ HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */ -}HAL_MMC_CallbackIDTypeDef; +} HAL_MMC_CallbackIDTypeDef; /** * @} */ @@ -255,11 +255,11 @@ typedef enum /** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition * @{ */ -typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); +typedef void (*pMMC_CallbackTypeDef)(MMC_HandleTypeDef *hmmc); /** * @} */ -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @} */ @@ -282,13 +282,13 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); #define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ #define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ #define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ -#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the - number of transferred bytes does not match the block length */ +#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ +/*!< number of transferred bytes does not match the block length */ #define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ #define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ #define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ -#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock - command or if there was an attempt to access a locked card */ +#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ +/*!< command or if there was an attempt to access a locked card */ #define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ #define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ #define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ @@ -299,8 +299,8 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); #define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ #define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ #define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ -#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out - of erase sequence command was received */ +#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ +/*!< of erase sequence command was received */ #define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ #define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ #define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ @@ -313,7 +313,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) #define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @} */ @@ -403,22 +403,22 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); /* Exported macro ------------------------------------------------------------*/ /** @defgroup MMC_Exported_macros MMC Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ /** @brief Reset MMC handle state. * @param __HANDLE__ MMC Handle. * @retval None */ #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) #define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_MMC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) + (__HANDLE__)->State = HAL_MMC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET) -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @brief Enable the MMC device interrupt. @@ -632,7 +632,7 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); */ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc); HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc); void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc); void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); @@ -644,15 +644,21 @@ void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); * @{ */ /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks, uint32_t Timeout); HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); /* Non-Blocking mode: IT */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); @@ -664,9 +670,10 @@ void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc); #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) /* MMC callback registering/unregistering */ -HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, + pMMC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ /** * @} */ @@ -713,7 +720,8 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); /** @defgroup MMC_Exported_Functions_Group7 Peripheral Erase management * @{ */ -HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +HAL_StatusTypeDef HAL_MMC_EraseSequence(MMC_HandleTypeDef *hmmc, uint32_t EraseType, uint32_t BlockStartAdd, + uint32_t BlockEndAdd); HAL_StatusTypeDef HAL_MMC_Sanitize(MMC_HandleTypeDef *hmmc); HAL_StatusTypeDef HAL_MMC_ConfigSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t SRTMode); HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT); @@ -734,7 +742,8 @@ HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, ui /** @defgroup MMC_Private_Defines MMC Private Defines * @{ */ - +#define MMC_EXT_CSD_DATA_SEC_SIZE_INDEX 61 +#define MMC_EXT_CSD_DATA_SEC_SIZE_POS 8 /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc_ex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc_ex.c index b8fd8f2ea0..0f4029154b 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc_ex.c @@ -15,7 +15,8 @@ The MMC Extension HAL driver can be used as follows: (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function. - (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions. + (+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and + HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions. @endverbatim ****************************************************************************** @@ -60,8 +61,8 @@ /** @addtogroup MMCEx_Exported_Functions_Group1 - * @brief Multibuffer functions - * + * @brief Multibuffer functions + * @verbatim ============================================================================== ##### Multibuffer functions ##### @@ -82,13 +83,14 @@ * @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size. * @retval HAL status */ -HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize) +HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0, + uint32_t *pDataBuffer1, uint32_t BufferSize) { - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { - hmmc->Instance->IDMABASE0= (uint32_t) pDataBuffer0 ; - hmmc->Instance->IDMABASE1= (uint32_t) pDataBuffer1 ; - hmmc->Instance->IDMABSIZE= (uint32_t) (MMC_BLOCKSIZE * BufferSize); + hmmc->Instance->IDMABASE0 = (uint32_t) pDataBuffer0 ; + hmmc->Instance->IDMABASE1 = (uint32_t) pDataBuffer1 ; + hmmc->Instance->IDMABSIZE = (uint32_t)(MMC_BLOCKSIZE * BufferSize); return HAL_OK; } @@ -100,27 +102,48 @@ HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32 /** * @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1. - * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before + * call this function. * @param hmmc: MMC handle * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status */ -HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; - uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t DmaBase0_reg; + uint32_t DmaBase1_reg; uint32_t errorstate; uint32_t add = BlockAdd; - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + DmaBase0_reg = hmmc->Instance->IDMABASE0; DmaBase1_reg = hmmc->Instance->IDMABASE1; @@ -152,7 +175,7 @@ HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, ui hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; @@ -161,14 +184,15 @@ HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, ui /* Read Multi Block command */ errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->State = HAL_MMC_STATE_READY; hmmc->ErrorCode |= errorstate; return HAL_ERROR; } - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); return HAL_OK; } @@ -181,27 +205,48 @@ HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, ui /** * @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1. - * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before + * call this function. * @param hmmc: MMC handle * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status -*/ -HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks) + */ +HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; - uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t DmaBase0_reg; + uint32_t DmaBase1_reg; uint32_t add = BlockAdd; - if(hmmc->State == HAL_MMC_STATE_READY) + if (hmmc->State == HAL_MMC_STATE_READY) { - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + if ((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; } + /* Check the case of 4kB blocks (field DATA SECTOR SIZE of extended CSD register) */ + if (((hmmc->Ext_CSD[(MMC_EXT_CSD_DATA_SEC_SIZE_INDEX / 4)] >> MMC_EXT_CSD_DATA_SEC_SIZE_POS) & 0x000000FFU) != 0x0U) + { + if ((NumberOfBlocks % 8U) != 0U) + { + /* The number of blocks should be a multiple of 8 sectors of 512 bytes = 4 KBytes */ + hmmc->ErrorCode |= HAL_MMC_ERROR_BLOCK_LEN_ERR; + return HAL_ERROR; + } + + if ((BlockAdd % 8U) != 0U) + { + /* The address should be aligned to 8 (corresponding to 4 KBytes blocks) */ + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_MISALIGNED; + return HAL_ERROR; + } + } + DmaBase0_reg = hmmc->Instance->IDMABASE0; DmaBase1_reg = hmmc->Instance->IDMABASE1; @@ -232,7 +277,7 @@ HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, u config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hmmc->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hmmc->Instance); + __SDMMC_CMDTRANS_ENABLE(hmmc->Instance); hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; @@ -241,14 +286,15 @@ HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, u /* Write Multi Block command */ errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); - if(errorstate != HAL_MMC_ERROR_NONE) + if (errorstate != HAL_MMC_ERROR_NONE) { hmmc->State = HAL_MMC_STATE_READY; hmmc->ErrorCode |= errorstate; return HAL_ERROR; } - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)); return HAL_OK; } @@ -270,9 +316,10 @@ HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, u * transfer use BUFFER0. * @retval HAL status */ -HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer) +HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, + uint32_t *pDataBuffer) { - if(Buffer == MMC_DMA_BUFFER0) + if (Buffer == MMC_DMA_BUFFER0) { /* change the buffer0 address */ hmmc->Instance->IDMABASE0 = (uint32_t)pDataBuffer; diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc_ex.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc_ex.h index 91d0990632..bc007e3ffe 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_mmc_ex.h @@ -22,7 +22,7 @@ #define STM32L5xx_HAL_MMC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -50,7 +50,7 @@ typedef enum MMC_DMA_BUFFER0 = 0x00U, /*!< selects MMC internal DMA Buffer 0 */ MMC_DMA_BUFFER1 = 0x01U, /*!< selects MMC internal DMA Buffer 1 */ -}HAL_MMCEx_DMABuffer_MemoryTypeDef; +} HAL_MMCEx_DMABuffer_MemoryTypeDef; /** @@ -60,8 +60,6 @@ typedef enum /** * @} */ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions * @{ @@ -70,10 +68,14 @@ typedef enum /** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions * @{ */ -HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize); -HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer); +HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t *pDataBuffer0, + uint32_t *pDataBuffer1, uint32_t BufferSize); +HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, + uint32_t *pDataBuffer); void HAL_MMCEx_Read_DMADoubleBuf0CpltCallback(MMC_HandleTypeDef *hmmc); void HAL_MMCEx_Read_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc); diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nand.c index 19a5fb874e..a169a1930e 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nand.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nand.c @@ -181,7 +181,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT #else /* Initialize the low level hardware (MSP) */ HAL_NAND_MspInit(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ } /* Initialize NAND control Interface */ @@ -221,7 +221,7 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) #else /* Initialize the low level hardware (MSP) */ HAL_NAND_MspDeInit(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Configure the NAND registers with their reset values */ (void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank); @@ -284,7 +284,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Rising edge pending bit */ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE); @@ -298,7 +298,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Level pending bit */ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL); @@ -312,7 +312,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Falling edge pending bit */ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE); @@ -326,7 +326,7 @@ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt FIFO empty pending bit */ __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT); @@ -380,7 +380,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN { __IO uint32_t data = 0; __IO uint32_t data1 = 0; - uint32_t deviceAddress; + uint32_t deviceaddress; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -396,18 +396,18 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Send Read ID command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; __DSB(); /* Read the electronic signature from NAND flash */ if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) { - data = *(__IO uint32_t *)deviceAddress; + data = *(__IO uint32_t *)deviceaddress; /* Return the data read */ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); @@ -417,8 +417,8 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN } else { - data = *(__IO uint32_t *)deviceAddress; - data1 = *((__IO uint32_t *)deviceAddress + 4); + data = *(__IO uint32_t *)deviceaddress; + data1 = *((__IO uint32_t *)deviceaddress + 4); /* Return the data read */ pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); @@ -449,7 +449,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN */ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) { - uint32_t deviceAddress; + uint32_t deviceaddress; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -465,10 +465,10 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Send NAND reset command */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -519,7 +519,10 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesRead = 0U, nandAddress, nbpages = NumPageToRead; + uint32_t deviceaddress; + uint32_t numpagesread = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -536,16 +539,16 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) read loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); /* Cards with page size <= 512 bytes */ @@ -553,22 +556,22 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -576,31 +579,31 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); @@ -625,25 +628,25 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint8_t *)deviceAddress; + *buff = *(uint8_t *)deviceaddress; buff++; } /* Increment read pages number */ - numPagesRead++; + numpagesread++; /* Decrement pages to read */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -674,7 +677,10 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesRead = 0, nandAddress, nbpages = NumPageToRead; + uint32_t deviceaddress; + uint32_t numpagesread = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -691,16 +697,16 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) read loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); /* Cards with page size <= 512 bytes */ @@ -708,22 +714,22 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -731,31 +737,31 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); if (hnand->Config.ExtraCommandEnable == ENABLE) @@ -779,25 +785,36 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } + /* Calculate PageSize */ + if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) + { + hnand->Config.PageSize = hnand->Config.PageSize / 2U; + } + else + { + /* Do nothing */ + /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ + } + /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint16_t *)deviceAddress; + *buff = *(uint16_t *)deviceaddress; buff++; } /* Increment read pages number */ - numPagesRead++; + numpagesread++; /* Decrement pages to read */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -828,7 +845,10 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite; + uint32_t deviceaddress; + uint32_t numpageswritten = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -845,18 +865,18 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) write loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); /* Cards with page size <= 512 bytes */ @@ -864,22 +884,22 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -887,26 +907,26 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -914,12 +934,12 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address /* Write data to memory */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *(__IO uint8_t *)deviceAddress = *buff; + *(__IO uint8_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -941,13 +961,13 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address } /* Increment written pages number */ - numPagesWritten++; + numpageswritten++; /* Decrement pages to write */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -978,7 +998,10 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite; + uint32_t deviceaddress; + uint32_t numpageswritten = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -995,18 +1018,18 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Page(s) write loop */ - while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); /* Cards with page size <= 512 bytes */ @@ -1014,22 +1037,22 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1037,39 +1060,50 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres { if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } + /* Calculate PageSize */ + if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) + { + hnand->Config.PageSize = hnand->Config.PageSize / 2U; + } + else + { + /* Do nothing */ + /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ + } + /* Write data to memory */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *(__IO uint16_t *)deviceAddress = *buff; + *(__IO uint16_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -1091,13 +1125,13 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_Addres } /* Increment written pages number */ - numPagesWritten++; + numpageswritten++; /* Decrement pages to write */ nbpages--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1128,7 +1162,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead; + uint32_t deviceaddress; + uint32_t numsparearearead = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1145,78 +1183,78 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = COLUMN_ADDRESS(hnand); + columnaddress = COLUMN_ADDRESS(hnand); /* Spare area(s) read loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); if (hnand->Config.ExtraCommandEnable == ENABLE) @@ -1240,25 +1278,25 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint8_t *)deviceAddress; + *buff = *(uint8_t *)deviceaddress; buff++; } /* Increment read spare areas number */ - numSpareAreaRead++; + numsparearearead++; /* Decrement spare areas to read */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1289,7 +1327,11 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead; + uint32_t deviceaddress; + uint32_t numsparearearead = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1306,78 +1348,78 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U); + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); /* Spare area(s) read loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; __DSB(); if (hnand->Config.ExtraCommandEnable == ENABLE) @@ -1401,25 +1443,25 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_Ad } /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); __DSB(); } /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint16_t *)deviceAddress; + *buff = *(uint16_t *)deviceaddress; buff++; } /* Increment read spare areas number */ - numSpareAreaRead++; + numsparearearead++; /* Decrement spare areas to read */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1450,7 +1492,11 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; uint8_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1467,77 +1513,77 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Page address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = COLUMN_ADDRESS(hnand); + columnaddress = COLUMN_ADDRESS(hnand); /* Spare area(s) write loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1545,12 +1591,12 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad /* Write data to memory */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *(__IO uint8_t *)deviceAddress = *buff; + *(__IO uint8_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -1572,13 +1618,13 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad } /* Increment written spare areas number */ - numSpareAreaWritten++; + numspareareawritten++; /* Decrement spare areas to write */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1609,7 +1655,11 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A { uint32_t index; uint32_t tickstart; - uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; uint16_t *buff = pBuffer; /* Check the NAND controller state */ @@ -1626,77 +1676,77 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - deviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* NAND raw address calculation */ - nandAddress = ARRAY_ADDRESS(pAddress, hnand); + nandaddress = ARRAY_ADDRESS(pAddress, hnand); /* Column in page address */ - columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U); + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); /* Spare area(s) write loop */ - while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { /* Cards with page size <= 512 bytes */ if ((hnand->Config.PageSize) <= 512U) { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U; + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } else /* (hnand->Config.PageSize) > 512 */ { /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; __DSB(); if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); } else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ { - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); __DSB(); } } @@ -1704,12 +1754,12 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A /* Write data to memory */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *(__IO uint16_t *)deviceAddress = *buff; + *(__IO uint16_t *)deviceaddress = *buff; buff++; __DSB(); } - *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; __DSB(); /* Get tick */ @@ -1731,13 +1781,13 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A } /* Increment written spare areas number */ - numSpareAreaWritten++; + numspareareawritten++; /* Decrement spare areas to write */ nbspare--; /* Increment the NAND address */ - nandAddress = (uint32_t)(nandAddress + 1U); + nandaddress = (uint32_t)(nandaddress + 1U); } /* Update the NAND controller state */ @@ -1763,7 +1813,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A */ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { - uint32_t DeviceAddress; + uint32_t deviceaddress; /* Check the NAND controller state */ if (hnand->State == HAL_NAND_STATE_BUSY) @@ -1779,19 +1829,19 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy hnand->State = HAL_NAND_STATE_BUSY; /* Identify the device address */ - DeviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Send Erase block command sequence */ - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); __DSB(); - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; __DSB(); /* Update the NAND controller state */ @@ -1980,7 +2030,7 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAN __HAL_UNLOCK(hnand); return status; } -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} @@ -2142,17 +2192,17 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) { uint32_t data; - uint32_t DeviceAddress; + uint32_t deviceaddress; UNUSED(hnand); /* Identify the device address */ - DeviceAddress = NAND_DEVICE; + deviceaddress = NAND_DEVICE; /* Send Read status operation command */ - *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; /* Read status register data */ - data = *(__IO uint8_t *)DeviceAddress; + data = *(__IO uint8_t *)deviceaddress; /* Return the status */ if ((data & NAND_ERROR) == NAND_ERROR) diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nand.h index 947f9c6a61..d462900cb0 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nand.h @@ -133,7 +133,7 @@ typedef struct void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ } NAND_HandleTypeDef; #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) @@ -151,7 +151,7 @@ typedef enum * @brief HAL NAND Callback pointer definition */ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} @@ -175,7 +175,7 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); } while(0) #else #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} @@ -242,7 +242,7 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressT HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} @@ -287,19 +287,19 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); #define CMD_AREA (1UL<<16U) /* A16 = CLE high */ #define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ -#define NAND_CMD_AREA_A 0x00U -#define NAND_CMD_AREA_B 0x01U -#define NAND_CMD_AREA_C 0x50U -#define NAND_CMD_AREA_TRUE1 0x30U +#define NAND_CMD_AREA_A ((uint8_t)0x00) +#define NAND_CMD_AREA_B ((uint8_t)0x01) +#define NAND_CMD_AREA_C ((uint8_t)0x50) +#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) -#define NAND_CMD_WRITE0 0x80U -#define NAND_CMD_WRITE_TRUE1 0x10U -#define NAND_CMD_ERASE0 0x60U -#define NAND_CMD_ERASE1 0xD0U -#define NAND_CMD_READID 0x90U -#define NAND_CMD_STATUS 0x70U -#define NAND_CMD_LOCK_STATUS 0x7AU -#define NAND_CMD_RESET 0xFFU +#define NAND_CMD_WRITE0 ((uint8_t)0x80) +#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) +#define NAND_CMD_ERASE0 ((uint8_t)0x60) +#define NAND_CMD_ERASE1 ((uint8_t)0xD0) +#define NAND_CMD_READID ((uint8_t)0x90) +#define NAND_CMD_STATUS ((uint8_t)0x70) +#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) +#define NAND_CMD_RESET ((uint8_t)0xFF) /* NAND memory status */ #define NAND_VALID_ADDRESS 0x00000100UL @@ -324,7 +324,8 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ - (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) + (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * \ + ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) /** * @brief NAND memory Column address computation. diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nor.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nor.c index 9bcbfd5fe3..3e05cb8a3f 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nor.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nor.c @@ -472,9 +472,12 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I { /* Read the NOR IDs */ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); - pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); - pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); - pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); + pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE1_ADDR); + pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE2_ADDR); + pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE3_ADDR); } /* Check the NOR controller state */ @@ -739,7 +742,9 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) { - uint32_t deviceaddress, size = uwBufferSize, address = uwAddress; + uint32_t deviceaddress; + uint32_t size = uwBufferSize; + uint32_t address = uwAddress; uint16_t *data = pData; HAL_NOR_StateTypeDef state; HAL_StatusTypeDef status = HAL_OK; @@ -870,7 +875,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr /* Initialize variables */ p_currentaddress = (uint16_t *)(deviceaddress + uwAddress); - p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U*(uwBufferSize - 1U))); + p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U))); if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { @@ -900,7 +905,7 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr while (p_currentaddress <= p_endaddress) { NOR_WRITE(p_currentaddress, *data); - + data++; p_currentaddress ++; } @@ -1389,7 +1394,8 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) { HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; - uint16_t tmpSR1, tmpSR2; + uint16_t tmpsr1; + uint16_t tmpsr2; uint32_t tickstart; /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ @@ -1414,29 +1420,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres } /* Read NOR status register (DQ6 and DQ5) */ - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) { return HAL_NOR_STATUS_SUCCESS ; } - if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) { status = HAL_NOR_STATUS_ONGOING; } - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) { return HAL_NOR_STATUS_SUCCESS; } - if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) { return HAL_NOR_STATUS_ERROR; } @@ -1447,21 +1453,21 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres do { NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); - tmpSR2 = *(__IO uint16_t*)(Address); + tmpsr2 = *(__IO uint16_t *)(Address); /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { return HAL_NOR_STATUS_TIMEOUT; } } - } while ((tmpSR2 & NOR_MASK_STATUS_DQ7) == 0U); + } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U); NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); - tmpSR1 = *(__IO uint16_t*)(Address); - if((tmpSR1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U) + tmpsr1 = *(__IO uint16_t *)(Address); + if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U) { /* Clear the Status Register */ NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nor.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nor.h index 60f4651942..421ddba42e 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nor.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_nor.h @@ -125,7 +125,7 @@ typedef struct #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */ void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */ -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ } NOR_HandleTypeDef; #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) @@ -142,7 +142,7 @@ typedef enum * @brief HAL NOR Callback pointer definition */ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ @@ -164,7 +164,7 @@ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); } while(0) #else #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ @@ -213,7 +213,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ @@ -257,23 +257,23 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres #define DEVICE_CODE3_ADDR ((uint16_t)0x000F) /* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x61) -#define CFI2_ADDRESS ((uint16_t)0x62) -#define CFI3_ADDRESS ((uint16_t)0x63) -#define CFI4_ADDRESS ((uint16_t)0x64) +#define CFI1_ADDRESS ((uint16_t)0x0061) +#define CFI2_ADDRESS ((uint16_t)0x0062) +#define CFI3_ADDRESS ((uint16_t)0x0063) +#define CFI4_ADDRESS ((uint16_t)0x0064) /* NOR operation wait timeout */ #define NOR_TMEOUT ((uint16_t)0xFFFF) /* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x0) -#define NOR_MEMORY_16B ((uint8_t)0x1) +#define NOR_MEMORY_8B ((uint8_t)0x00) +#define NOR_MEMORY_16B ((uint8_t)0x01) /* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000) -#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000) -#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000) -#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000) +#define NOR_MEMORY_ADRESS1 (0x60000000U) +#define NOR_MEMORY_ADRESS2 (0x64000000U) +#define NOR_MEMORY_ADRESS3 (0x68000000U) +#define NOR_MEMORY_ADRESS4 (0x6C000000U) /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp.c index 7733ee0cbe..a8b8c68636 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp.c @@ -1154,11 +1154,6 @@ HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ - -/** - * @} - */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp.h index 86cd223951..32238ca5a8 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp.h @@ -145,10 +145,6 @@ void (* MspDeInitCallback) (struct __OPAMP_HandleTypeDef *hopamp); typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef; -/** - * @} - */ - #if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1) /** * @brief HAL OPAMP Callback ID enumeration definition @@ -166,6 +162,10 @@ typedef enum typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ @@ -223,8 +223,8 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp); /** @defgroup OPAMP_PowerMode OPAMP PowerMode * @{ */ -#define OPAMP_POWERMODE_NORMAL 0x00000000U -#define OPAMP_POWERMODE_LOWPOWER OPAMP_CSR_OPALPM +#define OPAMP_POWERMODE_NORMALPOWER 0x00000000U /*!< OPAMP power mode normal */ +#define OPAMP_POWERMODE_LOWPOWER OPAMP_CSR_OPALPM /*!< OPAMP power mode low-power */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp_ex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp_ex.c index e595694383..02f716c040 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp_ex.c @@ -45,11 +45,11 @@ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions +/** @defgroup OPAMPEx_Exported_Functions OPAMPEx Extended Exported Functions * @{ */ -/** @addtogroup OPAMPEx_Exported_Functions_Group1 +/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended operation functions * @brief Extended operation functions * @verbatim @@ -365,7 +365,7 @@ HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPA * @} */ -/** @defgroup OPAMPEx_Exported_Functions_Group2 Peripheral Control functions +/** @defgroup OPAMPEx_Exported_Functions_Group2 Extended Peripheral Control functions * @brief Peripheral Control functions * @verbatim diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp_ex.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp_ex.h index 524b9fd365..83615b6e9b 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_opamp_ex.h @@ -39,12 +39,12 @@ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions +/** @addtogroup OPAMPEx_Exported_Functions * @{ */ /* I/O operation functions *****************************************************/ -/** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions +/** @addtogroup OPAMPEx_Exported_Functions_Group1 * @{ */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd.c index 6434928bf2..cb3538954f 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd.c @@ -206,7 +206,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) { (void)HAL_PCDEx_ActivateLPM(hpcd); } - + return HAL_OK; } @@ -298,7 +298,9 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -508,7 +510,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_Ca * @param pCallback pointer to the USB PCD Data OUT Stage Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -581,7 +584,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd * @param pCallback pointer to the USB PCD Data IN Stage Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -654,7 +658,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -727,7 +732,8 @@ HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -1357,7 +1363,8 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) * @param ep_type endpoint type * @retval HAL status */ -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type) { HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; @@ -1534,10 +1541,7 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) __HAL_LOCK(hpcd); (void)USB_EPSetStall(hpcd->Instance, ep); - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t *)hpcd->Setup); - } + __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1672,6 +1676,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) { wIstr = hpcd->Instance->ISTR; + /* extract highest priority endpoint number */ epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID); @@ -1754,8 +1759,11 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + if ((PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0) & USB_EP_SETUP) == 0U) + { + PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } } } } @@ -1842,9 +1850,8 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* clear int flag */ PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - /* Manage all non bulk transaction or Bulk Single Buffer Transaction */ - if ((ep->type != EP_TYPE_BULK) || - ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U))) + /* Manage Bulk Single Buffer Transaction */ + if ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U)) { /* multi-packet on the NON control IN endpoint */ TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); @@ -1876,7 +1883,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) (void)USB_EPStartXfer(hpcd->Instance, ep); } } - /* bulk in double buffer enable in case of transferLen> Ep_Mps */ + /* Double Buffer Iso/bulk IN (bulk transfer Len > Ep_Mps) */ else { (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); @@ -1922,7 +1929,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /* Check if Buffer1 is in blocked sate which requires to toggle */ + /* Check if Buffer1 is in blocked state which requires to toggle */ if ((wEPVal & USB_EP_DTOG_TX) != 0U) { PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U); @@ -2000,6 +2007,9 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, /* Transfer is completed */ if (ep->xfer_len == 0U) { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2070,6 +2080,9 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, /* Transfer is completed */ if (ep->xfer_len == 0U) { + PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2077,7 +2090,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, HAL_PCD_DataInStageCallback(hpcd, ep->num); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - /*need to Free USB Buff*/ + /* need to Free USB Buff */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U); diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd.h index 119848f3c2..80cc2e68fb 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd.h @@ -260,25 +260,41 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType * @} */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, + pPCD_BcdCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, + pPCD_LpmCallbackTypeDef pCallback); + HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /** @@ -317,16 +333,24 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type); + HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint8_t *pBuf, uint32_t len); + +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint8_t *pBuf, uint32_t len); + + HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); + +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); /** * @} */ @@ -412,10 +436,10 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) /* GetENDPOINT */ -#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) /* ENDPOINT transfer */ -#define USB_EP0StartXfer USB_EPStartXfer +#define USB_EP0StartXfer USB_EPStartXfer /** * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) @@ -424,8 +448,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wType Endpoint Type. * @retval None */ -#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), \ - ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) +#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) /** * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) @@ -442,18 +465,19 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum, bDir * @retval None */ -#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) do { \ - if ((bDir) == 0U) \ - { \ - /* OUT double buffered endpoint */ \ - PCD_TX_DTOG((USBx), (bEpNum)); \ - } \ - else if ((bDir) == 1U) \ - { \ - /* IN double buffered endpoint */ \ - PCD_RX_DTOG((USBx), (bEpNum)); \ - } \ -} while(0) +#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT double buffered endpoint */ \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + else if ((bDir) == 1U) \ + { \ + /* IN double buffered endpoint */ \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /** * @brief sets the status for tx transfer (bits STAT_TX[1:0]). @@ -462,21 +486,22 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wState new state * @retval None */ -#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \ - uint16_t _wRegVal; \ - \ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \ + do { \ + uint16_t _wRegVal; \ + \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \ - /* toggle first bit ? */ \ - if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ - { \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ + { \ _wRegVal ^= USB_EPTX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ - { \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ + { \ _wRegVal ^= USB_EPTX_DTOG2; \ - } \ - PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ } while(0) /* PCD_SET_EP_TX_STATUS */ /** @@ -486,19 +511,20 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wState new state * @retval None */ -#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \ +#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \ /* toggle first bit ? */ \ if ((USB_EPRX_DTOG1 & (wState))!= 0U) \ { \ - _wRegVal ^= USB_EPRX_DTOG1; \ + _wRegVal ^= USB_EPRX_DTOG1; \ } \ /* toggle second bit ? */ \ if ((USB_EPRX_DTOG2 & (wState))!= 0U) \ { \ - _wRegVal ^= USB_EPRX_DTOG2; \ + _wRegVal ^= USB_EPRX_DTOG2; \ } \ PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ } while(0) /* PCD_SET_EP_RX_STATUS */ @@ -511,7 +537,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wStatetx new state. * @retval None */ -#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \ +#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \ @@ -573,7 +600,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_SET_EP_KIND(USBx, bEpNum) do { \ +#define PCD_SET_EP_KIND(USBx, bEpNum) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ @@ -581,7 +609,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \ } while(0) /* PCD_SET_EP_KIND */ -#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \ +#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \ @@ -613,7 +642,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \ +#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \ @@ -621,7 +651,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \ } while(0) /* PCD_CLEAR_RX_EP_CTR */ -#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \ +#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \ @@ -635,7 +666,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_RX_DTOG(USBx, bEpNum) do { \ +#define PCD_RX_DTOG(USBx, bEpNum) \ + do { \ uint16_t _wEPVal; \ \ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ @@ -643,7 +675,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \ } while(0) /* PCD_RX_DTOG */ -#define PCD_TX_DTOG(USBx, bEpNum) do { \ +#define PCD_TX_DTOG(USBx, bEpNum) \ + do { \ uint16_t _wEPVal; \ \ _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ @@ -656,7 +689,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bEpNum Endpoint Number. * @retval None */ -#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \ +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ @@ -667,7 +701,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } \ } while(0) /* PCD_CLEAR_RX_DTOG */ -#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \ +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ @@ -685,7 +720,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param bAddr Address. * @retval None */ -#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \ +#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \ + do { \ uint16_t _wRegVal; \ \ _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \ @@ -711,23 +747,25 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wAddr address to be set (must be word aligned). * @retval None */ -#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \ - __IO uint16_t *_wRegVal; \ - uint32_t _wRegBase = (uint32_t)USBx; \ - \ - _wRegBase += (uint32_t)(USBx)->BTABLE; \ - _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ - *_wRegVal = ((wAddr) >> 1) << 1; \ -} while(0) /* PCD_SET_EP_TX_ADDRESS */ +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \ + do { \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ + } while(0) /* PCD_SET_EP_TX_ADDRESS */ -#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \ - __IO uint16_t *_wRegVal; \ - uint32_t _wRegBase = (uint32_t)USBx; \ - \ - _wRegBase += (uint32_t)(USBx)->BTABLE; \ - _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ - *_wRegVal = ((wAddr) >> 1) << 1; \ -} while(0) /* PCD_SET_EP_RX_ADDRESS */ +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \ + do { \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ + } while(0) /* PCD_SET_EP_RX_ADDRESS */ /** * @brief Gets address of the tx/rx buffer. @@ -745,7 +783,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wNBlocks no. of Blocks. * @retval None */ -#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) do { \ +#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ + do { \ (wNBlocks) = (wCount) >> 5; \ if (((wCount) & 0x1fU) == 0U) \ { \ @@ -754,7 +793,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \ } while(0) /* PCD_CALC_BLK32 */ -#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) do { \ +#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ + do { \ (wNBlocks) = (wCount) >> 1; \ if (((wCount) & 0x1U) != 0U) \ { \ @@ -763,7 +803,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); *(pdwReg) = (uint16_t)((wNBlocks) << 10); \ } while(0) /* PCD_CALC_BLK2 */ -#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) do { \ +#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \ + do { \ uint32_t wNBlocks; \ if ((wCount) == 0U) \ { \ @@ -780,10 +821,11 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } \ } while(0) /* PCD_SET_EP_CNT_RX_REG */ -#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \ - uint32_t _wRegBase = (uint32_t)(USBx); \ - __IO uint16_t *pdwReg; \ - \ +#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *pdwReg; \ + \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \ @@ -796,23 +838,25 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wCount Counter value. * @retval None */ -#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \ +#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \ + do { \ uint32_t _wRegBase = (uint32_t)(USBx); \ __IO uint16_t *_wRegVal; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ *_wRegVal = (uint16_t)(wCount); \ -} while(0) + } while(0) -#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \ +#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \ + do { \ uint32_t _wRegBase = (uint32_t)(USBx); \ __IO uint16_t *_wRegVal; \ \ _wRegBase += (uint32_t)(USBx)->BTABLE; \ _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \ -} while(0) + } while(0) /** * @brief gets counter of the tx buffer. @@ -830,10 +874,13 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wBuf0Addr buffer 0 address. * @retval Counter value */ -#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) do { \ +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \ + do { \ PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \ } while(0) /* PCD_SET_EP_DBUF0_ADDR */ -#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) do { \ + +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \ + do { \ PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \ } while(0) /* PCD_SET_EP_DBUF1_ADDR */ @@ -845,7 +892,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wBuf1Addr = buffer 1 address. * @retval None */ -#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) do { \ +#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \ + do { \ PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \ PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \ } while(0) /* PCD_SET_EP_DBUF_ADDR */ @@ -868,7 +916,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @param wCount: Counter value * @retval None */ -#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) do { \ +#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ if ((bDir) == 0U) \ /* OUT endpoint */ \ { \ @@ -884,7 +933,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } \ } while(0) /* SetEPDblBuf0Count*/ -#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \ +#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ uint32_t _wBase = (uint32_t)(USBx); \ __IO uint16_t *_wEPRegVal; \ \ @@ -905,7 +955,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); } \ } while(0) /* SetEPDblBuf1Count */ -#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \ +#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ } while(0) /* PCD_SET_EP_DBUF_CNT */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd_ex.c index 3f7e5007ff..0035920d8c 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd_ex.c @@ -78,10 +78,8 @@ * @retval HAL status */ -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress) +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, + uint16_t ep_kind, uint32_t pmaadress) { PCD_EPTypeDef *ep; diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd_ex.h index 0dbfc943bd..11ddb2e5e3 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_pcd_ex.h @@ -49,10 +49,8 @@ extern "C" { -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, - uint16_t ep_addr, - uint16_t ep_kind, - uint32_t pmaadress); +HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, + uint16_t ep_kind, uint32_t pmaadress); HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc.c index 696606aacf..bab519c89f 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc.c @@ -65,8 +65,8 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** @defgroup RCC_Private_Constants RCC Private Constants - * @{ - */ + * @{ + */ #define LSI_TIMEOUT_VALUE 7UL /* 7 ms (maximum 6ms + 1) */ #define HSI48_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ #define PLL_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ @@ -255,7 +255,11 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) { if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) + { + return HAL_TIMEOUT; + } } } @@ -283,12 +287,17 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_SYSCLKSOURCE_STATUS_MSI) + { + return HAL_TIMEOUT; + } } } /* Reset HSION, HSIKERON, HSIASFS, HSEON, HSECSSON, PLLON, PLLSAIxON bits */ - CLEAR_BIT(RCC->CR, RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON); + CLEAR_BIT(RCC->CR, RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_PLLON | + RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON); /* Insure PLLRDY, PLLSAI1RDY and PLLSAI2RDY (if present) are reset */ /* Get start tick */ @@ -297,19 +306,33 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) #if defined(RCC_PLLSAI2_SUPPORT) while (READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY | RCC_CR_PLLSAI2RDY) != 0U) + { + return HAL_TIMEOUT; + } + } + } #else while (READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) - -#endif { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLRDY | RCC_CR_PLLSAI1RDY) != 0U) + { + return HAL_TIMEOUT; + } } } +#endif /* RCC_PLLSAI2_SUPPORT */ + /* Reset PLLCFGR register */ CLEAR_REG(RCC->PLLCFGR); SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN_4); @@ -334,7 +357,11 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void) { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + { + return HAL_TIMEOUT; + } } } @@ -500,7 +527,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) + { + return HAL_TIMEOUT; + } } } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ @@ -522,7 +553,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) + { + return HAL_TIMEOUT; + } } } } @@ -559,7 +594,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + return HAL_TIMEOUT; + } } } } @@ -573,7 +612,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) + { + return HAL_TIMEOUT; + } } } } @@ -618,7 +661,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + return HAL_TIMEOUT; + } } } @@ -638,7 +685,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) + { + return HAL_TIMEOUT; + } } } } @@ -674,7 +725,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U) + { + return HAL_TIMEOUT; + } } } } @@ -691,7 +746,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U) + { + return HAL_TIMEOUT; + } } } } @@ -724,7 +783,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + return HAL_TIMEOUT; + } } } } @@ -761,7 +824,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + return HAL_TIMEOUT; + } } } @@ -775,7 +842,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) + { + return HAL_TIMEOUT; + } } } } @@ -789,7 +860,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + { + return HAL_TIMEOUT; + } } } } @@ -804,7 +879,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) + { + return HAL_TIMEOUT; + } } } @@ -818,7 +897,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + { + return HAL_TIMEOUT; + } } } } @@ -850,7 +933,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U) + { + return HAL_TIMEOUT; + } } } } @@ -867,7 +954,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U) + { + return HAL_TIMEOUT; + } } } } @@ -902,7 +993,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + return HAL_TIMEOUT; + } } } @@ -928,7 +1023,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U) + { + return HAL_TIMEOUT; + } } } } @@ -953,7 +1052,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) + { + return HAL_TIMEOUT; + } } } } @@ -1162,7 +1265,11 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + return HAL_TIMEOUT; + } } } } @@ -1222,8 +1329,8 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui */ /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions - * + * @brief RCC clocks control functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -1647,8 +1754,8 @@ __weak void HAL_RCC_CSSCallback(void) */ /** @defgroup RCC_Exported_Functions_Group3 Attributes management functions - * @brief Attributes management functions. - * + * @brief Attributes management functions. + * @verbatim =============================================================================== ##### RCC attributes functions ##### diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc.h index b92ec92cee..3c36765c19 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc.h @@ -652,59 +652,59 @@ typedef struct */ #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_DMA2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_FLASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_TSC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_GTZC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) @@ -734,128 +734,128 @@ typedef struct */ #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOHEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_ADC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADCEN); \ + UNUSED(tmpreg); \ + } while(0) #if defined(AES) #define __HAL_RCC_AES_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* AES */ #if defined(HASH) #define __HAL_RCC_HASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* HASH */ #define __HAL_RCC_RNG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_PKA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_PKAEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTFDEC1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) @@ -905,20 +905,20 @@ typedef struct */ #define __HAL_RCC_FMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) @@ -937,238 +937,238 @@ typedef struct */ #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_TIM5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_SPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_I2C4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_CRS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_PWR_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_DAC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_DAC1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_OPAMPEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM3EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ + UNUSED(tmpreg); \ + } while(0) #if defined(USB) #define __HAL_RCC_USB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_USBFSEN); \ + UNUSED(tmpreg); \ + } while(0) #endif /* USB */ #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) @@ -1242,93 +1242,93 @@ typedef struct */ #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_TIM15_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_TIM16_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_TIM17_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_SAI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_SAI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ - UNUSED(tmpreg); \ - } while(0) + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN); \ + UNUSED(tmpreg); \ + } while(0) #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) @@ -1814,9 +1814,9 @@ typedef struct * @{ */ #define __HAL_RCC_APB1_FORCE_RESET() do { \ - WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFUL); \ - WRITE_REG(RCC->APB1RSTR2, 0xFFFFFFFFUL); \ - } while(0) + WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFUL); \ + WRITE_REG(RCC->APB1RSTR2, 0xFFFFFFFFUL); \ + } while(0) #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) @@ -1876,9 +1876,9 @@ typedef struct #define __HAL_RCC_APB1_RELEASE_RESET() do { \ - WRITE_REG(RCC->APB1RSTR1, 0x00000000UL); \ - WRITE_REG(RCC->APB1RSTR2, 0x00000000UL); \ - } while(0) + WRITE_REG(RCC->APB1RSTR1, 0x00000000UL); \ + WRITE_REG(RCC->APB1RSTR2, 0x00000000UL); \ + } while(0) #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) @@ -2740,7 +2740,7 @@ typedef struct * @retval None */ #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos) /** * @brief Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI) @@ -2798,7 +2798,7 @@ typedef struct * @retval None */ #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__) \ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8) + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(__MSICALIBRATIONVALUE__) << 8) /** * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode @@ -2827,10 +2827,10 @@ typedef struct * @retval None */ #define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ - do { \ - SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ - MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ - } while(0) + do { \ + SET_BIT(RCC->CR, RCC_CR_MSIRGSEL); \ + MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \ + } while(0) /** * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode @@ -2844,7 +2844,7 @@ typedef struct * @retval None */ #define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \ - MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) + MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U) /** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode * @retval MSI clock range. @@ -2863,9 +2863,9 @@ typedef struct * @arg @ref RCC_MSIRANGE_11 MSI clock is around 48 MHz */ #define __HAL_RCC_GET_MSI_RANGE() \ - ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \ - (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \ - (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4)) + ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ? \ + (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) : \ + (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4)) /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). * @note After enabling the LSI, the application software should wait on @@ -2904,22 +2904,22 @@ typedef struct * @retval None */ #define __HAL_RCC_HSE_CONFIG(__STATE__) \ - do { \ - if((__STATE__) == RCC_HSE_ON) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if((__STATE__) == RCC_HSE_BYPASS) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - } while(0) + do { \ + if((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0) /** * @brief Macro to configure the External Low Speed oscillator (LSE). @@ -2942,22 +2942,22 @@ typedef struct * @retval None */ #define __HAL_RCC_LSE_CONFIG(__STATE__) \ - do { \ - if((__STATE__) == RCC_LSE_ON) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else if((__STATE__) == RCC_LSE_BYPASS) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - } while(0) + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0) /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. @@ -2995,7 +2995,7 @@ typedef struct * @retval None */ #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ - MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) + MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) /** @brief Macro to get the RTC clock source. @@ -3031,7 +3031,7 @@ typedef struct * */ #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) /** @brief Macro to configure the PLL source division factor M. * @note This function must be used only when the main PLL is disabled. @@ -3044,7 +3044,7 @@ typedef struct * */ #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos) + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos) /** * @brief Macro to configure the main PLL clock source, multiplication and division factors. @@ -3085,15 +3085,15 @@ typedef struct * @retval None */ #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \ - MODIFY_REG(RCC->PLLCFGR, \ - (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ - RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \ - ((__PLLSOURCE__) | \ - (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ - ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ - ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ - ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ - ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos))) + MODIFY_REG(RCC->PLLCFGR, \ + (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \ + RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \ + ((__PLLSOURCE__) | \ + (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \ + ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos))) /** @brief Macro to get the oscillator used as PLL clock source. * @retval The oscillator used as PLL clock source. The returned value can be one @@ -3147,7 +3147,7 @@ typedef struct * @retval None */ #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) /** @brief Macro to get the clock source used as system clock. * @retval The clock source used as system clock. The returned value can be one @@ -3174,7 +3174,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) /** * @brief Macro to configure the wake up from stop clock. @@ -3185,7 +3185,7 @@ typedef struct * @retval None */ #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__STOPWUCLK__)) /** @brief Macro to configure the MCO clock. @@ -3209,7 +3209,7 @@ typedef struct * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 */ #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management * @brief macros to manage the specified RCC Flags and interrupts. @@ -3312,11 +3312,11 @@ typedef struct * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \ - ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \ - (1UL << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \ - ? 1U : 0U) + ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \ + ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \ + ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \ + (1UL << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \ + ? 1U : 0U) /** * @} @@ -3371,7 +3371,8 @@ typedef struct #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) -#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) +#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) \ + <= (uint32_t)( RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos)) #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc_ex.c index 32c7083e15..584ee45398 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc_ex.c @@ -40,8 +40,8 @@ /* Private typedef -----------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /** @defgroup RCCEx_Private_Constants RCCEx Private Constants - * @{ - */ + * @{ + */ #define PLLSAI1_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ #define PLLSAI2_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ #define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */ @@ -71,8 +71,8 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /** @defgroup RCCEx_Private_Functions RCCEx Private Functions - * @{ - */ + * @{ + */ static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource); static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *pPllSai1, uint32_t Divider); static uint32_t RCCEx_PLLSAI1_GetVCOFreq(void); @@ -91,8 +91,8 @@ static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t */ /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * + * @brief Extended Peripheral Control functions + * @verbatim =============================================================================== ##### Extended Peripheral Control functions ##### @@ -276,7 +276,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) { - ret = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if ((PWR->CR1 & PWR_CR1_DBP) == 0U) + { + ret = HAL_TIMEOUT; + } break; } } @@ -308,7 +312,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) { - ret = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) + { + ret = HAL_TIMEOUT; + } break; } } @@ -661,7 +669,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the OctoSPI clock source */ __HAL_RCC_OSPI_CONFIG(PeriphClkInit->OspiClockSelection); - + if (PeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL) { /* Enable PLL48M1CLK output clock */ @@ -1597,8 +1605,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) */ /** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions - * @brief Extended Clock management functions - * + * @brief Extended Clock management functions + * @verbatim =============================================================================== ##### Extended clock management functions ##### @@ -1642,7 +1650,11 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) + { + status = HAL_TIMEOUT; + } break; } } @@ -1672,7 +1684,11 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init) { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) + { + status = HAL_TIMEOUT; + } break; } } @@ -1702,7 +1718,11 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void) { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) + { + status = HAL_TIMEOUT; + } break; } } @@ -1743,7 +1763,11 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) { if ((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) + { + status = HAL_TIMEOUT; + } break; } } @@ -1773,7 +1797,11 @@ HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init) { if ((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U) + { + status = HAL_TIMEOUT; + } break; } } @@ -1803,7 +1831,11 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void) { if ((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) + { + status = HAL_TIMEOUT; + } break; } } @@ -2013,8 +2045,8 @@ void HAL_RCCEx_DisableMSIPLLMode(void) #if defined(CRS) /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions - * @brief Extended Clock Recovery System Control functions - * + * @brief Extended Clock Recovery System Control functions + * @verbatim =============================================================================== ##### Extended Clock Recovery System Control functions ##### @@ -2031,7 +2063,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) (+++) Default values can be set for frequency Error Measurement (reload and error limit) and also HSI48 oscillator smooth trimming. (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate - directly reload value with target and sychronization frequencies values + directly reload value with target and synchronization frequencies values (##) Call function HAL_RCCEx_CRSConfig which (+++) Resets CRS registers to their default values. (+++) Configures CRS registers with synchronization configuration @@ -2073,8 +2105,8 @@ void HAL_RCCEx_DisableMSIPLLMode(void) This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) @endverbatim - * @{ - */ + * @{ + */ /** * @brief Start automatic synchronization for polling mode. @@ -2152,24 +2184,25 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo } /** -* @brief Wait for CRS Synchronization status. -* @param Timeout Duration of the timeout -* @note Timeout is based on the maximum time to receive a SYNC event based on synchronization -* frequency. -* @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. -* @retval Combination of Synchronization status -* This parameter can be a combination of the following values: -* @arg @ref RCC_CRS_TIMEOUT -* @arg @ref RCC_CRS_SYNCOK -* @arg @ref RCC_CRS_SYNCWARN -* @arg @ref RCC_CRS_SYNCERR -* @arg @ref RCC_CRS_SYNCMISS -* @arg @ref RCC_CRS_TRIMOVF -*/ + * @brief Wait for CRS Synchronization status. + * @param Timeout Duration of the timeout + * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization + * frequency. + * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. + * @retval Combination of Synchronization status + * This parameter can be a combination of the following values: + * @arg @ref RCC_CRS_TIMEOUT + * @arg @ref RCC_CRS_SYNCOK + * @arg @ref RCC_CRS_SYNCWARN + * @arg @ref RCC_CRS_SYNCERR + * @arg @ref RCC_CRS_SYNCMISS + * @arg @ref RCC_CRS_TRIMOVF + */ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { uint32_t crsstatus = RCC_CRS_NONE; uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; /* Get timeout */ tickstart = HAL_GetTick(); @@ -2181,7 +2214,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - crsstatus = RCC_CRS_TIMEOUT; + status = HAL_TIMEOUT; } } /* Check CRS SYNCOK flag */ @@ -2240,9 +2273,13 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) /* frequency error counter reached a zero value */ __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); } - } - while (RCC_CRS_NONE == crsstatus); + } while ((crsstatus == RCC_CRS_NONE) && (status == HAL_OK)); + if (crsstatus == RCC_CRS_NONE) + { + crsstatus = RCC_CRS_TIMEOUT; + } + return crsstatus; } @@ -2374,8 +2411,8 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) */ /** @addtogroup RCCEx_Private_Functions - * @{ - */ + * @{ + */ static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource) { @@ -2399,7 +2436,11 @@ static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource) { if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) + { + status = HAL_TIMEOUT; + } break; } } @@ -2421,7 +2462,11 @@ static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource) { if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) + { + status = HAL_TIMEOUT; + } break; } } @@ -2443,7 +2488,11 @@ static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource) { if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) + { + status = HAL_TIMEOUT; + } break; } } @@ -2523,7 +2572,11 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *pPllSai1, { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U) + { + status = HAL_TIMEOUT; + } break; } } @@ -2578,7 +2631,11 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *pPllSai1, { if ((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U) + { + status = HAL_TIMEOUT; + } break; } } @@ -2655,7 +2712,11 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *pPllSai2, { if ((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U) + { + status = HAL_TIMEOUT; + } break; } } @@ -2687,7 +2748,11 @@ static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *pPllSai2, { if ((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE) { - status = HAL_TIMEOUT; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U) + { + status = HAL_TIMEOUT; + } break; } } diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc_ex.h index 7984b13ed7..fd0119114a 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rcc_ex.h @@ -271,7 +271,7 @@ typedef struct #define RCC_PERIPHCLK_SAI2 0x00001000U #if defined(USB) #define RCC_PERIPHCLK_USB 0x00002000U -#endif +#endif /* USB */ #define RCC_PERIPHCLK_ADC 0x00004000U #define RCC_PERIPHCLK_DFSDM1 0x00010000U #define RCC_PERIPHCLK_RTC 0x00020000U @@ -683,8 +683,8 @@ typedef struct /* Exported macros -----------------------------------------------------------*/ /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros - * @{ - */ + * @{ + */ /** @@ -724,16 +724,16 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1SOURCE__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, \ - (RCC_PLLSAI1CFGR_PLLSAI1SRC | RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | \ - RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | \ - RCC_PLLSAI1CFGR_PLLSAI1PDIV), \ - ((__PLLSAI1SOURCE__) | \ - (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \ - ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ - ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ - ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ - ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))) + MODIFY_REG(RCC->PLLSAI1CFGR, \ + (RCC_PLLSAI1CFGR_PLLSAI1SRC | RCC_PLLSAI1CFGR_PLLSAI1M | RCC_PLLSAI1CFGR_PLLSAI1N | \ + RCC_PLLSAI1CFGR_PLLSAI1P | RCC_PLLSAI1CFGR_PLLSAI1Q | RCC_PLLSAI1CFGR_PLLSAI1R | \ + RCC_PLLSAI1CFGR_PLLSAI1PDIV), \ + ((__PLLSAI1SOURCE__) | \ + (((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) | \ + ((__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) | \ + ((((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) | \ + ((((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) | \ + ((__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))) /** * @brief Macro to configure the PLLSAI1 clock multiplication factor N. @@ -751,7 +751,7 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) /** @brief Macro to configure the PLLSAI1 input clock division factor M. * @@ -765,7 +765,7 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI1_DIVM_CONFIG(__PLLSAI1M__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M, ((__PLLSAI1M__) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos) /** @brief Macro to configure the PLLSAI1 clock division factor P. * @@ -780,7 +780,7 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV, (__PLLSAI1P__) << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos) /** @brief Macro to configure the PLLSAI1 clock division factor Q. * @@ -795,7 +795,7 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) /** @brief Macro to configure the PLLSAI1 clock division factor R. * @@ -810,7 +810,7 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ - MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) /** * @brief Macros to enable or disable the PLLSAI1. @@ -881,13 +881,13 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2SOURCE__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, \ - (RCC_PLLSAI2CFGR_PLLSAI2SRC | RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | \ - RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ - ((__PLLSAI2SOURCE__) | \ - (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \ - ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ - ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) + MODIFY_REG(RCC->PLLSAI2CFGR, \ + (RCC_PLLSAI2CFGR_PLLSAI2SRC | RCC_PLLSAI2CFGR_PLLSAI2M | RCC_PLLSAI2CFGR_PLLSAI2N | \ + RCC_PLLSAI2CFGR_PLLSAI2P | RCC_PLLSAI2CFGR_PLLSAI2PDIV), \ + ((__PLLSAI2SOURCE__) | \ + (((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) | \ + ((__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) | \ + ((__PLLSAI2P__) << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))) /** * @brief Macro to configure the PLLSAI2 clock multiplication factor N. @@ -905,7 +905,7 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) /** @brief Macro to configure the PLLSAI2 input clock division factor M. * @@ -920,7 +920,7 @@ typedef struct */ #define __HAL_RCC_PLLSAI2_DIVM_CONFIG(__PLLSAI2M__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M, ((__PLLSAI2M__) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos) /** @brief Macro to configure the PLLSAI2 clock division factor P. * @@ -935,7 +935,7 @@ typedef struct * @retval None */ #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ - MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) + MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << RCC_PLLSAI2CFGR_PLLSAI2P_Pos) /** * @brief Macros to enable or disable the PLLSAI2. @@ -988,7 +988,7 @@ typedef struct * @retval None */ #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) /** @brief Macro to get the SAI1 clock source. * @retval The clock source can be one of the following values: @@ -1018,7 +1018,7 @@ typedef struct * @retval None */ #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) /** @brief Macro to get the SAI2 clock source. * @retval The clock source can be one of the following values: @@ -1040,7 +1040,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) /** @brief Macro to get the I2C1 clock source. * @retval The clock source can be one of the following values: @@ -1060,7 +1060,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) /** @brief Macro to get the I2C2 clock source. * @retval The clock source can be one of the following values: @@ -1080,7 +1080,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) /** @brief Macro to get the I2C3 clock source. * @retval The clock source can be one of the following values: @@ -1100,7 +1100,7 @@ typedef struct * @retval None */ #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) /** @brief Macro to get the I2C4 clock source. * @retval The clock source can be one of the following values: @@ -1122,7 +1122,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) /** @brief Macro to get the USART1 clock source. * @retval The clock source can be one of the following values: @@ -1144,7 +1144,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) /** @brief Macro to get the USART2 clock source. * @retval The clock source can be one of the following values: @@ -1166,7 +1166,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) /** @brief Macro to get the USART3 clock source. * @retval The clock source can be one of the following values: @@ -1188,7 +1188,7 @@ typedef struct * @retval None */ #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) /** @brief Macro to get the UART4 clock source. * @retval The clock source can be one of the following values: @@ -1210,7 +1210,7 @@ typedef struct * @retval None */ #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) /** @brief Macro to get the UART5 clock source. * @retval The clock source can be one of the following values: @@ -1232,7 +1232,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) /** @brief Macro to get the LPUART1 clock source. * @retval The clock source can be one of the following values: @@ -1254,7 +1254,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) /** @brief Macro to get the LPTIM1 clock source. * @retval The clock source can be one of the following values: @@ -1276,7 +1276,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) /** @brief Macro to get the LPTIM2 clock source. * @retval The clock source can be one of the following values: @@ -1298,7 +1298,7 @@ typedef struct * @retval None */ #define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM3SEL, (uint32_t)(__LPTIM3_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM3SEL, (uint32_t)(__LPTIM3_CLKSOURCE__)) /** @brief Macro to get the LPTIM3 clock source. * @retval The clock source can be one of the following values: @@ -1319,7 +1319,7 @@ typedef struct * @retval None */ #define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__)) /** @brief Macro to get the FDCAN clock source. * @retval The clock source can be one of the following values: @@ -1341,18 +1341,18 @@ typedef struct * @retval None */ #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ - do \ - { \ - if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ - { \ - SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ - } \ - else \ - { \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__SDMMC1_CLKSOURCE__)); \ - CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ - } \ - } while(0) + do \ + { \ + if((__SDMMC1_CLKSOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP) \ + { \ + SET_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ + } \ + else \ + { \ + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__SDMMC1_CLKSOURCE__)); \ + CLEAR_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL); \ + } \ + } while(0) /** @brief Macro to get the SDMMC1 clock. * @retval The clock source can be one of the following values: @@ -1363,7 +1363,7 @@ typedef struct * @arg @ref RCC_SDMMC1CLKSOURCE_PLLP PLL "P" clock (PLLSAI3CLK) selected as SDMMC1 clock */ #define __HAL_RCC_GET_SDMMC1_SOURCE() \ - ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL)))) + ((READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL) != 0U) ? RCC_SDMMC1CLKSOURCE_PLLP : ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL)))) /** @brief Macro to configure the RNG clock. * @@ -1378,7 +1378,7 @@ typedef struct * @retval None */ #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__RNG_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__RNG_CLKSOURCE__)) /** @brief Macro to get the RNG clock. * @retval The clock source can be one of the following values: @@ -1404,7 +1404,7 @@ typedef struct * @retval None */ #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__USB_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_CLK48MSEL, (uint32_t)(__USB_CLKSOURCE__)) /** @brief Macro to get the USB clock source. * @retval The clock source can be one of the following values: @@ -1426,7 +1426,7 @@ typedef struct * @retval None */ #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) /** @brief Macro to get the ADC clock source. * @retval The clock source can be one of the following values: @@ -1444,7 +1444,7 @@ typedef struct * @retval None */ #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDMSEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDMSEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) /** @brief Macro to get the DFSDM1 clock source. * @retval The clock source can be one of the following values: @@ -1462,7 +1462,7 @@ typedef struct * @retval None */ #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDMSEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDMSEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) /** @brief Macro to get the DFSDM1 audio clock source. * @retval The clock source can be one of the following values: @@ -1481,7 +1481,7 @@ typedef struct * @retval None */ #define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) + MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) /** @brief Macro to get the OctoSPI clock source. * @retval The clock source can be one of the following values: @@ -1771,18 +1771,19 @@ typedef struct * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt */ /* CRS IT Error Mask */ -#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) +#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF\ + | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ - if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ - } \ - } while(0) + if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ + } \ + } while(0) /** * @brief Check whether the specified CRS flag is set or not. @@ -1815,18 +1816,19 @@ typedef struct */ /* CRS Flag Error Mask */ -#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) +#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF\ + | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ - if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__FLAG__)); \ - } \ - } while(0) + if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ + { \ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ + } \ + else \ + { \ + WRITE_REG(CRS->ICR, (__FLAG__)); \ + } \ + } while(0) /** * @brief Enable the oscillator clock for frequency error counter. @@ -1952,165 +1954,165 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ - ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ - (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ - (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ - (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ - (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)) + ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_LPTIM3) == RCC_PERIPHCLK_LPTIM3) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ + (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_DFSDM1AUDIO) == RCC_PERIPHCLK_DFSDM1AUDIO) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ + (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ + (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((__SELECTION__) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) || \ + (((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)) #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) #define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)) #define IS_RCC_SAI1CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) #define IS_RCC_SAI2CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) + (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI1) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ + ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) #define IS_RCC_LPTIM1CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) + (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) #define IS_RCC_LPTIM2CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) + (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) #define IS_RCC_LPTIM3CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE)) + (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE)) #define IS_RCC_FDCANCLK(__SOURCE__) \ - (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLLSAI1)) + (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLLSAI1)) #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI) || \ - ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP)) + (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLP)) #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) + (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) #if defined(USB) #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ - ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) + (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) #endif /* USB */ #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ - ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) + (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ + ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) #define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ - ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) + (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK)) #define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ - ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI)) + (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ + ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_MSI)) #define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \ - ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)) + (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)) #define IS_RCC_PLLSAI1SOURCE(__VALUE__) IS_RCC_PLLSOURCE(__VALUE__) diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rng.c index c009a581ad..b3cc17fa0e 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rng.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rng.c @@ -115,11 +115,7 @@ */ /* Health test control register information to use in CCM algorithm */ #define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ -#if defined(RNG_VER_3_1) || defined(RNG_VER_3_0) -#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */ -#else /* RNG_VER_3_2 */ -#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */ -#endif /* RNG_VER_3_0 || RNG_VER_3_1 */ +#define RNG_HTCFG 0x0000A2B3U /*!< Recommended value for NIST compliancy */ /** * @} */ @@ -134,14 +130,6 @@ */ /* Private macros ------------------------------------------------------------*/ /* Private functions prototypes ----------------------------------------------*/ -/** @addtogroup RNG_Private_Functions - * @{ - */ -HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng); - -/** - * @} - */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup RNG_Exported_Functions @@ -239,9 +227,13 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } } } @@ -261,9 +253,13 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_ERROR; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + { + hrng->State = HAL_RNG_STATE_ERROR; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } } } @@ -307,11 +303,15 @@ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } } } @@ -677,11 +677,15 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } } } diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rng.h index 8de71902d3..101d112369 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rng.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rng.h @@ -363,6 +363,14 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); * @} */ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RNG_Private_Functions RNG Private functions + * @{ + */ +HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng); +/** + * @} + */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rng_ex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rng_ex.c index 718721bcdc..b6ea20ab54 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rng_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rng_ex.c @@ -44,12 +44,8 @@ * @{ */ /* Health test control register information to use in CCM algorithm */ -#define RNG_HTCFG_1 0x17590ABCU /*!< magic number */ -#if defined(RNG_VER_3_1) || defined(RNG_VER_3_0) -#define RNG_HTCFG 0x000CAA74U /*!< for best latency and To be compliant with NIST */ -#else /* RNG_VER_3_2 */ -#define RNG_HTCFG 0x00007274U /*!< for best latency and To be compliant with NIST */ -#endif /* RNG_VER_3_1 || RNG_VER_3_0 */ +#define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ +#define RNG_HTCFG 0x0000A2B3U /*!< Recommended value for NIST compliancy */ /** * @} */ @@ -64,14 +60,6 @@ */ /* Private macros ------------------------------------------------------------*/ /* Private functions prototypes ----------------------------------------------*/ -/** @addtogroup RNG_Private_Functions - * @{ - */ -HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng); - -/** - * @} - */ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ @@ -164,9 +152,13 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - return HAL_ERROR; + /* New check to avoid false timeout detection in case of prememption */ + if (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST)) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + return HAL_ERROR; + } } } diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc.c index 3784bc44be..bf83d475cd 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc.c @@ -872,10 +872,10 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Set the RTC_TR register */ WRITE_REG(RTC->TR, (tmpreg & RTC_TR_RESERVED_MASK)); - /* Clear the bits to be configured */ + /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ CLEAR_BIT(RTC->CR, RTC_CR_BKP); - /* Configure the RTC_CR register */ + /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ SET_BIT(RTC->CR, (sTime->DayLightSaving | sTime->StoreOperation)); /* Exit Initialization mode */ @@ -1074,6 +1074,73 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat return HAL_OK; } +/** + * @brief Daylight Saving Time, Add one hour to the calendar in one single operation + * without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(RTC->CR, RTC_CR_ADD1H); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Substract one hour from the calendar in one + * single operation without going through the initialization procedure. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(RTC->CR, RTC_CR_SUB1H); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Set the store operation bit. + * @note It can be used by the software in order to memorize the DST status. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + SET_BIT(RTC->CR, RTC_CR_BKP); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Clear the store operation bit. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + CLEAR_BIT(RTC->CR, RTC_CR_BKP); + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +} + +/** + * @brief Daylight Saving Time, Read the store operation bit. + * @param hrtc RTC handle + * @retval operation see RTC_StoreOperation_Definitions + */ +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) +{ + UNUSED(hrtc); + return READ_BIT(RTC->CR, RTC_CR_BKP); +} + + /** * @} */ @@ -1186,7 +1253,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + subsecondtmpreg = (uint32_t)(((uint32_t)(sAlarm->AlarmTime.SubSeconds) & RTC_ALRMBSSR_SS_Msk) | (uint32_t)(sAlarm->AlarmSubSecondMask)); /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -1330,7 +1397,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef ((uint32_t)sAlarm->AlarmMask)); } /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + subsecondtmpreg = (uint32_t)(((uint32_t)(sAlarm->AlarmTime.SubSeconds) & RTC_ALRMBSSR_SS_Msk) | (uint32_t)(sAlarm->AlarmSubSecondMask)); /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -1657,7 +1724,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) UNUSED(hrtc); /* Clear RSF flag */ - SET_BIT(RTC->ICSR, RTC_RSF_MASK); + CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF); tickstart = HAL_GetTick(); diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc.h index 0e35129c8f..c4651fc6a2 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc.h @@ -112,12 +112,9 @@ typedef struct with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function */ - uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. - This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ + uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ - uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BKP bit - in CR register to store the operation. - This parameter can be a value of @ref RTC_StoreOperation_Definitions */ + uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ } RTC_TimeTypeDef; /** @@ -557,6 +554,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** * @brief Add 1 hour (summer time change). + * @note This interface is deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions * @param __HANDLE__ specifies the RTC handle. * @param __BKP__ Backup * This parameter can be: @@ -574,6 +573,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to /** * @brief Subtract 1 hour (winter time change). + * @note This interface is deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions * @param __HANDLE__ specifies the RTC handle. * @param __BKP__ Backup * This parameter can be: @@ -747,6 +748,11 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc_ex.c index b39715a988..cc3a806153 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc_ex.c @@ -233,15 +233,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti hrtc->State = HAL_RTC_STATE_BUSY; - /* RTC timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT(); - - /* Get the RTC_CR register and clear the bits to be configured */ - CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE)); - /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /* Get the RTC_CR register and clear the bits to be configured */ + CLEAR_BIT(RTC->CR, (RTC_CR_TSEDGE | RTC_CR_TSE | RTC_CR_TSIE)); + /* Configure the Time Stamp TSEDGE before Enable bit to avoid unwanted TSF setting. */ SET_BIT(RTC->CR, (uint32_t)TimeStampEdge); @@ -251,6 +248,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* RTC timestamp Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT(); + hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1525,32 +1525,29 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + /* Mask flag only supported by TAMPER 1, 2 and 3 */ + assert_param(!((sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (sTamper->Tamper > RTC_TAMPER_3))); assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + /* Trigger and Filter have exclusive configurations */ + assert_param(((sTamper->Filter != RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_LOWLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL))) + || ((sTamper->Filter == RTC_TAMPERFILTER_DISABLE) && ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)))); /* Configuration register 2 */ tmpreg = READ_REG(TAMP->CR2); tmpreg &= ~((sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos) | (sTamper->Tamper << TAMP_CR2_TAMP1NOERASE_Pos)); - if (sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + if ((sTamper->Trigger == RTC_TAMPERTRIGGER_HIGHLEVEL) || (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE)) { tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1TRG_Pos); } if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { - /* Feature only supported by TAMPER 1, 2 and 3 */ - if (sTamper->Tamper < RTC_TAMPER_4) - { - tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); - } - else - { - return HAL_ERROR; - } + tmpreg |= (sTamper->Tamper << TAMP_CR2_TAMP1MSK_Pos); } if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) @@ -1633,7 +1630,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active assert_param(IS_RTC_TAMPER_ERASE_MODE(sAllTamper->TampInput[i].NoErase)); assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sAllTamper->TampInput[i].MaskFlag)); /* Mask flag only supported by TAMPER 1, 2 and 3 */ - assert_param(!((sAllTamper->TampInput[i].MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) && (i > RTC_TAMPER_3))); + assert_param(!((sAllTamper->TampInput[i].MaskFlag == RTC_TAMPERMASK_FLAG_ENABLE) && (i >= RTC_TAMPER_MASKABLE_NB))); } assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sAllTamper->TimeStampOnTamperDetection)); #endif /* #ifdef USE_FULL_ASSERT */ @@ -1775,12 +1772,13 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc) UNUSED(hrtc); /* Disable all actives tampers but not passives tampers */ CLEAR_BIT(TAMP->CR1, ATamp_mask); - /* Disable no erase and mask */ - CLEAR_BIT(TAMP->CR2, (ATamp_mask | ((ATamp_mask & (TAMP_ATCR1_TAMP1AM | TAMP_ATCR1_TAMP2AM | TAMP_ATCR1_TAMP3AM)) << TAMP_CR2_TAMP1MSK_Pos))); /* Clear tamper interrupt and event flags (WO register) of all actives tampers but not passives tampers */ WRITE_REG(TAMP->SCR, ATamp_mask); + /* Disable no erase and mask */ + CLEAR_BIT(TAMP->CR2, (ATamp_mask | ((ATamp_mask & (TAMP_ATCR1_TAMP1AM | TAMP_ATCR1_TAMP2AM | TAMP_ATCR1_TAMP3AM)) << TAMP_CR2_TAMP1MSK_Pos))); + /* Clear all active tampers interrupt mode configuration but not passives tampers */ CLEAR_BIT(TAMP->IER, ATamp_mask); @@ -2516,6 +2514,82 @@ __weak void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc) the HAL_RTCEx_InternalTamper8EventCallback could be implemented in the user file */ } + +/** + * @brief Enable Temperature Monitoring. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_EnableTemperatureMonitoring(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + SET_BIT(TAMP->CFGR, TAMP_CFGR_TMONEN); +} + +/** + * @brief Disable Temperature Monitoring. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_DisableTemperatureMonitoring(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_TMONEN); +} + +/** + * @brief Enable Voltage Monitoring. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_EnableVoltageMonitoring(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + SET_BIT(TAMP->CFGR, TAMP_CFGR_VMONEN); +} + +/** + * @brief Disable Voltage Monitoring. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_DisableVoltageMonitoring(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_VMONEN); +} + +/** + * @brief Enable WUT Monitoring. + * @note Voltage and temperature monitor periodic enable by RTC WakeUp Timer (WUT). + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_EnableWUTMonitoring(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + SET_BIT(TAMP->CFGR, TAMP_CFGR_WUTMONEN); +} + +/** + * @brief Disable WUT Monitoring. + * @note Voltage and temperature monitor periodic Disable by RTC WakeUp Timer (WUT). + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_DisableWUTMonitoring(RTC_HandleTypeDef *hrtc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_WUTMONEN); +} + + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc_ex.h index 41c6d9911f..1ff163aff8 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_rtc_ex.h @@ -383,6 +383,16 @@ typedef struct * @} */ + +/** @defgroup RTCEx_Tamper_Maskable_nb RTCEx Tampers maskable number + * @{ + */ +#define RTC_TAMPER_MASKABLE_NB 3u + +/** + * @} + */ + /** @defgroup RTCEx_Tamper_EraseBackUp RTCEx Tamper EraseBackUp * @{ */ @@ -1395,6 +1405,12 @@ void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_EnableTemperatureMonitoring(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_DisableTemperatureMonitoring(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_EnableVoltageMonitoring(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_DisableVoltageMonitoring(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_EnableWUTMonitoring(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_DisableWUTMonitoring(RTC_HandleTypeDef *hrtc); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd.c index 2789511ddf..06d2f59011 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd.c @@ -268,38 +268,42 @@ /** @addtogroup SD_Private_Defines * @{ */ +/* Frequencies used in the driver for clock divider calculation */ +#define SD_INIT_FREQ 400000U /* Initalization phase : 400 kHz max */ +#define SD_NORMAL_SPEED_FREQ 25000000U /* Normal speed phase : 25 MHz max */ +#define SD_HIGH_SPEED_FREQ 50000000U /* High speed phase : 50 MHz max */ +/* Private macro -------------------------------------------------------------*/ +#if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2) +#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)? \ + DLYB_SDMMC1 : DLYB_SDMMC2 ) +#elif defined (DLYB_SDMMC1) +#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 ) +#endif /* (DLYB_SDMMC1) && defined (DLYB_SDMMC2) */ /** * @} */ -/* Private macro -------------------------------------------------------------*/ -#if defined (DLYB_SDMMC1) && defined (DLYB_SDMMC2) -#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) (((SDMMC_INSTANCE) == SDMMC1)? \ - DLYB_SDMMC1 : DLYB_SDMMC2 ) -#elif defined (DLYB_SDMMC1) -#define SD_GET_DLYB_INSTANCE(SDMMC_INSTANCE) ( DLYB_SDMMC1 ) -#endif /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup SD_Private_Functions SD Private Functions * @{ */ -static uint32_t SD_InitCard (SD_HandleTypeDef *hsd); -static uint32_t SD_PowerON (SD_HandleTypeDef *hsd); -static uint32_t SD_SendSDStatus (SD_HandleTypeDef *hsd, uint32_t *pSDstatus); -static uint32_t SD_SendStatus (SD_HandleTypeDef *hsd, uint32_t *pCardStatus); -static uint32_t SD_WideBus_Enable (SD_HandleTypeDef *hsd); +static uint32_t SD_InitCard(SD_HandleTypeDef *hsd); +static uint32_t SD_PowerON(SD_HandleTypeDef *hsd); +static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); +static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd); static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); -static uint32_t SD_FindSCR (SD_HandleTypeDef *hsd, uint32_t *pSCR); -static void SD_PowerOFF (SD_HandleTypeDef *hsd); -static void SD_Write_IT (SD_HandleTypeDef *hsd); -static void SD_Read_IT (SD_HandleTypeDef *hsd); -static uint32_t SD_HighSpeed (SD_HandleTypeDef *hsd); +static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); +static void SD_PowerOFF(SD_HandleTypeDef *hsd); +static void SD_Write_IT(SD_HandleTypeDef *hsd); +static void SD_Read_IT(SD_HandleTypeDef *hsd); +static uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd); #if (USE_SD_TRANSCEIVER != 0U) -static uint32_t SD_UltraHighSpeed (SD_HandleTypeDef *hsd); -static uint32_t SD_DDR_Mode (SD_HandleTypeDef *hsd); +static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd); +static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd); #endif /* USE_SD_TRANSCEIVER */ /** * @} @@ -311,8 +315,8 @@ static uint32_t SD_DDR_Mode (SD_HandleTypeDef *hsd); */ /** @addtogroup SD_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions - * + * @brief Initialization and de-initialization functions + * @verbatim ============================================================================== ##### Initialization and de-initialization functions ##### @@ -334,11 +338,12 @@ static uint32_t SD_DDR_Mode (SD_HandleTypeDef *hsd); HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) { HAL_SD_CardStatusTypeDef CardStatus; - uint32_t speedgrade, unitsize; + uint32_t speedgrade; + uint32_t unitsize; uint32_t tickstart; /* Check the SD handle allocation */ - if(hsd == NULL) + if (hsd == NULL) { return HAL_ERROR; } @@ -351,7 +356,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv)); - if(hsd->State == HAL_SD_STATE_RESET) + if (hsd->State == HAL_SD_STATE_RESET) { /* Allocate lock resource and initialize it */ hsd->Lock = HAL_UNLOCKED; @@ -362,7 +367,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) { hsd->Init.TranceiverPresent = SDMMC_TRANSCEIVER_PRESENT; } -#endif +#endif /*USE_SD_TRANSCEIVER */ #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) /* Reset Callback pointers in HAL_SD_STATE_RESET only */ hsd->TxCpltCallback = HAL_SD_TxCpltCallback; @@ -380,7 +385,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) } #endif /* USE_SD_TRANSCEIVER */ - if(hsd->MspInitCallback == NULL) + if (hsd->MspInitCallback == NULL) { hsd->MspInitCallback = HAL_SD_MspInit; } @@ -401,7 +406,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) return HAL_ERROR; } - if( HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK) + if (HAL_SD_GetCardStatus(hsd, &CardStatus) != HAL_OK) { return HAL_ERROR; } @@ -425,19 +430,19 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) } /* Configure the bus wide */ - if(HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK) + if (HAL_SD_ConfigWideBusOperation(hsd, hsd->Init.BusWide) != HAL_OK) { return HAL_ERROR; } /* Verify that SD card is ready to use after Initialization */ tickstart = HAL_GetTick(); - while((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) + while ((HAL_SD_GetCardState(hsd) != HAL_SD_CARD_TRANSFER)) { - if((HAL_GetTick()-tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State= HAL_SD_STATE_READY; + hsd->State = HAL_SD_STATE_READY; return HAL_TIMEOUT; } } @@ -477,21 +482,23 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1); if (sdmmc_clk == 0U) { - hsd->State = HAL_SD_STATE_READY; - hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; - return HAL_ERROR; + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; + return HAL_ERROR; } - Init.ClockDiv = sdmmc_clk/(2U*400000U); + Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ); #if (USE_SD_TRANSCEIVER != 0U) + Init.TranceiverPresent = hsd->Init.TranceiverPresent; + if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) { /* Set Transceiver polarity */ hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; } #elif defined (USE_SD_DIRPOL) - /* Set Transceiver polarity */ - hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; + /* Set Transceiver polarity */ + hsd->Instance->POWER |= SDMMC_POWER_DIRPOL; #endif /* USE_SD_TRANSCEIVER */ /* Initialize SDMMC peripheral interface with default configuration */ @@ -502,12 +509,12 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /* wait 74 Cycles: required power up waiting time before starting the SD initialization sequence */ - sdmmc_clk = sdmmc_clk/(2U*Init.ClockDiv); - HAL_Delay(1U+ (74U*1000U/(sdmmc_clk))); + sdmmc_clk = sdmmc_clk / (2U * Init.ClockDiv); + HAL_Delay(1U + (74U * 1000U / (sdmmc_clk))); /* Identify card operating voltage */ errorstate = SD_PowerON(hsd); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->State = HAL_SD_STATE_READY; hsd->ErrorCode |= errorstate; @@ -516,7 +523,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /* Card initialization */ errorstate = SD_InitCard(hsd); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->State = HAL_SD_STATE_READY; hsd->ErrorCode |= errorstate; @@ -525,7 +532,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -545,7 +552,7 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) { /* Check the SD handle allocation */ - if(hsd == NULL) + if (hsd == NULL) { return HAL_ERROR; } @@ -560,7 +567,7 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - if(hsd->DriveTransceiver_1_8V_Callback == NULL) + if (hsd->DriveTransceiver_1_8V_Callback == NULL) { hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback; } @@ -575,7 +582,7 @@ HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) SD_PowerOFF(hsd); #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - if(hsd->MspDeInitCallback == NULL) + if (hsd->MspDeInitCallback == NULL) { hsd->MspDeInitCallback = HAL_SD_MspDeInit; } @@ -629,8 +636,8 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) */ /** @addtogroup SD_Exported_Functions_Group2 - * @brief Data transfer functions - * + * @brief Data transfer functions + * @verbatim ============================================================================== ##### IO operation functions ##### @@ -655,26 +662,29 @@ __weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, + uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count, data, dataremaining; + uint32_t count; + uint32_t data; + uint32_t dataremaining; uint32_t add = BlockAdd; uint8_t *tempbuff = pData; - if(NULL == pData) + if (NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -685,7 +695,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 /* Initialize data control register */ hsd->Instance->DCTRL = 0U; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -698,10 +708,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; @@ -715,7 +725,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 /* Read Single Block command */ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); } - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -727,12 +737,12 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 /* Poll on SDMMC flags */ dataremaining = config.DataLength; - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining >= 32U)) { /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = SDMMC_ReadFIFO(hsd->Instance); *tempbuff = (uint8_t)(data & 0xFFU); @@ -747,26 +757,26 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 dataremaining -= 32U; } - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; - hsd->State= HAL_SD_STATE_READY; + hsd->State = HAL_SD_STATE_READY; hsd->Context = SD_CONTEXT_NONE; return HAL_TIMEOUT; } } - __SDMMC_CMDTRANS_DISABLE( hsd->Instance); + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); /* Send stop transmission command in case of multiblock read */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) { - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { /* Send stop transmission command */ errorstate = SDMMC_CmdStopTransfer(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -779,7 +789,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 } /* Get error state */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -788,7 +798,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -797,7 +807,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -837,26 +847,29 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint3 * @param Timeout: Specify timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, + uint32_t Timeout) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t tickstart = HAL_GetTick(); - uint32_t count, data, dataremaining; + uint32_t count; + uint32_t data; + uint32_t dataremaining; uint32_t add = BlockAdd; uint8_t *tempbuff = pData; - if(NULL == pData) + if (NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -867,7 +880,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint /* Initialize data control register */ hsd->Instance->DCTRL = 0U; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -880,10 +893,10 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; @@ -897,7 +910,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -909,12 +922,13 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint /* Write block(s) in polling mode */ dataremaining = config.DataLength; - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | + SDMMC_FLAG_DATAEND)) { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining >= 32U)) { /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = (uint32_t)(*tempbuff); tempbuff++; @@ -929,7 +943,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint dataremaining -= 32U; } - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -939,16 +953,16 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint return HAL_TIMEOUT; } } - __SDMMC_CMDTRANS_DISABLE( hsd->Instance); + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); /* Send stop transmission command in case of multiblock write */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) { - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { /* Send stop transmission command */ errorstate = SDMMC_CmdStopTransfer(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -961,7 +975,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint } /* Get error state */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -970,7 +984,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -979,7 +993,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint hsd->Context = SD_CONTEXT_NONE; return HAL_ERROR; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1020,23 +1034,24 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1050,7 +1065,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui hsd->pRxBuffPtr = pData; hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -1063,10 +1078,10 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); /* Read Blocks in IT mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT); @@ -1080,7 +1095,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui /* Read Single Block command */ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); } - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1090,7 +1105,8 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui return HAL_ERROR; } - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_RXFIFOHF)); return HAL_OK; } @@ -1113,23 +1129,24 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, ui * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1143,7 +1160,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u hsd->pTxBuffPtr = pData; hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -1157,12 +1174,12 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { - hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT); + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_IT); /* Write Multi Block command */ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); @@ -1174,7 +1191,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1185,7 +1202,8 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u } /* Enable transfer interrupts */ - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | + SDMMC_FLAG_TXFIFOHE)); return HAL_OK; } @@ -1208,23 +1226,24 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, u * @param NumberOfBlocks: Number of blocks to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1238,7 +1257,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u hsd->pRxBuffPtr = pData; hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -1252,12 +1271,12 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); hsd->Instance->IDMABASE0 = (uint32_t) pData ; hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; /* Read Blocks in DMA mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); @@ -1271,7 +1290,7 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u /* Read Single Block command */ errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); } - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1306,23 +1325,24 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u * @param NumberOfBlocks: Number of blocks to write * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; uint32_t add = BlockAdd; - if(NULL == pData) + if (NULL == pData) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1336,7 +1356,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, hsd->pTxBuffPtr = pData; hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -1351,13 +1371,13 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); hsd->Instance->IDMABASE0 = (uint32_t) pData ; hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_SINGLE_BUFF; /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) + if (NumberOfBlocks > 1U) { hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); @@ -1371,7 +1391,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, /* Write Single Block command */ errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); } - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1407,17 +1427,17 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui uint32_t start_add = BlockStartAdd; uint32_t end_add = BlockEndAdd; - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->ErrorCode = HAL_SD_ERROR_NONE; - if(end_add < start_add) + if (end_add < start_add) { hsd->ErrorCode |= HAL_SD_ERROR_PARAM; return HAL_ERROR; } - if(end_add > (hsd->SdCard.LogBlockNbr)) + if (end_add > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -1426,7 +1446,7 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui hsd->State = HAL_SD_STATE_BUSY; /* Check if the card command class supports erase command */ - if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U) + if (((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1435,7 +1455,7 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui return HAL_ERROR; } - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1445,18 +1465,18 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui } /* Get start and end block for high capacity cards */ - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { start_add *= 512U; end_add *= 512U; } /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1467,7 +1487,7 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1479,7 +1499,7 @@ HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, ui /* Send CMD38 ERASE */ errorstate = SDMMC_CmdErase(hsd->Instance, 0UL); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -1509,28 +1529,28 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) uint32_t context = hsd->Context; /* Check for SDMMC interrupt flags */ - if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) { SD_Read_IT(hsd); } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ - SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ - SDMMC_IT_RXFIFOHF); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE | \ + SDMMC_IT_RXFIFOHF); __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); - __SDMMC_CMDTRANS_DISABLE( hsd->Instance); + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); - if((context & SD_CONTEXT_IT) != 0U) + if ((context & SD_CONTEXT_IT) != 0U) { - if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) @@ -1546,7 +1566,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) hsd->State = HAL_SD_STATE_READY; hsd->Context = SD_CONTEXT_NONE; - if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->RxCpltCallback(hsd); @@ -1563,17 +1583,17 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } } - else if((context & SD_CONTEXT_DMA) != 0U) + else if ((context & SD_CONTEXT_DMA) != 0U) { hsd->Instance->DLEN = 0; hsd->Instance->DCTRL = 0; hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; /* Stop Transfer for Write Multi blocks or Read Multi blocks */ - if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + if (((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { errorstate = SDMMC_CmdStopTransfer(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) @@ -1586,7 +1606,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) hsd->State = HAL_SD_STATE_READY; hsd->Context = SD_CONTEXT_NONE; - if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->TxCpltCallback(hsd); @@ -1594,7 +1614,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) HAL_SD_TxCpltCallback(hsd); #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } - if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->RxCpltCallback(hsd); @@ -1609,27 +1629,28 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } } - else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + else if ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) { SD_Write_IT(hsd); } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | + SDMMC_FLAG_TXUNDERR) != RESET) { /* Set Error code */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DCRCFAIL) != RESET) { hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_DTIMEOUT) != RESET) { hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_RXOVERR) != RESET) { hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_IT_TXUNDERR) != RESET) { hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; } @@ -1638,17 +1659,17 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Disable all interrupts */ - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); - __SDMMC_CMDTRANS_DISABLE( hsd->Instance); + __SDMMC_CMDTRANS_DISABLE(hsd->Instance); hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; hsd->Instance->CMD |= SDMMC_CMD_CMDSTOP; hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); hsd->Instance->CMD &= ~(SDMMC_CMD_CMDSTOP); __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DABORT); - if((context & SD_CONTEXT_IT) != 0U) + if ((context & SD_CONTEXT_IT) != 0U) { /* Set the SD state to ready to be able to start again the process */ hsd->State = HAL_SD_STATE_READY; @@ -1659,9 +1680,9 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) HAL_SD_ErrorCallback(hsd); #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ } - else if((context & SD_CONTEXT_DMA) != 0U) + else if ((context & SD_CONTEXT_DMA) != 0U) { - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if (hsd->ErrorCode != HAL_SD_ERROR_NONE) { /* Disable Internal DMA */ __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_IDMABTC); @@ -1682,13 +1703,13 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) } } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_IDMABTC) != RESET) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_IDMABTC); - if(READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) + if (READ_BIT(hsd->Instance->IDMACTRL, SDMMC_IDMA_IDMABACT) == 0U) { /* Current buffer is buffer0, Transfer complete for buffer1 */ - if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->Write_DMADblBuf1CpltCallback(hsd); @@ -1708,7 +1729,7 @@ void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) else /* SD_DMA_BUFFER1 */ { /* Current buffer is buffer1, Transfer complete for buffer0 */ - if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + if ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) { #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) hsd->Write_DMADblBuf0CpltCallback(hsd); @@ -1743,11 +1764,11 @@ HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) } /** -* @brief Return the SD error code -* @param hsd : Pointer to a SD_HandleTypeDef structure that contains + * @brief Return the SD error code + * @param hsd : Pointer to a SD_HandleTypeDef structure that contains * the configuration information. -* @retval SD Error Code -*/ + * @retval SD Error Code + */ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) { return hsd->ErrorCode; @@ -1849,11 +1870,12 @@ __weak void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status) * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, + pSD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; @@ -1863,64 +1885,64 @@ HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callback /* Process locked */ __HAL_LOCK(hsd); - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { switch (CallbackID) { - case HAL_SD_TX_CPLT_CB_ID : - hsd->TxCpltCallback = pCallback; - break; - case HAL_SD_RX_CPLT_CB_ID : - hsd->RxCpltCallback = pCallback; - break; - case HAL_SD_ERROR_CB_ID : - hsd->ErrorCallback = pCallback; - break; - case HAL_SD_ABORT_CB_ID : - hsd->AbortCpltCallback = pCallback; - break; - case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : - hsd->Read_DMADblBuf0CpltCallback = pCallback; - break; - case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : - hsd->Read_DMADblBuf1CpltCallback = pCallback; - break; - case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : - hsd->Write_DMADblBuf0CpltCallback = pCallback; - break; - case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : - hsd->Write_DMADblBuf1CpltCallback = pCallback; - break; - case HAL_SD_MSP_INIT_CB_ID : - hsd->MspInitCallback = pCallback; - break; - case HAL_SD_MSP_DEINIT_CB_ID : - hsd->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = pCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = pCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = pCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = pCallback; + break; + case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Read_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Read_DMADblBuf1CpltCallback = pCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Write_DMADblBuf0CpltCallback = pCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Write_DMADblBuf1CpltCallback = pCallback; + break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else if (hsd->State == HAL_SD_STATE_RESET) { switch (CallbackID) { - case HAL_SD_MSP_INIT_CB_ID : - hsd->MspInitCallback = pCallback; - break; - case HAL_SD_MSP_DEINIT_CB_ID : - hsd->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1961,64 +1983,64 @@ HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_Callba /* Process locked */ __HAL_LOCK(hsd); - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { switch (CallbackID) { - case HAL_SD_TX_CPLT_CB_ID : - hsd->TxCpltCallback = HAL_SD_TxCpltCallback; - break; - case HAL_SD_RX_CPLT_CB_ID : - hsd->RxCpltCallback = HAL_SD_RxCpltCallback; - break; - case HAL_SD_ERROR_CB_ID : - hsd->ErrorCallback = HAL_SD_ErrorCallback; - break; - case HAL_SD_ABORT_CB_ID : - hsd->AbortCpltCallback = HAL_SD_AbortCallback; - break; - case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : - hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuf0CpltCallback; - break; - case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : - hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuf1CpltCallback; - break; - case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : - hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuf0CpltCallback; - break; - case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : - hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuf1CpltCallback; - break; - case HAL_SD_MSP_INIT_CB_ID : - hsd->MspInitCallback = HAL_SD_MspInit; - break; - case HAL_SD_MSP_DEINIT_CB_ID : - hsd->MspDeInitCallback = HAL_SD_MspDeInit; - break; - default : - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = HAL_SD_TxCpltCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = HAL_SD_RxCpltCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = HAL_SD_ErrorCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = HAL_SD_AbortCallback; + break; + case HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Read_DMADblBuf0CpltCallback = HAL_SDEx_Read_DMADoubleBuf0CpltCallback; + break; + case HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Read_DMADblBuf1CpltCallback = HAL_SDEx_Read_DMADoubleBuf1CpltCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID : + hsd->Write_DMADblBuf0CpltCallback = HAL_SDEx_Write_DMADoubleBuf0CpltCallback; + break; + case HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID : + hsd->Write_DMADblBuf1CpltCallback = HAL_SDEx_Write_DMADoubleBuf1CpltCallback; + break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else if (hsd->State == HAL_SD_STATE_RESET) { switch (CallbackID) { - case HAL_SD_MSP_INIT_CB_ID : - hsd->MspInitCallback = HAL_SD_MspInit; - break; - case HAL_SD_MSP_DEINIT_CB_ID : - hsd->MspDeInitCallback = HAL_SD_MspDeInit; - break; - default : - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -2046,7 +2068,7 @@ HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_ { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; @@ -2056,7 +2078,7 @@ HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_ /* Process locked */ __HAL_LOCK(hsd); - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->DriveTransceiver_1_8V_Callback = pCallback; } @@ -2086,7 +2108,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) /* Process locked */ __HAL_LOCK(hsd); - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { hsd->DriveTransceiver_1_8V_Callback = HAL_SD_DriveTransceiver_1_8V_Callback; } @@ -2110,8 +2132,8 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) */ /** @addtogroup SD_Exported_Functions_Group3 - * @brief management functions - * + * @brief management functions + * @verbatim ============================================================================== ##### Peripheral Control functions ##### @@ -2193,7 +2215,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef pCSD->Reserved2 = 0U; /*!< Reserved */ - if(hsd->SdCard.CardType == CARD_SDSC) + if (hsd->SdCard.CardType == CARD_SDSC) { pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)); @@ -2211,10 +2233,10 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); hsd->SdCard.LogBlockSize = 512U; } - else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) + else if (hsd->SdCard.CardType == CARD_SDHC_SDXC) { /* Byte 7 */ pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)); @@ -2245,7 +2267,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); - pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); + pCSD->MaxWrBlockLen = (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); @@ -2263,7 +2285,7 @@ HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); - pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); + pCSD->ECC = (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); @@ -2286,7 +2308,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT HAL_StatusTypeDef status = HAL_OK; errorstate = SD_SendSDStatus(hsd, sd_status); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2324,7 +2346,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2372,6 +2394,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t { SDMMC_InitTypeDef Init; uint32_t errorstate; + uint32_t sdmmc_clk; HAL_StatusTypeDef status = HAL_OK; /* Check the parameters */ @@ -2380,19 +2403,19 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t /* Change State */ hsd->State = HAL_SD_STATE_BUSY; - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { - if(WideMode == SDMMC_BUS_WIDE_8B) + if (WideMode == SDMMC_BUS_WIDE_8B) { hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; } - else if(WideMode == SDMMC_BUS_WIDE_4B) + else if (WideMode == SDMMC_BUS_WIDE_4B) { errorstate = SD_WideBus_Enable(hsd); hsd->ErrorCode |= errorstate; } - else if(WideMode == SDMMC_BUS_WIDE_1B) + else if (WideMode == SDMMC_BUS_WIDE_1B) { errorstate = SD_WideBus_Disable(hsd); @@ -2410,7 +2433,7 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; } - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if (hsd->ErrorCode != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2418,39 +2441,94 @@ HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t } else { - /* Configure the SDMMC peripheral */ - Init.ClockEdge = hsd->Init.ClockEdge; - Init.ClockPowerSave = hsd->Init.ClockPowerSave; - Init.BusWide = WideMode; - Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; + sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1); + if (sdmmc_clk != 0U) + { + /* Configure the SDMMC peripheral */ + Init.ClockEdge = hsd->Init.ClockEdge; + Init.ClockPowerSave = hsd->Init.ClockPowerSave; + Init.BusWide = WideMode; + Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; - /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */ - if(hsd->Init.ClockDiv >= SDMMC_NSpeed_CLK_DIV) - { - Init.ClockDiv = hsd->Init.ClockDiv; - } - else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) - { - /* UltraHigh speed SD card,user Clock div */ - Init.ClockDiv = hsd->Init.ClockDiv; - } - else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) - { - /* High speed SD card, Max Frequency = 50Mhz */ - Init.ClockDiv = SDMMC_HSpeed_CLK_DIV; + /* Check if user Clock div < Normal speed 25Mhz, no change in Clockdiv */ + if (hsd->Init.ClockDiv >= (sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ))) + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + else if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) + { + /* UltraHigh speed SD card,user Clock div */ + Init.ClockDiv = hsd->Init.ClockDiv; + } + else if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) + { + /* High speed SD card, Max Frequency = 50Mhz */ + if (hsd->Init.ClockDiv == 0U) + { + if (sdmmc_clk > SD_HIGH_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + else + { + if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_HIGH_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_HIGH_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + } + else + { + /* No High speed SD card, Max Frequency = 25Mhz */ + if (hsd->Init.ClockDiv == 0U) + { + if (sdmmc_clk > SD_NORMAL_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + else + { + if ((sdmmc_clk/(2U * hsd->Init.ClockDiv)) > SD_NORMAL_SPEED_FREQ) + { + Init.ClockDiv = sdmmc_clk / (2U * SD_NORMAL_SPEED_FREQ); + } + else + { + Init.ClockDiv = hsd->Init.ClockDiv; + } + } + } + +#if (USE_SD_TRANSCEIVER != 0U) + Init.TranceiverPresent = hsd->Init.TranceiverPresent; +#endif /* USE_SD_TRANSCEIVER */ + + (void)SDMMC_Init(hsd->Instance, Init); } else { - /* No High speed SD card, Max Frequency = 25Mhz */ - Init.ClockDiv = SDMMC_NSpeed_CLK_DIV; + hsd->ErrorCode |= SDMMC_ERROR_INVALID_PARAMETER; + status = HAL_ERROR; } - - (void)SDMMC_Init(hsd->Instance, Init); } /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2492,7 +2570,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t { switch (SpeedMode) { - case SDMMC_SPEED_MODE_AUTO: + case SDMMC_SPEED_MODE_AUTO: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardType == CARD_SDHC_SDXC)) @@ -2523,7 +2601,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_ULTRA: + case SDMMC_SPEED_MODE_ULTRA: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardType == CARD_SDHC_SDXC)) @@ -2543,7 +2621,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_DDR: + case SDMMC_SPEED_MODE_DDR: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardType == CARD_SDHC_SDXC)) @@ -2563,11 +2641,11 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_HIGH: + case SDMMC_SPEED_MODE_HIGH: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) @@ -2583,23 +2661,23 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_DEFAULT: - break; - default: - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - status = HAL_ERROR; - break; + case SDMMC_SPEED_MODE_DEFAULT: + break; + default: + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + status = HAL_ERROR; + break; } } else { switch (SpeedMode) { - case SDMMC_SPEED_MODE_AUTO: + case SDMMC_SPEED_MODE_AUTO: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) @@ -2614,11 +2692,11 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_HIGH: + case SDMMC_SPEED_MODE_HIGH: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) @@ -2634,23 +2712,23 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_DEFAULT: - break; - case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ - default: - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - status = HAL_ERROR; - break; + case SDMMC_SPEED_MODE_DEFAULT: + break; + case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ + default: + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + status = HAL_ERROR; + break; } } #else switch (SpeedMode) { - case SDMMC_SPEED_MODE_AUTO: + case SDMMC_SPEED_MODE_AUTO: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) @@ -2665,11 +2743,11 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_HIGH: + case SDMMC_SPEED_MODE_HIGH: { if ((hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) || (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) || - (hsd->SdCard.CardType == CARD_SDHC_SDXC)) + (hsd->SdCard.CardType == CARD_SDHC_SDXC)) { /* Enable High Speed */ if (SD_HighSpeed(hsd) != HAL_SD_ERROR_NONE) @@ -2685,13 +2763,13 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t } break; } - case SDMMC_SPEED_MODE_DEFAULT: - break; - case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ - default: - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - status = HAL_ERROR; - break; + case SDMMC_SPEED_MODE_DEFAULT: + break; + case SDMMC_SPEED_MODE_ULTRA: /*not valid without transceiver*/ + default: + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + status = HAL_ERROR; + break; } #endif /* USE_SD_TRANSCEIVER */ @@ -2709,7 +2787,7 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t /* Set Block Size for Card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); @@ -2734,7 +2812,7 @@ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) uint32_t resp1 = 0; errorstate = SD_SendStatus(hsd, &resp1); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= errorstate; } @@ -2755,8 +2833,8 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) HAL_SD_CardStateTypeDef CardState; /* DIsable All interrupts */ - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); /* Clear All flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); @@ -2770,11 +2848,11 @@ HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) hsd->Context = SD_CONTEXT_NONE; CardState = HAL_SD_GetCardState(hsd); - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); } - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if (hsd->ErrorCode != HAL_SD_ERROR_NONE) { return HAL_ERROR; } @@ -2792,8 +2870,8 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) HAL_SD_CardStateTypeDef CardState; /* Disable All interrupts */ - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | \ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR); /* If IDMA Context, disable Internal DMA */ hsd->Instance->IDMACTRL = SDMMC_DISABLE_IDMA; @@ -2804,12 +2882,12 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) CardState = HAL_SD_GetCardState(hsd); hsd->State = HAL_SD_STATE_READY; - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + if ((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) { hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); } - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + if (hsd->ErrorCode != HAL_SD_ERROR_NONE) { return HAL_ERROR; } @@ -2851,17 +2929,17 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) uint16_t sd_rca = 1U; /* Check the power State */ - if(SDMMC_GetPowerState(hsd->Instance) == 0U) + if (SDMMC_GetPowerState(hsd->Instance) == 0U) { /* Power off */ return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { /* Send CMD2 ALL_SEND_CID */ errorstate = SDMMC_CmdSendCID(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -2875,24 +2953,24 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) } } - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { /* Send CMD3 SET_REL_ADDR with argument 0 */ /* SD Card publishes its RCA. */ errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } } - if(hsd->SdCard.CardType != CARD_SECURED) + if (hsd->SdCard.CardType != CARD_SECURED) { /* Get the SD card RCA */ hsd->SdCard.RelCardAdd = sd_rca; /* Send CMD9 SEND_CSD with argument as card's RCA */ errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -2917,7 +2995,7 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) /* Select the Card */ errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -2936,7 +3014,8 @@ static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) { __IO uint32_t count = 0U; - uint32_t response = 0U, validvoltage = 0U; + uint32_t response = 0U; + uint32_t validvoltage = 0U; uint32_t errorstate; #if (USE_SD_TRANSCEIVER != 0U) uint32_t tickstart = HAL_GetTick(); @@ -2944,19 +3023,19 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ errorstate = SDMMC_CmdOperCond(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->SdCard.CardVersion = CARD_V1_X; /* CMD0: GO_IDLE_STATE */ errorstate = SDMMC_CmdGoIdleState(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -2967,29 +3046,30 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) hsd->SdCard.CardVersion = CARD_V2_X; } - if( hsd->SdCard.CardVersion == CARD_V2_X) + if (hsd->SdCard.CardVersion == CARD_V2_X) { /* SEND CMD55 APP_CMD with RCA as 0 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return HAL_SD_ERROR_UNSUPPORTED_FEATURE; } } /* SD CARD */ /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) + while ((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) { /* SEND CMD55 APP_CMD with RCA as 0 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send CMD41 */ - errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY); - if(errorstate != HAL_SD_ERROR_NONE) + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | + SD_SWITCH_1_8V_CAPACITY); + if (errorstate != HAL_SD_ERROR_NONE) { return HAL_SD_ERROR_UNSUPPORTED_FEATURE; } @@ -3003,18 +3083,18 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) count++; } - if(count >= SDMMC_MAX_VOLT_TRIAL) + if (count >= SDMMC_MAX_VOLT_TRIAL) { return HAL_SD_ERROR_INVALID_VOLTRANGE; } - if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + if ((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ { hsd->SdCard.CardType = CARD_SDHC_SDXC; #if (USE_SD_TRANSCEIVER != 0U) if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT) { - if((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY) + if ((response & SD_SWITCH_1_8V_CAPACITY) == SD_SWITCH_1_8V_CAPACITY) { hsd->SdCard.CardSpeed = CARD_ULTRA_HIGH_SPEED; @@ -3023,15 +3103,15 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* Send CMD11 to switch 1.8V mode */ errorstate = SDMMC_CmdVoltageSwitch(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Check to CKSTOP */ - while(( hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP) + while ((hsd->Instance->STA & SDMMC_FLAG_CKSTOP) != SDMMC_FLAG_CKSTOP) { - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3041,7 +3121,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) hsd->Instance->ICR = SDMMC_FLAG_CKSTOP; /* Check to BusyD0 */ - if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0) + if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) != SDMMC_FLAG_BUSYD0) { /* Error when activate Voltage Switch in SDMMC Peripheral */ return SDMMC_ERROR_UNSUPPORTED_FEATURE; @@ -3059,9 +3139,9 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) hsd->Instance->POWER |= SDMMC_POWER_VSWITCH; /* Check VSWEND Flag */ - while(( hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND) + while ((hsd->Instance->STA & SDMMC_FLAG_VSWEND) != SDMMC_FLAG_VSWEND) { - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3071,7 +3151,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) hsd->Instance->ICR = SDMMC_FLAG_VSWEND; /* Check BusyD0 status */ - if(( hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0) + if ((hsd->Instance->STA & SDMMC_FLAG_BUSYD0) == SDMMC_FLAG_BUSYD0) { /* Error when enabling 1.8V mode */ return HAL_SD_ERROR_INVALID_VOLTRANGE; @@ -3119,14 +3199,14 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) uint32_t *pData = pSDstatus; /* Check SD response */ - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } /* Set block size for card if it is not equal to current block size for card */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_NONE; return errorstate; @@ -3134,7 +3214,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) /* Send CMD55 */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_NONE; return errorstate; @@ -3151,39 +3231,39 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ errorstate = SDMMC_CmdStatusRegister(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->ErrorCode |= HAL_SD_ERROR_NONE; return errorstate; } /* Get status data */ - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { *pData = SDMMC_ReadFIFO(hsd->Instance); pData++; } } - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { return HAL_SD_ERROR_DATA_TIMEOUT; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) { return HAL_SD_ERROR_DATA_CRC_FAIL; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) { return HAL_SD_ERROR_RX_OVERRUN; } @@ -3197,7 +3277,7 @@ static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) *pData = SDMMC_ReadFIFO(hsd->Instance); pData++; - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } @@ -3220,14 +3300,14 @@ static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) { uint32_t errorstate; - if(pCardStatus == NULL) + if (pCardStatus == NULL) { return HAL_SD_ERROR_PARAM; } /* Send Status command */ errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3248,31 +3328,31 @@ static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) uint32_t scr[2U] = {0UL, 0UL}; uint32_t errorstate; - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* If requested card supports wide bus operation */ - if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) + if ((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA.*/ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3295,31 +3375,31 @@ static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) uint32_t scr[2U] = {0UL, 0UL}; uint32_t errorstate; - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + if ((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) { return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; } /* Get SCR Register */ errorstate = SD_FindSCR(hsd, scr); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* If requested card supports 1 bit mode operation */ - if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) + if ((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) { /* Send CMD55 APP_CMD with argument as card's RCA */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3350,14 +3430,14 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /* Set Block Size To 8 Bytes */ errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } /* Send CMD55 APP_CMD with argument as card's RCA */ errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } @@ -3372,14 +3452,15 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ errorstate = SDMMC_CmdSendSCR(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DATAEND)) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | + SDMMC_FLAG_DATAEND)) { - if((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U)) + if ((!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOE)) && (index == 0U)) { tempscr[0] = SDMMC_ReadFIFO(hsd->Instance); tempscr[1] = SDMMC_ReadFIFO(hsd->Instance); @@ -3387,25 +3468,25 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) } - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) { return HAL_SD_ERROR_TIMEOUT; } } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); return HAL_SD_ERROR_DATA_TIMEOUT; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); return HAL_SD_ERROR_DATA_CRC_FAIL; } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + else if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) { __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); @@ -3417,10 +3498,10 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) /* Clear all the static flags */ __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) | \ ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); scr++; - *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) | \ ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); } @@ -3436,15 +3517,16 @@ static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) */ static void SD_Read_IT(SD_HandleTypeDef *hsd) { - uint32_t count, data; - uint8_t* tmp; + uint32_t count; + uint32_t data; + uint8_t *tmp; tmp = hsd->pRxBuffPtr; if (hsd->RxXferSize >= 32U) { /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = SDMMC_ReadFIFO(hsd->Instance); *tmp = (uint8_t)(data & 0xFFU); @@ -3470,15 +3552,16 @@ static void SD_Read_IT(SD_HandleTypeDef *hsd) */ static void SD_Write_IT(SD_HandleTypeDef *hsd) { - uint32_t count, data; - uint8_t* tmp; + uint32_t count; + uint32_t data; + uint8_t *tmp; tmp = hsd->pTxBuffPtr; if (hsd->TxXferSize >= 32U) { /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) + for (count = 0U; count < 8U; count++) { data = (uint32_t)(*tmp); tmp++; @@ -3509,16 +3592,17 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) uint32_t errorstate = HAL_SD_ERROR_NONE; SDMMC_DataInitTypeDef sdmmc_datainitstructure; uint32_t SD_hs[16] = {0}; - uint32_t count, loop = 0 ; + uint32_t count; + uint32_t loop = 0 ; uint32_t Timeout = HAL_GetTick(); - if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) { - /* Standard Speed Card <= 12.5Mhz */ - return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } - if(hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) + if (hsd->SdCard.CardSpeed == CARD_HIGH_SPEED) { /* Initialize the Data control register */ hsd->Instance->DCTRL = 0; @@ -3540,27 +3624,28 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) (void)SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure); - errorstate = SDMMC_CmdSwitch(hsd->Instance,SDMMC_SDR25_SWITCH_PATTERN); - if(errorstate != HAL_SD_ERROR_NONE) + errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR25_SWITCH_PATTERN); + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND )) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | + SDMMC_FLAG_DATAEND)) { if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { for (count = 0U; count < 8U; count++) { - SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance); + SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance); } loop ++; } - if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State= HAL_SD_STATE_READY; + hsd->State = HAL_SD_STATE_READY; return HAL_SD_ERROR_TIMEOUT; } } @@ -3596,7 +3681,7 @@ uint32_t SD_HighSpeed(SD_HandleTypeDef *hsd) __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Test if the switch mode HS is ok */ - if ((((uint8_t*)SD_hs)[13] & 2U) != 2U) + if ((((uint8_t *)SD_hs)[13] & 2U) != 2U) { errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; } @@ -3620,16 +3705,17 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) uint32_t errorstate = HAL_SD_ERROR_NONE; SDMMC_DataInitTypeDef sdmmc_datainitstructure; uint32_t SD_hs[16] = {0}; - uint32_t count, loop = 0 ; + uint32_t count; + uint32_t loop = 0 ; uint32_t Timeout = HAL_GetTick(); - if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) { - /* Standard Speed Card <= 12.5Mhz */ - return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } - if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) + if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) { /* Initialize the Data control register */ hsd->Instance->DCTRL = 0; @@ -3648,32 +3734,33 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) + if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) { return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); } errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_SDR104_SWITCH_PATTERN); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND )) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | + SDMMC_FLAG_DATAEND)) { if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { for (count = 0U; count < 8U; count++) { - SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance); + SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance); } loop ++; } - if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State= HAL_SD_STATE_READY; + hsd->State = HAL_SD_STATE_READY; return HAL_SD_ERROR_TIMEOUT; } } @@ -3709,7 +3796,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Test if the switch mode HS is ok */ - if ((((uint8_t*)SD_hs)[13] & 2U) != 2U) + if ((((uint8_t *)SD_hs)[13] & 2U) != 2U) { errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; } @@ -3723,7 +3810,7 @@ static uint32_t SD_UltraHighSpeed(SD_HandleTypeDef *hsd) #if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) /* Enable DelayBlock Peripheral */ /* SDMMC_FB_CLK tuned feedback clock selected as receive clock, for SDR104 */ - MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_1); + MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_1); if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK) { return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); @@ -3748,16 +3835,17 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) uint32_t errorstate = HAL_SD_ERROR_NONE; SDMMC_DataInitTypeDef sdmmc_datainitstructure; uint32_t SD_hs[16] = {0}; - uint32_t count, loop = 0 ; + uint32_t count; + uint32_t loop = 0 ; uint32_t Timeout = HAL_GetTick(); - if(hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) + if (hsd->SdCard.CardSpeed == CARD_NORMAL_SPEED) { - /* Standard Speed Card <= 12.5Mhz */ - return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + /* Standard Speed Card <= 12.5Mhz */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; } - if(hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) + if (hsd->SdCard.CardSpeed == CARD_ULTRA_HIGH_SPEED) { /* Initialize the Data control register */ hsd->Instance->DCTRL = 0; @@ -3776,32 +3864,33 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) sdmmc_datainitstructure.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; sdmmc_datainitstructure.DPSM = SDMMC_DPSM_ENABLE; - if ( SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) + if (SDMMC_ConfigData(hsd->Instance, &sdmmc_datainitstructure) != HAL_OK) { return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); } errorstate = SDMMC_CmdSwitch(hsd->Instance, SDMMC_DDR50_SWITCH_PATTERN); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { return errorstate; } - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND| SDMMC_FLAG_DATAEND )) + while (!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND | + SDMMC_FLAG_DATAEND)) { if (__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) { for (count = 0U; count < 8U; count++) { - SD_hs[(8U*loop)+count] = SDMMC_ReadFIFO(hsd->Instance); + SD_hs[(8U * loop) + count] = SDMMC_ReadFIFO(hsd->Instance); } loop ++; } - if((HAL_GetTick()-Timeout) >= SDMMC_DATATIMEOUT) + if ((HAL_GetTick() - Timeout) >= SDMMC_DATATIMEOUT) { hsd->ErrorCode = HAL_SD_ERROR_TIMEOUT; - hsd->State= HAL_SD_STATE_READY; + hsd->State = HAL_SD_STATE_READY; return HAL_SD_ERROR_TIMEOUT; } } @@ -3837,7 +3926,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); /* Test if the switch mode is ok */ - if ((((uint8_t*)SD_hs)[13] & 2U) != 2U) + if ((((uint8_t *)SD_hs)[13] & 2U) != 2U) { errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; } @@ -3851,7 +3940,7 @@ static uint32_t SD_DDR_Mode(SD_HandleTypeDef *hsd) #if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) /* Enable DelayBlock Peripheral */ /* SDMMC_CKin feedback clock selected as receive clock, for DDR50 */ - MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX,SDMMC_CLKCR_SELCLKRX_0); + MODIFY_REG(hsd->Instance->CLKCR, SDMMC_CLKCR_SELCLKRX, SDMMC_CLKCR_SELCLKRX_0); if (DelayBlock_Enable(SD_GET_DLYB_INSTANCE(hsd->Instance)) != HAL_OK) { return (HAL_SD_ERROR_GENERAL_UNKNOWN_ERR); diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd.h index ae45839bec..5fb82a89ff 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd.h @@ -22,7 +22,7 @@ #define STM32L5xx_HAL_SD_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -58,7 +58,7 @@ typedef enum HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receiving State */ HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfer State */ HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */ -}HAL_SD_StateTypeDef; +} HAL_SD_StateTypeDef; /** * @} */ @@ -110,7 +110,7 @@ typedef struct uint32_t CardSpeed; /*!< Specifies the card Speed */ -}HAL_SD_CardInfoTypeDef; +} HAL_SD_CardInfoTypeDef; /** * @brief SD handle Structure definition @@ -148,22 +148,22 @@ typedef struct uint32_t CID[4]; /*!< SD card identification number table */ #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd); - void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* Read_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* Read_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* Write_DMADblBuf0CpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* Write_DMADblBuf1CpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* TxCpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* RxCpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* ErrorCallback)(struct __SD_HandleTypeDef *hsd); + void (* AbortCpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* Read_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* Read_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* Write_DMADblBuf0CpltCallback)(struct __SD_HandleTypeDef *hsd); + void (* Write_DMADblBuf1CpltCallback)(struct __SD_HandleTypeDef *hsd); #if (USE_SD_TRANSCEIVER != 0U) - void (* DriveTransceiver_1_8V_Callback) (FlagStatus status); + void (* DriveTransceiver_1_8V_Callback)(FlagStatus status); #endif /* USE_SD_TRANSCEIVER */ - void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd); - void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd); + void (* MspInitCallback)(struct __SD_HandleTypeDef *hsd); + void (* MspDeInitCallback)(struct __SD_HandleTypeDef *hsd); #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ -}SD_HandleTypeDef; +} SD_HandleTypeDef; /** * @} @@ -211,7 +211,7 @@ typedef struct __IO uint8_t ECC; /*!< ECC code */ __IO uint8_t CSD_CRC; /*!< CSD CRC */ __IO uint8_t Reserved4; /*!< Always 1 */ -}HAL_SD_CardCSDTypeDef; +} HAL_SD_CardCSDTypeDef; /** * @} */ @@ -232,7 +232,7 @@ typedef struct __IO uint8_t CID_CRC; /*!< CID CRC */ __IO uint8_t Reserved2; /*!< Always 1 */ -}HAL_SD_CardCIDTypeDef; +} HAL_SD_CardCIDTypeDef; /** * @} */ @@ -255,7 +255,7 @@ typedef struct __IO uint8_t UhsSpeedGrade; /*!< Carries information about the speed grade of UHS card */ __IO uint8_t UhsAllocationUnitSize; /*!< Carries information about the UHS card's allocation unit size */ __IO uint8_t VideoSpeedClass; /*!< Carries information about the Video Speed Class of UHS card */ -}HAL_SD_CardStatusTypeDef; +} HAL_SD_CardStatusTypeDef; /** * @} */ @@ -277,7 +277,7 @@ typedef enum HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */ HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */ -}HAL_SD_CallbackIDTypeDef; +} HAL_SD_CallbackIDTypeDef; /** * @} */ @@ -285,7 +285,7 @@ typedef enum /** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition * @{ */ -typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); +typedef void (*pSD_CallbackTypeDef)(SD_HandleTypeDef *hsd); #if (USE_SD_TRANSCEIVER != 0U) typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #endif /* USE_SD_TRANSCEIVER */ @@ -298,7 +298,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup SD_Exported_Constants Exported Constants +/** @defgroup SD_Exported_Constants SD Exported Constants * @{ */ @@ -315,13 +315,13 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ #define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ #define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ -#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the - number of transferred bytes does not match the block length */ +#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the */ + /*!< number of transferred bytes does not match the block length */ #define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ #define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ #define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ -#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock - command or if there was an attempt to access a locked card */ +#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock */ + /*!< command or if there was an attempt to access a locked card */ #define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ #define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ #define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ @@ -332,8 +332,8 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ #define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ #define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ -#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out - of erase sequence command was received */ +#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out */ + /*!< of erase sequence command was received */ #define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ #define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ #define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ @@ -342,7 +342,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); #define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ #define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ #define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ -#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ +#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) #define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ @@ -397,9 +397,9 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); /* Exported macro ------------------------------------------------------------*/ /** @defgroup SD_Exported_macros SD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ /** @brief Reset SD handle state. * @param __HANDLE__ SD Handle. * @retval None @@ -620,10 +620,10 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status); /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ -HAL_StatusTypeDef HAL_SD_Init (SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_InitCard (SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); -void HAL_SD_MspInit (SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd); +void HAL_SD_MspInit(SD_HandleTypeDef *hsd); void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); /** * @} @@ -633,23 +633,29 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); * @{ */ /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SD_ReadBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_SD_WriteBlocks (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_SD_Erase (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); /* Non-Blocking mode: IT */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, + uint32_t NumberOfBlocks); -void HAL_SD_IRQHandler (SD_HandleTypeDef *hsd); +void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); /* Callback in non blocking modes (DMA) */ -void HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd); -void HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd); -void HAL_SD_ErrorCallback (SD_HandleTypeDef *hsd); -void HAL_SD_AbortCallback (SD_HandleTypeDef *hsd); +void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd); +void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd); #if (USE_SD_TRANSCEIVER != 0U) /* Callback to switch in 1.8V mode */ @@ -658,11 +664,12 @@ void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status); #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) /* SD callback registering/unregistering */ -HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, + pSD_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID); #if (USE_SD_TRANSCEIVER != 0U) -HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback (SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback(SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd); #endif /* USE_SD_TRANSCEIVER */ #endif /* USE_HAL_SD_REGISTER_CALLBACKS */ @@ -684,10 +691,10 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t * @{ */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_GetCardCID (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); -HAL_StatusTypeDef HAL_SD_GetCardCSD (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); -HAL_StatusTypeDef HAL_SD_GetCardInfo (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} */ @@ -704,7 +711,7 @@ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); /** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management * @{ */ -HAL_StatusTypeDef HAL_SD_Abort (SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd); HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd_ex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd_ex.c index ef291b242f..56d8fa4034 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd_ex.c @@ -14,7 +14,8 @@ [..] The SD Extension HAL driver can be used as follows: (+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_SDEx_ConfigDMAMultiBuffer() function. - (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions. + (+) Start Read and Write for multibuffer mode using HAL_SDEx_ReadBlocksDMAMultiBuffer() + and HAL_SDEx_WriteBlocksDMAMultiBuffer() functions. @endverbatim ****************************************************************************** @@ -57,8 +58,8 @@ */ /** @addtogroup SDEx_Exported_Functions_Group1 - * @brief Multibuffer functions - * + * @brief Multibuffer functions + * @verbatim ============================================================================== ##### Multibuffer functions ##### @@ -79,13 +80,14 @@ * @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, + uint32_t BufferSize) { - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { - hsd->Instance->IDMABASE0= (uint32_t) pDataBuffer0; - hsd->Instance->IDMABASE1= (uint32_t) pDataBuffer1; - hsd->Instance->IDMABSIZE= (uint32_t) (BLOCKSIZE * BufferSize); + hsd->Instance->IDMABASE0 = (uint32_t) pDataBuffer0; + hsd->Instance->IDMABASE1 = (uint32_t) pDataBuffer1; + hsd->Instance->IDMABSIZE = (uint32_t)(BLOCKSIZE * BufferSize); return HAL_OK; } @@ -97,7 +99,8 @@ HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t /** * @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1. - * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before + * call this function. * @param hsd: SD handle * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Total number of blocks to read @@ -107,12 +110,13 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 { SDMMC_DataInitTypeDef config; uint32_t errorstate; - uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t DmaBase0_reg; + uint32_t DmaBase1_reg; uint32_t add = BlockAdd; - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -135,7 +139,7 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 hsd->ErrorCode = HAL_SD_ERROR_NONE; hsd->State = HAL_SD_STATE_BUSY; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -151,7 +155,7 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 hsd->Instance->DCTRL |= SDMMC_DCTRL_FIFORST; - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; @@ -160,14 +164,15 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 /* Read Multi Block command */ errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->State = HAL_SD_STATE_READY; hsd->ErrorCode |= errorstate; return HAL_ERROR; } - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC)); + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | + SDMMC_IT_IDMABTC)); return HAL_OK; } @@ -180,22 +185,24 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3 /** * @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1. - * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function. + * Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before + * call this function. * @param hsd: SD handle * @param BlockAdd: Block Address from where data is to be read * @param NumberOfBlocks: Total number of blocks to read * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks) { SDMMC_DataInitTypeDef config; uint32_t errorstate; - uint32_t DmaBase0_reg, DmaBase1_reg; + uint32_t DmaBase0_reg; + uint32_t DmaBase1_reg; uint32_t add = BlockAdd; - if(hsd->State == HAL_SD_STATE_READY) + if (hsd->State == HAL_SD_STATE_READY) { - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + if ((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) { hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; return HAL_ERROR; @@ -216,7 +223,7 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint hsd->State = HAL_SD_STATE_BUSY; - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + if (hsd->SdCard.CardType != CARD_SDHC_SDXC) { add *= 512U; } @@ -230,7 +237,7 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint config.DPSM = SDMMC_DPSM_DISABLE; (void)SDMMC_ConfigData(hsd->Instance, &config); - __SDMMC_CMDTRANS_ENABLE( hsd->Instance); + __SDMMC_CMDTRANS_ENABLE(hsd->Instance); hsd->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0; @@ -239,14 +246,15 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint /* Write Multi Block command */ errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); - if(errorstate != HAL_SD_ERROR_NONE) + if (errorstate != HAL_SD_ERROR_NONE) { hsd->State = HAL_SD_STATE_READY; hsd->ErrorCode |= errorstate; return HAL_ERROR; } - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_IT_IDMABTC)); + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | + SDMMC_IT_IDMABTC)); return HAL_OK; } @@ -268,9 +276,10 @@ HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint * transfer use BUFFER0. * @retval HAL status */ -HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer) +HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, + uint32_t *pDataBuffer) { - if(Buffer == SD_DMA_BUFFER0) + if (Buffer == SD_DMA_BUFFER0) { /* change the buffer0 address */ hsd->Instance->IDMABASE0 = (uint32_t)pDataBuffer; diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd_ex.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd_ex.h index c45ff2048c..952093a439 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sd_ex.h @@ -22,7 +22,7 @@ #define STM32L5xx_HAL_SD_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -50,17 +50,15 @@ typedef enum SD_DMA_BUFFER0 = 0x00U, /*!< selects SD internal DMA Buffer 0 */ SD_DMA_BUFFER1 = 0x01U, /*!< selects SD internal DMA Buffer 1 */ -}HAL_SDEx_DMABuffer_MemoryTypeDef; +} HAL_SDEx_DMABuffer_MemoryTypeDef; /** * @} */ - /** * @} */ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ + /* Exported functions --------------------------------------------------------*/ /** @defgroup SDEx_Exported_Functions SDEx Exported Functions * @{ @@ -70,10 +68,12 @@ typedef enum * @{ */ -HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t *pDataBuffer0, uint32_t *pDataBuffer1, + uint32_t BufferSize); HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks); HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer); +HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, + uint32_t *pDataBuffer); void HAL_SDEx_Read_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd); void HAL_SDEx_Read_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd); diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard.c index 75a6777a3f..1eb6858cfd 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard.c @@ -2345,7 +2345,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard uint32_t tmpreg; SMARTCARD_ClockSourceTypeDef clocksource; HAL_StatusTypeDef ret = HAL_OK; - const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; + static const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; uint32_t pclk; /* Check the parameters */ @@ -2370,8 +2370,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard * Configure the Parity and Mode: * set PS bit according to hsmartcard->Init.Parity value * set TE and RE bits according to hsmartcard->Init.Mode value */ - tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode; - tmpreg |= (uint32_t) hsmartcard->Init.WordLength | hsmartcard->FifoMode; + tmpreg = ((uint32_t)(hsmartcard->Init.Parity)) | ((uint32_t)(hsmartcard->Init.Mode)) | ((uint32_t)(hsmartcard->Init.WordLength)); MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard.h index 7fb3afb3a8..9aa89fffcb 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard.h @@ -163,7 +163,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called) + * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -180,7 +180,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard_ex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard_ex.c index c7d3100117..9017dc59cb 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smartcard_ex.c @@ -458,8 +458,8 @@ static void SMARTCARDEx_SetNbDataToProcess(SMARTCARD_HandleTypeDef *hsmartcard) uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_DISABLE) { diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus.h index 3b4248a310..6655ba4dce 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus.h @@ -27,6 +27,7 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32l5xx_hal_def.h" +#include "stm32l5xx_hal_smbus_ex.h" /** @addtogroup STM32L5xx_HAL_Driver * @{ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus_ex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus_ex.c new file mode 100644 index 0000000000..a66237ed68 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus_ex.c @@ -0,0 +1,156 @@ +/** + ****************************************************************************** + * @file stm32l5xx_hal_smbus_ex.c + * @author MCD Application Team + * @brief SMBUS Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of SMBUS Extended peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### SMBUS peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the SMBUS interface for STM32L5xx + devices contains the following additional features + + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_SMBUSEx_EnableFastModePlus() + (++) HAL_SMBUSEx_DisableFastModePlus() + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l5xx_hal.h" + +/** @addtogroup STM32L5xx_HAL_Driver + * @{ + */ + +/** @defgroup SMBUSEx SMBUSEx + * @brief SMBUS Extended HAL module driver + * @{ + */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @defgroup SMBUSEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Enable the SMBUS fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref SMBUSEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @retval None + */ +void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the SMBUS fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref SMBUSEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @retval None + */ +void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_SMBUS_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SMBUS_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus_ex.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus_ex.h new file mode 100644 index 0000000000..ba2350c47d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_smbus_ex.h @@ -0,0 +1,140 @@ +/** + ****************************************************************************** + * @file stm32l5xx_hal_smbus_ex.h + * @author MCD Application Team + * @brief Header file of SMBUS HAL Extended module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L5xx_HAL_SMBUS_EX_H +#define STM32L5xx_HAL_SMBUS_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l5xx_hal_def.h" + +/** @addtogroup STM32L5xx_HAL_Driver + * @{ + */ + +/** @addtogroup SMBUSEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants + * @{ + */ + +/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus + * @{ + */ +#define SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#define SMBUS_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions + * @{ + */ + +/** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions + * @{ + */ +void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros + * @{ + */ +#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8)) == SMBUS_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9)) == SMBUS_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3) || \ + (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C4)) == SMBUS_FASTMODEPLUS_I2C4)) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32l5xx_hal_smbus_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L5xx_HAL_SMBUS_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_spi.c index 9fd89ca56e..406a6b7a61 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_spi.c @@ -1007,6 +1007,9 @@ error: */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; @@ -1173,12 +1176,16 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) { @@ -1190,7 +1197,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 goto error; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } } @@ -1235,6 +1244,9 @@ error : HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; uint32_t tmp_mode; @@ -1476,12 +1488,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -1493,7 +1509,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD goto error; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } } @@ -3048,6 +3066,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3072,12 +3093,16 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) { /* Read 16bit CRC */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { /* Read 8bit CRC */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) { @@ -3087,7 +3112,9 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } } @@ -3152,6 +3179,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -3175,7 +3205,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } else { @@ -3185,7 +3217,9 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); } /* Read CRC to Flush DR and RXNE flag */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); } } #endif /* USE_SPI_CRC */ @@ -3520,8 +3554,12 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 8bit CRC to flush Data Register */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); hspi->CRCSize--; @@ -3628,8 +3666,12 @@ static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 16bit CRC to flush Data Register */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); @@ -3684,8 +3726,12 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 8bit CRC to flush Data Register */ - READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); hspi->CRCSize--; @@ -3738,8 +3784,12 @@ static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) { + __IO uint32_t tmpreg = 0U; + /* Read 16bit CRC to flush Data Register */ - READ_REG(hspi->Instance->DR); + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); @@ -3914,6 +3964,7 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { + __IO uint32_t tmpreg; __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; @@ -3929,8 +3980,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, { if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) { - /* Read 8bit CRC to flush Data Register */ - READ_REG(*((__IO uint8_t *)&hspi->Instance->DR)); + /* Flush Data Register by a blank read */ + tmpreg = READ_REG(*((__IO uint8_t *)&hspi->Instance->DR)); + /* To avoid GCC warning */ + UNUSED(tmpreg); } if (Timeout != HAL_MAX_DELAY) diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sram.c index b3ca520703..d6a10db72e 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sram.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sram.c @@ -127,9 +127,6 @@ * @{ */ -/** - @cond 0 - */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -138,9 +135,6 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma); static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma); static void SRAM_DMAError(DMA_HandleTypeDef *hdma); -/** - @endcond - */ /* Exported functions --------------------------------------------------------*/ @@ -197,7 +191,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp #else /* Initialize the low level hardware (MSP) */ HAL_SRAM_MspInit(hsram); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } /* Initialize SRAM control Interface */ @@ -208,7 +202,7 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp /* Initialize SRAM extended mode timing Interface */ (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, - hsram->Init.ExtendedMode); + hsram->Init.ExtendedMode); /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); @@ -238,7 +232,7 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) #else /* De-Initialize the low level hardware (MSP) */ HAL_SRAM_MspDeInit(hsram); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /* Configure the SRAM registers with their reset values */ (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); @@ -686,7 +680,7 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres } else { - return HAL_ERROR; + status = HAL_ERROR; } return status; @@ -727,7 +721,7 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre } else { - return HAL_ERROR; + status = HAL_ERROR; } return status; @@ -909,7 +903,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR __HAL_UNLOCK(hsram); return status; } -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} @@ -1036,9 +1030,6 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) * @} */ -/** - @cond 0 - */ /** * @brief DMA SRAM process complete callback. * @param hdma : DMA handle @@ -1058,7 +1049,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) hsram->DmaXferCpltCallback(hdma); #else HAL_SRAM_DMA_XferCpltCallback(hdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } /** @@ -1080,7 +1071,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) hsram->DmaXferCpltCallback(hdma); #else HAL_SRAM_DMA_XferCpltCallback(hdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } /** @@ -1102,11 +1093,8 @@ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) hsram->DmaXferErrorCallback(hdma); #else HAL_SRAM_DMA_XferErrorCallback(hdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } -/** - @endcond - */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sram.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sram.h index 5d4820cb07..69c470e5d1 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sram.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_sram.h @@ -78,9 +78,9 @@ typedef struct #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ - void (* DmaXferCpltCallback)(DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */ - void (* DmaXferErrorCallback)(DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */ -#endif + void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } SRAM_HandleTypeDef; #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) @@ -100,7 +100,7 @@ typedef enum */ typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} */ @@ -124,7 +124,7 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); } while(0) #else #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} @@ -182,7 +182,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tim.c index feabba4511..36d72c6ed1 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tim.c @@ -504,7 +504,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - + /* Disable the TIM Update interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); @@ -563,6 +563,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1079,6 +1080,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1099,6 +1101,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1119,6 +1122,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1138,6 +1142,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -1715,6 +1720,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -1735,6 +1741,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1754,6 +1761,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Capture/Compare 3 request */ @@ -1773,6 +1781,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -2068,7 +2077,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2150,7 +2159,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Check the TIM channel state */ if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2302,12 +2311,12 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Set the TIM channel state */ if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { @@ -2324,6 +2333,23 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel return HAL_ERROR; } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + switch (Channel) { case TIM_CHANNEL_1: @@ -2338,6 +2364,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -2357,6 +2384,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -2376,6 +2404,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -2395,6 +2424,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 4 DMA request */ @@ -2406,23 +2436,6 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - /* Return function status */ return HAL_OK; } @@ -2677,11 +2690,12 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) /** * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2696,9 +2710,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2713,7 +2727,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2733,11 +2747,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu /** * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2749,7 +2764,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -2775,11 +2790,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2794,9 +2810,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -2811,7 +2827,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ @@ -2837,11 +2853,12 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param OutputChannel See note above * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) @@ -2859,7 +2876,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); @@ -3131,7 +3148,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3144,7 +3161,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3157,9 +3174,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3249,7 +3266,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - else + else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -3285,7 +3302,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha if (Channel == TIM_CHANNEL_1) { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3298,7 +3315,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3311,9 +3328,9 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -3411,7 +3428,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - else + else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -3451,12 +3468,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch if (Channel == TIM_CHANNEL_1) { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData1 == NULL) && (Length > 0U)) { @@ -3476,12 +3493,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else if (Channel == TIM_CHANNEL_2) { if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData2 == NULL) && (Length > 0U)) { @@ -3501,16 +3518,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch else { if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) { @@ -3544,6 +3561,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3568,6 +3586,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Input Capture DMA request */ @@ -3593,6 +3612,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } @@ -3606,6 +3626,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the Peripheral */ @@ -3684,7 +3705,7 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); } - else + else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -4523,8 +4544,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4540,8 +4562,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4557,8 +4580,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4574,8 +4598,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4591,8 +4616,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4608,8 +4634,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4625,8 +4652,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4846,8 +4874,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4863,8 +4892,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4880,8 +4910,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4897,8 +4928,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4914,8 +4946,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4931,8 +4964,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -4948,8 +4982,9 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } break; @@ -6337,12 +6372,12 @@ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; - + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - + return channel_state; } @@ -6355,7 +6390,7 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - + return htim->DMABurstState; } @@ -6419,14 +6454,14 @@ void TIM_DMAError(DMA_HandleTypeDef *hdma) * @param hdma pointer to DMA handle. * @retval None */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); @@ -6435,7 +6470,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -6444,7 +6479,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); @@ -6453,7 +6488,7 @@ void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); @@ -6524,7 +6559,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); @@ -6534,7 +6569,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -6544,7 +6579,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); @@ -6554,7 +6589,7 @@ void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tim.h index 515cfd7c30..ca8d26c9ec 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tim.h @@ -1071,24 +1071,24 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length * @{ */ -#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ /** * @} */ @@ -2060,7 +2060,7 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ (__HANDLE__)->ChannelState[5]) - + #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ @@ -2083,7 +2083,7 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ (__HANDLE__)->ChannelNState[3]) - + #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tim_ex.c index f98b64b8de..e17e55a4d6 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tim_ex.c @@ -333,9 +333,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -345,7 +345,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - + /* Enable the Input Capture channel 1 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); @@ -413,9 +413,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) /* Check the TIM channels state */ if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } @@ -499,12 +499,12 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Set the TIM channel state */ if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - ||(complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) { return HAL_BUSY; } else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) { if ((pData == NULL) && (Length > 0U)) { @@ -534,6 +534,7 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 /* Enable the DMA channel for Capture 1*/ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the capture compare 1 Interrupt */ @@ -635,7 +636,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { return HAL_ERROR; } - + /* Set the TIM complementary channel state */ TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); @@ -899,6 +900,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -918,6 +920,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -937,6 +940,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Output Compare DMA request */ @@ -1353,6 +1357,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 1 DMA request */ @@ -1372,6 +1377,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 2 DMA request */ @@ -1391,6 +1397,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha /* Enable the DMA channel */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) { + /* Return error status */ return HAL_ERROR; } /* Enable the TIM Capture/Compare 3 DMA request */ @@ -1513,8 +1520,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1523,22 +1532,28 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); - HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the complementary One Pulse output channel and the Input Capture channel */ TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); @@ -1554,8 +1569,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1579,8 +1596,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -1589,8 +1608,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be enabled + * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1599,22 +1620,28 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef input_channel_state = TIM_CHANNEL_STATE_GET(htim, input_channel); - HAL_TIM_ChannelStateTypeDef output_channel_state = TIM_CHANNEL_N_STATE_GET(htim, OutputChannel); + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((output_channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (input_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) { return HAL_ERROR; } /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); @@ -1636,8 +1663,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channel to be disabled + * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1667,8 +1696,10 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t __HAL_TIM_DISABLE(htim); /* Set the TIM channels state */ - TIM_CHANNEL_N_STATE_SET(htim, OutputChannel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, input_channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); /* Return function status */ return HAL_OK; @@ -2399,15 +2430,17 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - do + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) { - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != TIM_BDTR_BKDSRM) + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) { - return HAL_OK; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) + { + return HAL_TIMEOUT; + } } - } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); - - return HAL_TIMEOUT; + } } break; } @@ -2420,15 +2453,17 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - do + while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) { - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != TIM_BDTR_BK2DSRM) + if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) { - return HAL_OK; + /* New check to avoid false timeout detection in case of preemption */ + if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) + { + return HAL_TIMEOUT; + } } - } while ((HAL_GetTick() - tickstart) <= TIM_BREAKINPUT_REARM_TIMEOUT); - - return HAL_TIMEOUT; + } } break; } @@ -2559,12 +2594,12 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; - + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); - + return channel_state; } /** @@ -2631,7 +2666,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) if (hdma == htim->hdma[TIM_DMA_ID_CC1]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); @@ -2640,7 +2675,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); @@ -2649,7 +2684,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); @@ -2658,7 +2693,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) { htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - + if (hdma->Init.Mode == DMA_NORMAL) { TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); @@ -2683,7 +2718,7 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) * @param hdma pointer to DMA handle. * @retval None */ -void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -2706,13 +2741,13 @@ void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) { /* nothing to do */ } - + #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->ErrorCallback(htim); #else HAL_TIM_ErrorCallback(htim); #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tsc.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tsc.c index e3db4fb95d..17edc20b2d 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tsc.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tsc.c @@ -257,6 +257,7 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc) assert_param(IS_TSC_SSD(htsc->Init.SpreadSpectrumDeviation)); assert_param(IS_TSC_SS_PRESC(htsc->Init.SpreadSpectrumPrescaler)); assert_param(IS_TSC_PG_PRESC(htsc->Init.PulseGeneratorPrescaler)); + assert_param(IS_TSC_PG_PRESC_VS_CTPL(htsc->Init.PulseGeneratorPrescaler, htsc->Init.CTPulseLowLength)); assert_param(IS_TSC_MCV(htsc->Init.MaxCountValue)); assert_param(IS_TSC_IODEF(htsc->Init.IODefaultMode)); assert_param(IS_TSC_SYNC_POL(htsc->Init.SynchroPinPolarity)); @@ -430,7 +431,8 @@ __weak void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, pTSC_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID, + pTSC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tsc.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tsc.h index 04afcb0809..dafdc787c2 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tsc.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_tsc.h @@ -634,6 +634,10 @@ typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to ((__VALUE__) == TSC_PG_PRESC_DIV64) || \ ((__VALUE__) == TSC_PG_PRESC_DIV128)) +#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && ((__CTPL__) > TSC_CTPL_2CYCLES)) || \ + (((__PGPSC__) == TSC_PG_PRESC_DIV2) && ((__CTPL__) > TSC_CTPL_1CYCLE)) || \ + (((__PGPSC__) > TSC_PG_PRESC_DIV2) && (((__CTPL__) == TSC_CTPL_1CYCLE) || ((__CTPL__) > TSC_CTPL_1CYCLE)))) + #define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \ ((__VALUE__) == TSC_MCV_511) || \ ((__VALUE__) == TSC_MCV_1023) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_uart.c index d6e7fecb68..e826144bd6 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_uart.c @@ -1370,6 +1370,16 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + return(UART_Start_Receive_IT(huart, pData, Size)); } else @@ -1479,6 +1489,16 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + return(UART_Start_Receive_DMA(huart, pData, Size)); } else @@ -3012,7 +3032,6 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - tmpreg |= (uint32_t)huart->FifoMode; MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*-------------------------- USART CR2 Configuration -----------------------*/ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_uart.h index f6906e4ad5..aac174a063 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_uart.h @@ -146,7 +146,7 @@ typedef struct * 11 : Error * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state @@ -163,7 +163,7 @@ typedef struct * xx : Should be set to 00 * b5 Peripheral initialization status * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_uart_ex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_uart_ex.c index aa75591671..d51e0ea44c 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_uart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_uart_ex.c @@ -977,8 +977,8 @@ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) uint8_t tx_fifo_depth; uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) { diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_usart_ex.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_usart_ex.c index 597cdee31d..a8d5645c11 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_usart_ex.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_hal_usart_ex.c @@ -503,8 +503,8 @@ static void USARTEx_SetNbDataToProcess(USART_HandleTypeDef *husart) uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; /* 2 0U/1U added for MISRAC2012-Rule-18.1_b and MISRAC2012-Rule-18.1_d */ - uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (husart->FifoMode == USART_FIFOMODE_DISABLE) { diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_adc.c index 195558e45d..aca110e742 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_adc.c @@ -825,6 +825,11 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + + /* ADC group regular continuous mode and discontinuous mode */ + /* can not be enabled simultenaeously */ + assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); } assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); @@ -941,6 +946,12 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). * - Set ADC channel sampling time * Refer to function LL_ADC_SetChannelSamplingTime(); + * @note Caution if feature ADC group injected contexts queue is enabled + * (refer to with function @ref LL_ADC_INJ_SetQueueMode() ): + * using successively several times this function will appear as + * having no effect. + * To set several features of ADC group injected, use + * function @ref LL_ADC_INJ_ConfigQueueContext(). * @param ADCx ADC instance * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure * @retval An ErrorStatus enumeration value: diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_adc.h index 2cbb89c4e2..5cfcf804ab 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_adc.h @@ -1285,7 +1285,7 @@ typedef struct /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tADCVREG_STUP"). */ /* Unit: us */ -#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ +#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ /* Delay for internal voltage reference stabilization time. */ /* Delay set to maximum value (refer to device datasheet, */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_bus.h index e702642547..79cfe53307 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_bus.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_bus.h @@ -219,7 +219,7 @@ extern "C" { * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC * @retval None -*/ + */ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -247,7 +247,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC * @retval State of Periphs (1 or 0). -*/ + */ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); @@ -272,7 +272,7 @@ __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC * @retval None -*/ + */ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->AHB1ENR, Periphs); @@ -295,7 +295,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @retval None -*/ + */ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->AHB1RSTR, Periphs); @@ -318,7 +318,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_CRC * @arg @ref LL_AHB1_GRP1_PERIPH_TSC * @retval None -*/ + */ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->AHB1RSTR, Periphs); @@ -347,7 +347,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE * @retval None -*/ + */ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -380,7 +380,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE * @retval None -*/ + */ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) { CLEAR_BIT(RCC->AHB1SMENR, Periphs); @@ -431,7 +431,7 @@ __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * * (*) value not defined in all devices. * @retval None -*/ + */ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -477,7 +477,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) * * (*) value not defined in all devices. * @retval State of Periphs (1 or 0). -*/ + */ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL); @@ -520,7 +520,7 @@ __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) * * (*) value not defined in all devices. * @retval None -*/ + */ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->AHB2ENR, Periphs); @@ -563,7 +563,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) * * (*) value not defined in all devices. * @retval None -*/ + */ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->AHB2RSTR, Periphs); @@ -606,7 +606,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) * * (*) value not defined in all devices. * @retval None -*/ + */ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->AHB2RSTR, Periphs); @@ -651,7 +651,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) * * (*) value not defined in all devices. * @retval None -*/ + */ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -700,7 +700,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * * (*) value not defined in all devices. * @retval None -*/ + */ __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) { CLEAR_BIT(RCC->AHB2SMENR, Periphs); @@ -723,7 +723,7 @@ __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB3_GRP1_PERIPH_FMC * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 * @retval None -*/ + */ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -741,7 +741,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_AHB3_GRP1_PERIPH_FMC * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 * @retval State of Periphs (1 or 0). -*/ + */ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); @@ -756,7 +756,7 @@ __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_AHB3_GRP1_PERIPH_FMC * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 * @retval None -*/ + */ __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->AHB3ENR, Periphs); @@ -771,7 +771,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_AHB3_GRP1_PERIPH_FMC * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 * @retval None -*/ + */ __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->AHB3RSTR, Periphs); @@ -786,7 +786,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_AHB3_GRP1_PERIPH_FMC * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 * @retval None -*/ + */ __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->AHB3RSTR, Periphs); @@ -801,7 +801,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_AHB3_GRP1_PERIPH_FMC * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 * @retval None -*/ + */ __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -820,7 +820,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_AHB3_GRP1_PERIPH_FMC * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 * @retval None -*/ + */ __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs) { CLEAR_BIT(RCC->AHB3SMENR, Periphs); @@ -883,7 +883,7 @@ __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -912,7 +912,7 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_USB * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -970,7 +970,7 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 * @retval State of Periphs (1 or 0). -*/ + */ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL); @@ -994,7 +994,7 @@ __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_USB * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 * @retval State of Periphs (1 or 0). -*/ + */ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); @@ -1049,7 +1049,7 @@ __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->APB1ENR1, Periphs); @@ -1074,7 +1074,7 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_USB * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->APB1ENR2, Periphs); @@ -1127,7 +1127,7 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->APB1RSTR1, Periphs); @@ -1152,7 +1152,7 @@ __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_USB * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) { SET_BIT(RCC->APB1RSTR2, Periphs); @@ -1205,7 +1205,7 @@ __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->APB1RSTR1, Periphs); @@ -1230,7 +1230,7 @@ __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_USB * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->APB1RSTR2, Periphs); @@ -1285,7 +1285,7 @@ __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1314,7 +1314,7 @@ __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_USB * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1373,7 +1373,7 @@ __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) { CLEAR_BIT(RCC->APB1SMENR1, Periphs); @@ -1398,7 +1398,7 @@ __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB1_GRP2_PERIPH_USB * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) { CLEAR_BIT(RCC->APB1SMENR2, Periphs); @@ -1439,7 +1439,7 @@ __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1475,7 +1475,7 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 * @retval State of Periphs (1 or 0). -*/ + */ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) { return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL); @@ -1508,7 +1508,7 @@ __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) { CLEAR_BIT(RCC->APB2ENR, Periphs); @@ -1541,7 +1541,7 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) { SET_BIT(RCC->APB2RSTR, Periphs); @@ -1574,7 +1574,7 @@ __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) { CLEAR_BIT(RCC->APB2RSTR, Periphs); @@ -1607,7 +1607,7 @@ __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) { __IO uint32_t tmpreg; @@ -1644,7 +1644,7 @@ __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 * @retval None -*/ + */ __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) { CLEAR_BIT(RCC->APB2SMENR, Periphs); diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_cortex.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_cortex.h index dfcf6232d6..2eeeac9e93 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_cortex.h @@ -83,6 +83,112 @@ extern "C" { * @} */ +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U +#define LL_MPU_CTRL_HARDFAULT_NMI 2U +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U +#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Attributes MPU Attributes + * @{ + */ +#define LL_MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ +#define LL_MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ +#define LL_MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ +#define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ + +#define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ +#define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ +#define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ + +#define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */ +#define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ + +#define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ +#define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ +#define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ +#define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Enable MPU Region Enable + * @{ + */ +#define LL_MPU_REGION_ENABLE 1U +#define LL_MPU_REGION_DISABLE 0U +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Instruction_Access MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Access_Shareable MPU Instruction Access Shareable + * @{ + */ +#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) +#define LL_MPU_ACCESS_OUTER_SHAREABLE (1U << MPU_RBAR_SH_Pos) +#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes MPU Region Permission Attributes + * @{ + */ +#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Region_Number MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0U +#define LL_MPU_REGION_NUMBER1 1U +#define LL_MPU_REGION_NUMBER2 2U +#define LL_MPU_REGION_NUMBER3 3U +#define LL_MPU_REGION_NUMBER4 4U +#define LL_MPU_REGION_NUMBER5 5U +#define LL_MPU_REGION_NUMBER6 6U +#define LL_MPU_REGION_NUMBER7 7U +/** + * @} + */ + +/** @defgroup CORTEX_LL_MPU_Attributes_Number MPU Memory Attributes Number + * @{ + */ +#define LL_MPU_ATTRIBUTES_NUMBER0 0U +#define LL_MPU_ATTRIBUTES_NUMBER1 1U +#define LL_MPU_ATTRIBUTES_NUMBER2 2U +#define LL_MPU_ATTRIBUTES_NUMBER3 3U +#define LL_MPU_ATTRIBUTES_NUMBER4 4U +#define LL_MPU_ATTRIBUTES_NUMBER5 5U +#define LL_MPU_ATTRIBUTES_NUMBER6 6U +#define LL_MPU_ATTRIBUTES_NUMBER7 7U +/** + * @} + */ + +#endif /* __MPU_PRESENT */ + /** * @} */ @@ -361,6 +467,795 @@ __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) * @} */ +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable\n + * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Enable\n + * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Enable + * @param MPU_Control This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU*/ + MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; + + /* Ensure MPU settings take effects */ + __DSB(); + + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable\n + * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Disable\n + * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RNR REGION LL_MPU_EnableRegion\n + * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Enable the MPU region */ + SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Check if MPU region is enabled or not + * @rmtoll MPU_RNR REGION LL_MPU_IsEnabledRegion\n + * @rmtoll MPU_RLAR EN LL_MPU_IsEnabledRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion(uint32_t Region) +{ + return ((READ_BIT(MPU->RNR, Region) == (Region)) ? 1UL : 0UL); +} + +/** + * @brief Disable a MPU region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * @rmtoll MPU_RLAR EN LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Disable the MPU region */ + CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Configure and enable a MPU region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RLAR ADDR LL_MPU_ConfigRegion\n + * MPU_RBAR XN LL_MPU_ConfigRegion\n + * MPU_RBAR AP LL_MPU_ConfigRegion\n + * MPU_RBAR SH LL_MPU_ConfigRegion\n + * MPU_RLAR EN LL_MPU_ConfigRegion\n + * MPU_RLAR AttrIndx LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param AttrIndx This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_ALL_RO + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set base address */ + MPU->RBAR |= Attributes; + /* Set base address */ + MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U); + + /* Set limit address */ + MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U); + /* Configure MPU */ + MPU->RLAR |= (MPU_RLAR_EN_Msk | AttrIndx); +} + +/** + * @brief Configure a MPU region address range + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n + * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n + * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + + /* Set base address */ + MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U) ; + + /* Set limit address */ + MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U); +} + +/** + * @brief Configure a MPU attributes index + * @rmtoll MPU_MAIR0 ATTR0 LL_MPU_ConfigAttributes\n + * MPU_MAIR0 ATTR1 LL_MPU_ConfigAttributes\n + * MPU_MAIR0 ATTR2 LL_MPU_ConfigAttributes\n + * MPU_MAIR0 ATTR3 LL_MPU_ConfigAttributes\n + * MPU_MAIR1 ATTR4 LL_MPU_ConfigAttributes\n + * MPU_MAIR1 ATTR5 LL_MPU_ConfigAttributes\n + * MPU_MAIR1 ATTR6 LL_MPU_ConfigAttributes\n + * MPU_MAIR1 ATTR7 LL_MPU_ConfigAttributes + * @param AttIndex This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param Attributes This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes) +{ + if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) + { + /* Program MPU_MAIR0 */ + WRITE_REG(MPU->MAIR0, (Attributes << (AttIndex * 8U))); + } + else + { + /* Program MPU_MAIR1 */ + WRITE_REG(MPU->MAIR1, (Attributes << ((AttIndex - 4U) * 8U))); + } +} + +/** + * @brief Configure a MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n + * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + MPU->RBAR |= (BaseAddress & 0xFFFFFFE0U); +} + +/** + * @brief Get a MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n + * @rmtoll MPU_RBAR BASE LL_MPU_GetRegionBaseAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Configure a MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n + * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param LimitAddress Value of region limit address + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set limit address */ + MPU->RLAR |= (LimitAddress & 0xFFFFFFE0U); +} + +/** + * @brief Get a MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n + * @rmtoll MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Configure a MPU region access attributes and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n + * MPU_RBAR XN LL_MPU_SetRegionAccess\n + * MPU_RBAR AP LL_MPU_SetRegionAccess\n + * MPU_RBAR SH LL_MPU_SetRegionAccess + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_ALL_RO + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + MPU->RBAR |= Attributes; +} + +/** + * @brief Get a MPU region access attributes + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n + * MPU_RBAR XN LL_MPU_GetRegionAccess\n + * MPU_RBAR AP LL_MPU_GetRegionAccess\n + * MPU_RBAR SH LL_MPU_GetRegionAccess + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief Enable non-secure MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable_NS\n + * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Enable_NS\n + * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Enable_NS + * @param MPU_Control This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control) +{ + /* Enable the MPU*/ + MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; + + /* Ensure MPU settings take effects */ + __DSB(); + + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable non-secure MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS\n + * @rmtoll MPU_CTRL HFNMIENA LL_MPU_Disable_NS\n + * @rmtoll MPU_CTRL PRIVDEFENA LL_MPU_Disable_NS + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable_NS(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU_NS->CTRL, 0U); +} + +/** + * @brief Check if non-secure MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void) +{ + return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Enable a non-secure MPU region + * @rmtoll MPU_RNR REGION LL_MPU_EnableRegion_NS\n + * @rmtoll MPU_RLAR EN LL_MPU_EnableRegion_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Enable the MPU region */ + SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Disable a non-secure MPU region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n + * @rmtoll MPU_RLAR EN LL_MPU_DisableRegion_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Disable the MPU region */ + CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); +} + +/** + * @brief Check if non-secure MPU region is enabled or not + * @rmtoll MPU_RNR REGION LL_MPU_IsEnabledRegion_NS\n + * @rmtoll MPU_RLAR EN LL_MPU_IsEnabledRegion_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabledRegion_NS(uint32_t Region) +{ + return ((READ_BIT(MPU_NS->RNR, Region) == (Region)) ? 1UL : 0UL); +} + +/** + * @brief Configure and enable a non-secure MPU region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n + * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n + * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n + * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n + * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n + * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n + * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param AttrIndx This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_ALL_RO + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address */ + MPU_NS->RBAR |= Attributes; + + /* Set base address */ + MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U); + + /* Set limit address */ + MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U); + /* Configure MPU */ + MPU_NS->RLAR |= (MPU_RLAR_EN_Msk | AttrIndx); +} + +/** + * @brief Configure a non-secure MPU region address range + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n + * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n + * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @param LimitAddress Value of region limit address + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + + /* Set base address */ + MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U); + + /* Set limit address */ + MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U); +} + +/** + * @brief Configure a non-secure MPU attributes index + * @rmtoll MPU_MAIR0 ATTR0 LL_MPU_ConfigAttributes_NS\n + * MPU_MAIR0 ATTR1 LL_MPU_ConfigAttributes_NS\n + * MPU_MAIR0 ATTR2 LL_MPU_ConfigAttributes_NS\n + * MPU_MAIR0 ATTR3 LL_MPU_ConfigAttributes_NS\n + * MPU_MAIR1 ATTR4 LL_MPU_ConfigAttributes_NS\n + * MPU_MAIR1 ATTR5 LL_MPU_ConfigAttributes_NS\n + * MPU_MAIR1 ATTR6 LL_MPU_ConfigAttributes_NS\n + * MPU_MAIR1 ATTR7 LL_MPU_ConfigAttributes_NS + * @param AttIndex This parameter can be one of the following values: + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 + * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 + * @param Attributes This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes) +{ + if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) + { + /* Program MPU_MAIR0 */ + WRITE_REG(MPU_NS->MAIR0, (Attributes << (AttIndex * 8U))); + } + else + { + /* Program MPU_MAIR1 */ + WRITE_REG(MPU_NS->MAIR1, (Attributes << ((AttIndex - 4U) * 8U))); + } +} + +/** + * @brief Configure a non-secure MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n + * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param BaseAddress Value of region base address + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + /* Set base address */ + MPU_NS->RBAR |= (BaseAddress & 0xFFFFFFE0U); +} + +/** + * @brief Get a non-secure MPU region base address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n + * @rmtoll MPU_RBAR BASE LL_MPU_GetRegionBaseAddress_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk)); +} + +/** + * @brief Configure a non-secure MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n + * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param LimitAddress Value of region limit address + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + /* Set limit address */ + MPU_NS->RLAR |= (LimitAddress & 0xFFFFFFE0U); +} + +/** + * @brief Get a non-secure MPU region limit address + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n + * @rmtoll MPU_RLAR LIMIT LL_MPU_GetRegionLimitAddress_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk)); +} + +/** + * @brief Configure a non-secure MPU region access attributes and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n + * MPU_RBAR SH LL_MPU_SetRegionAccess_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE or @ref LL_MPU_ACCESS_INNER_SHAREABLE + * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_ALL_RO + * @note cortex-M33 support 8 secure and 8 non secure regions. + * @retval None + */ +__STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + /* Set base address Attributes */ + MPU_NS->RBAR |= Attributes; +} + +/** + * @brief Get a non-secure MPU region access attributes + * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n + * MPU_RBAR SH LL_MPU_GetRegionAccess_NS + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU_NS->RNR, Region); + return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); +} +#endif /* __ARM_FEATURE_CMSE */ + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_fmc.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_fmc.c index 220210f4ad..1b5f0b41a7 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_fmc.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_fmc.c @@ -58,7 +58,7 @@ /** @addtogroup STM32L5xx_HAL_Driver * @{ */ -#if ((defined HAL_NOR_MODULE_ENABLED || defined HAL_SRAM_MODULE_ENABLED) || defined HAL_NAND_MODULE_ENABLED ) +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules @@ -86,15 +86,9 @@ /* --- BWTR Register ---*/ /* BWTR register clear mask */ -#if defined(FMC_BWTRx_BUSTURN) #define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ FMC_BWTRx_DATAST | FMC_BWTRx_BUSTURN |\ FMC_BWTRx_ACCMOD | FMC_BWTRx_DATAHLD)) -#else -#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\ - FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD |\ - FMC_BWTRx_DATAHLD)) -#endif /* FMC_BWTRx_BUSTURN */ /* --- PCR Register ---*/ /* PCR register clear mask */ @@ -176,7 +170,7 @@ * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init) + FMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; uint32_t btcr_reg; @@ -290,11 +284,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); break; - case FMC_NORSRAM_BANK4 : - SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); - break; - default : + SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); break; } } @@ -310,7 +301,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); @@ -350,11 +341,8 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); break; - case FMC_NORSRAM_BANK4 : - CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); - break; - default : + CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); break; } @@ -370,7 +358,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { uint32_t tmpr; @@ -399,7 +387,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0F) << FMC_BTRx_CLKDIV_Pos)); + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); } @@ -420,7 +408,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) { /* Check the parameters */ assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); @@ -434,9 +423,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); -#if defined(FMC_BWTRx_BUSTURN) assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); -#endif /* FMC_BWTRx_BUSTURN */ assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); @@ -445,12 +432,8 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | ((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) | -#if defined(FMC_BWTRx_BUSTURN) Timing->AccessMode | ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); -#else - Timing->AccessMode)); -#endif /* FMC_BWTRx_BUSTURN */ } else { @@ -605,7 +588,7 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -636,7 +619,7 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -758,7 +741,7 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, - uint32_t Timeout) + uint32_t Timeout) { uint32_t tickstart; diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_fmc.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_fmc.h index 585bba8126..80a46801bc 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_fmc.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_fmc.h @@ -41,51 +41,51 @@ extern "C" { */ #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ - ((__BANK__) == FMC_NORSRAM_BANK2) || \ - ((__BANK__) == FMC_NORSRAM_BANK3) || \ - ((__BANK__) == FMC_NORSRAM_BANK4)) + ((__BANK__) == FMC_NORSRAM_BANK2) || \ + ((__BANK__) == FMC_NORSRAM_BANK3) || \ + ((__BANK__) == FMC_NORSRAM_BANK4)) #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) + ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) + ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ - ((__SIZE__) == FMC_PAGE_SIZE_128) || \ - ((__SIZE__) == FMC_PAGE_SIZE_256) || \ - ((__SIZE__) == FMC_PAGE_SIZE_512) || \ - ((__SIZE__) == FMC_PAGE_SIZE_1024)) + ((__SIZE__) == FMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FMC_PAGE_SIZE_512) || \ + ((__SIZE__) == FMC_PAGE_SIZE_1024)) #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ - ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) + ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ - ((__MODE__) == FMC_ACCESS_MODE_B) || \ - ((__MODE__) == FMC_ACCESS_MODE_C) || \ - ((__MODE__) == FMC_ACCESS_MODE_D)) + ((__MODE__) == FMC_ACCESS_MODE_B) || \ + ((__MODE__) == FMC_ACCESS_MODE_C) || \ + ((__MODE__) == FMC_ACCESS_MODE_D)) #define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \ - ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ - ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ - ((__NBL__) == FMC_NBL_SETUPTIME_3)) + ((__NBL__) == FMC_NBL_SETUPTIME_1) || \ + ((__NBL__) == FMC_NBL_SETUPTIME_2) || \ + ((__NBL__) == FMC_NBL_SETUPTIME_3)) #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) + ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) + ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) + ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) + ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) + ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) + ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) + ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FMC_WRITE_BURST_ENABLE)) + ((__BURST__) == FMC_WRITE_BURST_ENABLE)) #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ - ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) + ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) @@ -99,18 +99,18 @@ extern "C" { #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ - ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) + ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) + ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ - ((__STATE__) == FMC_NAND_ECC_ENABLE)) + ((__STATE__) == FMC_NAND_ECC_ENABLE)) #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) @@ -144,75 +144,75 @@ extern "C" { typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Write_FIFO */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ + This parameter can be a value of @ref FMC_Page_Size */ uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number - This parameter can be a value of @ref FMC_Byte_Lane */ + This parameter can be a value of @ref FMC_Byte_Lane */ - FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this NSBank - for PSRAM refresh. - This parameter can be set to ENABLE or DISABLE */ + FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this + NSBank for PSRAM refresh. + This parameter can be set to ENABLE or DISABLE */ - uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for synchronous - accesses and in HCLK cycles for asynchronous accesses, + uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for + synchronous accesses and in HCLK cycles for asynchronous accesses, valid only if MaxChipSelectPulse is ENABLE. This parameter can be a value between Min_Data = 1 and Max_Data = 65535. - @note: This parameter is common to all NSBank. */ -}FMC_NORSRAM_InitTypeDef; + @note: This parameter is common to all NSBank. */ +} FMC_NORSRAM_InitTypeDef; /** * @brief FMC NORSRAM Timing parameters structure definition @@ -222,45 +222,46 @@ typedef struct uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the address setup time. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. This parameter can be a value between Min_Data = 1 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between Min_Data = 1 and Max_Data = 255. @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed - NOR Flash memories. */ + NOR Flash memories. */ uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the data hold time. This parameter can be a value between Min_Data = 0 and Max_Data = 3. - @note This parameter is used for used in asynchronous accesses. */ + @note This parameter is used for used in asynchronous accesses. */ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is only used for multiplexed NOR Flash memories. */ + @note This parameter is only used for multiplexed NOR Flash memories. */ uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of - HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. + HCLK cycles. This parameter can be a value between Min_Data = 2 and + Max_Data = 16. @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM - accesses. */ + accesses. */ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories - with synchronous burst mode enable */ + - It may assume a value between Min_Data = 2 and Max_Data = 17 + in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ -}FMC_NORSRAM_TimingTypeDef; + This parameter can be a value of @ref FMC_Access_Mode */ +} FMC_NORSRAM_TimingTypeDef; /** * @brief FMC NAND Configuration Structure definition @@ -268,19 +269,19 @@ typedef struct typedef struct { uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. - This parameter can be a value of @ref FMC_NAND_Bank */ + This parameter can be a value of @ref FMC_NAND_Bank */ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. - This parameter can be any value of @ref FMC_Wait_feature */ + This parameter can be any value of @ref FMC_Wait_feature */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FMC_NAND_Data_Width */ + This parameter can be any value of @ref FMC_NAND_Data_Width */ uint32_t EccComputation; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FMC_ECC */ + This parameter can be any value of @ref FMC_ECC */ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FMC_ECC_Page_Size */ + This parameter can be any value of @ref FMC_ECC_Page_Size */ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. @@ -289,7 +290,7 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ -}FMC_NAND_InitTypeDef; +} FMC_NAND_InitTypeDef; /** * @brief FMC NAND Timing parameters structure definition @@ -320,7 +321,7 @@ typedef struct write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ -}FMC_NAND_PCC_TimingTypeDef; +} FMC_NAND_PCC_TimingTypeDef; /** @@ -339,10 +340,10 @@ typedef struct /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank * @{ */ -#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000) -#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002) -#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004) -#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006) +#define FMC_NORSRAM_BANK1 (0x00000000U) +#define FMC_NORSRAM_BANK2 (0x00000002U) +#define FMC_NORSRAM_BANK3 (0x00000004U) +#define FMC_NORSRAM_BANK4 (0x00000006U) /** * @} */ @@ -350,8 +351,8 @@ typedef struct /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing * @{ */ -#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) -#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002) +#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) /** * @} */ @@ -359,9 +360,9 @@ typedef struct /** @defgroup FMC_Memory_Type FMC Memory Type * @{ */ -#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) -#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004) -#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008) +#define FMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FMC_MEMORY_TYPE_NOR (0x00000008U) /** * @} */ @@ -369,9 +370,9 @@ typedef struct /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width * @{ */ -#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) -#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) -#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020) +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) /** * @} */ @@ -379,8 +380,8 @@ typedef struct /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access * @{ */ -#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040) -#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) /** * @} */ @@ -388,8 +389,8 @@ typedef struct /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode * @{ */ -#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) -#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100) +#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) /** * @} */ @@ -397,8 +398,8 @@ typedef struct /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity * @{ */ -#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) -#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200) +#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) /** * @} */ @@ -406,8 +407,8 @@ typedef struct /** @defgroup FMC_Wait_Timing FMC Wait Timing * @{ */ -#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) -#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800) +#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) +#define FMC_WAIT_TIMING_DURING_WS (0x00000800U) /** * @} */ @@ -415,8 +416,8 @@ typedef struct /** @defgroup FMC_Write_Operation FMC Write Operation * @{ */ -#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) -#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000) +#define FMC_WRITE_OPERATION_DISABLE (0x00000000U) +#define FMC_WRITE_OPERATION_ENABLE (0x00001000U) /** * @} */ @@ -424,8 +425,8 @@ typedef struct /** @defgroup FMC_Wait_Signal FMC Wait Signal * @{ */ -#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) -#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000) +#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) /** * @} */ @@ -433,8 +434,8 @@ typedef struct /** @defgroup FMC_Extended_Mode FMC Extended Mode * @{ */ -#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) -#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000) +#define FMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FMC_EXTENDED_MODE_ENABLE (0x00004000U) /** * @} */ @@ -442,8 +443,8 @@ typedef struct /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait * @{ */ -#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) -#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000) +#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) /** * @} */ @@ -451,12 +452,12 @@ typedef struct /** @defgroup FMC_Page_Size FMC Page Size * @{ */ -#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000) -#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0) -#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1) -#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0\ - | FMC_BCRx_CPSIZE_1)) -#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2) +#define FMC_PAGE_SIZE_NONE (0x00000000U) +#define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0 +#define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1 +#define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\ + | FMC_BCRx_CPSIZE_1) +#define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2 /** * @} */ @@ -464,8 +465,8 @@ typedef struct /** @defgroup FMC_Write_Burst FMC Write Burst * @{ */ -#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) -#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000) +#define FMC_WRITE_BURST_DISABLE (0x00000000U) +#define FMC_WRITE_BURST_ENABLE (0x00080000U) /** * @} */ @@ -473,8 +474,8 @@ typedef struct /** @defgroup FMC_Continous_Clock FMC Continuous Clock * @{ */ -#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000) -#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000) +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) /** * @} */ @@ -482,19 +483,19 @@ typedef struct /** @defgroup FMC_Write_FIFO FMC Write FIFO * @{ */ -#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) -#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000) +#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS +#define FMC_WRITE_FIFO_ENABLE (0x00000000U) /** * @} */ /** @defgroup FMC_Access_Mode FMC Access Mode * @{ -*/ -#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000) -#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000) -#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000) -#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000) + */ +#define FMC_ACCESS_MODE_A (0x00000000U) +#define FMC_ACCESS_MODE_B (0x10000000U) +#define FMC_ACCESS_MODE_C (0x20000000U) +#define FMC_ACCESS_MODE_D (0x30000000U) /** * @} */ @@ -502,10 +503,10 @@ typedef struct /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup * @{ */ -#define FMC_NBL_SETUPTIME_0 ((uint32_t)0x00000000) -#define FMC_NBL_SETUPTIME_1 ((uint32_t)0x00400000) -#define FMC_NBL_SETUPTIME_2 ((uint32_t)0x00800000) -#define FMC_NBL_SETUPTIME_3 ((uint32_t)0x00C00000) +#define FMC_NBL_SETUPTIME_0 (0x00000000U) +#define FMC_NBL_SETUPTIME_1 (0x00400000U) +#define FMC_NBL_SETUPTIME_2 (0x00800000U) +#define FMC_NBL_SETUPTIME_3 (0x00C00000U) /** * @} */ @@ -521,7 +522,7 @@ typedef struct /** @defgroup FMC_NAND_Bank FMC NAND Bank * @{ */ -#define FMC_NAND_BANK3 ((uint32_t)0x00000100) +#define FMC_NAND_BANK3 (0x00000100U) /** * @} */ @@ -529,8 +530,8 @@ typedef struct /** @defgroup FMC_Wait_feature FMC Wait feature * @{ */ -#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000) -#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002) +#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) +#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) /** * @} */ @@ -538,7 +539,7 @@ typedef struct /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type * @{ */ -#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008) +#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) /** * @} */ @@ -546,8 +547,8 @@ typedef struct /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width * @{ */ -#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) -#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010) +#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) /** * @} */ @@ -555,8 +556,8 @@ typedef struct /** @defgroup FMC_ECC FMC ECC * @{ */ -#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000) -#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040) +#define FMC_NAND_ECC_DISABLE (0x00000000U) +#define FMC_NAND_ECC_ENABLE (0x00000040U) /** * @} */ @@ -564,12 +565,12 @@ typedef struct /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size * @{ */ -#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000) -#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000) -#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000) -#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000) -#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000) -#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000) +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) +#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) +#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) +#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) +#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) +#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) /** * @} */ @@ -582,9 +583,9 @@ typedef struct /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition * @{ */ -#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008) -#define FMC_IT_LEVEL ((uint32_t)0x00000010) -#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020) +#define FMC_IT_RISING_EDGE (0x00000008U) +#define FMC_IT_LEVEL (0x00000010U) +#define FMC_IT_FALLING_EDGE (0x00000020U) /** * @} */ @@ -592,10 +593,10 @@ typedef struct /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition * @{ */ -#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001) -#define FMC_FLAG_LEVEL ((uint32_t)0x00000002) -#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004) -#define FMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define FMC_FLAG_RISING_EDGE (0x00000001U) +#define FMC_FLAG_LEVEL (0x00000002U) +#define FMC_FLAG_FALLING_EDGE (0x00000004U) +#define FMC_FLAG_FEMPT (0x00000040U) /** * @} */ @@ -624,7 +625,7 @@ typedef struct * @retval None */ #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ - |= FMC_BCRx_MBKEN) + |= FMC_BCRx_MBKEN) /** * @brief Disable the NORSRAM device access. @@ -633,7 +634,7 @@ typedef struct * @retval None */ #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ - &= ~FMC_BCRx_MBKEN) + &= ~FMC_BCRx_MBKEN) /** * @} @@ -744,13 +745,14 @@ typedef struct * @{ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init); + FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); /** * @} */ @@ -775,9 +777,9 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic */ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -789,7 +791,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, - uint32_t Timeout); + uint32_t Timeout); /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_icache.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_icache.c new file mode 100644 index 0000000000..c71bcf9364 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_icache.c @@ -0,0 +1,139 @@ +/** + ****************************************************************************** + * @file stm32l5xx_ll_icache.c + * @author MCD Application Team + * @brief ICACHE LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l5xx_ll_icache.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32L5xx_LL_Driver + * @{ + */ + +#if defined(ICACHE) + +/** @defgroup ICACHE_LL ICACHE + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Private_Macros ICACHE Private Macros + * @{ + */ + +#define IS_LL_ICACHE_REGION(__VALUE__) (((__VALUE__) == LL_ICACHE_REGION_0) || \ + ((__VALUE__) == LL_ICACHE_REGION_1) || \ + ((__VALUE__) == LL_ICACHE_REGION_2) || \ + ((__VALUE__) == LL_ICACHE_REGION_3)) + +#define IS_LL_ICACHE_REGION_SIZE(__VALUE__) (((__VALUE__) == LL_ICACHE_REGIONSIZE_2MB) || \ + ((__VALUE__) == LL_ICACHE_REGIONSIZE_4MB) || \ + ((__VALUE__) == LL_ICACHE_REGIONSIZE_8MB) || \ + ((__VALUE__) == LL_ICACHE_REGIONSIZE_16MB) || \ + ((__VALUE__) == LL_ICACHE_REGIONSIZE_32MB) || \ + ((__VALUE__) == LL_ICACHE_REGIONSIZE_64MB) || \ + ((__VALUE__) == LL_ICACHE_REGIONSIZE_128MB)) + +#define IS_LL_ICACHE_MASTER_PORT(__VALUE__) (((__VALUE__) == LL_ICACHE_MASTER1_PORT) || \ + ((__VALUE__) == LL_ICACHE_MASTER2_PORT)) + +#define IS_LL_ICACHE_OUTPUT_BURST(__VALUE__) (((__VALUE__) == LL_ICACHE_OUTPUT_BURST_WRAP) || \ + ((__VALUE__) == LL_ICACHE_OUTPUT_BURST_INCR)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ICACHE_LL_Exported_Functions + * @{ + */ + +/** @addtogroup ICACHE_LL_EF_REGION_Init + * @{ + */ + +/** + * @brief Configure and enable the memory remapped region. + * @note The Instruction Cache and corresponding region must be disabled. + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param ICACHE_RegionStruct pointer to a @ref LL_ICACHE_RegionTypeDef structure. + * @retval None + */ +void LL_ICACHE_ConfigRegion(uint32_t Region, LL_ICACHE_RegionTypeDef *ICACHE_RegionStruct) +{ + __IO uint32_t *reg; + uint32_t value; + + /* Check the parameters */ + assert_param(IS_LL_ICACHE_REGION(Region)); + assert_param(IS_LL_ICACHE_REGION_SIZE(ICACHE_RegionStruct->Size)); + assert_param(IS_LL_ICACHE_MASTER_PORT(ICACHE_RegionStruct->TrafficRoute)); + assert_param(IS_LL_ICACHE_OUTPUT_BURST(ICACHE_RegionStruct->OutputBurstType)); + + /* Get region control register address */ + reg = &(ICACHE->CRR0) + (1U * Region); + + /* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */ + /* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */ + /* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */ + /* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */ + /* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */ + /* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */ + /* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */ + value = ((ICACHE_RegionStruct->BaseAddress & 0x1FFFFFFFU) >> 21U) & (0xFFU & ~(ICACHE_RegionStruct->Size - 1U)); + value |= ((ICACHE_RegionStruct->RemapAddress >> 5U) & ((uint32_t)(0x7FFU & ~(ICACHE_RegionStruct->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos)); + value |= (ICACHE_RegionStruct->Size << ICACHE_CRRx_RSIZE_Pos) | ICACHE_RegionStruct->TrafficRoute | ICACHE_RegionStruct->OutputBurstType; + *reg = (value | ICACHE_CRRx_REN); /* Configure and enable region */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ICACHE */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_icache.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_icache.h new file mode 100644 index 0000000000..6cfebd43e5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_icache.h @@ -0,0 +1,782 @@ +/** + ****************************************************************************** + * @file stm32l5xx_ll_icache.h + * @author MCD Application Team + * @brief Header file of ICACHE LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion ------------------------------------*/ +#ifndef STM32L5xx_LL_ICACHE_H +#define STM32L5xx_LL_ICACHE_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes -----------------------------------------------------------------*/ +#include "stm32l5xx.h" + +/** @addtogroup STM32L5xx_LL_Driver + * @{ + */ + +#if defined(ICACHE) + +/** @defgroup ICACHE_LL ICACHE + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure + * @{ + */ + +/** + * @brief LL ICACHE region configuration structure definition + */ +typedef struct +{ + uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */ + + uint32_t RemapAddress; /*!< Configures the remap address to be remapped */ + + uint32_t Size; /*!< Configures the region size. + This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */ + + uint32_t TrafficRoute; /*!< Selects the traffic route. + This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */ + + uint32_t OutputBurstType; /*!< Selects the output burst type. + This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */ +} LL_ICACHE_RegionTypeDef; + +/** + * @} + */ + +/* Exported constants -------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants + * @{ + */ + +/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection + * @{ + */ +#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ +#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type + * @{ + */ +#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */ +#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */ +#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_ICACHE_ReadReg function + * @{ + */ +#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */ +#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */ +#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_ICACHE_WriteReg function + * @{ + */ +#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */ +#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions + * @{ + */ +#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ +#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Region Remapped Region number + * @{ + */ +#define LL_ICACHE_REGION_0 0U /*!< Region 0 */ +#define LL_ICACHE_REGION_1 1U /*!< Region 1 */ +#define LL_ICACHE_REGION_2 2U /*!< Region 2 */ +#define LL_ICACHE_REGION_3 3U /*!< Region 3 */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size + * @{ + */ +#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ +#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ +#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ +#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ +#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ +#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ +#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route + * @{ + */ +#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */ +#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ +/** + * @} + */ + +/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type + * @{ + */ +#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ +#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros ----------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros + * @{ + */ + +/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ICACHE register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ICACHE register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions + * @{ + */ + +/** @defgroup ICACHE_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable the ICACHE. + * @rmtoll CR EN LL_ICACHE_Enable + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Enable(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_EN); +} + +/** + * @brief Disable the ICACHE. + * @rmtoll CR EN LL_ICACHE_Disable + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Disable(void) +{ + CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); +} + +/** + * @brief Return if ICACHE is enabled or not. + * @rmtoll CR EN LL_ICACHE_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void) +{ + return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Select the ICACHE operating mode. + * @rmtoll CR WAYSEL LL_ICACHE_SetMode + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_ICACHE_1WAY + * @arg @ref LL_ICACHE_2WAYS + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode) +{ + MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode); +} + +/** + * @brief Get the selected ICACHE operating mode. + * @rmtoll CR WAYSEL LL_ICACHE_GetMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_1WAY + * @arg @ref LL_ICACHE_2WAYS + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void) +{ + return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL)); +} + +/** + * @brief Invalidate the ICACHE. + * @note Until the BSYEND flag is set, the cache is bypassed. + * @rmtoll CR CACHEINV LL_ICACHE_Invalidate + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_Invalidate(void) +{ + SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_Monitors Monitors + * @{ + */ + +/** + * @brief Enable the hit/miss monitor(s). + * @rmtoll CR HITMEN LL_ICACHE_EnableMonitors\n + * @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors) +{ + SET_BIT(ICACHE->CR, Monitors); +} + +/** + * @brief Disable the hit/miss monitor(s). + * @rmtoll CR HITMEN LL_ICACHE_DisableMonitors\n + * @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors) +{ + CLEAR_BIT(ICACHE->CR, Monitors); +} + +/** + * @brief Check if the monitor(s) is(are) enabled or disabled. + * @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors\n + * @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval State of parameter value (1 or 0). + * @retval None + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors) +{ + return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL); +} + +/** + * @brief Reset the hit/miss monitor(s). + * @rmtoll CR HITMRST LL_ICACHE_ResetMonitors\n + * @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors + * @param Monitors This parameter can be one or a combination of the following values: + * @arg @ref LL_ICACHE_MONITOR_HIT + * @arg @ref LL_ICACHE_MONITOR_MISS + * @arg @ref LL_ICACHE_MONITOR_ALL + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors) +{ + /* Reset */ + SET_BIT(ICACHE->CR, (Monitors << 2U)); + /* Release reset */ + CLEAR_BIT(ICACHE->CR, (Monitors << 2U)); +} + +/** + * @brief Get the Hit monitor. + * @note Upon reaching the 32-bit maximum value, hit monitor does not wrap. + * @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void) +{ + return (ICACHE->HMONR); +} + +/** + * @brief Get the Miss monitor. + * @note Upon reaching the 16-bit maximum value, miss monitor does not wrap. + * @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor + * @retval Value between Min_Data=0 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void) +{ + return (ICACHE->MMONR); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable BSYEND interrupt. + * @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void) +{ + SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); +} + +/** + * @brief Disable BSYEND interrupt. + * @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void) +{ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); +} + +/** + * @brief Check if the BSYEND Interrupt is enabled or disabled. + * @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void) +{ + return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable ERR interrupt. + * @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void) +{ + SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE); +} + +/** + * @brief Disable ERR interrupt. + * @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void) +{ + CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); +} + +/** + * @brief Check if the ERR Interrupt is enabled or disabled. + * @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void) +{ + return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Indicate the status of an ongoing operation flag. + * @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of an operation end flag. + * @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of an error flag. + * @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void) +{ + return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL); +} + +/** + * @brief Clear busy end of operation flag. + * @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void) +{ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); +} + +/** + * @brief Clear error flag. + * @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void) +{ + WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); +} + +/** + * @} + */ + +/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management + * @{ + */ + +/** + * @brief Enable the remapped memory region. + * @note The region must have been already configured. + * @rmtoll CRRx REN LL_ICACHE_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region) +{ + SET_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REN); +} + +/** + * @brief Disable the remapped memory region. + * @rmtoll CRRx REN LL_ICACHE_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region) +{ + CLEAR_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REN); +} + +/** + * @brief Return if remapped memory region is enabled or not. + * @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region) +{ + return ((READ_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL); +} + +/** + * @brief Select the memory remapped region base address. + * @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Address Alias address in the Code region + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address) +{ + MODIFY_REG(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_BASEADDR, (((Address & 0x1FFFFFFFU) >> 21U) & ICACHE_CRRx_BASEADDR)); +} + +/** + * @brief Get the memory remapped region base address. + * @note The base address is the alias in the Code region. + * @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Address Alias address in the Code region + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region) +{ + return (READ_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_BASEADDR)); +} + +/** + * @brief Select the memory remapped region remap address. + * @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Address External memory address + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address) +{ + MODIFY_REG(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos)); +} + +/** + * @brief Get the memory remapped region base address. + * @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Address External memory address + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region) +{ + return ((READ_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U); +} + +/** + * @brief Select the memory remapped region size. + * @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGIONSIZE_2MB + * @arg @ref LL_ICACHE_REGIONSIZE_4MB + * @arg @ref LL_ICACHE_REGIONSIZE_8MB + * @arg @ref LL_ICACHE_REGIONSIZE_16MB + * @arg @ref LL_ICACHE_REGIONSIZE_32MB + * @arg @ref LL_ICACHE_REGIONSIZE_64MB + * @arg @ref LL_ICACHE_REGIONSIZE_128MB + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size) +{ + MODIFY_REG(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos)); +} + +/** + * @brief Get the selected the memory remapped region size. + * @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_REGIONSIZE_2MB + * @arg @ref LL_ICACHE_REGIONSIZE_4MB + * @arg @ref LL_ICACHE_REGIONSIZE_8MB + * @arg @ref LL_ICACHE_REGIONSIZE_16MB + * @arg @ref LL_ICACHE_REGIONSIZE_32MB + * @arg @ref LL_ICACHE_REGIONSIZE_64MB + * @arg @ref LL_ICACHE_REGIONSIZE_128MB + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region) +{ + return (READ_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos); +} + +/** + * @brief Select the memory remapped region output burst type. + * @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Type This parameter can be one of the following values: + * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP + * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type) +{ + MODIFY_REG(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_HBURST, Type); +} + +/** + * @brief Get the selected the memory remapped region output burst type. + * @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP + * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region) +{ + return (READ_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_HBURST)); +} + +/** + * @brief Select the memory remapped region cache master port. + * @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @param Port This parameter can be one of the following values: + * @arg @ref LL_ICACHE_MASTER1_PORT + * @arg @ref LL_ICACHE_MASTER2_PORT + * @retval None + */ +__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port) +{ + MODIFY_REG(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_MSTSEL, Port); +} + +/** + * @brief Get the selected the memory remapped region cache master port. + * @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort + * @param Region This parameter can be one of the following values: + * @arg @ref LL_ICACHE_REGION_0 + * @arg @ref LL_ICACHE_REGION_1 + * @arg @ref LL_ICACHE_REGION_2 + * @arg @ref LL_ICACHE_REGION_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ICACHE_MASTER1_PORT + * @arg @ref LL_ICACHE_MASTER2_PORT + */ +__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region) +{ + return (READ_BIT(*((volatile uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ + ICACHE_CRRx_MSTSEL)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions + * @{ + */ + +void LL_ICACHE_ConfigRegion(uint32_t Region, LL_ICACHE_RegionTypeDef *ICACHE_RegionStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ICACHE */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L5xx_LL_ICACHE_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_iwdg.h index fa62fbfe81..13baa969b1 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_iwdg.h @@ -304,8 +304,8 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) /** * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not * @rmtoll SR PVU LL_IWDG_IsReady\n - * SR WVU LL_IWDG_IsReady\n - * SR RVU LL_IWDG_IsReady + * SR RVU LL_IWDG_IsReady\n + * SR WVU LL_IWDG_IsReady * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ @@ -318,7 +318,6 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) * @} */ - /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_lptim.c index c6c00f2d0f..e85c8c96b2 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_lptim.c @@ -48,22 +48,22 @@ * @{ */ #define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ - || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) + || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) #define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ + || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) #define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) + || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) #define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) + || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) /** * @} */ @@ -266,8 +266,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } - while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_CMPOK(LPTIMx); } @@ -298,8 +297,7 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) do { rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } - while (((LL_LPTIM_IsActiveFlag_REPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); + } while (((LL_LPTIM_IsActiveFlag_REPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); LL_LPTIM_ClearFlag_REPOK(LPTIMx); } diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_opamp.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_opamp.h index 5545388224..9b70a49734 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_opamp.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_opamp.h @@ -153,8 +153,11 @@ typedef struct /** @defgroup OPAMP_LL_EC_POWERMODE OPAMP power mode * @{ */ -#define LL_OPAMP_POWERMODE_NORMAL (OPAMP_POWERMODE_OTR_REGOFFSET) /*!< OPAMP power mode normal */ +#define LL_OPAMP_POWERMODE_NORMALPOWER (OPAMP_POWERMODE_OTR_REGOFFSET) /*!< OPAMP power mode normal */ #define LL_OPAMP_POWERMODE_LOWPOWER (OPAMP_POWERMODE_LPOTR_REGOFFSET | OPAMP_CSR_OPALPM) /*!< OPAMP power mode low-power */ + +#define LL_OPAMP_POWERMODE_NORMAL LL_OPAMP_POWERMODE_NORMALPOWER /*!< OPAMP power mode normal - Old Naming for compatibility */ + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rcc.c index 1fc09903e2..6742a14e39 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rcc.c @@ -24,7 +24,8 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ + /** @addtogroup STM32L5xx_LL_Driver * @{ */ @@ -43,25 +44,25 @@ * @{ */ #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE)) #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)) + || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE)) #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)) #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)) + || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)) #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_LPTIM3_CLKSOURCE)) + || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_LPTIM3_CLKSOURCE)) #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE)) + || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE)) #define IS_LL_RCC_SDMMC_KERNELCLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_KERNELCLKSOURCE)) @@ -89,17 +90,17 @@ /** @defgroup RCC_LL_Private_Functions RCC Private Functions * @{ */ -uint32_t RCC_GetSystemClockFreq(void); -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); -uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); -uint32_t RCC_PLL_GetFreqDomain_SYS(void); -uint32_t RCC_PLL_GetFreqDomain_SAI(void); -uint32_t RCC_PLL_GetFreqDomain_48M(void); -uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void); -uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void); -uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void); -uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void); +static uint32_t RCC_GetSystemClockFreq(void); +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); +static uint32_t RCC_PLL_GetFreqDomain_SYS(void); +static uint32_t RCC_PLL_GetFreqDomain_SAI(void); +static uint32_t RCC_PLL_GetFreqDomain_48M(void); +static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void); +static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void); +static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void); +static uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void); /** * @} */ @@ -1284,7 +1285,7 @@ uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource) * @brief Return SYSTEM clock frequency * @retval SYSTEM clock frequency (in Hz) */ -uint32_t RCC_GetSystemClockFreq(void) +static uint32_t RCC_GetSystemClockFreq(void) { uint32_t frequency; @@ -1326,7 +1327,7 @@ uint32_t RCC_GetSystemClockFreq(void) * @param SYSCLK_Frequency SYSCLK clock frequency * @retval HCLK clock frequency (in Hz) */ -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) { /* HCLK clock frequency */ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); @@ -1337,7 +1338,7 @@ uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) * @param HCLK_Frequency HCLK clock frequency * @retval PCLK1 clock frequency (in Hz) */ -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) { /* PCLK1 clock frequency */ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); @@ -1348,7 +1349,7 @@ uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) * @param HCLK_Frequency HCLK clock frequency * @retval PCLK2 clock frequency (in Hz) */ -uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) +static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) { /* PCLK2 clock frequency */ return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); @@ -1358,7 +1359,7 @@ uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) * @brief Return PLL clock frequency used for system domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_SYS(void) +static uint32_t RCC_PLL_GetFreqDomain_SYS(void) { uint32_t pllinputfreq, pllsource; @@ -1398,7 +1399,7 @@ uint32_t RCC_PLL_GetFreqDomain_SYS(void) * @brief Return PLL clock frequency used for SAI domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_SAI(void) +static uint32_t RCC_PLL_GetFreqDomain_SAI(void) { uint32_t pllinputfreq, plloutputfreq, pllsource; uint32_t plln, pllpdiv; @@ -1451,7 +1452,7 @@ uint32_t RCC_PLL_GetFreqDomain_SAI(void) * @brief Return PLL clock frequency used for 48 MHz domain * @retval PLL clock frequency (in Hz) */ -uint32_t RCC_PLL_GetFreqDomain_48M(void) +static uint32_t RCC_PLL_GetFreqDomain_48M(void) { uint32_t pllinputfreq, pllsource; @@ -1492,7 +1493,7 @@ uint32_t RCC_PLL_GetFreqDomain_48M(void) * @brief Return PLLSAI1 clock frequency used for SAI domain * @retval PLLSAI1 clock frequency (in Hz) */ -uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) +static uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) { uint32_t pllinputfreq, plloutputfreq, pllsource; uint32_t plln, pllpdiv; @@ -1544,7 +1545,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_SAI(void) * @brief Return PLLSAI1 clock frequency used for 48Mhz domain * @retval PLLSAI1 clock frequency (in Hz) */ -uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) +static uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) { uint32_t pllinputfreq, pllsource; @@ -1584,7 +1585,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_48M(void) * @brief Return PLLSAI1 clock frequency used for ADC domain * @retval PLLSAI1 clock frequency (in Hz) */ -uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) +static uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) { uint32_t pllinputfreq, pllsource; @@ -1624,7 +1625,7 @@ uint32_t RCC_PLLSAI1_GetFreqDomain_ADC(void) * @brief Return PLLSAI2 clock frequency used for SAI domain * @retval PLLSAI2 clock frequency (in Hz) */ -uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) +static uint32_t RCC_PLLSAI2_GetFreqDomain_SAI(void) { uint32_t pllinputfreq, plloutputfreq, pllsource; uint32_t plln, pllpdiv; diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rcc.h index 2963597c98..c9ccc6357f 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rcc.h @@ -1056,8 +1056,9 @@ typedef struct * @arg @ref LL_RCC_PLLR_DIV_8 * @retval PLL clock frequency (in Hz) */ -#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ - ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U)) +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) \ + ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ + ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U)) /** * @brief Helper macro to calculate the PLLCLK frequency used on SAI domain @@ -1115,8 +1116,9 @@ typedef struct * @arg @ref LL_RCC_PLLP_DIV_31 * @retval PLL clock frequency (in Hz) */ -#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ - ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos)) +#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) \ + ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ + ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos)) /** * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain @@ -1148,8 +1150,9 @@ typedef struct * @arg @ref LL_RCC_PLLQ_DIV_8 * @retval PLL clock frequency (in Hz) */ -#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ - ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)) +#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) \ + ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \ + ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U)) /** * @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain @@ -1208,8 +1211,8 @@ typedef struct * @retval PLLSAI1 clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \ - ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ - ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) + ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos)) /** * @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain @@ -1242,8 +1245,8 @@ typedef struct * @retval PLLSAI1 clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \ - ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ - ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)) + ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U)) /** * @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain @@ -1276,8 +1279,8 @@ typedef struct * @retval PLLSAI1 clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \ - ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ - ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) + ((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \ + ((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U)) /** * @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain @@ -1336,8 +1339,8 @@ typedef struct * @retval PLLSAI2 clock frequency (in Hz) */ #define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \ - ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ - ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) + ((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \ + ((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos)) /** * @brief Helper macro to calculate the HCLK frequency @@ -1354,7 +1357,8 @@ typedef struct * @arg @ref LL_RCC_SYSCLK_DIV_512 * @retval HCLK clock frequency (in Hz) */ -#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) \ + ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) /** * @brief Helper macro to calculate the PCLK1 frequency (ABP1) @@ -1414,9 +1418,10 @@ typedef struct * @arg @ref LL_RCC_MSISRANGE_7 * @retval MSI clock frequency (in Hz) */ -#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \ - MSIRangeTable[((__MSIRANGE__) >> RCC_CSR_MSISRANGE_Pos) & 0x0FU] : \ - MSIRangeTable[((__MSIRANGE__) >> RCC_CR_MSIRANGE_Pos) & 0x0FU]) +#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) \ + (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \ + MSIRangeTable[((__MSIRANGE__) >> RCC_CSR_MSISRANGE_Pos) & 0x0FU] : \ + MSIRangeTable[((__MSIRANGE__) >> RCC_CR_MSIRANGE_Pos) & 0x0FU]) /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rng.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rng.c index a9b9739316..193a736188 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rng.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rng.c @@ -42,7 +42,7 @@ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ -/** @addtogroup RNG_LL_Private_Macros +/** @defgroup RNG_LL_Private_Macros RNG Private Macros * @{ */ #define IS_LL_RNG_CED(__MODE__) (((__MODE__) == LL_RNG_CED_ENABLE) || \ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rtc.h index 4557e3062f..affb447096 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_rtc.h @@ -5327,6 +5327,79 @@ __STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(RTC_TypeDef *RTCx) return READ_REG(TAMP->COUNTR); } +/** + * @brief Enable Temperature Monitoring. + * @rmtoll TAMP_CFGR TMONEN LL_RTC_EnableTemperatureMonitoring + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableTemperatureMonitoring(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CFGR, TAMP_CFGR_TMONEN); +} + +/** + * @brief Disable Temperature Monitoring. + * @rmtoll TAMP_CFGR TMONEN LL_RTC_DisableTemperatureMonitoring + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableTemperatureMonitoring(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_TMONEN); +} + +/** + * @brief Enable Voltage Monitoring. + * @rmtoll TAMP_CFGR VMONEN LL_RTC_EnableVoltageMonitoring + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableVoltageMonitoring(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CFGR, TAMP_CFGR_VMONEN); +} + +/** + * @brief Disable Voltage Monitoring. + * @rmtoll TAMP_CFGR VMONEN LL_RTC_DisableVoltageMonitoring + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableVoltageMonitoring(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_VMONEN); +} + +/** + * @brief Enable WUT Monitoring. + * @rmtoll TAMP_CFGR WUTMONEN LL_RTC_EnableWUTMonitoring + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableWUTMonitoring(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + SET_BIT(TAMP->CFGR, TAMP_CFGR_WUTMONEN); +} + +/** + * @brief Disable WUT Monitoring. + * @rmtoll TAMP_CFGR WUTMONEN LL_RTC_DisableWUTMonitoring + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableWUTMonitoring(RTC_TypeDef *RTCx) +{ + UNUSED(RTCx); + CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_WUTMONEN); +} + + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_sdmmc.c index 7975f9199a..afd32fde66 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_sdmmc.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_sdmmc.c @@ -178,8 +178,8 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx); */ /** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization/de-initialization functions ##### @@ -210,12 +210,12 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv)); /* Set SDMMC configuration parameters */ - tmpreg |= (Init.ClockEdge |\ - Init.ClockPowerSave |\ - Init.BusWide |\ - Init.HardwareFlowControl |\ + tmpreg |= (Init.ClockEdge | \ + Init.ClockPowerSave | \ + Init.BusWide | \ + Init.HardwareFlowControl | \ Init.ClockDiv - ); + ); /* Write to SDMMC CLKCR */ MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); @@ -229,8 +229,8 @@ HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) */ /** @defgroup HAL_SDMMC_LL_Group2 IO operation functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### I/O operation functions ##### @@ -273,8 +273,8 @@ HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) */ /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions - * @brief management functions - * + * @brief management functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -362,9 +362,9 @@ HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef SDMMCx->ARG = Command->Argument; /* Set SDMMC command parameters */ - tmpreg |= (uint32_t)(Command->CmdIndex |\ - Command->Response |\ - Command->WaitForInterrupt |\ + tmpreg |= (uint32_t)(Command->CmdIndex | \ + Command->Response | \ + Command->WaitForInterrupt | \ Command->CPSM); /* Write to SDMMC CMD register */ @@ -416,7 +416,7 @@ uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) * that contains the configuration information for the SDMMC data. * @retval HAL status */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data) +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data) { uint32_t tmpreg = 0; @@ -434,9 +434,9 @@ HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* SDMMCx->DLEN = Data->DataLength; /* Set the SDMMC data configuration parameters */ - tmpreg |= (uint32_t)(Data->DataBlockSize |\ - Data->TransferDir |\ - Data->TransferMode |\ + tmpreg |= (uint32_t)(Data->DataBlockSize | \ + Data->TransferDir | \ + Data->TransferMode | \ Data->DPSM); /* Write to SDMMC DCTRL */ @@ -492,8 +492,8 @@ HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDM /** @defgroup HAL_SDMMC_LL_Group4 Command management functions - * @brief Data transfers functions - * + * @brief Data transfers functions + * @verbatim =============================================================================== ##### Commands management functions ##### @@ -788,7 +788,7 @@ uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) * @param addr: Address of the card to be selected * @retval HAL status */ -uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) +uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr) { SDMMC_CmdInitTypeDef sdmmc_cmdinit; uint32_t errorstate; @@ -1201,7 +1201,7 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT); + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD, SDMMC_CMDTIMEOUT); return errorstate; } @@ -1212,8 +1212,8 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) /** @defgroup HAL_SDMMC_LL_Group5 Responses management functions - * @brief Responses functions - * + * @brief Responses functions + * @verbatim =============================================================================== ##### Responses management functions ##### @@ -1237,7 +1237,7 @@ uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeo /* 8 is the number of required instructions cycles for the below loop statement. The Timeout is expressed in ms */ - uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); + uint32_t count = Timeout * (SystemCoreClock / 8U / 1000U); do { @@ -1246,16 +1246,16 @@ uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeo return SDMMC_ERROR_TIMEOUT; } sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_BUSYD0END)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT | + SDMMC_FLAG_BUSYD0END)) == 0U) || ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); return SDMMC_ERROR_CMD_RSP_TIMEOUT; } - else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); @@ -1270,7 +1270,7 @@ uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeo __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); /* Check response received is of desired command */ - if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) + if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) { return SDMMC_ERROR_CMD_CRC_FAIL; } @@ -1278,79 +1278,79 @@ uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeo /* We have received response, retrieve it for analysis */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); - if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) + if ((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) { return SDMMC_ERROR_NONE; } - else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) + else if ((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) { return SDMMC_ERROR_ADDR_OUT_OF_RANGE; } - else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) + else if ((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) { return SDMMC_ERROR_ADDR_MISALIGNED; } - else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) + else if ((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) { return SDMMC_ERROR_BLOCK_LEN_ERR; } - else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) + else if ((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) { return SDMMC_ERROR_ERASE_SEQ_ERR; } - else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) + else if ((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) { return SDMMC_ERROR_BAD_ERASE_PARAM; } - else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) + else if ((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) { return SDMMC_ERROR_WRITE_PROT_VIOLATION; } - else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) + else if ((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) { return SDMMC_ERROR_LOCK_UNLOCK_FAILED; } - else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) + else if ((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) { return SDMMC_ERROR_COM_CRC_FAILED; } - else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) + else if ((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) { return SDMMC_ERROR_ILLEGAL_CMD; } - else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) + else if ((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) { return SDMMC_ERROR_CARD_ECC_FAILED; } - else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) + else if ((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) { return SDMMC_ERROR_CC_ERR; } - else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) + else if ((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) { return SDMMC_ERROR_STREAM_READ_UNDERRUN; } - else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) + else if ((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) { return SDMMC_ERROR_STREAM_WRITE_OVERRUN; } - else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) + else if ((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) { return SDMMC_ERROR_CID_CSD_OVERWRITE; } - else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) + else if ((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) { return SDMMC_ERROR_WP_ERASE_SKIP; } - else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) + else if ((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) { return SDMMC_ERROR_CARD_ECC_DISABLED; } - else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) + else if ((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) { return SDMMC_ERROR_ERASE_RESET; } - else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) + else if ((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) { return SDMMC_ERROR_AKE_SEQ_ERR; } @@ -1370,7 +1370,7 @@ uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); do { @@ -1379,8 +1379,8 @@ uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_TIMEOUT; } sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { @@ -1414,7 +1414,7 @@ uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); do { @@ -1423,10 +1423,10 @@ uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_TIMEOUT; } sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); @@ -1456,7 +1456,7 @@ uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); do { @@ -1465,16 +1465,16 @@ uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA return SDMMC_ERROR_TIMEOUT; } sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); return SDMMC_ERROR_CMD_RSP_TIMEOUT; } - else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) { __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); @@ -1486,7 +1486,7 @@ uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA } /* Check response received is of desired command */ - if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) + if (SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) { return SDMMC_ERROR_CMD_CRC_FAIL; } @@ -1497,17 +1497,18 @@ uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA /* We have received response, retrieve it. */ response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); - if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) + if ((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | + SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) { - *pRCA = (uint16_t) (response_r1 >> 16); + *pRCA = (uint16_t)(response_r1 >> 16); return SDMMC_ERROR_NONE; } - else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) + else if ((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) { return SDMMC_ERROR_ILLEGAL_CMD; } - else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) + else if ((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) { return SDMMC_ERROR_COM_CRC_FAILED; } @@ -1527,7 +1528,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); do { @@ -1536,10 +1537,10 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_TIMEOUT; } sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) { /* Card is SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); @@ -1547,7 +1548,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_CMD_RSP_TIMEOUT; } - else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) { /* Card is SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); @@ -1559,7 +1560,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) /* Nothing to do */ } - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) { /* Card is SD V2.0 compliant */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); @@ -1587,7 +1588,7 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) { /* 8 is the number of required instructions cycles for the below loop statement. The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); do { @@ -1596,7 +1597,7 @@ static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_TIMEOUT; } - }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); + } while (!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); /* Clear all the static flags */ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_sdmmc.h index f2b50bf7ef..f9c246ff29 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_sdmmc.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_sdmmc.h @@ -22,7 +22,7 @@ #define STM32L5xx_LL_SDMMC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -66,7 +66,7 @@ typedef struct uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher. This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */ #endif /* USE_SD_TRANSCEIVER */ -}SDMMC_InitTypeDef; +} SDMMC_InitTypeDef; /** @@ -92,7 +92,7 @@ typedef struct uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) is enabled or disabled. This parameter can be a value of @ref SDMMC_LL_CPSM_State */ -}SDMMC_CmdInitTypeDef; +} SDMMC_CmdInitTypeDef; /** @@ -117,7 +117,7 @@ typedef struct uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) is enabled or disabled. This parameter can be a value of @ref SDMMC_LL_DPSM_State */ -}SDMMC_DataInitTypeDef; +} SDMMC_DataInitTypeDef; /** * @} @@ -135,13 +135,13 @@ typedef struct #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ -#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the - number of transferred bytes does not match the block length */ +#define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the */ + /*!< number of transferred bytes does not match the block length */ #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ -#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock - command or if there was an attempt to access a locked card */ +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock */ + /*!< command or if there was an attempt to access a locked card */ #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ @@ -152,8 +152,8 @@ typedef struct #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ -#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out - of erase sequence command was received */ +#define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out */ + /*!< of erase sequence command was received */ #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ @@ -172,12 +172,12 @@ typedef struct #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ -#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its - operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its */ + /*!< operating condition register (OCR) content in the response on the CMD line. */ #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information - and asks the card whether card supports voltage. */ +#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information */ + /*!< and asks the card whether card supports voltage. */ #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ @@ -185,18 +185,18 @@ typedef struct #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ -#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands - (read, write, lock). Default block length is fixed to 512 Bytes. Not effective - for SDHS and SDXC. */ -#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by - STOP_TRANSMISSION command. */ +#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands */ + /*!< (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ +/*!< for SDHS and SDXC. */ +#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of */ + /*!< fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by */ + /*!< STOP_TRANSMISSION command. */ #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ -#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of */ + /*!< fixed 512 bytes in case of SDHC and SDXC. */ #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ @@ -205,32 +205,32 @@ typedef struct #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command - system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. - Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command */ + /*!< system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. */ + /*!< Reserved for each command system set by switch function command (CMD6). */ #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by - the SET_BLOCK_LEN command. */ -#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather - than a standard command. */ -#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card - for general purpose/application specific commands. */ +#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by */ + /*!< the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather */ + /*!< than a standard command. */ +#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card */ + /*!< for general purpose/application specific commands. */ #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ /** * @brief Following commands are SD Card Specific commands. * SDMMC_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus - widths are given in SCR register. */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus */ + /*!< widths are given in SCR register. */ #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ -#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with - 32bit+CRC data block. */ -#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to - send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with */ + /*!< 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to */ + /*!< send its operating condition register (OCR) content in the response on the CMD line. */ #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ @@ -503,14 +503,18 @@ typedef struct #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) -#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) +#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0| \ + SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) -#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0| \ + SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) -#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) -#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0| \ + SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1| \ + SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ @@ -642,21 +646,21 @@ typedef struct #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC -#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ - SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ - SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ - SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ - SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ - SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ - SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) +#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ + SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ + SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ + SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ + SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ + SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) -#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ - SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) +#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ + SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) -#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ - SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ - SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ - SDMMC_FLAG_IDMABTC)) +#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ + SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ + SDMMC_FLAG_IDMABTC)) /** * @} */ @@ -707,9 +711,9 @@ typedef struct */ /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ /** * @brief Enable the SDMMC device interrupt. @@ -1034,7 +1038,7 @@ uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); /* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); @@ -1059,7 +1063,7 @@ uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx, uint32_t EraseType); uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr); +uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint32_t Addr); uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); @@ -1106,7 +1110,7 @@ uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); * @} */ - /** +/** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_spi.c index eb406a5bbd..00f11245c5 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_spi.c @@ -232,6 +232,12 @@ ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) SPI_CR2_DS | SPI_CR2_SSOE, SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U)); + /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */ + if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT) + { + LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER); + } + /*---------------------------- SPIx CRCPR Configuration ---------------------- * Configure SPIx CRCPR with parameters: * - CRCPoly: CRCPOLY[15:0] bits diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_system.h index 0cfec05de1..18f9456bde 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_system.h @@ -59,16 +59,16 @@ extern "C" { * @{ */ /** - * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values - */ + * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values + */ #define VREFBUF_SC0_CAL_ADDR ((uint8_t*) (0x0BFA0579UL)) /*!< Address of VREFBUF trimming value for VRS=0, VREF_SC0 in STM32L5 datasheet */ #define VREFBUF_SC1_CAL_ADDR ((uint8_t*) (0x0BFA0530UL)) /*!< Address of VREFBUF trimming value for VRS=1, VREF_SC1 in STM32L5 datasheet */ /** - * @brief Power-down in Run mode Flash key - */ + * @brief Power-down in Run mode Flash key + */ #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */ #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1 to unlock the RUN_PD bit in FLASH_ACR */ diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_tim.h index d6b3466aba..f3e3a7af97 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_tim.h @@ -601,8 +601,8 @@ typedef struct /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode * @{ */ -#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ -#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ /** * @} */ @@ -1545,7 +1545,16 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo */ __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) { - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; } /** @@ -2000,8 +2009,8 @@ __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); @@ -2045,8 +2054,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } @@ -2084,8 +2093,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint */ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } @@ -2118,7 +2127,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); } @@ -2150,7 +2159,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -2187,7 +2196,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Chann */ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); } @@ -2219,7 +2228,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); } @@ -2244,8 +2253,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2270,8 +2279,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); } @@ -2296,9 +2305,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2322,8 +2331,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Cha */ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2347,8 +2356,8 @@ __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); } @@ -2372,9 +2381,9 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2401,8 +2410,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t */ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2428,8 +2437,8 @@ __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); } @@ -2457,9 +2466,9 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) */ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); } @@ -2728,8 +2737,8 @@ __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t G */ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), @@ -2756,8 +2765,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 */ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2780,8 +2789,8 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe */ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2806,8 +2815,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Ch */ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2831,8 +2840,8 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2869,8 +2878,8 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Chan */ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); } @@ -2906,8 +2915,8 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui */ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); } @@ -2935,7 +2944,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel */ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), ICPolarity << SHIFT_TAB_CCxP[iChannel]); } @@ -2963,7 +2972,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, */ __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) { - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); } @@ -3356,7 +3365,6 @@ __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, u */ __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) { - MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource); } @@ -3696,7 +3704,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) */ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); SET_BIT(*pReg, Source); } @@ -3725,7 +3733,7 @@ __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t B */ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) { - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); CLEAR_BIT(*pReg, Source); } @@ -3755,7 +3763,7 @@ __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, uint32_t Polarity) { - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); } /** diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_usart.c index 36001d3e65..14c09d138a 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_usart.c @@ -66,9 +66,6 @@ /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) -/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ -#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) - #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ || ((__VALUE__) == LL_USART_DIRECTION_RX) \ || ((__VALUE__) == LL_USART_DIRECTION_TX) \ @@ -290,9 +287,6 @@ ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_Ini /* Check BRR is greater than or equal to 16d */ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); - - /* Check BRR is lower than or equal to 0xFFFF */ - assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); } /*---------------------------- USART PRESC Configuration ----------------------- @@ -352,37 +346,25 @@ ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef CRx registers */ if (LL_USART_IsEnabled(USARTx) == 0U) { - /*---------------------------- USART CR2 Configuration -----------------------*/ - /* If Clock signal has to be output */ - if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) - { - /* Deactivate Clock signal delivery : - * - Disable Clock Output: USART_CR2_CLKEN cleared - */ - LL_USART_DisableSCLKOutput(USARTx); - } - else - { - /* Ensure USART instance is USART capable */ - assert_param(IS_USART_INSTANCE(USARTx)); + /* Ensure USART instance is USART capable */ + assert_param(IS_USART_INSTANCE(USARTx)); - /* Check clock related parameters */ - assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); - assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); - assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); + /* Check clock related parameters */ + assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); + assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); + assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); - /*---------------------------- USART CR2 Configuration ----------------------- - * Configure USARTx CR2 (Clock signal related bits) with parameters: - * - Enable Clock Output: USART_CR2_CLKEN set - * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value - * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value - * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. - */ - MODIFY_REG(USARTx->CR2, - USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, - USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | - USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); - } + /*---------------------------- USART CR2 Configuration ----------------------- + * Configure USARTx CR2 (Clock signal related bits) with parameters: + * - Clock Output: USART_CR2_CLKEN bit according to USART_ClockInitStruct->ClockOutput value + * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value + * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value + * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. + */ + MODIFY_REG(USARTx->CR2, + USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, + USART_ClockInitStruct->ClockOutput | USART_ClockInitStruct->ClockPolarity | + USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); } /* Else (USART not in Disabled state => return ERROR */ else diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_usb.c index c6a748f73a..34e33d2048 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_usb.c @@ -56,8 +56,8 @@ /** * @brief Initializes the USB Core - * @param USBx: USB Instance - * @param cfg : pointer to a USB_CfgTypeDef structure that contains + * @param USBx USB Instance + * @param cfg pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -78,7 +78,7 @@ HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) /** * @brief USB_EnableGlobalInt * Enables the controller's Global Int in the AHB Config reg - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) @@ -103,7 +103,7 @@ HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx) /** * @brief USB_DisableGlobalInt * Disable the controller's Global Int in the AHB Config reg - * @param USBx : Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) @@ -123,11 +123,11 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) } /** - * @brief USB_SetCurrentMode : Set functional mode - * @param USBx : Selected device - * @param mode : current core mode + * @brief USB_SetCurrentMode Set functional mode + * @param USBx Selected device + * @param mode current core mode * This parameter can be one of the these values: - * @arg USB_DEVICE_MODE: Peripheral mode + * @arg USB_DEVICE_MODE Peripheral mode * @retval HAL status */ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) @@ -144,10 +144,10 @@ HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) } /** - * @brief USB_DevInit : Initializes the USB controller registers + * @brief USB_DevInit Initializes the USB controller registers * for device mode - * @param USBx : Selected device - * @param cfg : pointer to a USB_CfgTypeDef structure that contains + * @param USBx Selected device + * @param cfg pointer to a USB_CfgTypeDef structure that contains * the configuration information for the specified USBx peripheral. * @retval HAL status */ @@ -157,13 +157,13 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) UNUSED(cfg); /* Init Device */ - /*CNTR_FRES = 1*/ + /* CNTR_FRES = 1 */ USBx->CNTR = (uint16_t)USB_CNTR_FRES; - /*CNTR_FRES = 0*/ + /* CNTR_FRES = 0 */ USBx->CNTR = 0U; - /*Clear pending interrupts*/ + /* Clear pending interrupts */ USBx->ISTR = 0U; /*Set Btable Address*/ @@ -172,71 +172,11 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) return HAL_OK; } -/** - * @brief USB_SetDevSpeed :Initializes the device speed - * depending on the PHY type and the enumeration speed of the device. - * @param USBx Selected device - * @param speed device speed - * @retval Hal status - */ -HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(speed); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - return HAL_OK; -} - -/** - * @brief USB_FlushTxFifo : Flush a Tx FIFO - * @param USBx : Selected device - * @param num : FIFO number - * This parameter can be a value from 1 to 15 - 15 means Flush all Tx FIFOs - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(num); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - return HAL_OK; -} - -/** - * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - return HAL_OK; -} - +#if defined (HAL_PCD_MODULE_ENABLED) /** * @brief Activate and configure an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) @@ -297,9 +237,11 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { /*Set the endpoint Receive buffer address */ PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); + /*Set the endpoint Receive buffer counter*/ PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); PCD_CLEAR_RX_DTOG(USBx, ep->num); + /* Configure VALID status for the Endpoint*/ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); } @@ -309,6 +251,7 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) { /* Set the endpoint as double buffered */ PCD_SET_EP_DBUF(USBx, ep->num); + /* Set buffer address for double buffered mode */ PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); @@ -327,7 +270,6 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) { /* Configure NAK status for the Endpoint */ @@ -348,8 +290,8 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) /** * @brief De-activate and de-initialize an endpoint - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) @@ -359,12 +301,14 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) if (ep->is_in != 0U) { PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Configure DISABLE status for the Endpoint*/ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } else { PCD_CLEAR_RX_DTOG(USBx, ep->num); + /* Configure DISABLE status for the Endpoint*/ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); } @@ -390,6 +334,7 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); PCD_RX_DTOG(USBx, ep->num); + /* Configure DISABLE status for the Endpoint*/ PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); @@ -400,21 +345,21 @@ HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) } /** - * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @brief USB_EPStartXfer setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - uint16_t pmabuffer; uint32_t len; + uint16_t pmabuffer; uint16_t wEPVal; /* IN endpoint */ if (ep->is_in == 1U) { - /* Multi packet transfer */ + /*Multi packet transfer*/ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -499,10 +444,11 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - /* auto Switch to single buffer mode when transfer xfer_len_db; + /* disable double buffer mode */ PCD_CLEAR_EP_DBUF(USBx, ep->num); @@ -518,21 +464,73 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* manage isochronous double buffer IN mode */ else { - /* Write the data to the USB endpoint */ + /* enable double buffer */ + PCD_SET_EP_DBUF(USBx, ep->num); + + /* each Time to write in PMA xfer_len_db will */ + ep->xfer_len_db -= len; + + /* Fill the data buffer */ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) { /* Set the Double buffer counter for pmabuffer1 */ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + if (len > 0U) + { + /* Set the Double buffer counter for pmabuffer0 */ + PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } } else { /* Set the Double buffer counter for pmabuffer0 */ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); pmabuffer = ep->pmaaddr0; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + ep->xfer_buff += len; + + if (ep->xfer_len_db > ep->maxpacket) + { + ep->xfer_len_db -= len; + } + else + { + len = ep->xfer_len_db; + ep->xfer_len_db = 0U; + } + + if (len > 0U) + { + /* Set the Double buffer counter for pmabuffer1 */ + PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); + pmabuffer = ep->pmaaddr1; + + /* Write the user buffer to USB PMA */ + USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); + } } - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - PCD_FreeUserBuffer(USBx, ep->num, ep->is_in); } } @@ -542,7 +540,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { - /* Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -554,21 +552,22 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) ep->xfer_len = 0U; } /* configure and validate Rx endpoint */ - /*Set RX buffer count*/ PCD_SET_EP_RX_CNT(USBx, ep->num, len); } else { - /*First Transfer Coming From HAL_PCD_EP_Receive & From ISR*/ - /*Set the Double buffer counter*/ + /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */ + /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /*Coming from ISR*/ + + /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state*/ + /* update last value to check if there is blocking state */ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); + /*Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) @@ -577,10 +576,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) } } } - /*iso out double */ + /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -605,54 +604,11 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) return HAL_OK; } -/** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated - * with the EP/channel - * @param USBx : Selected device - * @param src : pointer to source buffer - * @param ch_ep_num : endpoint or host channel number - * @param len : Number of bytes to write - * @retval HAL status - */ -HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(src); - UNUSED(ch_ep_num); - UNUSED(len); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return HAL_OK; -} /** - * @brief USB_ReadPacket : read a packet from the Tx FIFO associated - * with the EP/channel - * @param USBx : Selected device - * @param dest : destination pointer - * @param len : Number of bytes to read - * @retval pointer to destination buffer - */ -void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(dest); - UNUSED(len); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return ((void *)NULL); -} - -/** - * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @brief USB_EPSetStall set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) @@ -670,9 +626,9 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) } /** - * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx : Selected device - * @param ep: pointer to endpoint structure + * @brief USB_EPClearStall Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure * @retval HAL status */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) @@ -693,17 +649,18 @@ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { PCD_CLEAR_RX_DTOG(USBx, ep->num); - /* Configure VALID status for the Endpoint*/ + /* Configure VALID status for the Endpoint */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); } } return HAL_OK; } +#endif /** - * @brief USB_StopDevice : Stop the usb device mode - * @param USBx : Selected device + * @brief USB_StopDevice Stop the usb device mode + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) @@ -721,9 +678,9 @@ HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx) } /** - * @brief USB_SetDevAddress : Stop the usb device mode - * @param USBx : Selected device - * @param address : new device address to be assigned + * @brief USB_SetDevAddress Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned * This parameter can be a value from 0 to 255 * @retval HAL status */ @@ -739,8 +696,8 @@ HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address) } /** - * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down - * @param USBx : Selected device + * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) @@ -752,8 +709,8 @@ HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx) } /** - * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx : Selected device + * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) @@ -765,8 +722,8 @@ HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx) } /** - * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx : Selected device + * @brief USB_ReadInterrupts return the global USB interrupt status + * @param USBx Selected device * @retval HAL status */ uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) @@ -777,114 +734,9 @@ uint32_t USB_ReadInterrupts(USB_TypeDef *USBx) return tmpreg; } -/** - * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return (0); -} - -/** - * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx : Selected device - * @retval HAL status - */ -uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return (0); -} - -/** - * @brief Returns Device OUT EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device OUT EP Interrupt register - */ -uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(epnum); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return (0); -} - -/** - * @brief Returns Device IN EP Interrupt register - * @param USBx : Selected device - * @param epnum : endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device IN EP Interrupt register - */ -uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(epnum); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return (0); -} - -/** - * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx Selected device - * @param interrupt flag - * @retval None - */ -void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(interrupt); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ -} - -/** - * @brief Prepare the EP0 to start the first control setup - * @param USBx Selected device - * @param psetup pointer to setup packet - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(psetup); - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - return HAL_OK; -} - /** * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling - * @param USBx Selected device + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) @@ -895,13 +747,14 @@ HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx) } /** - * @brief USB_DeActivateRemoteWakeup : de-active remote wakeup signalling - * @param USBx Selected device + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) { USBx->CNTR &= (uint16_t)(~USB_CNTR_RESUME); + return HAL_OK; } @@ -910,7 +763,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx) * @param USBx USB peripheral instance register address. * @param pbUsrBuf pointer to user memory area. * @param wPMABufAddr address into PMA. - * @param wNBytes: no. of bytes to be copied. + * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) @@ -941,10 +794,10 @@ void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui /** * @brief Copy data from packet memory area (PMA) to user memory buffer - * @param USBx: USB peripheral instance register address. + * @param USBx USB peripheral instance register address. * @param pbUsrBuf pointer to user memory area. * @param wPMABufAddr address into PMA. - * @param wNBytes: no. of bytes to be copied. + * @param wNBytes no. of bytes to be copied. * @retval None */ void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_usb.h index 208ec14609..5da5131728 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/STM32L5xx_HAL_Driver/stm32l5xx_ll_usb.h @@ -135,10 +135,10 @@ typedef struct /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define EP_MPS_64 0U -#define EP_MPS_32 1U -#define EP_MPS_16 2U -#define EP_MPS_8 3U +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U /** * @} */ @@ -163,10 +163,10 @@ typedef struct * @} */ -#define BTABLE_ADDRESS 0x000U +#define BTABLE_ADDRESS 0x000U #define PMA_ACCESS 1U -#define EP_ADDR_MSK 0x7U +#define EP_ADDR_MSK 0x7U /** * @} */ @@ -187,32 +187,28 @@ HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg); HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(USB_TypeDef *USBx, uint8_t speed); -HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef *USBx, uint32_t num); + +#if defined (HAL_PCD_MODULE_ENABLED) HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep); -HAL_StatusTypeDef USB_WritePacket(USB_TypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len); -void *USB_ReadPacket(USB_TypeDef *USBx, uint8_t *dest, uint16_t len); HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep); +#endif + HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address); HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx); HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(USB_TypeDef *USBx, uint8_t *psetup); uint32_t USB_ReadInterrupts(USB_TypeDef *USBx); -uint32_t USB_ReadDevAllOutEpInterrupt(USB_TypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt(USB_TypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt(USB_TypeDef *USBx, uint8_t epnum); -void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt); - HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx); -void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); -void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); + +void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, + uint16_t wPMABufAddr, uint16_t wNBytes); + +void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, + uint16_t wPMABufAddr, uint16_t wNBytes); /** * @} diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/stm32l5xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/stm32l5xx_hal_conf.h index bad385f5d6..6bdbf667ca 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/stm32l5xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/stm32l5xx_hal_conf.h @@ -24,7 +24,7 @@ #define STM32L5xx_HAL_CONF_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -86,11 +86,11 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */ +#define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -98,7 +98,7 @@ * This value is the default MSI range value after Reset. */ #if !defined (MSI_VALUE) - #define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/ +#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ /** @@ -107,7 +107,7 @@ * (when HSI is used as system clock source, directly or through the PLL). */ #if !defined (HSI_VALUE) - #define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/ +#define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ /** @@ -118,7 +118,7 @@ * which is subject to manufacturing process variations. */ #if !defined (HSI48_VALUE) - #define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. +#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. The real value my vary depending on manufacturing process variations.*/ #endif /* HSI48_VALUE */ @@ -126,20 +126,20 @@ * @brief Internal Low Speed oscillator (LSI) value. */ #if !defined (LSI_VALUE) - #define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ +The real value may vary depending on the variations +in voltage and temperature.*/ /** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency */ #if !defined (LSE_VALUE) - #define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ #endif /* LSE_VALUE */ #if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ #endif /* HSE_STARTUP_TIMEOUT */ /** @@ -148,7 +148,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI1_CLOCK_VALUE) - #define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/ +#define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/ #endif /* EXTERNAL_SAI1_CLOCK_VALUE */ /** @@ -157,7 +157,7 @@ * frequency. */ #if !defined (EXTERNAL_SAI2_CLOCK_VALUE) - #define EXTERNAL_SAI2_CLOCK_VALUE 48000UL /*!< Value of the SAI2 External clock source in Hz*/ +#define EXTERNAL_SAI2_CLOCK_VALUE 48000UL /*!< Value of the SAI2 External clock source in Hz*/ #endif /* EXTERNAL_SAI2_CLOCK_VALUE */ /* Tip: To avoid modifying this file each time you need to use different HSE, @@ -189,127 +189,127 @@ * for each PPP peripheral). */ #if !defined (USE_HAL_ADC_REGISTER_CALLBACKS) - #define USE_HAL_ADC_REGISTER_CALLBACKS 0U +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_COMP_REGISTER_CALLBACKS) - #define USE_HAL_COMP_REGISTER_CALLBACKS 0U +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_CRYP_REGISTER_CALLBACKS) - #define USE_HAL_CRYP_REGISTER_CALLBACKS 0U +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_DAC_REGISTER_CALLBACKS) - #define USE_HAL_DAC_REGISTER_CALLBACKS 0U +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) - #define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_FDCAN_REGISTER_CALLBACKS) - #define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_HASH_REGISTER_CALLBACKS) - #define USE_HAL_HASH_REGISTER_CALLBACKS 0U +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_I2C_REGISTER_CALLBACKS) - #define USE_HAL_I2C_REGISTER_CALLBACKS 0U +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_IRDA_REGISTER_CALLBACKS) - #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_LPTIM_REGISTER_CALLBACKS) - #define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_MMC_REGISTER_CALLBACKS) - #define USE_HAL_MMC_REGISTER_CALLBACKS 0U +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_NAND_REGISTER_CALLBACKS) - #define USE_HAL_NAND_REGISTER_CALLBACKS 0U +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_NOR_REGISTER_CALLBACKS) - #define USE_HAL_NOR_REGISTER_CALLBACKS 0U +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_OPAMP_REGISTER_CALLBACKS) - #define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_OSPI_REGISTER_CALLBACKS) - #define USE_HAL_OSPI_REGISTER_CALLBACKS 0U +#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_OTFDEC_REGISTER_CALLBACKS) - #define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U +#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_PCD_REGISTER_CALLBACKS) - #define USE_HAL_PCD_REGISTER_CALLBACKS 0U +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_PKA_REGISTER_CALLBACKS) - #define USE_HAL_PKA_REGISTER_CALLBACKS 0U +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_RNG_REGISTER_CALLBACKS) - #define USE_HAL_RNG_REGISTER_CALLBACKS 0U +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_RTC_REGISTER_CALLBACKS) - #define USE_HAL_RTC_REGISTER_CALLBACKS 0U +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_SAI_REGISTER_CALLBACKS) - #define USE_HAL_SAI_REGISTER_CALLBACKS 0U +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_SD_REGISTER_CALLBACKS) - #define USE_HAL_SD_REGISTER_CALLBACKS 0U +#define USE_HAL_SD_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_SMARTCARD_REGISTER_CALLBACKS) - #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_SMBUS_REGISTER_CALLBACKS) - #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_SPI_REGISTER_CALLBACKS) - #define USE_HAL_SPI_REGISTER_CALLBACKS 0U +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_SRAM_REGISTER_CALLBACKS) - #define USE_HAL_SRAM_REGISTER_CALLBACKS 0U +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_TIM_REGISTER_CALLBACKS) - #define USE_HAL_TIM_REGISTER_CALLBACKS 0U +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_TSC_REGISTER_CALLBACKS) - #define USE_HAL_TSC_REGISTER_CALLBACKS 0U +#define USE_HAL_TSC_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_UART_REGISTER_CALLBACKS) - #define USE_HAL_UART_REGISTER_CALLBACKS 0U +#define USE_HAL_UART_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_USART_REGISTER_CALLBACKS) - #define USE_HAL_USART_REGISTER_CALLBACKS 0U +#define USE_HAL_USART_REGISTER_CALLBACKS 0U #endif #if !defined (USE_HAL_WWDG_REGISTER_CALLBACKS) - #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U #endif /* ################## SPI peripheral configuration ########################## */ @@ -337,178 +337,178 @@ */ #ifdef HAL_RCC_MODULE_ENABLED - #include "stm32l5xx_hal_rcc.h" +#include "stm32l5xx_hal_rcc.h" #endif /* HAL_RCC_MODULE_ENABLED */ #ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32l5xx_hal_gpio.h" +#include "stm32l5xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ #ifdef HAL_DMA_MODULE_ENABLED - #include "stm32l5xx_hal_dma.h" +#include "stm32l5xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ #ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32l5xx_hal_dfsdm.h" +#include "stm32l5xx_hal_dfsdm.h" #endif /* HAL_DFSDM_MODULE_ENABLED */ #ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32l5xx_hal_cortex.h" +#include "stm32l5xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ #ifdef HAL_ADC_MODULE_ENABLED - #include "stm32l5xx_hal_adc.h" +#include "stm32l5xx_hal_adc.h" #endif /* HAL_ADC_MODULE_ENABLED */ #ifdef HAL_COMP_MODULE_ENABLED - #include "stm32l5xx_hal_comp.h" +#include "stm32l5xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ #ifdef HAL_CRC_MODULE_ENABLED - #include "stm32l5xx_hal_crc.h" +#include "stm32l5xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32l5xx_hal_cryp.h" +#include "stm32l5xx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DAC_MODULE_ENABLED - #include "stm32l5xx_hal_dac.h" +#include "stm32l5xx_hal_dac.h" #endif /* HAL_DAC_MODULE_ENABLED */ #ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32l5xx_hal_exti.h" +#include "stm32l5xx_hal_exti.h" #endif /* HAL_EXTI_MODULE_ENABLED */ #ifdef HAL_FDCAN_MODULE_ENABLED - #include "stm32l5xx_hal_fdcan.h" +#include "stm32l5xx_hal_fdcan.h" #endif /* HAL_FDCAN_MODULE_ENABLED */ #ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32l5xx_hal_flash.h" +#include "stm32l5xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ #ifdef HAL_GTZC_MODULE_ENABLED - #include "stm32l5xx_hal_gtzc.h" +#include "stm32l5xx_hal_gtzc.h" #endif /* HAL_GTZC_MODULE_ENABLED */ #ifdef HAL_HASH_MODULE_ENABLED - #include "stm32l5xx_hal_hash.h" +#include "stm32l5xx_hal_hash.h" #endif /* HAL_HASH_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l5xx_hal_i2c.h" +#include "stm32l5xx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ #ifdef HAL_ICACHE_MODULE_ENABLED - #include "stm32l5xx_hal_icache.h" +#include "stm32l5xx_hal_icache.h" #endif /* HAL_ICACHE_MODULE_ENABLED */ #ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l5xx_hal_irda.h" +#include "stm32l5xx_hal_irda.h" #endif /* HAL_IRDA_MODULE_ENABLED */ #ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l5xx_hal_iwdg.h" +#include "stm32l5xx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ #ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32l5xx_hal_lptim.h" +#include "stm32l5xx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ #ifdef HAL_MMC_MODULE_ENABLED - #include "stm32l5xx_hal_mmc.h" +#include "stm32l5xx_hal_mmc.h" #endif /* HAL_MMC_MODULE_ENABLED */ #ifdef HAL_NAND_MODULE_ENABLED - #include "stm32l5xx_hal_nand.h" +#include "stm32l5xx_hal_nand.h" #endif /* HAL_NAND_MODULE_ENABLED */ #ifdef HAL_NOR_MODULE_ENABLED - #include "stm32l5xx_hal_nor.h" +#include "stm32l5xx_hal_nor.h" #endif /* HAL_NOR_MODULE_ENABLED */ #ifdef HAL_OPAMP_MODULE_ENABLED - #include "stm32l5xx_hal_opamp.h" +#include "stm32l5xx_hal_opamp.h" #endif /* HAL_OPAMP_MODULE_ENABLED */ #ifdef HAL_OSPI_MODULE_ENABLED - #include "stm32l5xx_hal_ospi.h" +#include "stm32l5xx_hal_ospi.h" #endif /* HAL_OSPI_MODULE_ENABLED */ #ifdef HAL_OTFDEC_MODULE_ENABLED - #include "stm32l5xx_hal_otfdec.h" +#include "stm32l5xx_hal_otfdec.h" #endif /* HAL_OTFDEC_MODULE_ENABLED */ #ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l5xx_hal_pcd.h" +#include "stm32l5xx_hal_pcd.h" #endif /* HAL_PCD_MODULE_ENABLED */ #ifdef HAL_PKA_MODULE_ENABLED - #include "stm32l5xx_hal_pka.h" +#include "stm32l5xx_hal_pka.h" #endif /* HAL_PKA_MODULE_ENABLED */ #ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l5xx_hal_pwr.h" +#include "stm32l5xx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ #ifdef HAL_RNG_MODULE_ENABLED - #include "stm32l5xx_hal_rng.h" +#include "stm32l5xx_hal_rng.h" #endif /* HAL_RNG_MODULE_ENABLED */ #ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l5xx_hal_rtc.h" +#include "stm32l5xx_hal_rtc.h" #endif /* HAL_RTC_MODULE_ENABLED */ #ifdef HAL_SAI_MODULE_ENABLED - #include "stm32l5xx_hal_sai.h" +#include "stm32l5xx_hal_sai.h" #endif /* HAL_SAI_MODULE_ENABLED */ #ifdef HAL_SD_MODULE_ENABLED - #include "stm32l5xx_hal_sd.h" +#include "stm32l5xx_hal_sd.h" #endif /* HAL_SD_MODULE_ENABLED */ #ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l5xx_hal_smartcard.h" +#include "stm32l5xx_hal_smartcard.h" #endif /* HAL_SMARTCARD_MODULE_ENABLED */ #ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32l5xx_hal_smbus.h" +#include "stm32l5xx_hal_smbus.h" #endif /* HAL_SMBUS_MODULE_ENABLED */ #ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l5xx_hal_spi.h" +#include "stm32l5xx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ #ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32l5xx_hal_sram.h" +#include "stm32l5xx_hal_sram.h" #endif /* HAL_SRAM_MODULE_ENABLED */ #ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l5xx_hal_tim.h" +#include "stm32l5xx_hal_tim.h" #endif /* HAL_TIM_MODULE_ENABLED */ #ifdef HAL_TSC_MODULE_ENABLED - #include "stm32l5xx_hal_tsc.h" +#include "stm32l5xx_hal_tsc.h" #endif /* HAL_TSC_MODULE_ENABLED */ #ifdef HAL_UART_MODULE_ENABLED - #include "stm32l5xx_hal_uart.h" +#include "stm32l5xx_hal_uart.h" #endif /* HAL_UART_MODULE_ENABLED */ #ifdef HAL_USART_MODULE_ENABLED - #include "stm32l5xx_hal_usart.h" +#include "stm32l5xx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ #ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l5xx_hal_wwdg.h" +#include "stm32l5xx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ #ifdef USE_FULL_ASSERT #include "stm32_assert.h" // MBED patch #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ #ifdef __cplusplus diff --git a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/system_stm32l5xx.c b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/system_stm32l5xx.c index 7639b5084b..bb952bb4a2 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/system_stm32l5xx.c +++ b/targets/TARGET_STM/TARGET_STM32L5/STM32Cube_FW/system_stm32l5xx.c @@ -206,7 +206,7 @@ * @retval None */ -void SystemInit(void) +__WEAK void SystemInit(void) { /* Configure the Vector Table location -------------------------------------*/ #include "nvic_addr.h" // MBED diff --git a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xE/TARGET_DISCO_L562QE/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xE/TARGET_DISCO_L562QE/PeripheralPins.c index dee2ebf67c..4772207b1d 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xE/TARGET_DISCO_L562QE/PeripheralPins.c +++ b/targets/TARGET_STM/TARGET_STM32L5/TARGET_STM32L562xE/TARGET_DISCO_L562QE/PeripheralPins.c @@ -294,7 +294,7 @@ MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to OCTOSPI1_IO2 {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to USB_DP {PB_5_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to UCPD_DBn - {PB_5 , SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to UCPD_DBn + {PB_5, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to UCPD_DBn {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to UCPD1_CC2 {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_SPI2)}, // Connected to OCTOSPI1_IO4 {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to OCTOSPI1_IO6 @@ -310,7 +310,7 @@ MBED_WEAK const PinMap PinMap_SPI_MISO[] = { {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to OCTOSPI1_IO3 {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to USB_DM {PB_4_ALT0, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, - {PB_4 , SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_4, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to UCPD_FLT {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, // Connected to OCTOSPI1_IO5 {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, // Connected to SDMMC1_D3 diff --git a/targets/TARGET_STM/TARGET_STM32L5/can_device.h b/targets/TARGET_STM/TARGET_STM32L5/can_device.h index 357b6ec561..17f055456f 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/can_device.h +++ b/targets/TARGET_STM/TARGET_STM32L5/can_device.h @@ -39,4 +39,8 @@ extern "C" { #endif // DEVICE_CAN +#ifdef __cplusplus +} +#endif + #endif diff --git a/targets/TARGET_STM/TARGET_STM32L5/i2c_device.c b/targets/TARGET_STM/TARGET_STM32L5/i2c_device.c new file mode 100755 index 0000000000..bd593f5dc5 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32L5/i2c_device.c @@ -0,0 +1,159 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "i2c_device.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "stm32l5xx_ll_rcc.h" + +/* Define I2C Device */ +#if DEVICE_I2C + +/** + * @brief Get I2C clock source frequency according I2C instance used. + * @param i2c I2C instance name. + * @retval I2C clock source frequency in Hz. + */ +uint32_t i2c_get_pclk(I2CName i2c) +{ + uint32_t clocksource; + uint32_t pclk = 0; + if (i2c == I2C_1) { + clocksource = __HAL_RCC_GET_I2C1_SOURCE(); + switch (clocksource) { + case RCC_I2C1CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C1CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C1CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#if defined I2C2_BASE + else if (i2c == I2C_2) { + clocksource = __HAL_RCC_GET_I2C2_SOURCE(); + switch (clocksource) { + case RCC_I2C2CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C2CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C2CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif +#if defined I2C3_BASE + else if (i2c == I2C_3) { + clocksource = __HAL_RCC_GET_I2C3_SOURCE(); + switch (clocksource) { + case RCC_I2C3CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C3CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C3CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif +#if defined I2C4_BASE + else if (i2c == I2C_4) { + clocksource = __HAL_RCC_GET_I2C4_SOURCE(); + switch (clocksource) { + case RCC_I2C4CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C4CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C4CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif + else { + // should not happend + error("I2C: unknown instance"); + } + return pclk; +} +/** + * @} + */ + +/** @defgroup I2C_DEVICE_Exported_Functions I2C_DEVICE Exported Functions + * @{ + */ +/** + * @brief Provide the suitable timing depending on requested frequency + * @param hz Required I2C clock in Hz. + * @retval I2C timing or 0 in case of error. + */ +uint32_t i2c_get_timing(I2CName i2c, int hz) +{ + uint32_t tim; + uint32_t pclk; + + pclk = i2c_get_pclk(i2c); + if (pclk == I2C_PCLK_DEF) { + switch (hz) { + case 100000: + tim = TIMING_VAL_DEFAULT_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_DEFAULT_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_DEFAULT_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } + + else { + /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. + User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. + Enabling this may impact performance */ + MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO); +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + tim = i2c_compute_timing(pclk, hz); +#endif + } + return tim; +} +/** + * @} + */ + +#endif // DEVICE_I2C diff --git a/targets/TARGET_STM/TARGET_STM32L5/i2c_device.h b/targets/TARGET_STM/TARGET_STM32L5/i2c_device.h index 90ee70c22f..089bfeb875 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32L5/i2c_device.h @@ -2,7 +2,7 @@ * SPDX-License-Identifier: BSD-3-Clause ****************************************************************************** * - * Copyright (c) 2015 STMicroelectronics. + * Copyright (c) 2015-2021 STMicroelectronics. * All rights reserved. * * This software component is licensed by ST under BSD 3-Clause license, @@ -16,17 +16,24 @@ #ifndef MBED_I2C_DEVICE_H #define MBED_I2C_DEVICE_H -#include "cmsis.h" -#include "mbed_error.h" +#include "PeripheralNames.h" #ifdef __cplusplus extern "C" { #endif +/* Define I2C Device */ #if DEVICE_I2C +/* Define IP version */ #define I2C_IP_VERSION_V2 +// Common settings: I2C clock = 110 MHz, Analog filter = ON, Digital filter coefficient = 0 +#define TIMING_VAL_DEFAULT_CLK_100KHZ 0x40E15676 // Standard mode with Rise Time = 400ns and Fall Time = 100ns +#define TIMING_VAL_DEFAULT_CLK_400KHZ 0x20C11434 // Fast mode with Rise Time = 250ns and Fall Time = 100ns +#define TIMING_VAL_DEFAULT_CLK_1MHZ 0x00C31536 // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns +#define I2C_PCLK_DEF 110000000 // 110 MHz + #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI) /* Family specifc settings for clock source */ @@ -35,36 +42,19 @@ extern "C" { #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_SYSCLK #define I2CAPI_I2C4_CLKSRC RCC_I2C4CLKSOURCE_SYSCLK -/* Provide the suitable timing depending on requested frequencie */ -static inline uint32_t get_i2c_timing(int hz) -{ - uint32_t tim = 0; - if (SystemCoreClock == 110000000) { - // Common settings: I2C clock = 80 MHz, Analog filter = ON, Digital filter coefficient = 0 - switch (hz) { - case 100000: - tim = 0x40E15676; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - tim = 0x20C11434; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - tim = 0x00C31536; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - } - else { - error("Value not provided for SystemCoreClock %u\n", SystemCoreClock); - } - return tim; -} +uint32_t i2c_get_pclk(I2CName i2c); +uint32_t i2c_get_timing(I2CName i2c, int hz); + +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq); +void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t I2C_speed); +uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t I2C_speed); +#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + +#endif // DEVICE_I2C #ifdef __cplusplus } #endif -#endif // DEVICE_I2C - #endif diff --git a/targets/TARGET_STM/TARGET_STM32L5/objects.h b/targets/TARGET_STM/TARGET_STM32L5/objects.h index fb8af8dd37..4d9cbcaaa1 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/objects.h +++ b/targets/TARGET_STM/TARGET_STM32L5/objects.h @@ -118,6 +118,9 @@ struct i2c_s { uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32L5/system_clock.c b/targets/TARGET_STM/TARGET_STM32L5/system_clock.c index ef740466c4..49252f4f5a 100644 --- a/targets/TARGET_STM/TARGET_STM32L5/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32L5/system_clock.c @@ -121,18 +121,18 @@ uint8_t SetSysClock_PLL_MSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - - /* Configure the main internal regulator output voltage */ - if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE0) != HAL_OK) { - return 0; // FAIL - } - + /* Configure LSE Drive Capability */ __HAL_RCC_PWR_CLK_ENABLE(); __HAL_RCC_SYSCFG_CLK_ENABLE(); HAL_PWR_EnableBkUpAccess(); __HAL_RCC_RTCAPB_CLK_ENABLE(); + /* Configure the main internal regulator output voltage */ + if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE0) != HAL_OK) { + return 0; // FAIL + } + #if MBED_CONF_TARGET_LSE_AVAILABLE RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; diff --git a/targets/TARGET_STM/TARGET_STM32WB/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WB/CMakeLists.txt index 73de69f785..be3fc690fa 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32WB/CMakeLists.txt @@ -26,6 +26,7 @@ target_sources(mbed-stm32wb analogin_device.c flash_api.c gpio_irq_device.c + i2c_device.c pwmout_device.c serial_device.c spi_api.c diff --git a/targets/TARGET_STM/TARGET_STM32WB/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32WB/PeripheralNames.h index 18d86d95fe..7b95553dbc 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32WB/PeripheralNames.h @@ -35,28 +35,42 @@ typedef enum { #define DEVICE_SPI_COUNT 2 typedef enum { SPI_1 = (int)SPI1_BASE, - SPI_2 = (int)SPI2_BASE +#if defined SPI2_BASE + SPI_2 = (int)SPI2_BASE, +#endif } SPIName; typedef enum { I2C_1 = (int)I2C1_BASE, +#if defined I2C3_BASE I2C_3 = (int)I2C3_BASE +#endif } I2CName; typedef enum { PWM_1 = (int)TIM1_BASE, +#if defined TIM2_BASE PWM_2 = (int)TIM2_BASE, +#endif +#if defined TIM16_BASE PWM_16 = (int)TIM16_BASE, +#endif +#if defined TIM17_BASE PWM_17 = (int)TIM17_BASE +#endif } PWMName; +#if defined QUADSPI_R_BASE typedef enum { QSPI_1 = (int)QUADSPI_R_BASE } QSPIName; +#endif +#if defined USB_BASE typedef enum { USB_FS = (int)USB_BASE, } USBName; +#endif #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32WB/README.md b/targets/TARGET_STM/TARGET_STM32WB/README.md index d33b04bf23..5dcd2c107f 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/README.md +++ b/targets/TARGET_STM/TARGET_STM32WB/README.md @@ -1,12 +1,13 @@ * [STM32WB family](#stm32wb-family) * [Supported boards](#supported-boards) - * [NUCLEO_WB55RG](#nucleo_wb55rg) + * [NUCLEO_WB55RG (NUCLEO-WB55RG)](#nucleo_wb55rg-nucleo-wb55rg) * [DISCO_WB5MMG (STM32WB5MM-DK)](#disco_wb5mmg-stm32wb5mm-dk) * [BLE](#ble) * [MBED-OS support](#mbed-os-support) - * [mbed-trace support](#mbed-trace-support) + * [BLE FW](#ble-fw) * [BLE FW update](#ble-fw-update) * [BLE FW flashing procedure](#ble-fw-flashing-procedure) + * [mbed-trace support](#mbed-trace-support) # STM32WB family @@ -30,8 +31,9 @@ This ST MCU family is dual-core : based on an Arm Cortex-M4 core and an Arm Cort [mbed.com platform page](https://os.mbed.com/platforms/ST-Nucleo-WB55RG/) -- Total FLASH is 1MB, but note that it is shared by M4 and M0 cores. - - mbed-os application size is then limited to 768 KB +- Total FLASH is 1MB + +But FLASH is shared by M4 and M0 cores, [see BLE FW](#ble-fw) - RAM: 256 KB - SRAM1: 192 KB @@ -51,8 +53,9 @@ SRAM2 is dedicated for M0 core and inter CPU communication, and then can not be [mbed.com platform page](https://os.mbed.com/platforms/DISCO-WB5MMG/) -- Total FLASH is 1MB, but note that it is shared by M4 and M0 cores. - - mbed-os application size is then limited to 768 KB +- Total FLASH is 1MB + +But FLASH is shared by M4 and M0 cores, [see BLE FW](#ble-fw) - RAM: 256 KB - SRAM1: 192 KB @@ -69,6 +72,33 @@ mbedls -m 0884:DISCO_WB5MMG ``` +## NUCLEO_WB15CC (NUCLEO-WB15CC) + +[st.com STM32WB15CC module page](https://www.st.com/en/microcontrollers-microprocessors/stm32wb15cc.html) + +[st.com NUCLEO board page]() + +[mbed.com platform page](https://os.mbed.com/platforms/ST-NUCLEO-WB15CC/) + +- Total FLASH is 320KB + +But FLASH is shared by M4 and M0 cores, [see BLE FW](#ble-fw) + +- RAM: 48 KB + - SRAM1: 12 KB + - SRAM2a: 32 KB + - SRAM2b: 4 KB + +SRAM1 is dedicated for M4 core, and then for mbed-os applications. + +SRAM2 is dedicated for M0 core and inter CPU communication, and some part can not be addressed by M4. + +NB: MBED CLI1 tool can be used thanks to this command: +``` +mbedls -m 0883:NUCLEO_WB15CC +``` + + # BLE ## MBED-OS support @@ -83,11 +113,72 @@ Note that the BLE controller firmware running on the cortex-M0 is the same as in Official ST Application Note : [AN5289: Building wireless applications with STM32WB Series microcontrollers](https://www.st.com/resource/en/application_note/dm00598033-building-wireless-applications-with-stm32wb-series-microcontrollers-stmicroelectronics.pdf) +## BLE FW + +All available BLE FW for M0 core are provided in ths ST STM32CubeWB repo: + +### STM32WB5x + +https://github.com/STMicroelectronics/STM32CubeWB/tree/master/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x + +Default BLE FW in ST boards is **stm32wb5x_BLE_Stack_full_fw.bin** +- As explained in Release_Notes.html, this FW is flashed at @ 0x080CA000 +- Default "mbed_rom_size" in targets.json is then "0xCA000" (808K) + +To optimize FLASH size, **stm32wb5x_BLE_HCILayer_fw.bin** is supported for MBED-OS use case +- As explained in Release_Notes.html, this FW is flashed at @ 0x080E0000 +- Then "mbed_rom_size" can be updated to "0xE0000" (896K) + +Example in your local mbed_app.json: +``` + "target_overrides": { + "NUCLEO_WB55RG": { + "target.mbed_rom_size": "0xE0000" + } +``` + +### STM32WB1x + +https://github.com/STMicroelectronics/STM32CubeWB/tree/master/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB1x + +Default BLE FW in ST boards is **stm32wb1x_BLE_Stack_full_fw.bin** +- **this is not supported in mbed** + +It is mandatory to use **stm32wb1x_BLE_HCILayer_fw.bin** +- As explained in Release_Notes.html, this FW is flashed at @ 0x08032800 +- Then "mbed_rom_size" is "0x32800" (202K) (default configuration in targets.json) + + +## BLE FW update + +Official ST Application Note : +[AN5185: ST firmware upgrade services for STM32WB Series](http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00513965.pdf) + + +## BLE FW flashing procedure + +STM32CubeProgrammer needs to be used: + +https://www.st.com/en/development-tools/stm32cubeprog.html + +Please check the Release Note and complete flashing procedure: +https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeWB/blob/master/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/Release_Notes.html + +- connect the board with ST-LINK +- In the left column, go to "Firmware Upgrade Services" +- "Start FUS" +- "Read FUS infos" => version v1.2.0 is expected +- Firmware Upgrade / "Browse" : select the chosen FW (see above) +- Firmware Upgrade / Start address : depends on the chosen FW (see above) +- Firmware Upgrade / "Firmware Upgrade" +- In the left column, go to "Option bytes" +- User Configuration => "Read" +- User Configuration / enable nSWBOOT0 => "Apply" ## mbed-trace support -trace group: BLE_WB +trace group: BLWB example: ```` @@ -99,104 +190,3 @@ example: [DBG ][BLWB]: Cmd 0xc03 [DBG ][BLWB]: Len 0D] ```` - -## BLE FW update - -Official ST Application Note : -[AN5185: ST firmware upgrade services for STM32WB Series](http://www.st.com/st-web-ui/static/active/en/resource/technical/document/application_note/DM00513965.pdf) - -Latest BLE FW : -https://github.com/STMicroelectronics/STM32CubeWB/blob/master/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/stm32wb5x_BLE_Stack_full_fw.bin - -## BLE FW flashing procedure - -Release Note and complete flashing procedure: -https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeWB/blob/master/Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/Release_Notes.html - - -- STEP 1: Use STM32CubeProgrammer - -https://www.st.com/en/development-tools/stm32cubeprog.html - -```` -FLASHPATH="C:\Program Files\STMicroelectronics\STM32Cube\STM32CubeProgrammer\bin" -export PATH=$FLASHPATH:$PATH -```` - -- STEP 2: Access to Bootloader USB Interface (system flash) - - * Boot0 pin set to VDD : Jumper between CN7.5(VDD) and CN7.7(Boot0) - * Jumper JP1 on USB_MCU - * Power ON via USB_USER - -![Image description](stm32wb_ble_update.jpg) - -- STEP 3 : Delete current wireless stack : - -``` -$ STM32_Programmer_CLI.exe -c port=usb1 -fwdelete -... -FUS state is FUS_IDLE - -FUS status is FUS_NO_ERROR -Deleting firmware ... -Firmware delete finished -fwdelete command execution finished -``` - -- STEP 4 : Read FUS Version - -``` -$ STM32_Programmer_CLI.exe -c port=usb1 -r32 0x20030030 1 -... - -Reading 32-bit memory content - Size : 4 Bytes - Address: : 0x20030030 - -0x20030030 : 00050300 -``` - -- STEP 5A if last result is 00050300 : Download new FUS : - -``` -$ ./STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade stm32wb5x_FUS_fw_for_fus_0_5_3.bin 0x080EC000 firstinstall=0 -``` - -- STEP 5B if last result is 01000100 or 01000200 : Download new FUS : - -``` -$ STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade stm32wb5x_FUS_fw.bin 0x080EC000 firstinstall=0 -... -Firmware Upgrade Success -``` - - -- STEP 4 (to check) : Read FUS Version - -``` -$ STM32_Programmer_CLI.exe -c port=usb1 -r32 0x20030030 1 - -Reading 32-bit memory content - Size : 4 Bytes - Address: : 0x20030030 - -0x20030030 : 01020000 -``` - -- STEP 6 : Download new wireless stack : - - -``` -$ STM32_Programmer_CLI.exe -c port=usb1 -fwupgrade stm32wb5x_BLE_Stack_full_fw.bin 0x080CA000 firstinstall=1 - -... -Download firmware image at address 0x80cb000 ... -... -File download complete -... -Firmware Upgrade Success -``` - -- STEP 7 : Revert STEP 2 procedure to put back device in normal mode. - diff --git a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/app_conf.h b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/app_conf.h index 8171527f2f..2a7dc3d253 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/app_conf.h +++ b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/app_conf.h @@ -148,7 +148,11 @@ * Maximum number of simultaneous connections that the device will support. * Valid values are from 1 to 8 */ +#ifdef TARGET_MCU_STM32WB15xC +#define CFG_BLE_NUM_LINK 4 +#else #define CFG_BLE_NUM_LINK 8 +#endif /** * Maximum number of Services that can be stored in the GATT database. diff --git a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/stm32_lpm_if.c b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/stm32_lpm_if.c index b351547547..bf7dedf99c 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/stm32_lpm_if.c +++ b/targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/stm32_lpm_if.c @@ -122,7 +122,11 @@ void PWR_EnterStopMode( void ) /************************************************************************************ * ENTER STOP MODE ***********************************************************************************/ +#if defined(PWR_SUPPORT_STOP2) LL_PWR_SetPowerMode( LL_PWR_MODE_STOP2 ); +#else + LL_PWR_SetPowerMode( LL_PWR_MODE_STOP1 ); +#endif LL_LPM_EnableDeepSleep( ); /**< Set SLEEPDEEP bit of Cortex System Control Register */ diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/CMakeLists.txt index 02cd80d7f2..5d6c75d23d 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/CMakeLists.txt @@ -1,6 +1,8 @@ # Copyright (c) 2020 ARM Limited. All rights reserved. # SPDX-License-Identifier: Apache-2.0 +add_subdirectory(TARGET_NUCLEO_WB15CC EXCLUDE_FROM_ALL) + if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM") set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32wb15xx.S) set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32wb15xc.ld) @@ -19,6 +21,7 @@ target_include_directories(mbed-stm32wb15xc target_sources(mbed-stm32wb15xc INTERFACE ${STARTUP_FILE} + system_clock.c ) mbed_set_linker_script(mbed-stm32wb15xc ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE}) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TARGET_NUCLEO_WB15CC/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TARGET_NUCLEO_WB15CC/CMakeLists.txt new file mode 100644 index 0000000000..b4ac1d1b4c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TARGET_NUCLEO_WB15CC/CMakeLists.txt @@ -0,0 +1,16 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +add_library(mbed-nucleo-wb15cc INTERFACE) + +target_sources(mbed-nucleo-wb15cc + INTERFACE + PeripheralPins.c +) + +target_include_directories(mbed-nucleo-wb15cc + INTERFACE + . +) + +target_link_libraries(mbed-nucleo-wb15cc INTERFACE mbed-stm32wb15xc) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TARGET_NUCLEO_WB15CC/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TARGET_NUCLEO_WB15CC/PeripheralPins.c new file mode 100644 index 0000000000..40aa49dc7b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TARGET_NUCLEO_WB15CC/PeripheralPins.c @@ -0,0 +1,168 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32WB15CCUx.xml + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5 // Connected to B1 [Push Button] + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11 // Connected to B3 [Push Button] + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 + {PA_8, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3 +// {PA_9, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 // Connected to STDIO_UART_TX + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, + {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, + {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { +// {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_RX + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { +// {PA_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // Connected to STDIO_UART_TX + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM2 cannot be used because already used by the us_ticker +// (update us_ticker_data.h file if another timer is chosen) +MBED_WEAK const PinMap PinMap_PWM[] = { +// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to B1 [Push Button] +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 +// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 // Connected to STDIO_UART_TX +// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 // Connected to STDIO_UART_RX + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to JTDO + {PB_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_TIM1, 3, 0)}, // TIM1_CH3 + {PB_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_2, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX + {PB_5, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD1 [Blue Led] + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_3, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX + {PA_12, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LD3 [Red Led] + {PB_3, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to JTDO + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_6, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to B3 [Push Button] + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_4, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF4_SPI1)}, + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_13, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to JTMS + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to LD1 [Blue Led] + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to B3 [Push Button] + {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_1, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to JTDO + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_14, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, // Connected to JTCK + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_2, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TARGET_NUCLEO_WB15CC/PinNames.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TARGET_NUCLEO_WB15CC/PinNames.h new file mode 100644 index 0000000000..3c378e7d64 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TARGET_NUCLEO_WB15CC/PinNames.h @@ -0,0 +1,138 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32WB15CCUx.xml + */ + +/* MBED TARGET LIST: NUCLEO_WB15CC */ + +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + + PA_0 = 0x00, + PA_1 = 0x01, + PA_2 = 0x02, + PA_3 = 0x03, + PA_4 = 0x04, + PA_5 = 0x05, + PA_6 = 0x06, + PA_7 = 0x07, + PA_8 = 0x08, + PA_9 = 0x09, + PA_10 = 0x0A, + PA_11 = 0x0B, + PA_12 = 0x0C, + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PB_0 = 0x10, + PB_1 = 0x11, + PB_2 = 0x12, + PB_3 = 0x13, + PB_4 = 0x14, + PB_5 = 0x15, + PB_6 = 0x16, + PB_7 = 0x17, + PB_8 = 0x18, + PB_9 = 0x19, + PC_14 = 0x2E, + PC_15 = 0x2F, + PE_4 = 0x44, + PH_3 = 0x73, + + /**** ADC internal channels ****/ + + ADC_TEMP = 0xF0, // Internal pin virtual value + ADC_VREF = 0xF1, // Internal pin virtual value + ADC_VBAT = 0xF2, // Internal pin virtual value + +#ifdef TARGET_FF_ARDUINO_UNO + // Arduino Uno (Rev3) pins + ARDUINO_UNO_A0 = PA_4, + ARDUINO_UNO_A1 = PA_6, + ARDUINO_UNO_A2 = PA_1, + ARDUINO_UNO_A3 = PA_0, + ARDUINO_UNO_A4 = PA_2, + ARDUINO_UNO_A5 = PA_3, + + ARDUINO_UNO_D0 = PB_7, + ARDUINO_UNO_D1 = PB_6, + ARDUINO_UNO_D2 = PB_0, + ARDUINO_UNO_D3 = PA_12, + ARDUINO_UNO_D4 = PB_1, + ARDUINO_UNO_D5 = PA_11, + ARDUINO_UNO_D6 = PA_8, + ARDUINO_UNO_D7 = PE_4, + ARDUINO_UNO_D8 = PB_5, + ARDUINO_UNO_D9 = PA_15, + ARDUINO_UNO_D10 = PB_2, + ARDUINO_UNO_D11 = PA_7, + ARDUINO_UNO_D12 = PB_4, + ARDUINO_UNO_D13 = PA_5, + ARDUINO_UNO_D14 = PB_9, + ARDUINO_UNO_D15 = PB_8, +#endif + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + CONSOLE_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + CONSOLE_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + CONSOLE_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + CONSOLE_RX = PA_10, +#endif + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + + /**** DEBUG pins ****/ + SYS_JTCK_SWCLK = PA_14, + SYS_JTDI = PA_15, + SYS_JTDO_SWO = PB_3, + SYS_JTMS_SWDIO = PA_13, + SYS_JTRST = PB_4, + SYS_PVD_IN = PB_7, + SYS_WKUP1 = PA_0, + SYS_WKUP4 = PA_2, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +// Standardized LED and button names +#define LED1 PB_5 // LD1 [Blue Led] +#define LED2 PB_0 // LD2 [Green Led] +#define LED3 PB_1 // LD3 [Red Led] +#define BUTTON1 PA_0 // B1 [Push Button] +#define BUTTON2 PE_4 // B2 [Push Button] +#define BUTTON3 PA_6 // B3 [Push Button] + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_ARM/stm32wb15xc.sct b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_ARM/stm32wb15xc.sct index 7aff08bc28..cef609c228 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_ARM/stm32wb15xc.sct +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_ARM/stm32wb15xc.sct @@ -22,7 +22,9 @@ #endif #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE +// MBED_APP_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH +// Size is defined in json with "mbed_rom_size" +#define MBED_APP_SIZE MBED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) @@ -37,6 +39,7 @@ /* Round up VECTORS_SIZE to 8 bytes */ #define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) +; RAM_SIZE = 12KB SRAM (0x3000) + Shared mem (part of SRAM2) LR_IROM1 MBED_APP_START MBED_APP_SIZE { ER_IROM1 MBED_APP_START MBED_APP_SIZE { @@ -49,9 +52,17 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { .ANY (+RW +ZI) } - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up + ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + 0x3000 - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up } - ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down + ARM_LIB_STACK (MBED_RAM_START + 0x3000) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down } + + ; SRAM2 - Shared memory + RW_IRAM2 0x20030000 0x2800 { ; RW data + *(MAPPING_TABLE) + *(MB_MEM1) + *(MB_MEM2) + } + } diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_GCC_ARM/stm32wb15xc.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_GCC_ARM/stm32wb15xc.ld index 5f479936c8..ed217f3d9d 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_GCC_ARM/stm32wb15xc.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_GCC_ARM/stm32wb15xc.ld @@ -23,7 +23,9 @@ #endif #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE +/* MBED_APP_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH */ +/* Size is defined in json with "mbed_rom_size" */ +#define MBED_APP_SIZE MBED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) @@ -35,10 +37,12 @@ /* Round up VECTORS_SIZE to 8 bytes */ #define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) +/* RAM_SIZE = 12KB SRAM (0x3000) + Shared mem (part of SRAM2) */ MEMORY -{ - FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE - RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE +{ + FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = 0x3000 - VECTORS_SIZE + RAM2 (rw) : ORIGIN = 0x20030000, LENGTH = 10K } /* Linker script to place sections and symbol values. Should be used together @@ -191,6 +195,19 @@ SECTIONS *(.stack*) } > RAM + .ble_stby_mem (NOLOAD) : + { + *(MAPPING_TABLE); + *(MB_MEM1); + } >RAM2 + + .ble_shared_no_ret (NOLOAD) : + { + _sMB_MEM2 = . ; + *(MB_MEM2); + _eMB_MEM2 = . ; + } >RAM2 + /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ __StackTop = ORIGIN(RAM) + LENGTH(RAM); diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_IAR/startup_stm32wb15xx.S b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_IAR/startup_stm32wb15xx.S deleted file mode 100644 index 5c3e61967a..0000000000 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_IAR/startup_stm32wb15xx.S +++ /dev/null @@ -1,432 +0,0 @@ -;****************************************************************************** -;* File Name : startup_stm32wb15xx_cm4.s -;* Author : MCD Application Team -;* Description : M4 core vector table of the STM32WB15xx devices for the -;* IAR (EWARM) toolchain. -;* -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;****************************************************************************** -;* @attention -;* -;*

© Copyright (c) 2019 STMicroelectronics. -;* All rights reserved.

-;* -;* This software component is licensed by ST under Apache License, Version 2.0, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/Apache-2.0 -;* -;****************************************************************************** -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_PVM_IRQHandler ; PVD and PVM Interrupt - DCD TAMP_STAMP_LSECSS_IRQHandler ; RTC Tamper, TimeStamp Interrupts and LSECSS Interrupts - DCD RTC_WKUP_IRQHandler ; RTC Wakeup Interrupt - DCD FLASH_IRQHandler ; FLASH global Interrupt - DCD RCC_IRQHandler ; RCC Interrupt - DCD EXTI0_IRQHandler ; EXTI Line 0 Interrupt - DCD EXTI1_IRQHandler ; EXTI Line 1 Interrupt - DCD EXTI2_IRQHandler ; EXTI Line 2 Interrupt - DCD EXTI3_IRQHandler ; EXTI Line 3 Interrup - DCD EXTI4_IRQHandler ; EXTI Line 4 Interrupt - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 Interrupt - DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 Interrupt - DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 Interrupt - DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 Interrupt - DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 Interrupt - DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 Interrupt - DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 Interrupt - DCD ADC1_IRQHandler ; ADC1 Interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD C2SEV_PWR_C2H_IRQHandler ; CPU M0+ SEV Interrupt - DCD COMP_IRQHandler ; COMP1 Interrupts - DCD EXTI9_5_IRQHandler ; EXTI Lines [9:5] Interrupt - DCD TIM1_BRK_IRQHandler ; TIM1 Break Interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Communication Interrupts - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare Interrupt - DCD TIM2_IRQHandler ; TIM2 Global Interrupt - DCD PKA_IRQHandler ; PKA Interrupt - DCD I2C1_EV_IRQHandler ; I2C1 Event Interrupt - DCD I2C1_ER_IRQHandler ; I2C1 Error Interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 Interrupt - DCD 0 ; Reserved - DCD USART1_IRQHandler ; USART1 Interrupt - DCD LPUART1_IRQHandler ; LPUART1 Interrupt - DCD 0 ; Reserved - DCD TSC_IRQHandler ; TSC Interrupt - DCD EXTI15_10_IRQHandler ; EXTI Lines1[15:10 ]Interrupts - DCD RTC_Alarm_IRQHandler ; RTC Alarms (A and B) Interrupt - DCD 0 ; Reserved - DCD PWR_SOTF_BLEACT_RFPHASE_IRQHandler ; WKUP Interrupt from PWR - DCD IPCC_C1_RX_IRQHandler ; IPCC CPU1 RX occupied interrupt - DCD IPCC_C1_TX_IRQHandler ; IPCC CPU1 RX free interrupt - DCD HSEM_IRQHandler ; HSEM0 Interrupt - DCD LPTIM1_IRQHandler ; LPTIM1 Interrupt - DCD LPTIM2_IRQHandler ; LPTIM2 Interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD AES2_IRQHandler ; AES2 Interrupt - DCD RNG_IRQHandler ; RNG1 Interrupt - DCD FPU_IRQHandler ; FPU Interrupt - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMAMUX1_OVR_IRQHandler ; DMAMUX overrun Interrupt - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_PVM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -PVD_PVM_IRQHandler - B PVD_PVM_IRQHandler - - PUBWEAK TAMP_STAMP_LSECSS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TAMP_STAMP_LSECSS_IRQHandler - B TAMP_STAMP_LSECSS_IRQHandler - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_IRQHandler - B DMA1_Channel2_IRQHandler - - PUBWEAK DMA1_Channel3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel3_IRQHandler - B DMA1_Channel3_IRQHandler - - PUBWEAK DMA1_Channel4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_IRQHandler - B DMA1_Channel4_IRQHandler - - PUBWEAK DMA1_Channel5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel5_IRQHandler - B DMA1_Channel5_IRQHandler - - PUBWEAK DMA1_Channel6_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel6_IRQHandler - B DMA1_Channel6_IRQHandler - - PUBWEAK DMA1_Channel7_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel7_IRQHandler - B DMA1_Channel7_IRQHandler - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - PUBWEAK C2SEV_PWR_C2H_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -C2SEV_PWR_C2H_IRQHandler - B C2SEV_PWR_C2H_IRQHandler - - PUBWEAK COMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -COMP_IRQHandler - B COMP_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_IRQHandler - B TIM1_BRK_IRQHandler - - PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_UP_IRQHandler - B TIM1_UP_IRQHandler - - PUBWEAK TIM1_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_TRG_COM_IRQHandler - B TIM1_TRG_COM_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK PKA_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -PKA_IRQHandler - B PKA_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK LPUART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPUART1_IRQHandler - B LPUART1_IRQHandler - - PUBWEAK TSC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TSC_IRQHandler - B TSC_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK PWR_SOTF_BLEACT_RFPHASE_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -PWR_SOTF_BLEACT_RFPHASE_IRQHandler - B PWR_SOTF_BLEACT_RFPHASE_IRQHandler - - PUBWEAK IPCC_C1_RX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -IPCC_C1_RX_IRQHandler - B IPCC_C1_RX_IRQHandler - - PUBWEAK IPCC_C1_TX_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -IPCC_C1_TX_IRQHandler - B IPCC_C1_TX_IRQHandler - - PUBWEAK HSEM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -HSEM_IRQHandler - B HSEM_IRQHandler - - PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - - PUBWEAK LPTIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LPTIM2_IRQHandler - B LPTIM2_IRQHandler - - PUBWEAK AES2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -AES2_IRQHandler - B AES2_IRQHandler - - PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RNG_IRQHandler - B RNG_IRQHandler - - PUBWEAK FPU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FPU_IRQHandler - B FPU_IRQHandler - - PUBWEAK DMAMUX1_OVR_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMAMUX1_OVR_IRQHandler - B DMAMUX1_OVR_IRQHandler - - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_IAR/stm32wb15xc.icf b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_IAR/stm32wb15xc.icf deleted file mode 100644 index d136a6500c..0000000000 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/TOOLCHAIN_IAR/stm32wb15xc.icf +++ /dev/null @@ -1,59 +0,0 @@ -/* Linker script to configure memory regions. - * - * SPDX-License-Identifier: BSD-3-Clause - ****************************************************************************** - * @attention - * - * Copyright (c) 2016-2020 STMicroelectronics. - * All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** -*/ -/* Device specific values */ - -/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */ - -define symbol VECTORS = 79; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */ -define symbol HEAP_SIZE = 0x1000; - -/* Common - Do not change */ - -if (!isdefinedsymbol(MBED_APP_START)) { - define symbol MBED_APP_START = MBED_ROM_START; -} - -if (!isdefinedsymbol(MBED_APP_SIZE)) { - define symbol MBED_APP_SIZE = MBED_ROM_SIZE; -} - -if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) { - /* This value is normally defined by the tools - to 0x1000 for bare metal and 0x400 for RTOS */ - define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400; -} - -/* Round up VECTORS_SIZE to 8 bytes */ -define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7; -define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE; -define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE; - -define memory mem with size = 4G; -define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE]; -define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE]; - -define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { }; -define block HEAP with alignment = 8, size = HEAP_SIZE { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem: MBED_APP_START { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/cmsis_nvic.h index 9d55636da2..38da1db06f 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/cmsis_nvic.h @@ -22,7 +22,9 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x0 // 0 B +// MBED_ROM_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH +// Size is defined in json with "mbed_rom_size" +#error "mbed_rom_size is missing" #endif #if !defined(MBED_RAM_START) @@ -30,7 +32,7 @@ #endif #if !defined(MBED_RAM_SIZE) -#define MBED_RAM_SIZE 0x0 // 0 B +#define MBED_RAM_SIZE 0xC000 // 48 KB #endif #define NVIC_NUM_VECTORS 79 diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/system_clock.c b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/system_clock.c new file mode 100644 index 0000000000..9ff1c76e78 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB15xC/system_clock.c @@ -0,0 +1,119 @@ +/* mbed Microcontroller Library + * Copyright (c) 2019 ARM Limited + * Copyright (c) 2019 STMicroelectronics + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * This file configures the system clock as follows: + *----------------------------------------------------------------------------- + * System clock source | HSE (external 32 MHz clock) + *----------------------------------------------------------------------------- + * SYSCLK(MHz) | 32 + * AHBCLK (MHz) | 32 + * APB1CLK (MHz) | 32 + * APB2CLK (MHz) | 32 + * USB capable | YES + *----------------------------------------------------------------------------- +**/ + +#include "stm32wbxx.h" +#include "mbed_error.h" +#include "stm32wbxx_ll_hsem.h" +#include "otp.h" + + +static void Config_HSE(void) +{ + OTP_ID0_t *p_otp; + + /** + * Read HSE_Tuning from OTP + */ + p_otp = (OTP_ID0_t *) OTP_Read(0); + if (p_otp) { + LL_RCC_HSE_SetCapacitorTuning(p_otp->hse_tuning); + } + + return; +} + + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + __HAL_RCC_HSEM_CLK_ENABLE(); + + /* This prevents the CPU2 (M0+) to configure RCC */ + while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)); + + Config_HSE(); + + /* Initializes the CPU, AHB and APB busses clocks */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + error("HAL_RCC_OscConfig error\n"); + } + + /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2 + | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) { + error("HAL_RCC_ClockConfig error\n"); + } + + /* Initializes the peripherals clocks */ + /* RNG needs to be configured like in M0 core, i.e. with HSI48 */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RNG ; + PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_LSE; + PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE; + PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE; + PeriphClkInitStruct.SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + error("HAL_RCCEx_PeriphCLKConfig error\n"); + } + + LL_PWR_SMPS_SetStartupCurrent(LL_PWR_SMPS_STARTUP_CURRENT_80MA); + LL_PWR_SMPS_SetOutputVoltageLevel(LL_PWR_SMPS_OUTPUT_VOLTAGE_1V40); + // LL_PWR_SMPS_Enable(); + + /* Select HSI as system clock source after Wake Up from Stop mode */ + LL_RCC_SetClkAfterWakeFromStop(LL_RCC_STOP_WAKEUPCLOCK_HSI); + + LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, 0); +} diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_ARM/stm32wb55xg.sct b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_ARM/stm32wb55xg.sct index b1b77343ad..9a60ba3dbb 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_ARM/stm32wb55xg.sct +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_ARM/stm32wb55xg.sct @@ -22,8 +22,9 @@ #endif #if !defined(MBED_APP_SIZE) -; 768KB FLASH // BLE firmware is being flashed strating from @ 0x080C0000 -#define MBED_APP_SIZE 0xC0000 +// MBED_APP_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH +// Size is defined in json with "mbed_rom_size" +#define MBED_APP_SIZE MBED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) @@ -38,7 +39,7 @@ /* Round up VECTORS_SIZE to 8 bytes */ #define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) -; RAM_SIZE = 192KB SRAM (0x30000) + Shared mem +; RAM_SIZE = 192KB SRAM1 (0x30000) + Shared mem (part of SRAM2) LR_IROM1 MBED_APP_START MBED_APP_SIZE { ER_IROM1 MBED_APP_START MBED_APP_SIZE { diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_GCC_ARM/stm32wb55xg.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_GCC_ARM/stm32wb55xg.ld index 158dbefdef..e29ce7789d 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_GCC_ARM/stm32wb55xg.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_GCC_ARM/stm32wb55xg.ld @@ -23,8 +23,9 @@ #endif #if !defined(MBED_APP_SIZE) -/* 768KB FLASH - BLE firmware is being flashed strating from @ 0x080C0000 */ -#define MBED_APP_SIZE 768K +// MBED_APP_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH +// Size is defined in json with "mbed_rom_size" +#define MBED_APP_SIZE MBED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) @@ -36,7 +37,7 @@ /* Round up VECTORS_SIZE to 8 bytes */ #define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) -/* RAM_SIZE = 192KB SRAM (0x30000) + Shared mem */ +/* RAM_SIZE = 192KB SRAM1 (0x30000) + Shared mem (part of SRAM2) */ MEMORY { FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_IAR/stm32wb55xg.icf b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_IAR/stm32wb55xg.icf index e02e5ae57d..a7c7d402d8 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_IAR/stm32wb55xg.icf +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/TOOLCHAIN_IAR/stm32wb55xg.icf @@ -17,7 +17,7 @@ /* Device specific values */ if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } -if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0xC0000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = MBED_ROM_START; } /* [ROM = 768kb = 0xC0000] */ define symbol __intvec_start__ = MBED_APP_START; diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/cmsis_nvic.h index 85808e7bad..e434ab6000 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/cmsis_nvic.h @@ -22,7 +22,9 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x100000 // 1.0 MB +// MBED_ROM_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH +// Size is defined in json with "mbed_rom_size" +#error "mbed_rom_size is missing" #endif #if !defined(MBED_RAM_START) diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TARGET_DISCO_WB5MMG/PinNames.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TARGET_DISCO_WB5MMG/PinNames.h index fe26e9982d..94a74c40d4 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TARGET_DISCO_WB5MMG/PinNames.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TARGET_DISCO_WB5MMG/PinNames.h @@ -127,12 +127,12 @@ typedef enum { ARDUINO_UNO_D7 = PB_2, ARDUINO_UNO_D8 = PD_13, ARDUINO_UNO_D9 = PD_15, - ARDUINO_UNO_D10= PA_4, - ARDUINO_UNO_D11= PA_7, - ARDUINO_UNO_D12= PB_4, - ARDUINO_UNO_D13= PA_1, - ARDUINO_UNO_D14= PA_10, - ARDUINO_UNO_D15= PB_8, + ARDUINO_UNO_D10 = PA_4, + ARDUINO_UNO_D11 = PA_7, + ARDUINO_UNO_D12 = PB_4, + ARDUINO_UNO_D13 = PA_1, + ARDUINO_UNO_D14 = PA_10, + ARDUINO_UNO_D15 = PB_8, #endif // STDIO for console print @@ -186,8 +186,8 @@ typedef enum { // Standardized LED and button names #define LED1 PA_7 // LD4 is a RGB LED connected to a PWM LED driver // TODO -#define BUTTON1 PC_12 -#define BUTTON2 PC_13 +#define BUTTON1 PC_12 +#define BUTTON2 PC_13 #ifdef __cplusplus } diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_ARM/stm32wb5mxg.sct b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_ARM/stm32wb5mxg.sct index fcab08d7d9..9a60ba3dbb 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_ARM/stm32wb5mxg.sct +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_ARM/stm32wb5mxg.sct @@ -22,8 +22,9 @@ #endif #if !defined(MBED_APP_SIZE) -; 768KB FLASH // BLE firmware is being flashed strating from @ 0x080C0000 -#define MBED_APP_SIZE 0xC0000 +// MBED_APP_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH +// Size is defined in json with "mbed_rom_size" +#define MBED_APP_SIZE MBED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) @@ -38,6 +39,7 @@ /* Round up VECTORS_SIZE to 8 bytes */ #define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7) +; RAM_SIZE = 192KB SRAM1 (0x30000) + Shared mem (part of SRAM2) LR_IROM1 MBED_APP_START MBED_APP_SIZE { ER_IROM1 MBED_APP_START MBED_APP_SIZE { diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_GCC_ARM/stm32wb5mxg.ld b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_GCC_ARM/stm32wb5mxg.ld index 158dbefdef..e29ce7789d 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_GCC_ARM/stm32wb5mxg.ld +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_GCC_ARM/stm32wb5mxg.ld @@ -23,8 +23,9 @@ #endif #if !defined(MBED_APP_SIZE) -/* 768KB FLASH - BLE firmware is being flashed strating from @ 0x080C0000 */ -#define MBED_APP_SIZE 768K +// MBED_APP_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH +// Size is defined in json with "mbed_rom_size" +#define MBED_APP_SIZE MBED_ROM_SIZE #endif #if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE) @@ -36,7 +37,7 @@ /* Round up VECTORS_SIZE to 8 bytes */ #define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8) -/* RAM_SIZE = 192KB SRAM (0x30000) + Shared mem */ +/* RAM_SIZE = 192KB SRAM1 (0x30000) + Shared mem (part of SRAM2) */ MEMORY { FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_IAR/stm32wb5mxg.icf b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_IAR/stm32wb5mxg.icf index e02e5ae57d..a7c7d402d8 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_IAR/stm32wb5mxg.icf +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/TOOLCHAIN_IAR/stm32wb5mxg.icf @@ -17,7 +17,7 @@ /* Device specific values */ if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; } -if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0xC0000; } +if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = MBED_ROM_START; } /* [ROM = 768kb = 0xC0000] */ define symbol __intvec_start__ = MBED_APP_START; diff --git a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/cmsis_nvic.h index 85808e7bad..e434ab6000 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/cmsis_nvic.h +++ b/targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB5MxG/cmsis_nvic.h @@ -22,7 +22,9 @@ #endif #if !defined(MBED_ROM_SIZE) -#define MBED_ROM_SIZE 0x100000 // 1.0 MB +// MBED_ROM_SIZE cannot be full ROM size as core M0 FW is using the end of FLASH +// Size is defined in json with "mbed_rom_size" +#error "mbed_rom_size is missing" #endif #if !defined(MBED_RAM_START) diff --git a/targets/TARGET_STM/TARGET_STM32WB/analogin_device.c b/targets/TARGET_STM/TARGET_STM32WB/analogin_device.c index 9ff0c4390e..a8cc37bfda 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/analogin_device.c +++ b/targets/TARGET_STM/TARGET_STM32WB/analogin_device.c @@ -66,12 +66,19 @@ void analogin_init(analogin_t *obj, PinName pin) obj->handle.Init.ContinuousConvMode = DISABLE; // Continuous mode disabled to have only 1 conversion at each conversion trig obj->handle.Init.NbrOfConversion = 1; // Parameter discarded because sequencer is disabled obj->handle.Init.DiscontinuousConvMode = DISABLE; // Parameter discarded because sequencer is disabled - obj->handle.Init.NbrOfDiscConversion = 1; // Parameter discarded because sequencer is disabled obj->handle.Init.ExternalTrigConv = ADC_SOFTWARE_START; // Software start to trig the 1st conversion manually, without external event obj->handle.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; obj->handle.Init.DMAContinuousRequests = DISABLE; obj->handle.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN; // DR register is overwritten with the last conversion result in case of overrun +#if defined (ADC_SUPPORT_2_5_MSPS) + obj->handle.Init.LowPowerAutoPowerOff = DISABLE; + obj->handle.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_79CYCLES_5; + obj->handle.Init.SamplingTimeCommon2 = ADC_SAMPLETIME_160CYCLES_5; + obj->handle.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH; +#else + obj->handle.Init.NbrOfDiscConversion = 1; // Parameter discarded because sequencer is disabled obj->handle.Init.OversamplingMode = DISABLE; // No oversampling +#endif // Enable ADC core clock __HAL_RCC_ADC_CLK_ENABLE(); @@ -96,15 +103,23 @@ uint16_t adc_read(analogin_t *obj) // Configure ADC channel sConfig.Rank = ADC_REGULAR_RANK_1; +#if !defined (ADC_SUPPORT_2_5_MSPS) sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5; sConfig.SingleDiff = ADC_SINGLE_ENDED; sConfig.OffsetNumber = ADC_OFFSET_NONE; sConfig.Offset = 0; +#else + sConfig.SamplingTime = ADC_SAMPLINGTIME_COMMON_1; +#endif switch (obj->channel) { case 0: sConfig.Channel = ADC_CHANNEL_VREFINT; +#if !defined (ADC_SUPPORT_2_5_MSPS) sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; // Minimum ADC sampling time when reading the internal reference voltage is 4us +#else + sConfig.SamplingTime = ADC_SAMPLINGTIME_COMMON_2; +#endif break; case 1: sConfig.Channel = ADC_CHANNEL_1; @@ -156,11 +171,19 @@ uint16_t adc_read(analogin_t *obj) break; case 17: sConfig.Channel = ADC_CHANNEL_TEMPSENSOR; +#if !defined (ADC_SUPPORT_2_5_MSPS) sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; // Minimum ADC sampling time when reading the temperature is 5us +#else + sConfig.SamplingTime = ADC_SAMPLINGTIME_COMMON_2; +#endif break; case 18: sConfig.Channel = ADC_CHANNEL_VBAT; +#if !defined (ADC_SUPPORT_2_5_MSPS) sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5; // Minimum ADC sampling time when reading the VBAT is 12us +#else + sConfig.SamplingTime = ADC_SAMPLINGTIME_COMMON_2; +#endif break; default: return 0; diff --git a/targets/TARGET_STM/TARGET_STM32WB/flash_api.c b/targets/TARGET_STM/TARGET_STM32WB/flash_api.c index 04447ad502..67fee5099c 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/flash_api.c +++ b/targets/TARGET_STM/TARGET_STM32WB/flash_api.c @@ -19,7 +19,6 @@ #if DEVICE_FLASH #include "flash_api.h" -#include "flash_data.h" #include "mbed_critical.h" #include "mbed_assert.h" #include "cmsis.h" @@ -80,7 +79,7 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address) uint32_t cpu1_sem_status = 1; uint32_t cpu2_sem_status = 1; - if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { + if ((address >= (FLASH_BASE + MBED_ROM_SIZE)) || (address < FLASH_BASE)) { return -1; } @@ -179,7 +178,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t cpu1_sem_status = 1; uint32_t cpu2_sem_status = 1; - if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { + if ((address >= (FLASH_BASE + MBED_ROM_SIZE)) || (address < FLASH_BASE)) { return -1; } @@ -267,7 +266,7 @@ int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) { /* considering 1 sector = 1 page */ - if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) { + if ((address >= (FLASH_BASE + MBED_ROM_SIZE)) || (address < FLASH_BASE)) { return MBED_FLASH_INVALID_SIZE; } else { return FLASH_PAGE_SIZE; @@ -301,7 +300,7 @@ uint32_t flash_get_start_address(const flash_t *obj) */ uint32_t flash_get_size(const flash_t *obj) { - return FLASH_SIZE; + return MBED_ROM_SIZE; } uint8_t flash_get_erase_value(const flash_t *obj) diff --git a/targets/TARGET_STM/TARGET_STM32WB/i2c_device.c b/targets/TARGET_STM/TARGET_STM32WB/i2c_device.c new file mode 100755 index 0000000000..b3292c9059 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WB/i2c_device.c @@ -0,0 +1,157 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#include "i2c_device.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "stm32wbxx_ll_rcc.h" + +/* Define I2C Device */ +#if DEVICE_I2C + +/** + * @brief Get I2C clock source frequency according I2C instance used. + * @param i2c I2C instance name. + * @retval I2C clock source frequency in Hz. + */ +uint32_t i2c_get_pclk(I2CName i2c) +{ + uint32_t clocksource; + uint32_t pclk = 0; + if (i2c == I2C_1) { + clocksource = __HAL_RCC_GET_I2C1_SOURCE(); + switch (clocksource) { + case RCC_I2C1CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C1CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C1CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#if defined I2C2_BASE + if (i2c == I2C_2) { + clocksource = __HAL_RCC_GET_I2C2_SOURCE(); + switch (clocksource) { + case RCC_I2C2CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C2CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C2CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif +#if defined I2C3_BASE + else if (i2c == I2C_3) { + clocksource = __HAL_RCC_GET_I2C3_SOURCE(); + switch (clocksource) { + case RCC_I2C3CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C3CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C3CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif + else { + // should not happend + error("I2C: unknown instance"); + } + return pclk; +} +/** + * @} + */ + +/** @defgroup I2C_DEVICE_Exported_Functions I2C_DEVICE Exported Functions + * @{ + */ +/** + * @brief Provide the suitable timing depending on requested frequency + * @param hz Required I2C clock in Hz. + * @retval I2C timing or 0 in case of error. + */ +uint32_t i2c_get_timing(I2CName i2c, int hz) +{ + uint32_t tim; + uint32_t pclk; + + pclk = i2c_get_pclk(i2c); + if (pclk == I2C_PCLK_64M) { + switch (hz) { + case 100000: + tim = TIMING_VAL_64M_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_64M_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_64M_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } + + else if (pclk == I2C_PCLK_32M) { + switch (hz) { + case 100000: + tim = TIMING_VAL_32M_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_32M_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_32M_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } + + else { + /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. + User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. + Enabling this may impact performance */ + MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO); +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + tim = i2c_compute_timing(pclk, hz); +#endif + } + return tim; +} +/** + * @} + */ + +#endif // DEVICE_I2C diff --git a/targets/TARGET_STM/TARGET_STM32WB/i2c_device.h b/targets/TARGET_STM/TARGET_STM32WB/i2c_device.h index 023f8ab9d5..d275089130 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32WB/i2c_device.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2019 STMicroelectronics + * Copyright (c) 2019-2021 STMicroelectronics * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,16 +18,30 @@ #ifndef MBED_I2C_DEVICE_H #define MBED_I2C_DEVICE_H -#include "cmsis.h" +#include "PeripheralNames.h" #ifdef __cplusplus extern "C" { #endif -#ifdef DEVICE_I2C +/* Define I2C Device */ +#if DEVICE_I2C +/* Define IP version */ #define I2C_IP_VERSION_V2 +// Common settings: I2C clock = 64 MHz, Analog filter = ON, Digital filter coefficient = 0 +#define TIMING_VAL_64M_CLK_100KHZ 0x10707DBC // Standard mode with Rise Time = 400ns and Fall Time = 100ns +#define TIMING_VAL_64M_CLK_400KHZ 0x00602173 // Fast mode with Rise Time = 250ns and Fall Time = 100ns +#define TIMING_VAL_64M_CLK_1MHZ 0x00300B29 // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns +#define I2C_PCLK_64M 64000000 // 64 MHz + +// Common settings: I2C clock = 32 MHz, Analog filter = ON, Digital filter coefficient = 0 +#define TIMING_VAL_32M_CLK_100KHZ 0x00707CBB // Standard mode with Rise Time = 400ns and Fall Time = 100ns +#define TIMING_VAL_32M_CLK_400KHZ 0x00300F38 // Fast mode with Rise Time = 250ns and Fall Time = 100ns +#define TIMING_VAL_32M_CLK_1MHZ 0x00100413 // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns +#define I2C_PCLK_32M 32000000 // 32 MHz + #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI) /* Family specific settings for clock source */ @@ -35,48 +49,19 @@ extern "C" { #define I2CAPI_I2C2_CLKSRC RCC_I2C2CLKSOURCE_SYSCLK #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_SYSCLK -/* Provide the suitable timing depending on requested frequency */ -static inline uint32_t get_i2c_timing(int hz) -{ - uint32_t tim = 0; - if (SystemCoreClock == 64000000) { - // Common settings: I2C clock = 64 MHz, Analog filter = ON, Digital filter coefficient = 0 - switch (hz) { - case 100000: - tim = 0x10707DBC; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - tim = 0x00602173; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - tim = 0x00300B29; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - } else if (SystemCoreClock == 32000000) { - // Common settings: I2C clock = 32 MHz, Analog filter = ON, Digital filter coefficient = 0 - switch (hz) { - case 100000: - tim = 0x00707CBB; // Standard mode with Rise Time = 400ns and Fall Time = 100ns - break; - case 400000: - tim = 0x00300F38; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - tim = 0x00100413; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - } - return tim; -} +uint32_t i2c_get_pclk(I2CName i2c); +uint32_t i2c_get_timing(I2CName i2c, int hz); + +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq); +void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t I2C_speed); +uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t I2C_speed); +#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + +#endif // DEVICE_I2C #ifdef __cplusplus } #endif -#endif // DEVICE_I2C - #endif diff --git a/targets/TARGET_STM/TARGET_STM32WB/objects.h b/targets/TARGET_STM/TARGET_STM32WB/objects.h index ee48fe55c8..ead49f7692 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/objects.h +++ b/targets/TARGET_STM/TARGET_STM32WB/objects.h @@ -101,6 +101,9 @@ struct i2c_s { uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32WB/spi_api.c b/targets/TARGET_STM/TARGET_STM32WB/spi_api.c index 853a7e7f6c..7f2b55f776 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/spi_api.c +++ b/targets/TARGET_STM/TARGET_STM32WB/spi_api.c @@ -45,9 +45,11 @@ int spi_get_clock_freq(spi_t *obj) case SPI_1: spi_hz = HAL_RCC_GetPCLK2Freq(); break; +#if defined SPI2_BASE case SPI_2: spi_hz = HAL_RCC_GetPCLK1Freq(); break; +#endif default: error("CLK: SPI instance not set"); break; diff --git a/targets/TARGET_STM/TARGET_STM32WB/stm32wb_ble_update.jpg b/targets/TARGET_STM/TARGET_STM32WB/stm32wb_ble_update.jpg deleted file mode 100644 index bce840fc16..0000000000 Binary files a/targets/TARGET_STM/TARGET_STM32WB/stm32wb_ble_update.jpg and /dev/null differ diff --git a/targets/TARGET_STM/TARGET_STM32WB/us_ticker_data.h b/targets/TARGET_STM/TARGET_STM32WB/us_ticker_data.h index b4bf37f425..42eace2145 100644 --- a/targets/TARGET_STM/TARGET_STM32WB/us_ticker_data.h +++ b/targets/TARGET_STM/TARGET_STM32WB/us_ticker_data.h @@ -1,18 +1,16 @@ /* mbed Microcontroller Library - * Copyright (c) 2019 ARM Limited - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at + * Copyright (c) 2016-2021 STMicroelectronics. + * All rights reserved. * - * http://www.apache.org/licenses/LICENSE-2.0 + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. + ****************************************************************************** */ #ifndef __US_TICKER_DATA_H @@ -26,22 +24,34 @@ extern "C" { #include "stm32wbxx_ll_tim.h" #include "cmsis_nvic.h" +#if defined TIM16_BASE + #define TIM_MST TIM16 #define TIM_MST_IRQ TIM1_UP_TIM16_IRQn #define TIM_MST_RCC __HAL_RCC_TIM16_CLK_ENABLE() #define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM16() - #define TIM_MST_RESET_ON __HAL_RCC_TIM16_FORCE_RESET() #define TIM_MST_RESET_OFF __HAL_RCC_TIM16_RELEASE_RESET() #define TIM_MST_BIT_WIDTH 16 // 16 or 32 -#define TIM_MST_PCLK 2 // Select the peripheral clock number (1 or 2) +#else +#define TIM_MST TIM2 +#define TIM_MST_IRQ TIM2_IRQn +#define TIM_MST_RCC __HAL_RCC_TIM2_CLK_ENABLE() +#define TIM_MST_DBGMCU_FREEZE __HAL_DBGMCU_FREEZE_TIM2() +#define TIM_MST_RESET_ON __HAL_RCC_TIM2_FORCE_RESET() +#define TIM_MST_RESET_OFF __HAL_RCC_TIM2_RELEASE_RESET() + +#define TIM_MST_BIT_WIDTH 32 // 16 or 32 + +#endif + +#define TIM_MST_PCLK 2 // Select the peripheral clock number (1 or 2) #ifdef __cplusplus } #endif #endif // __US_TICKER_DATA_H - diff --git a/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt index 36c47064a1..1b8e784872 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt @@ -12,6 +12,7 @@ target_sources(mbed-stm32wl analogout_device.c flash_api.c gpio_irq_device.c + i2c_device.c pwmout_device.c serial_device.c spi_api.c diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/PeripheralNames.h index 3a95d6d25d..3971fb445f 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/PeripheralNames.h +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/PeripheralNames.h @@ -35,7 +35,7 @@ typedef enum { typedef enum { UART_1 = (int)USART1_BASE, - UART_2 = (int)USART2_BASE, + UART_2 = (int)USART2_BASE, LPUART_1 = (int)LPUART1_BASE } UARTName; diff --git a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/system_clock.c b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/system_clock.c index ae2309a02a..70d3920250 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32WL/TARGET_STM32WL55xC/TARGET_NUCLEO_WL55JC/system_clock.c @@ -39,31 +39,31 @@ MBED_WEAK void SetSysClock(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Configure the main internal regulator output voltage - */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the CPU, AHB and APB busses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - MBED_ASSERT(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK); - /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3|RCC_CLOCKTYPE_HCLK - |RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 - |RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1; - MBED_ASSERT(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK); - /* Peripheral clock enable */ + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Initializes the CPU, AHB and APB busses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + MBED_ASSERT(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK); + /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3 | RCC_CLOCKTYPE_HCLK + | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 + | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1; + MBED_ASSERT(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK); + /* Peripheral clock enable */ } diff --git a/targets/TARGET_STM/TARGET_STM32WL/i2c_device.c b/targets/TARGET_STM/TARGET_STM32WL/i2c_device.c new file mode 100755 index 0000000000..118f9e278c --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32WL/i2c_device.c @@ -0,0 +1,142 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#include "i2c_device.h" +#include "mbed_assert.h" +#include "mbed_error.h" +#include "stm32wlxx_ll_rcc.h" + +/* Define I2C Device */ +#if DEVICE_I2C + +/** + * @brief Get I2C clock source frequency according I2C instance used. + * @param i2c I2C instance name. + * @retval I2C clock source frequency in Hz. + */ +uint32_t i2c_get_pclk(I2CName i2c) +{ + uint32_t clocksource; + uint32_t pclk = 0; + if (i2c == I2C_1) { + clocksource = __HAL_RCC_GET_I2C1_SOURCE(); + switch (clocksource) { + case RCC_I2C1CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C1CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C1CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#if defined I2C2_BASE + if (i2c == I2C_2) { + clocksource = __HAL_RCC_GET_I2C2_SOURCE(); + switch (clocksource) { + case RCC_I2C2CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C2CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C2CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif +#if defined I2C3_BASE + else if (i2c == I2C_3) { + clocksource = __HAL_RCC_GET_I2C3_SOURCE(); + switch (clocksource) { + case RCC_I2C3CLKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + + case RCC_I2C3CLKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + + case RCC_I2C3CLKSOURCE_HSI: + pclk = HSI_VALUE; + break; + } + } +#endif + else { + // should not happend + error("I2C: unknown instance"); + } + + return pclk; +} +/** + * @} + */ + +/** @defgroup I2C_DEVICE_Exported_Functions I2C_DEVICE Exported Functions + * @{ + */ +/** + * @brief Provide the suitable timing depending on requested frequency + * @param hz Required I2C clock in Hz. + * @retval I2C timing or 0 in case of error. + */ +uint32_t i2c_get_timing(I2CName i2c, int hz) +{ + uint32_t tim; + uint32_t pclk; + + pclk = i2c_get_pclk(i2c); + if (pclk == I2C_PCLK_DEF) { + switch (hz) { + case 100000: + tim = TIMING_VAL_DEFAULT_CLK_100KHZ; + break; + case 400000: + tim = TIMING_VAL_DEFAULT_CLK_400KHZ; + break; + case 1000000: + tim = TIMING_VAL_DEFAULT_CLK_1MHZ; + break; + default: + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + break; + } + } + + else { + /* If MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO assert is triggered. + User needs to enable I2C_TIMING_VALUE_ALGO in target.json for specific target. + Enabling this may impact performance */ + MBED_ASSERT(MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO); +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + tim = i2c_compute_timing(pclk, hz); +#endif + } + return tim; +} +/** + * @} + */ + +#endif // DEVICE_I2C diff --git a/targets/TARGET_STM/TARGET_STM32WL/i2c_device.h b/targets/TARGET_STM/TARGET_STM32WL/i2c_device.h index eedf470733..a84d941f89 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/i2c_device.h +++ b/targets/TARGET_STM/TARGET_STM32WL/i2c_device.h @@ -16,16 +16,24 @@ #ifndef MBED_I2C_DEVICE_H #define MBED_I2C_DEVICE_H -#include "cmsis.h" +#include "PeripheralNames.h" #ifdef __cplusplus extern "C" { #endif -#ifdef DEVICE_I2C +/* Define I2C Device */ +#if DEVICE_I2C +/* Define IP version */ #define I2C_IP_VERSION_V2 +// Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0 +#define TIMING_VAL_DEFAULT_CLK_100KHZ 0x20E03F53 // Standard mode with Rise Time = 640ns and Fall Time = 20ns +#define TIMING_VAL_DEFAULT_CLK_400KHZ 0x20500817 // Fast mode with Rise Time = 250ns and Fall Time = 100ns +#define TIMING_VAL_DEFAULT_CLK_1MHZ 0x00500A18 // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns +#define I2C_PCLK_DEF 48000000 // 48 MHz + #define I2C_IT_ALL (I2C_IT_ERRI|I2C_IT_TCI|I2C_IT_STOPI|I2C_IT_NACKI|I2C_IT_ADDRI|I2C_IT_RXI|I2C_IT_TXI) /* Family specific settings for clock source */ @@ -33,32 +41,19 @@ extern "C" { #define I2CAPI_I2C2_CLKSRC RCC_I2C2CLKSOURCE_SYSCLK #define I2CAPI_I2C3_CLKSRC RCC_I2C3CLKSOURCE_SYSCLK -/* Provide the suitable timing depending on requested frequency */ -static inline uint32_t get_i2c_timing(int hz) -{ - uint32_t tim = 0; +uint32_t i2c_get_pclk(I2CName i2c); +uint32_t i2c_get_timing(I2CName i2c, int hz); - // Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0 - switch (hz) { - case 100000: - tim = 0x20E03F53; // Standard mode with Rise Time = 640ns and Fall Time = 20ns - break; - case 400000: - tim = 0x20500817; // Fast mode with Rise Time = 250ns and Fall Time = 100ns - break; - case 1000000: - tim = 0x00500A18; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns - break; - default: - break; - } - return tim; -} +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq); +void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t I2C_speed); +uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t I2C_speed); +#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + +#endif // DEVICE_I2C #ifdef __cplusplus } #endif -#endif // DEVICE_I2C - #endif diff --git a/targets/TARGET_STM/TARGET_STM32WL/objects.h b/targets/TARGET_STM/TARGET_STM32WL/objects.h index 4116fec5ef..72270cd4c2 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/objects.h +++ b/targets/TARGET_STM/TARGET_STM32WL/objects.h @@ -104,6 +104,9 @@ struct i2c_s { uint8_t slave; volatile uint8_t pending_slave_tx_master_rx; volatile uint8_t pending_slave_rx_maxter_tx; + uint8_t *slave_rx_buffer; + volatile uint8_t slave_rx_buffer_size; + volatile uint8_t slave_rx_count; #endif #if DEVICE_I2C_ASYNCH uint32_t address; diff --git a/targets/TARGET_STM/TARGET_STM32WL/serial_device.c b/targets/TARGET_STM/TARGET_STM32WL/serial_device.c index b2377cb628..ed6023fc46 100644 --- a/targets/TARGET_STM/TARGET_STM32WL/serial_device.c +++ b/targets/TARGET_STM/TARGET_STM32WL/serial_device.c @@ -125,7 +125,7 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); // Check if RxIrq is disabled too if ((huart->Instance->CR1 & USART_CR1_RXNEIE_RXFNEIE) == 0) { - + all_disabled = 1; } } diff --git a/targets/TARGET_STM/USBPhy_STM32.cpp b/targets/TARGET_STM/USBPhy_STM32.cpp index 20eaa38278..1810bb6e29 100644 --- a/targets/TARGET_STM/USBPhy_STM32.cpp +++ b/targets/TARGET_STM/USBPhy_STM32.cpp @@ -250,13 +250,13 @@ void USBPhyHw::init(USBPhyEvents *events) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); - #ifdef __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE - __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE(); - #endif - #ifdef __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE - __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE(); - #endif - +#ifdef __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE + __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE(); +#endif +#ifdef __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE + __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE(); +#endif + map = PinMap_USB_HS; #elif (MBED_CONF_TARGET_USB_SPEED == USE_USB_OTG_FS) @@ -267,13 +267,13 @@ void USBPhyHw::init(USBPhyEvents *events) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - #ifdef __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE - __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE(); - #endif - #ifdef __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE - __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE(); - #endif - +#ifdef __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE + __HAL_RCC_USB1_OTG_FS_ULPI_CLK_SLEEP_DISABLE(); +#endif +#ifdef __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE + __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE(); +#endif + map = PinMap_USB_FS; #elif (MBED_CONF_TARGET_USB_SPEED == USE_USB_NO_OTG) @@ -317,6 +317,7 @@ void USBPhyHw::init(USBPhyEvents *events) hpcd.State = HAL_PCD_STATE_RESET; HAL_StatusTypeDef ret = HAL_PCD_Init(&hpcd); MBED_ASSERT(ret == HAL_OK); + __HAL_PCD_ENABLE(&hpcd); // Configure FIFOs #if (MBED_CONF_TARGET_USB_SPEED == USE_USB_NO_OTG) diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c index 3893735d94..eae7753abe 100644 --- a/targets/TARGET_STM/can_api.c +++ b/targets/TARGET_STM/can_api.c @@ -142,13 +142,13 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz // !When the sample point should be lower than 50%, this must be changed to // !IS_FDCAN_NOMINAL_TSEG2(ntq/nominalPrescaler), since // NTSEG2 and SJW max values are lower. For now the sample point is fix @75% - while (!IS_FDCAN_NOMINAL_TSEG1(ntq/nominalPrescaler)){ + while (!IS_FDCAN_NOMINAL_TSEG1(ntq / nominalPrescaler)) { nominalPrescaler ++; - if (!IS_FDCAN_NOMINAL_PRESCALER(nominalPrescaler)){ + if (!IS_FDCAN_NOMINAL_PRESCALER(nominalPrescaler)) { error("Could not determine good nominalPrescaler. Bad clock value\n"); } } - ntq = ntq/nominalPrescaler; + ntq = ntq / nominalPrescaler; obj->CanHandle.Init.FrameFormat = FDCAN_FRAME_CLASSIC; obj->CanHandle.Init.Mode = FDCAN_MODE_NORMAL; @@ -163,12 +163,23 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz obj->CanHandle.Init.DataSyncJumpWidth = 0x1; // Not used - only in FDCAN obj->CanHandle.Init.DataTimeSeg1 = 0x1; // Not used - only in FDCAN obj->CanHandle.Init.DataTimeSeg2 = 0x1; // Not used - only in FDCAN -#ifndef TARGET_STM32G4 +#ifdef TARGET_STM32H7 + /* Message RAM offset is only supported in STM32H7 platforms of supported FDCAN platforms */ obj->CanHandle.Init.MessageRAMOffset = 0; + + /* The number of Standard and Extended ID filters are initialized to the maximum possile extent + * for STM32H7 platforms + */ + obj->CanHandle.Init.StdFiltersNbr = 128; // to be aligned with the handle parameter in can_filter + obj->CanHandle.Init.ExtFiltersNbr = 128; // to be aligned with the handle parameter in can_filter +#else + /* The number of Standard and Extended ID filters are initialized to the maximum possile extent + * for STM32G0x1, STM32G4 and STM32L5 platforms + */ + obj->CanHandle.Init.StdFiltersNbr = 28; // to be aligned with the handle parameter in can_filter + obj->CanHandle.Init.ExtFiltersNbr = 8; // to be aligned with the handle parameter in can_filter #endif - obj->CanHandle.Init.StdFiltersNbr = 1; // to be aligned with the handle parameter in can_filter - obj->CanHandle.Init.ExtFiltersNbr = 1; // to be aligned with the handle parameter in can_filter -#ifndef TARGET_STM32G4 +#ifdef TARGET_STM32H7 obj->CanHandle.Init.RxFifo0ElmtsNbr = 8; obj->CanHandle.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_8; obj->CanHandle.Init.RxFifo1ElmtsNbr = 0; @@ -180,7 +191,7 @@ static void _can_init_freq_direct(can_t *obj, const can_pinmap_t *pinmap, int hz obj->CanHandle.Init.TxFifoQueueElmtsNbr = 3; #endif obj->CanHandle.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION; -#ifndef TARGET_STM32G4 +#ifdef TARGET_STM32H7 obj->CanHandle.Init.TxElmtSize = FDCAN_DATA_BYTES_8; #endif can_internal_init(obj); @@ -298,13 +309,13 @@ int can_frequency(can_t *obj, int f) // !When the sample point should be lower than 50%, this must be changed to // !IS_FDCAN_DATA_TSEG2(ntq/nominalPrescaler), since // NTSEG2 and SJW max values are lower. For now the sample point is fix @75% - while (!IS_FDCAN_DATA_TSEG1(ntq/nominalPrescaler)){ + while (!IS_FDCAN_DATA_TSEG1(ntq / nominalPrescaler)) { nominalPrescaler ++; - if (!IS_FDCAN_NOMINAL_PRESCALER(nominalPrescaler)){ + if (!IS_FDCAN_NOMINAL_PRESCALER(nominalPrescaler)) { error("Could not determine good nominalPrescaler. Bad clock value\n"); } } - ntq = ntq/nominalPrescaler; + ntq = ntq / nominalPrescaler; obj->CanHandle.Init.NominalPrescaler = nominalPrescaler; obj->CanHandle.Init.NominalTimeSeg1 = ntq * 0.75; // Phase_segment_1 @@ -329,20 +340,18 @@ int can_frequency(can_t *obj, int f) */ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) { - UNUSED(handle); // Not supported yet (seems to be a used in read function?) - FDCAN_FilterTypeDef sFilterConfig = {0}; if (format == CANStandard) { sFilterConfig.IdType = FDCAN_STANDARD_ID; - sFilterConfig.FilterIndex = 0; + sFilterConfig.FilterIndex = handle; sFilterConfig.FilterType = FDCAN_FILTER_MASK; sFilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; sFilterConfig.FilterID1 = id; sFilterConfig.FilterID2 = mask; } else if (format == CANExtended) { sFilterConfig.IdType = FDCAN_EXTENDED_ID; - sFilterConfig.FilterIndex = 0; + sFilterConfig.FilterIndex = handle; sFilterConfig.FilterType = FDCAN_FILTER_MASK; sFilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0; sFilterConfig.FilterID1 = id; @@ -391,7 +400,7 @@ int can_write(can_t *obj, CAN_Message msg, int cc) int can_read(can_t *obj, CAN_Message *msg, int handle) { - UNUSED(handle); // Not supported yet (seems to be a handle to a filter configuration?) + UNUSED(handle); // Not supported, RXFIFO0 is set default by can_filter and cannot be changed. if (HAL_FDCAN_GetRxFifoFillLevel(&obj->CanHandle, FDCAN_RX_FIFO0) == 0) { return 0; // No message arrived @@ -596,7 +605,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) #ifndef TARGET_STM32G4 interrupts = FDCAN_IT_RX_BUFFER_NEW_MESSAGE; #else - interrupts = FDCAN_IT_RX_FIFO0_NEW_MESSAGE; + interrupts = FDCAN_IT_RX_FIFO0_NEW_MESSAGE; #endif break; case IRQ_ERROR: @@ -612,7 +621,16 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) } if (enable) { - HAL_FDCAN_ActivateNotification(&obj->CanHandle, interrupts, 0); + /* The TXBTIE register controls the TX complete interrupt in FDCAN + * and is only used in case of TX interrupts, Hence in case of enabling the + * TX interrupts the bufferIndexes of TXBTIE are to be set */ +#ifdef TARGET_STM32H7 + // TXBTIE for STM32H7 is 2 bytes long + HAL_FDCAN_ActivateNotification(&obj->CanHandle, interrupts, 0xFFFF); +#else + //TXBTIE for rest supported FDCAN Platforms(STM32G0x1, STM32G4 and STM32L5) is 3 bits. + HAL_FDCAN_ActivateNotification(&obj->CanHandle, interrupts, 0x07); +#endif } else { HAL_FDCAN_DeactivateNotification(&obj->CanHandle, interrupts); } @@ -646,8 +664,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) #include #include -#define ENABLED true -#define DISABLED false +#define DEFAULT_RXFIFO 0 // default rx fifo for can by hardware is FIFO0 static uint32_t can_irq_ids[CAN_NUM] = {0}; static can_irq_handler irq_handler; @@ -961,8 +978,8 @@ int can_write(can_t *obj, CAN_Message msg, int cc) int can_read(can_t *obj, CAN_Message *msg, int handle) { - //handle is the FIFO number - + //FIFO selection cannot be controlled by software for STM32, default FIFO is 0, hence handle is not used + int rxfifo_default = DEFAULT_RXFIFO; CAN_TypeDef *can = obj->CanHandle.Instance; // check FPM0 which holds the pending message count in FIFO 0 @@ -972,36 +989,30 @@ int can_read(can_t *obj, CAN_Message *msg, int handle) } /* Get the Id */ - msg->format = (CANFormat)(((uint8_t)0x04 & can->sFIFOMailBox[handle].RIR) >> 2); + msg->format = (CANFormat)(((uint8_t)0x04 & can->sFIFOMailBox[rxfifo_default].RIR) >> 2); if (!msg->format) { - msg->id = (uint32_t)0x000007FF & (can->sFIFOMailBox[handle].RIR >> 21); + msg->id = (uint32_t)0x000007FF & (can->sFIFOMailBox[rxfifo_default].RIR >> 21); } else { - msg->id = (uint32_t)0x1FFFFFFF & (can->sFIFOMailBox[handle].RIR >> 3); + msg->id = (uint32_t)0x1FFFFFFF & (can->sFIFOMailBox[rxfifo_default].RIR >> 3); } - msg->type = (CANType)(((uint8_t)0x02 & can->sFIFOMailBox[handle].RIR) >> 1); + msg->type = (CANType)(((uint8_t)0x02 & can->sFIFOMailBox[rxfifo_default].RIR) >> 1); /* Get the DLC */ - msg->len = (uint8_t)0x0F & can->sFIFOMailBox[handle].RDTR; + msg->len = (uint8_t)0x0F & can->sFIFOMailBox[rxfifo_default].RDTR; /* Get the FMI */ - // msg->FMI = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDTR >> 8); + // msg->FMI = (uint8_t)0xFF & (can->sFIFOMailBox[rxfifo_default].RDTR >> 8); /* Get the data field */ - msg->data[0] = (uint8_t)0xFF & can->sFIFOMailBox[handle].RDLR; - msg->data[1] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 8); - msg->data[2] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 16); - msg->data[3] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDLR >> 24); - msg->data[4] = (uint8_t)0xFF & can->sFIFOMailBox[handle].RDHR; - msg->data[5] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 8); - msg->data[6] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 16); - msg->data[7] = (uint8_t)0xFF & (can->sFIFOMailBox[handle].RDHR >> 24); + msg->data[0] = (uint8_t)0xFF & can->sFIFOMailBox[rxfifo_default].RDLR; + msg->data[1] = (uint8_t)0xFF & (can->sFIFOMailBox[rxfifo_default].RDLR >> 8); + msg->data[2] = (uint8_t)0xFF & (can->sFIFOMailBox[rxfifo_default].RDLR >> 16); + msg->data[3] = (uint8_t)0xFF & (can->sFIFOMailBox[rxfifo_default].RDLR >> 24); + msg->data[4] = (uint8_t)0xFF & can->sFIFOMailBox[rxfifo_default].RDHR; + msg->data[5] = (uint8_t)0xFF & (can->sFIFOMailBox[rxfifo_default].RDHR >> 8); + msg->data[6] = (uint8_t)0xFF & (can->sFIFOMailBox[rxfifo_default].RDHR >> 16); + msg->data[7] = (uint8_t)0xFF & (can->sFIFOMailBox[rxfifo_default].RDHR >> 24); /* Release the FIFO */ - if (handle == CAN_FIFO0) { - /* Release FIFO0 */ - can->RF0R |= CAN_RF0R_RFOM0; - } else { /* FIFONumber == CAN_FIFO1 */ - /* Release FIFO1 */ - can->RF1R |= CAN_RF1R_RFOM1; - } + can->RF0R |= CAN_RF0R_RFOM0; if(obj->rxIrqStatus == ENABLED) { __HAL_CAN_ENABLE_IT(&obj->CanHandle, CAN_IT_FMP0); @@ -1112,7 +1123,7 @@ int can_mode(can_t *obj, CanMode mode) int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle) { int success = 0; - + // filter for CANAny format cannot be configured for STM32 if ((format == CANStandard) || (format == CANExtended)) { CAN_FilterConfTypeDef sFilterConfig; @@ -1136,10 +1147,11 @@ int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t sFilterConfig.FilterActivation = ENABLE; sFilterConfig.BankNumber = 14; - if (HAL_CAN_ConfigFilter(&obj->CanHandle, &sFilterConfig) == HAL_OK) - { + if (HAL_CAN_ConfigFilter(&obj->CanHandle, &sFilterConfig) == HAL_OK) { success = 1; } + } else if (format == CANAny) { + success = 0; // filter for CANAny is not supported by STM32, return a failure } return success; diff --git a/targets/TARGET_STM/device.h b/targets/TARGET_STM/device.h index 643ed21d43..a2fd83c54e 100644 --- a/targets/TARGET_STM/device.h +++ b/targets/TARGET_STM/device.h @@ -37,4 +37,11 @@ #include "objects.h" +#if DEVICE_USTICKER +#include "us_ticker_defines.h" +#endif +#if DEVICE_LPTICKER +#include "lp_ticker_defines.h" +#endif + #endif diff --git a/targets/TARGET_STM/gpio_api.c b/targets/TARGET_STM/gpio_api.c index 448a1cb3c9..00420528b6 100644 --- a/targets/TARGET_STM/gpio_api.c +++ b/targets/TARGET_STM/gpio_api.c @@ -136,21 +136,6 @@ void gpio_init(gpio_t *obj, PinName pin) // Enable GPIO clock GPIO_TypeDef *gpio = Set_GPIO_Clock(port_index); -#if defined(ALTC) - if (pin == PA_0C) { - HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PA0, SYSCFG_SWITCH_PA0_CLOSE); - } - if (pin == PA_1C) { - HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PA1, SYSCFG_SWITCH_PA1_CLOSE); - } - if (pin == PC_2C) { - HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC2, SYSCFG_SWITCH_PC2_CLOSE); - } - if (pin == PC_3C) { - HAL_SYSCFG_AnalogSwitchConfig(SYSCFG_SWITCH_PC3, SYSCFG_SWITCH_PC3_CLOSE); - } -#endif /* ALTC */ - // Fill GPIO object structure for future use obj->mask = gpio_set(pin); obj->gpio = gpio; diff --git a/targets/TARGET_STM/hal_tick_overrides.c b/targets/TARGET_STM/hal_tick_overrides.c index c12c84df8e..f12f79da59 100644 --- a/targets/TARGET_STM/hal_tick_overrides.c +++ b/targets/TARGET_STM/hal_tick_overrides.c @@ -71,7 +71,7 @@ uint32_t HAL_GetTick() prev_tick_remainder = elapsed_time % 1000; } total_ticks += elapsed_ticks; - + core_util_critical_section_exit(); return total_ticks; } diff --git a/targets/TARGET_STM/i2c_api.c b/targets/TARGET_STM/i2c_api.c index 257a345aad..e4ace431e2 100644 --- a/targets/TARGET_STM/i2c_api.c +++ b/targets/TARGET_STM/i2c_api.c @@ -1,6 +1,6 @@ /* mbed Microcontroller Library ******************************************************************************* - * Copyright (c) 2015, STMicroelectronics + * Copyright (c) 2015-2021, STMicroelectronics * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -43,6 +43,117 @@ #include "mbed_error.h" #include "platform/mbed_power_mgmt.h" +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +/** @defgroup I2C_DEVICE_Private_Constants I2C_DEVICE Private Constants + * @{ + */ +#ifndef I2C_VALID_TIMING_NBR +#define I2C_VALID_TIMING_NBR 128U +#endif +#define I2C_SPEED_FREQ_STANDARD 0U /* 100 kHz */ +#define I2C_SPEED_FREQ_FAST 1U /* 400 kHz */ +#define I2C_SPEED_FREQ_FAST_PLUS 2U /* 1 MHz */ +#define I2C_ANALOG_FILTER_DELAY_MIN 50U /* ns */ +#define I2C_ANALOG_FILTER_DELAY_MAX 260U /* ns */ +#define I2C_USE_ANALOG_FILTER 1U +#define I2C_DIGITAL_FILTER_COEF 0U +#define I2C_PRESC_MAX 16U +#define I2C_SCLDEL_MAX 16U +#define I2C_SDADEL_MAX 16U +#define I2C_SCLH_MAX 256U +#define I2C_SCLL_MAX 256U +#define SEC2NSEC 1000000000UL +/** + * @} + */ + + +/** @defgroup I2C_DEVICE_Private_Types I2C_DEVICE Private Types + * @{ + */ +typedef struct { + uint32_t freq; /* Frequency in Hz */ + uint32_t freq_min; /* Minimum frequency in Hz */ + uint32_t freq_max; /* Maximum frequency in Hz */ + uint32_t hddat_min; /* Minimum data hold time in ns */ + uint32_t vddat_max; /* Maximum data valid time in ns */ + uint32_t sudat_min; /* Minimum data setup time in ns */ + uint32_t lscl_min; /* Minimum low period of the SCL clock in ns */ + uint32_t hscl_min; /* Minimum high period of SCL clock in ns */ + uint32_t trise; /* Rise time in ns */ + uint32_t tfall; /* Fall time in ns */ + uint32_t dnf; /* Digital noise filter coefficient */ +} I2C_Charac_t; + +typedef struct { + uint32_t presc; /* Timing prescaler */ + uint32_t tscldel; /* SCL delay */ + uint32_t tsdadel; /* SDA delay */ + uint32_t sclh; /* SCL high period */ + uint32_t scll; /* SCL low period */ +} I2C_Timings_t; +/** + * @} + */ + +/** @defgroup I2C_DEVICE_Private_Constants I2C_DEVICE Private Constants + * @{ + */ +static const I2C_Charac_t I2C_Charac[] = { + [I2C_SPEED_FREQ_STANDARD] = + { + .freq = 100000, + .freq_min = 80000, + .freq_max = 120000, + .hddat_min = 0, + .vddat_max = 3450, + .sudat_min = 250, + .lscl_min = 4700, + .hscl_min = 4000, + .trise = 640, + .tfall = 20, + .dnf = I2C_DIGITAL_FILTER_COEF, + }, + [I2C_SPEED_FREQ_FAST] = + { + .freq = 400000, + .freq_min = 320000, + .freq_max = 480000, + .hddat_min = 0, + .vddat_max = 900, + .sudat_min = 100, + .lscl_min = 1300, + .hscl_min = 600, + .trise = 250, + .tfall = 100, + .dnf = I2C_DIGITAL_FILTER_COEF, + }, + [I2C_SPEED_FREQ_FAST_PLUS] = + { + .freq = 1000000, + .freq_min = 800000, + .freq_max = 1200000, + .hddat_min = 0, + .vddat_max = 450, + .sudat_min = 50, + .lscl_min = 500, + .hscl_min = 260, + .trise = 60, + .tfall = 100, + .dnf = I2C_DIGITAL_FILTER_COEF, + }, +}; +/** + * @} + */ + +/** @defgroup I2C_DEVICE_Private_Variables I2C_DEVICE Private Variables +* @{ +*/ +static I2C_Timings_t I2c_valid_timing[I2C_VALID_TIMING_NBR]; +static uint32_t I2c_valid_timing_nbr = 0; +#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + #ifndef DEBUG_STDIO # define DEBUG_STDIO 0 #endif @@ -86,6 +197,14 @@ static I2C_HandleTypeDef *i2c_handles[I2C_NUM]; #define FLAG_TIMEOUT ((int)0x1000) #endif +#ifdef I2C_IP_VERSION_V1 +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +#endif + +#define SLAVE_MODE_RECEIVE 1 +#define SLAVE_MODE_LISTEN 2 +#define DEFAULT_SLAVE_MODE SLAVE_MODE_LISTEN + /* Declare i2c_init_internal to be used in this file */ void i2c_init_internal(i2c_t *obj, const i2c_pinmap_t *pinmap); @@ -480,9 +599,6 @@ void i2c_frequency(i2c_t *obj, int hz) handle->Init.DutyCycle = I2C_DUTYCYCLE_2; #endif #ifdef I2C_IP_VERSION_V2 - /* Only predefined timing for below frequencies are supported */ - MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); - // Enable the Fast Mode Plus capability if (hz == 1000000) { #if defined(I2C1_BASE) && defined(I2C_FASTMODEPLUS_I2C1) // sometimes I2C_FASTMODEPLUS_I2Cx is define even if not supported by the chip @@ -541,6 +657,12 @@ void i2c_frequency(i2c_t *obj, int hz) __HAL_RCC_I2C4_CONFIG(I2CAPI_I2C4_CLKSRC); } #endif +#ifdef I2C_IP_VERSION_V2 +/* Only predefined timing for below frequencies are supported */ + MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000)); + /* Calculates I2C timing value with respect to I2C input clock and I2C bus frequency */ + handle->Init.Timing = i2c_get_timing(obj_s->i2c, hz); +#endif #if defined(DUAL_CORE) && (TARGET_STM32H7) LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT); #endif /* DUAL_CORE */ @@ -550,14 +672,6 @@ void i2c_frequency(i2c_t *obj, int hz) HAL_I2CEx_ConfigAnalogFilter(handle, I2C_ANALOGFILTER_ENABLE); #endif -#ifdef I2C_IP_VERSION_V2 -#ifdef TARGET_STM32H7 - handle->Init.Timing = get_i2c_timing(obj_s->i2c, hz); -#else - handle->Init.Timing = get_i2c_timing(hz); -#endif -#endif - // I2C configuration handle->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; @@ -1057,7 +1171,9 @@ void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) /* Get object ptr based on handler ptr */ i2c_t *obj = get_i2c_obj(hi2c); struct i2c_s *obj_s = I2C_S(obj); - +#ifdef I2C_IP_VERSION_V1 + hi2c->PreviousState = I2C_STATE_NONE; +#endif /* Set event flag */ obj_s->event = I2C_EVENT_TRANSFER_COMPLETE; } @@ -1067,10 +1183,10 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) /* Get object ptr based on handler ptr */ i2c_t *obj = get_i2c_obj(hi2c); struct i2c_s *obj_s = I2C_S(obj); + I2C_HandleTypeDef *handle = &(obj_s->handle); uint32_t event_code = 0; #if DEVICE_I2CSLAVE - I2C_HandleTypeDef *handle = &(obj_s->handle); uint32_t address = 0; /* Store address to handle it after reset */ if (obj_s->slave) { @@ -1091,7 +1207,7 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) #if DEVICE_I2CSLAVE /* restore slave address */ if (address != 0) { - obj_s->slave = 1; + obj_s->slave = DEFAULT_SLAVE_MODE; i2c_slave_address(obj, 0, address, 0); } #endif @@ -1143,7 +1259,7 @@ void i2c_slave_mode(i2c_t *obj, int enable_slave) I2C_HandleTypeDef *handle = &(obj_s->handle); if (enable_slave) { - obj_s->slave = 1; + obj_s->slave = DEFAULT_SLAVE_MODE; HAL_I2C_EnableListen_IT(handle); } else { obj_s->slave = 0; @@ -1187,11 +1303,28 @@ void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *I2cHandle) /* Get object ptr based on handler ptr */ i2c_t *obj = get_i2c_obj(I2cHandle); struct i2c_s *obj_s = I2C_S(obj); - obj_s->pending_slave_rx_maxter_tx = 0; + + if (obj_s->slave == SLAVE_MODE_LISTEN) { + obj_s->slave_rx_count++; + if (obj_s->slave_rx_count < obj_s->slave_rx_buffer_size){ + HAL_I2C_Slave_Seq_Receive_IT(I2cHandle, &(obj_s->slave_rx_buffer[obj_s->slave_rx_count]), 1, I2C_NEXT_FRAME); + } else { + obj_s->pending_slave_rx_maxter_tx = 0; + } + } else { + obj_s->pending_slave_rx_maxter_tx = 0; + } } void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) { + i2c_t *obj = get_i2c_obj(hi2c); + struct i2c_s *obj_s = I2C_S(obj); + + if (obj_s->slave == SLAVE_MODE_LISTEN) { + obj_s->pending_slave_rx_maxter_tx = 0; + } + /* restart listening for master requests */ HAL_I2C_EnableListen_IT(hi2c); } @@ -1220,18 +1353,34 @@ int i2c_slave_read(i2c_t *obj, char *data, int length) int count = 0; int ret = 0; uint32_t timeout = 0; + int _length = 0; + + if (obj_s->slave == SLAVE_MODE_LISTEN) { + /* We don't know in advance how many bytes will be sent by master so + * we'll fetch one by one until master ends the sequence */ + _length = 1; + obj_s->slave_rx_buffer_size = length; + obj_s->slave_rx_count = 0; + obj_s->slave_rx_buffer = (uint8_t*)data; + } else { + _length = length; + } /* Always use I2C_NEXT_FRAME as slave will just adapt to master requests */ - ret = HAL_I2C_Slave_Seq_Receive_IT(handle, (uint8_t *) data, length, I2C_NEXT_FRAME); + ret = HAL_I2C_Slave_Seq_Receive_IT(handle, (uint8_t *) data, _length, I2C_NEXT_FRAME); if (ret == HAL_OK) { - timeout = BYTE_TIMEOUT_US * (length + 1); + timeout = BYTE_TIMEOUT_US * (_length + 1); while (obj_s->pending_slave_rx_maxter_tx && (--timeout != 0)) { wait_us(1); } if (timeout != 0) { - count = length; + if (obj_s->slave == SLAVE_MODE_LISTEN) { + count = obj_s->slave_rx_count; + } else { + count = _length; + } } else { DEBUG_PRINTF("TIMEOUT or error in i2c_slave_read\r\n"); } @@ -1406,6 +1555,186 @@ void i2c_abort_asynch(i2c_t *obj) HAL_I2C_Master_Abort_IT(handle, Dummy_DevAddress); } +#if MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO +/** + * @brief Calculate SCLL and SCLH and find best configuration. + * @param clock_src_freq I2C source clock in HZ. + * @param I2C_speed I2C frequency (index). + * @retval config index (0 to I2C_VALID_TIMING_NBR], 0xFFFFFFFF for no valid config. + */ +uint32_t i2c_compute_scll_sclh(uint32_t clock_src_freq, uint32_t I2C_speed) +{ + uint32_t ret = 0xFFFFFFFFU; + uint32_t ti2cclk; + uint32_t ti2cspeed; + uint32_t prev_error; + uint32_t dnf_delay; + uint32_t clk_min, clk_max; + uint32_t scll, sclh; + uint32_t tafdel_min; + + ti2cclk = (SEC2NSEC + (clock_src_freq / 2U)) / clock_src_freq; + ti2cspeed = (SEC2NSEC + (I2C_Charac[I2C_speed].freq / 2U)) / I2C_Charac[I2C_speed].freq; + + tafdel_min = (I2C_USE_ANALOG_FILTER == 1U) ? I2C_ANALOG_FILTER_DELAY_MIN : 0U; + + /* tDNF = DNF x tI2CCLK */ + dnf_delay = I2C_Charac[I2C_speed].dnf * ti2cclk; + + clk_max = SEC2NSEC / I2C_Charac[I2C_speed].freq_min; + clk_min = SEC2NSEC / I2C_Charac[I2C_speed].freq_max; + + prev_error = ti2cspeed; + + for (uint32_t count = 0; count < I2c_valid_timing_nbr; count++) { + /* tPRESC = (PRESC+1) x tI2CCLK*/ + uint32_t tpresc = (I2c_valid_timing[count].presc + 1U) * ti2cclk; + + for (scll = 0; scll < I2C_SCLL_MAX; scll++) { + /* tLOW(min) <= tAF(min) + tDNF + 2 x tI2CCLK + [(SCLL+1) x tPRESC ] */ + uint32_t tscl_l = tafdel_min + dnf_delay + (2U * ti2cclk) + ((scll + 1U) * tpresc); + + + /* The I2CCLK period tI2CCLK must respect the following conditions: + tI2CCLK < (tLOW - tfilters) / 4 and tI2CCLK < tHIGH */ + if ((tscl_l > I2C_Charac[I2C_speed].lscl_min) && (ti2cclk < ((tscl_l - tafdel_min - dnf_delay) / 4U))) { + for (sclh = 0; sclh < I2C_SCLH_MAX; sclh++) { + /* tHIGH(min) <= tAF(min) + tDNF + 2 x tI2CCLK + [(SCLH+1) x tPRESC] */ + uint32_t tscl_h = tafdel_min + dnf_delay + (2U * ti2cclk) + ((sclh + 1U) * tpresc); + + /* tSCL = tf + tLOW + tr + tHIGH */ + uint32_t tscl = tscl_l + tscl_h + I2C_Charac[I2C_speed].trise + I2C_Charac[I2C_speed].tfall; + + if ((tscl >= clk_min) && (tscl <= clk_max) && (tscl_h >= I2C_Charac[I2C_speed].hscl_min) && (ti2cclk < tscl_h)) { + int32_t error = (int32_t)tscl - (int32_t)ti2cspeed; + + if (error < 0) { + error = -error; + } + + /* look for the timings with the lowest clock error */ + if ((uint32_t)error < prev_error) { + prev_error = (uint32_t)error; + I2c_valid_timing[count].scll = scll; + I2c_valid_timing[count].sclh = sclh; + ret = count; + } + } + } + } + } + } + + return ret; +} + +/** + * @brief Compute PRESC, SCLDEL and SDADEL. + * @param clock_src_freq I2C source clock in HZ. + * @param I2C_speed I2C frequency (index). + * @retval None. + */ +void i2c_compute_presc_scldel_sdadel(uint32_t clock_src_freq, uint32_t I2C_speed) +{ + uint32_t prev_presc = I2C_PRESC_MAX; + uint32_t ti2cclk; + int32_t tsdadel_min, tsdadel_max; + int32_t tscldel_min; + uint32_t presc, scldel, sdadel; + uint32_t tafdel_min, tafdel_max; + + ti2cclk = (SEC2NSEC + (clock_src_freq / 2U)) / clock_src_freq; + + tafdel_min = (I2C_USE_ANALOG_FILTER == 1U) ? I2C_ANALOG_FILTER_DELAY_MIN : 0U; + tafdel_max = (I2C_USE_ANALOG_FILTER == 1U) ? I2C_ANALOG_FILTER_DELAY_MAX : 0U; + + /* tDNF = DNF x tI2CCLK + tPRESC = (PRESC+1) x tI2CCLK + SDADEL >= {tf +tHD;DAT(min) - tAF(min) - tDNF - [3 x tI2CCLK]} / {tPRESC} + SDADEL <= {tVD;DAT(max) - tr - tAF(max) - tDNF- [4 x tI2CCLK]} / {tPRESC} */ + + tsdadel_min = (int32_t)I2C_Charac[I2C_speed].tfall + (int32_t)I2C_Charac[I2C_speed].hddat_min - + (int32_t)tafdel_min - (int32_t)(((int32_t)I2C_Charac[I2C_speed].dnf + 3) * (int32_t)ti2cclk); + + tsdadel_max = (int32_t)I2C_Charac[I2C_speed].vddat_max - (int32_t)I2C_Charac[I2C_speed].trise - + (int32_t)tafdel_max - (int32_t)(((int32_t)I2C_Charac[I2C_speed].dnf + 4) * (int32_t)ti2cclk); + + + /* {[tr+ tSU;DAT(min)] / [tPRESC]} - 1 <= SCLDEL */ + tscldel_min = (int32_t)I2C_Charac[I2C_speed].trise + (int32_t)I2C_Charac[I2C_speed].sudat_min; + + if (tsdadel_min <= 0) { + tsdadel_min = 0; + } + + if (tsdadel_max <= 0) { + tsdadel_max = 0; + } + + for (presc = 0; presc < I2C_PRESC_MAX; presc++) { + for (scldel = 0; scldel < I2C_SCLDEL_MAX; scldel++) { + /* TSCLDEL = (SCLDEL+1) * (PRESC+1) * TI2CCLK */ + uint32_t tscldel = (scldel + 1U) * (presc + 1U) * ti2cclk; + + if (tscldel >= (uint32_t)tscldel_min) { + for (sdadel = 0; sdadel < I2C_SDADEL_MAX; sdadel++) { + /* TSDADEL = SDADEL * (PRESC+1) * TI2CCLK */ + uint32_t tsdadel = (sdadel * (presc + 1U)) * ti2cclk; + + if ((tsdadel >= (uint32_t)tsdadel_min) && (tsdadel <= (uint32_t)tsdadel_max)) { + if (presc != prev_presc) { + I2c_valid_timing[I2c_valid_timing_nbr].presc = presc; + I2c_valid_timing[I2c_valid_timing_nbr].tscldel = scldel; + I2c_valid_timing[I2c_valid_timing_nbr].tsdadel = sdadel; + prev_presc = presc; + I2c_valid_timing_nbr ++; + + if (I2c_valid_timing_nbr >= I2C_VALID_TIMING_NBR) { + return; + } + } + } + } + } + } + } +} + +/** + * @brief Compute I2C timing according current I2C clock source and required I2C clock. + * @param clock_src_freq I2C clock source in Hz. + * @param i2c_freq Required I2C clock in Hz. + * @retval I2C timing or 0 in case of error. + */ +uint32_t i2c_compute_timing(uint32_t clock_src_freq, uint32_t i2c_freq) +{ + uint32_t ret = 0; + uint32_t speed; + uint32_t idx; + + if ((clock_src_freq != 0U) && (i2c_freq != 0U)) { + for (speed = 0 ; speed <= (uint32_t)I2C_SPEED_FREQ_FAST_PLUS ; speed++) { + if ((i2c_freq >= I2C_Charac[speed].freq_min) && + (i2c_freq <= I2C_Charac[speed].freq_max)) { + i2c_compute_presc_scldel_sdadel(clock_src_freq, speed); + idx = i2c_compute_scll_sclh(clock_src_freq, speed); + + if (idx < I2C_VALID_TIMING_NBR) { + ret = ((I2c_valid_timing[idx].presc & 0x0FU) << 28) | \ + ((I2c_valid_timing[idx].tscldel & 0x0FU) << 20) | \ + ((I2c_valid_timing[idx].tsdadel & 0x0FU) << 16) | \ + ((I2c_valid_timing[idx].sclh & 0xFFU) << 8) | \ + ((I2c_valid_timing[idx].scll & 0xFFU) << 0); + } + break; + } + } + } + + return ret; +} +#endif // MBED_CONF_TARGET_I2C_TIMING_VALUE_ALGO + #endif // DEVICE_I2C_ASYNCH #endif // DEVICE_I2C diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c index 4774ede0cb..964b508cee 100644 --- a/targets/TARGET_STM/lp_ticker.c +++ b/targets/TARGET_STM/lp_ticker.c @@ -285,7 +285,7 @@ void lp_ticker_init(void) #if (LPTIM_MST_BASE == LPTIM1_BASE) #if defined (__HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT) -__HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT(); + __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT(); #endif #endif #if defined (__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT) diff --git a/targets/TARGET_STM/lp_ticker_defines.h b/targets/TARGET_STM/lp_ticker_defines.h new file mode 100644 index 0000000000..dc2d46b773 --- /dev/null +++ b/targets/TARGET_STM/lp_ticker_defines.h @@ -0,0 +1,41 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2015-2021 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#ifndef __LP_TICKER_DEFINES_H +#define __LP_TICKER_DEFINES_H + +#define LP_TICKER_PERIOD_NUM 1000000 + +#if MBED_CONF_TARGET_LPTICKER_LPTIM + +#if MBED_CONF_TARGET_LSE_AVAILABLE +#define LP_TICKER_PERIOD_DEN (LSE_VALUE / MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK) +#else +#define LP_TICKER_PERIOD_DEN (LSI_VALUE / MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK) +#endif +#define LP_TICKER_MASK 0xFFFF // 16 bits + +#else // MBED_CONF_TARGET_LPTICKER_LPTIM == 0 => Use RTC WAKEUP timer + +#if MBED_CONF_TARGET_LSE_AVAILABLE +#define LP_TICKER_PERIOD_DEN (LSE_VALUE / 4) // RTC_CLOCK / RTC_WAKEUPCLOCK_RTCCLK_DIV4 +#else +#define LP_TICKER_PERIOD_DEN (LSI_VALUE / 4) // RTC_CLOCK / RTC_WAKEUPCLOCK_RTCCLK_DIV4 +#endif +#define LP_TICKER_MASK 0xFFFFFFFF // 32 bits + +#endif // MBED_CONF_TARGET_LPTICKER_LPTIM + +#endif // __LP_TICKER_DEFINES_H diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index 5647d97132..f5e1e6c614 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -41,30 +41,31 @@ extern void SetSysClock(void); /** * @brief configure the LSE crystal driver load - * This settings ist target hardware dependend and + * This setting is target hardware dependend and * depends on the crystal that is used for LSE clock. * For low power requirements, crystals with low load capacitors can be used and * driver setting is RCC_LSEDRIVE_LOW. * For higher stablity, crystals with higher load capacitys can be used and * driver setting is RCC_LSEDRIVE_HIGH. - * + * * A detailed description about this setting can be found here: * https://www.st.com/resource/en/application_note/cd00221665-oscillator-design-guide-for-stm8afals-stm32-mcus-and-mpus-stmicroelectronics.pdf - * - * LSE maybe used later, but crystal load drive setting is necessary before + * + * LSE maybe used later, but crystal load drive setting is necessary before * enabling LSE. - * + * * @param None * @retval None */ -static void LSEDriveConfig(void) { +static void LSEDriveConfig(void) +{ HAL_PWR_EnableBkUpAccess(); - #if defined(__HAL_RCC_LSEDRIVE_CONFIG) - __HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL); - #else - HAL_RCCEx_SelectLSEMode(LSE_DRIVE_LOAD_LEVEL); - #endif +#if defined(__HAL_RCC_LSEDRIVE_CONFIG) + __HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL); +#else + HAL_RCCEx_SelectLSEMode(LSE_DRIVE_LOAD_LEVEL); +#endif } #endif // LSE_CONFIG_AVAILABLE @@ -79,13 +80,15 @@ static void LSEDriveConfig(void) { * @param None * @retval None */ -MBED_WEAK void TargetBSP_Init(void) { +MBED_WEAK void TargetBSP_Init(void) +{ /** Do nothing */ } #ifndef MBED_DEBUG #if MBED_CONF_TARGET_GPIO_RESET_AT_INIT -void GPIO_Full_Init(void) { +void GPIO_Full_Init(void) +{ GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitStruct.Pin = GPIO_PIN_All; @@ -238,7 +241,7 @@ void mbed_sdk_init() #if IS_PWR_SUPPLY(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY) HAL_PWREx_ConfigSupply(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY); #else - #error system_power_supply not configured +#error system_power_supply not configured #endif #endif @@ -276,7 +279,7 @@ void mbed_sdk_init() #if IS_PWR_SUPPLY(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY) HAL_PWREx_ConfigSupply(MBED_CONF_TARGET_SYSTEM_POWER_SUPPLY); #else - #error system_power_supply not configured +#error system_power_supply not configured #endif #endif @@ -290,8 +293,7 @@ void mbed_sdk_init() RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; PeriphClkInitStruct.RTCClockSelection = (RCC_RTCCLKSOURCE_HSE_DIVX | RTC_HSE_DIV << 16); - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { error("PeriphClkInitStruct RTC failed with HSE\n"); } #elif ((MBED_CONF_TARGET_RTC_CLOCK_SOURCE == USE_RTC_CLK_LSE_OR_LSI) && !MBED_CONF_TARGET_LSE_AVAILABLE) || (MBED_CONF_TARGET_RTC_CLOCK_SOURCE == USE_RTC_CLK_LSI) diff --git a/targets/TARGET_STM/ospi_api.c b/targets/TARGET_STM/ospi_api.c index bd9df34748..6ce5514e1b 100644 --- a/targets/TARGET_STM/ospi_api.c +++ b/targets/TARGET_STM/ospi_api.c @@ -34,7 +34,7 @@ /* Max amount of flash size is 4Gbytes */ /* hence 2^(31+1), then FLASH_SIZE_DEFAULT = 1<<31 */ -#define OSPI_FLASH_SIZE_DEFAULT 0x80000000 +#define OSPI_FLASH_SIZE_DEFAULT 0x4000000 //512Mbits static uint32_t get_alt_bytes_size(const uint32_t num_bytes) { @@ -65,7 +65,7 @@ ospi_status_t ospi_prepare_command(const ospi_command_t *command, OSPI_RegularCm st_command->Instruction = 0; } else { st_command->Instruction = ((command->instruction.bus_width == OSPI_CFG_BUS_OCTA) || (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR)) - ? command->instruction.value << 8 | (0xFF - command->instruction.value) : command->instruction.value; + ? command->instruction.value << 8 | (0xFF - command->instruction.value) : command->instruction.value; switch (command->instruction.bus_width) { case OSPI_CFG_BUS_SINGLE: st_command->InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE; @@ -87,14 +87,14 @@ ospi_status_t ospi_prepare_command(const ospi_command_t *command, OSPI_RegularCm } st_command->InstructionSize = (st_command->InstructionMode == HAL_OSPI_INSTRUCTION_8_LINES) ? HAL_OSPI_INSTRUCTION_16_BITS : HAL_OSPI_INSTRUCTION_8_BITS; - st_command->InstructionDtrMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE :HAL_OSPI_INSTRUCTION_DTR_DISABLE; + st_command->InstructionDtrMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_INSTRUCTION_DTR_ENABLE : HAL_OSPI_INSTRUCTION_DTR_DISABLE; st_command->DummyCycles = command->dummy_count; // these are target specific settings, use default values st_command->SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD; st_command->DataDtrMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_DATA_DTR_ENABLE : HAL_OSPI_DATA_DTR_DISABLE; st_command->AddressDtrMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_ADDRESS_DTR_ENABLE : HAL_OSPI_ADDRESS_DTR_DISABLE; st_command->AlternateBytesDtrMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE : HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE; - st_command->DQSMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_DQS_ENABLE :HAL_OSPI_DQS_DISABLE; + st_command->DQSMode = (command->instruction.bus_width == OSPI_CFG_BUS_OCTA_DTR) ? HAL_OSPI_DQS_ENABLE : HAL_OSPI_DQS_DISABLE; st_command->OperationType = HAL_OSPI_OPTYPE_COMMON_CFG; if (command->address.disabled == true) { @@ -245,14 +245,14 @@ static ospi_status_t _ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap, // Set default OCTOSPI handle values obj->handle.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE; //#if defined(TARGET_MX25LM512451G) - // obj->handle.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX; // Read sequence in DTR mode: D1-D0-D3-D2 +// obj->handle.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX; // Read sequence in DTR mode: D1-D0-D3-D2 //#else obj->handle.Init.MemoryType = HAL_OSPI_MEMTYPE_MICRON; // Read sequence in DTR mode: D0-D1-D2-D3 //#endif obj->handle.Init.ClockPrescaler = 4; // default value, will be overwritten in ospi_frequency obj->handle.Init.FifoThreshold = 4; obj->handle.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE; - obj->handle.Init.DeviceSize = POSITION_VAL(OSPI_FLASH_SIZE_DEFAULT) - 1; + obj->handle.Init.DeviceSize = 32; obj->handle.Init.ChipSelectHighTime = 3; obj->handle.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE; #if defined(HAL_OSPI_WRAP_NOT_SUPPORTED) // removed in STM32L4 @@ -365,7 +365,7 @@ static ospi_status_t _ospi_init_direct(ospi_t *obj, const ospi_pinmap_t *pinmap, } ospi_status_t ospi_init(ospi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName io4, PinName io5, PinName io6, PinName io7, - PinName sclk, PinName ssel, PinName dqs, uint32_t hz, uint8_t mode) + PinName sclk, PinName ssel, PinName dqs, uint32_t hz, uint8_t mode) { OSPIName ospiio0name = (OSPIName)pinmap_peripheral(io0, PinMap_OSPI_DATA0); OSPIName ospiio1name = (OSPIName)pinmap_peripheral(io1, PinMap_OSPI_DATA1); @@ -403,8 +403,9 @@ ospi_status_t ospi_init(ospi_t *obj, PinName io0, PinName io1, PinName io2, PinN int function_dqs = (int)pinmap_find_function(dqs, PinMap_OSPI_DQS); const ospi_pinmap_t static_pinmap = {peripheral, io0, function_io0, io1, function_io1, io2, function_io2, io3, function_io3, - io4, function_io4, io5, function_io5, io6, function_io6, io7, function_io7, - sclk, function_sclk, ssel, function_ssel, dqs, function_dqs}; + io4, function_io4, io5, function_io5, io6, function_io6, io7, function_io7, + sclk, function_sclk, ssel, function_ssel, dqs, function_dqs + }; return OSPI_INIT_DIRECT(obj, &static_pinmap, hz, mode); } diff --git a/targets/TARGET_STM/pinmap.c b/targets/TARGET_STM/pinmap.c index c659b29a97..8a9d8ff4c1 100644 --- a/targets/TARGET_STM/pinmap.c +++ b/targets/TARGET_STM/pinmap.c @@ -35,6 +35,85 @@ extern GPIO_TypeDef *Set_GPIO_Clock(uint32_t port_idx); +#if defined(DUAL_PAD) // STM32H7 + +typedef struct { + PinName pin; + uint32_t LL_AnalogSwitch; +} PinAnalogSwitch; + + +const PinAnalogSwitch PinMapAnalogSwitch[] = { + {PA_0, LL_SYSCFG_ANALOG_SWITCH_PA0}, + {PA_1, LL_SYSCFG_ANALOG_SWITCH_PA1}, + {PC_2, LL_SYSCFG_ANALOG_SWITCH_PC2}, + {PC_3, LL_SYSCFG_ANALOG_SWITCH_PC3}, + {NC, 0} +}; + +/** + * Configure Analog dualpad switch if necessary + * LL_AnalogSwitch: LL define to be used to configure Analog switch + */ +static void configure_dualpad_switch(PinName pin, int function, uint32_t LL_AnalogSwitch) +{ + if (LL_AnalogSwitch == 0) { + return ; + } + + if (((function & STM_MODE_ANALOG) != STM_MODE_ANALOG) + && ((pin & DUAL_PAD) == DUAL_PAD)) { + /** + * We don't configure an analog function but the pin is an analog pad + * Pxy_C. In this cases Analog switch should be closed + */ + LL_SYSCFG_CloseAnalogSwitch(LL_AnalogSwitch); + return ; + } else { + /** + * Either we configure an analog function, + * or it is not an analog function but it is not an analog pad Pxy_C. + * In both cases Analog switch should be opened + * Note: direct ADC is restricted to Pxy_C, pin only + */ + LL_SYSCFG_OpenAnalogSwitch(LL_AnalogSwitch); + return ; + } +} + +/** + * In case of dual pad, determine whether gpio needs to be configured + * pLL_AnalogSwitch: pointer used to retrun LL define to be used to configure + * Analog switch + * return: true when gpio must be configured + */ +static bool is_dualpad_switch_gpio_configurable(PinName pin, int function, uint32_t *pLL_AnalogSwitch) +{ + PinAnalogSwitch *AnalogSwitch = (PinAnalogSwitch *) PinMapAnalogSwitch; + + /* Read through PinMapAnalogSwitch array */ + while (AnalogSwitch->pin != NC) { + /* Check whether pin is or is associated to dualpad Analog Input */ + if ((AnalogSwitch->pin | DUAL_PAD) == (pin | DUAL_PAD)) { + *pLL_AnalogSwitch = AnalogSwitch->LL_AnalogSwitch; + if (((function & STM_MODE_ANALOG) == STM_MODE_ANALOG) + && ((pin & DUAL_PAD) == DUAL_PAD)) { + /** + * We configure an analog function and the pin is an analog pad Pxy_C + * In this case gpio configuration must be skipped + */ + return false; + } else { + return true; + } + } + AnalogSwitch ++; + } + *pLL_AnalogSwitch = 0; + return true; +} +#endif /* DUAL_PAD */ + const uint32_t ll_pin_defines[16] = { LL_GPIO_PIN_0, LL_GPIO_PIN_1, @@ -71,6 +150,15 @@ void pin_function(PinName pin, int data) uint32_t ll_pin = ll_pin_defines[STM_PIN(pin)]; uint32_t ll_mode = 0; +#if defined(DUAL_PAD) + uint32_t LL_AnalogSwitch = 0; + if (!is_dualpad_switch_gpio_configurable(pin, data, &LL_AnalogSwitch)) { + /* Skip gpio configuration */ + configure_dualpad_switch(pin, data, LL_AnalogSwitch); + return; + } +#endif /* DUAL_PAD */ + // Enable GPIO clock GPIO_TypeDef *const gpio = Set_GPIO_Clock(port); @@ -153,6 +241,10 @@ void pin_function(PinName pin, int data) stm_pin_PullConfig(gpio, ll_pin, STM_PIN_PUPD(data)); +#if defined(DUAL_PAD) + configure_dualpad_switch(pin, data, LL_AnalogSwitch); +#endif /* DUAL_PAD */ + stm_pin_DisconnectDebug(pin); #if defined(DUAL_CORE) && (TARGET_STM32H7) diff --git a/targets/TARGET_STM/serial_api.c b/targets/TARGET_STM/serial_api.c index 259c7b8719..d905aceb4d 100644 --- a/targets/TARGET_STM/serial_api.c +++ b/targets/TARGET_STM/serial_api.c @@ -354,10 +354,10 @@ void serial_free(serial_t *obj) pin_function(obj_s->pin_tx, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)); pin_function(obj_s->pin_rx, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)); #if DEVICE_SERIAL_FC - if ( (obj_s->hw_flow_ctl == UART_HWCONTROL_RTS) || (obj_s->hw_flow_ctl == UART_HWCONTROL_RTS_CTS) ) { + if ((obj_s->hw_flow_ctl == UART_HWCONTROL_RTS) || (obj_s->hw_flow_ctl == UART_HWCONTROL_RTS_CTS)) { pin_function(obj_s->pin_rts, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)); } - if ( (obj_s->hw_flow_ctl == UART_HWCONTROL_CTS) || (obj_s->hw_flow_ctl == UART_HWCONTROL_RTS_CTS) ) { + if ((obj_s->hw_flow_ctl == UART_HWCONTROL_CTS) || (obj_s->hw_flow_ctl == UART_HWCONTROL_RTS_CTS)) { pin_function(obj_s->pin_cts, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)); } #endif diff --git a/targets/TARGET_STM/sleep.c b/targets/TARGET_STM/sleep.c index df92380813..b266c74c70 100644 --- a/targets/TARGET_STM/sleep.c +++ b/targets/TARGET_STM/sleep.c @@ -181,7 +181,7 @@ __WEAK void hal_deepsleep(void) save_timer_ctx(); // Request to enter STOP mode with regulator in low power mode - //PWR_CR1_LPMS_STOP2 -> STM32L4 ; PWR_LOWPOWERMODE_STOP2 -> STM32WL + //PWR_CR1_LPMS_STOP2 -> STM32L4 ; PWR_LOWPOWERMODE_STOP2 -> STM32WL #if defined (PWR_CR1_LPMS_STOP2) || defined(PWR_LOWPOWERMODE_STOP2) int pwrClockEnabled = __HAL_RCC_PWR_IS_CLK_ENABLED(); int lowPowerModeEnabled = PWR->CR1 & PWR_CR1_LPR; diff --git a/targets/TARGET_STM/stm_spi_api.c b/targets/TARGET_STM/stm_spi_api.c index 2c891635e4..3c10bdaf3d 100644 --- a/targets/TARGET_STM/stm_spi_api.c +++ b/targets/TARGET_STM/stm_spi_api.c @@ -400,132 +400,132 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) DataSize = SPI_DATASIZE_4BIT; break; #endif -#if defined(SPI_DATASIZE_5BIT) +#if defined(SPI_DATASIZE_5BIT) case 5: DataSize = SPI_DATASIZE_5BIT; break; #endif -#if defined(SPI_DATASIZE_6BIT) +#if defined(SPI_DATASIZE_6BIT) case 6: DataSize = SPI_DATASIZE_6BIT; break; #endif -#if defined(SPI_DATASIZE_7BIT) +#if defined(SPI_DATASIZE_7BIT) case 7: DataSize = SPI_DATASIZE_7BIT; break; #endif -#if defined(SPI_DATASIZE_9BIT) +#if defined(SPI_DATASIZE_9BIT) case 9: DataSize = SPI_DATASIZE_9BIT; break; #endif -#if defined(SPI_DATASIZE_10BIT) +#if defined(SPI_DATASIZE_10BIT) case 10: DataSize = SPI_DATASIZE_10BIT; break; #endif -#if defined(SPI_DATASIZE_11BIT) +#if defined(SPI_DATASIZE_11BIT) case 11: DataSize = SPI_DATASIZE_11BIT; break; #endif -#if defined(SPI_DATASIZE_12BIT) +#if defined(SPI_DATASIZE_12BIT) case 12: DataSize = SPI_DATASIZE_12BIT; break; #endif -#if defined(SPI_DATASIZE_13BIT) +#if defined(SPI_DATASIZE_13BIT) case 13: DataSize = SPI_DATASIZE_13BIT; break; #endif -#if defined(SPI_DATASIZE_14BIT) +#if defined(SPI_DATASIZE_14BIT) case 14: DataSize = SPI_DATASIZE_14BIT; break; #endif -#if defined(SPI_DATASIZE_15BIT) +#if defined(SPI_DATASIZE_15BIT) case 15: DataSize = SPI_DATASIZE_15BIT; break; #endif -#if defined(SPI_DATASIZE_17BIT) +#if defined(SPI_DATASIZE_17BIT) case 17: DataSize = SPI_DATASIZE_17BIT; break; #endif -#if defined(SPI_DATASIZE_18BIT) +#if defined(SPI_DATASIZE_18BIT) case 18: DataSize = SPI_DATASIZE_18BIT; break; #endif -#if defined(SPI_DATASIZE_19BIT) +#if defined(SPI_DATASIZE_19BIT) case 19: DataSize = SPI_DATASIZE_19BIT; break; #endif -#if defined(SPI_DATASIZE_20BIT) +#if defined(SPI_DATASIZE_20BIT) case 20: DataSize = SPI_DATASIZE_20BIT; break; #endif -#if defined(SPI_DATASIZE_21BIT) +#if defined(SPI_DATASIZE_21BIT) case 21: DataSize = SPI_DATASIZE_21BIT; break; #endif -#if defined(SPI_DATASIZE_22BIT) +#if defined(SPI_DATASIZE_22BIT) case 22: DataSize = SPI_DATASIZE_22BIT; break; #endif -#if defined(SPI_DATASIZE_23BIT) +#if defined(SPI_DATASIZE_23BIT) case 23: DataSize = SPI_DATASIZE_23BIT; break; #endif -#if defined(SPI_DATASIZE_24BIT) +#if defined(SPI_DATASIZE_24BIT) case 24: DataSize = SPI_DATASIZE_24BIT; break; #endif -#if defined(SPI_DATASIZE_25BIT) +#if defined(SPI_DATASIZE_25BIT) case 25: DataSize = SPI_DATASIZE_25BIT; break; #endif -#if defined(SPI_DATASIZE_26BIT) +#if defined(SPI_DATASIZE_26BIT) case 26: DataSize = SPI_DATASIZE_26BIT; break; #endif -#if defined(SPI_DATASIZE_27BIT) +#if defined(SPI_DATASIZE_27BIT) case 27: DataSize = SPI_DATASIZE_27BIT; break; #endif -#if defined(SPI_DATASIZE_28BIT) +#if defined(SPI_DATASIZE_28BIT) case 28: DataSize = SPI_DATASIZE_28BIT; break; #endif -#if defined(SPI_DATASIZE_29BIT) +#if defined(SPI_DATASIZE_29BIT) case 29: DataSize = SPI_DATASIZE_29BIT; break; #endif -#if defined(SPI_DATASIZE_30BIT) +#if defined(SPI_DATASIZE_30BIT) case 30: DataSize = SPI_DATASIZE_30BIT; break; #endif -#if defined(SPI_DATASIZE_31BIT) +#if defined(SPI_DATASIZE_31BIT) case 31: DataSize = SPI_DATASIZE_31BIT; break; #endif -#if defined(SPI_DATASIZE_32BIT) +#if defined(SPI_DATASIZE_32BIT) case 32: DataSize = SPI_DATASIZE_32BIT; break; @@ -667,106 +667,107 @@ static inline int ssp_busy(spi_t *obj) return status; } -static inline int datasize_to_transfer_bitshift(uint32_t DataSize) { +static inline int datasize_to_transfer_bitshift(uint32_t DataSize) +{ switch (DataSize) { #if defined(SPI_DATASIZE_4BIT) case SPI_DATASIZE_4BIT: #endif -#if defined(SPI_DATASIZE_5BIT) +#if defined(SPI_DATASIZE_5BIT) case SPI_DATASIZE_5BIT: #endif -#if defined(SPI_DATASIZE_6BIT) +#if defined(SPI_DATASIZE_6BIT) case SPI_DATASIZE_6BIT: #endif -#if defined(SPI_DATASIZE_7BIT) +#if defined(SPI_DATASIZE_7BIT) case SPI_DATASIZE_7BIT: #endif case SPI_DATASIZE_8BIT: return 0; -#if defined(SPI_DATASIZE_9BIT) +#if defined(SPI_DATASIZE_9BIT) case SPI_DATASIZE_9BIT: #endif -#if defined(SPI_DATASIZE_10BIT) +#if defined(SPI_DATASIZE_10BIT) case SPI_DATASIZE_10BIT: #endif -#if defined(SPI_DATASIZE_11BIT) +#if defined(SPI_DATASIZE_11BIT) case SPI_DATASIZE_11BIT: #endif -#if defined(SPI_DATASIZE_12BIT) +#if defined(SPI_DATASIZE_12BIT) case SPI_DATASIZE_12BIT: #endif -#if defined(SPI_DATASIZE_13BIT) +#if defined(SPI_DATASIZE_13BIT) case SPI_DATASIZE_13BIT: #endif -#if defined(SPI_DATASIZE_14BIT) +#if defined(SPI_DATASIZE_14BIT) case SPI_DATASIZE_14BIT: #endif -#if defined(SPI_DATASIZE_15BIT) +#if defined(SPI_DATASIZE_15BIT) case SPI_DATASIZE_15BIT: #endif case SPI_DATASIZE_16BIT: return 1; -#if defined(SPI_DATASIZE_17BIT) +#if defined(SPI_DATASIZE_17BIT) case SPI_DATASIZE_17BIT: return 2; #endif -#if defined(SPI_DATASIZE_18BIT) +#if defined(SPI_DATASIZE_18BIT) case SPI_DATASIZE_18BIT: return 2; #endif -#if defined(SPI_DATASIZE_19BIT) +#if defined(SPI_DATASIZE_19BIT) case SPI_DATASIZE_19BIT: return 2; #endif -#if defined(SPI_DATASIZE_20BIT) +#if defined(SPI_DATASIZE_20BIT) case SPI_DATASIZE_20BIT: return 2; #endif -#if defined(SPI_DATASIZE_21BIT) +#if defined(SPI_DATASIZE_21BIT) case SPI_DATASIZE_21BIT: return 2; #endif -#if defined(SPI_DATASIZE_22BIT) +#if defined(SPI_DATASIZE_22BIT) case SPI_DATASIZE_22BIT: return 2; #endif -#if defined(SPI_DATASIZE_23BIT) +#if defined(SPI_DATASIZE_23BIT) case SPI_DATASIZE_23BIT: return 2; #endif -#if defined(SPI_DATASIZE_24BIT) +#if defined(SPI_DATASIZE_24BIT) case SPI_DATASIZE_24BIT: return 2; #endif -#if defined(SPI_DATASIZE_25BIT) +#if defined(SPI_DATASIZE_25BIT) case SPI_DATASIZE_25BIT: return 2; #endif -#if defined(SPI_DATASIZE_26BIT) +#if defined(SPI_DATASIZE_26BIT) case SPI_DATASIZE_26BIT: return 2; #endif -#if defined(SPI_DATASIZE_27BIT) +#if defined(SPI_DATASIZE_27BIT) case SPI_DATASIZE_27BIT: return 2; #endif -#if defined(SPI_DATASIZE_28BIT) +#if defined(SPI_DATASIZE_28BIT) case SPI_DATASIZE_28BIT: return 2; #endif -#if defined(SPI_DATASIZE_29BIT) +#if defined(SPI_DATASIZE_29BIT) case SPI_DATASIZE_29BIT: return 2; #endif -#if defined(SPI_DATASIZE_30BIT) +#if defined(SPI_DATASIZE_30BIT) case SPI_DATASIZE_30BIT: return 2; #endif -#if defined(SPI_DATASIZE_31BIT) +#if defined(SPI_DATASIZE_31BIT) case SPI_DATASIZE_31BIT: return 2; #endif -#if defined(SPI_DATASIZE_32BIT) +#if defined(SPI_DATASIZE_32BIT) case SPI_DATASIZE_32BIT: return 2; #endif @@ -1034,6 +1035,7 @@ static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer } // asynchronous API +// DMA support for SPI is currently not supported, hence asynchronous SPI does not support high speeds(MHZ range) void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) { struct spi_s *spiobj = SPI_S(obj); diff --git a/targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py b/targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py index ece2ef2d08..f8fbe34b47 100644 --- a/targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py +++ b/targets/TARGET_STM/tools/STM32_gen_PeripheralPins.py @@ -27,7 +27,7 @@ from xml.dom.minidom import parse, Node from argparse import RawTextHelpFormatter import subprocess -GENPINMAP_VERSION = "1.20" +GENPINMAP_VERSION = "1.20.1" ADD_DEVICE_IF = 0 ADD_GPIO_PINMAP = 0 @@ -467,7 +467,14 @@ extern "C" { if DUAL_PAD: line_to_write = (""" -#define ALTC 0xF00 +#define DUAL_PAD 0xF00 +""") + out_h_file.write(line_to_write) + + if ADD_GPIO_PINMAP: + line_to_write = (""" +/* If this macro is defined, then PinMap_GPIO is present in PeripheralPins.c */ +#define GPIO_PINMAP_READY 1 """) out_h_file.write(line_to_write) @@ -490,11 +497,14 @@ def print_footer(): name_counter = 1 if not LED_list: LED_list.append("Pxx") + StandardLED = {} for EachLED in LED_list: - led_label = "" - if EachLED in PinLabel: - led_label = " // %s" % PinLabel[EachLED] - out_h_file.write("#define LED%i %-5s %s\n" % (name_counter, re.sub(r'(P.)', r'\1_', EachLED), led_label)) + PinLabel[EachLED] = "TODO" + StandardLED[PinLabel[EachLED]] = EachLED + + for EachLED in sorted(StandardLED): + led_label = " // %s" % EachLED + out_h_file.write("#define LED%i %-5s %s\n" % (name_counter, re.sub(r'(P.)', r'\1_', StandardLED[EachLED]), led_label)) name_counter += 1 name_counter = 1 @@ -642,7 +652,7 @@ def print_gpio(): if "OSC" in parsed_pin[2]: commented_line = "//" line_to_write = "%-11s" % (commented_line + " {" + parsed_pin[0] + ',') - line_to_write += ' 0, 0},' + line_to_write += ' 0, GPIO_NOPULL},' if parsed_pin[1] in PinLabel: line_to_write += ' // Connected to ' + PinLabel[parsed_pin[1]] if parsed_pin[1] in PinPuPd: @@ -666,7 +676,6 @@ def print_adc(): # the GPIOx_ASCR register if re.match("STM32L4[78]+", mcu_file): s_pin_data += "_ADC_CONTROL" - s_pin_data += ", GPIO_NOPULL, 0, " prev_p = '' alt_index = 0 @@ -698,8 +707,9 @@ def print_adc(): if len(inst) == 0: inst = '1' #single ADC for this product line_to_write += "%-7s" % ('ADC_' + inst + ',') - chan = re.sub('IN[N|P]?', '', a[1]) - line_to_write += s_pin_data + chan + chan = re.sub(r"^IN[N|P]?|\D*$", "", a[1]) + bank = "_ADC_CHANNEL_BANK_B" if a[1].endswith("b") else "" + line_to_write += s_pin_data + bank + ", GPIO_NOPULL, 0, " + chan line_to_write += ', 0)}, // ' + parsed_pin[2] if parsed_pin[1] in PinLabel: line_to_write += ' // Connected to ' + PinLabel[parsed_pin[1]] @@ -1146,7 +1156,7 @@ typedef enum { if "_ALT" in parsed_pin[0]: s1 = " %-10s = %-5s | %s, // same pin used for alternate HW\n" % (parsed_pin[0], parsed_pin[0].split('_A')[0], parsed_pin[0].split('_')[2]) elif len(parsed_pin[0]) > 4 and "C" == parsed_pin[0][4]: - s1 = " %-10s = %-5s | ALTC, // dual pad\n" % (parsed_pin[0], parsed_pin[0].split('_A')[0].replace("PC", "PP").replace("C", "").replace("PP", "PC")) + s1 = " %-10s = %-5s | DUAL_PAD, // dual pad\n" % (parsed_pin[0], parsed_pin[0].split('_A')[0].replace("PC", "PP").replace("C", "").replace("PP", "PC")) else: pin_value = 0 if "PA" in parsed_pin[0]: @@ -1371,10 +1381,6 @@ def parse_pins(): name = s.attributes["Name"].value.strip() # full name: "PF0 / OSC_IN" if "_C" in name: DUAL_PAD = True - store_pin("PA_0C", "", "") - store_pin("PA_1C", "", "") - store_pin("PC_2C", "", "") - store_pin("PC_3C", "", "") if s.attributes["Type"].value == "I/O": if "-" in s.attributes["Name"].value: @@ -1671,7 +1677,7 @@ if args.target: print("C40_Discovery_STM32F4DISCOVERY_STM32F407VG_Board replaced by C47_Discovery_STM32F407G-DISC1_STM32F407VG_Board") sys.exit(0) elif "P-NUCLEO-WB55" in board_file_name: - print("Same board as NUCLEO-WB55") + print("Same board as NUCLEO-WB55 (J02)") sys.exit(0) elif "MultiToSingleCore_Board" in board_file_name: print("Same board as PL0_Nucleo_NUCLEO-WL55JC1_STM32WL55JCI_Board_AllConfig.ioc") @@ -1680,7 +1686,7 @@ if args.target: print("Same board as PL0_Nucleo_NUCLEO-WL55JC1_STM32WL55JCI_Board_AllConfig.ioc") sys.exit(0) elif "B-L475E-IOT01A2" in board_file_name: - print("Same board as B-L475E-IOT01A1") + print("Same board as B-L475E-IOT01A1 (42)") sys.exit(0) elif "USBDongle" in board_file_name: print("USB dongle not parsed") diff --git a/targets/TARGET_STM/trng_api.c b/targets/TARGET_STM/trng_api.c index b02e169193..7e9ddba46c 100644 --- a/targets/TARGET_STM/trng_api.c +++ b/targets/TARGET_STM/trng_api.c @@ -128,8 +128,8 @@ void trng_init(trng_t *obj) } /* first random number generated after setting the RNGEN bit should not be used */ - if (HAL_RNG_GenerateRandomNumber(&obj->handle, &dummy) != HAL_OK) { - error("trng_init: HAL_RNG_GenerateRandomNumber\n"); + /* could be executed few times in case of long init (obj->handle.ErrorCode can be checked for debug) */ + while (HAL_RNG_GenerateRandomNumber(&obj->handle, &dummy) != HAL_OK) { } #if defined(CFG_HW_RNG_SEMID) diff --git a/targets/targets.json b/targets/targets.json index 9cdaa427fd..180ec930ba 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -1307,6 +1307,10 @@ "lse_drive_load_level": { "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", "value": "RCC_LSEDRIVE_LOW" + }, + "i2c_timing_value_algo": { + "help": "If value was set to true I2C timing algorithm is enabled. Enabling may leads to performance issue. Keeping this false and changing system clock will trigger assert.)", + "value": false } }, "macros_add": [ @@ -1597,6 +1601,10 @@ "lse_drive_load_level": { "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", "value": "RCC_LSEDRIVE_LOW" + }, + "i2c_timing_value_algo": { + "help": "If value was set to true I2C timing algorithm is enabled. Enabling may leads to performance issue. Keeping this false and changing system clock will trigger assert.)", + "value": false } }, "device_has_add": [ @@ -2343,6 +2351,10 @@ "lse_drive_load_level": { "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", "value": "RCC_LSEDRIVE_LOW" + }, + "i2c_timing_value_algo": { + "help": "If value was set to true I2C timing algorithm is enabled. Enabling may leads to performance issue. Keeping this false and changing system clock will trigger assert.)", + "value": false } }, "overrides": { @@ -2590,6 +2602,10 @@ "lse_drive_load_level": { "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", "value": "RCC_LSEDRIVE_LOW" + }, + "i2c_timing_value_algo": { + "help": "If value was set to true I2C timing algorithm is enabled. Enabling may leads to performance issue. Keeping this false and changing system clock will trigger assert.)", + "value": false } }, "extra_labels_add": [ @@ -2716,6 +2732,10 @@ "lse_drive_load_level": { "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", "value": "RCC_LSEDRIVE_LOW" + }, + "i2c_timing_value_algo": { + "help": "If value was set to true I2C timing algorithm is enabled. Enabling may leads to performance issue. Keeping this false and changing system clock will trigger assert.)", + "value": false } }, "extra_labels_add": [ @@ -2917,6 +2937,10 @@ "expected_value2": "PWR_SMPS_1V8_SUPPLIES_LDO | PWR_SMPS_2V5_SUPPLIES_LDO | PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO | PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO", "expected_value3": "PWR_SMPS_1V8_SUPPLIES_EXT | PWR_SMPS_2V5_SUPPLIES_EXT | PWR_EXTERNAL_SOURCE_SUPPLY", "value": "NC" + }, + "i2c_timing_value_algo": { + "help": "If value was set to true I2C timing algorithm is enabled. Enabling may leads to performance issue. Keeping this false and changing system clock will trigger assert.)", + "value": false } }, "components_add": [ @@ -3174,7 +3198,8 @@ "clock_source": "USE_PLL_HSE_EXTC", "lse_available": 1, "lpticker_delay_ticks": 0, - "network-default-interface-type": "ETHERNET" + "network-default-interface-type": "ETHERNET", + "i2c_timing_value_algo": true }, "device_name": "STM32H747XIHx" }, @@ -3266,6 +3291,10 @@ "lse_drive_load_level": { "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", "value": "RCC_LSEDRIVE_LOW" + }, + "i2c_timing_value_algo": { + "help": "If value was set to true I2C timing algorithm is enabled. Enabling may leads to performance issue. Keeping this false and changing system clock will trigger assert.)", + "value": false } }, "macros_add": [ @@ -3539,6 +3568,10 @@ "lse_drive_load_level": { "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", "value": "RCC_LSEDRIVE_LOW" + }, + "i2c_timing_value_algo": { + "help": "If value was set to true I2C timing algorithm is enabled. Enabling may leads to performance issue. Keeping this false and changing system clock will trigger assert.)", + "value": false } }, "macros_add": [ @@ -4069,6 +4102,10 @@ "lse_drive_load_level": { "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", "value": "RCC_LSEDRIVE_LOW" + }, + "i2c_timing_value_algo": { + "help": "If value was set to true I2C timing algorithm is enabled. Enabling may leads to performance issue. Keeping this false and changing system clock will trigger assert.)", + "value": false } }, "overrides": { @@ -4160,6 +4197,7 @@ "STM32WB", "CORDIO" ], + "mbed_rom_start": "0x08000000", "config": { "lpticker_lptim": { "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer", @@ -4168,6 +4206,10 @@ "lse_drive_load_level": { "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", "value": "RCC_LSEDRIVE_LOW" + }, + "i2c_timing_value_algo": { + "help": "If value was set to true I2C timing algorithm is enabled. Enabling may leads to performance issue. Keeping this false and changing system clock will trigger assert.)", + "value": false } }, "macros_add": [ @@ -4188,6 +4230,38 @@ "BLE" ] }, + "MCU_STM32WB15xC": { + "inherits": [ + "MCU_STM32WB" + ], + "public": false, + "supported_application_profiles": [ + "bare-metal" + ], + "c_lib": "small", + "extra_labels_add": [ + "STM32WB15xC" + ], + "mbed_rom_size": "0x32800", + "overrides": { + "boot-stack-size": "0x400" + }, + "macros_add": [ + "STM32WB15xx" + ] + }, + "NUCLEO_WB15CC": { + "inherits": [ + "MCU_STM32WB15xC" + ], + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "detect_code": [ + "0883" + ], + "device_name": "STM32WB15CCUx" + }, "MCU_STM32WB55xG": { "inherits": [ "MCU_STM32WB" @@ -4196,6 +4270,7 @@ "extra_labels_add": [ "STM32WB55xG" ], + "mbed_rom_size": "0xCA000", "macros_add": [ "STM32WB55xx", "MBEDTLS_CONFIG_HW_SUPPORT" @@ -4224,6 +4299,7 @@ "extra_labels_add": [ "STM32WB5MxG" ], + "mbed_rom_size": "0xCA000", "macros_add": [ "STM32WB5Mxx", "MBEDTLS_CONFIG_HW_SUPPORT" @@ -4258,6 +4334,10 @@ "lse_drive_load_level": { "help": "HSE drive load level RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH", "value": "RCC_LSEDRIVE_LOW" + }, + "i2c_timing_value_algo": { + "help": "If value was set to true I2C timing algorithm is enabled. Enabling may leads to performance issue. Keeping this false and changing system clock will trigger assert.)", + "value": false } }, "macros_add": [ @@ -5898,6 +5978,9 @@ "TRNG", "USTICKER" ], + "components": [ + "FLASHIAP" + ], "extra_labels": [ "NORDIC", "NRF5x", @@ -6183,6 +6266,16 @@ "GCC_ARM" ], "config": { + "hxt-present": { + "help": "High-speed external crystal oscillator HXT is present", + "options": [false, true], + "value": false + }, + "lxt-present": { + "help": "Low-speed external crystal oscillator LXT is present", + "options": [false, true], + "value": true + }, "gpio-irq-debounce-enable": { "help": "Enable GPIO IRQ debounce", "value": 0 @@ -6247,6 +6340,8 @@ "device_name": "NUC472HI8AE", "bootloader_supported": true, "overrides": { + "hxt-present": false, + "lxt-present": true, "network-default-interface-type": "ETHERNET", "deep-sleep-latency": 1, "tickless-from-us-ticker": true @@ -6285,6 +6380,16 @@ "IAR" ], "config": { + "hxt-present": { + "help": "High-speed external crystal oscillator HXT is present", + "options": [false, true], + "value": false + }, + "lxt-present": { + "help": "Low-speed external crystal oscillator LXT is present", + "options": [false, true], + "value": true + }, "gpio-irq-debounce-enable": { "help": "Enable GPIO IRQ debounce", "value": 0 @@ -6372,6 +6477,8 @@ "device_name": "M453VG6AE", "bootloader_supported": true, "overrides": { + "hxt-present": false, + "lxt-present": true, "deep-sleep-latency": 1, "tickless-from-us-ticker": true }, @@ -6394,6 +6501,16 @@ "IAR" ], "config": { + "hxt-present": { + "help": "High-speed external crystal oscillator HXT is present", + "options": [false, true], + "value": false + }, + "lxt-present": { + "help": "Low-speed external crystal oscillator LXT is present", + "options": [false, true], + "value": true + }, "gpio-irq-debounce-enable": { "help": "Enable GPIO IRQ debounce", "value": 0 @@ -6473,6 +6590,8 @@ ], "device_name": "NANO130KE3BN", "overrides": { + "hxt-present": false, + "lxt-present": true, "deep-sleep-latency": 1, "tickless-from-us-ticker": true }, @@ -6496,6 +6615,16 @@ "GCC_ARM" ], "config": { + "hxt-present": { + "help": "High-speed external crystal oscillator HXT is present", + "options": [false, true], + "value": false + }, + "lxt-present": { + "help": "Low-speed external crystal oscillator LXT is present", + "options": [false, true], + "value": true + }, "spim-ccm-enable": { "help": "Enable SPIM CCM mode to spare 32KiB SRAM for normal use", "value": 0 @@ -6624,6 +6753,8 @@ "1304" ], "overrides": { + "hxt-present": false, + "lxt-present": true, "usb-uart": "UART_0", "usb-uart-tx": "PB_13", "usb-uart-rx": "PB_12", @@ -6643,6 +6774,8 @@ "1308" ], "overrides": { + "hxt-present": false, + "lxt-present": true, "usb-uart": "UART_0", "usb-uart-tx": "PB_13", "usb-uart-rx": "PB_12", @@ -6830,6 +6963,152 @@ "MPU" ] }, + "MCU_M2354": { + "inherits": [ + "PSA_V8_M" + ], + "public": false, + "core": "Cortex-M23-NS", + "default_toolchain": "ARMC6", + "supported_toolchains": [ + "ARMC6", + "GCC_ARM", + "IAR" + ], + "features_add": [ + "EXPERIMENTAL_API" + ], + "extra_labels_add": [ + "NUVOTON", + "M2354" + ], + "macros": [ + "CMSIS_NVIC_VIRTUAL", + "LPTICKER_DELAY_TICKS=4" + ], + "is_disk_virtual": true, + "config": { + "hxt-present": { + "help": "High-speed external crystal oscillator HXT is present", + "options": [false, true], + "value": false + }, + "usb-uart": { + "help": "Configure USB_UART. USB_UART and USBTX/USBRX must be consistent.", + "value": null + }, + "usb-uart-tx": { + "help": "Configure USBTX. USB_UART and USBTX/USBRX must be consistent.", + "value": null + }, + "usb-uart-rx": { + "help": "Configure USBRX. USB_UART and USBTX/USBRX must be consistent.", + "value": null + }, + "stdio-uart": { + "help": "Configure STDIO_UART. STDIO_UART and STDIO_UART_TX/STDIO_UART_RX must be consistent. STDIO_UART defaults to USB_UART.", + "value": null + }, + "stdio-uart-tx": { + "help": "Configure STDIO_UART_TX. STDIO_UART and STDIO_UART_TX/STDIO_UART_RX must be consistent. STDIO_UART_TX defaults to USBTX.", + "value": null + }, + "stdio-uart-rx": { + "help": "Configure STDIO_UART_RX. STDIO_UART and STDIO_UART_TX/STDIO_UART_RX must be consistent. STDIO_UART_RX defaults to USBRX.", + "value": null + }, + "gpio-irq-debounce-enable": { + "help": "Enable GPIO IRQ debounce", + "value": 0 + }, + "gpio-irq-debounce-enable-list": { + "help": "Comma separated pin list to enable GPIO IRQ debounce", + "value": "NC" + }, + "gpio-irq-debounce-clock-source": { + "help": "Select GPIO IRQ debounce clock source: GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC", + "value": "GPIO_DBCTL_DBCLKSRC_LIRC" + }, + "gpio-irq-debounce-sample-rate": { + "help": "Select GPIO IRQ debounce sample rate: GPIO_DBCTL_DBCLKSEL_1, GPIO_DBCTL_DBCLKSEL_2, GPIO_DBCTL_DBCLKSEL_4, ..., or GPIO_DBCTL_DBCLKSEL_32768", + "value": "GPIO_DBCTL_DBCLKSEL_16" + } + }, + "overrides": { + "deep-sleep-latency": 1, + "tickless-from-us-ticker": true, + "mpu-rom-end": "0x1fffffff" + }, + "device_has": [ + "USTICKER", + "LPTICKER", + "RTC", + "ANALOGIN", + "ANALOGOUT", + "I2C", + "I2CSLAVE", + "I2C_ASYNCH", + "INTERRUPTIN", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "SERIAL", + "SERIAL_ASYNCH", + "SERIAL_FC", + "STDIO_MESSAGES", + "SLEEP", + "SPI", + "SPISLAVE", + "SPI_ASYNCH", + "MPU" + ], + "release_versions": [ + "5" + ], + "sectors": [ + [ + 0, + 2048 + ] + ], + "bootloader_supported": true, + "forced_reset_timeout": 3 + }, + "NU_M2354": { + "inherits": [ + "MCU_M2354" + ], + "supported_form_factors": [ + "ARDUINO_UNO" + ], + "detect_code": [ + "1312" + ], + "device_name": "M2354KJFAE", + "overrides": { + "hxt-present": false, + "usb-uart": "UART_0", + "usb-uart-tx": "PA_7", + "usb-uart-rx": "PA_6" + }, + "OUTPUT_EXT": "bin", + "components_add": [ + "TFM_S_FW" + ], + "post_binary_hook": { + "function": "NuM2354Code.merge_secure" + }, + "secure_image_filename": "tfm_s.bin", + "tfm_target_name": "nuvoton/m2354", + "tfm_bootloader_supported": true, + "tfm_default_toolchain": "GNUARM", + "tfm_supported_toolchains": [ + "ARMCLANG", + "GNUARM" + ], + "tfm_delivery_dir": "TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW" + }, "MCU_M251": { "core": "Cortex-M23", "public": false, @@ -6849,6 +7128,16 @@ "GCC_ARM" ], "config": { + "hxt-present": { + "help": "High-speed external crystal oscillator HXT is present", + "options": [false, true], + "value": false + }, + "lxt-present": { + "help": "Low-speed external crystal oscillator LXT is present", + "options": [false, true], + "value": true + }, "usb-uart": { "help": "Configure USB_UART. USB_UART and USB_UART_TX/USB_UART_RX must be consistent.", "value": null @@ -6896,6 +7185,8 @@ } }, "overrides": { + "hxt-present": false, + "lxt-present": true, "mpu-rom-end": "0x1fffffff", "deep-sleep-latency": 1, "tickless-from-us-ticker": true @@ -6926,7 +7217,8 @@ "SPISLAVE", "SPI_ASYNCH", "FLASH", - "MPU" + "MPU", + "WATCHDOG" ], "components_add": [ "FLASHIAP" @@ -7784,6 +8076,16 @@ "GCC_ARM" ], "config": { + "hxt-present": { + "help": "High-speed external crystal oscillator HXT is present", + "options": [false, true], + "value": false + }, + "lxt-present": { + "help": "Low-speed external crystal oscillator LXT is present", + "options": [false, true], + "value": true + }, "usb-uart": { "help": "Configure USB_UART. USB_UART and USB_UART_TX/USB_UART_RX must be consistent.", "value": null @@ -7853,6 +8155,7 @@ "TRNG", "FLASH", "MPU", + "WATCHDOG", "USBDEVICE" ], "components_add": [ @@ -7869,6 +8172,8 @@ ], "bootloader_supported": true, "overrides": { + "hxt-present": false, + "lxt-present": true, "deep-sleep-latency": 1, "tickless-from-us-ticker": true }, diff --git a/tools/arm_pack_manager/index.json b/tools/arm_pack_manager/index.json index effb263e4b..c0d6f22f9b 100644 --- a/tools/arm_pack_manager/index.json +++ b/tools/arm_pack_manager/index.json @@ -179274,6 +179274,120 @@ "sub_family": "M2351", "vendor": "Nuvoton:18" }, + "M2354KJFAE": { + "algorithms": [ + { + "default": false, + "file_name": "Flash/M2354_NS.FLM", + "ram_size": 4608, + "ram_start": 805371904, + "size": 1048576, + "start": 268435456 + }, + { + "default": false, + "file_name": "Flash/M2354_LD_16.FLM", + "ram_size": 4608, + "ram_start": 536870912, + "size": 16384, + "start": 1048576 + }, + { + "default": false, + "file_name": "Flash/M2354_AP_1M.FLM", + "ram_size": 4608, + "ram_start": 536870912, + "size": 1048576, + "start": 0 + } + ], + "family": "NuMicro M23 Family", + "from_pack": { + "pack": "NuMicro_DFP", + "url": "http://www.nuvoton.com/hq/enu/Documents/KEILSoftwarePack", + "vendor": "Nuvoton", + "version": "1.3.7" + }, + "memories": { + "IRAM1": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": true, + "size": 131072, + "start": 536870912, + "startup": false + }, + "IRAM2": { + "access": { + "execute": false, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": true + }, + "default": false, + "size": 131072, + "start": 805437440, + "startup": false + }, + "IROM1": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": true, + "size": 524288, + "start": 0, + "startup": true + }, + "IROM2": { + "access": { + "execute": true, + "non_secure": false, + "non_secure_callable": false, + "peripheral": false, + "read": true, + "secure": false, + "write": false + }, + "default": false, + "size": 524288, + "start": 268959744, + "startup": false + } + }, + "name": "M2354KJFAE", + "processor": { + "Symmetric": { + "core": "CortexM23", + "fpu": "None", + "mpu": "Present", + "units": 1 + } + }, + "sectors": [ + [ + 0, + 2048 + ] + ], + "sub_family": "M2354", + "vendor": "Nuvoton:18" + }, "M251EB2AE": { "algorithms": [ { @@ -480109,6 +480223,71 @@ ], "sub_family": "STM32WL55" }, + "STM32WB15CCUx": { + "name": "STM32WB15CCUx", + "memories": { + "IROM1": { + "access": { + "read": true, + "write": false, + "execute": true, + "peripheral": false, + "secure": false, + "non_secure": false, + "non_secure_callable": false + }, + "start": 134217728, + "size": 327680, + "startup": true, + "default": true + }, + "IRAM1": { + "access": { + "read": true, + "write": true, + "execute": false, + "peripheral": false, + "secure": false, + "non_secure": false, + "non_secure_callable": false + }, + "start": 536870912, + "size": 49152, + "startup": false, + "default": true + } + }, + "algorithms": [ + { + "file_name": "CMSIS/Flash/STM32WB_M4.FLM", + "start": 134217728, + "size": 1048576, + "default": true, + "ram_start": null, + "ram_size": null + } + ], + "processor": { + "Symmetric": { + "units": 1, + "core": "CortexM4", + "fpu": "SinglePrecision", + "mpu": "Present" + } + }, + "from_pack": { + "vendor": "Keil", + "pack": "STM32WBxx_DFP", + "version": "1.2.0", + "url": "http://www.keil.com/pack" + }, + "sectors" : [ + [ 134217728, 4096 ] + ], + "vendor": "STMicroelectronics:13", + "family": "STM32WB Series", + "sub_family": "STM32WB15" + }, "STM32WB55CCUx": { "name": "STM32WB55CCUx", "memories": { diff --git a/tools/cmake/cores/Cortex-M55.cmake b/tools/cmake/cores/Cortex-M55.cmake index 796ee4823d..37410aa9f3 100644 --- a/tools/cmake/cores/Cortex-M55.cmake +++ b/tools/cmake/cores/Cortex-M55.cmake @@ -17,13 +17,6 @@ elseif(${MBED_TOOLCHAIN} STREQUAL "ARM") ) endif() -# We'd like to use just "-mcpu=cortex-m55" in common_options, but due to a bug -# in armclang passing options to armasm, we use the following flags as a -# workaround to select M55. -list(APPEND asm_compile_options - -mcpu=cortex-r7 - -Wa,--cpu=cortex-m55 -) function(mbed_set_cpu_core_definitions target) target_compile_definitions(${target} diff --git a/tools/export/uvision/__init__.py b/tools/export/uvision/__init__.py index 3a28977dfa..e82b6e4625 100644 --- a/tools/export/uvision/__init__.py +++ b/tools/export/uvision/__init__.py @@ -135,7 +135,8 @@ class Uvision(Exporter): "LPCTargetCode.lpc_patch", "MTSCode.combine_bins_mts_dragonfly", "LPC55S69Code.binary_hook", - "M2351Code.merge_secure" + "M2351Code.merge_secure", + "M2354Code.merge_secure" ]) # File associations within .uvprojx file diff --git a/tools/targets/NU_M2354.py b/tools/targets/NU_M2354.py new file mode 100644 index 0000000000..66732d9f80 --- /dev/null +++ b/tools/targets/NU_M2354.py @@ -0,0 +1,207 @@ +#!/usr/bin/python +# Copyright (c) 2017-2021 Arm Limited +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +import os +from os.path import abspath, basename, dirname, splitext, isdir +from os.path import join as path_join +import re +import subprocess +import shutil +from intelhex import IntelHex + +SCRIPT_DIR = dirname(abspath(__file__)) +MBED_OS_ROOT = abspath(path_join(SCRIPT_DIR, os.pardir, os.pardir)) + +def m2354_tfm_bin(t_self, non_secure_image, secure_bin): + + assert os.path.isfile(secure_bin) + assert os.path.isfile(non_secure_image) + + secure_bin = abspath(secure_bin) + non_secure_image = abspath(non_secure_image) + + SECURE_ROOT = abspath(dirname(secure_bin)) + + build_dir = dirname(non_secure_image) + tempdir = path_join(build_dir, 'temp') + if not isdir(tempdir): + os.makedirs(tempdir) + + flash_layout = path_join(SECURE_ROOT, 'partition', 'flash_layout.h') + + bl2_bin = path_join(SECURE_ROOT, 'bl2.bin') + image_macros_s_ns = path_join(SECURE_ROOT, 'partition', 'signing_layout_preprocessed.h') + ns_bin_basename, output_ext = splitext(basename(non_secure_image)) + concatenated_bin = abspath(path_join(tempdir, 'tfm_' + ns_bin_basename + ".bin")) + signed_bin = abspath(path_join(tempdir, 'tfm_' + ns_bin_basename + '_signed' + ".bin")) + signed_nopad_bin = abspath(path_join(tempdir, 'tfm_' + ns_bin_basename + '_signed_nopad' + ".bin")) + + # Convert NS image to BIN format if it is HEX + if output_ext == ".hex": + non_secure_bin = abspath(path_join(tempdir, ns_bin_basename + ".bin")) + ns_ih = IntelHex(non_secure_image) + ns_ih.tobinfile(non_secure_bin) + else: + non_secure_bin = non_secure_image + + assert os.path.isfile(image_macros_s_ns) + + signing_key = path_join(SCRIPT_DIR, 'nuvoton_m2354-root-rsa-3072.pem') + assert os.path.isfile(signing_key) + + # Find Python 3 command name across platforms + python3_cmd = "python3" if shutil.which("python3") is not None else "python" + + #1. Concatenate secure TFM and non-secure mbed binaries + cmd = [ + python3_cmd, + path_join(MBED_OS_ROOT, "tools", "psa","tfm", "bin_utils","assemble.py"), + "--layout", + image_macros_s_ns, + "-s", + secure_bin, + "-n", + non_secure_bin, + "-o", + concatenated_bin, + ] + + retcode = run_cmd(cmd, MBED_OS_ROOT) + if retcode: + raise Exception("Unable to concatenate " + "TF-M Secure/Mbed Non-secure" + + " binaries, Error code: " + str(retcode)) + return + + #2.1 Run wrapper to sign the concatenated binary with padding ("--pad"), so upgradeable by mcuboot + cmd = [ + python3_cmd, + path_join(MBED_OS_ROOT, "tools", "psa", "tfm", "bin_utils", "wrapper.py"), + "-v", + '1.2.0', + "-k", + signing_key, + "--layout", + image_macros_s_ns, + "--public-key-format", + 'full', + "--align", + '1', + "--pad", + "--pad-header", + "-H", + '0x400', + "--overwrite-only", + "-s", + 'auto', + "-d", + '(0,0.0.0+0)', + concatenated_bin, + signed_bin, + ] + + retcode = run_cmd(cmd, MBED_OS_ROOT) + if retcode: + raise Exception("Unable to sign " + "concatenated" + + " binary, Error code: " + str(retcode)) + return + + #2.2. Re-run above but without padding ("--pad"), so non-upgradeable by mcuboot + cmd.remove("--pad") + cmd.pop() + cmd.append(signed_nopad_bin) + + retcode = run_cmd(cmd, MBED_OS_ROOT) + if retcode: + raise Exception("Unable to sign " + "concatenated" + + " binary, Error code: " + str(retcode)) + return + + #3. Concatenate mcuboot and signed binary and overwrite mbed built bin/hex file + flash_area_0_offset = find_flash_area_0_offset(flash_layout) + out_ih = IntelHex() + out_ih.loadbin(bl2_bin) + out_ih.loadbin(signed_nopad_bin, flash_area_0_offset) + out_ih.tofile(non_secure_image, 'hex' if output_ext == ".hex" else "bin") + +def find_flash_area_0_offset(configFile): + # Compiled regular expressions + flash_area_bl2_offset_re = re.compile(r"^#define\s+FLASH_AREA_BL2_OFFSET\s+\({0,1}(0x[0-9a-fA-F]+)\){0,1}") + flash_area_bl2_size_re = re.compile(r"^#define\s+FLASH_AREA_BL2_SIZE\s+\({0,1}(0x[0-9a-fA-F]+)\){0,1}") + rsvd_stor_size_re = re.compile(r"^#define\s+FLASH_AREA_0_OFFSET\s+\(FLASH_AREA_BL2_OFFSET\s+\+\s+FLASH_AREA_BL2_SIZE\s+\+\s+\({0,1}(0x[0-9a-fA-F]+)\){0,1}\)") + + # Match values + flash_area_bl2_offset = None + flash_area_bl2_size = None + rsvd_stor_size = None + flash_area_0_offset = None + + with open(configFile, 'r') as configFile_: + for line in configFile_: + # Seek "#define FLASH_AREA_BL2_OFFSET..." + if flash_area_bl2_offset is None: + m = flash_area_bl2_offset_re.match(line) + if m is not None: + flash_area_bl2_offset = int(m.group(1), 0) + continue + + # Seek "#define FLASH_AREA_BL2_SIZE..." + if flash_area_bl2_size is None: + m = flash_area_bl2_size_re.match(line) + if m is not None: + flash_area_bl2_size = int(m.group(1), 0) + continue + + # Seek "#define FLASH_AREA_0_OFFSET..." + if rsvd_stor_size is None: + m = rsvd_stor_size_re.match(line) + if m is not None: + rsvd_stor_size = int(m.group(1), 0) + continue + + # FLASH_AREA_0_OFFSET = FLASH_AREA_BL2_OFFSET + FLASH_AREA_BL2_SIZE + Reserved storage area size + if flash_area_bl2_offset is not None and \ + flash_area_bl2_size is not None and \ + rsvd_stor_size is not None: + flash_area_0_offset = flash_area_bl2_offset + flash_area_bl2_size + rsvd_stor_size + break + + return flash_area_0_offset + +def run_cmd(cmd, directory): + + # Redirect stdout/stderr to pipe, text mode + POPEN_INSTANCE = subprocess.Popen( + cmd, + stdout=subprocess.PIPE, + stderr=subprocess.STDOUT, + cwd=directory, + universal_newlines=True + ) + + # Command line + print("COMMAND: {}".format(POPEN_INSTANCE.args)) + + stdout_data, stderr_data = POPEN_INSTANCE.communicate() + + # stdout/stderr messages + if (stdout_data): + print(stdout_data) + if (stderr_data): + print(stderr_data) + + # Return code + return POPEN_INSTANCE.returncode diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py index b018cedde5..fdf76137cf 100644 --- a/tools/targets/__init__.py +++ b/tools/targets/__init__.py @@ -789,6 +789,21 @@ class M2351Code(object): s_ih.merge(ns_ih) s_ih.tofile(ns_hex, 'hex') +class NuM2354Code(object): + """M2354 Hooks""" + @staticmethod + def merge_secure(t_self, resources, elf, binf): + from tools.targets.NU_M2354 import m2354_tfm_bin + configured_secure_image_filename = t_self.target.secure_image_filename + secure_bin = find_secure_image( + t_self.notify, + resources, + binf, + configured_secure_image_filename, + FileType.BIN + ) + m2354_tfm_bin(t_self, binf, secure_bin) + # End Target specific section ############################################################################### def update_target_data(): diff --git a/tools/targets/nuvoton_m2354-root-rsa-3072.md b/tools/targets/nuvoton_m2354-root-rsa-3072.md new file mode 100644 index 0000000000..0ca0675c49 --- /dev/null +++ b/tools/targets/nuvoton_m2354-root-rsa-3072.md @@ -0,0 +1,11 @@ +# Nuvoton M2354 RSA keypair + +A default RSA key pair is given to the Nuvoton M2354 target. + +Public key was pre-compiled to `targets/TARGET_NUVOTON/TARGET_M2354/TARGET_TFM/TARGET_NU_M2354/COMPONENT_TFM_S_FW/bl2.bin` and private key is in `nuvoton_m2354-root-rsa-3072.pem` for Secure image and Non-Secure image together. + +DO NOT use them in production code, they are exclusively for testing! + +Private key must be stored in a safe place outside of the repository. + +`tools/psa/tfm/bin_utils/imgtool.py` can be used to generate new key pairs. diff --git a/tools/targets/nuvoton_m2354-root-rsa-3072.pem b/tools/targets/nuvoton_m2354-root-rsa-3072.pem new file mode 100644 index 0000000000..23288bc101 --- /dev/null +++ b/tools/targets/nuvoton_m2354-root-rsa-3072.pem @@ -0,0 +1,39 @@ +-----BEGIN RSA PRIVATE KEY----- +MIIG4gIBAAKCAYEAnLrCWr/MxU8gDE9vbFFPXAqrgLhrEMSbK8RSMglLOyeUah3V +TKhcoMB2lXsmBLETfngn1gy06LAtklKK+2n/QhCqVgyDyGVuug1fjvcrKZL8Qi0t ++YD1hSGH6qxAqMvQqDvi0uzwFEgOzyuKS6TNoQVbF2Yd3m5E/kajDdBpv4ytqRZo +Uet5kSDmgQMHiUBVS+vPZ/gxxxxUTlILYOiiUAfRz84SJs2Ogo1OZKn3xyGZJQfd +xdVf9GP6zCvaBlxZZ7AGNemqkkU15aAD/xwCtcdOlEturXOdzm8Js7GPYGyi+s13 +D8wn5jZYs1L3j75JmLfpYP2XV83q0wvfokL3RNOH3uAQA5Ta/LzdvpOzSitY3JYS +8m8jujs3/vwYH3V9VAEOvj0YE7MouTQs1fvFM72HvTvkHdcCPRxyZXJDQzao+uZz +LaRh6AKcOlZNHNF2nIyqXxvrHEr1ubhvQUsnh972lB/d5vGpwgLCT6P8pANa2W94 +/YTw5f09pU0brVtLAgMBAAECggGAG786mltbctEL0PIdPVV10cs3yq2bktfjys9S +Z/ZaQcpDjbfjY9NotrLsK5GmTO1WkKzQDKaqPom2P7HqVhFRdg5CQcKscAV5IWot +sT9T/mO90i9ydLoefWfOyr6dIeUXdzlG8mWtKUIKkSXZsYOnPesXUeCryA3InCXA +RzlPB3Dt68ICTQJ9vrJO7KcvJd7kWvEQAo2frmr3B/iheBInbji8LeiDMShyIu3G +Y67tpWzu0m3+lsAsYTV0GMJosniVulaZ3hYQQazHUk+zDzMSC7zryICrpjEbgzWU +HZI9EGi1B890nwUtdhlCpkr8zoWDb0BjawpftiGz7fRm7q2TQkYAWGzNKm3DZlIS +4LsRACvHnPZ17wUSze9tqP14Pb593WR3nOTiVjrJWm+4Z5hgV3QfoEqW5swOAYl4 +6QmKZsCXAfGkozJiHnYcyaULkGBVegn1LQ5rcb8JUMribQddrHZxCVHrbgwh2zm/ +v9CYfTtpWCnKHq+wF3mwjl6w7m4JAoHBALolVbgs919Dx0xjcPnW5MSxW3ctflI9 +2ZE1BOH/Rtg5gfBwR/aToUM3a/ZgIJHQYhVty2TzUVtthtmLNTRKu2FSqWN8//GJ +wmj4bcNBshMgniHEfkutlBiP9exhdvCZX4bYpdTkJAyvOmUGjEM8QBFsod60u0z7 +Bd0EIXs7PIURP0fNAUXCgSHMPjdICLljhwHinr31VEIU2/xehw8DBIJwkR/rCsPq +xBmlIwPWVjzCRTnYUxQuxCAYf+qvgNylKQKBwQDXi3UGI7t30rYNMdIjMn1GPkhW +o62BOJNCusoXiGnbVOkj8qBayf7kPu10ONBzHcYL7+SQYeVVXQY+DH033ji8oa0J +p1xMGIlx4JZEduQYlk0ke4hUNrcBQczTRA47DmMm2kIdWlaTHtB7aCJNx72IrwWn +lVTY9TWm6+yOPcpV5JfyCMM6GqoRycikgNS5IQug5hl2pFVLw+UTfxo6msYaAOnp +ICUjoeDUKS0Z8+FtzGhAkWTk8GXIiPbfu7RoN1MCgcAcah6Poq2QKTR/AJ76REdf +jwM7SgKCY1aWx9Ua+nDCCOVA4qLZjOeM7yTX0wyltX2Db+MgYdQFdM6k3o8ckFvS +G2AoA6i+Ih0/EM0QhTK9oLkCxo/Q1YpJxY/wqWASkhb26pNF0B2Aoi7zxPAcQ1I0 +VrTO3h/JPHhEqKDDwuMWHO/f8fdDwtEba6YDokdSpVKygvlgXdaiz7RU7ckIDZne +n3hHuwVFqsyMbZzOtSUs2SrgDZmA9zKRA6xjEq9E/yECgcAnm7XecfSCGVNg61XN +J/sDTHCokx1QEKBm88ItPuEM7/aDp5M1+8Z+FN43rDUJ4l/BU8zxhzvISvbZshvU +h15vs1oD2yBHz356UaXrYNmbdwsn+BdeOku4zGmiLPBcg9FOk27wy+f60v/GnaUo +G9tFYbwtRnC4CZ9ZVCM9JDepPv9494lAhSPZbvYS3KW6e0sSvxXQynPuH0paIdIl +EMn0f1R8hW6ttJKHCiYCjeFP9u71ZoJe25oolpqfFHQbbocCgcAuBR4w3Qmnbscm +3b7fyy8n3AXa1gIfYjjPpR35qyp1K9thiLyj66YZIl0ACC/dt08lmI9/lguRoNIQ +AfjzZ8DByZa0caiSiFIMlgNZXdh7N3BUNNbIQk98Wd91gBlWDAiFEhrJKFPpRkmv +FySATPYcq0lcrjJb3IW2GDK4uo/jb4Nb7Cfog95W6T76XcSKHS5O8k1aI4kFPRsr +1wGZw64OkA8VXVaCaEBQ4brZ1YKB3mx4/tDqwn0I6bqkGRX3RJg= +-----END RSA PRIVATE KEY----- diff --git a/tools/test/examples/cloud_examples.json b/tools/test/examples/cloud_examples.json index 8ace07fdb3..4ce0bb2f42 100644 --- a/tools/test/examples/cloud_examples.json +++ b/tools/test/examples/cloud_examples.json @@ -11,7 +11,7 @@ "exporters": [], "compile" : true, "export": true, - "test" : false, + "test" : true, "baud_rate": 115200, "compare_log": ["mbed-os-example-for-aws/tests/aws.log"], "auto-update" : true diff --git a/tools/test/examples/examples.json b/tools/test/examples/examples.json index b5f7b31bcc..078b16fbb8 100644 --- a/tools/test/examples/examples.json +++ b/tools/test/examples/examples.json @@ -40,7 +40,7 @@ "authcrypt" ], "features" : [], - "targets" : ["K66F", "NUCLEO_F429ZI"], + "targets" : ["K64F", "NUCLEO_F429ZI"], "toolchains" : ["GCC_ARM", "ARM"], "exporters": [], "compile" : true, diff --git a/tools/test/travis-ci/doxy-spellchecker/ignore.en.pws b/tools/test/travis-ci/doxy-spellchecker/ignore.en.pws index f8061ae43b..fbc768bb80 100644 --- a/tools/test/travis-ci/doxy-spellchecker/ignore.en.pws +++ b/tools/test/travis-ci/doxy-spellchecker/ignore.en.pws @@ -121,3 +121,5 @@ instantiation instantiations KVStore _doxy_ +nothrow +conf